Semiconductor device

Abstract

To provide a semiconductor device with high field-effect mobility.SOLUTION: A semiconductor device includes: an oxide semiconductor; a first conductor and a second conductor which are separated from each other over the oxide semiconductor; a first insulation body that is arranged on the first conductor and the second conductor, and includes an opening that is overlapped with a region between the first conductor and the second conductor; a second insulator that is arranged in the opening of the first insulation body, and is in contact with an upper surface of the oxide semiconductor, a side surface of the first conductor, a side surface of the second conductor, and a side surface of the first insulation body; and a third conductor that is arranged on the second conductor in the opening of the first insulation body, and includes the region overlapped with the oxide semiconductor via the second insulation body. The oxide semiconductor includes a first layer, a second layer over the first layer, and a third layer over the second layer, in the region overlapped with the third conductor. The first layer includes gallium, the second layer includes indium oxide, the third layer includes indium, gallium, and oxygen, and a content of indium in the second layer is higher than the content of indium in the third layer.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device, a memory device, and an electronic device using an oxide semiconductor. Another aspect of the present invention relates to a method for manufacturing the semiconductor device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. Examples of the technical field of one aspect of the present invention include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device (for example, a touch sensor), an input / output device (for example, a touch panel), a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, the semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and memory devices are one aspect of semiconductor devices. A display device (such as a liquid crystal display device or a light-emitting display device), a projection device, a lighting device, an electro-optical device, a power storage device, a memory device, a semiconductor circuit, an imaging device, an electronic device, etc. may be said to have a semiconductor device.

Background Art

[0004] In recent years, the development of semiconductor devices has been advanced, and LSI (Large Scale Integration), CPU (Central Processing Unit), memory, etc. are mainly used in semiconductor devices. The CPU is an aggregate of semiconductor elements obtained by processing a semiconductor wafer into a chipped semiconductor integrated circuit (at least a transistor and a memory) and having electrodes as connection terminals.

[0005] Semiconductor circuits (IC chips) such as LSI, CPU, and memory are mounted on a circuit board, for example, a printed wiring board, and used as one of the components of various electronic devices.

[0006] In addition, a technique for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. The transistor is widely applied to electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). As a semiconductor thin film applicable to transistors, silicon-based semiconductor materials are widely known, but oxide semiconductors are attracting attention as other materials.

[0007] In addition, a transistor using an oxide semiconductor is known to have an extremely small leakage current in the non-conductive state. For example, Patent Document 1 discloses a low-power CPU and the like that apply the characteristic of a small leakage current of a transistor using an oxide semiconductor. Also, for example, Patent Document 2 discloses a memory device and the like that can retain stored content over a long period by applying the characteristic of a small leakage current of a transistor using an oxide semiconductor.

Prior Art Documents

Patent Documents

[0008]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0009] One aspect of the present invention aims to provide a semiconductor device with high field-effect mobility. Or, one aspect of the present invention aims to provide a semiconductor device having good electrical characteristics. Or, one aspect of the present invention aims to provide a highly reliable semiconductor device. Or, one aspect of the present invention aims to provide a semiconductor device capable of miniaturization or high integration. Or, one aspect of the present invention aims to provide a semiconductor device with a high operating speed. Or, one aspect of the present invention aims to provide a semiconductor device with low power consumption. Or, one aspect of the present invention aims to provide a semiconductor device with little variation in the electrical characteristics of transistors. Or, one aspect of the present invention aims to provide a novel semiconductor device. Or, one aspect of the present invention aims to provide a method for manufacturing a highly productive semiconductor device. Or, one aspect of the present invention aims to provide a method for manufacturing a novel semiconductor device. Or, one aspect of the present invention aims to provide a novel display device.

[0010] Note that the description of these problems does not prevent the existence of other problems. One aspect of the present invention does not necessarily need to solve all of these problems. It is possible to extract other problems from the description of the specification, drawings, and claims.

Means for Solving the Problems

[0011] One aspect of the present invention is an oxide semiconductor, a first conductor and a second conductor separated from each other on the oxide semiconductor, and a first insulator disposed on the first conductor and the second conductor and having an opening that overlaps a region between the first conductor and the second conductor. A second insulator disposed within the opening and in contact with the upper surface of the oxide semiconductor, the side surface of the first conductor, the side surface of the second conductor, and the side surface of the first insulator; and a third conductor disposed within the opening on the second insulator and having a region overlapping the oxide semiconductor via the second insulator. The oxide semiconductor has a first layer, a second layer on the first layer, and a third layer on the second layer in a region overlapping the third conductor. The first layer has gallium and oxygen, the second layer has indium oxide, the third layer has indium, gallium, and oxygen, and the indium content in the second layer is higher than the indium content in the third layer. It is a semiconductor device.

[0012] In the above semiconductor device, it is preferable that the lower end of the conduction band of the first layer is located closer to the vacuum level side than the lower end of the conduction band of the second layer, and the lower end of the conduction band of the third layer is located closer to the vacuum level side than the lower end of the conduction band of the second layer.

[0013] Further, in the above semiconductor device, it is preferable that the first layer has indium and the indium content in the first layer is lower than the gallium content.

[0014] Further, in the above semiconductor device, it is preferable that a part of the side surface of the first insulator coincides with or substantially coincides with the side surfaces of the first conductor and the second conductor in plan view.

[0015] Further, in the above semiconductor device, it preferably has a third insulator in contact with the upper surface of the third conductor, the upper end of the second insulator, and the upper surface of the first insulator, and a fourth insulator in contact with the upper surface of the third insulator.

[0016] Further, in the above semiconductor device, it is preferable that the third insulator has aluminum oxide.

[0017] Also, in the semiconductor device, it is preferable that the fourth insulator has silicon nitride.

[0018] Also, in the semiconductor device, the first conductor and the second conductor each have a first conductive layer and a second conductive layer on the first conductive layer, and the shortest distance between the first conductive layer of the first conductor and the first conductive layer of the second conductor is preferably smaller than the shortest distance between the second conductive layer of the first conductor and the second conductive layer of the second conductor.

[0019] Also, in the semiconductor device, it is preferable that a side surface of a part of the first insulator coincides with or substantially coincides with the side surfaces of the second conductive layer of the first conductor and the second conductive layer of the second conductor in plan view.

[0020] Also, in the semiconductor device, it is preferable that the first conductive layer of the first conductor and the first conductive layer of the second conductor have tantalum nitride.

[0021] Also, in the semiconductor device, it has a fifth insulator, the fifth insulator is disposed in the opening, and is in contact with the upper surface of the first conductive layer of the first conductor, the side surface of the second conductive layer of the first conductor, the upper surface of the first conductive layer of the second conductor, and the side surface of the second conductive layer of the second conductor, and it is preferable that the fifth insulator has an opening that overlaps with the region between the first conductive layer of the first conductor and the first conductive layer of the second conductor.

[0022] Also, in the semiconductor device, it is preferable that the fifth insulator has silicon nitride.

[0023] Also, in the semiconductor device, the second insulator has a first insulating layer, and it is preferable that the first insulating layer has an oxide containing hafnium.

[0024] Also, in the semiconductor device, it is preferable that the first insulating layer has hafnium zirconium oxide.

[0025] In the semiconductor device, it is preferable that the second insulator has a second insulating layer on the first insulating layer, and the second insulating layer contains silicon nitride.

Advantages of the Invention

[0026] According to one aspect of the present invention, a semiconductor device having a high field-effect mobility can be provided. Or, according to one aspect of the present invention, a semiconductor device having good electrical characteristics can be provided. Or, according to one aspect of the present invention, a highly reliable semiconductor device can be provided. Or, according to one aspect of the present invention, a semiconductor device capable of miniaturization or high integration can be provided. Or, according to one aspect of the present invention, a semiconductor device having a high operating speed can be provided. Or, according to one aspect of the present invention, a semiconductor device with low power consumption can be provided. Or, according to one aspect of the present invention, a semiconductor device with little variation in the electrical characteristics of transistors can be provided. Or, according to one aspect of the present invention, a novel semiconductor device can be provided. Or, according to one aspect of the present invention, a method for manufacturing a highly productive semiconductor device can be provided. Or, according to one aspect of the present invention, a method for manufacturing a novel semiconductor device can be provided. Or, according to one aspect of the present invention, a novel display device can be provided.

[0027] Note that the description of these effects does not preclude the existence of other effects. One aspect of the present invention does not necessarily have all of these effects. It is possible to extract other effects from the description of the specification, drawings, and claims.

Brief Description of the Drawings

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Best Mode for Carrying Out the Invention

[0029] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that the form and details thereof can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below.

[0030] In the configuration of the invention described below, the same reference numerals are commonly used for the same parts or parts having the same function among different drawings, and the repeated description thereof is omitted. In addition, when referring to the same function, the hatching pattern may be the same and may not be particularly labeled.

[0031] In addition, the positions, sizes, ranges, etc. of each configuration shown in the drawings may not represent the actual positions, sizes, ranges, etc. for the sake of easy understanding. For this reason, the disclosed invention is not necessarily limited to the positions, sizes, ranges, etc. disclosed in the drawings.

[0032] In this specification and the like, ordinal numbers such as "first" and "second" are used for convenience and do not limit the number of components or the order of components (for example, the process order or the stacking order). In addition, the ordinal number attached to a component in one part of this specification may not match the ordinal number attached to the same component in another part of this specification or in the claims.

[0033] Note that the terms "film" and "layer" can be interchanged with each other depending on the case or situation. For example, the term "conductive layer" can be changed to the term "conductive film". Also, the term "insulating film" can be changed to the term "insulating layer". Also, the term "oxide semiconductor film" can be changed to the term "oxide semiconductor layer". Also, the term "conductor" can be interchanged with the term "conductive layer" or the term "conductive film" depending on the case or situation. Also, the term "insulator" can be interchanged with the term "insulating layer" or the term "insulating film" depending on the case or situation. Also, the term "oxide semiconductor" can be interchanged with the term "oxide semiconductor layer" or the term "oxide semiconductor film" depending on the case or situation.

[0034] In addition, in this specification and the like, "parallel" means a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, cases of -5 degrees or more and 5 degrees or less are also included. Also, "substantially parallel" means a state in which two straight lines are arranged at an angle of -20 degrees or more and 20 degrees or less. Also, "perpendicular" means a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, cases of 85 degrees or more and 95 degrees or less are also included. Also, "substantially perpendicular" means a state in which two straight lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0035] An opening includes, for example, a groove, a slit, etc. Also, the region where an opening is formed may be referred to as an opening portion.

[0036] In addition, in the drawings used in this specification and the like, a case is shown where the side wall of the insulator at the opening of the insulator is perpendicular or substantially perpendicular to the substrate surface or the surface to be formed, but it may have a tapered shape.

[0037] In the present specification and the like, the tapered shape refers to a shape in which at least a part of the side surface of the structure is provided to be inclined with respect to the substrate surface or the surface to be formed. For example, it preferably has a region where the angle formed by the inclined side surface and the substrate surface or the surface to be formed (hereinafter sometimes referred to as the taper angle) is less than 90°. Note that the side surface of the structure and the substrate surface do not necessarily have to be completely flat, and may be a substantially planar shape having a minute curvature or a substantially planar shape having fine unevenness.

[0038] In the present specification and the like, a transistor using an oxide semiconductor or a metal oxide for a semiconductor layer, and a transistor having an oxide semiconductor or a metal oxide in a channel formation region may be referred to as an OS transistor. Further, a transistor having silicon in a channel formation region may be referred to as an Si transistor.

[0039] (Embodiment 1) In this embodiment, a semiconductor device using an oxide semiconductor and a method for manufacturing the semiconductor device will be described with reference to FIGS. 1 to 16.

[0040] <Configuration Example of Semiconductor Device> With reference to FIGS. 1 and 2, a configuration example of a semiconductor device will be described. FIGS. 1(A) to 1(D) are a plan view and cross-sectional views of a semiconductor device (transistor 200). FIG. 1(A) is a plan view of the semiconductor device. FIGS. 1(B) to 1(D) are cross-sectional views of the semiconductor device. Here, FIG. 1(B) is a cross-sectional view of the portion indicated by the dashed-dotted line A1 - A2 in FIG. 1(A), and is also a cross-sectional view in the channel length direction of transistor 200. FIG. 1(C) is a cross-sectional view of the portion indicated by the dashed-dotted line A3 - A4 in FIG. 1(A), and is also a cross-sectional view in the channel width direction of transistor 200. FIG. 1(D) is a cross-sectional view of the portion indicated by the dashed-dotted line A5 - A6 in FIG. 1(A), and is also a cross-sectional view in the channel width direction of transistor 200. Note that in the plan view of FIG. 1(A), some elements are omitted for clarity of the drawing. FIGS. 2(A) and 2(B) show enlarged cross-sectional views in the channel length direction of transistor 200.

[0041] The transistor 200 includes a conductor 205 provided to be embedded in an insulator 216, an insulator 221 on the insulator 216 and the conductor 205, an insulator 222 on the insulator 221, an insulator 224 on the insulator 222, an oxide semiconductor 230 on the insulator 224, conductors 242a and 242b on the oxide semiconductor 230, an insulator 271a on the conductor 242a, an insulator 271b on the conductor 242b, an insulator 250 on the oxide semiconductor 230, and a conductor 260 on the insulator 250.

[0042] The oxide semiconductor 230 has a region that functions as a channel formation region of the transistor 200. The conductor 260 has a region that functions as a first gate electrode (also referred to as an upper gate electrode or a top gate electrode) of the transistor 200. The insulator 250 has a region that functions as a first gate insulator of the transistor 200. The conductor 205 has a region that functions as a second gate electrode (also referred to as a lower gate electrode or a bottom gate electrode) of the transistor 200. The insulators 224, 222, and 221 each have a region that functions as a second gate insulator of the transistor 200. The conductor 242a has a region that functions as one of a source electrode or a drain electrode of the transistor 200. The conductor 242b has a region that functions as the other of a source electrode or a drain electrode of the transistor 200.

[0043] On insulators 271a and 271b, an insulator 275 is provided, and on the insulator 275, an insulator 280 is provided. Openings reaching the insulator 222 and the oxide semiconductor 230 are formed in the insulator 280 and the insulator 275, and the openings overlap a region between the conductor 242a and the conductor 242b. In a top view (which can also be called a plan view), the side surface of the insulator 280 in the opening coincides with or substantially coincides with the side surfaces of the conductor 242a and the conductor 242b. The insulator 250 and the conductor 260 are disposed inside the openings provided in the insulator 280 and the insulator 275. Further, an insulator 282 is provided in contact with the upper surface of the insulator 280, the upper end portion of the insulator 250, and the upper surface of the conductor 260. Further, an insulator 283 is provided on the insulator 282. Further, an insulator 285 is provided on the insulator 283. Further, an insulator 214 is provided under the insulator 216 and the conductor 205. Further, an insulator 212 is provided under the insulator 214. The insulator 212, the insulator 214, the insulator 280, the insulator 282, the insulator 283, and the insulator 285 function as interlayer films.

[0044] Openings reaching the conductor 242a are formed in the insulator 285, the insulator 283, the insulator 282, the insulator 280, the insulator 275, and the insulator 271a, and a conductor 240a and an insulator 241a are provided in the openings. The insulator 241a is provided in contact with the side wall of the opening, and the conductor 240a is provided inside the insulator 241a. Further, openings reaching the conductor 242b are formed in the insulator 285, the insulator 283, the insulator 282, the insulator 280, the insulator 275, and the insulator 271b, and a conductor 240b and an insulator 241b are provided in the openings. The insulator 241b is provided in contact with the side wall of the opening, and the conductor 240b is provided inside the insulator 241b. The conductor 240a and the conductor 240b function as vias connecting wiring or the like provided on the transistor 200 and the source or drain of the transistor 200.

[0045] The oxide semiconductor 230 has a channel formation region. The oxide semiconductor 230 further has a source region and a drain region. The source region and the drain region are n-type regions (low resistance regions) with a higher carrier concentration compared to the channel formation region. The oxide semiconductor 230 may have a single-layer structure or a laminated structure of two or more layers.

[0046] The crystallinity of the semiconductor material used for the oxide semiconductor 230 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, or a semiconductor having crystallinity other than a single crystal (microcrystalline semiconductor, polycrystalline semiconductor, or a semiconductor having a crystal region in part) may be used. Using a single crystal semiconductor or a semiconductor having crystallinity is preferable because deterioration of transistor characteristics can be suppressed.

[0047] The band gap of the metal oxide that functions as a semiconductor is preferably 2.0 eV or more, and more preferably 2.5 eV or more. By using a metal oxide having a large band gap for the oxide semiconductor 230, the off-current of the transistor 200 can be reduced. Since the OS transistor has a small off-current, the power consumption of the semiconductor device can be sufficiently reduced. In addition, since the frequency characteristics of the OS transistor are high, the semiconductor device can be operated at high speed.

[0048] Regarding the oxide semiconductor that can be used as the semiconductor layer of the transistor according to one aspect of the present invention, reference can be made to the description in Embodiment 2. Here, detailed description is omitted.

[0049] Note that a transistor using another semiconductor material in the channel formation region may be applied to the semiconductor device of this embodiment. Examples of the other semiconductor material include a semiconductor made of a single element or a compound semiconductor.

[0050] Examples of single-element semiconductors that can be used as semiconductor materials include silicon and germanium. Examples of silicon that can be used as a semiconductor material include single-crystalline silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low-temperature polycrystalline silicon (LTPS).

[0051] Examples of compound semiconductors that can be used as semiconductor materials include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. Boron nitride that can be used in a semiconductor layer preferably includes an amorphous structure. Boron arsenide that can be used in a semiconductor layer preferably includes a crystal having a cubic crystal structure. Other examples of compound semiconductors include organic semiconductors and nitride semiconductors. Note that the aforementioned oxide semiconductors are also a type of compound semiconductor. Note that these semiconductor materials may contain impurities as dopants.

[0052] Here, the oxide semiconductor 230 used in the semiconductor device preferably contains indium oxide. For example, as the oxide semiconductor 230, indium oxide, indium gallium oxide, indium zinc oxide, indium gallium zinc oxide, indium gallium tin zinc oxide, or the like can be used. Further, the oxide semiconductor 230 can have a stacked structure. For example, the oxide semiconductor 230 can have a stacked structure of indium oxide and indium gallium zinc oxide on indium oxide. Further, as shown in FIG. 2(A), the oxide semiconductor 230 can have a configuration including an oxide semiconductor 230a on an insulator 224, an oxide semiconductor 230b on the oxide semiconductor 230a, and an oxide semiconductor 230c on the oxide semiconductor 230b. For example, indium oxide can be used for the oxide semiconductor 230b, and indium gallium zinc oxide can be used for the oxide semiconductor 230a and the oxide semiconductor 230c. As described above, by configuring the oxide semiconductor 230 to contain indium oxide, a semiconductor device having a high field-effect mobility can be provided. Further, a semiconductor device having at least one of good electrical characteristics, frequency characteristics, and reliability can be provided. For details of the configuration of the oxide semiconductor 230, reference can be made to the description of Embodiment 2.

[0053] In the oxide semiconductor 230, a channel formation region and a source region and a drain region provided so as to sandwich the channel formation region are formed in the transistor 200. At least a part of the channel formation region overlaps with the conductor 260. The source region overlaps with the conductor 242a, and the drain region overlaps with the conductor 242b. Note that the source region and the drain region can be interchanged with each other.

[0054] Since the channel formation region has less oxygen deficiency or a lower impurity concentration than the source region and the drain region, it is a high-resistance region with a low carrier concentration. Therefore, the channel formation region can be said to be of i-type (intrinsic) or substantially i-type.

[0055] In addition, the source region and the drain region are low-resistance regions with a high carrier concentration because they have a large amount of oxygen deficiency or a high impurity concentration such as hydrogen, nitrogen, and metal elements. That is, the source region and the drain region are n-type regions (low-resistance regions) with a higher carrier concentration than the channel formation region.

[0056] Note that the carrier concentration in the channel formation region is 1×10 18 cm -3 or less, 1×10 17 cm -3 or less, 1×10 16 cm -3 or less, 1×10 15 cm -3 or less, 1×10 14 cm -3 or less, 1×10 13 cm -3 or less, 1×10 12 cm -3 or less, 1×10 11 cm -3 or less, or 1×10 10 cm -3 or less, which is preferable. In addition, the lower limit value of the carrier concentration in the channel formation region is not particularly limited. For example, it can be 1×10 -9 cm -3 .

[0057] Note that when reducing the carrier concentration of the oxide semiconductor 230, the impurity concentration in the oxide semiconductor 230 is reduced and the density of defect levels is reduced. In this specification and the like, a low impurity concentration and a low density of defect levels are referred to as high-purity intrinsic or substantially high-purity intrinsic. Note that an oxide semiconductor (or metal oxide) with a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor (or metal oxide).

[0058] In order to stabilize the electrical characteristics of the transistor 200, it is effective to reduce the impurity concentration in the channel formation region in the oxide semiconductor 230. Further, in order to reduce the impurity concentration of the oxide semiconductor 230, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like. Note that the impurities in the oxide semiconductor 230 refer to, for example, components other than the main components constituting the oxide semiconductor 230. For example, an element with a concentration of less than 0.1 atomic% can be regarded as an impurity.

[0059] In addition, in the oxide semiconductor 230, it may be difficult to clearly detect the boundary between each region. The concentration of metal elements, as well as impurity elements such as hydrogen and nitrogen, detected within each region may not be limited to a stepwise change from region to region, but may also change continuously within each region. That is, the concentration of metal elements, as well as impurity elements such as hydrogen and nitrogen, may decrease in a region closer to the channel formation region.

[0060] In a transistor using an oxide semiconductor, if impurities and oxygen deficiencies are present in the region where the channel is formed in the oxide semiconductor, the electrical characteristics are likely to fluctuate and the reliability may deteriorate. In addition, hydrogen near the oxygen deficiency may form a defect in which hydrogen enters the oxygen deficiency (hereinafter sometimes referred to as V O H), and may generate electrons serving as carriers. For this reason, if the channel formation region in the oxide semiconductor contains an oxygen deficiency, the transistor is likely to have a normally-on characteristic (a characteristic in which a channel exists even when no voltage is applied to the gate electrode and a current flows through the transistor). Therefore, in the channel formation region in the oxide semiconductor, it is preferable that impurities, oxygen deficiencies, and V O H are reduced as much as possible. In other words, the channel formation region in the oxide semiconductor preferably has a reduced carrier concentration and is of an i-type (intrinsic) or substantially i-type.

[0061] On the other hand, an insulator containing oxygen that desorbs by heating (hereinafter sometimes referred to as excess oxygen) is provided near the oxide semiconductor, and by performing heat treatment, oxygen is supplied from the insulator to the oxide semiconductor, and oxygen deficiency and V O H can be reduced. However, if an excessive amount of oxygen is supplied to the source region or the drain region, it may cause a decrease in the on-current of the transistor 200 or a decrease in the field-effect mobility. Furthermore, variations in the amount of oxygen supplied to the source region or the drain region within the substrate surface will result in variations in the characteristics of the semiconductor device having the transistor. Also, if the amount of oxygen supplied from the insulator to the oxide semiconductor becomes excessively large, it may adversely affect the electrical characteristics and reliability of the transistor. Furthermore, there is also a risk that oxygen diffuses into conductors such as the gate electrode, the source electrode, and the drain electrode, oxidizes the conductor, and impairs the conductivity.

[0062] First, an insulator having a barrier property against hydrogen is formed near the transistor 200, and it is preferable to reduce V O H in the channel formation region of the oxide semiconductor 230 and in its vicinity.

[0063] At least one of insulator 212, insulator 214, insulator 221, insulator 222, insulator 275, insulator 282, and insulator 283 preferably functions as a barrier insulator against hydrogen. Also, at least one of insulator 212, insulator 214, insulator 221, insulator 222, insulator 275, insulator 282, and insulator 283 preferably functions as a barrier insulator against impurities. Also, at least one of insulator 212, insulator 214, insulator 221, insulator 222, insulator 275, insulator 282, and insulator 283 preferably functions as a barrier insulator against oxygen. Note that it is not always necessary to provide all of insulator 212, insulator 214, insulator 221, insulator 222, insulator 275, insulator 282, and insulator 283. If the barrier properties against hydrogen, impurities, oxygen, etc. are sufficient, they can be appropriately selected and formed from among insulator 212, insulator 214, insulator 221, insulator 222, insulator 275, insulator 282, and insulator 283. For example, a configuration can be adopted in which insulator 216 and conductor 205 are in contact with the upper surface of insulator 212 without providing insulator 214.

[0064] In this specification and the like, a barrier insulator refers to an insulator having barrier properties. In this specification and the like, having barrier properties means having a property that the corresponding substance is difficult to diffuse (also referred to as a property that the corresponding substance is difficult to permeate, a property that the permeability of the corresponding substance is low, or a function of suppressing the diffusion of the corresponding substance). Or it means having a function of capturing or fixing (also referred to as gettering) the corresponding substance inside the insulator. Note that hydrogen in the case of being described as the corresponding substance refers to at least one of, for example, hydrogen atoms, hydrogen molecules, and substances bonded to hydrogen such as water molecules and OH - and the like. Also, impurities in the case of being described as the corresponding substance refer to impurities in the channel formation region or semiconductor layer unless otherwise specified, and refer to at least one of, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as N2O, NO, NO2), and copper atoms. Also, oxygen in the case of being described as the corresponding substance refers to at least one of, for example, oxygen atoms and oxygen molecules.

[0065] As the insulator having a function of suppressing hydrogen diffusion, for example, it is preferable to use silicon nitride or silicon oxynitride. Also, for example, aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium (hafnium aluminate), oxides containing hafnium and zirconium (hafnium zirconium oxide), gallium oxide, indium gallium zinc oxide, etc. may be used in some cases.

[0066] It is preferable to use an insulator having a function of suppressing hydrogen diffusion for insulator 212, insulator 221, insulator 275, and insulator 283. For example, silicon nitride with higher hydrogen barrier properties may be used for insulator 212, insulator 221, insulator 275, and insulator 283.

[0067] A part of the insulator having a function of suppressing hydrogen diffusion has a function of capturing or fixing hydrogen. As the insulator having a function of capturing or fixing hydrogen, for example, it is preferable to use metal oxides such as oxides containing hafnium, oxides containing aluminum, oxides containing aluminum and hafnium (hafnium aluminate), oxides containing hafnium and zirconium (hafnium zirconium oxide), or magnesium oxide. The insulator having a function of capturing or fixing hydrogen preferably has an amorphous structure. In such a metal oxide having an amorphous structure, oxygen atoms have dangling bonds, and there are cases where hydrogen can be captured or fixed by the dangling bonds. That is, it can be said that a metal oxide having an amorphous structure has a high ability to capture or fix hydrogen. By adding silicon to the above metal oxide, crystallization can be suppressed and it can be made more likely to be amorphous. Therefore, it is preferable to use a metal oxide (for example, hafnium silicate, aluminum silicate, etc.) obtained by adding silicon to the above metal oxide.

[0068] It is preferable to use insulators having a function of capturing or fixing hydrogen for the insulator 214, the insulator 222, and the insulator 282. For example, aluminum oxide may be used for the insulator 214 and the insulator 282. Further, for example, it is preferable to use hafnium oxide, which is a high dielectric constant (high-k) material, for the insulator 222 that functions as the second gate insulator.

[0069] In addition, the inorganic insulators cited as insulators having a function of suppressing hydrogen diffusion and insulators having a function of capturing or fixing hydrogen also have a barrier property against oxygen.

[0070] As shown in FIG. 2(A), it is preferable to provide an insulator 212 having a function of suppressing hydrogen diffusion and an insulator 214 having a function of capturing or fixing hydrogen under the transistor 200. By providing the insulator 212 under the transistor 200, it is possible to suppress the diffusion of hydrogen from the lower layer of the transistor 200. Further, by providing the insulator 214 on the insulator 212, the hydrogen contained in the insulator 216 or the like can be captured or fixed by the insulator 214. Thereby, the hydrogen concentration in the oxide semiconductor 230 and its vicinity can be reduced.

[0071] Also, as shown in FIG. 2(A), it is preferable to provide an insulator 221 having a function of suppressing hydrogen diffusion and an insulator 222 having a function of capturing or fixing hydrogen below the transistor 200. By providing the insulator 221 below the transistor 200, it is possible to suppress the diffusion of hydrogen from the lower layer of the transistor 200. Further, by providing the insulator 222 on the insulator 221, the hydrogen contained in the insulator 224 or the like can be captured or fixed by the insulator 222. Thereby, the hydrogen concentration in the oxide semiconductor 230 and its vicinity can be reduced.

[0072] Further, as shown in FIG. 2(A), it is preferable to provide an insulator 275 so as to cover the oxide semiconductor 230, the conductor 242a, the conductor 242b, and the like. By providing the insulator 275 in this manner, it is possible to suppress the diffusion of hydrogen from the insulator 280 to the oxide semiconductor 230, the conductor 242a, the conductor 242b, and the like.

[0073] Further, as shown in FIG. 2(A), it is preferable to provide an insulator 282 having a function of capturing or fixing hydrogen and an insulator 283 having a function of suppressing the diffusion of hydrogen on the transistor 200. By providing the insulator 283 on the transistor 200, it is possible to suppress the diffusion of hydrogen from the upper layer of the transistor 200. Further, by providing the insulator 282 under the insulator 283, it is possible to capture or fix the hydrogen contained in the insulator 280 and the like by the insulator 282. Thereby, the hydrogen concentration in the oxide semiconductor 230 and its vicinity can be reduced.

[0074] In this way, by surrounding the upper and lower sides of the transistor 200 with a barrier insulator against hydrogen, the diffusion of hydrogen into the oxide semiconductor is reduced, and V O H can be reduced. Thereby, the electrical characteristics and reliability of the transistor 200 can be improved.

[0075] Furthermore, it is preferable to include oxygen that desorbs by heating in the insulator 280. By supplying the oxygen to the oxide semiconductor 230 through the insulator 250 by heat treatment, oxygen deficiency in the channel formation region can be reduced.

[0076] Further, as shown in FIG. 2(A), the insulator 282 may have a laminated structure of an insulator 282a and an insulator 282b on the insulator 282a.

[0077] In this case, by forming the insulator 282b by sputtering in an atmosphere containing oxygen gas, oxygen can be added to the insulator 280. At this time, with the insulator 282a already formed, by forming the insulator 282b, oxygen is added through the insulator 282a, so the amount of oxygen added to the insulator 280 can be controlled. If the film thickness of the insulator 282a is large, the addition of the above-mentioned oxygen is likely to be inhibited, and the amount of oxygen injected into the insulator 280 decreases. If the film thickness of the insulator 282a is small, the addition of the above-mentioned oxygen is less likely to be inhibited, and the amount of oxygen injected into the insulator 280 increases. For example, by setting the film thickness of the insulator 282a to be 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less, a suitable amount of oxygen can be supplied to the insulator 280.

[0078] Also, in order to prevent oxygen from being added to the insulator 280 during the film formation of the insulator 282a, it is preferable to form the insulator 282a using the atomic layer deposition (ALD) method. Further, in order to make the film thickness of the insulator 282a thin as described above, it is preferable to form the film using the ALD method. The ALD method includes a thermal ALD method that performs the reaction of the precursor and the reactant only with thermal energy, a PEALD (Plasma Enhanced ALD) method that uses a plasma-excited reactant, and the like.

[0079] Some of the precursors used in the ALD method contain carbon or the like. Therefore, the film formed by the ALD method may contain more impurities such as carbon compared to the film formed by other film formation methods. Thus, the carbon concentration of the insulator 282a may be higher than that of the insulator 282b. The quantification of impurities can be performed using secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), or Auger electron spectroscopy (AES).

[0080] For example, when both the insulator 282a and the insulator 282b have aluminum oxide, the carbon concentration of the insulator 282a may be higher than that of the insulator 282b. At this time, the carbon concentration of the insulator 282a is 1×10 18 atoms / cm 3 or more and preferably 1×10 21 atoms / cm 3 or less in SIMS analysis. The insulator 282a may have a region where the carbon concentration is 1×10 19 atoms / cm 3 or more and preferably 1×10 21 atoms / cm 3 or less. Also, the carbon concentration of the insulator 282b is preferably the detection lower limit or more and 1×10 20 atoms / cm 3 or less in SIMS analysis. The insulator 282b may have a region where the carbon concentration is 4.46×10 17 atoms / cm 3 or more and preferably 1×10 19 atoms / cm 3 or less.

[0081] As described above, by performing a heat treatment on the insulator 280 in a state containing oxygen that desorbs by heating, an appropriate amount of oxygen can be supplied to the oxide semiconductor 230 via the insulator 250. In the heat treatment, since the insulators 282 and 283 having a barrier property against oxygen are formed on the insulator 280, it is possible to prevent the oxygen contained in the insulator 280 from being excessively diffused from the insulator 280. Further, since the insulator 275 having a barrier property against oxygen is formed between the insulator 280 and the oxide semiconductor 230, the conductor 242a, and the conductor 242b, it is possible to prevent the oxygen contained in the insulator 280 from being excessively diffused from the insulator 280. Further, by performing the heat treatment in a state where openings are formed in a part of the insulator 280, the insulator 282, and the insulator 283, a part of the oxygen contained in the insulator 280 can be diffused outward, and the amount of oxygen supplied from the insulator 280 to the oxide semiconductor 230 can also be adjusted.

[0082] Here, the insulator 250 preferably has a configuration that allows oxygen to diffuse from the insulator 280 to the oxide semiconductor 230 and suppresses the oxidation of the conductor 242a, the conductor 242b, and the conductor 260.

[0083] As shown in FIGS. 1(B) and 1(C), the insulator 250 is disposed in the openings formed in the insulator 280 and the insulator 275. In the openings, the insulator 250 is formed in contact with the upper surface of the insulator 222, the side surfaces of the insulator 224, the side surfaces and the upper surface of the oxide semiconductor 230, the side surfaces of the conductor 242a, the side surfaces of the conductor 242b, the side surfaces of the insulator 271a, the side surfaces of the insulator 271b, the side surfaces of the insulator 275, and the side surfaces of the insulator 280. Further, as shown in FIG. 2(A), when the oxide semiconductor 230 includes the oxide semiconductors 230a to 230c, the insulator 250 is in contact with the side surfaces of the oxide semiconductors 230a and 230b and the upper surface and the side surfaces of the oxide semiconductor 230c. Here, it is preferable to increase the crystallinity of the oxide semiconductor 230c shown in FIG. 2(A). Since the oxide semiconductor 230c has a large contact area with the insulator 250, the carrier mobility can be increased when the transistor 200 is in the on state.

[0084] Here, as shown in FIG. 2(A), the insulator 250 preferably has a stacked structure including an insulator 250a in contact with the oxide semiconductor 230, an insulator 250b on the insulator 250a, and an insulator 250c on the insulator 250b.

[0085] The insulator 250b is preferably made of silicon oxide, silicon oxynitride, or the like with a high breakdown voltage. Further, in order to improve the breakdown voltage, the thickness of the insulator 250b may be made larger than that of the insulator 250a. By using the oxide insulator as described above, oxygen can be diffused in the insulator 250b by performing a high-temperature heat treatment. Therefore, by performing the heat treatment, oxygen contained in the insulator 280 can be supplied to the oxide semiconductor 230 through the insulator 250b. In this specification and the like, oxynitride refers to a material having a higher oxygen content than nitrogen in its composition, and oxynitride refers to a material having a higher nitrogen content than oxygen in its composition. For example, when silicon oxynitride is described, it refers to a material having a higher oxygen content than nitrogen in its composition, and when silicon oxynitride is described, it indicates a material having a higher nitrogen content than oxygen in its composition.

[0086] In order to suppress the oxidation of the conductor 242a, the conductor 242b, and the conductor 260, it is preferable to provide an oxygen barrier insulator in the vicinity of each of the conductor 242a, the conductor 242b, and the conductor 260. For example, it is preferable to provide an oxygen barrier insulator on the insulators 250a and 250c.

[0087] The insulator 250a preferably has a barrier property against oxygen. The insulator 250a is preferably at least less permeable to oxygen than the insulator 250b. The insulator 250a has regions in contact with the side surfaces of the conductor 242a and the conductor 242b. Since the insulator 250a has a barrier property against oxygen, oxidation of the side surfaces of the conductor 242a and the conductor 242b and formation of an oxide film on the side surfaces can be suppressed. Thereby, a decrease in the on-current or a decrease in the field-effect mobility of the transistor 200 can be suppressed. Further, with such a configuration, the amount of oxygen in the insulator 250b absorbed by the conductor 242a and the conductor 242b can be reduced. Therefore, an appropriate amount of oxygen can be supplied from the insulator 250b to the oxide semiconductor 230, and oxygen deficiency in the channel formation region of the oxide semiconductor 230 can be reduced.

[0088] Also, by providing the insulator 250a between the insulator 280 and the insulator 250b, and between the insulator 250b and the oxide semiconductor 230, it is possible to suppress the excessive supply of oxygen from the insulator 280 to the oxide semiconductor 230, and supply an appropriate amount of oxygen to the oxide semiconductor 230. Therefore, since the amount of oxygen in the channel formation region of the oxide semiconductor 230 and its vicinity can be controlled to an appropriate amount, excessive normal-off of the transistor 200 can be prevented, and the reliability can be improved. Further, it is possible to suppress the excessive oxidation of the source region and the drain region, which may cause a decrease in the on-current of the transistor 200 or a decrease in the field-effect mobility.

[0089] Therefore, it is preferable that the insulator 250a has a film thickness that does not excessively hinder the diffusion of oxygen from the insulator 280 to the insulator 250b and the diffusion of oxygen from the insulator 250b to the oxide semiconductor 230. For example, the film thickness of the insulator 250a is preferably 0.1 nm or more and 5.0 nm or less, more preferably 0.5 nm or more and 5.0 nm or less, still more preferably 0.5 nm or more and less than 3.0 nm, and even more preferably 0.5 nm or more and 2.0 nm or less.

[0090] As described above, it is preferable to moderately perform the diffusion of oxygen from the insulator 280 to the insulator 250b and the diffusion of oxygen from the insulator 250b to the oxide semiconductor 230, and to suppress the diffusion of oxygen from the insulator 250b to the conductors 242a and 242b as much as possible. Here, in the semiconductor device according to the present embodiment, the contact areas of the insulator 250a with the conductor 242a and the insulator 250a with the conductor 242b are much smaller than the contact area of the insulator 250a with the oxide semiconductor 230. That is, it is presumed that the amount of oxygen diffusing from the insulator 250b to the conductors 242a and 242b through the insulator 250a is less than the amount of oxygen diffusing from the insulator 250b to the oxide semiconductor 230 through the insulator 250a. Therefore, by controlling the amount of oxygen contained in the insulator 280 so that an appropriate amount of oxygen is supplied from the insulator 280 to the insulator 250b and the oxide semiconductor 230, the oxidation of the conductors 242a and 242b can be reduced.

[0091] The insulator 250a in contact with the channel formation region in the oxide semiconductor 230 preferably has a function of capturing hydrogen or fixing hydrogen. Thereby, the hydrogen concentration in the channel formation region of the oxide semiconductor 230 can be reduced. Thus, V O H in the channel formation region can be reduced, and the channel formation region can be made into an i-type or substantially an i-type.

[0092] Also, it is preferable to use a high-k (high dielectric constant) material for the insulator 250a. As an example of the high-k material, there is an oxide containing one or both of aluminum and hafnium. By using a high-k material as the insulator 250a, it becomes possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. Also, it becomes possible to thin the equivalent oxide film thickness (EOT) of the insulator functioning as the gate insulator.

[0093] From the above, as the insulator 250a, it is preferable to use an oxide containing one or both of aluminum and hafnium, and it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium. Aluminum oxide can relatively easily form an amorphous film using the ALD method, so it is even more preferable to use aluminum oxide having an amorphous structure. In the present embodiment, an aluminum oxide film is used as the insulator 250a. Aluminum oxide has a function of capturing or fixing hydrogen and has a barrier property against oxygen, so it can be suitably used as the insulator 250a.

[0094] The insulator 250c preferably also has a barrier property against oxygen. The insulator 250c is provided between the channel formation region of the oxide semiconductor 230 and the conductor 260, and between the insulator 280 and the conductor 260. With such a configuration, it is possible to suppress oxygen contained in the channel formation region of the oxide semiconductor 230 from diffusing into the conductor 260 and the formation of oxygen vacancies in the channel formation region of the oxide semiconductor 230. Further, it is possible to suppress oxygen contained in the oxide semiconductor 230 and oxygen contained in the insulator 280 from diffusing into the conductor 260 and the oxidation of the conductor 260. The insulator 250c preferably has at least a lower oxygen permeability than the insulator 250b. Further, the insulator 250c preferably has a function of suppressing the diffusion of hydrogen. Thereby, impurities such as hydrogen contained in the conductor 260 can be prevented from diffusing into the oxide semiconductor 230. For example, it is preferable to use a silicon nitride film as the insulator 250c.

[0095] Also, as shown in FIG. 2(B), it is preferable to adopt a structure in which an insulator 250d is provided on the insulator 250b. In this case, as the insulator 250d, an insulator having a function of capturing or fixing hydrogen, which can be used for the insulator 250a, can be provided. For example, it is preferable to use an oxide containing hafnium as the insulator 250d. Examples of the oxide containing hafnium include hafnium oxide, hafnium aluminate, hafnium silicate, hafnium zirconium oxide, hafnium zirconium oxide containing yttrium, and the like. Also, a hafnium zirconium oxide containing a lanthanoid such as lanthanum can be used as the insulator 250d. Here, by providing the insulator 250d between the insulator 250c and the insulator 250b, hydrogen contained in the insulator 250b and the like can be more effectively captured and fixed. Under the insulator 250c having a function of suppressing the diffusion of hydrogen, a channel formation region of the oxide semiconductor 230, and the insulators 250a and 250d having a function of capturing and fixing hydrogen are provided. In a region where the diffusion of hydrogen from above is blocked by the insulator 250c, hydrogen contained in the channel formation region of the oxide semiconductor 230 and the like can be captured or fixed by the insulators 250a and 250d. As a result, the hydrogen concentration in the oxide semiconductor 230 can be reduced, so that a negative shift in the initial characteristics of the transistor 200 can be suppressed, and a normally-off characteristic can be achieved. Also, negative drift degradation in the +GBT (Gate Bias-Temperature) stress test can be suppressed.

[0096] Note that, instead of providing the insulator 250c, a configuration may be adopted in which the insulators 250a, 250b, and 250d are provided. In this case, it is preferable to provide an insulator (for example, silicon nitride or the like) having a function of suppressing hydrogen diffusion on the insulator 283 on the insulator 250. By adopting such a configuration, the oxide semiconductor 230, and the insulators 250a and 250d having a function of capturing or fixing hydrogen are formed in a region covered with silicon nitride having high hydrogen barrier properties. Therefore, hydrogen contained in the channel formation region or the like of the oxide semiconductor 230 can be captured or fixed by the insulators 250a and 250d.

[0097] By adopting the above-described configuration, the channel formation region can be made i-type or substantially i-type, and the source region and the drain region can be made n-type, thereby providing a semiconductor device having good electrical characteristics. Further, by adopting the above configuration, even when the semiconductor device is miniaturized or highly integrated, it can have good electrical characteristics. Further, by miniaturizing the transistor 200, the frequency characteristics can be improved. Specifically, the cut-off frequency can be improved.

[0098] Further, the metal oxide containing hafnium used for the insulator 250d preferably functions as a high-k material. By adopting such a configuration, it becomes possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. Further, it becomes possible to thin the equivalent oxide film thickness (EOT) of the insulator functioning as the gate insulator.

[0099] In addition, the insulator 250d preferably has ferroelectricity. For example, for the insulator 250d, hafnium zirconium oxide having ferroelectricity, hafnium zirconium oxide containing yttrium, or the like can be used. Further, the insulator 250d may have a structure in which a layer of hafnium zirconium oxide is laminated on a layer of hafnium zirconium oxide containing yttrium. When a ferroelectric is used for the insulator 250d, the insulator 250d does not necessarily have to have a function of capturing or fixing hydrogen. For example, a material capable of having ferroelectricity described in Embodiment 4 can be used for the insulator 250d.

[0100] Thus, by using a ferroelectric for the insulator 250d, the transistor 200 can function as a FeFET (Ferroelectric Field Effect Transistor). A FeFET functions as a memory element alone. Therefore, compared with a DRAM (Dynamic Random Access Memory)-type memory element having a transistor and a capacitor element, the structure of the memory element can be reduced. Therefore, miniaturization and high integration of a memory device including the transistor 200 can be achieved. In addition, the productivity of a memory device including the transistor 200 can be improved.

[0101] Insulators 250a to 250d function as part of the first gate insulator. Insulators 250a to 250d are provided in an opening formed in insulator 280 or the like together with conductor 260. In order to miniaturize transistor 200, it is preferable that the film thicknesses of insulators 250a, 250c, and 250d are each thin. The film thicknesses of insulators 250a, 250c, and 250d are each preferably 0.1 nm or more and 20 nm or less, more preferably 0.1 nm or more and 10 nm or less, still more preferably 0.5 nm or more and 5.0 nm or less, even more preferably 1.0 nm or more and less than 5.0 nm, and still even more preferably 1.0 nm or more and 3.0 nm or less. For example, aluminum oxide with a film thickness of 1 nm can be used for insulator 250a, silicon oxide with a film thickness of 2 nm can be used for insulator 250b, hafnium oxide, hafnium zirconium oxide, or hafnium zirconium oxide containing yttrium with a film thickness of 2 nm can be used for insulator 250d, and silicon nitride with a film thickness of 1 nm can be used for insulator 250c. Note that insulators 250a, 250c, and 250d only need to each have a region with a film thickness in the above range at least in part.

[0102] In order to make the film thicknesses of insulators 250a, 250c, and 250d as thin as described above, it is preferable to form a film using the ALD method. Further, in order to form insulators 250a to 250d with good coverage in the opening of insulator 280 or the like, it is preferable to form a film using the ALD method.

[0103] In the above description, the case where the insulator 250 has a three-layer structure of the insulators 250a to 250c or a four-layer structure of the insulators 250a to 250d has been described. However, the present invention is not limited to this. The insulator 250 can have a single-layer structure, a two-layer structure, or a laminated structure of five or more layers. Further, the insulator 250 can be configured to have at least one of the insulators 250a to 250d. For example, the insulator 250 can be a single-layer structure of the insulator 250c. In this case, the insulator 250 can also be formed of a single-layer hafnium zirconium oxide. By configuring the insulator 250 with one, two, or three layers out of the insulators 250a to 250d, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0104] When the insulator 250 has a four-layer structure or a five-layer structure, for example, it can have a laminated structure as shown in FIGS. 3(A) to 3(E). Here, FIGS. 3(A) to 3(E) are enlarged views corresponding to the region A shown in FIG. 2(B).

[0105] In FIG. 3(A), an example is shown in which the insulator 250 has a stacked structure including an insulator 250a on the oxide semiconductor 230, an insulator 250d on the insulator 250a, an insulator 250b on the insulator 250d, and an insulator 250c on the insulator 250b. That is, the insulator 250 shown in FIG. 3(A) is obtained by swapping the positions of the insulator 250b and the insulator 250d in the insulator 250 shown in FIG. 2(B). For example, aluminum oxide with a film thickness of 1 nm can be used for the insulator 250a, hafnium zirconium oxide with a film thickness of 2 nm or hafnium zirconium oxide containing yttrium can be used for the insulator 250d, silicon oxide with a film thickness of 2 nm can be used for the insulator 250b, and silicon nitride with a film thickness of 1 nm can be used for the insulator 250c. Further, the insulator 250d may have a structure in which a layer of hafnium zirconium oxide is stacked on a layer of hafnium zirconium oxide containing yttrium. However, the present invention is not limited to the above, and the insulators 250a to 250d can be appropriately selected from the above-described insulating materials, and the film thicknesses of the insulators 250a to 250d can also be appropriately selected. By stacking the insulators 250a to 250d as shown in FIG. 3(A), the insulators 250a and 250d having a function of capturing or fixing hydrogen are provided adjacent to each other, so that hydrogen can be captured and fixed more effectively.

[0106] Also, as shown in FIG. 3(B), the positions of the insulator 250c and the insulator 250b can be swapped. In this case, the insulator 250 has a stacked structure including an insulator 250a on the oxide semiconductor 230, an insulator 250d on the insulator 250a, an insulator 250c on the insulator 250d, and an insulator 250b on the insulator 250c.

[0107] In addition, in FIG. 3(A), the insulator 250c can be configured to be in contact with the upper surface and the lower surface of the insulator 250b, respectively. In this case, as shown in FIG. 3(C), the insulator 250 has a stacked structure including an insulator 250a on the oxide semiconductor 230, an insulator 250d on the insulator 250a, an insulator 250c1 on the insulator 250d, an insulator 250b on the insulator 250c1, and an insulator 250c2 on the insulator 250b. Here, for the insulator 250c1 and the insulator 250c2, an insulator that can be used for the above-described insulator 250c may be used. For example, silicon nitride with a film thickness of 1 nm can be used for each of the insulator 250c1 and the insulator 250c2.

[0108] In FIG. 3(D), an example is shown in which the insulator 250 has a stacked structure including an insulator 250a on the oxide semiconductor 230, an insulator 250b on the insulator 250a, an insulator 250d1 on the insulator 250b, an insulator 250c on the insulator 250d1, and an insulator 250d2 on the insulator 250c. That is, the insulator 250 shown in FIG. 3(D) is configured such that, in the insulator 250 shown in FIG. 2(B), insulators that can be used for the insulator 250d are provided in contact with the upper surface and the lower surface of the insulator 250c. Here, for the insulator 250d1, an insulator having a function of capturing or fixing hydrogen (for example, hafnium oxide) can be used, and for the insulator 250d2, an insulator having ferroelectricity (for example, hafnium zirconium oxide or hafnium zirconium oxide containing yttrium) can be used. Further, the insulator 250d2 may have a structure in which a layer of hafnium zirconium oxide is stacked on a layer of hafnium zirconium oxide containing yttrium. By using a ferroelectric for the insulator 250d2 in such a structure, the transistor 200 can function as a FeFET. Furthermore, since hydrogen can be captured or fixed by the insulator 250d1, the electrical characteristics and reliability of the transistor 200 can be improved.

[0109] Further, when forming the insulator 250d2 and using a ferroelectric material such as hafnium zirconium oxide for the insulator 250d2, as shown in FIG. 3(E), a configuration can be adopted in which the conductor 252 is provided in contact with the lower surface of the insulator 250d2. It is preferable to use a material that easily polarizes the insulator 250d2 for the conductor 252. For example, it is preferable to use titanium nitride. Also, in this case, it is preferable to use titanium nitride for the portion (for example, the conductor 260a) of the insulator 250d2 in contact with the lower part of the conductor 260. By adopting such a configuration, the insulator 250d2 can be used as a ferroelectric body, and the transistor 200 can function as a FeFET.

[0110] In the transistor 200, the conductor 205 is arranged to overlap with the oxide semiconductor 230 and the conductor 260. The conductive material described in the item of <<conductor>> can be used for the conductor 205. Here, it is preferable that the conductor 205 is provided so as to be embedded in the opening formed in the insulator 216. Also, as shown in FIGS. 1(A) and 1(C), it is preferable that the conductor 205 extends in the channel width direction. By adopting such a configuration, when a plurality of transistors are provided, the conductor 205 functions as a wiring.

[0111] As shown in FIG. 2(A), the conductor 205 preferably has a conductor 205a and a conductor 205b. The conductor 205a is provided in contact with the bottom surface and the side wall of the opening. The conductor 205b is provided so as to fill the recess of the conductor 205a formed along the opening. Here, the height of the upper surface of the conductor 205 coincides with or substantially coincides with the height of the upper surface of the insulator 216.

[0112] Here, it is preferable that the conductor 205a has a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as N2O, NO, NO2), and copper atoms. Or, it is preferable to have a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules).

[0113] By using a conductive material having a function of reducing the diffusion of hydrogen for the conductor 205a, impurities such as hydrogen contained in the conductor 205b can be prevented from diffusing into the oxide semiconductor 230 through the insulator 216 or the like. Further, by using a conductive material having a function of suppressing the diffusion of oxygen for the conductor 205a, it is possible to suppress the oxidation of the conductor 205b and a decrease in the conductivity. Examples of the conductive material having a function of suppressing the diffusion of oxygen include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The conductor 205a can have a single-layer structure or a laminated structure of the above conductive material. For example, the conductor 205a preferably has titanium nitride.

[0114] In addition, for the conductor 205b, it is preferable to use a conductive material mainly composed of tungsten, copper, or aluminum. For example, the conductor 205b preferably has tungsten.

[0115] The conductor 205 can function as a second gate electrode. In that case, by changing the potential applied to the conductor 205 independently without linking it to the potential applied to the conductor 260, the threshold voltage (Vth) of the transistor 200 can be controlled. In particular, by applying a negative potential to the conductor 205, it is possible to increase the Vth of the transistor 200 and reduce the off-current. Therefore, applying a negative potential to the conductor 205 can make the drain current smaller when the potential applied to the conductor 260 is 0V than when no negative potential is applied.

[0116] In addition, the electrical resistivity of the conductor 205 is designed in consideration of the potential applied to the conductor 205, and the film thickness of the conductor 205 is set according to the electrical resistivity. Also, the film thickness of the insulator 216 is made substantially the same as that of the conductor 205. Here, it is preferable to reduce the film thicknesses of the conductor 205 and the insulator 216 within the range allowed by the design of the conductor 205. By reducing the film thickness of the insulator 216, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, so that the diffusion of such impurities into the oxide semiconductor 230 can be suppressed.

[0117] In FIG. 2(A), the laminated structure of the conductor 205a and the conductor 205b is shown. However, the present invention is not limited to this, and the conductor 205 may have a single-layer structure or a laminated structure of three or more layers. For example, the conductor 205a may have a two-layer structure of tantalum nitride and titanium nitride on the tantalum nitride, and a conductor 205b having tungsten may be provided on the conductor 205a. By adopting such a configuration, the diffusion of impurities such as hydrogen and metal impurities such as copper contained in the lower layer of the transistor 200 into the conductor 205 can be suppressed.

[0118] The insulator 224 functions as a second gate insulator together with the insulator 221 and the insulator 222.

[0119] As the insulator 224 in contact with the oxide semiconductor 230, the insulating material described in <<Insulator>> can be used. The insulator 224 preferably has, for example, silicon oxide or silicon oxynitride. Thereby, oxygen can be supplied from the insulator 224 to the oxide semiconductor 230, and oxygen deficiency can be reduced. Note that the insulator 224 may have a laminated structure of two or more layers. In that case, it is not limited to a laminated structure made of the same material, and a laminated structure made of different materials may also be used.

[0120] In addition, similar to the oxide semiconductor 230, the insulator 224 is preferably processed into an island shape. As a result, when a plurality of transistors 200 are provided, each transistor 200 will have an insulator 224 of approximately the same size. Thereby, in each transistor 200, the amount of oxygen supplied from the insulator 224 to the oxide semiconductor 230 will be approximately the same. Therefore, variations in the electrical characteristics of the transistors 200 within the substrate surface can be suppressed.

[0121] However, the insulator 224 does not necessarily have to be processed into an island shape. For example, as shown in FIGS. 4(A) to 4(D), the insulator 224 may be formed in a shape with an opening formed in a part thereof instead of an island shape. Here, FIGS. 4(A) to 4(D) respectively correspond to FIGS. 1(A) to 1(D), and are the same as FIGS. 1(A) to 1(D) except for the different shape of the insulator 224.

[0122] In the insulator 224 shown in FIGS. 4(A) to 4(D), the film thickness of the region that does not overlap with the oxide semiconductor 230 is thinner than the film thickness of the region that overlaps with the oxide semiconductor 230. In addition, an opening is formed in the region that does not overlap with the oxide semiconductor 230 and overlaps with the insulator 250. When a plurality of transistors are provided on the same substrate, by forming the insulator 224 in this way, the oxide semiconductors 230 of each transistor are formed on the same insulator 224. Thereby, variations in the amount of oxygen supplied from the insulator 224 to the oxide semiconductors 230 of each transistor can be reduced. Therefore, variations in the electrical characteristics of each transistor can be reduced.

[0123] Note that in the insulator 224 shown in FIGS. 4(A) to 4(D), although an opening is formed in the region that does not overlap with the oxide semiconductor 230 and overlaps with the insulator 250, a configuration without providing the opening may also be adopted.

[0124] For the conductor 242a, the conductor 242b, and the conductor 260, the conductive material described in the item of <<conductor>> can be used. In particular, as the conductor 242a, the conductor 242b, and the conductor 260, it is preferable to use a conductive material that is difficult to be oxidized or a conductive material having a function of suppressing the diffusion of oxygen. Examples of the conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. Thereby, it is possible to suppress a decrease in the conductivity of the conductor 242a, the conductor 242b, and the conductor 260. When a conductive material containing metal and nitrogen is used as the conductor 242a, the conductor 242b, and the conductor 260, the conductor 242a, the conductor 242b, and the conductor 260 become conductors having at least metal and nitrogen.

[0125] As the conductor 242a and the conductor 242b, it is preferable to use a metal nitride. For example, it is preferable to use a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, a nitride containing titanium and aluminum, and the like. For example, tantalum nitride can be used as the conductor 242a and the conductor 242b. Further, for example, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, and the like may be used. These materials are preferable because they are conductive materials that are difficult to be oxidized or materials that maintain conductivity even when they absorb oxygen.

[0126] Note that hydrogen contained in the oxide semiconductor 230 or the like may diffuse into the conductor 242a or the conductor 242b. In particular, by using a nitride containing tantalum for the conductor 242a and the conductor 242b, hydrogen contained in the oxide semiconductor 230 or the like easily diffuses into the conductor 242a or the conductor 242b, and the diffused hydrogen may combine with nitrogen that the conductor 242a or the conductor 242b has. That is, hydrogen contained in the oxide semiconductor 230 or the like may be absorbed by the conductor 242a or the conductor 242b.

[0127] Further, the conductors 242a and 242b may have a laminated structure. In this case, the above-described conductive material may be used for the lower layers of the conductors 242a and 242b, and a more conductive material may be used for the upper layers of the conductors 242a and 242b. For example, tantalum nitride may be used for the lower layer, and tungsten may be used for the upper layer.

[0128] The insulators 271a and 271b are inorganic insulators that function as an etching stopper during the processing of the conductors 242a and 242b and protect the conductors 242a and 242b. Further, since the insulators 271a and 271b are in contact with the conductors 242a and 242b, it is preferable that they are inorganic insulators that are less likely to oxidize the conductors 242a and 242b. Therefore, as shown in FIG. 2(A), it is preferable that the insulator 271a has a laminated structure of an insulator 271a1 and an insulator 271a2 on the insulator 271a1, and the insulator 271b has a laminated structure of an insulator 271b1 and an insulator 271b2 on the insulator 271b1. Here, it is preferable to use a nitride insulator that can be used for the insulator 250c for the insulators 271a1 and 271b1 so that the conductors 242a and 242b are less likely to be oxidized. Further, it is preferable to use an oxide insulator that can be used for the insulator 250b for the insulators 271a2 and 271b2 so that they function as an etching stopper.

[0129] Here, the insulator 271a1 is in contact with the upper surface of the conductor 242a and a part of the insulator 275, and the insulator 271b1 is in contact with the upper surface of the conductor 242b and a part of the insulator 275. Further, the insulator 271a2 is in contact with the upper surface of the insulator 271a1 and the lower surface of the insulator 275, and the insulator 271b2 is in contact with the upper surface of the insulator 271b1 and the lower surface of the insulator 275. For example, silicon nitride can be used for the insulators 271a1 and 271b1, and silicon oxide can be used for the insulators 271a2 and 271b2.

[0130] The insulator that serves as the basis for insulator 271a and insulator 271b functions as a mask for the conductor that serves as the basis for conductor 242a and conductor 242b. Therefore, as shown in FIG. 1(D), conductors 242a and 242b do not have a curved surface between their side surfaces and upper surfaces. As a result, the ends where the side surfaces and upper surfaces of conductors 242a and 242b meet are angular. When the ends where the side surfaces and upper surfaces of conductors 242a and 242b meet are angular, the cross-sectional areas of conductors 242a and 242b are larger than when the ends have a curved surface. Furthermore, by using a nitride insulator that is difficult to oxidize for insulators 271a1 and 271b1, it is possible to prevent conductors 242a and 242b from being overly oxidized. As a result, since the resistance of conductors 242a and 242b is reduced, the on-current of the transistor can be increased.

[0131] As shown in FIGS. 1(B) and 1(C), conductor 260 is disposed within openings formed in insulator 280 and insulator 275. Within the opening, conductor 260 is provided so as to cover the upper surface of insulator 222, the side surface of insulator 224, the side surface and upper surface of oxide semiconductor 230 via insulator 250. Also, the upper surface of conductor 260 is arranged to be flush or substantially flush with the upper end of insulator 250 and the upper surface of insulator 280.

[0132] Note that in the above-described opening in which conductor 260 and insulator 250 are disposed, the side wall of the opening may be perpendicular or substantially perpendicular to the upper surface of insulator 222, or may have a tapered shape. By making the side wall have a tapered shape, the covering property of insulator 250 provided in the opening of insulator 280 is improved, and defects such as looseness can be reduced.

[0133] Conductor 260 functions as the first gate electrode of transistor 200. Here, as shown in FIGS. 1(A) and 1(C), conductor 260 is preferably provided to extend in the channel width direction. With such a configuration, when a plurality of transistors are provided, conductor 260 functions as a wiring.

[0134] When having the structure as described above, as shown in FIG. 1(C), in a cross-sectional view in the channel width direction of the transistor 200, a curved surface may be provided between the side surface and the upper surface of the oxide semiconductor 230. That is, the end of the side surface and the end of the upper surface may be curved (hereinafter, also referred to as a rounded shape).

[0135] The radius of curvature of the curved surface is preferably greater than 0 nm and less than the film thickness of the oxide semiconductor 230 in the region overlapping with the conductor 242a and the conductor 242b, or less than half of the length of the region without the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and 20 nm or less, preferably 1 nm or more and 15 nm or less, and more preferably 2 nm or more and 10 nm or less. By adopting such a shape, the covering properties of the insulator 250 and the conductor 260 on the oxide semiconductor 230 can be enhanced.

[0136] In this specification and the like, a structure of a transistor in which a channel formation region is electrically surrounded by an electric field of at least a first gate electrode is referred to as a surrounded channel (S-channel) structure. In addition, the S-channel structure disclosed in this specification and the like has a structure different from a Fin type structure and a planar type structure. On the other hand, the S-channel structure disclosed in this specification and the like can also be regarded as a kind of Fin type structure. In this specification and the like, the Fin type structure refers to a structure in which a gate electrode is arranged so as to surround at least two or more surfaces (specifically, two surfaces, three surfaces, or four surfaces, etc.) of a channel. By adopting the Fin type structure and the S-channel structure, the resistance to the short channel effect can be enhanced, in other words, a transistor in which the short channel effect is less likely to occur can be obtained.

[0137] By forming the transistor 200 with the above-described S-channel structure, the channel formation region can be electrically surrounded. Since the S-channel structure is a structure that electrically surrounds the channel formation region, it can be said that it is substantially equivalent to a GAA (Gate All Around) structure or an LGAA (Lateral Gate All Around) structure. By forming the transistor 200 with an S-channel structure, a GAA structure, or an LGAA structure, the channel formation region formed at or near the interface between the oxide semiconductor 230 and the gate insulator can be made the entire bulk of the oxide semiconductor 230. Therefore, since it becomes possible to improve the current density flowing through the transistor, an increase in the on-current of the transistor or an increase in the field-effect mobility of the transistor can be expected.

[0138] In this embodiment, the insulator 224 is provided in an island shape. Therefore, as shown in FIG. 1(C), at least a part of the lower surface of the conductor 260 can be provided below the lower surface of the oxide semiconductor 230. Thereby, since the conductor 260 can be provided facing the upper surface and the side surfaces of the oxide semiconductor 230, the electric field of the conductor 260 can act on the upper surface and the side surfaces of the oxide semiconductor 230. By adopting the configuration in which the insulator 224 is provided in an island shape in this way, the transistor 200 can be formed with an S-channel structure.

[0139] Note that, although the transistor 200 shown in FIG. 1(C) is an example of a transistor with an S-channel structure, the semiconductor device according to one aspect of the present invention is not limited thereto. For example, as a transistor structure that can be used in one aspect of the present invention, any one or more selected from a planar structure, a Fin structure, and a GAA structure may be used.

[0140] As shown in FIG. 2(A), it is preferable that the conductor 260 has a two-layer structure. Here, the conductor 260 preferably has a conductor 260a and a conductor 260b disposed on the conductor 260a. For example, the conductor 260a is preferably disposed so as to wrap the bottom surface and the side surface of the conductor 260b. At this time, as the conductor 260a, it is preferable to use a conductive material that is difficult to be oxidized or a conductive material having a function of suppressing the diffusion of oxygen.

[0141] It is preferable to use a conductive material for the conductor 260a that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules).

[0142] In addition, since the conductor 260a has a function of suppressing the diffusion of oxygen, it is possible to suppress the oxidation of the conductor 260b by oxygen contained in the insulator 280 or the like and the decrease in conductivity. As the conductive material having a function of suppressing the diffusion of oxygen, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. are preferably used.

[0143] In addition, for the conductor 260b, it is preferable to use a conductor having high conductivity. For example, the conductor 260b can use a conductive material mainly composed of tungsten, copper, or aluminum. Also, the conductor 260b may have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.

[0144] In addition, in the transistor 200, the conductor 260 is self-alignedly formed so as to fill an opening formed in the insulator 280 or the like. By forming the conductor 260 in this way, the conductor 260 can be disposed so as to overlap the region between the conductor 242a and the conductor 242b without alignment.

[0145] The insulator 216, the insulator 280, and the insulator 285 preferably each have a lower dielectric constant than the insulator 222. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced.

[0146] For example, the insulator 216, the insulator 280, and the insulator 285 preferably each have one or more of silicon oxide, silicon oxynitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, and silicon oxide having pores.

[0147] In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having pores are preferable because regions containing oxygen that desorb by heating can be easily formed.

[0148] Also, the upper surfaces of the insulator 216 and the insulator 280 may each be planarized.

[0149] The impurity concentrations such as water and hydrogen in the insulator 280 are preferably reduced. For example, the insulator 280 preferably has an oxide containing silicon such as silicon oxide or silicon oxynitride.

[0150] For the conductor 240a and the conductor 240b, the conductive materials described in the item of <<Conductor>> can be used. The conductor 240a and the conductor 240b preferably use, for example, a conductive material mainly composed of tungsten, copper, or aluminum. Also, the conductor 240a and the conductor 240b may have a laminated structure.

[0151] For example, as shown in FIG. 2(A), the conductors 240a and 240b may have a two-layer stacked structure. The conductor 240a has a conductor 240a1 formed along the opening and a conductor 240a2 formed inside the conductor 240a1. Also, the conductor 240b has a conductor 240b1 formed along the opening and a conductor 240b2 formed inside the conductor 240b1.

[0152] For the conductors 240a1 and 240b1, it is preferable to use a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen, similar to the conductor 205a. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. Also, the conductive material having a function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or in a stacked manner. By providing the conductors 240a1 and 240b1, it is possible to suppress impurities such as water and hydrogen from mixing into the oxide semiconductor 230 through the conductors 240a2 and 240b2. Note that for the conductors 240a2 and 240b2, a conductive material that can be used for the above-mentioned conductors 240a and 240b may be used.

[0153] Also, as shown in FIG. 1(B), the upper surfaces of the conductors 240a and 240b can be formed to coincide with or substantially coincide with the upper surface of the insulator 285. Also, as shown in FIG. 2(A), the lower part of the conductor 240a may be formed to be embedded in the conductor 242a. Similarly, the lower part of the conductor 240b may be formed to be embedded in the conductor 242b.

[0154] As the insulators 241a and 241b, a barrier insulator that can be used for the insulator 275 or the like may be used. For example, silicon nitride may be used as the insulators 241a and 241b. The insulators 241a and 241b are provided in contact with the insulator 285, the insulator 283, the insulator 282, the insulator 275, the insulator 271a, and the insulator 271b. Thereby, it is possible to suppress impurities such as water and hydrogen contained in the insulator 280 or the like from being mixed into the oxide semiconductor 230 through the conductors 240a and 240b. In particular, silicon nitride is suitable because it has high blocking property against hydrogen. Further, it is possible to prevent oxygen contained in the insulator 280 from being absorbed by the conductors 240a and 240b.

[0155] Further, the insulators 241a and 241b may have a laminated structure. In this case, it is preferable to use a combination of a first insulator in contact with the side wall of the opening of the insulator 280 or the like and a second insulator inside thereof as a barrier insulator against oxygen and a barrier insulator against hydrogen.

[0156] <Modification 1> In FIG. 1(B) or the like, in the opening provided in the insulator 280, the insulator 250 is in contact with the side surface of the insulator 280, but the present invention is not limited to this configuration. For example, an insulator may be provided between the insulator 250 and the insulator 280 in the opening.

[0157] Using FIGS. 5(A) to 6(C), a modification of the semiconductor device described in <Configuration Example of Semiconductor Device> will be described. FIGS. 5(A) to 5(D) are a plan view and a cross-sectional view of a semiconductor device having a transistor 200, and correspond to the plan view and the cross-sectional view shown in FIGS. 1(A) to 1(D), respectively. FIGS. 6(A) to 6(C) are enlarged cross-sectional views in the channel length direction of the transistor 200, and correspond to the enlarged cross-sectional view shown in FIG. 2(B), respectively.

[0158] The transistor 200 shown in FIGS. 5(A) to 5(D) is a modified example of the transistor 200 shown in FIGS. 1(A) to 1(D). Specifically, the transistor 200 shown in FIGS. 5(A) to 5(D) mainly differs from the transistor 200 shown in FIGS. 1(A) to 1(D) in that it has an insulator 255. Hereinafter, mainly the parts different from the description of the <configuration example of the semiconductor device> described above will be described, and for the overlapping parts, these will be referred to, and the description may be omitted in some cases.

[0159] Note that in FIG. 5, each of the conductor 242a and the conductor 242b is shown in a two-layer structure. The conductor 242a has a stacked structure of a conductor 242a1 and a conductor 242a2 on the conductor 242a1. The conductor 242b has a stacked structure of a conductor 242b1 and a conductor 242b2 on the conductor 242b1. The conductor 242a1 and the conductor 242b1 correspond to the lower layers of the conductor 242a and the conductor 242b described above, respectively, and the conductor 242a2 and the conductor 242b2 correspond to the upper layers of the conductor 242a and the conductor 242b described above, respectively.

[0160] As shown in FIGS. 5(B) and 5(C), the insulator 255 is disposed inside an opening formed in the insulator 280 or the like, and is in contact with the side surface of the insulator 280, the side surface of the conductor 242a2, the side surface of the conductor 242b2, the upper surface of the conductor 242a1, the upper surface of the conductor 242b1, and the upper surface of the insulator 222 in the opening. In other words, it can also be said that the insulator 255 is formed in a sidewall shape in contact with the sidewall of the opening formed in the insulator 280 or the like. Here, the sidewall of the opening corresponds to, for example, the side surface of the insulator 280 or the like in the opening.

[0161] Further, the insulator 250 is in contact with the side surface of the insulator 255.

[0162] The insulator 255 preferably has barrier properties against oxygen. Since the insulator 255 has barrier properties against oxygen, it is possible to suppress the oxidation of the side surfaces of the conductor 242a and the conductor 242b and the formation of an oxide film on the side surfaces. Thereby, it is possible to suppress a decrease in the on-current or a decrease in the field-effect mobility of the transistor 200. As the insulator 255, a barrier insulator that can be used for the insulator 275 or the like can be used. For example, silicon nitride may be used as the insulator 255.

[0163] The opening provided in the insulator 280 overlaps with the region between the conductor 242a2 and the conductor 242b2. In a top view, the side surface of the insulator 280 in the opening coincides with or substantially coincides with the side surfaces of the conductor 242a2 and the conductor 242b2. Further, a part of the conductor 242a1 and a part of the conductor 242b1 are formed so as to protrude inside the opening. In other words, in the conductor 242a1, a portion where the insulator 255 is formed on the upper surface (hereinafter sometimes referred to as the protruding portion of the conductor 242a1) protrudes toward the conductor 260 side from the conductor 242a2. Similarly, in the conductor 242b1, a portion where the insulator 255 is formed on the upper surface (hereinafter sometimes referred to as the protruding portion of the conductor 242b1) protrudes toward the conductor 260 side from the conductor 242b2.

[0164] Here, a part of the upper surface of the conductor 242a1 is in contact with the conductor 242a2, and a part of the upper surface of the conductor 242b1 is in contact with the conductor 242b2. Therefore, the insulator 255 is in contact with the other part of the upper surface of the conductor 242a1, the other part of the upper surface of the conductor 242b1, the side surface of the conductor 242a2, and the side surface of the conductor 242b2 inside the opening. Further, the insulator 250 is in contact with the upper surface of the oxide semiconductor 230, the side surfaces of the conductor 242a1 and the conductor 242b1, and the side surface of the insulator 255.

[0165] After the conductive layer is divided into the conductors 242a2 and 242b2, the insulator 255 is formed using anisotropic etching. The insulator 255 is formed in a sidewall shape in contact with the sidewalls of the openings provided in the insulator 280. The insulator 255 is formed in contact with the side surfaces of the conductor 242a2 and the side surfaces of the conductor 242b2, and has a function of protecting the conductor 242a2 and the conductor 242b2.

[0166] Also, the insulator 255 functions as a mask when dividing the conductive layer into the conductors 242a1 and 242b1. Therefore, as shown in FIG. 6(A), in a cross-sectional view of the transistor 200, it is preferable that the side ends of the insulator 255 coincide with the side ends of the conductor 242a1 and the side ends of the conductor 242b1.

[0167] Note that after dividing into the conductors 242a1 and 242b1 and before forming the insulator 250, it is preferable to perform heat treatment in an atmosphere containing oxygen. At this time, since the insulator 255 is formed in contact with the side surfaces of the conductor 242a2 and the side surfaces of the conductor 242b2, it is possible to prevent the conductor 242a2 and the conductor 242b2 from being excessively oxidized. Also, even when performing microwave treatment after dividing into the conductors 242a1 and 242b1, it is possible to suppress the formation of an oxide film on the side surfaces of the conductor 242a and the conductor 242b.

[0168] The portions of the insulator 255, the insulator 250, and the conductor 260 disposed in the opening provided in the insulator 280 are provided in reflection of the shape of the opening. Therefore, the insulator 255 is provided so as to cover the sidewalls of the opening, the insulator 250 is provided so as to cover the bottom of the opening and the insulator 255, and the conductor 260 is provided so as to fill the recess of the insulator 250.

[0169] Note that, similar to the above <configuration example of the semiconductor device>, the insulator 250 may have a stacked structure. For example, as shown in FIG. 6(A), the insulator 250 may have a three-layer structure of insulator 250a, insulator 250b, and insulator 250c. Also, for example, as shown in FIG. 6(B), the insulator 250 may have a four-layer structure of insulator 250a, insulator 250b, insulator 250c, and insulator 250d. Further, not limited to the structure shown in FIG. 6(B), any one or more of insulator 250a, insulator 250b, insulator 250c, and insulator 250d can be selected to form the insulator 250. For example, it can be the insulator 250 having the structure shown in FIGS. 3(A) to 3(D).

[0170] Also, the film thickness of the insulator 255 is preferably 0.5 nm or more and 20 nm or less, more preferably 0.5 nm or more and 10 nm or less, and still more preferably 0.5 nm or more and 3 nm or less. By setting the film thickness of the insulator 255 as described above, it is possible to suppress excessive oxidation of the conductor 242a2 and the conductor 242b2. Note that the insulator 255 only needs to have a region with the above-described film thickness in at least a part thereof. Also, since the insulator 255 is provided in contact with the sidewalls of the openings formed in the insulator 280 or the like, it is preferable to form the film using a method such as ALD method with good coverage. If the film thickness of the insulator 255 is excessively thick, the film formation time of the insulator 255 by the ALD method becomes long and the productivity decreases. Therefore, the film thickness of the insulator 255 is preferably set to about the above range. Also, the insulator 255 preferably has a film thickness that does not excessively prevent the diffusion of excessive oxygen from the insulator 280 to the insulator 250b and the diffusion of excessive oxygen from the insulator 250b to the oxide semiconductor 230.

[0171] As shown in FIG. 6(A), in the cross-sectional view in the channel length direction of the transistor 200, the distance L1 between the conductors 242a1 and 242b1 is smaller than the distance L2 between the conductors 242a2 and 242b2. Here, the distance L1 refers to the shortest distance between the conductors 242a1 and 242b1, and the distance L2 refers to the shortest distance between the conductors 242a2 and 242b2. With such a configuration, it becomes possible to shorten the distance between the source and the drain, and accordingly shorten the channel length. Therefore, the frequency characteristics of the transistor 200 can be improved. In this way, by miniaturizing the semiconductor device, a semiconductor device with an improved operating speed can be provided.

[0172] In the configuration shown in FIG. 6(A), the difference between the distance L2 and the distance L1 coincides with twice the film thickness of the insulator 255. In other words, the distance L2 coincides with the distance L1 added with twice the film thickness of the insulator 255. Here, the film thickness of the insulator 255 refers to the width in the A1 - A2 direction in at least a part of the insulator 255.

[0173] Also, the insulator 255 may have a laminated structure of two or more layers. In this case, at least one layer may be the above-mentioned inorganic insulator that is difficult to be oxidized. For example, the above-mentioned inorganic insulator that is difficult to be oxidized may be used for the first insulator of the insulator 255, and an insulator applicable to the insulator 250b (for example, silicon oxide, etc.) may be used for the second insulator on the first insulator of the insulator 255. It is preferable that the dielectric constant of the second insulator of the insulator 255 is lower than that of the first insulator of the insulator 255. In this way, by making the insulator 255 have a two-layer structure and increasing the film thickness, the distance between the conductor 260 and the conductor 242a or the conductor 242b can be increased, and the parasitic capacitance can be reduced.

[0174] In the above description, an example in which the insulator 255 is formed in a sidewall shape by anisotropic etching has been shown, but the present invention is not limited to this. As shown in FIG. 6(C), the insulator 255 can also have a shape with an opening inside the opening formed in the insulator 280 or the like. In this case, the opening of the insulator 255 can be formed by removing a part of the insulating film that becomes the insulator 255 by a lithography method. The opening of the insulator 255 preferably overlaps with the region between the conductor 242a1 and the conductor 242b1.

[0175] As shown in FIG. 6(C), in a cross-sectional view, a protruding portion is formed below the insulator 255. The protruding portion of the insulator 255 overlaps with the protruding portion of the conductor 242a1 and the protruding portion of the conductor 242b1.

[0176] <Modification Example 2> In Modification Example 1, the configuration in which the insulator 255 is provided in contact with the side wall of the opening formed in the insulator 280 or the like has been described, but the present invention is not limited to this configuration. For example, the insulator 255 may not be provided in the opening.

[0177] Using FIGS. 7(A) to 8, a modification example of the semiconductor device described in Modification Example 1 will be described. FIGS. 7(A) to 7(D) are a plan view and a cross-sectional view of a semiconductor device having the transistor 200, and correspond to the plan view and the cross-sectional view shown in FIGS. 5(A) to 5(D), respectively. Further, FIG. 8 is an enlarged cross-sectional view in the channel length direction of the transistor 200, and corresponds to the enlarged cross-sectional view shown in FIG. 6(C).

[0178] The transistor 200 shown in FIGS. 7(A) to 7(D) is a modification example of the transistor 200 shown in FIGS. 5(A) to 5(D). Specifically, the transistor 200 shown in FIGS. 7(A) to 7(D) is mainly different from the transistor 200 shown in FIGS. 5(A) to 5(D) in that it does not have the insulator 255. Hereinafter, mainly the parts different from the descriptions of the above <Configuration Example of Semiconductor Device> and <Modification Example 1> will be described, and the overlapping parts will be referred to and the description may be omitted.

[0179] As shown in FIG. 8, when the configuration is such that the insulator 255 is not provided, a part of the insulator 250 is disposed so as to overlap the protruding portions of the conductor 242a1 and the conductor 242b1. Also, in some cases, a part of the conductor 260 is disposed so as to overlap the protruding portions of the conductor 242a1 and the conductor 242b1. Here, the protruding portions of the conductor 242a1 and the conductor 242b1 are in contact with the insulator 250. Also, the side surface of the insulator 250 is in contact with the side surfaces of the insulator 280, the insulator 275, the insulator 271a, the insulator 271b, the conductor 242a2, and the conductor 242b2.

[0180] The portion of the insulator 250 disposed in the opening provided in the insulator 280 is formed to reflect the shape of the opening. Therefore, the insulator 250 is formed to reflect the shapes of the conductor 242a1 and the conductor 242b1 protruding into the opening.

[0181] As shown in FIG. 8, in a cross-sectional view in the channel length direction of the transistor 200, the distance L1 between the conductor 242a1 and the conductor 242b1 is smaller than the distance L2 between the conductor 242a2 and the conductor 242b2. By adopting such a configuration, it is possible to make the distance between the source and the drain shorter, and accordingly shorten the channel length. Therefore, the frequency characteristics of the transistor 200 can be improved. In this way, by miniaturizing the semiconductor device, a semiconductor device with an improved operating speed can be provided.

[0182] Furthermore, by adopting the structure as shown in FIG. 8, the width of the upper part of the conductor 260 can be made larger than the distance L1. Thereby, the wiring resistance of the conductor 260 can be reduced. Therefore, the power consumption of the semiconductor device can be reduced.

[0183] In addition, similar to the above <configuration example of the semiconductor device>, the insulator 250 may have a stacked structure. For example, as shown in FIG. 6(A), the insulator 250 may have a three-layer structure of insulator 250a, insulator 250b, and insulator 250c. Also, for example, as shown in FIG. 6(B), the insulator 250 may have a four-layer structure of insulator 250a, insulator 250b, insulator 250c, and insulator 250d. Further, not limited to the structure shown in FIG. 6(B), any one or more of insulator 250a, insulator 250b, insulator 250c, and insulator 250d can be selected to form the insulator 250. For example, it can be the insulator 250 having the structure shown in FIGS. 3(A) to 3(D).

[0184] <Constituent materials of the semiconductor device> Hereinafter, the constituent materials that can be used in the semiconductor device will be described. Note that each layer constituting the semiconductor device may have a single-layer structure or a stacked structure.

[0185] <<Substrate>> As the substrate for forming the transistor, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate can be used. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as yttria-stabilized zirconia substrate), and a resin substrate. Examples of the semiconductor substrate include a semiconductor substrate made of silicon or germanium, and a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Further, a semiconductor substrate having an insulator region inside the aforementioned semiconductor substrate, such as a SOI (Silicon On Insulator) substrate, can be mentioned. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Also, as the substrate, for example, a substrate having a metal nitride, a substrate having a metal oxide, a substrate in which a conductor or a semiconductor is provided on an insulator substrate, a substrate in which a conductor or an insulator is provided on a semiconductor substrate, and a substrate in which a semiconductor or an insulator is provided on a conductor substrate can be mentioned. Or, those in which one or more types of elements are provided on these substrates may be used. Examples of the elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, and a memory element.

[0186] <<Insulator>> Among the insulators shown in this embodiment, namely, insulator 212, insulator 214, insulator 216, insulator 221, insulator 222, insulator 224, insulator 250, insulator 275, insulator 280, insulator 282, insulator 283, insulator 285, insulator 241a, insulator 241b, insulator 271a, insulator 271b, and insulator 255, any of the insulators shown below can be appropriately used. Examples of the insulator include an oxide having insulating properties, a nitride, an oxynitride, a nitroxide, a metal oxide, a metal oxynitride, and a metal nitroxide.

[0187] For example, as the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for the insulator that functions as the gate insulator, it becomes possible to lower the voltage during transistor operation while maintaining the physical film thickness. On the other hand, for the insulator that functions as the interlayer film, by using a material with a low relative permittivity, the parasitic capacitance generated between the wirings can be reduced. Therefore, it is advisable to select a material according to the function of the insulator.

[0188] Examples of insulators with a high relative permittivity include, for example, gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0189] Examples of insulators with a low relative permittivity include, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with pores, and resin.

[0190] In addition, a transistor using a metal oxide can have its electrical characteristics stabilized by surrounding it with an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen. As the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing one or more of boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum can be used in a single layer or in a stacked layer. Specifically, examples of the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and nitrides such as aluminum nitride, silicon oxynitride, and silicon nitride.

[0191] In addition, the insulator functioning as a gate insulator is preferably an insulator having a region containing oxygen that desorbs upon heating. For example, by forming a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that desorbs upon heating is in contact with the oxide semiconductor 230, the oxygen deficiency of the oxide semiconductor 230 can be compensated.

[0192] <<Conductor>> The conductor 205, conductor 242a, conductor 242b, conductor 260, conductor 240a, and conductor 240b shown in this embodiment can be appropriately selected from the following conductors. As the conductor, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, cobalt, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-described metal element as a component, or an alloy combining the above-described metal elements, etc. is preferably used. As the conductor, for example, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, and an oxide containing lanthanum and nickel can be mentioned. Further, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, and an oxide containing lanthanum and nickel are each a conductive material that is difficult to be oxidized, or a material that maintains conductivity even when absorbing oxygen, and thus are preferable. Also, a semiconductor having a high electrical conductivity typified by polycrystalline silicon containing impurity elements such as phosphorus, or a silicide such as nickel silicide may be used.

[0193] When using a laminated conductor, for example, a laminated structure combining a material containing the above-described metal element and a conductive material containing oxygen, a laminated structure combining a material containing the above-described metal element and a conductive material containing nitrogen, or a laminated structure combining a material containing the above-described metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be applied.

[0194] In addition, when an oxide is used for the channel formation region of the transistor, it is preferable to use a stacked structure in which a conductor functioning as a gate electrode combines a material containing the above-described metal element and a conductive material containing oxygen. In this case, it is preferable to provide the conductive material containing oxygen on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is likely to be supplied to the channel formation region.

[0195] In particular, as the conductor functioning as a gate electrode, it is preferable to use a conductive material containing a metal element and oxygen contained in the metal oxide in which the channel is formed. Also, a conductive material containing the above-described metal element and nitrogen may be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used. Also, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide added with silicon may be used. Also, indium gallium zinc oxide containing nitrogen may be used. By using such a material, it may be possible to capture hydrogen contained in the metal oxide in which the channel is formed. Or, it may be possible to capture hydrogen mixed from an external insulator or the like.

[0196] <Example of manufacturing method of semiconductor device> An example of a manufacturing method of a semiconductor device according to an aspect of the present invention will be described with reference to FIGS. 9(A) to 16(D). Here, the case of manufacturing the semiconductor device shown in FIGS. 1(A) to 1(D) will be described as an example.

[0197] 9 to 12, and (A) of 14 to 16 are plan views. Also, (B) of 9 to 12, and 14 to 16 are cross-sectional views corresponding to the portions indicated by the one-dot chain line A1 - A2 in (A) of each figure, and are also cross-sectional views in the channel length direction of the transistor 200. Further, (C) of 9 to 12, and 14 to 16 are cross-sectional views corresponding to the portions indicated by the one-dot chain line A3 - A4 in (A) of each figure, and are also cross-sectional views in the channel width direction of the transistor 200. Also, (D) of 9 to 12, and 14 to 16 are cross-sectional views of the portions indicated by the one-dot chain line A5 - A6 in (A) of each figure, and are also cross-sectional views in the channel width direction of the transistor 200. In the plan views of (A) of 9 to 12, and 14 to 16, some elements are omitted for clarity of the figure. Also, 13(A1) to 13(D1) are cross-sectional views corresponding to a part of 1(B), and are also cross-sectional views in the channel length direction of the transistor 200. Further, 13(A2) to 13(D2) are cross-sectional views corresponding to a part of 1(C), and are also cross-sectional views in the channel width direction of the transistor 200.

[0198] In the following, an insulating material for forming an insulator, a conductive material for forming a conductor, or a semiconductor material for forming a semiconductor can be formed into a film by appropriately using a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an ALD method, etc.

[0199] First, prepare a substrate (not shown), form an insulator 212 on the substrate, and form an insulator 214 on the insulator 212 (see FIGS. 9(A) to 9(D)). As the insulator 212 and the insulator 214, the above-described insulating material can be used. As the method for forming the insulator 212 and the insulator 214, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method can be used. By using a sputtering method that does not require a molecule containing hydrogen as a film-forming gas, the hydrogen concentration in the insulator 212 and the insulator 214 can be reduced, which is preferable.

[0200] In this embodiment, as the insulator 212, silicon nitride is formed using a sputtering method, and as the insulator 214, aluminum oxide is formed using a sputtering method. In this way, by using silicon nitride having a function of suppressing the diffusion of hydrogen for the insulator 212, it is possible to suppress the diffusion of hydrogen from the lower layer of the transistor 200. Further, by using aluminum oxide having a function of capturing or fixing hydrogen for the insulator 214, the hydrogen contained in the insulator 216 or the like can be captured or fixed by the insulator 214. Thereby, the hydrogen concentration in the oxide semiconductor 230 and its vicinity can be reduced.

[0201] Also, before forming the insulator 212, it is preferable to perform a heat treatment to reduce the water and hydrogen adsorbed on the substrate (including the circuit elements and the interlayer films formed on the substrate). In this embodiment, the temperature of the heat treatment is set to 400°C.

[0202] Next, an insulator 216 is formed on the insulator 214. The formation of the insulator 216 is preferably performed using a sputtering method. By using a sputtering method that does not require a molecule containing hydrogen as a film-forming gas, the hydrogen concentration in the insulator 216 can be reduced. However, the formation of the insulator 216 is not limited to the sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may be appropriately used. In this embodiment, as the insulator 216, silicon oxide is formed using a sputtering method.

[0203] The insulator 212, the insulator 214, and the insulator 216 are preferably formed continuously without being exposed to the atmosphere. For example, a multi-chamber film forming apparatus may be used. Thereby, the insulator 212, the insulator 214, and the insulator 216 can be formed while reducing hydrogen in the film, and further, the incorporation of hydrogen into the film during the intervals between the respective film forming steps can be reduced.

[0204] Next, an opening reaching the insulator 214 is formed in the insulator 216. The opening is formed in the region where the conductor 205 is formed. The opening may be formed using wet etching, but dry etching is more preferable for microfabrication. Further, it is preferable to select the insulator 214 as an insulator that functions as an etching stopper film when etching the insulator 216. For example, when silicon oxide or silicon oxynitride is used for the insulator 216, the insulator 214 may be silicon nitride, aluminum oxide, hafnium oxide, or the like.

[0205] After the formation of the opening, a conductive film to be the conductor 205 is formed, and CMP processing is performed until the insulator 216 is exposed to remove a part of the conductive film to be the conductor 205. Thereby, the conductor 205 embedded in the insulator 216 can be formed (see FIGS. 9(A) to 9(D)).

[0206] Here, the conductive film to be the conductor 205 can be formed using the above-described conductive material by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, a tantalum nitride film, a titanium nitride film, and a tungsten film may be laminated and formed using the CVD method. Thereby, as shown in FIG. 2(A), the conductor 205 can have a laminated structure of a conductor 205a in which titanium nitride is laminated on tantalum nitride and a tungsten conductor 205b.

[0207] Next, an insulator 221 is formed on the insulator 216 and the conductor 205 (see FIGS. 9(A) to 9(D)).

[0208] As the insulator 221, an insulator having barrier properties against oxygen, hydrogen, and water described above may be used. The insulator 221 can be formed, for example, by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In the present embodiment, silicon nitride is formed as the insulator 221 using the PEALD method.

[0209] Next, an insulator 222 is formed on the insulator 221 (see FIGS. 9(A) to 9(D)).

[0210] As the insulator 222, an insulator containing one or both of oxides of aluminum and hafnium may be formed. Note that, as the insulator containing one or both of oxides of aluminum and hafnium, for example, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used. Alternatively, hafnium zirconium oxide is preferably used. The insulator containing one or both of oxides of aluminum and hafnium has barrier properties against oxygen, hydrogen, and water. Since the insulator 222 has barrier properties against hydrogen and water, hydrogen and water contained in the structure provided around the transistor are suppressed from diffusing inside the transistor through the insulator 222, and generation of oxygen vacancies in the oxide semiconductor 230 can be suppressed.

[0211] The insulator 222 can be formed, for example, by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In the present embodiment, hafnium oxide is formed as the insulator 222 using the thermal ALD method.

[0212] In this embodiment, silicon nitride is formed as the insulator 221 by using the PEALD method, and hafnium oxide is formed as the insulator 222 by using the thermal ALD method. In this way, by using silicon nitride having a function of suppressing the diffusion of hydrogen for the insulator 221, it is possible to suppress the diffusion of hydrogen from the lower layer of the transistor 200. Further, by using hafnium oxide having a function of capturing or fixing hydrogen for the insulator 222, the hydrogen contained in the insulator 224 or the like can be captured or fixed by the insulator 222. Thereby, the hydrogen concentration in the oxide semiconductor 230 and its vicinity can be reduced.

[0213] Next, an insulating film 224f is formed on the insulator 222 (see FIGS. 9(A) to 9(D)). As the insulating film 224f, an insulator corresponding to the above-described insulator 224 may be used. By forming the insulating film 224f in this way, the insulating film 224f is formed parallel or substantially parallel to the surface of the substrate.

[0214] The insulating film 224f can be formed, for example, by using a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, silicon oxide is formed as the insulating film 224f by using the sputtering method. By using the sputtering method that does not require a molecule containing hydrogen in the film-forming gas, the hydrogen concentration in the insulating film 224f can be reduced. Since the insulating film 224f comes into contact with the oxide semiconductor 230 in a later process, it is preferable that the hydrogen concentration is reduced in this way.

[0215] Next, an oxide semiconductor film 230f is formed on the insulating film 224f (see FIGS. 9(A) to 9(D)). The oxide semiconductor film 230f may be formed by the same method as the formation of the oxide semiconductor described in Embodiment 2. It is preferable to use indium oxide (for example, indium oxide, indium gallium oxide, indium zinc oxide, indium gallium zinc oxide, or indium gallium tin zinc oxide, etc.) for the oxide semiconductor film 230f. By configuring the oxide semiconductor film 230f to contain indium oxide, a semiconductor device with high field-effect mobility can be provided. In addition, a semiconductor device with at least one of good electrical characteristics, frequency characteristics, and reliability can be provided. Note that by forming the oxide semiconductor film 230f as described above, the oxide semiconductor film 230f is formed parallel or substantially parallel to the surface of the substrate.

[0216] For example, as shown in FIG. 2(A), when the oxide semiconductor 230 has a three-layer structure of oxide semiconductors 230a to 230c, the films that become the oxide semiconductor 230a and the oxide semiconductor 230b can be formed by the ALD method, and the film that becomes the oxide semiconductor 230c can be formed by the sputtering method. Specifically, the film that becomes the oxide semiconductor 230a can be formed to have a composition of In:Ga:Zn = 1:3:2 [atomic ratio] or in the vicinity thereof. Alternatively, gallium oxide may be used for the film that becomes the oxide semiconductor 230a. Also, the film that becomes the oxide semiconductor 230b can be formed using indium oxide. Further, the film that becomes the oxide semiconductor 230c can be formed using an oxide target having a composition of In:Ga:Zn = 1:1:1.2 [atomic ratio] or in the vicinity thereof.

[0217] Also, for example, in the above, the oxide semiconductor 230a can also be formed by the sputtering method. Specifically, the film that becomes the oxide semiconductor 230a can be formed using an oxide target having a composition of In:Ga:Zn = 1:3:2 [atomic ratio] or in the vicinity thereof.

[0218] Next, it is preferable to perform a heat treatment. The heat treatment of the oxide semiconductor film 230f may be performed in the same manner as the heat treatment described in Embodiment 2.

[0219] For example, as the heat treatment, a treatment can be performed at a temperature of 450°C for 1 hour with a flow rate ratio of nitrogen gas to oxygen gas of 4:1.

[0220] By performing the heat treatment, the crystallinity of the oxide semiconductor 230 can be improved. Thereby, the on-current, S value (subthreshold swing value), field-effect mobility, frequency characteristics, etc. of the transistor 200 can be improved, and a semiconductor device having good electrical characteristics can be provided. Also, a highly reliable semiconductor device can be provided.

[0221] Note that the heat treatment is preferably performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. Also, the heat treatment may be performed under reduced pressure. Or, after heat treatment in an atmosphere of nitrogen gas or an inert gas, heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to supplement the desorbed oxygen.

[0222] Also, the gas used in the above heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the above heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and even more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being incorporated into the oxide semiconductor film 230f as much as possible. Note that highly purified gas can also be used for the heat treatment before this step and the heat treatment after this step in the same manner.

[0223] Also, by the heat treatment including oxygen gas as described above, impurities such as carbon, water, and hydrogen in the oxide semiconductor film 230f can be reduced. By reducing the impurities in the film in this way, the crystallinity of the oxide semiconductor film 230f can be improved, and a denser and more compact structure can be obtained. As a result, the crystal region in the oxide semiconductor film 230f can be increased, and the in-plane variation of the crystal region in the oxide semiconductor film 230f can be reduced. Therefore, the in-plane variation of the electrical characteristics of the transistor can be reduced.

[0224] Also, by performing the heat treatment, oxygen can be supplied into the oxide semiconductor film 230f, and the oxygen deficiency in the oxide semiconductor film 230f can be reduced. Thereby, the reliability of the transistor 200 can be improved.

[0225] Also, by performing the heat treatment, hydrogen in the insulator 216, the insulating film 224f, and the oxide semiconductor film 230f moves to the insulator 222 and is absorbed into the insulator 222. In other words, hydrogen in the insulator 216, the insulating film 224f, and the oxide semiconductor film 230f diffuses into the insulator 222. Therefore, the hydrogen concentration of the insulator 222 increases, but the respective hydrogen concentrations in the insulator 216, the insulating film 224f, and the oxide semiconductor film 230f decrease. By providing the insulator 221 in contact with the lower surface of the insulator 222, it is possible to prevent impurities such as moisture or hydrogen from entering from below the insulator 221 in the heat treatment.

[0226] In particular, the insulating film 224f (the subsequent insulator 224) functions as the second gate insulator of the transistor 200, and the oxide semiconductor film 230f (the subsequent oxide semiconductor 230) functions as the channel formation region of the transistor 200. The transistor 200 formed using the insulating film 224f and the oxide semiconductor film 230f with reduced hydrogen concentration is preferable because it has good reliability.

[0227] Next, a conductive film 242f is formed on the oxide semiconductor film 230f (see FIGS. 9(A) to 9(D)). As the conductive film 242f, a conductor corresponding to the above-described conductors 242a and 242b may be used. After the formation of the oxide semiconductor film 230f, the conductive film 242f is formed in contact with the oxide semiconductor film 230f without including an etching process or the like therebetween, so that the upper surface of the oxide semiconductor film 230f can be protected by the conductive film 242f. As a result, diffusion of impurities into the oxide semiconductor 230 constituting the transistor can be reduced, and thus improvement in the electrical characteristics and reliability of the semiconductor device can be achieved.

[0228] The conductive film 242f can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0229] In the present embodiment, tantalum nitride is formed as the conductive film 242f using a sputtering method. Note that a heat treatment may be performed before the formation of the conductive film 242f. The heat treatment is performed under reduced pressure, and the conductive film 242f may be continuously formed without being exposed to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide semiconductor 230 can be removed, and further, the moisture concentration and hydrogen concentration in the oxide semiconductor 230 can be reduced. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower.

[0230] Next, an insulating film 271f is formed on the conductive film 242f (see FIGS. 9(A) to 9(D)). The insulating film 271f can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method or the like. It is preferable to use an insulating film having a function of suppressing oxygen permeation as the insulating film 271f. For example, as the insulating film 271f, a laminated film of a silicon nitride film and a silicon oxide film on the silicon nitride film may be formed by a sputtering method. With such a configuration, the insulator 271a (insulator 271b) can be formed into a laminated structure of a silicon nitride insulator 271a1 (insulator 271b1) and a silicon oxide insulator 271a2 (insulator 271b2).

[0231] Here, when the insulating film 271f is formed as a stacked film, it is preferable to form the film continuously without exposing it to the atmospheric environment. By forming the film without opening to the atmosphere, the vicinity of the interface of the stacked film of the insulating film 271f can be kept clean. Further, it is more preferable to form the film continuously from the conductive film 242f to the insulating film 271f without exposing it to the atmospheric environment.

[0232] Note that a heat treatment may be performed before forming the insulating film 271f. The heat treatment is performed under reduced pressure, and the insulating film 271f may be formed continuously without being exposed to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the conductive film 242f can be removed, and further, the moisture concentration and hydrogen concentration in the conductive film 242f can be reduced. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower.

[0233] Next, using a lithography method, the insulating film 224f, the oxide semiconductor film 230f, the conductive film 242f, and the insulating film 271f are processed into islands to form the insulator 224, the oxide semiconductor 230, the conductor 242A, and the insulator 271A (see FIGS. 10(A) to 10(D)).

[0234] For the above processing, a dry etching method or a wet etching method can be used. Processing by the dry etching method is suitable for microfabrication. Further, the processing of the insulating film 224f, the oxide semiconductor film 230f, the conductive film 242f, and the insulating film 271f may be performed under different conditions.

[0235] Here, it is preferable to process the insulator 224, the oxide semiconductor 230, the conductor 242A, and the insulator 271A into an island shape all at once. At this time, it is preferable that the side end portion of the conductor 242A coincides with or substantially coincides with the side end portion of the oxide semiconductor 230. Furthermore, it is preferable that the side end portion of the insulator 224 coincides with or substantially coincides with the side end portion of the oxide semiconductor 230. Furthermore, it is preferable that the side end portion of the insulator 271A coincides with or substantially coincides with the side end portion of the conductor 242A. By adopting such a configuration, the number of steps of the semiconductor device according to one aspect of the present invention can be reduced. Therefore, a method for manufacturing a semiconductor device with good productivity can be provided.

[0236] In addition, the insulator 224, the oxide semiconductor 230, the conductor 242A, and the insulator 271A are formed so that at least a part thereof overlaps with the conductor 205. Also, in a region where the insulator 224, the oxide semiconductor 230, the conductor 242A, and the insulator 271A do not overlap, the insulator 222 is exposed. However, it is not limited to this, and in a region where the insulator 224 does not overlap with the oxide semiconductor 230, the insulator 224 may remain on the insulator 222. In this case, like the transistor 200 in FIGS. 4(A) to 4(D), the insulator 224 is not in an island shape but has an opening in part.

[0237] As shown in FIGS. 10(B) to 10(D), the side surfaces of the insulator 224, the oxide semiconductor 230, the conductor 242A, and the insulator 271A may be tapered. The taper angle of the side surfaces of the insulator 224, the oxide semiconductor 230, the conductor 242A, and the insulator 271A may be, for example, 60° or more and less than 90°. By tapering the side surfaces in this way, in subsequent steps, the covering property of the insulator 275 and the like is improved, and defects such as looseness can be reduced.

[0238] In addition, not limited to the above, the side surfaces of the insulator 224, the oxide semiconductor 230, the conductor 242A, and the insulator 271A may be perpendicular or substantially perpendicular to the upper surface of the insulator 222. By adopting such a configuration, when providing a plurality of transistors, it is possible to reduce the area and increase the density.

[0239] In the lithography method, first, the resist is exposed through a mask. Next, the exposed area is removed or left intact using a developer to form a resist mask. Next, by performing an etching process through the resist mask, conductors, semiconductors, insulators, etc. can be processed into a desired shape. For example, a resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, etc. Also, a liquid immersion technique may be used in which a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. Further, instead of the light described above, an electron beam or an ion beam may be used. Note that when using an electron beam or an ion beam, it may not be necessary to use a photomask.

[0240] Note that the resist mask that has become unnecessary after processing can be removed by performing a dry etching process such as ashing using oxygen plasma (hereinafter sometimes referred to as oxygen plasma treatment), performing a wet etching process, performing a wet etching process after a dry etching process, or performing a dry etching process after a wet etching process.

[0241] Furthermore, a hard mask made of an insulator or a conductor may be used under the resist mask. When using a hard mask, an insulating film or a conductive film serving as a hard mask material is formed on the insulating film 271f, a resist mask is formed thereon, and a hard mask having a desired shape can be formed by etching the hard mask material. For example, tungsten may be used as the hard mask material. The etching of the insulating film 271f etc. may be performed after removing the resist mask, or may be performed with the resist mask remaining. In the latter case, the resist mask may disappear during etching. The hard mask may be removed by etching after etching the oxide semiconductor film 230f etc. On the other hand, if the material of the hard mask has no influence on the subsequent process or can be used in the subsequent process, it is not always necessary to remove the hard mask.

[0242] Also, a configuration may be adopted in which an SOC (Spin On Carbon) film and an SOG (Spin On Glass) film are formed between the workpiece and the resist mask. By using the SOC film and the SOG film as masks, the adhesion to the resist mask can be improved, and the durability of the mask pattern can be improved. For example, lithography can be performed by forming an SOC film, an SOG film, and a resist mask in this order on the workpiece.

[0243] As the etching gas for dry etching, an etching gas containing a halogen can be used. Specifically, an etching gas containing one or more of fluorine, chlorine, and bromine can be used. For example, as the etching gas, C4F6 gas, C5F6 gas, C4F8 gas, CF4 gas, SF6 gas, CHF3 gas, CH2F2 gas, Cl2 gas, BCl3 gas, SiCl4 gas, or BBr3 gas, etc. can be used alone or in a mixture of two or more gases. Further, oxygen gas, carbon dioxide gas, nitrogen gas, helium gas, argon gas, hydrogen gas, or hydrocarbon gas, etc. can be appropriately added to the above etching gas. Also, depending on the workpiece to be dry-etched, a gas containing no halogen gas but containing a hydrocarbon gas or hydrogen gas can be used as the etching gas. As the hydrocarbon used in the etching gas, one or more of methane (CH4), ethane (C2H6), propane (C3H8), butane (C4H 10 )), ethylene (C2H4), propylene (C3H6), acetylene (C2H2), and propyne (C3H4) can be used. The etching conditions can be appropriately set according to the object to be etched.

[0244] As the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high-frequency voltage to one of the parallel plate electrodes. Alternatively, it may be configured to apply high-frequency voltages of the same frequency to each of the parallel plate electrodes. Further, it may be configured to apply a plurality of different high-frequency voltages to the parallel plate electrodes. Such a CCP etching apparatus is called a dual frequency capacitively coupled plasma (DF-CCP) etching apparatus. In the DF-CCP etching apparatus, a configuration may be adopted in which high-frequency voltages of different frequencies are applied to each of the parallel plate electrodes. Alternatively, a configuration may be adopted in which a plurality of different high-frequency voltages are applied to one of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. As the dry etching apparatus having a high-density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus or the like can be used. The etching apparatus can be appropriately set according to the object to be etched. In the above dry etching apparatus, reactive ion etching can be performed by applying a high-frequency voltage to the electrode on the substrate side to generate a self-bias potential. In reactive ion etching, etching is performed by accelerating ion species in the plasma and causing them to collide with the workpiece, so that an etching process with high anisotropy can be performed.

[0245] In addition, in the above etching process, the insulator 271A can function as an etching stopper for protecting the conductor 242A. For example, in the above etching process, when a metal hard mask is formed on the insulator 271A, it may be difficult to obtain an etching selectivity with respect to the conductor 242A when removing the hard mask. However, by forming the insulator 271A on the conductor 242A, the insulator 271A can function as an etching stopper for protecting the conductor 242A in the etching process of removing the hard mask. Thereby, it is possible to prevent the formation of a curved surface between the side surface and the upper surface of the conductor 242A. Therefore, as shown in FIG. 1(D), the conductors 242a and 242b to be formed later have a corner-shaped end where the side surface and the upper surface intersect. By making the end where the side surface and the upper surface of the conductor 242A intersect into a corner shape, the cross-sectional area of the conductor 242A becomes larger than when the end has a curved surface. Furthermore, by using a nitride insulator that is difficult to oxidize the metal for the insulator 271A, it is possible to prevent the conductor 242A from being excessively oxidized. As a result, since the resistance of the conductors 242a and 242b is reduced, the on-current of the transistor can be increased.

[0246] Also, by processing the insulator 224 into an island shape, the insulator 275 can be provided in contact with the side surface of the insulator 224 and the upper surface of the insulator 222 in a process described later. That is, the insulator 224 can be separated from the insulator 280 by the insulator 275. With such a configuration, it is possible to prevent excessive amounts of impurities such as oxygen and hydrogen from being mixed into the oxide semiconductor 230 from the insulator 280 through the insulator 224.

[0247] Next, an insulator 275 is formed to cover the insulator 224, the oxide semiconductor 230, the conductor 242A, and the insulator 271A, and then an insulator 280 is formed on the insulator 275 (see FIGS. 11(A) to 11(D)). For the insulator 275 and the insulator 280, the above-described insulating material may be used.

[0248] Here, the insulator 275 preferably contacts the upper surface of the insulator 222.

[0249] As the insulator 280, it is preferable to form an insulating film that becomes the insulator 280 and perform CMP processing on the insulating film to form an insulator with a flat upper surface. Note that, for example, a silicon nitride film may be formed on the insulator 280 by a sputtering method, and CMP processing may be performed until the silicon nitride reaches the insulator 280.

[0250] The insulator 275 and the insulator 280 can each be formed by using, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0251] It is preferable to use an insulator having a function of suppressing oxygen permeation for the insulator 275. For example, it is preferable to form a silicon nitride film as the insulator 275 by using the PEALD method. Alternatively, as the insulator 275, an aluminum oxide film may be formed by using a sputtering method, and a silicon nitride film may be formed thereon by using the PEALD method. By forming the insulator 275 into the above structure, it is possible to improve the function of suppressing the diffusion of impurities such as water and hydrogen and oxygen.

[0252] In this way, the oxide semiconductor 230 and the conductor 242A can be covered with the insulator 275 having a function of suppressing oxygen diffusion. Thereby, in subsequent steps, it is possible to suppress oxygen from directly diffusing from the insulator 280 or the like to the oxide semiconductor 230 and the conductor 242A.

[0253] In addition, as the insulator 280, it is preferable to form a silicon oxide film using a sputtering method. By forming an insulating film to be the insulator 280 in an atmosphere containing oxygen using a sputtering method, an insulator 280 containing excess oxygen can be formed. Also, by using a sputtering method that does not require a molecule containing hydrogen in the film-forming gas, the hydrogen concentration in the insulator 280 can be reduced. Note that a heat treatment may be performed before forming the insulating film. The heat treatment is performed under reduced pressure, and the insulating film may be continuously formed without being exposed to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the insulator 275 or the like can be removed. The above-described heat treatment conditions can be used for the heat treatment.

[0254] Next, using a lithography method, the conductor 242A, the insulator 271A, the insulator 275, and the insulator 280 are processed to form openings reaching the oxide semiconductor 230 and the insulator 222 (see FIGS. 12(A) to 12(D)). Here, the conductor 242A is divided to form the conductor 242a and the conductor 242b, and the insulator 271A is divided to form the insulator 271a and the insulator 271b. The openings formed in the insulator 280 and the insulator 275 overlap the oxide semiconductor 230 and the conductor 205.

[0255] For the lithography method, the above method can be appropriately used. To finely process the opening of the insulator 280, it is preferable to use a lithography method using light with a short wavelength such as EUV light or an electron beam. For example, an opening may be formed in the insulator 280 and the conductor 242a and the conductor 242b may be formed using the method shown in FIGS. 13(A1) to 13(D2).

[0256] First, a coating film 277 is formed on an insulator 280, and then a coating film 278 is further formed (see FIGS. 13(A1) and 13(A2)). The coating film 277 and the coating film 278 may have a function of improving the adhesion between the resist mask described later and the insulator 280. The coating films 277 and 278 may be formed, for example, by using a spin coating method or the like. As the coating films 277 and 278, a non-photosensitive organic resin may be used.

[0257] Here, the coating film 278 functions as a mask in the etching process for processing the coating film 277. Therefore, under the etching conditions of the coating film 277, it is preferable that the etching rate of the coating film 278 is smaller than the etching rate of the coating film 277. For example, the coating film 277 may be a film containing carbon, and the coating film 278 may be a film containing silicon and carbon. In the present embodiment, an SOC film is formed as the coating film 277, and an SOG film is formed as the coating film 278.

[0258] Note that the coating film 277 and the coating film 278 contain an organic solvent such as alcohol during coating, but the contained organic substances may be reduced or removed during subsequent processes or when the semiconductor device is completed. Note that the coating film may be provided as needed. The coating film may be configured as a single layer, or may not be provided if only the resist mask described later is sufficient.

[0259] Next, a resist mask 279 having an opening is formed on the coating film 278 by using a lithography method (see FIGS. 13(A1) and 13(A2)). The resist mask 279 can be formed, for example, by exposing a resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Also, a liquid immersion technique in which a liquid (for example, water) is filled between the substrate and the projection lens for exposure may be used. Further, instead of the light described above, an electron beam or an ion beam may be used. Note that when an electron beam or an ion beam is used, a mask may not be necessary in some cases.

[0260] In the following steps according to FIGS. 13(B1) to 13(D2), it is preferable to process the workpiece using a dry etching method. Since the dry etching method enables anisotropic etching, it is suitable for forming openings with a high aspect ratio. When performing anisotropic etching, for example, it is preferable to perform reactive ion etching. Regarding the conditions of the dry etching method and the dry etching apparatus, reference can be made to the above description. In addition, the steps according to FIGS. 13(B1) to 13(D2) are preferably performed continuously without being exposed to the outside air. For example, using a multi-chamber etching apparatus, the treatment can be performed without being exposed to the outside air.

[0261] First, using the resist mask 279, the coating film 278 is processed to form a coating film 278 having an opening. For example, when using a SOG film for the coating film 278, using a DF-CCP etching apparatus, etching treatment can be performed using CF4 as the etching gas.

[0262] Next, using the coating film 278 as a mask, the coating film 277 is processed to form a coating film 277 having an opening (see FIGS. 13(B1) and 13(B2)). For example, when using a SOC film for the coating film 277, using a DF-CCP etching apparatus, etching treatment can be performed using H2 and N2 as the etching gas. Here, since a SOG film is used for the coating film 278, it is possible to prevent the coating film 278 from disappearing during the etching process of the coating film 277.

[0263] Also, it is preferable to simultaneously remove the resist mask 279 during the processing of the coating film 277. Since a SOC film is used for the coating film 277, the resist mask 279 can be easily removed. In addition, when the resist mask 279 remains after the formation of the coating film 277, it is preferable to remove the resist mask 279.

[0264] Next, using the coating film 277 as a mask, the insulator 280 is processed to form an insulator 280 having an opening. For example, when a silicon oxide film is used for the insulator 280, an etching process can be performed using a DF-CCP etching apparatus with C4F8, C4F6, O2, and Ar as the etching gas.

[0265] Furthermore, using the coating film 277 as a mask, the insulators 275 and 271A are processed to form insulators 275, 271a, and 271b having openings (see FIGS. 13(C1) and 13(C2)). For example, when a silicon oxide film and a silicon nitride film are used for the insulators 275 and 271A, an etching process can be performed using a DF-CCP etching apparatus with CH2F2, O2, and Ar as the etching gas. At this time, the conductors 242A and 222 can function as an etching stopper. Also, it is preferable to simultaneously remove the coating film 278 during the processing of the insulators 275 and 271A.

[0266] After forming the insulators 271a and 271b, it is preferable to perform a dry etching process such as ashing using oxygen plasma to remove the coating film 277. However, it is not limited thereto, and the coating film 277 may be removed after forming the conductors 242a and 242b.

[0267] Next, it is preferable to remove the surface oxide film of the conductor 242A using the insulator 280 as a mask. For example, when a tantalum nitride film is used for the conductor 242A, an etching process can be performed using an ICP etching apparatus with BCl3 and Cl2 as the etching gas.

[0268] Further, using the insulator 280 as a mask, the conductor 242A is processed to form the conductor 242a and the conductor 242b (see FIGS. 13(D1) and 13(D2)). For example, when a tantalum nitride film is used for the conductor 242A, an etching process can be performed using an ICP etching apparatus with Cl2 and Ar as the etching gas. At this time, the oxide semiconductor 230 and the insulator 222 can function as an etching stopper. At this time, as shown in FIG. 13(D2), in a cross-sectional view in the channel width direction of the transistor 200, there may be a curved surface between the side surface and the upper surface of the oxide semiconductor 230. That is, the end of the side surface and the end of the upper surface may be rounded.

[0269] In addition, a recess may be formed in the portion of the oxide semiconductor 230 exposed from the conductor 242a and the conductor 242b. In other words, on the upper surface of the oxide semiconductor 230, the region sandwiched between the conductor 242a and the conductor 242b may be lower in height than the region overlapping the conductor 242a and the region overlapping the conductor 242b.

[0270] As described above, openings can be formed in the insulator 275 and the insulator 280, and the insulator 271a, the insulator 271b, the conductor 242a, and the conductor 242b can be formed.

[0271] Note that, after processing the conductor 242A, an ashing process using oxygen plasma may be performed. By performing such an oxygen plasma treatment, impurities generated by the above etching process and diffused into the oxide semiconductor 230 or the like can be removed. Examples of such impurities include components contained in the workpiece of the above etching process and components contained in the gas used for etching. For example, chlorine, fluorine, tantalum, silicon, hafnium, etc. can be mentioned. By removing the impurities adhering to the oxide semiconductor 230 in this way, the electrical characteristics and reliability of the transistor can be improved.

[0272] In addition, the processing of the conductor 242A and the oxygen plasma treatment can be continuously performed without exposure to the outside air. For example, using an etching apparatus of a multi-chamber system, the treatment may be performed without exposure to the outside air.

[0273] In addition, in order to remove impurities and the like adhering to the surface of the oxide semiconductor 230 in the etching step, it is preferable to perform a cleaning treatment. Examples of the cleaning method include wet cleaning using a cleaning solution or the like (which may also be referred to as wet etching treatment), plasma treatment using plasma, and cleaning by heat treatment. The above cleaning may be appropriately combined. Note that the recess may become deeper by the cleaning treatment.

[0274] The wet cleaning may be performed using an aqueous solution in which one or more of oxalic acid, phosphoric acid, and hydrofluoric acid are diluted with carbonated water or pure water. The wet cleaning may also be performed using an aqueous solution in which aqueous ammonia is diluted with carbonated water or pure water. The wet cleaning may also be performed using pure water or carbonated water. Alternatively, ultrasonic cleaning using these aqueous solutions, pure water, or carbonated water may be performed. Alternatively, these cleanings may be appropriately combined.

[0275] In this specification and the like, an aqueous solution in which hydrofluoric acid is diluted with pure water may be referred to as diluted hydrofluoric acid, and an aqueous solution in which aqueous ammonia is diluted with pure water may be referred to as diluted aqueous ammonia. In addition, the concentration, temperature, etc. of the aqueous solution are appropriately adjusted according to the impurities to be removed, the configuration of the semiconductor device to be cleaned, and the like. The ammonia concentration of the diluted aqueous ammonia is preferably 0.01% or more and 5% or less, and more preferably 0.1% or more and 0.5% or less. The hydrogen fluoride concentration of the diluted hydrofluoric acid is preferably 0.01 ppm or more and 100 ppm or less, and more preferably 0.1 ppm or more and 10 ppm or less.

[0276] Note that for ultrasonic cleaning, it is preferable to use a frequency of 200 kHz or more, and more preferably 900 kHz or more. By using the frequency, damage to the oxide semiconductor 230 or the like can be reduced.

[0277] Also, the above cleaning process may be performed multiple times, and the cleaning liquid may be changed for each cleaning process. For example, as the first cleaning process, a process using diluted hydrofluoric acid or diluted aqueous ammonia may be performed, and as the second cleaning process, a process using pure water or carbonated water may be performed.

[0278] In this embodiment, as the above cleaning process, wet cleaning is performed using carbonated water. By performing such a cleaning process, impurities attached to the surface or diffused inside the oxide semiconductor 230 can be removed. Further, the surface layer of the oxide semiconductor 230 damaged by the above etching process can also be removed.

[0279] It is preferable to perform a heat treatment after the above etching or after the above cleaning. The temperature of the heat treatment is 100°C or higher and 650°C or lower, preferably 250°C or higher and 600°C or lower, more preferably 300°C or higher and 550°C or lower, and even more preferably 350°C or higher and 400°C or lower. The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. The heat treatment is preferably performed in an atmosphere containing oxygen. For example, it is preferable to perform a treatment at a temperature of 350°C for 1 hour with a flow rate ratio of nitrogen gas to oxygen gas of 4:1. Thereby, oxygen can be supplied to the oxide semiconductor 230 to reduce oxygen deficiency. Further, by performing such a heat treatment, the crystallinity of the oxide semiconductor 230 can be improved. Furthermore, the oxygen supplied to the hydrogen remaining in the oxide semiconductor 230 reacts, so that the hydrogen can be removed (dehydrated) as H2O. As a result, the hydrogen remaining in the oxide semiconductor 230 recombines with the oxygen deficiency to form V OThe formation of H can be suppressed. Therefore, the electrical characteristics of the transistor provided with the oxide semiconductor 230 can be improved, and the reliability can be enhanced. In addition, variations in the electrical characteristics of transistors formed in a plurality on the same substrate can be suppressed. Note that the heat treatment may be performed under a reduced pressure state. Alternatively, after heat treatment in an oxygen atmosphere, heat treatment may be continuously performed in a nitrogen atmosphere without being exposed to the air. Further, by performing the heat treatment, the heat treatment after the formation of the oxide semiconductor film 230f can be also served as. Therefore, the crystal region of the oxide semiconductor 230 may grow by the heat treatment.

[0280] Note that when the heat treatment is performed with the conductor 242a and the conductor 242b in contact with the oxide semiconductor 230, the sheet resistance may decrease in the region of the oxide semiconductor 230 that overlaps with the conductor 242a and in the region that overlaps with the conductor 242b, respectively. In addition, the carrier concentration may increase. Therefore, the regions of the oxide semiconductor 230 that overlap with the conductor 242a and with the conductor 242b can be self-alignedly made to have a lower resistance.

[0281] For example, as shown in FIG. 2(A), even if the oxide semiconductor 230 has a stacked structure and a metal oxide having relatively low conductivity or a metal oxide having a large band gap is used for the oxide semiconductor 230c, the regions of the oxide semiconductor 230 that overlap with the conductor 242a and with the conductor 242b can be made to have a lower resistance as described above. Thereby, a source region and a drain region can be formed in the oxide semiconductor 230c.

[0282] Next, an insulating film 250f serving as the insulator 250 is formed so as to cover the opening formed in the insulator 280 or the like (see FIGS. 14(A) to 14(D)). Here, the insulating film 250f is formed along the openings of the insulator 280 and the insulator 275. The insulating film 250f is in contact with the insulator 280, the conductor 242a, the conductor 242b, the insulator 222, the insulator 224, and the oxide semiconductor 230.

[0283] The insulating film 250f can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. For example, it is preferable to form the insulating film 250f using the ALD method. The insulating film 250f is preferably formed with a thin film thickness, and it is necessary to reduce the variation in the film thickness. On the other hand, the ALD method is a film formation method in which a precursor and a reactant (such as an oxidizing agent) are alternately introduced, and the film thickness can be adjusted by the number of times this cycle is repeated, so precise film thickness adjustment is possible. Also, the insulating film 250f needs to be formed with good coverage on the bottom surface and side surfaces of the above opening. By using the ALD method, atomic layers can be deposited one by one on the bottom surface and side surfaces of the above opening, so the insulating film 250f can be formed with good coverage for the opening.

[0284] Also, when forming the insulating film 250f by the ALD method, ozone (O3), oxygen (O2), water (H2O), etc. can be used as the oxidizing agent. By using ozone (O3), oxygen (O2), etc. that do not contain hydrogen as the oxidizing agent, the hydrogen diffusing into the oxide semiconductor 230 can be reduced.

[0285] The insulator 250 can have a laminated structure as shown in FIG. 2(B) etc. Hereinafter, similar to FIG. 2(B), the method for forming the insulating film 250f when the insulator 250 has a four-layer structure of the insulator 250a, the insulator 250b, the insulator 250d, and the insulator 250c will be described.

[0286] First, a film to be the insulator 250a is formed so as to cover the opening formed in the insulator 280 etc., and then a film to be the insulator 250b is formed on the film to be the insulator 250a. In the present embodiment, aluminum oxide is formed as the film to be the insulator 250a by the thermal ALD method, and silicon oxide is formed as the film to be the insulator 250b by the PEALD method.

[0287] Next, it is preferable to perform microwave treatment in an oxygen-containing atmosphere. Here, the microwave treatment refers to a treatment using, for example, a device having a power source for generating high-density plasma using microwaves. Also, in this specification and the like, microwaves are defined as electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.

[0288] In the microwave treatment, it is preferable to use a microwave treatment device having a power source for generating high-density plasma using microwaves. Here, the frequency of the microwave treatment device is preferably 300 MHz or more and 300 GHz or less, more preferably 2.4 GHz or more and 2.5 GHz or less, and can be, for example, 2.45 GHz. By using high-density plasma, high-density oxygen radicals can be generated. Also, the power of the power source for applying microwaves to the microwave treatment device is preferably 1000 W or more and 10000 W or less, more preferably 2000 W or more and 5000 W or less. Further, the microwave treatment device may have a power source for applying RF to the substrate side. Also, by applying RF to the substrate side, oxygen ions generated by high-density plasma can be efficiently introduced into the oxide semiconductor 230.

[0289] Also, the above-mentioned microwave treatment is preferably performed under reduced pressure, and the pressure is preferably 10 Pa or more and 1000 Pa or less, more preferably 300 Pa or more and 700 Pa or less. Also, the treatment temperature is preferably 750 °C or less, more preferably 500 °C or less, and can be, for example, about 250 °C. Also, after performing the oxygen plasma treatment, heat treatment may be continuously performed without exposing to the outside air. The temperature of the heat treatment is preferably, for example, 100 °C or more and 750 °C or less, more preferably 300 °C or more and 500 °C or less.

[0290] Also, for example, the microwave treatment can be performed using oxygen gas and argon gas. Here, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 0% and less than 100%. Preferably, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 0% and less than 50%. More preferably, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 10% and less than 40%. Still more preferably, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 10% and less than 30%. In this way, by performing the microwave treatment in an atmosphere containing oxygen, the carrier concentration of the region exposed from the opening of the oxide semiconductor 230 can be reduced. Also, by preventing an excessive amount of oxygen from being introduced into the chamber in the microwave treatment, the carrier concentration of the oxide semiconductor 230 can be prevented from being excessively reduced.

[0291] By performing microwave treatment in an atmosphere containing oxygen, oxygen gas can be turned into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be applied to the region between the conductor 242a and the conductor 242b of the oxide semiconductor 230. The action of the plasma, microwaves, etc. can reduce the V O H can be split into oxygen vacancies and hydrogen, and the hydrogen can be removed from the region. When using the structure shown in FIG. 2B, it is preferable to use an insulating film (such as aluminum oxide) that has the function of capturing or fixing hydrogen as the film that becomes the insulator 250a. With this structure, hydrogen generated by microwave treatment can be captured or fixed in the film that becomes the insulator 250a. In this way, V included in the channel formation region can be removed. O As a result, oxygen vacancies in the channel formation region and V O By supplying oxygen radicals generated by the oxygen plasma to the oxygen vacancies formed in the channel formation region, the oxygen vacancies in the channel formation region can be further reduced, and the carrier concentration can be reduced.

[0292] The oxygen injected into the channel formation region exists in various forms such as oxygen atoms, oxygen molecules, oxygen ions, and oxygen radicals (also referred to as O radicals, atoms, molecules, or ions with unpaired electrons). Note that the oxygen injected into the channel formation region may be any one or more of the above-mentioned forms, and it is particularly preferable that it is an oxygen radical. In addition, since the film quality of the insulator 250 can be improved, the reliability of the transistor is improved.

[0293] On the other hand, in the oxide semiconductor 230, there is a region that overlaps with either the conductor 242a or the conductor 242b. This region can function as a source region or a drain region. Here, the conductors 242a and 242b preferably function as a shielding film against the action of microwaves, high-frequency waves such as RF, and oxygen plasma when performing microwave treatment in an oxygen-containing atmosphere. For this reason, the conductors 242a and 242b preferably have a function of shielding electromagnetic waves of 300 MHz or more and 300 GHz or less, for example, 2.4 GHz or more and 2.5 GHz or less.

[0294] Since the conductors 242a and 242b shield the action of microwaves or high-frequency waves such as RF and oxygen plasma, these actions do not reach the region that overlaps with either the conductor 242a or the conductor 242b of the oxide semiconductor 230. As a result, by microwave treatment, in the source region and the drain region, the reduction of V O H and the supply of an excessive amount of oxygen do not occur, so that a decrease in carrier concentration can be prevented.

[0295] As described above, oxygen deficiency and V O H can be selectively removed in the channel formation region of the oxide semiconductor, and the channel formation region can be made into an i-type or substantially i-type. Furthermore, the supply of excessive oxygen to the region functioning as the source region or the drain region can be suppressed, and the conductivity (the state of a low-resistance region) before performing microwave treatment can be maintained. Thereby, the variation in the electrical characteristics of the transistor can be suppressed, and the variation in the electrical characteristics of the transistor within the substrate surface can be suppressed.

[0296] In addition, by performing microwave treatment to modify the film quality of the film that becomes the insulator 250a and the film that becomes the insulator 250b, diffusion of hydrogen, water, impurities, etc. can be suppressed. Therefore, in a subsequent process such as forming a conductive film that becomes the conductor 260, or in a post-treatment such as heat treatment, diffusion of hydrogen, water, impurities, etc. into the oxide semiconductor 230 or the like through the insulator 250 can be suppressed. Thus, by improving the film quality of the insulator 250, the reliability of the transistor can be improved.

[0297] Next, a film that becomes the insulator 250d is formed on the film that becomes the insulator 250b. In the present embodiment, hafnium oxide is formed as the film that becomes the insulator 250d by thermal ALD method. Also, the film that becomes the insulator 250d can be configured to be formed of hafnium zirconium oxide by thermal ALD method. Note that microwave treatment may be performed again after the formation of the film that becomes the insulator 250d.

[0298] Next, a film that becomes the insulator 250c is formed on the film that becomes the insulator 250d. In the present embodiment, silicon nitride is formed as the film that becomes the insulator 250c by PEALD method. In this way, an insulating film 250f having the film that becomes the insulator 250a to the film that becomes the insulator 250d can be formed.

[0299] Note that in the above, an example in which microwave treatment is performed after forming the film that becomes the insulator 250b and after forming the film that becomes the insulator 250d has been shown, but the present invention is not limited to this. A configuration in which microwave treatment is performed after forming the film that becomes the insulator 250c can also be adopted. Or, a configuration in which microwave treatment is performed before forming the film that becomes the insulator 250a can also be adopted. Also, a configuration in which microwave treatment is performed three or more times may be adopted. Also, in some cases, the microwave treatment described above can also serve as the heat treatment shown in Embodiment 2. Therefore, the crystal region of the oxide semiconductor 230 may grow by the above microwave treatment.

[0300] Also, heat treatment may be performed while maintaining a reduced pressure state after the microwave treatment. By performing such treatment, hydrogen in the insulating film and in the oxide semiconductor 230 can be efficiently removed. Alternatively, the step of performing heat treatment may be repeated a plurality of times while maintaining a reduced pressure state after the microwave treatment. By repeatedly performing heat treatment, hydrogen in the insulating film and in the oxide semiconductor 230 can be removed more efficiently. Note that the heat treatment temperature is preferably 300°C or higher and 500°C or lower. Further, the heat treatment described above can also serve as the heat treatment shown in Embodiment 2. Therefore, the crystal region of the oxide semiconductor 230 may grow by the above heat treatment.

[0301] Next, a conductive film 260f to be the conductor 260 is formed (see FIGS. 14(A) to 14(D)). The conductive film 260f can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, a plating method, or an ALD method using the above-described conductive material. For example, a titanium nitride film and a tungsten film may be laminated and formed using the CVD method. As shown in FIG. 2(A), the conductor 260 can have a laminated structure of a titanium nitride conductor 260a and a tungsten conductor 260b. Note that the formation of the conductive film 260f may be performed while heating the substrate. By heating the substrate, the heat treatment shown in Embodiment 2 can also be achieved. Therefore, the crystal region of the oxide semiconductor 230 may grow by the above substrate heating.

[0302] Next, by CMP treatment, the insulating film 250f and the conductive film 260f are polished until the insulator 280 is exposed. That is, the portions of the insulating film 250f and the conductive film 260f exposed from the above opening are removed. Thereby, the insulator 250 and the conductor 260 (conductor 260a and conductor 260b) are formed in the opening overlapping with the conductor 205 (see FIGS. 15(A) to 15(D)).

[0303] As a result, the insulator 250 is provided in contact with the conductor 242a, the conductor 242b, the oxide semiconductor 230, the insulator 224, and the insulator 222 within the above-described opening. Further, the conductor 260 is disposed so as to fill the above-described opening via the insulator 250. In this way, the transistor 200 is formed.

[0304] Next, an insulator 282 is formed on the insulator 250, on the conductor 260, and on the insulator 280 (see FIGS. 16(A) to 16(D)). The insulator 282 can be formed, for example, by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The formation of the insulator 282 is preferably performed by a sputtering method. By using a sputtering method that does not require a molecule containing hydrogen as a film formation gas, the hydrogen concentration in the insulator 282 can be reduced.

[0305] Also, as shown in FIG. 2(A), it is preferable that the insulator 282 has a laminated structure of an insulator 282a and an insulator 282b. Here, the insulator 282a is preferably formed by an ALD method, and the formation of the insulator 282b is preferably performed by a sputtering method.

[0306] In the present embodiment, aluminum oxide may be formed as the insulator 282a by using a thermal ALD method. Here, the film thickness of the insulator 282a may be 1 nm or more and 20 nm or less, preferably 3 nm or more and 10 nm or less.

[0307] By forming the insulator 282a by an ALD method, the insulator 282a can be formed without causing excessive damage to the surface to be formed. Therefore, it is possible to prevent excessive damage from being formed on the upper end portion of the insulator 250 and the upper surface of the conductor 260, and thus it is possible to improve the electrical characteristics and reliability of the transistor 200.

[0308] In addition, by forming the insulator 282a by ALD method, the insulator 282a can be formed without adding oxygen to the insulator 280. Thereby, it is possible to prevent an excessive amount of oxygen from being added to the insulator 280. Therefore, the electrical characteristics and reliability of the transistor 200 can be improved.

[0309] In the present embodiment, as the insulator 282b, aluminum oxide may be formed by a sputtering method. By using a sputtering method that does not require a molecule containing hydrogen in the film-forming gas, the hydrogen concentration in the insulator 282 can be reduced.

[0310] Here, by forming the insulator 282b in an atmosphere containing oxygen using a sputtering method, oxygen can be added to the insulator 280 while forming the film. Thereby, the insulator 280 can contain excess oxygen. At this time, it is preferable to form the insulator 282b while heating the substrate. Here, by forming the insulator 282b on the insulator 282a, oxygen is added through the insulator 282a, so that the amount of oxygen injected into the insulator 280 can be controlled. If the film thickness of the insulator 282a is thick, the addition of the above oxygen is likely to be inhibited, and the amount of oxygen injected into the insulator 280 decreases. If the film thickness of the insulator 282a is thin, the addition of the above oxygen is less likely to be inhibited, and the amount of oxygen injected into the insulator 280 increases. For example, by setting the film thickness of the insulator 282a within the above range, a sufficient amount of oxygen can be supplied to the oxide semiconductor 230, and an excessive amount of oxygen can be prevented from being supplied to the oxide semiconductor 230. Thereby, the electrical characteristics and reliability of the transistor 200 can be improved. Note that when forming the insulator 282b as described above, oxygen can be added not only to the insulator 280 but also to the upper end portion of the insulator 250.

[0311] In addition, by forming the insulator 282b on the insulator 282a, the upper end portion of the insulator 250 and the upper surface of the conductor 260 can be protected from the impact of ion collision due to the sputtering film formation of the insulator 282b.

[0312] The formation of aluminum oxide film is carried out using an aluminum target in an atmosphere containing oxygen gas. The amount of oxygen injected into the insulator 280 can be controlled by the magnitude of the bias power applied to the substrate by the sputtering method. For example, the smaller the bias power, the less the amount of oxygen injected into the insulator 280, and even if the film thickness of the insulator 282b is thin, the amount of oxygen is likely to saturate. Also, the larger the bias power, the more the amount of oxygen injected into the insulator 280. By reducing the bias power, the amount of oxygen injected into the insulator 280 can be suppressed. When the substrate bias is applied by an RF power supply, the frequency of the RF is preferably 10 MHz or more. Typically, it is 13.56 MHz. The higher the frequency of the RF, the smaller the damage to the substrate can be.

[0313] Also, before forming the insulator 282b, heat treatment may be performed. The heat treatment is carried out under reduced pressure, and the insulator 282b may be continuously formed without being exposed to the atmosphere. By performing such a treatment, the moisture and hydrogen adsorbed on the surface of the insulator 280 can be captured or fixed to the insulator 282a, and the moisture concentration and hydrogen concentration in the insulator 280 can be reduced. The temperature of the heat treatment is preferably 100°C or more and 400°C or less. In the present embodiment, the temperature of the heat treatment is 250°C.

[0314] Next, an insulator 283 is formed on the insulator 282 (see FIGS. 16(A) to 16(D)). The insulator 283 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The formation of the insulator 283 is preferably carried out using the sputtering method. By using a sputtering method that does not require a molecule containing hydrogen in the film-forming gas, the hydrogen concentration in the insulator 283 can be reduced. In the present embodiment, as the insulator 283, silicon nitride is formed using the sputtering method.

[0315] In this embodiment, silicon nitride is formed as the insulator 283 by using a sputtering method, and aluminum oxide is formed as the insulator 282 by using a thermal ALD method and a sputtering method. In this way, by using silicon nitride having a function of suppressing the diffusion of hydrogen for the insulator 283, it is possible to suppress the diffusion of hydrogen from the upper layer of the transistor 200. Further, by using aluminum oxide having a function of capturing or fixing hydrogen for the insulator 282, the hydrogen contained in the insulator 280 or the like can be captured or fixed by the insulator 282. Thereby, the hydrogen concentration in the oxide semiconductor 230 and its vicinity can be reduced.

[0316] Next, an insulator 285 is formed on the insulator 283 (see FIGS. 16(A) to 16(D)). The insulator 285 can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. It is preferable to form the insulator 285 by using a sputtering method. By using a sputtering method that does not require a molecule containing hydrogen as a film-forming gas, the hydrogen concentration in the insulator 285 can be reduced. In this embodiment, silicon oxide is formed as the insulator 285 by using a sputtering method.

[0317] Here, it is preferable that the insulator 282, the insulator 283, and the insulator 285 are continuously formed by a sputtering method without being exposed to an air environment. By forming the film without opening to the air, it is possible to prevent impurities or moisture from the air environment from adhering to the insulator 282, the insulator 283, and the insulator 285, and to keep the vicinity of the interface between the insulator 282 and the insulator 283 and the vicinity of the interface between the insulator 283 and the insulator 285 clean.

[0318] Next, openings reaching the conductor 242a are formed in the insulator 271a, the insulator 275, the insulator 280, the insulator 282, the insulator 283, and the insulator 285, and openings reaching the conductor 242b are formed in the insulator 271b, the insulator 275, the insulator 280, the insulator 282, the insulator 283, and the insulator 285. The formation of the openings may be performed using a lithography method. In the formation of the openings, it is preferable to process the workpiece using a dry etching method. Since the dry etching method enables anisotropic etching, it is suitable for forming openings with a high aspect ratio. When performing anisotropic etching, for example, it is preferable to perform reactive ion etching. Note that for the conditions of the dry etching method and the dry etching apparatus, reference can be made to the above description. Note that the shape of the opening in a top view can be a circular shape, a substantially circular shape such as an ellipse, a polygonal shape such as a quadrangle, a shape in which the corners of a polygon such as a quadrangle are rounded, or the like.

[0319] Next, after the formation of the above openings, a heat treatment is performed. The temperature of the heat treatment may be 100°C or higher and 600°C or lower, preferably 250°C or higher and 550°C or lower, more preferably 350°C or higher and 450°C or lower. Note that the heat treatment is preferably performed in an atmosphere of nitrogen gas or an inert gas. Further, since the heat treatment is performed with the conductors 242a and 242b exposed, it is preferably performed in an atmosphere that does not contain an oxidizing gas and oxygen gas. For example, it is preferable to perform a heat treatment at a temperature of 400°C for 1 hour in a nitrogen gas atmosphere. Note that the above heat treatment may be performed under reduced pressure. By the above heat treatment, oxygen contained in the insulator 280 can be supplied to the oxide semiconductor 230 via the insulator 250. Thereby, oxygen deficiency in the channel formation region of the oxide semiconductor 230 can be reduced. Further, by the above heat treatment, the heat treatment shown in Embodiment 2 can be also served as. Therefore, the crystal region of the oxide semiconductor 230 may grow by the above heat treatment.

[0320] Here, since the side surface of the insulator 280 is exposed in the above opening, oxygen contained in the insulator 280 can be diffused outward by the above heat treatment to control the amount of oxygen contained in the insulator 280. On the other hand, since the insulators 282 and 283 having barrier properties against oxygen are provided on the insulator 280, oxygen does not diffuse outward from the upper surface of the insulator 280. Thereby, it is possible to prevent excessive outward diffusion of oxygen from the insulator 280 and the formation of oxygen vacancies in the insulator 280. Further, the oxide semiconductor 230, the conductor 242a, and the conductor 242b are covered with the insulator 275. Thereby, it is possible to prevent an excessive amount of oxygen from directly diffusing from the insulator 280 to the oxide semiconductor 230, the conductor 242a, and the conductor 242b during the above heat treatment.

[0321] As described above, in the film formation of the insulator 282b, by adding oxygen to the insulator 280 through the insulator 282a, the amount of oxygen added to the insulator 280 can be controlled. Further, by diffusing oxygen outward from the side surface of the insulator 280 in the above heat treatment, the amount of oxygen in the insulator 280 can be made more suitable. In this way, by supplying oxygen from the insulator 280 with the adjusted oxygen amount to the oxide semiconductor 230, a suitable amount of oxygen can be supplied to the oxide semiconductor 230. Thereby, oxygen vacancies in the oxide semiconductor 230 can be reduced, and it is possible to prevent an excessive amount of oxygen from being supplied to the oxide semiconductor 230. Therefore, the electrical characteristics and reliability of the transistor 200 can be improved. Further, since the step of exposing the side surface of the insulator 280 can be combined with the step of forming the opening for embedding the conductors 240a and 240b, the manufacturing process of the semiconductor device can be simplified.

[0322] Also, by performing the above heat treatment, hydrogen contained in the insulator 280, the insulator 250, and the oxide semiconductor 230 moves to the insulator 282 and is trapped therein. In other words, hydrogen contained in the insulator 280, the insulator 250, and the oxide semiconductor 230 diffuses into the insulator 282. Therefore, the hydrogen concentration of the insulator 282 increases, while the hydrogen concentrations of the insulator 280, the insulator 250, and the oxide semiconductor 230 respectively decrease. By providing the insulator 283 in contact with the upper surface of the insulator 282, it is possible to prevent impurities such as moisture or hydrogen from entering from above the insulator 283 in the heat treatment. Also, by performing the heat treatment, hydrogen contained in the insulator 216, the insulator 224, and the oxide semiconductor 230 moves to the insulator 222 and is trapped therein. In other words, hydrogen contained in the insulator 216, the insulator 224, and the oxide semiconductor 230 diffuses into the insulator 222. Therefore, the hydrogen concentration of the insulator 222 increases, while the hydrogen concentrations in the insulator 216, the insulator 224, and the oxide semiconductor 230 respectively decrease. By providing the insulator 221 in contact with the lower surface of the insulator 222, it is possible to prevent impurities such as moisture or hydrogen from entering from below the insulator 221 in the heat treatment.

[0323] Next, an insulating film that becomes the insulator 241a and the insulator 241b is formed along the shape of the above opening. The formation of the insulating film can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Since the insulating film that becomes the insulator 241a and the insulator 241b is formed in an opening with a large aspect ratio, it is preferable to form the film using the ALD method. Also, as the insulating film that becomes the insulator 241a and the insulator 241b, it is preferable to use an insulating film having a function of suppressing oxygen permeation. For example, it is preferable to form a silicon nitride film using the PEALD method. Silicon nitride is preferable because it has a high blocking property against hydrogen.

[0324] Next, the insulating film is anisotropically etched to form insulator 241a and insulator 241b. Here, insulator 241a is formed to cover the sidewall of the opening on conductor 242a, and insulator 241b is formed to cover the sidewall of the opening on conductor 242b. As the anisotropic etching of the insulating film to become insulator 241a and insulator 241b, a dry etching method or the like may be used. For example, it is preferable to perform reactive ion etching. By providing insulator 241a and insulator 241b on the sidewall portion of the opening, permeation of oxygen from the outside can be suppressed, and oxidation of conductor 240a and conductor 240b to be formed next can be prevented. Also, diffusion of impurities such as water and hydrogen contained in insulator 280 or the like into conductor 240a and conductor 240b can be prevented. Note that, due to the anisotropic etching, recesses may be formed in a part of the upper surface of conductor 242a and conductor 242b.

[0325] Next, a conductive film to become conductor 240a and conductor 240b is formed. It is desirable that the conductive film has a laminated structure including a conductor having a function of suppressing permeation of impurities such as water and hydrogen. For example, it can be a laminate of tantalum nitride, titanium nitride, etc. and tungsten, molybdenum, copper, etc. The formation of the conductive film to become conductor 240a and conductor 240b can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0326] Next, by performing CMP processing, a part of the conductive film to become conductor 240a and conductor 240b is removed, and the upper surface of insulator 285 is exposed. As a result, conductors 240a and 240b having a flat upper surface can be formed by the remaining conductive film only in the opening (see FIGS. 1(A) to 1(D)). Note that, due to the CMP processing, a part of the upper surface of insulator 285 may be removed.

[0327] Further, heat treatment may be performed after forming the conductors 240a and 240b. The same conditions as the above heat treatment can be used for the heat treatment. By performing the heat treatment, the amount of oxygen supplied to the oxide semiconductor 230 can be adjusted. Thereby, the electrical characteristics and reliability of the transistor 200 can be improved.

[0328] As described above, the semiconductor device shown in FIGS. 1(A) to 1(D) can be manufactured.

[0329] The semiconductor device according to the present embodiment includes an OS transistor. In the present embodiment, by using indium oxide (for example, indium oxide, indium gallium oxide, indium zinc oxide, indium gallium zinc oxide, or indium gallium tin zinc oxide, etc.) as the oxide semiconductor layer of the OS transistor, a semiconductor device with high field-effect mobility can be provided. For example, the electrical characteristics, on-current, S value, frequency characteristics, etc. of the transistor can be improved. In addition, a highly reliable semiconductor device can be provided.

[0330] The present embodiment can be appropriately combined with other embodiments. Further, in this specification, when a plurality of configuration examples are shown in one embodiment, the configuration examples can be appropriately combined.

[0331] (Embodiment 2) In the present embodiment, an oxide semiconductor that can be used as the semiconductor layer of the transistor will be described. As the oxide semiconductor according to one aspect of the present invention, a layer containing a metal oxide can be used singly or in a stacked manner. In the case of an oxide semiconductor having a stacked structure, as will be described later, it may be difficult to confirm the boundary between the stacked films.

[0332] [Metal Oxide] The metal oxide according to one aspect of the present invention preferably contains at least indium (In) or zinc (Zn), and particularly preferably contains indium as a main component. Further, the metal oxide preferably has two or three selected from indium, element M, and zinc, and particularly preferably contains indium and zinc as main components. Here, the metal oxide can contain indium and zinc as main components and further have element M. Note that element M is a metal element or a metalloid element having a high binding energy with oxygen, for example, a metal element or a metalloid element having a higher binding energy with oxygen than indium. Specifically, examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably any one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably one or more selected from gallium and tin. When the element M contained in the metal oxide is gallium, the metal oxide according to one aspect of the present invention preferably has any one or more selected from indium, gallium, and zinc. In this specification and the like, a metal element and a metalloid element may be collectively referred to as a "metal element", and the "metal element" described in this specification and the like may include a metalloid element.

[0333] As the metal oxide according to one aspect of the present invention, for example, indium zinc oxide (also referred to as In-Zn oxide, IZO (registered trademark)), indium tin oxide (also referred to as In-Sn oxide, ITO), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (also referred to as In-Ga-Sn oxide, IGTO), indium aluminum zinc oxide (also referred to as In-Al-Zn oxide, IAZO), indium tin zinc oxide (also referred to as In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (also referred to as In-Ga-Zn oxide, IGZO), indium tin oxide containing silicon oxide (ITSO), indium gallium tin zinc oxide (also referred to as In-Ga-Sn-Zn oxide, IGZTO), indium gallium aluminum zinc oxide (also referred to as In-Ga-Al-Zn oxide, IGAZO or IAGZO), etc. can be used. Or, gallium zinc oxide (also referred to as Ga-Zn oxide, GZO), aluminum zinc oxide (also referred to as Al-Zn oxide, AZO), gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc. can be used. Further, indium oxide can be used as the metal oxide according to one aspect of the present invention. Further, gallium oxide, zinc oxide, etc. can be used as the metal oxide according to one aspect of the present invention.

[0334] By increasing the indium content in the metal oxide, the transistor can obtain a large on-current and high frequency characteristics.

[0335] In addition, the metal oxide may contain one or more kinds of metal elements with a large periodic number in the periodic table instead of indium. Alternatively, the metal oxide may contain one or more kinds of metal elements with a large periodic number in the periodic table in addition to indium. The greater the overlap of the orbits of the metal elements, the greater the tendency for carrier conduction in the metal oxide. Therefore, including a metal element with a large periodic number in the periodic table may increase the field-effect mobility of the transistor. Examples of the metal element with a large periodic number in the periodic table include metal elements belonging to the fifth period and metal elements belonging to the sixth period. Specifically, examples of the metal element include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0336] In addition, the metal oxide may contain one or more kinds of non-metal elements. Having non-metal elements in the metal oxide may increase the field-effect mobility of the transistor. Examples of the non-metal element include, for example, carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0337] In addition, by increasing the zinc content in the metal oxide, a highly crystalline metal oxide can be obtained, and the diffusion of impurities in the metal oxide can be suppressed. Therefore, fluctuations in the electrical characteristics of the transistor can be suppressed, and the reliability can be improved.

[0338] In addition, by increasing the content of element M in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-current can be obtained. In addition, fluctuations in the electrical characteristics of the transistor can be suppressed, and the reliability can be improved.

[0339] An example of the structure of an oxide semiconductor capable of increasing the field-effect mobility of a transistor will be described. For example, it is preferable to use a stacked structure of indium oxide and IGZO. Specifically, the oxide semiconductor preferably has indium oxide and IGZO on the indium oxide. Further, as the oxide semiconductor, it is preferable to use IGZO containing nitrogen. For example, by performing N2O plasma treatment during or after film formation, IGZO containing nitrogen can be formed. Further, as the oxide semiconductor, it is preferable to use at least one of indium oxide, In-Ga oxide, In-Zn oxide, and IGZTO.

[0340] In this embodiment, as the metal oxide, there may be a case where an In-M-Zn oxide is taken as an example for explanation.

[0341] The oxide semiconductor according to one aspect of the present invention preferably has a crystalline metal oxide. Examples of the structure of the crystalline metal oxide include a CAAC (c-axis aligned crystal) structure, a poly-crystal structure, and a nano-crystal structure. By using a crystalline metal oxide for the oxide semiconductor, the density of defect levels in the oxide semiconductor can be reduced. Therefore, the reliability of a transistor using the oxide semiconductor according to one aspect of the present invention can be improved, and the reliability of a semiconductor device on which the transistor is mounted can be improved.

[0342] Note that the crystallinity of the metal oxide included in the oxide semiconductor is not particularly limited. For example, the oxide semiconductor may include one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single crystal semiconductor (a semiconductor having a single crystal structure), or a semiconductor having crystallinity other than a single crystal (a nano-crystal semiconductor, a poly-crystal semiconductor, or a semiconductor having a crystal region in part). When the oxide semiconductor has crystallinity, deterioration of transistor characteristics may be suppressed.

[0343] The crystallinity of the oxide semiconductor can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, analysis may be performed by combining a plurality of these techniques.

[0344] The oxide semiconductor according to one embodiment of the present invention preferably has a metal oxide having a CAAC structure. The CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) have c-axis orientation and, in the a-b plane, the plurality of microcrystals are connected without orientation. Further, when observing the cross section of the oxide semiconductor having a CAAC structure using a high-resolution TEM image (also referred to as a multi-wave interference image), it can be confirmed that metal atoms are arranged in layers in the crystal portion. Therefore, it can be said that the oxide semiconductor having a CAAC structure also has a layered crystal portion.

[0345] The CAAC structure is formed, for example, such that the c-axis is perpendicular or substantially perpendicular to the surface to be formed or the surface of the oxide semiconductor. In the CAAC structure, metal atoms are arranged in layers in a direction parallel or substantially parallel to the surface to be formed. In a region having a CAAC structure, the c-axis is preferably within 90° ± 20° (70° or more and 110° or less), more preferably within 90° ± 15° (75° or more and 105° or less), more preferably within 90° ± 10° (80° or more and 100° or less), and still more preferably within 90° ± 5° (85° or more and 95° or less) with respect to the surface to be formed.

[0346] When the oxide semiconductor has a CAAC structure, in the cross section of the oxide semiconductor observed using a TEM image, a group of bright spots (specifically, bright spots arranged in layers) reflecting the layered arrangement of metal atoms is observed. Specifically, a state in which bright spots are arranged in layers in a direction parallel or substantially parallel to the surface to be formed is observed.

[0347] When electron diffraction is performed on an oxide semiconductor having a CAAC structure, spots (bright spots) showing c-axis orientation are observed in the electron diffraction pattern.

[0348] In addition, the FFT pattern obtained by performing fast Fourier transform (FFT) processing on the TEM image reflects the same reciprocal lattice space information as the electron diffraction pattern.

[0349] A cross-sectional TEM image of an oxide semiconductor having a CAAC structure is acquired, and an FFT pattern is created by performing FFT processing on each region within the cross-sectional TEM image. From the created FFT pattern, the direction of the crystal axis of each region can be calculated. Specifically, among the spots observed in the created FFT pattern, the direction of the line segment connecting two spots with high brightness and at approximately equal distances from the center is taken as the direction of the crystal axis. Regions where the direction of the crystal axis of each region calculated from the FFT pattern is preferably 70° or more and 110° or less (within 90° ± 20°), more preferably 75° or more and 105° or less (within 90° ± 15°), still more preferably 80° or more and 100° or less (within 90° ± 10°), and even more preferably 85° or more and 95° or less (within 90° ± 5°) with respect to the formation surface can be regarded as having a CAAC structure.

[0350] When an oxide semiconductor having a CAAC structure is viewed from a direction perpendicular to the formation surface using a TEM image, a triangular or hexagonal atomic arrangement is observed on the a-b plane and has crystallinity.

[0351] [Composition of Metal Oxide] The metal oxide according to one aspect of the present invention preferably contains indium (In), and more preferably has a high content of In. By using a metal oxide having a high content of In as the oxide semiconductor, the on-current of the transistor can be increased and the frequency characteristics can be improved. For example, it is preferable to use indium oxide as the oxide semiconductor.

[0352] In addition, the metal oxide according to one aspect of the present invention can contain zinc. By the metal oxide containing zinc, a highly crystalline metal oxide, for example, a metal oxide having a CAAC structure can be obtained. For example, In-Zn oxide can be used as the oxide semiconductor. Specifically, a metal oxide having a composition of In:Zn = 1:1 [atomic ratio] or in the vicinity thereof, In:Zn = 2:1 [atomic ratio] or in the vicinity thereof, or In:Zn = 4:1 [atomic ratio] or in the vicinity thereof can be used. Here, the vicinity of the composition includes a range of ±30% of the desired atomic ratio.

[0353] In addition, the metal oxide according to one aspect of the present invention can contain element M. By the metal oxide containing element M, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, the reliability of the transistor to which the oxide semiconductor is applied can be improved.

[0354] For example, as the oxide semiconductor, an In-Zn oxide containing a trace amount of element M can be used. Specifically, a metal oxide having a composition of In:Ga:Zn = 4:0.1:1 [atomic ratio] or in the vicinity thereof, In:Ga:Zn = 2:0.1:1 [atomic ratio] or in the vicinity thereof, or In:Ga:Zn = 1:0.1:1 [atomic ratio] or in the vicinity thereof can be used. Also, a metal oxide having a composition of In:Sn:Zn = 4:0.1:1 [atomic ratio] or in the vicinity thereof, In:Sn:Zn = 2:0.1:1 [atomic ratio] or in the vicinity thereof, or In:Sn:Zn = 1:0.1:1 [atomic ratio] or in the vicinity thereof can be used.

[0355] In addition, as the oxide semiconductor, an In-Zn oxide containing element M can be used. Specifically, a metal oxide having a composition of In:M:Zn = 1:1:1 [atomic ratio] or in the vicinity thereof, a composition of In:M:Zn = 1:1:1.2 [atomic ratio] or in the vicinity thereof, a composition of In:M:Zn = 1:1:0.5 [atomic ratio] or in the vicinity thereof, a composition of In:M:Zn = 1:1:2 [atomic ratio] or in the vicinity thereof, a composition of In:M:Zn = 4:2:3 [atomic ratio] or in the vicinity thereof, a composition of In:M:Zn = 1:3:2 [atomic ratio] or in the vicinity thereof, or a composition of In:M:Zn = 1:3:4 [atomic ratio] or in the vicinity thereof can be used.

[0356] When the metal oxide is formed by a sputtering method, the composition of the metal oxide after formation may be different from the composition of the sputtering target. In particular, the content of zinc in the metal oxide after formation may be reduced to about 50% compared with the sputtering target.

[0357] In addition, when a metal oxide having a plurality of metal elements such as an In-Ga-Zn oxide is formed by ALD, the ratio of the number of cycles of the precursors containing the respective metal elements can be set according to the target composition. For example, when forming an In-Ga-Zn oxide with an atomic ratio of In:Ga:Zn = 1:3:2, the film formation cycle of the precursor containing In and the treatment cycle with an oxidizing agent can be performed once, the film formation cycle of the precursor containing Ga and the treatment cycle with an oxidizing agent can be performed three times, and the film formation cycle of the precursor containing Zn and the treatment cycle with an oxidizing agent can be performed twice. However, the ratio of the number of cycles of the precursors containing the respective metal elements may not match the atomic ratio of the respective metal elements in the formed metal oxide.

[0358] For the analysis of the composition of metal oxides used in oxide semiconductors, for example, EDX, XPS, inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES) can be used. Or, these methods may be combined in multiple ways for analysis. Note that for elements with low content, due to the influence of analysis accuracy, the actual content and the content obtained by analysis may be different. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0359] The oxide semiconductor according to one aspect of the present invention may have a stacked structure of two or more layers. When the oxide semiconductor has a two-layer structure of a first layer and a second layer on the first layer, the second layer preferably has a different composition from the first layer. Also, when the oxide semiconductor has a three-layer structure of a first layer, a second layer on the first layer, and a third layer on the second layer, the second layer preferably has a different composition from the first layer and the third layer. Note that the same composition as that of the third layer can be used for the first layer. Or, the first layer and the third layer may have different compositions.

[0360] For each of the first to third layers, the above-described metal oxide can be used.

[0361] For the second layer, for example, indium oxide, In-Zn oxide, or In-Zn oxide containing a trace amount of element M can be used. By increasing the content of In in the second layer, the on-current can be increased and the frequency characteristics can be improved.

[0362] It is preferable that the lower end of the conduction band of each of the first layer and the third layer is located closer to the vacuum level side than the lower end of the conduction band of the second layer. In other words, it is preferable that the energy of the lower end of the conduction band of each of the first layer and the third layer is smaller than the energy of the lower end of the conduction band of the second layer. At this time, the second layer is sandwiched between the first layer and the third layer whose lower ends of the conduction band are located closer to the vacuum level side, and can mainly function as a current path (channel).

[0363] By sandwiching the second layer between the first layer and the third layer, the carriers trapped at the interface of the second layer and in its vicinity can be reduced. In addition, the channel can be separated from the surface of the gate insulating layer, and the influence of surface scattering can be reduced. As a result, an embedded channel type transistor in which the channel is separated from the interface of the insulating layer can be realized, and the field effect mobility can be increased. In addition, the influence of the interface level that can be formed on the back channel side is reduced, the optical degradation (for example, photo negative bias degradation) of the transistor can be suppressed, and the reliability of the transistor can be improved.

[0364] For example, the band diagram in the vicinity of the oxide semiconductor 230 having the oxide semiconductors 230a to 230c shown in FIG. 2(A) is as shown in FIG. 17. In FIG. 17, the vertical axis represents energy, and the horizontal direction represents the film thickness direction at the center of the channel formation region. FIG. 17 shows the valence band maximum (VBM) and the conduction band minimum (CBM) of each of the oxide semiconductor 230a, the oxide semiconductor 230b, the oxide semiconductor 230c, and the insulator 250 in a state where no voltage is applied between the gate and the source. In addition, the vacuum level Vac is shown by a broken line in FIG. 17.

[0365] Note that since the energy at the upper end of the valence band and the energy at the lower end of the conduction band vary depending on the constituent elements and composition of each of the oxide semiconductor 230a, the oxide semiconductor 230b, the oxide semiconductor 230c, and the insulator 250, the relative levels of the energies at the upper ends of the valence bands and the relative levels of the energies at the lower ends of the conduction bands will be mainly described using the band diagram of FIG. 17.

[0366] Depending on the constituent elements and composition of each of the oxide semiconductor 230a, the oxide semiconductor 230b, and the oxide semiconductor 230c, as shown in FIG. 17, the oxide semiconductor 230b is sandwiched between the oxide semiconductor 230a and the oxide semiconductor 230c, where the lower end of the conduction band is located closer to the vacuum level compared to the oxide semiconductor 230b. By adopting such a configuration, an embedded channel can be realized. That is, in the oxide semiconductor 230b, a path is formed through which more current (electrons are illustrated as carriers in FIG. 17) flows. Therefore, an increase in the on-current or an improvement in reliability can be achieved.

[0367] When forming an embedded channel in the first to third layers, for example, as the first and third layers, a metal oxide with a higher Ga content compared to the second layer can be used. Specifically, for each of the first and third layers, a metal oxide with a composition of In:Ga:Zn = 1:1:1 [atomic ratio] or in the vicinity thereof, a metal oxide with a composition of In:Ga:Zn = 1:3:2 [atomic ratio] or in the vicinity thereof, or a metal oxide with a composition of In:Ga:Zn = 1:3:4 [atomic ratio] or in the vicinity thereof can be used. Alternatively, a Ga-Zn oxide or gallium oxide can be used. By increasing the Ga content in the first and third layers, the lower ends of the conduction bands of the first and third layers may be located closer to the vacuum level than the lower end of the conduction band of the second layer.

[0368] Moreover, by increasing the Ga content in the first layer and the third layer, the barrier property of the first layer and the third layer against hydrogen can be enhanced. Therefore, diffusion of hydrogen into the second layer from below the first layer or above the third layer can be suppressed. Further, by increasing the Ga content in the first layer and the third layer, impurities such as hydrogen or water contained in the oxide semiconductor can be reduced by heat applied after the formation of the oxide semiconductor or the like.

[0369] Moreover, by increasing the Ga content in the first layer and the third layer, the barrier property of the first layer and the third layer against oxygen can be enhanced. Therefore, release of oxygen from the second layer where the channel is formed can be suppressed, and formation of oxygen vacancies in the second layer or an increase in the amount of oxygen vacancies in the second layer can be suppressed. Thereby, the electrical characteristics of the transistor can be improved.

[0370] Moreover, by increasing the Ga content in the first layer, the resistivity of the first layer may be made higher than the resistivity of the second layer. When the first layer is provided on the back-channel side, by providing a layer with a high resistivity as the first layer, a negative shift of the threshold voltage or a decrease in the on-current can be suppressed. Therefore, the threshold voltage of the transistor shifts positively, and the transistor can be made normally-off. From the above, the electrical characteristics of the transistor can be improved and the reliability of the transistor can be enhanced.

[0371] For the evaluation of the band gap of a metal oxide, optical evaluation using a spectrophotometer, spectroscopic ellipsometry, photoluminescence method, X-ray photoelectron spectroscopy, or X-ray absorption fine structure (XAFS) can be used. Further, analysis can be performed by combining a plurality of these methods. The electron affinity or the bottom of the conduction band can be determined from the ionization potential, which is the difference between the vacuum level and the energy of the top of the valence band, and the band gap. For the evaluation of the ionization potential, for example, ultraviolet photoelectron spectroscopy (UPS) can be used.

[0372] Note that, for the first layer and the third layer, a metal oxide having a higher In content than the second layer may be used. Further, for one of the first layer and the third layer, a metal oxide having a higher In content than the second layer may be used, and for the other, a metal oxide having a higher Ga content than the second layer may be used.

[0373] Further, the first layer, the second layer, and the third layer may each have a plurality of layers having the composition described above laminated thereon. For example, the first layer may have a structure in which a metal oxide having a high In content is laminated on a metal oxide having a high Ga content. Further, for example, the third layer may have a structure in which a metal oxide having a high Ga content is laminated on a metal oxide having a high In content.

[0374] [Method for producing an oxide semiconductor] The oxide semiconductor according to one aspect of the present invention can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like.

[0375] Further, the oxide semiconductor according to one aspect of the present invention can be produced by forming a metal oxide using two film formation methods. For example, the oxide semiconductor according to one aspect of the present invention can be produced by forming a metal oxide using a first film formation method and a second film formation method.

[0376] An oxide semiconductor according to one embodiment of the present invention can have a two-layer structure including a first layer and a second layer on the first layer. When the oxide semiconductor has a two-layer structure, the oxide semiconductor can be manufactured by forming the first layer on a surface to be formed using a first film-forming method, and then forming the second layer thereon using a second film-forming method.

[0377] As the first film-forming method, it is preferable to use a film-forming method that causes less damage to the surface to be formed as compared with the second film-forming method. Thereby, formation of a mixed layer at the interface between the oxide semiconductor and the layer that is the surface to be formed of the oxide semiconductor can be suppressed. In addition, since impurities such as silicon can be prevented from being mixed into the second layer formed on the first layer, the crystallinity of the oxide semiconductor may be further increased.

[0378] Examples of the first film-forming method include an ALD method, a CVD method, and an MBE method. Examples of the CVD method include a plasma CVD (PECVD: Plasma Enhanced CVD) method, a thermal CVD method, an optical CVD method, and an MOCVD method. The MBE method is a film-forming method for growing a thin film having a crystal structure that reflects the crystal system of the substrate, and can be said to be one of the film-forming methods that cause less damage to the surface to be formed. In addition, as the first film-forming method, a wet method can be used. The wet method is one of the film-forming methods that cause less damage to the surface to be formed. Examples of the wet method include a spray coating method.

[0379] As the second film-forming method, it is preferable to use a method capable of forming a metal oxide having crystallinity. At this time, the metal oxide to be formed preferably has a CAAC structure. Examples of the second film-forming method include a sputtering method and a PLD method. Since a metal oxide formed by using the sputtering method is likely to have crystallinity, the sputtering method is suitable as the second film-forming method.

[0380] In addition, when forming a metal oxide on a surface to be formed using a second film-forming method, alloying may occur between the components contained in the metal oxide and the components contained in the layer that is the surface to be formed due to damage to the surface to be formed. When alloying occurs, a mixed layer may be formed at the interface between the metal oxide and the layer that is the surface to be formed. The mixed layer can also be said to be an alloyed region. Further, the formation of the mixed layer can also be said to be alloying.

[0381] For example, when using a sputtering method as the second film-forming method, a mixed layer may be formed by particles emitted from a target or the like (also referred to as sputtering particles), or energy applied to the substrate side by sputtering particles or the like. Specifically, when forming a metal oxide using the second film-forming method with an insulating layer having silicon, for example, a silicon oxide film, as the surface to be formed, there is a risk that silicon may be mixed into the metal oxide. There is a concern that the crystallization of the metal oxide may be inhibited due to the mixing of impurities such as silicon into the metal oxide. In addition, using an oxide semiconductor containing impurities in a transistor may have an adverse effect on the initial characteristics or reliability of the transistor. Also, even when the heat treatment described later is performed, it is difficult to enhance the crystallinity of the alloyed region.

[0382] Therefore, as described above, by forming a metal oxide using the first film-forming method before forming a metal oxide using the second film-forming method, the mixing of impurities into the oxide semiconductor can be suppressed. In addition, alloying with the layer that is the surface to be formed can be suppressed. Therefore, the initial characteristics and reliability of the transistor can be improved. Also, the crystallinity of the oxide semiconductor can be made higher.

[0383] Note that a mixed layer may be formed at the interface between the first layer and the second layer. The mixed layer has components included in the first layer and components included in the second layer. For example, when gallium oxide is used for the first layer and a metal oxide containing indium is used for the second layer, the mixed layer has gallium and indium. Further, for example, when the indium content rate in the second layer is higher than the indium content rate in the first layer, the indium content rate in the mixed layer is equal to or higher than the indium content rate in the first layer and equal to or lower than the indium content rate in the second layer.

[0384] The ALD method is suitable as the first film-forming method because it can suppress damage to the surface to be formed as compared with the sputtering method. Further, the ALD method is a film-forming method with excellent coating properties as compared with the sputtering method, and by using the ALD method as the film-forming method for the first layer, the coating property of the oxide semiconductor can be enhanced. Therefore, the oxide semiconductor can be well coated on steps, openings, etc. with a high aspect ratio.

[0385] As the first layer, for example, a metal oxide having a microcrystalline structure or an amorphous structure with lower crystallinity than the CAAC structure may be formed. By forming a second layer with high crystallinity on the first layer with low crystallinity or by applying heat treatment after forming the second layer, the crystallinity of the first layer may increase with the second layer as a nucleus. As a result, the crystallinity may be enhanced in the entire oxide semiconductor including the vicinity of the interface with the surface to be formed.

[0386] The layer that is the surface to be formed is, for example, an insulating film such as a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, or a hafnium oxide film. Note that depending on the transistor structure, it may be a conductive film such as a titanium nitride film, a tungsten film, or an ITSO film. Further, the layer that is the surface to be formed does not necessarily have crystallinity. Note that when the layer has crystallinity, it may have a crystal structure with low lattice matching with the metal oxide included in the oxide semiconductor.

[0387] The first layer is preferably formed using the ALD method. Here, a method for forming an In-M-Zn oxide using the ALD method will be described as the first layer.

[0388] First, a source gas containing a precursor having indium is introduced into a reaction chamber (also referred to as a chamber), and the precursor is adsorbed onto the surface to be formed. Next, as a reactant, an oxidizing agent is introduced into the reaction chamber and reacted with the adsorbed precursor to desorb components other than indium while indium is adsorbed on the substrate, thereby forming a layer in which indium and oxygen are bonded.

[0389] Next, a source gas containing a precursor having element M is introduced into the reaction chamber and adsorbed onto the layer in which indium and oxygen are bonded. Next, as a reactant, an oxidizing agent is introduced into the reaction chamber and reacted with the adsorbed precursor to desorb components other than element M while element M is adsorbed on the substrate, thereby forming a layer in which element M and oxygen are bonded.

[0390] Next, a source gas containing a precursor having zinc is introduced into the reaction chamber and adsorbed onto the layer in which element M and oxygen are bonded. Next, as a reactant, an oxidizing agent is introduced into the reaction chamber and reacted with the adsorbed precursor to desorb components other than zinc while zinc is adsorbed on the substrate, thereby forming a layer in which zinc and oxygen are bonded.

[0391] By repeating the above-described method, an In-M-Zn oxide can be formed as an oxide semiconductor on the layer that is the surface to be formed using the ALD method.

[0392] When forming an oxide semiconductor using the ALD method, ozone (O3), oxygen (O2), water (H2O), etc. can be used as the oxidizing agent. By using ozone (O3), oxygen (O2), etc. that do not contain hydrogen as the oxidizing agent, the amount of hydrogen mixed into the oxide semiconductor can be reduced.

[0393] In the above, after adsorbing the precursor, it is preferable to stop introducing the raw material gas containing the precursor, purge the reaction chamber, and then discharge excess precursor, reaction products, etc. from the reaction chamber. Also, in the above, after reacting the adsorbed precursor with the oxidant, it is preferable to stop introducing the oxidant, purge the reaction chamber, and then discharge excess reactants, reaction products, etc. from the reaction chamber.

[0394] Also, in the description of this specification, etc., unless otherwise specified, when using ozone, oxygen, or water as a reactant or an oxidant, these are not limited to the gaseous or molecular state, but also include those in a plasma state, a radical state, and an ionic state.

[0395] The second layer is preferably formed using a sputtering method.

[0396] As the target for the sputtering method, In-M-Zn oxide can be used. When forming a metal oxide by the sputtering method, oxygen or a mixed gas of oxygen and a noble gas can be used as the sputtering gas. Also, by increasing the proportion of oxygen contained in the sputtering gas, the excess oxygen in the formed oxide film can be increased.

[0397] Also, the higher the ratio of the flow rate of oxygen gas to the total film-forming gas used during formation (hereinafter also referred to as the oxygen flow ratio), the more likely it is to form a highly crystalline metal oxide.

[0398] When forming a metal oxide by sputtering, if the ratio of oxygen contained in the sputtering gas is more than 30% and 100% or less, preferably 70% or more and 100% or less, an oxygen-excess type metal oxide may be formed during film formation. A transistor using an oxygen-excess type metal oxide in the channel formation region can obtain relatively high reliability. However, one aspect of the present invention is not limited to this. When forming a film with the ratio of oxygen contained in the sputtering gas being 1% or more and 30% or less, preferably 5% or more and 20% or less, an oxygen-deficient type metal oxide is formed. A transistor using an oxygen-deficient type metal oxide in the channel formation region can obtain relatively high field-effect mobility.

[0399] In the formation of a metal oxide using the sputtering method, it is preferable to heat the substrate. By increasing the substrate temperature (stage temperature) during the formation of the metal oxide, a metal oxide with high crystallinity may be formed. In the formation of a metal oxide using the sputtering method, the temperature of substrate heating is preferably, for example, 100°C or more and 400°C or less, and more preferably 200°C or more and 300°C or less.

[0400] By adopting the above manufacturing method, the thickness of the mixed layer formed at the interface between the layer to be formed and the metal oxide can be reduced, or the alloyed region formed at the interface between the layer to be formed and the metal oxide can be made thin enough that it cannot be observed. For example, the thickness of the alloyed region can be 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and still more preferably 0 nm or more and less than 0.3 nm.

[0401] Note that the thickness of the alloyed region can sometimes be calculated by performing line analysis of the composition on the region and its periphery by secondary ion mass spectrometry (SIMS) or energy dispersive X-ray spectroscopy (EDX).

[0402] For example, with the direction perpendicular to the formation surface of the first layer as the depth direction, line analysis of EDX is performed on the alloyed region and its periphery. Next, in the profile of the quantitative values of each element with respect to the depth direction obtained by the analysis, the depth at which the quantitative value of the metal that is the main component of the first layer and not the main component of the layer to be the formation surface (In if the first layer contains In) becomes half value is defined as the depth (position) of the interface between the above region and the first layer. Further, the depth at which the quantitative value of the element (for example, Si) that is the main component of the layer to be the formation surface and not the main component of the first layer becomes half value is defined as the depth (position) of the interface between the above region and the layer to be the formation surface. Thus, the thickness of the alloyed region can be calculated.

[0403] In the oxide semiconductor according to one aspect of the present invention, when observing the thickness of the alloyed region by EDX analysis, for example, the thickness is 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and still more preferably 0 nm or more and less than 0.3 nm.

[0404] Also, for example, when performing SIMS analysis of an oxide semiconductor formed on a silicon oxide film which is the formation surface, the depth at which the concentration of silicon becomes 50% of the maximum value of the concentration of the silicon oxide film is defined as the interface, and the thickness t is the distance between the interface and the depth at which the concentration of silicon decreases to 1.0×10 21 atoms / cm 3 , preferably 5.0×10 20 atoms / cm 3 , more preferably 1.0×10 20 atoms / cm 3 The thickness t is preferably 3 nm or less, and more preferably 2 nm or less.

[0405] By making the thickness of the alloyed region thinner, the thickness t can be made to be a value within the above range.

[0406] By reducing the alloyed region, it becomes possible to form the CAAC structure near the surface to be formed. Here, the vicinity of the surface to be formed refers to, for example, a region that is more than 0 nm and 3 nm or less, preferably more than 0 nm and 2 nm or less, and more preferably 1 nm or more and 2 nm or less, measured perpendicularly from the surface to be formed of the oxide semiconductor.

[0407] Note that the CAAC structure in the vicinity of the surface to be formed may be confirmed in an observation using TEM. For example, in a cross-sectional observation using a high-resolution TEM of an oxide semiconductor, bright spots arranged in layers in a direction parallel to the surface to be formed are confirmed in the vicinity of the surface to be formed.

[0408] Also, the oxide semiconductor according to one aspect of the present invention can have a three-layer structure including a first layer, a second layer on the first layer, and a third layer on the second layer.

[0409] When the oxide semiconductor has a three-layer structure, the oxide semiconductor can be produced by forming the first layer using a first film-forming method on the surface to be formed, then forming the second layer using a second film-forming method, and forming the third layer using the first film-forming method.

[0410] Even when a composition that makes it difficult to form a CAAC structure by single-layer formation is used for the first layer and the third layer, crystal growth occurs with the second layer as a nucleus, so that the entire oxide semiconductor including the first layer and the third layer can have a configuration having a CAAC structure. Alternatively, a configuration having a CAAC structure can be adopted in a region including at least a part of each of the first layer and the third layer and in a region spanning the second layer.

[0411] In particular, even in a composition with a high In content in the first layer and the third layer, suitable crystallinity can be achieved as the semiconductor layer of the transistor. In the oxide semiconductor according to one aspect of the present invention, it is possible to achieve both an improvement in the on characteristics of the transistor by increasing the In content and an improvement in reliability by forming a highly crystalline CAAC structure.

[0412] Further, the first layer and the third layer may use a metal oxide having the same composition as that of the second layer. By using the same composition, CAAC crystallization may be likely to occur after heat treatment.

[0413] Since the second layer has high crystallinity, the third layer can grow crystals using the crystals of the second layer as nuclei or seeds. Therefore, even when a film-forming method that is likely to have crystallinity is not used as the film-forming method of the third layer, the third layer can be crystallized. Here, for example, by forming the third layer using a film-forming method with higher coverage compared to the second layer, the oxide semiconductor can have both high crystallinity and high coverage throughout the layer.

[0414] Further, the second layer has its crystallinity enhanced by reducing the influence of the surface to be formed by providing the first layer, and has extremely excellent crystallinity. Therefore, it can be expected that a layer with extremely excellent crystallinity will also be formed in the third layer that crystallizes using the second layer as nuclei or seeds.

[0415] When the oxide semiconductor is used as the semiconductor layer of a transistor, the third layer, which is the uppermost layer of the oxide semiconductor, may be in contact with the gate insulating layer. By enhancing the crystallinity of the layer in contact with the gate insulating layer, the carrier mobility can be increased when the transistor is in the on state.

[0416] The first layer and the third layer each have high crystallinity using the highly crystalline second layer as nuclei or seeds. Specifically, the crystallinity of the first layer may increase due to heat treatment during the film formation of the second layer or after the film formation of the third layer. Also, the crystallinity of the third layer may increase due to heat treatment during the film formation of the third layer or after the film formation of the third layer. Note that the above heat treatment has a function of assisting in enhancing crystallinity.

[0417] Thus, in the method for manufacturing an oxide semiconductor according to one aspect of the present invention, by using a second layer having a highly crystalline metal oxide (i.e., CAAC) as a nucleus or a seed, the crystallinity of the upper and lower metal oxides (here, the first layer and the third layer) can be increased. As a result, the crystallinity of the entire oxide semiconductor can be increased. In other words, by using the second layer as a nucleus or a seed, the upper and lower metal oxides can be solid-phase grown to form a highly crystalline oxide semiconductor. An oxide semiconductor formed using such a film formation method, here a CAAC film, can be referred to as Axial Growth CAAC (AG CAAC).

[0418] In the oxide semiconductor, it is preferable that regions having a CAAC structure widely exist over the entire layer. The region having a CAAC structure in the first layer is crystal-connected to the region having a CAAC structure in the second layer. The region having a CAAC structure in the third layer is crystal-connected to the region having a CAAC structure in the second layer. As a result, the boundary between the first layer and the second layer may not be observed. Also, the boundary between the second layer and the third layer may not be observed. The oxide semiconductor may be expressed as a single layer in which the interface is not clearly observed. The oxide semiconductor may be expressed as a single layer.

[0419] In each of the first to third layers, in a region having a CAAC structure, for example, in a cross-sectional observation using a high-resolution TEM, bright spots arranged parallel or substantially parallel to the surface to be formed are confirmed. Further, the c-axis of the CAAC structure possessed by each of the first to third layers is preferably parallel or substantially parallel to the normal direction of the surface to be formed or the surface of the oxide semiconductor.

[0420] Also, a part of the first layer or the third layer may not be crystallized.

[0421] In addition, when the oxide semiconductor has a three-layer structure, the oxide semiconductor can also be manufactured by forming a first layer on a surface to be formed using a first film formation method, then forming a second layer using the first film formation method, and forming a third layer using a second film formation method.

[0422] As described above, by using a metal oxide with a high In content in a transistor, the field-effect mobility of the transistor can be increased. On the other hand, a metal oxide with a high In content tends to have a cubic crystal structure. Therefore, by using a metal oxide with a high In content in the second layer in contact with the third layer, a crystal in which the crystal orientation of the third layer is reflected can be formed.

[0423] In addition, it is preferable that the lattice mismatch between the crystal of the third layer and the crystal of the second layer is small. Thereby, the second layer can form a crystal in which the crystal orientation of the third layer is reflected. At this time, for example, in a cross-sectional observation using a high-resolution TEM of the oxide semiconductor, bright spots arranged in layers in a direction parallel to the surface to be formed are confirmed in the second layer.

[0424] If the lattice mismatch between the crystal of the third layer and the crystal of the second layer is small, the crystal structure of the second layer is not particularly limited. The crystal structure of the second layer may be any of cubic, tetragonal, orthorhombic, hexagonal, monoclinic, and trigonal crystal systems.

[0425] In the above configuration, typically, the first layer is a metal oxide having a composition of In:Ga:Zn = 1:3:2 [atomic ratio] or in the vicinity thereof, or a layer containing gallium oxide, the second layer is a metal oxide containing a trace amount of the above-described element M, or a layer containing indium oxide, and the third layer can be a layer containing a metal oxide having a composition of In:Ga:Zn = 1:1:1 [atomic ratio] or in the vicinity thereof. At this time, the first layer has gallium. Further, when the first layer contains a metal oxide having a composition of In:Ga:Zn = 1:3:2 [atomic ratio] or in the vicinity thereof, in the first layer, the content ratio of indium is lower than the content ratio of gallium. Further, the content ratio of indium in the second layer is higher than the content ratio of indium in the third layer.

[0426] When the first layer and the second layer are formed using the first film formation method, it is preferable that the first layer and the second layer are continuously formed without exposure to the atmosphere. By continuously forming the first layer and the second layer without exposure to the atmosphere, it becomes possible to improve productivity. Further, impurities (typically moisture, etc.) incorporated into the interface between the first layer and the second layer and the vicinity thereof can be reduced.

[0427] Further, one or more of the first layer to the third layer may have a plurality of layers having different compositions laminated thereon. For example, the first layer may be produced by forming a layer containing a metal oxide having a high Ga content ratio using the first film formation method, and then forming a layer containing a metal oxide having a higher In content ratio than that layer using the first film formation method.

[0428] After forming a layer using the first film formation method, it is preferable to perform microwave plasma treatment.

[0429] In this specification and the like, the microwave refers to an electromagnetic wave having a frequency of 300 MHz or more and 300 GHz or less. Further, the microwave plasma treatment refers to a treatment using an apparatus having a power source for generating high-density plasma using microwaves, for example. Further, the microwave plasma treatment can also be referred to as microwave-excited high-density plasma treatment.

[0430] By performing microwave plasma treatment in an oxygen-containing atmosphere, the impurity concentration in the oxide semiconductor 230 can be reduced. In particular, examples of the impurities include hydrogen and carbon. In the above description, a configuration in which microwave plasma treatment is performed on a metal oxide in an oxygen-containing atmosphere is exemplified, but it is not limited thereto. For example, microwave plasma treatment may be performed on an insulating film, more specifically, a silicon oxide film provided near the metal oxide, in an oxygen-containing atmosphere. Also, the crystallinity of the oxide semiconductor may be enhanced by the heat in the microwave plasma treatment.

[0431] The microwave plasma treatment is preferably performed under reduced pressure, and the pressure is preferably 10 Pa or more and 1000 Pa or less, more preferably 50 Pa or more and 700 Pa or less, and even more preferably 100 Pa or more and 400 Pa or less. Also, the treatment temperature is preferably room temperature (25°C) or more and 750°C or less, more preferably 300°C or more and 500°C or less, and can be 400°C or more and 450°C or less.

[0432] When performing the microwave plasma treatment, heating of the substrate may be performed. The heating temperature of the substrate is preferably room temperature (for example, 25°C) or more, 100°C or more, 200°C or more, 300°C or more, or 400°C or more, and preferably 500°C or less, or 450°C or less.

[0433] The microwave plasma treatment can be performed using, for example, oxygen gas and argon gas. For example, the oxygen flow ratio (O2 / (O2+Ar)) in the microwave plasma treatment is preferably greater than 0% and 10% or less, preferably 0.5% or more and 5% or less, more preferably 0.5% or more and 3% or less, and typically 1% is more preferable.

[0434] By performing microwave plasma treatment in an oxygen-containing atmosphere, oxygen gas can be plasmaized using microwaves or high-frequency waves such as RF, and oxygen radicals generated by plasmaizing oxygen gas can act on the oxide semiconductor. Due to the action of plasma, microwaves, or oxygen radicals, etc., defects in the oxide semiconductor where hydrogen has entered the oxygen deficiency (hereinafter, sometimes referred to as V O H) can be divided into oxygen deficiency and hydrogen, and hydrogen, which is an impurity, can be removed from the oxide semiconductor. In this way, V O H contained in the oxide semiconductor can be reduced. Also, at this time, carbon that was bound to oxygen or hydrogen, etc., may also be removed. In this way, by performing microwave plasma treatment, impurities such as carbon or hydrogen can be reduced. Further, by supplying the above oxygen radicals to the oxygen deficiency formed in the oxide semiconductor, the oxygen deficiency in the oxide semiconductor can be further reduced.

[0435] Also, by performing microwave plasma treatment, the crystallinity of the layer formed using the first film formation method can be enhanced. Here, the principle by which the crystallinity of the oxide semiconductor is improved by microwave plasma treatment will be explained. First, active species such as oxygen radicals excited by microwaves arrive at the surface of the oxide semiconductor, and a substitution reaction occurs between the active species and oxygen in the oxide semiconductor. At this time, nuclei or seeds are formed. Also, lateral growth of the nuclei or seeds is caused. Note that it is preferable if the active species excited by microwaves contain oxygen (typically oxygen ions) that is likely to adsorb to the sides of the nuclei or seeds, because the above lateral growth is promoted. By performing microwave plasma treatment, formation of nuclei or seeds and lateral growth of the nuclei or seeds occur, and the crystallinity of the oxide semiconductor is improved.

[0436] On the one hand, a reaction occurs between a part of the oxygen in the oxide semiconductor that existed before the microwave plasma treatment and the hydrogen in the oxide semiconductor. In other words, a reaction of "2H + O → H2O↑" occurs, and thus the hydrogen can be removed as H2O (also referred to as dehydration or dehydrogenation). Since H2O is one of the factors inhibiting the improvement of crystallinity, it is preferably removed from the oxide semiconductor. By removing the hydrogen in the oxide semiconductor as H2O and reducing the hydrogen concentration in the oxide semiconductor, the improvement of crystallinity can also be promoted. Note that by increasing the temperature during the microwave plasma treatment, it is possible to further reduce the hydrogen concentration in the oxide semiconductor.

[0437] Note that after the microwave plasma treatment, heat treatment may be continuously performed without exposing to the outside air. The temperature of the heat treatment is preferably, for example, 100°C or higher and 750°C or lower, more preferably 300°C or higher and 500°C or lower, and even more preferably 400°C or higher and 450°C or lower.

[0438] Note that even without microwave plasma treatment, the crystallinity can be improved by plasma treatment containing oxygen gas.

[0439] By increasing the crystallinity of the layer formed using the first film formation method, the crystallinity of the layer formed on the layer can be further increased. Therefore, the crystallinity of the entire oxide semiconductor can be increased.

[0440] The oxygen supplied into the oxide semiconductor exists in various forms such as oxygen atoms, oxygen molecules, oxygen ions (charged oxygen atoms or oxygen molecules), and oxygen radicals (oxygen atoms, oxygen molecules, or oxygen ions having unpaired electrons). Note that the oxygen injected into the oxide semiconductor is preferably any one or more of the above-mentioned forms, and particularly preferably oxygen radicals.

[0441] Further, after forming the oxide semiconductor, it is preferable to perform a heat treatment. By performing the heat treatment, the crystallinity of the oxide semiconductor can be enhanced. The heat treatment here is not limited to heat treatment. For example, it may be heat applied during the manufacturing process.

[0442] The temperature of the heat treatment can be, for example, 100°C or higher and 800°C or lower, preferably 250°C or higher and 650°C or lower, and more preferably 350°C or higher and 550°C or lower. Typically, it can be 400°C ± 25°C (375°C or higher and 425°C or lower). Also, the treatment time can be 10 hours or less, for example, 1 minute or more and 5 hours or less, or 1 minute or more and 2 hours or less. Further, when using an RTA apparatus, the treatment time can be, for example, 1 second or more and 5 minutes or less. By this heat treatment, it is expected that the gaps between the atomic-level crystal parts of the CAAC structure of the second layer formed by the second film-forming method are repaired by the third layer formed by the first film-forming method (in other words, each crystalline molecule formed by the ALD method).

[0443] There is no particular limitation on the heating apparatus used for the heat treatment, and it may be an apparatus that heats the object to be treated by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, an electric furnace or an RTA (Rapid Thermal Anneal) apparatus such as an LRTA (Lamp Rapid Thermal Anneal) apparatus or a GRTA (Gas Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus is an apparatus that heats the object to be treated by radiation of light (electromagnetic wave) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA apparatus is an apparatus that performs a heat treatment using a high-temperature gas.

[0444] In the third layer formed by the first film formation method, the crystallinity of the region having the CAAC structure may be enhanced by the heat treatment step. Further, when the region is formed only below the third layer after film formation by the ALD method, the region may spread upward by the heat treatment step. That is, by performing the heat treatment, a region having the CAAC structure may be formed over the entire third layer.

[0445] Also, it is preferable that at least a part of the first layer or the second layer formed by the first film formation method is converted into CAAC by the heat treatment step. The conversion into CAAC is expected to occur more easily with the mixed layer formed in the first layer or the second layer serving as nuclei or seeds in the formation of the layer formed by the second film formation method. The region that is converted into CAAC in the first layer or the second layer is preferably wide, and preferably extends to the vicinity of the surface to be formed.

[0446] Further, in order to convert into CAAC from the upper part to the lower part of the first layer or the second layer, it is possible to convert into CAAC up to the vicinity of the layer without being limited to the material or crystallinity of the layer that is the surface to be formed. For example, even if the layer has an amorphous structure, the crystallinity of the first layer or the second layer can be enhanced. Therefore, the method for manufacturing an oxide semiconductor according to one aspect of the present invention is particularly suitable when the layer that is the surface to be formed has an amorphous structure.

[0447] As described above, by performing one or both of the microwave plasma treatment and the heat treatment, the crystallinity of the entire oxide semiconductor can be increased. Also, impurities in the oxide semiconductor can be reduced. Further improvement in crystallinity can be achieved by performing crystal growth in a state where the impurity concentration in the oxide semiconductor is reduced.

[0448] By enhancing the crystallinity of the oxide semiconductor, it is expected to suppress an increase in the electrical resistance of the semiconductor layer of a transistor using the oxide semiconductor, or to improve the initial characteristics (especially the on-current) of the transistor, resulting in a transistor suitable for high-speed driving. Also, the reliability of the transistor can be enhanced, and the on-current can be increased.

[0449] Note that one or both of the microwave plasma treatment and the heat treatment may be performed directly on the oxide semiconductor, or may be performed after forming an insulating film or the like on the oxide semiconductor.

[0450] Before forming the first layer, or after forming the first layer or the second layer using the first film-forming method, a process of supplying oxygen to the first layer or the second layer may be performed. Thereby, oxygen can be supplied to the oxide semiconductor by heat or the like applied after this process.

[0451] Examples of the process of supplying oxygen include heat treatment in an atmosphere containing oxygen, or plasma treatment (including microwave plasma treatment) in an atmosphere containing oxygen. Alternatively, by forming an oxide film (preferably a metal oxide film) in an atmosphere containing oxygen by a sputtering method, oxygen can be supplied to the first layer or the second layer formed using the first film-forming method. The formed oxide film may be removed immediately afterwards, or may be left as it is. When the formed oxide film is left as it is, the oxide film can be used as a layer (the second layer or the third layer) provided on the first layer or the second layer. Note that the atmosphere containing oxygen includes not only oxygen gas (O2), but also an atmosphere containing a gas of a compound containing oxygen such as ozone (O3) or nitrous oxide (N2O). Also, the substrate temperature during the plasma treatment is set to be 25°C or higher and 450°C or lower.

[0452] The oxide semiconductor according to one aspect of the present invention has high crystallinity throughout the entire layer. Therefore, in the oxide semiconductor, the boundaries between the stacked films may not be confirmed in the first to third layers. In particular, after heat treatment, it may be difficult to confirm the boundaries between the stacked films. The presence or absence of the boundaries between the stacked films can be confirmed using, for example, cross-sectional TEM, cross-sectional STEM (scanning transmission electron microscope), or the like.

[0453] In addition, an oxide semiconductor having a CAAC structure formed using the above two film formation methods may have one or more of the relative dielectric constant of the film, the film density, and the film hardness higher than those of an oxide semiconductor having a CAAC structure formed using one film formation method.

[0454] By using an oxide semiconductor having a CAAC structure formed using the above two film formation methods in the channel formation region of a transistor, a transistor having excellent characteristics (for example, a transistor having a large on-current, a transistor having a high field-effect mobility, a transistor having a small S value, a transistor having high frequency characteristics (also referred to as f characteristics), a highly reliable transistor, etc.) can be realized.

[0455] In addition, the oxide semiconductor according to one aspect of the present invention may be manufactured by using the first film formation method and one or both of microwave plasma treatment and heat treatment. In other words, it may be possible to manufacture the oxide semiconductor according to one aspect of the present invention without using the second film formation method. For example, after forming the first layer using the first film formation method, the crystallinity of the first layer can be enhanced by performing one or both of microwave plasma treatment and heat treatment. Thus, the crystallinity of the second layer formed on the first layer using the first film formation method can be increased with the first layer as a nucleus or seed. Further, after forming the second layer, the crystallinity of the oxide semiconductor can be enhanced by performing one or both of microwave plasma treatment and heat treatment. Therefore, a CAAC structure can be formed in the oxide semiconductor.

[0456] As described above, even in the manufacturing method without using the second film formation method, by using the first layer formed by the first film formation method as a nucleus or a seed, the upper oxide semiconductor can be solid-phase grown to form a highly crystalline oxide semiconductor. An oxide semiconductor formed by using such a film formation method can also be referred to as AG CAAC.

[0457] Note that when the oxide semiconductor has a stacked structure of two or more layers, it can also be manufactured by forming a metal oxide using one type of film formation method. When the oxide semiconductor has a two-layer structure including a first layer and a second layer on the first layer, the oxide semiconductor can be manufactured, for example, by forming the first layer and the second layer in this order using a sputtering method. Since the sputtering method has a higher film formation rate than the ALD method, productivity can be improved. Further, for example, when the oxide semiconductor has a three-layer structure including a first layer, a second layer on the first layer, and a third layer on the second layer, the first to third layers can also be manufactured using the sputtering method. Furthermore, a part of the first to third layers can be formed by the ALD method. For example, one or both of the second layer and the third layer may be formed by the ALD method.

[0458] [Oxide Semiconductor of Transistor] The oxide semiconductor of the present embodiment can be used as a semiconductor layer of a transistor.

[0459] The oxide semiconductor of the present embodiment can be used for the oxide semiconductor 230 or the like included in each transistor described in Embodiment 1. For example, the first layer can be used for the oxide semiconductor 230a, the second layer can be used for the oxide semiconductor 230b, and the third layer can be used for the oxide semiconductor 230c. Further, the layer to be formed corresponds to the insulator 224 described in Embodiment 1.

[0460] The oxide semiconductor of the present embodiment preferably has a CAAC structure. In an oxide semiconductor having a CAAC structure, metal atoms are arranged in layers in a direction parallel or substantially parallel to the surface to be formed in the crystal part.

[0461] In an oxide semiconductor having a CAAC structure, current anisotropy is presumed to occur. For example, in an IGZO crystal, current easily flows in the a-axis direction compared to the c-axis direction. That is, in an oxide semiconductor having a CAAC structure, it is presumed that current easily flows in the lateral direction rather than in the longitudinal direction.

[0462] In the semiconductor device described in the previous embodiment, in the oxide semiconductor 230, metal atoms are arranged in layers in a direction parallel or substantially parallel to the formation surface. It can also be expressed that the a-b plane of the CAAC structure is provided in a direction parallel or substantially parallel to the formation surface. By adopting such a configuration, in the channel of the transistor, the a-b plane of the CAAC structure can be provided along the direction in which current flows. Thereby, the on-current of the transistor can be increased.

[0463] When the oxide semiconductor of the present embodiment is used as the semiconductor layer of a transistor, the film thickness of the oxide semiconductor is preferably, for example, 3 nm or more and 200 nm or less, preferably 3 nm or more and 100 nm or less, more preferably 5 nm or more and 100 nm or less, still more preferably 10 nm or more and 100 nm or less, still more preferably 10 nm or more and 70 nm or less, still more preferably 15 nm or more and 70 nm or less, still more preferably 15 nm or more and 50 nm or less, still more preferably 20 nm or more and 50 nm or less. Also, in a transistor used for a more fine semiconductor device, the film thickness of the oxide semiconductor is preferably 1 nm or more and 20 nm or less, preferably 3 nm or more and 15 nm or less, preferably 5 nm or more and 12 nm or less, preferably 5 nm or more and 10 nm or less. Also, the average film thickness of the oxide semiconductor in the channel formation region of the transistor is particularly preferably, for example, 2 nm or more and 15 nm or less.

[0464] The film thickness of the first layer is preferably, for example, 0.5 nm or more and 50 nm or less, more preferably 0.5 nm or more and 30 nm or less, still more preferably 0.5 nm or more and 20 nm or less, even more preferably 1 nm or more and 50 nm or less, still even more preferably 1 nm or more and 30 nm or less, yet even more preferably 1 nm or more and 20 nm or less, and most preferably 2 nm or more and 20 nm or less. Further, the first layer is more preferably 0.5 nm or more and 3 nm or less.

[0465] Further, the first layer preferably has a region where the film thickness is 0.1 nm or more and 3 nm or less, and more preferably has a region where the film thickness is 0.1 nm or more and 2 nm or less. Alternatively, it more preferably has a region where the film thickness is 0.5 nm or more and 3 nm or less, and even more preferably has a region where the film thickness is 0.5 nm or more and 2 nm or less.

[0466] The film thickness of the second layer is preferably, for example, 200 nm or less. Further, when the second layer is layered, for example, it is preferably 1 nm or more and 200 nm or less, more preferably 1 nm or more and 100 nm or less, and preferably 2 nm or more and 100 nm or less.

[0467] Alternatively, if the second layer can function as a crystal nucleus, the second layer may not be layered and may be an aggregate of island-like regions. In such a case, for example, the island-like regions of the second layer are discretely present.

[0468] The preferable range of the film thickness of the third layer can be referred to the description of the film thickness of the first layer.

[0469] [Impurities in the oxide semiconductor] Here, the influence of each impurity in the oxide semiconductor will be described.

[0470] As described in the previous embodiment, in a transistor using an oxide semiconductor for the semiconductor layer, oxygen vacancies (V O) When oxygen and impurities are present, the electrical characteristics are likely to fluctuate and the reliability may deteriorate. Therefore, in order to stabilize the electrical characteristics of the OS transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Further, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, carbon, and nitrogen. Note that the impurities in the oxide semiconductor refer to, for example, components other than the main components constituting the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic% can be regarded as an impurity.

[0471] In an oxide semiconductor, when silicon or carbon, which is one of the Group 14 elements, is contained, defect levels are formed in the oxide semiconductor. Therefore, the concentration of carbon in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 20 atoms / cm 3 or less, preferably 5×10 19 atoms / cm 3 or less, more preferably 3×10 19 atoms / cm 3 or less, more preferably 1×10 19 atoms / cm 3 or less, more preferably 3×10 18 atoms / cm 3 or less, even more preferably 1×10 18 atoms / cm 3 or less. Also, the concentration of silicon in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 20 atoms / cm 3 or less, preferably 5×10 19 atoms / cm 3 or less, more preferably 3×10 19 atoms / cm 3 or less, more preferably 1×10 19 atoms / cm 3 or less, more preferably 3×10 18 atoms / cm 3 or less, even more preferably 1×10 18 atoms / cm 3 or less.

[0472] In addition, in an oxide semiconductor, when nitrogen is contained, electrons as carriers are generated, the carrier concentration increases, and it tends to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen tends to have normally-on characteristics. Or, in an oxide semiconductor, when nitrogen is contained, trap levels may be formed. As a result, the electrical characteristics of the transistor may become unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 20 atoms / cm 3 or less, preferably 5×10 19 atoms / cm 3 or less, more preferably 1×10 19 atoms / cm 3 or less, more preferably 5×10 18 atoms / cm 3 or less, more preferably 1×10 18 atoms / cm 3 or less, still more preferably 5×10 17 atoms / cm 3 or less.

[0473] In addition, since hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to form water, oxygen deficiency may be formed. When hydrogen enters the oxygen deficiency, electrons as carriers may be generated. Also, a part of hydrogen may bond with oxygen bonded to metal atoms to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen tends to have normally-on characteristics. For this reason, it is preferable that hydrogen in the channel formation region of the oxide semiconductor is reduced as much as possible. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is less than 1×10 20 atoms / cm 3 , preferably less than 5×10 19 atoms / cm 3 , more preferably less than 1×10 19 atoms / cm 3 , more preferably less than 5×1018 atoms / cm 3 less than, more preferably 1×10 18 atoms / cm 3 less than, even more preferably 1×10 17 atoms / cm 3 or less.

[0474] In addition, when an alkali metal or alkaline earth metal is contained in the oxide semiconductor, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or alkaline earth metal tends to have normally-on characteristics. For this reason, the concentration of the alkali metal or alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 18 atoms / cm 3 or less, preferably 2×10 16 atoms / cm 3 or less.

[0475] By using an oxide semiconductor with sufficiently reduced impurities in the channel formation region of the transistor, stable electrical characteristics can be imparted.

[0476] This embodiment can be appropriately combined with other embodiments. Also, in this specification, when a plurality of configuration examples are shown in one embodiment, the configuration examples can be appropriately combined.

[0477] (Embodiment 3) In this embodiment, an example of an operation method of a memory device according to one aspect of the present invention will be described. For the memory cells exemplified below, the transistor including the ferroelectric body exemplified in Embodiment 1 can be used.

[0478] [Regarding the hysteresis characteristics of the ferroelectric body] Ferroelectrics have hysteresis characteristics. FIG. 18 is a diagram showing an example of the hysteresis characteristics of ferroelectrics. The hysteresis characteristics can be measured in a capacitive element (ferroelectric capacitor) using ferroelectrics. In FIG. 18, the horizontal axis represents the voltage (electric field) applied to the ferroelectrics. The voltage is the potential difference between one electrode and the other electrode of the ferroelectric capacitor. Note that the electric field strength can be obtained by dividing the potential difference by the thickness of the ferroelectrics.

[0479] In FIG. 18, the vertical axis represents the polarization of the ferroelectrics. When the polarization is positive, it indicates that the positive charges in the ferroelectrics are biased toward one electrode side of the capacitive element, and the negative charges are biased toward the other electrode side of the capacitive element. On the other hand, when the polarization is negative, it indicates that the negative charges in the ferroelectrics are biased toward one electrode side of the capacitive element, and the positive charges are biased toward the other electrode side of the capacitive element.

[0480] Also, the polarization shown on the vertical axis of the graph in FIG. 18 may be defined as positive when the negative charges are biased toward one electrode side of the capacitive element and the positive charges are biased toward the other electrode side of the capacitive element, and negative when the positive charges are biased toward one electrode side of the capacitive element and the negative charges are biased toward the other electrode side of the capacitive element.

[0481] As shown in FIG. 18, the hysteresis characteristics of the ferroelectrics can be represented by curve 651 and curve 652. The voltages at the intersection of curve 651 and curve 652 are called the saturation polarization voltage +VSP (also referred to as “+VSP”) and the saturation polarization voltage -VSP (also referred to as “-VSP”). +VSP and -VSP can be said to have different polarities.

[0482] After applying a voltage of -VSP or less to the ferroelectric material and then increasing the voltage applied to the ferroelectric material, the polarization of the ferroelectric material increases according to curve 651. On the other hand, after applying a voltage of +VSP or more to the ferroelectric material and then decreasing the voltage applied to the ferroelectric material, the polarization of the ferroelectric material decreases according to curve 652. Note that +VSP may be referred to as the "positive saturation polarization voltage" or the "first saturation polarization voltage". Also, -VSP may be referred to as the "negative saturation polarization voltage" or the "second saturation polarization voltage". The absolute value of the first saturation polarization voltage and the absolute value of the second saturation polarization voltage may be the same or different.

[0483] When the polarization of the ferroelectric material changes according to curve 651, the voltage at which the polarization becomes 0 is called the antiferroelectric voltage +Vc. Also, when the polarization of the ferroelectric material changes according to curve 652, the voltage at which the polarization becomes 0 is called the antiferroelectric voltage -Vc. The values of +Vc and -Vc are between the values of +VSP and -VSP. Note that +Vc may be referred to as the "positive antiferroelectric voltage" or the "first antiferroelectric voltage", and -Vc may be referred to as the "negative antiferroelectric voltage" or the "second antiferroelectric voltage". The absolute value of the first antiferroelectric voltage and the absolute value of the second antiferroelectric voltage may be the same or different.

[0484] Also, when no voltage is applied to the ferroelectric material (when the voltage is 0V), the maximum value of the polarization is called the "residual polarization +Pr" or the "residual polarization Pr1", and the minimum value is called the "residual polarization -Pr" or the "residual polarization Pr2". Also, the absolute value of the difference between the residual polarization +Pr and the residual polarization -Pr is called the "residual polarization 2Pr". The larger the residual polarization 2Pr, the larger the variation range of the capacitance value of the ferroelectric capacitor due to the inversion of the polarization. The larger the residual polarization 2Pr, the more preferable.

[0485] [Relationship between the polarization of the ferroelectric material and the Id-Vg characteristics] Subsequently, a configuration in which a capacitive element having a ferroelectric material is provided in a transistor will be described. Hereinafter, the relationship between the polarization of the ferroelectric material included in the capacitive element 620 and the Id-Vg characteristics of the transistor 610 will be described.

[0486] FIG. 19(A) and FIG. 19(B) are equivalent circuit diagrams of a semiconductor device 600 including a transistor 610 and a capacitive element 620 which is a ferroelectric capacitor. The capacitive element 620 has an electrode 663 that also serves as the gate of the transistor 610, an electrode 668 connected to the wiring WL, and an insulating layer 667 therebetween. The transistor 610 has an electrode 663, an electrode 660 connected to the wiring BL, and an electrode 655 connected to the wiring SL. The electrode 660 functions as one of the source electrode and the drain electrode, and the electrode 655 functions as the other. The insulating layer 667 functions as a ferroelectric layer. In FIGS. 19(A) and 19(B), the polarization of the insulating layer 667 is schematically shown. Also, the electrode 663 can also be referred to as the node FN.

[0487] The semiconductor device 600 corresponds to the semiconductor device having the insulator 250 and the conductor 252 shown in FIG. 3(E) of Embodiment 1, and the insulating layer 667 of the capacitive element 620 corresponds to the insulator 250d2 shown in FIG. 3(E). Hereinafter, a configuration in which a capacitive element 620 which is a ferroelectric capacitor is connected to the gate of the transistor 610 will be described, but the present invention is not limited thereto. As shown in FIG. 19(C), a configuration (which can be called a FeFET) in which an insulating layer 667 which is a ferroelectric body is provided as the gate insulating layer of the transistor 610 without providing the capacitive element 620 in the semiconductor device 600 can also be adopted. Here, the electrode 663 of the transistor 610 is connected to the wiring WL. The semiconductor device 600 shown in FIG. 19(C) corresponds to the transistor 200 provided with the insulator 250 shown in FIGS. 3(A) to 3(D) in Embodiment 1. The operation principle and operation method exemplified below can also be applied to the semiconductor device 600 shown in FIG. 19(C).

[0488] FIG. 19(D) is a diagram for explaining the Id-Vg characteristics of the transistor 610 when the voltage between the source and the drain (also referred to as the “drain voltage” or “Vd”) is constant. The horizontal axis in FIG. 19(D) indicates the voltage between the source and the gate (also referred to as the “gate voltage” or “Vg”), and the vertical axis indicates the current flowing between the source and the drain (also referred to as the “drain current” or “Id”).

[0489] In FIG. 19(D), characteristic 690 shows the Id-Vg characteristics of transistor 610 when no polarization occurs in insulating layer 667 that constitutes capacitor element 620.

[0490] In FIG. 19(D), characteristic 691 shows the Id-Vg characteristics when the polarization of insulating layer 667 is the residual polarization Pr1. Also, FIG. 19(A) is a schematic diagram showing the polarization of insulating layer 667 that constitutes capacitor element 620 in characteristic 691.

[0491] Since the residual polarization Pr1 is a positive polarization, a positive voltage is generated at node FN. For this reason, the Id-Vg characteristics of characteristic 690 shift in the negative direction of Vg and become characteristic 691. That is, the threshold voltage of transistor 610 shifts in the negative direction of Vg.

[0492] In FIG. 19(D), characteristic 692 shows the Id-Vg characteristics when the polarization of insulating layer 667 is the residual polarization Pr2. Also, FIG. 19(B) is a schematic diagram showing the polarization of insulating layer 667 that constitutes capacitor element 620 in characteristic 692.

[0493] Since the residual polarization Pr2 is a negative polarization, a negative voltage is generated at node FN. For this reason, the Id-Vg characteristics of characteristic 690 shift in the positive direction of Vg and become characteristic 692. That is, the threshold voltage of transistor 610 shifts in the positive direction of Vg.

[0494] As shown in FIGS. 19(A) to 19(C), the Id-Vg characteristics of transistor 610 can be changed according to the polarization of insulating layer 667 which is a ferroelectric layer. In other words, by controlling the polarization of insulating layer 667, the threshold voltage of transistor 610 can be controlled. Therefore, semiconductor device 600 including transistor 610 and capacitor element 620 can function as a memory cell capable of holding binary data.

[0495] For example, when writing binary data of “0” or “1” to the semiconductor device 600 that functions as a memory cell, the polarization of the insulating layer 667 may be set to the residual polarization Pr1 when writing the data “1”, and the polarization of the insulating layer 667 may be set to the residual polarization Pr2 when writing the data “0”. The Id-Vg characteristic of the semiconductor device 600 in which the data “1” is written becomes characteristic 691. Also, the Id-Vg characteristic of the semiconductor device 600 in which the data “0” is written becomes characteristic 692.

[0496] Subsequently, the erasing operation, writing operation, holding operation, and reading operation of the semiconductor device 600 will be described.

[0497] <Erasing operation> Before writing data to the semiconductor device 600 that functions as a memory cell, it is necessary to erase the data. In the present embodiment, an operation of writing the data “0” to the semiconductor device 600 is performed as the erasing operation. That is, the polarization of the insulating layer 667 is set to the residual polarization Pr2.

[0498] FIG. 20(A) is a timing chart for explaining the erasing operation. FIG. 20(B) is a circuit diagram showing the state of the semiconductor device 600 in the period T11. In the circuit diagram or the like, in order to clearly show the potential of the wiring or the like, a symbol indicating the potential of the wiring may be marked adjacent to the wiring or the like. Also, in the wiring or the like where a potential change has occurred, the symbol indicating the potential may be enclosed and marked with a character.

[0499] In the period T11, a potential L is supplied to the wiring WL, and a potential H is supplied to the wiring BL and the wiring SL.

[0500] Note that between the wiring WL and the wiring BL, and between the wiring WL and the wiring SL, the gate capacitance of the transistor 610 and the capacitance element 620 are connected in series. The voltage applied to the capacitance element 620 is determined by the capacitance ratio between the gate capacitance of the transistor 610 and the capacitance element 620. In the present embodiment, it is assumed that the capacitance ratio between the gate capacitance of the transistor 610 and the capacitance element 620 is 1:1. Therefore, the potential difference between the potential H and the potential L is set to be twice or more the absolute value of VSP. Further, in order to set the polarization of the insulating layer 667 to the residual polarization Pr2, the potential H is supplied to the wiring BL and the wiring SL, and the potential L is supplied to the wiring WL. The potential H is a potential higher than the potential L.

[0501] For example, when the potential COM is used as the reference potential (0V), the potential H may be a potential higher than the potential COM, and the potential difference between the potential H and the potential COM is +VSP. Similarly, the potential L may be a potential lower than the potential COM, and the potential difference between the potential L and the potential COM is -VSP.

[0502] Under the above conditions, by supplying the potential L to the wiring WL and the potential H to the wiring BL and the wiring SL, -VSP is applied to the capacitance element 620. Subsequently, in the period T12, 0V is supplied to the wiring WL, the wiring BL, and the wiring SL. That is, the wiring WL, the wiring BL, and the wiring SL are set to the same potential.

[0503] In the period T12, the polarization of the insulating layer 667 becomes the residual polarization Pr2 (see FIG. 18). As described above, since the residual polarization Pr2 is a negative polarization, a negative voltage is generated at the node FN. For this reason, the Id-Vg characteristic of the characteristic 690 shifts in the positive direction of Vg and becomes the characteristic 692. That is, the threshold voltage of the transistor 610 shifts in the positive direction of Vg (see FIG. 19(D)).

[0504] In the period T13, the potential RL is supplied to the wiring WL. The potential RL will be described in detail in the description of the holding operation. Note that the period T12 may be omitted, and the period T13 may be performed after the period T11. By passing through the period T11, a negative voltage is generated at the node FN even if the period T12 is omitted.

[0505] <Write operation> Next, the operation of writing data "1" to the semiconductor device 600 functioning as a memory cell will be described. FIG. 21(A) is a timing chart for explaining the write operation. FIG. 21(B) is a circuit diagram showing the state of the semiconductor device 600 in period T21.

[0506] After performing the erase operation in period T11, in period T21, a potential H is supplied to the wiring WL, and potentials L are supplied to the wiring BL and the wiring SL. Then, +VSP is applied to the capacitive element 620, and the polarization of the insulating layer 667 changes along the curve 651 (see FIG. 18). Subsequently, in period T22, 0V is supplied to the wiring WL, the wiring BL, and the wiring SL. That is, the wiring WL, the wiring BL, and the wiring SL are set to the same potential.

[0507] In period T22, the polarization of the insulating layer 667 becomes the residual polarization Pr1 (see FIG. 18). As described above, since the residual polarization Pr1 is a positive polarization, a positive voltage is generated at the node FN. For this reason, the Id-Vg characteristic of the characteristic 690 shifts in the negative direction of Vg and becomes the characteristic 691. That is, the threshold voltage of the transistor 610 shifts in the negative direction of Vg (see FIG. 19(D)).

[0508] In this way, data "1" can be written to the semiconductor device 600. Further, since the capacitive element 620 is a ferroelectric capacitor, the polarization of the insulating layer 667, which is a ferroelectric body, is maintained even when the power supply to the semiconductor device 600 is cut off. Therefore, the data written to the semiconductor device 600 is maintained even when the power supply to the semiconductor device 600 is cut off. Therefore, the semiconductor device 600 functions as a non-volatile memory cell.

[0509] The operation of writing data "0" to the semiconductor device 600 is the same as the above-described erase operation. For this reason, it is not necessary to perform the operation of writing data "0" after the erase operation.

[0510] <Retention operation> After writing data to the semiconductor device 600, at time period T23, a potential RL is supplied to the wiring WL. The potential RL is a potential at which the transistor 610 is turned off even if the Id-Vg characteristic of the transistor 610 is characteristic 691 (see Fig. 19(D)). Therefore, the potential RL may be set to a potential lower than the threshold voltage of characteristic 691. Further, in order to make it difficult for the polarization of the insulating layer 667 to change, the potential RL is set to a voltage such that the voltage applied to the capacitor element 620 is equal to or higher than the counter voltage -Vc.

[0511] After the write operation is completed, it is preferable that the potential of the wiring WL be the potential RL until the read operation is performed. By setting the potential of the wiring WL to the potential RL, the transistor 610 is surely turned off, so that the power consumption of the semiconductor device 600 is reduced. Further, when the semiconductor devices 600 are arranged in a matrix to form a memory cell array, interference with the read operations of other memory cells (semiconductor devices 600) can be prevented. Therefore, the reliability of the memory cell array can be improved.

[0512] Note that the time period T22 may be omitted, and the time period T23 may be performed after the time period T21.

[0513] <Read operation> Next, a read operation of data held by the semiconductor device 600 functioning as a memory cell will be described. Fig. 22(A) is a timing chart for explaining the read operation. Fig. 22(B) is a circuit diagram showing the state of the semiconductor device 600 at time period T31.

[0514] In the present embodiment, a read operation of the semiconductor device 600 holding the data "1" will be described.

[0515] At time period T31, the potential H is precharged to the wiring BL. That is, after the potential of the wiring BL is set to the potential H, the wiring BL is put into a floating state (a state where no power is supplied from anywhere). Also, the potential COM is supplied to the wiring SL.

[0516] Subsequently, in period T32, a potential RH, which is a read potential, is supplied to the wiring WL. The potential RH is a potential that is equal to or higher than the threshold voltage of characteristic 691 and lower than the threshold voltage of characteristic 692. Also, in order to make it difficult for the polarization of the insulating layer 667 to change, the potential RH is set to a voltage such that the voltage applied to the capacitive element 620 is equal to or lower than the counter voltage +Vc.

[0517] When data "1" is held in the semiconductor device 600, when the potential RH is supplied to the wiring WL, the transistor 610 is turned on, and a current Id1 flows between the source and the drain (see Fig. 19(D)). Therefore, the wiring BL and the wiring SL are brought into a conductive state, and the potential of the floating wiring BL changes toward the potential COM.

[0518] After supplying the potential RH to the wiring WL, if there is a change in the potential of the wiring BL, it can be determined that data "1" is written in the semiconductor device 600. Also, when it is determined that the potential of the wiring BL does not change even when the potential RH is supplied to the wiring WL, it can be determined that data "0" is written in the semiconductor device 600.

[0519] After the read operation is completed, in period T33, a potential RL is supplied to the wiring WL. By setting the potential RH to a voltage such that the voltage applied to the capacitive element 620 is equal to or lower than the counter voltage +Vc, the polarization of the insulating layer 667 constituting the capacitive element 620 becomes difficult to change. Therefore, non-destructive readout of the semiconductor device 600 can be realized.

[0520] Note that the hysteresis characteristics of the ferroelectric material vary depending on the material, configuration, and manufacturing method. Therefore, the potential RH is preferably a voltage such that the voltage applied to the capacitive element 620 is equal to or lower than 0.8 times the counter voltage +Vc, and more preferably equal to or lower than 0.6 times the counter voltage +Vc. Also, the potential RL is preferably a voltage such that the voltage applied to the capacitive element 620 is equal to or higher than 0.8 times the counter voltage -Vc, and more preferably equal to or higher than 0.6 times the counter voltage -Vc.

[0521] The above is the description of the operation method of the memory device.

[0522] This embodiment can be implemented in appropriate combination with other embodiments described in this specification, at least in part.

[0523] (Embodiment 4) In this embodiment, a semiconductor device 900 according to one aspect of the present invention will be described. The semiconductor device 900 can function as a storage device.

[0524] FIG. 23 shows a block diagram of a configuration example of the semiconductor device 900. The semiconductor device 900 shown in FIG. 23 includes a drive circuit 910 and a memory array 920. The memory array 920 includes one or more memory cells 950. FIG. 23 shows an example in which the memory array 920 includes a plurality of memory cells 950 arranged in a matrix.

[0525] The transistor exemplified in Embodiment 1 can be applied to the memory cell 950. By using the above transistor, the operation speed of the storage device can be improved. In addition, miniaturization and high integration of the storage device can be achieved. Further, the capacity per area of the storage device can be increased.

[0526] The drive circuit 910 includes a PSW 931 (power switch), a PSW 932, and a peripheral circuit 915. The peripheral circuit 915 includes a peripheral circuit 911, a control circuit 912 (Control Circuit), and a voltage generation circuit 928.

[0527] In the semiconductor device 900, each circuit, each signal, and each voltage can be appropriately selected or discarded as necessary. Alt...

Claims

1. An oxide semiconductor, a first conductor and a second conductor spaced apart from each other on the oxide semiconductor, a first insulator disposed on the first conductor and the second conductor and having an opening that overlaps a region between the first conductor and the second conductor, a second insulator disposed in the opening and in contact with an upper surface of the oxide semiconductor, side surfaces of the first conductor, side surfaces of the second conductor, and side surfaces of the first insulator, a third conductor disposed in the opening on the second insulator and having a region that overlaps the oxide semiconductor via the second insulator, the oxide semiconductor having, in a region overlapping the third conductor, a first layer, a second layer on the first layer, and a third layer on the second layer, the first layer having gallium and oxygen, the second layer having indium oxide, the third layer having indium, gallium, and oxygen, a semiconductor device, wherein a content rate of indium in the second layer is higher than a content rate of indium in the third layer.

2. The semiconductor device according to claim 1, wherein a lower end of a conduction band of the first layer is located closer to a vacuum level side than a lower end of a conduction band of the second layer, and a lower end of a conduction band of the third layer is located closer to a vacuum level side than a lower end of a conduction band of the second layer.

3. The semiconductor device according to claim 1, wherein the first layer has indium, and a content rate of indium in the first layer is lower than a content rate of gallium in the first layer.

4. The semiconductor device according to claim 1, wherein side surfaces of a part of the first insulator coincide with or substantially coincide with side surfaces of the first conductor and side surfaces of the second conductor in a plan view.

5. The semiconductor device according to claim 1, further comprising a third insulator in contact with an upper surface of the third conductor, an upper end portion of the second insulator, and an upper surface of the first insulator, and a fourth insulator in contact with an upper surface of the third insulator.

6. The semiconductor device according to claim 5, wherein the third insulator has aluminum oxide.

7. The semiconductor device according to claim 6, wherein the fourth insulator has silicon nitride.

8. The semiconductor device according to claim 1, wherein each of the first conductor and the second conductor has a first conductive layer and a second conductive layer on the first conductive layer. ​ ​ ​ ​ ​ The shortest distance between the first conductive layer of the first conductor and the first conductive layer of the second conductor is smaller than the shortest distance between the second conductive layer of the first conductor and the second conductive layer of the second conductor. Semiconductor device.

9. In claim 8, A part of the side surface of the first insulator coincides with or substantially coincides with the side surface of the second conductive layer of the first conductor and the side surface of the second conductive layer of the second conductor in a plan view. Semiconductor device.

10. In claim 8, The first conductive layer of the first conductor and the first conductive layer of the second conductor include tantalum nitride. Semiconductor device.

11. In claim 8, It has a fifth insulator, The fifth insulator is disposed in the opening and is in contact with the upper surface of the first conductive layer of the first conductor, the side surface of the second conductive layer of the first conductor, the upper surface of the first conductive layer of the second conductor, and the side surface of the second conductive layer of the second conductor. The fifth insulator has an opening that overlaps with the region between the first conductive layer of the first conductor and the first conductive layer of the second conductor. Semiconductor device.

12. In claim 11, The fifth insulator includes silicon nitride. Semiconductor device.

13. In any one of claims 1 to 12, The second insulator has a first insulating layer, The first insulating layer includes an oxide containing hafnium. Semiconductor device.

14. In claim 13, The first insulating layer includes hafnium zirconium oxide. Semiconductor device.

15. In claim 14, The second insulator has a second insulating layer on the first insulating layer, The second insulating layer includes silicon nitride. Semiconductor device.

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