Electronic component

Abstract

To provide an electronic component that can be made compact while having desired characteristics.SOLUTION: An electronic component 1 comprises a first main body 50 and a second main body 80. The second main body 80 is mounted on a first surface 50A of the first main body 50. The first main body 50 includes a first region R1 overlapping with the second main body 80 when viewed from a lamination direction T, and a second region R2 not overlapping with the second main body 80 when viewed from the lamination direction T. At least some of a plurality of capacitor conductors are arranged in the first region R1. At least one inductor conductor includes a principal part arranged in the second region R2 and a non-principal part. The non-principal part is arranged in the second region R2, or arranged at least in part in the first region R1.SELECTED DRAWING: Figure 12

Description

Technical Field

[0001] The present invention relates to an electronic component including a main body and a mounted component mounted on the main body.

Background Art

[0002] Filters such as low-pass filters, high-pass filters, and band-pass filters are configured using a plurality of resonators. As resonators used in these filters, for example, LC resonators configured using an inductor and a capacitor, and elastic wave resonators configured using elastic wave elements are known. An elastic wave element is an element that utilizes elastic waves. Elastic wave elements include surface acoustic wave elements that utilize surface acoustic waves and bulk elastic wave elements that utilize bulk elastic waves.

[0003] As filter devices, in addition to filter devices configured using only LC resonators or only elastic wave resonators, hybrid filter devices configured using LC resonators and elastic wave resonators are known. For example, Patent Document 1 discloses a hybrid filter device including an elastic wave device including an elastic wave resonator and a passive device including an inductor element or an inductor element and a capacitor element.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In a hybrid filter device, generally, it is divided into a first component including a surface acoustic wave resonator and a second component including other components. The second component may be one or a plurality. From the viewpoint of miniaturizing the filter device, it is preferable to mount one of the first component and the second component on the other of the first component and the second component. However, when an inductor is included in the second component, depending on the shape and arrangement of the inductor, an electromagnetic field may interact between the inductor and the first component, and desired characteristics may not be obtained.

[0006] The above problem applies not only when the first component includes a surface acoustic wave resonator, but also when the first component includes any active element or any passive element such as a high-frequency switch.

[0007] The present invention has been made in view of such problems, and an object thereof is to provide an electronic component including a main body and a mounted component mounted on the main body, which can be miniaturized while realizing desired characteristics.

Means for Solving the Problems

[0008] The electronic component of the present invention includes a first main body including a plurality of stacked dielectric layers, a plurality of conductors, and a first circuit configured using the plurality of conductors, and a second main body including a second circuit connected to the first circuit. The first main body has a first surface located at an end in the stacking direction of the plurality of dielectric layers. The second main body is mounted on the first surface. The first main body includes a first region overlapping the second main body when viewed from the stacking direction and a second region not overlapping the second main body when viewed from the stacking direction. The plurality of conductors include a plurality of capacitor conductors for forming at least one capacitor and at least one inductor conductor for forming at least one inductor. At least a part of the plurality of capacitor conductors is arranged in the first region. The at least one inductor conductor includes a main part arranged in the second region and a non-main part. The non-main part is arranged in the second region or at least a part thereof is arranged in the first region.

Advantages of the Invention

[0009] In the electronic component of the present invention, at least a part of a plurality of capacitor conductors is arranged in a first region. The main part of at least one inductor conductor is arranged in a second region. The non-main part of at least one inductor conductor is arranged in the second region or at least a part thereof is arranged in the first region. Thus, according to the present invention, there is an effect that it is possible to miniaturize while realizing desired characteristics.

Brief Description of the Drawings

[0010]

Figure 1

Figure 2

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Figure 8

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Figure 11

Figure 12

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Figure 16

[0011] [First Embodiment] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. First, the schematic configuration of the electronic component 1 according to the first embodiment of the present invention will be described. The electronic component 1 according to the present embodiment is a band-pass filter that selectively passes signals having frequencies within a predetermined passband.

[0012] The electronic component 1 according to the present embodiment is a so-called hybrid type filter including at least one LC resonator configured using at least one inductor and at least one capacitor, and an elastic wave resonator configured using at least one elastic wave element. The at least one elastic wave element may be, for example, a bulk elastic wave element or a surface acoustic wave element.

[0013] Next, with reference to FIG. 1, an example of the circuit configuration of the electronic component 1 will be described. FIG. 1 is a circuit diagram showing the circuit configuration of the electronic component 1. The electronic component 1 includes a first input / output terminal 2, a second input / output terminal 3, and a first circuit provided between the first input / output terminal 2 and the second input / output terminal 3 in terms of circuit configuration. In the present application, the expression "in terms of circuit configuration" is used to refer to the arrangement on the circuit diagram rather than the arrangement in the physical configuration.

[0014] Each of the first and second input / output terminals 2 and 3 is a terminal for inputting or outputting a signal. That is, when a signal is input to the first input / output terminal 2, a signal is output from the second input / output terminal 3. When a signal is input to the second input / output terminal 3, a signal is output from the first input / output terminal 2.

[0015] The first circuit includes inductors L1, L2, L3, L5, L6, L7 and capacitors C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11. One end of the inductor L1 is connected to the first input / output terminal 2. One end of the inductor L2 is connected to the other end of the inductor L1.

[0016] One end of the capacitor C4 is connected to the other end of the inductor L2. One end of the capacitor C5 is connected to the other end of the capacitor C4. One end of the capacitor C6 is connected to the other end of the capacitor C5. One end of the capacitor C7 is connected to the other end of the capacitor C6. One end of the capacitor C8 is connected to the other end of the capacitor C7.

[0017] One end of the capacitor C11 is connected to the other end of the capacitor C8. One end of the inductor L7 is connected to the other end of the capacitor C11. The other end of the inductor L7 is connected to the second input / output terminal 3.

[0018] The capacitor C1 is connected in parallel to the inductor L1. One end of the capacitor C2 is connected to the connection point between the inductor L1 and the inductor L2. One end of the capacitor C3 is connected to the connection point between the inductor L2 and the capacitor C4. The other ends of the capacitors C2 and C3 are connected to the ground.

[0019] One end of the inductor L3 is connected to the connection point between the capacitor C4 and the capacitor C5. One end of the inductor L5 is connected to the connection point between the capacitor C6 and the capacitor C7. The other ends of the inductors L3 and L5 are connected to the ground.

[0020] One end of the inductor L6 is connected to the connection point between the capacitor C8 and the capacitor C11. One end of the capacitor C10 is connected to the other end of the inductor L6. The other end of the capacitor C10 is connected to the ground.

[0021] One end of the capacitor C9 is connected to one end of the capacitor C5. The other end of the capacitor C9 is connected to the other end of the capacitor C8.

[0022] The electronic component 1 further includes a second circuit connected to the first circuit. The second circuit includes signal terminals 81, 82, 83, 84, a surface acoustic wave device 31 disposed between the signal terminals 81 and 82 in the circuit configuration, and a surface acoustic wave device 32 disposed between the signal terminals 83 and 84 in the circuit configuration.

[0023] The first circuit further includes signal terminals 11, 12, 13, 14 respectively connected to the signal terminals 81, 82, 83, 84. In FIG. 1, for convenience, the signal terminal 12 is depicted as intervening between one end of the capacitor C9 and one end of the capacitor C5. However, the signal terminal 12 does not necessarily have to intervene between one end of the capacitor C9 and one end of the capacitor C5.

[0024] Capacitor C4 is connected in parallel to the surface acoustic wave device 31. The other end of inductor L2 and one end of each of capacitors C3 and C4 are connected to one end of the surface acoustic wave device 31 via signal terminals 11 and 81 in sequence. One end of inductor L3, the other end of capacitor C4, and one end of capacitor C5 are connected to the other end of the surface acoustic wave device 31 via signal terminals 12 and 82 in sequence.

[0025] The other end of capacitor C5 and one end of capacitor C6 are connected to one end of the surface acoustic wave device 32 via signal terminals 13 and 83 in sequence. The first circuit further includes inductor L4. One end of inductor L4 is connected to the other end of the surface acoustic wave device 32 via signal terminals 14 and 84 in sequence. The other end of inductor L4 is connected to the ground.

[0026] Next, with reference to FIGS. 2 to 4, other configurations of the electronic component 1 will be described. FIG. 2 is a perspective view showing the electronic component 1. FIGS. 3 and 4 are perspective views showing the first main body.

[0027] The electronic component 1 includes a first main body 50. The first main body 50 includes a plurality of stacked dielectric layers and a plurality of conductors (a plurality of conductor layers and a plurality of through holes). Further, the first main body 50 includes a first circuit including inductors L1 to L7 and capacitors C1 to C11 shown in FIG. 1. Inductors L1 to L7 and capacitors C1 to C11 are configured using a plurality of conductors. Each of the plurality of dielectric layers is made of a dielectric material. As the dielectric material, for example, low temperature co-fired ceramics (LTCC) is used.

[0028] The first main body 50 has a first surface 50A and a second surface 50B located at both ends in the stacking direction T of the plurality of dielectric layers, and four side surfaces 50C to 50F connecting the first surface 50A and the second surface 50B. Side surfaces 50C and 50D face opposite sides, and side surfaces 50E and 50F also face opposite sides. Side surfaces 50C to 50F are perpendicular to the first surface 50A and the second surface 50B.

[0029] Here, as shown in FIGS. 2 to 4, the X direction, Y direction, and Z direction are defined. The X direction, Y direction, and Z direction are orthogonal to each other. In the present embodiment, one direction parallel to the stacking direction T is defined as the Z direction. Also, the direction opposite to the X direction is defined as the -X direction, the direction opposite to the Y direction is defined as the -Y direction, and the direction opposite to the Z direction is defined as the -Z direction. Further, the expression "when viewed from a predetermined direction (for example, the Z direction)" means viewing an object from a position separated by a predetermined direction or a direction parallel to the predetermined direction.

[0030] As shown in FIGS. 3 and 4, the first surface 50A is located at the end of the first main body 50 in the Z direction. The first surface 50A is also the upper surface of the first main body 50 and is also a mounting surface for mounting a second main body described later. The second surface 50B is located at the end of the first main body 50 in the -Z direction. The second surface 50B is also the bottom surface of the first main body 50. FIG. 3 shows the first main body 50 viewed from the first surface 50A side. FIG. 4 shows the first main body 50 viewed from the second surface 50B side.

[0031] The side surface 50C is located at the end of the first main body 50 in the -X direction. The side surface 50D is located at the end of the first main body 50 in the X direction. The side surface 50E is located at the end of the first main body 50 in the -Y direction. The side surface 50F is located at the end of the first main body 50 in the Y direction.

[0032] The first main body 50 further includes a plurality of electrodes 111, 112, 113, 114, 115, 116, 117, 118, 119 provided on the second surface 50B of the first main body 50. The electrodes 111, 112, 113 are arranged in this order in the X direction at a position closer to the side surface 50E than the side surface 50F. The electrodes 115, 116, 117 are arranged in this order in the -X direction at a position closer to the side surface 50F than the side surface 50E.

[0033] Electrode 114 is disposed between electrode 113 and electrode 115. Electrode 118 is disposed between electrode 111 and electrode 117. Electrode 119 is disposed between electrode 112 and electrode 116. Also, electrode 119 is disposed substantially at the center of the second surface 50B.

[0034] Electrode 118 corresponds to the first input / output terminal 2. Electrode 114 corresponds to the second input / output terminal 3. Accordingly, the first and second input / output terminals 2, 3 are provided on the second surface 50B of the first body 50. Each of electrodes 111, 112, 113, 115, 116, 117, 119 is connected to ground.

[0035] The first body 50 further includes a plurality of electrodes 121, 122, 123, 124 provided on the first surface 50A of the first body 50. Electrodes 121, 122 are arranged in this order in the X direction at a position closer to the side surface 50E than the side surface 50F. Electrodes 123, 124 are arranged in this order in the -X direction at a position closer to the side surface 50F than the side surface 50E.

[0036] Electrode 121 corresponds to the signal terminal 11. Electrode 122 corresponds to the signal terminal 12. Electrode 123 corresponds to the signal terminal 13. Electrode 124 corresponds to the signal terminal 14. Accordingly, the signal terminals 11 to 14 are provided on the first surface 50A of the first body 50.

[0037] The electronic component 1 further includes a second body 80 mounted on the first surface 50A of the first body 50. The second body 80 includes a second circuit including the surface acoustic wave elements 31, 32 shown in FIG. 1.

[0038] The second main body 80 further includes four electrodes that respectively constitute signal terminals 81, 82, 83, and 84. In FIG. 2, for convenience, the four electrodes are shown with reference numerals 81 to 84 attached. In a state where the second main body 80 is mounted on the first main body 50, the four electrodes with reference numerals 81 to 84 respectively face the electrodes 121 to 124 of the first main body 50. The four electrodes with reference numerals 81 to 84 are physically connected to the electrodes 121 to 124 by, for example, solder bumps 7.

[0039] In the example shown in FIG. 2, the second main body 80 is arranged so as to overlap the center of gravity of the first surface 50A when viewed from the stacking direction T. The center of gravity of the second main body 80 when viewed from the stacking direction T may or may not coincide with the center of gravity of the first surface 50A.

[0040] The electronic component 1 further includes a sealing portion 90 that seals the second main body 80. The sealing portion 90 covers at least a part of the periphery of the second main body 80 and the first surface 50A of the first main body 50. The sealing portion 90 may further cover the side surfaces 50C to 50F of the first main body 50. The sealing portion 90 is made of, for example, resin.

[0041] Next, with reference to FIGS. 5(a) to 10(c), an example of a plurality of dielectric layers, a plurality of conductor layers, and a plurality of through holes that constitute the first main body 50 will be described. In this example, the first main body 50 includes 19 stacked dielectric layers. Hereinafter, these 19 dielectric layers will be referred to as the first dielectric layer to the 19th dielectric layer in order from the bottom. Also, the first dielectric layer to the 19th dielectric layer are represented by reference numerals 51 to 69.

[0042] In FIGS. 5(a) to 10(b), the plurality of circles represent a plurality of through holes. A plurality of through holes are formed in each of the dielectric layers 51 to 69. The plurality of through holes are each formed by filling a conductor paste into a hole for the through hole. Each of the plurality of through holes is connected to an electrode, a conductor layer, or another through hole.

[0043] In FIGS. 5(a) to 10(b), a plurality of specific through-holes among the plurality of through-holes are marked with symbols. Regarding the connection relationship between each of the plurality of specific through-holes and the electrodes, conductor layers, or other through-holes, the connection relationship in the state where the dielectric layers 51 to 69 of the first layer to the nineteenth layer are laminated is described.

[0044] FIG. 5(a) shows the pattern formation surface of the first dielectric layer 51. Electrodes 111 to 119 are formed on the pattern formation surface of the dielectric layer 51.

[0045] FIG. 5(b) shows the pattern formation surface of the second dielectric layer 52. Conductor layers 521, 522, 523, 524, and 525 are formed on the pattern formation surface of the dielectric layer 52. The conductor layer 525 is connected to the conductor layer 523. In FIG. 5(b), the boundary between the conductor layer 523 and the conductor layer 525 is indicated by a dotted line.

[0046] FIG. 5(c) shows the pattern formation surface of the third dielectric layer 53. Conductor layers 531, 532, and 533 are formed on the pattern formation surface of the dielectric layer 53. The through-hole marked with reference numeral 53T1a in FIG. 5(c) is connected to the conductor layer 531. In the following description, the through-hole marked with reference numeral 53T1a is simply referred to as through-hole 53T1a. Also, for through-holes marked with symbols other than through-hole 53T1a, they are referred to in the same manner as through-hole 53T1a.

[0047] FIG. 6(a) shows the pattern formation surface of the fourth dielectric layer 54. A conductor layer 541 is formed on the pattern formation surface of the dielectric layer 54. The through-hole 54T1b shown in FIG. 6(a) is connected to the conductor layer 541. The through-hole 53T1a is connected to the through-hole 54T1a shown in FIG. 6(a).

[0048] FIG. 6(b) shows the pattern formation surfaces of the fifth and sixth dielectric layers 55 and 56. The through-holes 54T1a and 54T1b are respectively connected to the through-holes 55T1a and 55T1b formed in the dielectric layer 55. Also, in the dielectric layers 55 and 56, the through-holes with the same reference numerals adjacent to each other vertically are connected to each other.

[0049] FIG. 6(c) shows the pattern formation surface of the seventh dielectric layer 57. A conductor layer 571 is formed on the pattern formation surface of the dielectric layer 57. The through-holes 55T1a and 55T1b formed in the dielectric layer 56 are respectively connected to the through-holes 57T1a and 57T1b shown in FIG. 6(c).

[0050] FIG. 7(a) shows the pattern formation surfaces of the eighth and ninth dielectric layers 58 and 59. The through-holes 57T1a and 57T1b are respectively connected to the through-holes 58T1a and 58T1b formed in the dielectric layer 58. Also, in the dielectric layers 58 and 59, the through-holes with the same reference numerals adjacent to each other vertically are connected to each other.

[0051] FIG. 7(b) shows the pattern formation surface of the tenth dielectric layer 60. Conductor layers 602, 606, and 607 for an inductor are formed on the pattern formation surface of the dielectric layer 60. The through-holes 58T1a and 58T1b formed in the dielectric layer 59 are respectively connected to the through-holes 60T1a and 60T1b shown in FIG. 7(b).

[0052] FIG. 7(c) shows the pattern formation surface of the eleventh dielectric layer 61. Conductor layers 612, 614, 616, and 617 for an inductor are formed on the pattern formation surface of the dielectric layer 61. The through-holes 60T1a and 60T1b are respectively connected to the through-holes 61T1a and 61T1b shown in FIG. 7(c).

[0053] FIG. 8(a) shows the pattern formation surface of the 12th dielectric layer 62. Conductor layers 622, 623, 626, and 627 for inductors are formed on the pattern formation surface of the dielectric layer 62. Through holes 61T1a and 61T1b are respectively connected to through holes 62T1a and 62T1b shown in FIG. 8(a).

[0054] FIG. 8(b) shows the pattern formation surface of the 13th dielectric layer 63. Conductor layers 632, 633, 635, 636, and 637 for inductors are formed on the pattern formation surface of the dielectric layer 63. Through holes 62T1a and 62T1b are respectively connected to through holes 63T1a and 63T1b shown in FIG. 8(b).

[0055] FIG. 8(c) shows the pattern formation surface of the 14th dielectric layer 64. Conductor layers 641a, 641b, 642, 643, 644, 646, 647, 648 and a conductor layer 645 for an inductor are formed on the pattern formation surface of the dielectric layer 64. The conductor layer 646 is connected to the conductor layer 644. In FIG. 8(c), the boundary between the conductor layer 644 and the conductor layer 646 is shown by a dotted line. The through hole 63T1a and the through hole 64T1a shown in FIG. 8(c) are connected to the conductor layer 641a. The through hole 63T1b and the through hole 64T1b shown in FIG. 8(c) are connected to the conductor layer 641b.

[0056] FIG. 9(a) shows the pattern formation surface of the 15th dielectric layer 65. Conductor layers 651, 652, 653, and 654 are formed on the pattern formation surface of the dielectric layer 65. The conductor layer 654 is connected to the conductor layer 653. In FIG. 9(a), the boundary between the conductor layer 653 and the conductor layer 654 is shown by a dotted line. The through holes 64T1a and 64T1b are respectively connected to the through holes 65T1a and 65T1b shown in FIG. 9(a).

[0057] Figure 9(b) shows the pattern formation surface of the 16th dielectric layer 66. Conductor layers 661, 662, and 663 are formed on the pattern formation surface of the dielectric layer 66. The conductor layer 662 is connected to the conductor layer 661. In Figure 9(b), the boundary between the conductor layer 661 and the conductor layer 662 is indicated by a dotted line. The through holes 65T1a and 65T1b are connected to the through holes 66T1a and 66T1b shown in Figure 9(b), respectively. The through hole 66T3 shown in Figure 9(b) is connected to the conductor layer 661.

[0058] Figure 9(c) shows the pattern formation surface of the 17th dielectric layer 67. Conductor layers 671, 672, 673, 675, 676, and 677 for an inductor are formed on the pattern formation surface of the dielectric layer 67. The conductor layer 671 has a first end and a second end that are located on opposite sides of each other in the longitudinal direction of the conductor layer 671. The through hole 66T1a and the through hole 67T1a shown in Figure 9(c) are connected to the vicinity of the first end of the conductor layer 671. The through hole 66T1b and the through hole 67T1b shown in Figure 9(c) are connected to the vicinity of the second end of the conductor layer 671. The through hole 66T3 is connected to the through hole 67T3 shown in Figure 9(c).

[0059] Figure 10(a) shows the pattern formation surface of the 18th dielectric layer 68. Conductor layers 681, 682, 683, 684, 685, 686, and 687 for an inductor are formed on the pattern formation surface of the dielectric layer 68. The conductor layer 681 has a first end and a second end that are located on opposite sides of each other in the longitudinal direction of the conductor layer 681. The through hole 67T1a is connected to the vicinity of the first end of the conductor layer 681. The through hole 67T1b is connected to the vicinity of the second end of the conductor layer 681. The through holes 68T1, 68T2, and 68T4 shown in Figure 10(a) are connected to the conductor layers 682, 683, and 684, respectively. The through hole 67T3 is connected to the through hole 68T3 shown in Figure 10(a).

[0060] FIG. 10(b) shows the pattern formation surface of the 19th dielectric layer 69. Conductor layers 691, 692, 693, and 694 are formed on the pattern formation surface of the dielectric layer 69. Through hole 68T1 and through hole 69T1 shown in FIG. 10(b) are connected to conductor layer 691. Through hole 68T2 and through hole 69T2 shown in FIG. 10(b) are connected to conductor layer 692. Through hole 68T3 and through hole 69T3 shown in FIG. 10(b) are connected to conductor layer 693. Through hole 68T4 and through hole 69T4 shown in FIG. 10(b) are connected to conductor layer 694.

[0061] FIG. 10(c) shows the surface opposite to the pattern formation surface of the 19th dielectric layer 69. Hereinafter, the surface opposite to the pattern formation surface of the dielectric layer 69 is referred to as the electrode formation surface of the dielectric layer 69. Electrodes 121, 122, 123, and 124 are formed on the electrode formation surface of the dielectric layer 69. Through holes 69T1, 69T2, 69T3, and 69T4 are connected to electrodes 121, 122, 123, and 124, respectively.

[0062] The first main body 50 is configured by laminating dielectric layers 51 to 69 of the first layer to the 19th layer such that the pattern formation surface of the first dielectric layer 51 becomes the second surface 50B of the first main body 50, and the electrode formation surface of the 19th dielectric layer 69 becomes the first surface 50A of the first main body 50.

[0063] Each of the plurality of through holes shown in FIGS. 5(a) to 10(b) is connected to a conductor layer overlapping in the stacking direction T or another through hole overlapping in the stacking direction T when the dielectric layers 51 to 69 of the first layer to the 19th layer are stacked. Among the plurality of through holes shown in FIGS. 5(a) to 10(b), the through holes located within the electrodes or the conductor layers are connected to those electrodes or those conductor layers.

[0064] FIG. 11 shows the inside of a first main body 50 configured by laminating dielectric layers 51 to 69 of the first layer to the nineteenth layer. As shown in FIG. 11, inside the first main body 50, a plurality of conductor layers and a plurality of through holes shown in FIGS. 5(a) to 10(c) are laminated.

[0065] Hereinafter, the correspondence between the components of the circuit of the electronic component 1 shown in FIG. 1 and the components inside the first main body 50 shown in FIGS. 5(a) to 10(c) will be described. Inductor L1 is composed of conductor layers 671 and 681 for an inductor, conductor layers 641a and 641b, and through holes 53T1a, 54T1a, 54T1b, 55T1a, 55T1b, 57T1a, 57T1b, 58T1a, 58T1b, 60T1a, 60T1b, 61T1a, 61T1b, 62T1a, 62T1b, 63T1a, 63T1b, 64T1a, 64T1b, 65T1a, 65T1b, 66T1a, 66T1b, 67T1a, 67T1b.

[0066] Inductor L2 is composed of conductor layers 602, 612, 622, 632, 672, and 682 for an inductor, and a plurality of through holes connecting these conductor layers. Conductor layer 682 is connected to electrode 121 via through hole 68T1, conductor layer 691, and through hole 69T1.

[0067] Inductor L3 is composed of conductor layers 623, 633, 673, and 683 for an inductor, and a plurality of through holes connecting these conductor layers. Conductor layer 683 is connected to electrode 122 via through hole 68T2, conductor layer 692, and through hole 69T2.

[0068] Inductor L4 is composed of conductor layers 614 and 684 for the inductor, conductor layers 533 and 571, a plurality of through holes connecting the conductor layers 614 and 684, a plurality of through holes connecting the conductor layers 571 and 614, a plurality of through holes connecting the conductor layers 533 and 571, and a through hole connecting the conductor layers 525 and 533. The conductor layer 684 is connected to the electrode 124 via the through hole 68T4, the conductor layer 694, and the through hole 69T4.

[0069] Inductor L5 is composed of conductor layers 635, 645, 675, and 685 for the inductor and a plurality of through holes connecting these conductor layers. Inductor L6 is composed of conductor layers 606, 616, 626, 636, 676, and 686 for the inductor and a plurality of through holes connecting these conductor layers. Inductor L7 is composed of conductor layers 607, 617, 627, 637, 677, and 687 for the inductor and a plurality of through holes connecting these conductor layers.

[0070] Capacitor C1 is composed of conductor layers 521, 522, 531, and 541 and dielectric layers 52 and 53 between these conductor layers. Capacitor C2 is composed of electrodes 111 and 117, conductor layers 521 and 522, and a dielectric layer 51 between the electrodes 111 and 117 and the conductor layers 521 and 522.

[0071] Capacitor C3 is composed of conductor layers 633 and 642 and a dielectric layer 63 between these conductor layers. Capacitor C4 is composed of conductor layers 643 and 651 and a dielectric layer 64 between these conductor layers.

[0072] Capacitor C5 is composed of conductor layers 651 and 661 and a dielectric layer 65 between these conductor layers. The conductor layer 661 is connected to the electrode 123 via the through holes 66T3, 67T3, 68T3, the conductor layer 693, and the through hole 69T3.

[0073] Capacitor C6 is composed of conductor layers 652 and 662 and dielectric layer 65 between these conductor layers. Capacitor C7 is composed of conductor layers 644 and 652 and dielectric layer 64 between these conductor layers. Capacitor C8 is composed of conductor layers 646 and 653 and dielectric layer 64 between these conductor layers. Capacitor C9 is composed of conductor layers 636 and 647 and dielectric layer 63 between these conductor layers.

[0074] Capacitor C10 is composed of conductor layers 523 and 532 and dielectric layer 52 between these conductor layers. Capacitor C11 is composed of conductor layers 648, 654, and 663 and dielectric layers 64 and 65 between these conductor layers.

[0075] Next, with reference to FIGS. 2 to 14, the structural features of the electronic component 1 according to the present embodiment will be described. FIGS. 12 and 13 are respectively plan views showing a part inside the first main body 50. FIG. 14 is a cross-sectional view showing the electronic component 1. In FIG. 12, a plurality of conductor layers constituting the inductor are shown by solid lines. In FIG. 13, the conductor layers constituting the capacitor are shown by solid lines, and the conductors constituting the inductor L6 are shown by dashed lines. FIG. 14 shows a plurality of conductors of the first main body 50.

[0076] First, two regions of the first main body 50 defined by the second main body 80 will be described. As described above, the second main body 80 is mounted on the first surface 50A of the first main body 50. The first main body 50 includes a first region R1 that overlaps the second main body 80 when viewed in the stacking direction T and a second region R2 that does not overlap the second main body 80 when viewed in the stacking direction T. The first region R1 is defined as a three-dimensional region whose Z-direction end exists on the first surface 50A and whose -Z-direction end exists on the second surface 50B. In FIGS. 12 and 13, the outer edge of the first region R1 including the X-direction end, -X-direction end, Y-direction end, and -Y-direction end of the first region R1 is shown by a two-dot chain line of a rectangle labeled R1.

[0077] The second region R2 is defined as a region obtained by removing the first region R1 from a three-dimensional region substantially surrounded by the outer peripheral surface of the first main body 50. The second region R2 covers at least a part of the outer peripheral portion of the first region R1. In particular, in the present embodiment, the second region R2 covers a portion of the outer peripheral portion of the first region R1 excluding the end in the Z direction (the first surface 50A) and the end in the -Z direction (the second surface 50B). In FIGS. 12 and 13, the outer edge of the second region R2 including the ends in the X direction, -X direction, Y direction, and -Y direction of the second region R2 is shown by a two-dot chain line of a rectangle with the symbol R2 attached. Note that, in FIGS. 12 and 13, for the sake of convenience, the outer edge of the second region R2 is drawn away from the side surfaces 50C to 50F of the first main body 50. In FIG. 14, the boundary between the first region R1 and the second region R2 is shown by a dotted line.

[0078] The planar shape of the second main body 80 (the shape as viewed from the stacking direction T) may be the same as the shape of the first region R1. Alternatively, the second main body 80 may include a first portion having the same planar shape as the shape of the first region R1 and a second portion having a planar shape size different from the planar shape size of the first region R1. In this case, the second main body 80 is mounted on the first main body 50 in a posture such that the first portion is located between the first main body 50 and the second portion.

[0079] Next, the relationship between the plurality of conductors of the first main body 50 and the first and second regions R1 and R2 will be described. Here, among the plurality of conductors, the plurality of conductors for forming at least one capacitor are also referred to as a plurality of capacitor conductors. In particular, in the present embodiment, at least one capacitor conductor is a plurality of capacitor conductors.

[0080] As shown in FIG. 13, at least a part of the plurality of capacitor conductors is disposed in the first region R1. In particular, in the present embodiment, in the first region R1, in a portion closer to the first surface 50A than the second surface 50B, a part of the conductor layer 643 constituting the capacitor C4, the entire conductor layer 651 constituting the capacitors C4 and C5, the entire conductor layer 661 constituting the capacitor C5, a part of the conductor layer 662 constituting the capacitor C6, a part of the conductor layer 652 constituting the capacitors C6 and C7, and a part of the conductor layer 644 constituting the capacitor C7 are disposed. Further, in the first region R1, in a portion closer to the second surface 50B than the first surface 50A, a part of each of the conductor layers 521, 522, 531, and 541 constituting the capacitor C1 and a part of each of 523 and 532 constituting the capacitor C10 are disposed.

[0081] Of the plurality of capacitor conductors, a portion other than the portion disposed in the first region R1 is disposed in the second region R2.

[0082] In the first main body 50, between the portion of the plurality of capacitor conductors disposed in the first region R1 and the second main body 80, no other inductor and no other capacitor are provided. Note that the other capacitor means a capacitor other than the plurality of capacitors constituted by the portion disposed in the first region R1 described above.

[0083] Also, at least one conductor for constituting at least one inductor among the plurality of conductors is also referred to as at least one inductor conductor. In particular, in the present embodiment, at least one inductor is a plurality of inductors, and at least one inductor conductor is a plurality of inductor conductors. The plurality of inductor conductors includes the plurality of conductor layers for the plurality of inductors, the plurality of through holes for connecting the plurality of conductor layers for the plurality of inductors, and the plurality of conductor layers connected to the plurality of through holes.

[0084] The plurality of inductor conductors constituting the inductor L2 are wound around an axis extending in a direction parallel to the stacking direction T such that an opening surrounded by the plurality of inductor conductors is formed. Hereinafter, the opening surrounded by the plurality of inductor conductors constituting the inductor L2 is referred to as the opening of the inductor L2. The opening of the inductor L2 faces the first surface 50A of the first body 50. Also, the entire opening of the inductor L2 is present in the second region R2. Hereinafter, for inductors other than the inductor L2 as well, the opening surrounded by the plurality of conductors constituting the inductor is referred to as the opening of the inductor.

[0085] Similarly, the plurality of inductor conductors constituting each of the inductors L3, L5, L6, and L7 are wound around an axis extending in a direction parallel to the stacking direction T such that an opening surrounded by the plurality of inductor conductors is formed. The opening of each of the inductors L3, L5, L6, and L7 faces the first surface 50A of the first body 50. Most of the opening of each of the inductors L3 and L5 is present in the second region R2. The entire opening of each of the inductors L6 and L7 is present in the second region R2.

[0086] Hereinafter, the plurality of inductor conductors constituting each of the inductors L2, L3, L5, L6, and L7 will be described. In the following description, when simply referring to a plurality of inductor conductors without limiting the inductor, it is intended to refer to the plurality of inductor conductors constituting any one of the inductors L2, L3, L5, L6, and L7.

[0087] Here, focusing on the magnetic field generated by the inductor, the plurality of inductor conductors will be described. The plurality of inductor conductors include at least one main part that contributes to the generation of the magnetic field and at least one non-main part. The at least one main part is, for example, a winding part that winds around the periphery of the opening of the inductor, or most of the winding part.

[0088] At least one non-primary portion does not contribute or hardly contributes to the generation of a magnetic field, or is a portion that does not contribute to the generation of a magnetic field as compared with at least one primary portion. The at least one non-primary portion is, for example, a portion that does not surround the periphery of the opening of the inductor, or a relatively short portion of a winding portion that does not substantially surround the periphery of the opening of the inductor.

[0089] At least one primary portion of the plurality of inductor conductors is disposed in the second region R2. At least one non-primary portion of the plurality of inductor conductors is disposed in the second region R2 or at least a part thereof is disposed in the first region R1. In particular, in the present embodiment, at least a part of at least one non-primary portion of the plurality of inductor conductors constituting each of the inductors L2, L3, and L5 is disposed in the first region R1. Specifically, a part (relatively short portion) of each of the conductor layers 602, 612, 622, 632, 672, and 682 for the inductor constituting the inductor L2 is disposed in the first region R1. Also, a part (relatively short portion) of each of the conductor layers 623, 633, 673, and 683 for the inductor constituting the inductor L3 is disposed in the first region R1. Also, a part (relatively short portion) of each of the conductor layers 635 and 645 for the inductor constituting the inductor L5 is disposed in the first region R1.

[0090] At least one other non-primary portion of the plurality of inductor conductors constituting each of the inductors L2, L3, and L5 may be disposed in the second region R2. At least one non-primary portion of the plurality of inductor conductors constituting each of the inductors L6 and L7 is disposed in the second region R2.

[0091] Here, as shown in FIG. 14, the first main body 50 is divided into an upper layer portion 50U and a lower layer portion 50L. The upper layer portion 50U and the lower layer portion 50L are divided based on the conductor layers 602, 606, and 607 for inductors that are closest to the second surface 50B among the plurality of inductor conductors. That is, a portion of the first main body 50 that includes the dielectric layers 60 to 69 located between the conductor layers 602, 606, 607 and the first surface 50A is defined as the upper layer portion 50U. Also, a portion of the first main body 50 that includes the dielectric layers 51 to 59 located between the conductor layers 602, 606, 607 and the second surface 50B is defined as the lower layer portion 50L.

[0092] As described above, the plurality of main portions of the plurality of inductor conductors are not arranged in the first region R1. However, a part of the plurality of main portions of the plurality of inductor conductors may be arranged in a portion of the first region R1 that belongs to the lower layer portion 50L. In this case, a part of the plurality of capacitor conductors arranged in the first region R1 is interposed between a part of the plurality of main portions and the second main body 80.

[0093] Note that the size of the plurality of non-main portions of the plurality of inductor conductors arranged in the first region R1 is preferably small. The size of the plurality of non-main portions in the first region R1 may be based on the portion of the plurality of capacitor conductors arranged in the first region R1. Here, a planar figure formed by vertically projecting the portion of the plurality of capacitor conductors arranged in the first region R1 onto the first surface 50A is referred to as the first planar figure, and a planar figure formed by vertically projecting the plurality of non-main portions in the first region R1 onto the first surface 50A is referred to as the second planar figure. The first planar figure can be drawn by selectively tracing the outer edge of the portion of the plurality of capacitor conductors arranged in the first region R1. Similarly, the second planar figure can be drawn by selectively tracing the outer edge of the plurality of non-main portions in the first region R1. In the present embodiment, the area of the first planar figure may be made larger than the area of the second planar figure, so that relatively, the size of the plurality of non-main portions of the plurality of inductor conductors arranged in the first region R1 can be made smaller.

[0094] So far, the plurality of inductor conductors that make up each of the inductors L2, L3, L5, L6, and L7 have been described. Here, the plurality of inductor conductors that make up the inductor L1 and the plurality of inductor conductors that make up the inductor L4 will be described. The plurality of inductor conductors that make up the inductor L1 are wound around an axis extending in a direction orthogonal to the stacking direction T such that an opening surrounded by the plurality of inductor conductors is formed. The opening of the inductor L1 faces the side surface 50C of the first main body 50.

[0095] The plurality of inductor conductors that make up the inductor L4 are arranged so that no opening surrounded by the plurality of inductor conductors is formed.

[0096] In the examples shown in FIGS. 12 and 14, the plurality of inductor conductors that make up the inductor L1 are arranged in the second region R2. A part of the plurality of inductor conductors that make up the inductor L4 is arranged in the second region R2, and another part of the plurality of inductor conductors that make up the inductor L4 is arranged in the first region R1. However, the plurality of inductor conductors that make up each of the inductors L1 and L4 may be entirely arranged in the first region R1.

[0097] Next, an example of the characteristics of the electronic component 1 according to the present embodiment will be shown. FIG. 15 is a characteristic diagram showing an example of the passing attenuation characteristics of the electronic component 1. In FIG. 15, the horizontal axis represents the frequency, and the vertical axis represents the attenuation amount. As shown in FIG. 15, it can be seen that the electronic component 1 has sufficient characteristics in practical use as a band-pass filter.

[0098] Next, the operation and effects of the electronic component 1 according to the present embodiment will be described. In the present embodiment, as described above, the openings of each of the inductors L2, L3, L5, L6, and L7 face the first surface 50A of the first main body 50. Therefore, the magnetic field generated by each of the inductors L2, L3, L5, L6, and L7 can act on the mounted components mounted on the first surface 50A. When the magnetic field generated by each of the inductors L2, L3, L5, L6, and L7 acts on the mounted components, an electromagnetic field may act mutually between each of the inductors L2, L3, L5, L6, and L7 and the mounted components, and desired characteristics may not be obtained. For example, when the mounted component includes a surface acoustic wave device, when an electromagnetic field acts mutually between each of the inductors L2, L3, L5, L6, and L7 and the surface acoustic wave device, the insertion loss in the passband of the bandpass filter may increase.

[0099] On the other hand, in the present embodiment, a plurality of main portions of a plurality of inductor conductors constituting each of the inductors L2, L3, L5, L6, and L7 are arranged in a second region R2 of the first main body 50 that does not overlap the second main body 80 when viewed in the stacking direction T. In the present embodiment in particular, the openings of each of the inductors L2, L3, L5, L6, and L7 are entirely or mostly present in the second region R2. Thereby, according to the present embodiment, it is possible to suppress the mutual action of the electromagnetic field between each of the inductors L2, L3, L5, L6, and L7 and the second main body 80.

[0100] Further, in the present embodiment, by arranging a plurality of main portions of a plurality of inductor conductors in the second region R2, a space for arranging a plurality of conductors is formed in a first region R1 of the first main body 50 that overlaps the second main body 80 when viewed in the stacking direction T. In the present embodiment, a part of a plurality of capacitor conductors is arranged in the above space in the first region R1. Thus, according to the present embodiment, the electronic component 1 can be miniaturized by efficiently using the space in the first main body 50.

[0101] In addition, in the present embodiment, a part of a plurality of non-primary portions of a plurality of inductor conductors is disposed in the first region R1. When the area of the planar figure formed by vertically projecting the portion of the plurality of capacitor conductors disposed in the first region R1 onto the first surface 50A is made larger than the area of the planar figure formed by vertically projecting the plurality of non-primary portions in the first region R1 onto the first surface 50A, relatively, the size of the plurality of non-primary portions of the plurality of inductor conductors disposed in the first region R1 becomes smaller. Thus, according to the present embodiment, while suppressing the mutual electromagnetic field interaction between each of the inductors L2, L3, L5, L6, L7 and the second main body 80, the space within the first main body 50 can be efficiently utilized to miniaturize the electronic component 1.

[0102] Also, in the present embodiment, since the mutual electromagnetic field interaction between each of the inductors L1 to L7 and the second main body 80 can be suppressed, the distance between the plurality of inductor conductors and the first surface 50A can be reduced. Thus, according to the present embodiment, the dimension in the stacking direction T of the first main body 50 can be reduced. Further, according to the present embodiment, by making the distance between the plurality of capacitor conductors and the first surface 50A larger than the distance between the plurality of inductor conductors and the first surface 50A, the mutual electromagnetic field interaction between the plurality of capacitor conductors and the second main body 80 can be suppressed.

[0103] Next, other effects of the electronic component 1 according to the present embodiment will be described. In the present embodiment, the dielectric material constituting each of the plurality of dielectric layers 51 to 69 is, for example, low-temperature co-fired ceramics (LTCC). LTCC is easier to thin than resin. Therefore, when comparing with the same number of capacitors, when each of the plurality of dielectric layers 51 to 69 is constituted by LTCC, the first main body 50 can be made smaller than the case where each of the plurality of dielectric layers 51 to 69 is constituted by resin.

[0104] Also, LTCC has lower hygroscopicity compared to resin. Therefore, when each of the plurality of dielectric layers 51 to 69 is made of LTCC, a more reliable electronic component 1 can be realized compared to the case where each of the plurality of dielectric layers 51 to 69 is made of resin.

[0105] Also, a capacitor formed using LTCC has a lower dielectric loss tangent compared to a capacitor formed using resin. Therefore, when each of the plurality of dielectric layers 51 to 69 is made of LTCC, high-performance capacitors C1 to C11 can be realized compared to the case where each of the plurality of dielectric layers 51 to 69 is made of resin, and as a result, a high-performance electronic component 1 can be realized.

[0106] [Second Embodiment] Next, with reference to FIG. 16, a second embodiment of the present invention will be described. FIG. 16 is a side view showing an electronic component according to the present embodiment.

[0107] The electronic component 101 according to the present embodiment includes a first main body 50, a second main body 80, and a sealing portion 90, similar to the electronic component 1 according to the first embodiment. The electronic component 101 further includes a third main body 110 mounted on the second surface 50B of the first main body 50. The planar shape of the third main body 110 may be the same as the planar shape of the first main body 50.

[0108] The electronic component 101 includes a first circuit and a second circuit, similar to the electronic component 1 according to the first embodiment. In the present embodiment, the first main body 50 may include the first circuit. In this case, the third main body 110 may include a third circuit connected to the first circuit. Alternatively, the first main body 50 may include a part of the first circuit. In this case, the third main body 110 may include the other part of the first circuit.

[0109] The third main body 110 has an upper surface 110A facing the second surface 50B of the first main body 50 and a bottom surface 110B on the side opposite to the upper surface 110A. The electronic component 101 further includes a fourth main body 120 mounted on the bottom surface 110B of the third main body 110. The fourth main body 120 may be a passive element such as an inductor or a capacitor, or may be any active element including a semiconductor such as a high-frequency switch.

[0110] In the example shown in FIG. 16, in addition to the fourth main body 120, a plurality of solder bumps 130 for connecting the electronic component 101 to the substrate on which the electronic component 101 is mounted are provided on the bottom surface 110B of the third main body 110. The dimension of each of the plurality of solder bumps 130 in the Z direction is larger than the dimension of the fourth main body 120 in the Z direction.

[0111] Other configurations, operations, and effects in the present embodiment are the same as those in the first embodiment.

[0112] Note that the present invention is not limited to the above-described embodiment, and various modifications are possible. For example, the electronic component of the present invention is not limited to a band-pass filter, and can be applied to other filters such as a low-pass filter and a high-pass filter, and an electronic component including a plurality of resonators such as a wave divider that separates a plurality of signals having different frequency bands.

[0113] Further, the second main body 80 may include only one elastic wave element, or may include three or more elastic wave elements. Further, in addition to the elastic wave elements 31 and 32, the second main body 80 may include any passive element such as a capacitor. In this case, the passive element may be connected to the elastic wave element 31 or 32. Further, instead of the elastic wave elements 31 and 32, or in addition to the elastic wave elements 31 and 32, the second main body 80 may include any active element including a semiconductor such as a high-frequency switch.

[0114] Further, the second main body 80 may be disposed near the outer edge of the first surface 50A of the first main body 50.

[0115] As described above, the electronic component of the present invention includes a first main body including a plurality of stacked dielectric layers, a plurality of conductors, and a first circuit configured using the plurality of conductors, and a second main body including a second circuit connected to the first circuit. The first main body has a first surface located at an end in the stacking direction of the plurality of dielectric layers. The second main body is mounted on the first surface. The first main body includes a first region that overlaps the second main body when viewed from the stacking direction and a second region that does not overlap the second main body when viewed from the stacking direction. The plurality of conductors includes a plurality of capacitor conductors for forming at least one capacitor and at least one inductor conductor for forming at least one inductor. At least a part of the plurality of capacitor conductors is disposed in the first region. The at least one inductor conductor includes a main part disposed in the second region and a non-main part. The non-main part is disposed in the second region or at least a part thereof is disposed in the first region.

[0116] In the electronic component of the present invention, the first circuit may include at least one capacitor and at least one inductor.

[0117] Also, in the electronic component of the present invention, no other inductor and other capacitor may be provided between at least a part of the plurality of capacitor conductors and the second main body.

[0118] Also, in the electronic component of the present invention, the area of the planar figure formed by vertically projecting at least a part of the plurality of capacitor conductors disposed in the first region onto the first surface may be larger than the area of the planar figure formed by vertically projecting the part of the non-main part disposed in the first region onto the first surface.

[0119] Also, in the electronic component of the present invention, the at least one capacitor may be a plurality of capacitors. At least a part of the plurality of capacitor conductors disposed in the first region may constitute two or more capacitors among the plurality of capacitors.

[0120] In addition, in the electronic component of the present invention, at least one inductor may be a plurality of inductors. At least one inductor conductor may be a plurality of inductor conductors.

[0121] In addition, in the electronic component of the present invention, at least one inductor conductor may be wound around an axis extending in a direction parallel to the stacking direction.

[0122] In addition, in the electronic component of the present invention, the second region may cover at least a part of the outer peripheral portion of the first region.

Description of reference numerals

[0123] 1... Electronic component, 2... First input / output terminal, 3... Second input / output terminal, 7... Solder bump, 11 to 14... Signal terminals, 31, 32... Surface acoustic wave elements, 50... First main body, 50A... First surface, 50B... Second surface, 50C to 50F... Side surfaces, 51 to 69... Dielectric layers, 80... Second main body, 81 to 84... Signal terminals, 90... Sealing portion, 111 to 119, 121 to 124... Electrodes, C1 to C11... Capacitors, L1 to L7... Inductors, R1... First region, R2... Second region.

Claims

1. A first body including a plurality of stacked dielectric layers, a plurality of conductors, and a first circuit configured using the plurality of conductors, and a second body including a second circuit connected to the first circuit. The first body has a first surface located at an end in the stacking direction of the plurality of dielectric layers, and the second body is mounted on the first surface. The first body includes a first region that overlaps the second body when viewed in the stacking direction and a second region that does not overlap the second body when viewed in the stacking direction. The plurality of conductors include a plurality of capacitor conductors for forming at least one capacitor and at least one inductor conductor for forming at least one inductor. At least a part of the plurality of capacitor conductors is disposed in the first region. The at least one inductor conductor includes a main part disposed in the second region and a non-main part. The non-main part is disposed in the second region or at least a part thereof is disposed in the first region. An electronic component characterized by this.

2. The first circuit includes the at least one capacitor and the at least one inductor. The electronic component according to Claim 1, characterized by this.

3. No other inductor and no other capacitor are provided between at least a part of the plurality of capacitor conductors and the second body. The electronic component according to Claim 1, characterized by this.

4. The area of the planar figure formed by vertically projecting at least a part of the plurality of capacitor conductors disposed in the first region onto the first surface is larger than the area of the planar figure formed by vertically projecting the part of the non-main part disposed in the first region onto the first surface. The electronic component according to Claim 1, characterized by this.

5. The at least one capacitor is a plurality of capacitors. At least a part of the plurality of capacitor conductors disposed in the first region constitutes two or more of the plurality of capacitors. The electronic component according to Claim 1, characterized by this.

6. The at least one inductor is a plurality of inductors. The at least one inductor conductor is a plurality of inductor conductors. The electronic component according to Claim 1, characterized by this.

7. The electronic component according to claim 1, wherein the at least one inductor conductor is wound around an axis extending in a direction parallel to the stacking direction.

8. The electronic component according to any one of claims 1 to 7, wherein the second region covers at least a part of the outer peripheral portion of the first region.

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