Multilayer electronic component

Abstract

To provide a multilayer electronic component that can be made compact without spoiling respective functions of an inductor and a capacitor.SOLUTION: A multilayer electronic component 5 comprises an inductor L3, an inductor L6, a capacitor C9, and a laminate 50. The inductor L3 and inductor L6 are arranged such that an opening part L3o of the inductor L3 and an opening part L6o of the inductor L6 do not face each other. The capacitor C9 includes a conductor layer 647. The conductor layer 647 includes a first overlap part 647B overlapping a conductor layer 636 constituting the inductor L6 when viewed from a lamination direction T.SELECTED DRAWING: Figure 14

Description

Technical Field

[0001] The present invention relates to an electronic component including an inductor and a capacitor.

Background Art

[0002] Various filters such as a low-pass filter, a high-pass filter, and a band-pass filter are configured using a plurality of resonators. As a resonator used for these filters, for example, an LC resonator configured using an inductor and a capacitor is known. As an inductor, one configured using a line is known. Generally, a filter is provided with a plurality of inductors and a plurality of capacitors.

[0003] Patent Document 1 discloses a high-frequency switch module in which a low-pass filter and a high-pass filter are formed in a laminate, and a band-pass filter is mounted on the laminate. The laminate is provided with a plurality of transmission lines and a plurality of capacitors.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In recent years, there has been a market demand for miniaturization and space saving of small mobile communication devices, and miniaturization of filters used in such communication devices has also been required. In a filter configured using a laminate, it has been required to miniaturize the laminate while satisfying desired characteristics. In order to further miniaturize the filter, it has been necessary to efficiently arrange a plurality of inductors and a plurality of capacitors in the laminate. However, there has been a limit to miniaturizing the laminate by optimizing the arrangement of the plurality of inductors and the plurality of capacitors without impairing the functions of each of the plurality of inductors and the plurality of capacitors.

[0006] The above problem applies not only to filters but also to all electronic components including inductors and capacitors.

[0007] The present invention has been made in view of such problems, and an object thereof is to provide a laminated electronic component that can be miniaturized without impairing the functions of an inductor and a capacitor.

Means for Solving the Problems

[0008] The multilayer electronic component according to the first aspect of the present invention includes a first inductor, a second inductor, a capacitor, and a laminate for integrating the first inductor, the second inductor, and the capacitor, the laminate including a plurality of stacked dielectric layers. The first inductor includes at least one first inductor conductor layer wound around a first axis extending in a direction parallel to the stacking direction of the plurality of dielectric layers. The second inductor includes at least one second inductor conductor layer wound around a second axis extending in a direction parallel to the stacking direction. The first inductor and the second inductor are arranged such that, when viewed from the stacking direction, a first opening surrounded by at least one first inductor conductor layer and a second opening surrounded by at least one second inductor conductor layer do not overlap. The capacitor includes a capacitor conductor layer. The capacitor conductor layer extends from at least one second inductor conductor layer toward at least one first inductor conductor layer when viewed from the stacking direction, and includes a first overlap portion that overlaps at least one first inductor conductor layer when viewed from the stacking direction.

[0009] The multilayer electronic component according to the second aspect of the present invention includes an inductor, a capacitor, and a laminate for integrating the inductor and the capacitor, the laminate including a plurality of stacked dielectric layers. The inductor includes at least one inductor conductor layer wound around an axis extending in a direction parallel to the stacking direction of the plurality of dielectric layers. The at least one inductor conductor layer includes an extending portion having a predetermined length and a smooth outer edge. The capacitor includes a capacitor conductor layer. The capacitor conductor layer extends from the outside of at least one inductor conductor layer toward an opening surrounded by at least one inductor conductor layer when viewed from the stacking direction, and includes a first overlap portion that overlaps the extending portion when viewed from the stacking direction.

Advantages of the Invention

[0010] In the multilayer electronic component according to the first aspect of the present invention, the capacitor conductor layer includes a first overlapping portion that overlaps at least one first inductor conductor layer when viewed in the stacking direction. Thus, according to the multilayer electronic component of the first aspect of the present invention, there is an effect that it can be miniaturized without impairing the functions of the inductor and the capacitor respectively.

[0011] In the multilayer electronic component according to the second aspect of the present invention, the capacitor conductor layer includes a first overlapping portion that overlaps at least one inductor conductor layer when viewed in the stacking direction. Thus, according to the multilayer electronic component of the second aspect of the present invention, there is an effect that it can be miniaturized without impairing the functions of the inductor and the capacitor respectively.

Brief Description of the Drawings

[0012]

Figure 1

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Figure 17

Embodiments for Carrying Out the Invention

[0013] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. First, the schematic configuration of the electronic component 1 including the multilayer electronic component according to an embodiment of the present invention will be described. The electronic component 1 in the present embodiment is a band-pass filter that selectively passes signals of frequencies within a predetermined passband.

[0014] The electronic component 1 in the present embodiment is a so-called hybrid type filter including at least one LC resonator composed of at least one inductor and at least one capacitor, and an elastic wave resonator composed of at least one elastic wave element. The at least one elastic wave element may be, for example, a bulk elastic wave element or a surface acoustic wave element.

[0015] Next, with reference to FIG. 1, an example of the circuit configuration of the electronic component 1 will be described. FIG. 1 is a circuit diagram showing the circuit configuration of the electronic component 1. The electronic component 1 includes a first input / output terminal 2, a second input / output terminal 3, and a filter circuit provided between the first input / output terminal 2 and the second input / output terminal 3 in terms of circuit configuration. In the present application, the expression "in terms of circuit configuration" is used to refer to the arrangement on the circuit diagram rather than the arrangement in the physical configuration.

[0016] Each of the first and second input / output terminals 2 and 3 is a terminal for inputting or outputting a signal. That is, when a signal is input to the first input / output terminal 2, the signal is output from the second input / output terminal 3. When a signal is input to the second input / output terminal 3, the signal is output from the first input / output terminal 2.

[0017] The filter circuit includes inductors L1, L2, L3, L5, L6, L7 and capacitors C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11. One end of the inductor L1 is connected to the first input / output terminal 2. One end of the inductor L2 is connected to the other end of the inductor L1.

[0018] One end of the capacitor C4 is connected to the other end of the inductor L2. One end of the capacitor C5 is connected to the other end of the capacitor C4. One end of the capacitor C6 is connected to the other end of the capacitor C5. One end of the capacitor C7 is connected to the other end of the capacitor C6. One end of the capacitor C8 is connected to the other end of the capacitor C7.

[0019] One end of the capacitor C11 is connected to the other end of the capacitor C8. One end of the inductor L7 is connected to the other end of the capacitor C11. The other end of the inductor L7 is connected to the second input / output terminal 3.

[0020] The capacitor C1 is connected in parallel to the inductor L1. One end of the capacitor C2 is connected to the connection point between the inductor L1 and the inductor L2. One end of the capacitor C3 is connected to the connection point between the inductor L2 and the capacitor C4. The other ends of the capacitors C2 and C3 are connected to the ground.

[0021] One end of the inductor L3 is connected to the connection point between the capacitor C4 and the capacitor C5. One end of the inductor L5 is connected to the connection point between the capacitor C6 and the capacitor C7. The other ends of the inductors L3 and L5 are connected to the ground.

[0022] One end of the inductor L6 is connected to the connection point between the capacitor C8 and the capacitor C11. One end of the capacitor C10 is connected to the other end of the inductor L6. The other end of the capacitor C10 is connected to the ground.

[0023] One end of the capacitor C9 is connected to one end of each of the inductor L3 and the capacitor C5. The other end of the capacitor C9 is connected to one end of the inductor L6 and the other end of the capacitor C8.

[0024] The filter circuit further includes signal terminals 81, 82, 83, 84, a surface acoustic wave device 31 disposed between the signal terminal 81 and the signal terminal 82 in terms of circuit configuration, and a surface acoustic wave device 32 disposed between the signal terminal 83 and the signal terminal 84 in terms of circuit configuration.

[0025] The filter circuit further includes signal terminals 11, 12, 13, and 14 respectively connected to signal terminals 81, 82, 83, and 84. In FIG. 1, for the sake of convenience, signal terminal 12 is depicted as being interposed between one end of capacitor C9 and one end of capacitor C5. However, signal terminal 12 does not necessarily have to be interposed between one end of capacitor C9 and one end of capacitor C5.

[0026] Capacitor C4 is connected in parallel to the surface acoustic wave element 31. The other end of inductor L2 and one end of each of capacitors C3 and C4 are connected to one end of the surface acoustic wave element 31 via signal terminals 11 and 81 in sequence. One end of inductor L3, the other end of capacitor C4, and one end of capacitor C5 are connected to the other end of the surface acoustic wave element 31 via signal terminals 12 and 82 in sequence.

[0027] The other end of capacitor C5 and one end of capacitor C6 are connected to one end of the surface acoustic wave element 32 via signal terminals 13 and 83 in sequence. The filter circuit further includes inductor L4. One end of inductor L4 is connected to the other end of the surface acoustic wave element 32 via signal terminals 14 and 84 in sequence. The other end of inductor L4 is connected to ground.

[0028] Next, with reference to FIGS. 2 to 4, the configuration of the multilayer electronic component according to the present embodiment will be described. FIG. 2 is a perspective view showing the electronic component 1. FIGS. 3 and 4 are perspective views showing the multilayer electronic component according to the present embodiment.

[0029] The electronic component 1 includes the multilayer electronic component 5 according to the present embodiment. The multilayer electronic component 5 includes a laminate 50 including a plurality of stacked dielectric layers and a plurality of conductors (a plurality of conductor layers and a plurality of through holes). The laminate 50 is for integrating the inductors L1 to L7 and the capacitors C1 to C11 among the filter circuits shown in FIG. 1. The inductors L1 to L7 and the capacitors C1 to C11 are configured using a plurality of conductors. Each of the plurality of dielectric layers is made of a dielectric material. As the dielectric material, for example, low-temperature co-fired ceramics (LTCC) is used.

[0030] The laminate 50 has a first surface 50A and a second surface 50B located at both ends in the stacking direction T of the plurality of dielectric layers, and four side surfaces 50C to 50F connecting the first surface 50A and the second surface 50B. The side surfaces 50C and 50D face opposite sides, and the side surfaces 50E and 50F also face opposite sides. The side surfaces 50C to 50F are perpendicular to the first surface 50A and the second surface 50B.

[0031] Here, as shown in FIGS. 2 to 4, the X direction, the Y direction, and the Z direction are defined. The X direction, the Y direction, and the Z direction are orthogonal to each other. In the present embodiment, one direction parallel to the stacking direction T is defined as the Z direction. Also, the direction opposite to the X direction is defined as the -X direction, the direction opposite to the Y direction is defined as the -Y direction, and the direction opposite to the Z direction is defined as the -Z direction. Also, the expression "when viewed from a predetermined direction (for example, the Z direction)" means viewing an object from a position separated in the predetermined direction or a direction parallel to the predetermined direction.

[0032] As shown in FIGS. 3 and 4, the first surface 50A is located at the end of the laminate 50 in the Z direction. The first surface 50A is also the upper surface of the laminate 50 and is also a mounting surface for mounting the mounting components described later. The second surface 50B is located at the end of the laminate 50 in the -Z direction. The second surface 50B is also the bottom surface of the laminate 50. FIG. 3 shows the laminate 50 viewed from the first surface 50A side. FIG. 4 shows the laminate 50 viewed from the second surface 50B side.

[0033] Side 50C is located at the -X direction end of the laminate 50. Side 50D is located at the X direction end of the laminate 50. Side 50E is located at the -Y direction end of the laminate 50. Side 50F is located at the Y direction end of the laminate 50.

[0034] The laminate 50 further includes a plurality of electrodes 111, 112, 113, 114, 115, 116, 117, 118, 119 provided on the second surface 50B of the laminate 50. Electrodes 111, 112, 113 are arranged in this order in the X direction at a position closer to side 50E than to side 50F. Electrodes 115, 116, 117 are arranged in this order in the -X direction at a position closer to side 50F than to side 50E.

[0035] Electrode 114 is disposed between electrode 113 and electrode 115. Electrode 118 is disposed between electrode 111 and electrode 117. Electrode 119 is disposed between electrode 112 and electrode 116. Also, electrode 119 is disposed substantially at the center of the second surface 50B.

[0036] Electrode 118 corresponds to the first input / output terminal 2. Electrode 114 corresponds to the second input / output terminal 3. Therefore, the first and second input / output terminals 2, 3 are provided on the second surface 50B of the laminate 50. Each of electrodes 111~113, 115~117, 119 is connected to the ground.

[0037] The laminate 50 further includes a plurality of electrodes 121, 122, 123, 124 provided on the first surface 50A of the laminate 50. Electrodes 121, 122 are arranged in this order in the X direction at a position closer to side 50E than to side 50F. Electrodes 123, 124 are arranged in this order in the -X direction at a position closer to side 50F than to side 50E.

[0038] Electrode 121 corresponds to signal terminal 11. Electrode 122 corresponds to signal terminal 12. Electrode 123 corresponds to signal terminal 13. Electrode 124 corresponds to signal terminal 14. Therefore, signal terminals 11 to 14 are provided on the first surface 50A of laminate 50.

[0039] Electronic component 1 further includes a mounted component 80 mounted on the first surface 50A of laminate 50. Mounted component 80 includes the surface acoustic wave elements 31 and 32 among the filter circuits shown in FIG. 1.

[0040] Mounted component 80 further includes four electrodes that respectively constitute signal terminals 81, 82, 83, and 84. In FIG. 2, for convenience, the four electrodes are shown with reference numerals 81 to 84 attached. In the state where mounted component 80 is mounted on laminate 50, the four electrodes with reference numerals 81 to 84 respectively face electrodes 121 to 124 of laminate 50. The four electrodes with reference numerals 81 to 84 are physically connected to electrodes 121 to 124 by, for example, solder bumps 7.

[0041] In the example shown in FIG. 2, mounted component 80 is arranged so as to overlap the center of gravity of the first surface 50A when viewed from the stacking direction T. The center of gravity of mounted component 80 when viewed from the stacking direction T may or may not coincide with the center of gravity of the first surface 50A.

[0042] Electronic component 1 further includes a sealing portion 90 that seals mounted component 80. Sealing portion 90 covers at least a part of the periphery of mounted component 80 and the first surface 50A of laminate 50. Sealing portion 90 may further cover side surfaces 50C to 50F of laminate 50. Sealing portion 90 is made of, for example, resin.

[0043] Next, with reference to FIGS. 5(a) to 10(c), an example of a plurality of dielectric layers, a plurality of conductor layers, and a plurality of through-holes constituting the laminate 50 will be described. In this example, the laminate 50 includes 19 stacked dielectric layers. Hereinafter, these 19 dielectric layers will be referred to as the first to 19th dielectric layers in order from the bottom. Also, the first to 19th dielectric layers are represented by reference numerals 51 to 69.

[0044] In FIGS. 5(a) to 10(b), the plurality of circles represent a plurality of through-holes. A plurality of through-holes are formed in each of the dielectric layers 51 to 69. Each of the plurality of through-holes is formed by filling a hole for a through-hole with a conductor paste. Each of the plurality of through-holes is connected to an electrode, a conductor layer, or another through-hole.

[0045] In FIGS. 5(a) to 10(b), a plurality of specific through-holes among the plurality of through-holes are labeled. The connection relationship between each of the plurality of specific through-holes and an electrode, a conductor layer, or another through-hole is described with respect to the connection relationship in the state where the first to 19th dielectric layers 51 to 69 are stacked.

[0046] FIG. 5(a) shows the pattern formation surface of the first dielectric layer 51. Electrodes 111 to 119 are formed on the pattern formation surface of the dielectric layer 51.

[0047] FIG. 5(b) shows the pattern formation surface of the second dielectric layer 52. Conductor layers 521, 522, 523, 524, and 525 are formed on the pattern formation surface of the dielectric layer 52. The conductor layer 525 is connected to the conductor layer 523. In FIG. 5(b), the boundary between the conductor layer 523 and the conductor layer 525 is indicated by a dotted line.

[0048] Figure 5(c) shows the pattern formation surface of the third dielectric layer 53. Conductor layers 531, 532, and 533 are formed on the pattern formation surface of the dielectric layer 53. The through hole labeled 53T1a in Figure 5(c) is connected to the conductor layer 531. In the following description, the through hole labeled 53T1a will be simply referred to as through hole 53T1a. Also, for through holes labeled with symbols other than 53T1a, they will be described in the same manner as through hole 53T1a.

[0049] Figure 6(a) shows the pattern formation surface of the fourth dielectric layer 54. A conductor layer 541 is formed on the pattern formation surface of the dielectric layer 54. The through hole 54T1b shown in Figure 6(a) is connected to the conductor layer 541. The through hole 53T1a is connected to the through hole 54T1a shown in Figure 6(a).

[0050] Figure 6(b) shows the pattern formation surfaces of the fifth and sixth dielectric layers 55 and 56, respectively. The through holes 54T1a and 54T1b are connected to the through holes 55T1a and 55T1b formed in the dielectric layer 55, respectively. Also, in the dielectric layers 55 and 56, the through holes with the same symbol that are adjacent vertically are connected to each other.

[0051] Figure 6(c) shows the pattern formation surface of the seventh dielectric layer 57. A conductor layer 571 is formed on the pattern formation surface of the dielectric layer 57. The through holes 55T1a and 55T1b formed in the dielectric layer 56 are connected to the through holes 57T1a and 57T1b shown in Figure 6(c), respectively.

[0052] Figure 7(a) shows the pattern formation surfaces of the eighth and ninth dielectric layers 58 and 59, respectively. The through holes 57T1a and 57T1b are connected to the through holes 58T1a and 58T1b formed in the dielectric layer 58, respectively. Also, in the dielectric layers 58 and 59, the through holes with the same symbol that are adjacent vertically are connected to each other.

[0053] FIG. 7(b) shows the pattern formation surface of the 10th dielectric layer 60. Conductor layers 602, 606, and 607 for inductors are formed on the pattern formation surface of the dielectric layer 60. The through holes 58T1a and 58T1b formed in the dielectric layer 59 are connected to the through holes 60T1a and 60T1b shown in FIG. 7(b), respectively.

[0054] FIG. 7(c) shows the pattern formation surface of the 11th dielectric layer 61. Conductor layers 612, 614, 616, and 617 for inductors are formed on the pattern formation surface of the dielectric layer 61. The through holes 60T1a and 60T1b are connected to the through holes 61T1a and 61T1b shown in FIG. 7(c), respectively.

[0055] FIG. 8(a) shows the pattern formation surface of the 12th dielectric layer 62. Conductor layers 622, 623, 626, and 627 for inductors are formed on the pattern formation surface of the dielectric layer 62. The through holes 61T1a and 61T1b are connected to the through holes 62T1a and 62T1b shown in FIG. 8(a), respectively.

[0056] FIG. 8(b) shows the pattern formation surface of the 13th dielectric layer 63. Conductor layers 632, 633, 635, 636, and 637 for inductors are formed on the pattern formation surface of the dielectric layer 63. The through holes 62T1a and 62T1b are connected to the through holes 63T1a and 63T1b shown in FIG. 8(b), respectively.

[0057] FIG. 8(c) shows the pattern formation surface of the 14th dielectric layer 64. On the pattern formation surface of the dielectric layer 64, conductor layers 641a, 641b, 642, 643, 644, 646, 647, 648 and a conductor layer 645 for an inductor are formed. The conductor layer 646 is connected to the conductor layer 644. In FIG. 8(c), the boundary between the conductor layer 644 and the conductor layer 646 is indicated by a dotted line. The through hole 63T1a and the through hole 64T1a shown in FIG. 8(c) are connected to the conductor layer 641a. The through hole 63T1b and the through hole 64T1b shown in FIG. 8(c) are connected to the conductor layer 641b. The through hole 64T5 shown in FIG. 8(c) is connected to the conductor layer 647.

[0058] FIG. 9(a) shows the pattern formation surface of the 15th dielectric layer 65. On the pattern formation surface of the dielectric layer 65, conductor layers 651, 652, 653, 654 are formed. The conductor layer 654 is connected to the conductor layer 653. In FIG. 9(a), the boundary between the conductor layer 653 and the conductor layer 654 is indicated by a dotted line. The through holes 64T1a, 64T1b are connected to the through holes 65T1a, 65T1b shown in FIG. 9(a), respectively. The through hole 64T5 and the through hole 65T5 shown in FIG. 9(a) are connected to the conductor layer 651.

[0059] FIG. 9(b) shows the pattern formation surface of the 16th dielectric layer 66. On the pattern formation surface of the dielectric layer 66, conductor layers 661, 662, 663 are formed. The conductor layer 662 is connected to the conductor layer 661. In FIG. 9(b), the boundary between the conductor layer 661 and the conductor layer 662 is indicated by a dotted line. The through holes 65T1a, 65T1b are connected to the through holes 66T1a, 66T1b shown in FIG. 9(b), respectively. The through hole 66T3 shown in FIG. 9(b) is connected to the conductor layer 661. The through hole 65T5 is connected to the through hole 66T5 shown in FIG. 9(b).

[0060] Fig. 9(c) shows the pattern formation surface of the 17th dielectric layer 67. Conductor layers 671, 672, 673, 675, 676, 677 for inductors are formed on the pattern formation surface of the dielectric layer 67. The conductor layer 671 has a first end and a second end located on opposite sides of each other in the longitudinal direction of the conductor layer 671. The through-hole 66T1a and the through-hole 67T1a shown in Fig. 9(c) are connected to the vicinity of the first end of the conductor layer 671. The through-hole 66T1b and the through-hole 67T1b shown in Fig. 9(c) are connected to the vicinity of the second end of the conductor layer 671. The through-hole 66T3 is connected to the through-hole 67T3 shown in Fig. 9(c). The through-hole 66T5 is connected to the conductor layer 673.

[0061] Fig. 10(a) shows the pattern formation surface of the 18th dielectric layer 68. Conductor layers 681, 682, 683, 684, 685, 686, 687 for inductors are formed on the pattern formation surface of the dielectric layer 68. The conductor layer 681 has a first end and a second end located on opposite sides of each other in the longitudinal direction of the conductor layer 681. The through-hole 67T1a is connected to the vicinity of the first end of the conductor layer 681. The through-hole 67T1b is connected to the vicinity of the second end of the conductor layer 681. The through-holes 68T1, 68T2, 68T4 shown in Fig. 10(a) are connected to the conductor layers 682, 683, 684, respectively. The through-hole 67T3 is connected to the through-hole 68T3 shown in Fig. 10(a).

[0062] Fig. 10(b) shows the pattern formation surface of the 19th dielectric layer 69. Conductor layers 691, 692, 693, 694 are formed on the pattern formation surface of the dielectric layer 69. The through-hole 68T1 and the through-hole 69T1 shown in Fig. 10(b) are connected to the conductor layer 691. The through-hole 68T2 and the through-hole 69T2 shown in Fig. 10(b) are connected to the conductor layer 692. The through-hole 68T3 and the through-hole 69T3 shown in Fig. 10(b) are connected to the conductor layer 693. The through-hole 68T4 and the through-hole 69T4 shown in Fig. 10(b) are connected to the conductor layer 694.

[0063] Figure 10(c) shows the surface of the 19th dielectric layer 69 opposite to the pattern formation surface. Hereinafter, the surface of the dielectric layer 69 opposite to the pattern formation surface is referred to as the electrode formation surface of the dielectric layer 69. Electrodes 121, 122, 123, and 124 are formed on the electrode formation surface of the dielectric layer 69. Through holes 69T1, 69T2, 69T3, and 69T4 are respectively connected to electrodes 121, 122, 123, and 124.

[0064] The laminate 50 is configured by laminating the 1st to 19th dielectric layers 51 to 69 such that the pattern formation surface of the 1st dielectric layer 51 becomes the second surface 50B of the laminate 50, and the electrode formation surface of the 19th dielectric layer 69 becomes the first surface 50A of the laminate 50.

[0065] Each of the plurality of through holes shown in FIGS. 5(a) to 10(b) is connected to a conductor layer overlapping in the stacking direction T or another through hole overlapping in the stacking direction T when the 1st to 19th dielectric layers 51 to 69 are laminated. Among the plurality of through holes shown in FIGS. 5(a) to 10(b), the through holes located within the electrode or the conductor layer are connected to that electrode or that conductor layer.

[0066] Figure 11 shows the inside of the laminate 50 configured by laminating the 1st to 19th dielectric layers 51 to 69. As shown in Figure 11, inside the laminate 50, the plurality of conductor layers and the plurality of through holes shown in FIGS. 5(a) to 10(c) are laminated.

[0067] The correspondence between the components of the circuit of the electronic component 1 shown in FIG. 1 and the internal components of the laminate 50 shown in FIGS. 5(a) to 10(c) will be described below. The inductor L1 is composed of inductor conductor layers 671 and 681, conductor layers 641a and 641b, and through holes 53T1a, 54T1a, 54T1b, 55T1a, 55T1b, 57T1a, 57T1b, 58T1a, 58T1b, 60T1a, 60T1b, 61T1a, 61T1b, 62T1a, 62T1b, 63T1a, 63T1b, 64T1a, 64T1b, 65T1a, 65T1b, 66T1a, 66T1b, 67T1a, 67T1b.

[0068] The inductor L2 is composed of inductor conductor layers 602, 612, 622, 632, 672, 682 and a plurality of through holes connecting these conductor layers. The conductor layer 682 is connected to the electrode 121 via the through hole 68T1, the conductor layer 691 and the through hole 69T1.

[0069] The inductor L3 is composed of inductor conductor layers 623, 633, 673, 683 and a plurality of through holes connecting these conductor layers. The conductor layer 683 is connected to the electrode 122 via the through hole 68T2, the conductor layer 692 and the through hole 69T2.

[0070] The inductor L4 is composed of inductor conductor layers 614, 684, conductor layers 533, 571, a plurality of through holes connecting the conductor layers 614, 684, a plurality of through holes connecting the conductor layers 571, 614, a plurality of through holes connecting the conductor layers 533, 571, and a through hole connecting the conductor layers 525, 533. The conductor layer 684 is connected to the electrode 124 via the through hole 68T4, the conductor layer 694 and the through hole 69T4.

[0071] Inductor L5 is composed of conductor layers 635, 645, 675, 685 for the inductor and a plurality of through holes connecting these conductor layers. Inductor L6 is composed of conductor layers 606, 616, 626, 636, 676, 686 for the inductor and a plurality of through holes connecting these conductor layers. Inductor L7 is composed of conductor layers 607, 617, 627, 637, 677, 687 for the inductor and a plurality of through holes connecting these conductor layers.

[0072] Capacitor C1 is composed of conductor layers 521, 522, 531, 541 and dielectric layers 52, 53 between these conductor layers. Capacitor C2 is composed of electrodes 111, 117, conductor layers 521, 522, and dielectric layer 51 between electrodes 111, 117 and conductor layers 521, 522.

[0073] Capacitor C3 is composed of conductor layers 633, 642 and dielectric layer 63 between these conductor layers. Capacitor C4 is composed of conductor layers 643, 651 and dielectric layer 64 between these conductor layers.

[0074] Capacitor C5 is composed of conductor layers 651, 661 and dielectric layer 65 between these conductor layers. Conductor layer 661 is connected to electrode 123 via through holes 66T3, 67T3, 68T3, conductor layer 693, and through hole 69T3.

[0075] Capacitor C6 is composed of conductor layers 652, 662 and dielectric layer 65 between these conductor layers. Capacitor C7 is composed of conductor layers 644, 652 and dielectric layer 64 between these conductor layers. Capacitor C8 is composed of conductor layers 646, 653 and dielectric layer 64 between these conductor layers.

[0076] The capacitor C9 is composed of conductor layers 636 and 647 and a dielectric layer 63 between these conductor layers. The conductor layer 647 is connected to the conductor layer 673 for the inductor that constitutes the inductor L3 via through holes 64T5, 65T5, and 66T5.

[0077] The capacitor C10 is composed of conductor layers 523 and 532 and a dielectric layer 52 between these conductor layers. The capacitor C11 is composed of conductor layers 648, 654, and 663 and dielectric layers 64 and 65 between these conductor layers.

[0078] Next, with reference to FIGS. 2 to 12, the structural features of the multilayer electronic component 5 according to the present embodiment will be described. FIG. 12 is a plan view showing the inside of the multilayer electronic component 5.

[0079] First, two regions of the multilayer electronic component 5 defined by the mounted component 80 will be described. As described above, the mounted component 80 is mounted on the first surface 50A of the laminate 50. The multilayer electronic component 5 includes a first region R1 that overlaps the mounted component 80 when viewed in the stacking direction T and a second region R2 that does not overlap the mounted component 80 when viewed in the stacking direction T. The first region R1 is defined as a three-dimensional region whose end in the Z direction exists on the first surface 50A and whose end in the -Z direction exists on the second surface 50B. In FIG. 12, the outer edge of the first region R1 including the ends in the X direction, -X direction, Y direction, and -Y direction of the first region R1 is shown by a two-dot chain line of a rectangle marked with the symbol R1.

[0080] The second region R2 is defined as the region obtained by removing the first region R1 from a three-dimensional region substantially surrounded by the outer peripheral surface of the laminate 50. The second region R2 covers at least a part of the outer peripheral portion of the first region R1. In particular, in the present embodiment, the second region R2 covers a portion of the outer peripheral portion of the first region R1 excluding the end in the Z direction (the first surface 50A) and the end in the -Z direction (the second surface 50B). In FIG. 12, the outer edge of the second region R2 including the ends in the X direction, -X direction, Y direction, and -Y direction of the second region R2 is indicated by a two-dot chain line of a rectangle to which the symbol R2 is attached. In FIG. 12, for the sake of convenience, the outer edge of the second region R2 is drawn apart from the side surfaces 50C to 50F of the laminate 50.

[0081] The planar shape of the mounted component 80 (the shape as viewed from the lamination direction T) may be the same as the shape of the first region R1. Alternatively, the mounted component 80 may include a first portion having the same planar shape as the shape of the first region R1 and a second portion having a planar shape size different from the planar shape size of the first region R1. In this case, the mounted component 80 is mounted on the laminate 50 in a posture such that the first portion is located between the laminate 50 and the second portion.

[0082] Next, the characteristics regarding the inductors L2, L3, L5, L6, and L7 will be described. The inductor L2 is wound around an axis extending in a direction parallel to the lamination direction T so that an opening surrounded by the inductor L2 is formed. Hereinafter, the opening surrounded by the inductor L2 will be referred to as the opening of the inductor L2. The opening of the inductor L2 faces the first surface 50A of the laminate 50. Further, the entire opening of the inductor L2 exists in the second region R2. Hereinafter, for inductors other than the inductor L2, the opening surrounded by the inductor will also be referred to as the opening of the inductor.

[0083] Similarly, each of the inductors L3, L5, L6, and L7 is wound around an axis extending in a direction parallel to the stacking direction T such that an opening surrounded by each of the inductors L3, L5, L6, and L7 is formed. Each of the openings of the inductors L3, L5, L6, and L7 faces the first surface 50A of the laminate 50. Most of each of the openings of the inductors L3 and L5 exists in the second region R2. The entirety of each of the openings of the inductors L6 and L7 exists in the second region R2.

[0084] The inductor L2 includes a plurality of conductor layers 602, 612, 622, 632, 672, and 682 for inductors arranged at a predetermined interval in the stacking direction T. Each of the conductor layers 602, 612, 622, 632, 672, and 682 is wound around an axis extending in a direction parallel to the stacking direction T so as to surround the opening of the inductor L2.

[0085] The inductor L3 includes a plurality of conductor layers 623, 633, 673, and 683 for inductors arranged at a predetermined interval in the stacking direction T. Each of the conductor layers 623, 633, 673, and 683 is wound around an axis extending in a direction parallel to the stacking direction T so as to surround the opening of the inductor L3.

[0086] The inductor L5 includes a plurality of conductor layers 635, 645, 675, and 685 for inductors arranged at a predetermined interval in the stacking direction T. Each of the conductor layers 635, 645, 675, and 685 is wound around an axis extending in a direction parallel to the stacking direction T so as to surround the opening of the inductor L5.

[0087] The inductor L6 includes a plurality of conductor layers 606, 616, 626, 636, 676, and 686 for inductors arranged at a predetermined interval in the stacking direction T. Each of the conductor layers 626, 636, 676, and 686 is wound around an axis extending in a direction parallel to the stacking direction T so as to surround the opening of the inductor L6. Each of the conductor layers 606 and 616 extends along the opening of the inductor L6.

[0088] Inductor L7 includes a plurality of conductor layers 607, 617, 627, 637, 677, 687 for inductors arranged at a predetermined interval in the stacking direction T. Each of the conductor layers 627, 637, 677, 687 is wound around an axis extending in a direction parallel to the stacking direction T so as to surround the opening of the inductor L7. Each of the conductor layers 607, 617 extends along the opening of the inductor L7.

[0089] Next, the characteristics regarding inductors L1 and L4 will be described. Inductor L1 is wound around an axis extending in a direction orthogonal to the stacking direction T so that an opening surrounded by the inductor L1 is formed. The opening of the inductor L1 faces the side surface 50C of the laminate 50.

[0090] Inductor L4 has a shape such that an opening surrounded by the inductor L4 is not formed.

[0091] Next, the characteristics regarding the relationship between inductors L3 and L6 and capacitor C9 will be described. As shown in FIG. 1, between inductor L3 and inductor L6, on the circuit configuration, an elastic wave element 32, inductors L4, L5 and capacitors C5, C6, C7, C8 are provided. Also, inductor L3 and inductor L6 are capacitively coupled by capacitor C9.

[0092] Here, with reference to FIG. 13, the connection between inductor L6 and capacitor C9 will be described. FIG. 13 is a circuit diagram showing the configuration of inductor L6. Inductor L6 can be divided into two inductor portions L61 and L62. The two inductor portions L61 and L62 are connected in series. In FIG. 13, reference symbol L6a indicates the first end of inductor L6, reference symbol L6b indicates the second end of inductor L6, and reference symbol L6c indicates a node located between the two inductor portions L61 and L62. The second end L6b of inductor L6 is connected to the ground.

[0093] In FIG. 1, for the sake of convenience, one end of capacitor C9 is depicted as being connected to the first end L6a of inductor L6. However, one end of capacitor C9 may be connected to the first end L6a of inductor L6 in terms of circuit configuration, or may be connected between the first end L6a and the second end L6b of inductor L6 in terms of circuit configuration. In the examples of the plurality of conductor layers and the plurality of through holes shown in FIGS. 5(a) to 12, one end of capacitor C9 is connected between the first end L6a and the second end L6b of inductor L6 in terms of circuit configuration.

[0094] When one end of capacitor C9 is connected to the node L6c of inductor L6 that is between the first end L6a and the second end L6b of inductor L6, by adjusting the physical connection position of capacitor C9 to inductor L6, the inductance of each of inductor portions L61 and L62 can be adjusted. Also, in this case, the substantial impedance of inductor L6 is determined by the inductance of inductor portion L62. By adjusting the physical connection position of capacitor C9 to inductor L6, the substantial impedance of inductor L6 can be adjusted.

[0095] Next, with reference to FIGS. 14 to 16, the features regarding the arrangement of inductors L3, L6 and capacitor C9 will be described. FIGS. 14 and 15 are plan views showing inductors L3, L6 and capacitor C9. FIG. 16 is an explanatory view showing the arrangement in the laminate 50 of inductors L3, L6 and capacitor C9. In FIGS. 14 and 15, reference sign L3o indicates the opening of inductor L3, and reference sign L6o indicates the opening of inductor L6.

[0096] As described above, the inductor L3 is composed of conductor layers 623, 633, 673, 683 for the inductor and a plurality of through-holes connected to these conductor layers. In FIGS. 14 to 16, reference sign A3 indicates an axis that passes through the opening L3o of the inductor L3 and extends in a direction parallel to the stacking direction T. The conductor layers 623, 633, 673, 683 are wound around the axis A3 as a whole. In particular, in the present embodiment, each of the conductor layers 623, 633, 673, 683 is wound around the axis A3.

[0097] As described above, the inductor L6 is composed of conductor layers 606, 616, 626, 636, 676, 686 for the inductor and a plurality of through-holes connected to these conductor layers. In FIGS. 14 to 16, reference sign A6 indicates an axis that passes through the opening L6o of the inductor L6 and extends in a direction parallel to the stacking direction T. The conductor layers 606, 616, 626, 636, 676, 686 are wound around the axis A6 as a whole. In particular, in the present embodiment, each of the conductor layers 606, 616, 626, 636, 676, 686 is wound around the axis A6.

[0098] The inductor L3 and the inductor L6 are arranged such that the opening L3o of the inductor L3 and the opening L6o of the inductor L6 do not face each other. In particular, in the present embodiment, the inductor L3 and the inductor L6 are arranged side by side in the X direction in a posture such that the openings L3o, L6o face the first surface 50A of the laminate 50.

[0099] Here, the third region R3 and the fourth region R4 defined by the inductors L3 and L6 will be described. As shown in FIGS. 14 and 15, the third region R3 is a planar region and is a rectangular virtual region having four sides R3a, R3b, R3c, R3d. Each of the four sides R3a, R3b, R3c, R3d overlaps the outer edge of the conductor layer constituting one of the inductors L3 and L6 when viewed from the stacking direction T, but does not overlap the portion excluding the outer edge of the conductor layer constituting the other of the inductors L3 and L6.

[0100] The first side R3a is located at the -X direction side end in the third region R3 and extends in a direction parallel to the Y direction. The first side R3a overlaps with the outer edges of each of the conductor layers 673 and 683 when viewed from the stacking direction T.

[0101] The second side R3b is located at the X direction side end in the third region R3 and extends in a direction parallel to the Y direction. The second side R3b overlaps with the outer edges of each of the conductor layers 626, 636, 676, and 686 when viewed from the stacking direction T.

[0102] The third side R3c is located at the -Y direction side end in the third region R3 and extends in a direction parallel to the X direction. The third side R3c overlaps with the outer edges of each of the conductor layers 623, 626, 633, 636, 673, 676, 683, and 686 when viewed from the stacking direction T.

[0103] The fourth side R3d is located at the Y direction side end in the third region R3 and extends in a direction parallel to the X direction. The fourth side R3d overlaps with the outer edges of the conductor layers 606 and 616 when viewed from the stacking direction T.

[0104] As shown in FIG. 16, the fourth region R4 is a planar region and is a rectangular virtual region having four sides R4a, R4b, R4c, and R4d. Each of the four sides R4a, R4b, R4c, and R4d overlaps with the outer edge or surface of the conductor layer constituting one of the inductor L3 and the inductor L6 when viewed from the -Y direction which is a direction orthogonal to the stacking direction T, but does not overlap with the portion excluding the outer edge or surface of the conductor layer constituting the other of the inductor L3 and the inductor L6.

[0105] The first side R4a is located at the -X direction side end in the fourth region R4 and extends in a direction parallel to the Z direction. The first side R4a overlaps with the outer edges of each of the conductor layers 673 and 683 when viewed from the -Y direction.

[0106] The second side R4b is located at the X-direction side end in the fourth region R4 and extends in a direction parallel to the Z direction. The second side R4b overlaps with the outer edge of each of the conductor layers 626, 636, 676, and 686 when viewed from the -Y direction.

[0107] The third side R4c is located at the -Z-direction side end in the fourth region R4 and extends in a direction parallel to the X direction. The third side R4c overlaps with the surface of the conductor layer 606 when viewed from the -Y direction. In FIG. 16, for the sake of convenience, the third side R4c is drawn separated from the conductor layer 606.

[0108] The fourth side R4d is located at the Z-direction side end in the fourth region R4 and extends in a direction parallel to the X direction. The fourth side R4d overlaps with the surface of each of the conductor layers 683 and 686 when viewed from the -Y direction. In FIG. 16, for the sake of convenience, the fourth side R4d is drawn separated from the conductor layers 683 and 686.

[0109] Next, with reference to FIGS. 14 to 16, the relationship between the capacitor C9 and the third and fourth regions R3 and R4 will be described. As described above, the capacitor C9 is composed of the conductor layers 636 and 647 and the dielectric layer 63 between these conductor layers. The conductor layers 636 and 647 are within the third region R3 when viewed from the stacking direction T. In particular, the conductor layer 647 is at a position separated from the four sides R3a, R3b, R3c, and R3d of the third region R3 when viewed from the stacking direction T. Also, the conductor layers 636 and 647 are within the fourth region R4 when viewed from the -Y direction. In particular, the conductor layer 647 is at a position separated from the four sides R4a, R4b, R4c, and R4d of the fourth region R4 when viewed from the -Y direction.

[0110] Here, assume a three-dimensional space within the laminate 50 where the planar shape viewed from the stacking direction T is equal to the third region R3 and the planar shape viewed from the -Y direction is equal to the fourth region R4. This three-dimensional space is also the three-dimensional space defined by the inductors L3 and L6. The conductor layers 636 and 647 that constitute the capacitor C9 exist within this three-dimensional space. In particular, the conductor layer 647 is positioned between the conductor layer 606 located at the -Z direction end of this three-dimensional space and the conductor layers 683 and 686 located at the Z direction end of this three-dimensional space in the stacking direction T. The conductor layer 647 is further positioned between the conductor layer 623 and the conductor layer 686 in the stacking direction T.

[0111] Next, with reference to FIGS. 14 and 15, features regarding the plurality of conductor layers that constitute the inductors L3, L6, and the capacitor C9 will be described. The conductor layer 647 that constitutes the capacitor C9 is electrically connected to the conductor layer 673 that constitutes the inductor L3 via the through holes 64T5, 65T5, and 66T5.

[0112] When viewed from the stacking direction T, the conductor layer 647 extends from the conductor layers 623, 633, 673, 683 that constitute the inductor L3 toward the conductor layers 606, 616, 626, 636, 676, 686 that constitute the inductor L6. Also, the conductor layer 647 extends from the outside of the conductor layers 606, 616, 626, 636, 676, 686 toward the opening L6o of the inductor L6.

[0113] In particular, in this embodiment, when viewed from the stacking direction T, the conductor layer 647 extends so as to overlap the conductor layer 636. The conductor layer 636 is disposed between the conductor layer 606 and the conductor layer 683 in the stacking direction T. The conductor layer 636 and the conductor layer 647 face each other with the dielectric layer 63 therebetween. The conductor layer 647 includes a first overlap portion 647B that overlaps the conductor layer 636 when viewed from the stacking direction T.

[0114] The conductor layer 647 further includes two non-overlap portions 647A and 647C that do not overlap with the conductor layer 636 when viewed in the stacking direction T. The non-overlap portion 647A is connected to one end of the first overlap portion 647B. In FIG. 14, the boundary between the non-overlap portion 647A and the first overlap portion 647B is indicated by a dashed line. Also, the non-overlap portion 647A is disposed outside the conductor layer 636 when viewed in the stacking direction T. The non-overlap portion 647A is connected to the conductor layer 673 that constitutes the inductor L3 via through holes 64T5, 65T5, and 66T5.

[0115] The non-overlap portion 647C is connected to the other end of the first overlap portion 647B. In FIG. 14, the boundary between the non-overlap portion 647C and the first overlap portion 647B is indicated by a dashed line. Also, the non-overlap portion 647C overlaps with the opening L6o of the inductor L6 when viewed in the stacking direction T. The area of the non-overlap portion 647C is smaller than the area of the first overlap portion 647B.

[0116] As shown in FIG. 14, the conductor layer 647 has a first edge 647a and a second edge 647b located at both longitudinal ends of the conductor layer 647. The first edge 647a is also the edge of the non-overlap portion 647A. The first edge 647a is located on the side opposite to the boundary between the non-overlap portion 647A and the first overlap portion 647B in the longitudinal direction of the conductor layer 647. The second edge 647b is also the edge of the non-overlap portion 647C. The second edge 647b is located on the side opposite to the boundary between the non-overlap portion 647C and the first overlap portion 647B in the longitudinal direction of the conductor layer 647.

[0117] The conductor layer 636 extends so as to surround the opening L6o of the inductor L6. In particular, in this embodiment, the conductor layer 636 includes a plurality of curved portions. The first overlap portion 647B overlaps with the curved portion when viewed in the stacking direction T. The second edge 647b of the non-overlap portion 647C has a shape along the curve of the curved portion of the conductor layer 636. The second edge 647b may be linear or curved.

[0118] Also, as shown in FIG. 8(b), the conductor layer 636 includes an extending portion 636a having a predetermined length and a smooth outer edge. The width of the extending portion 636a in the short side direction of the conductor layer 636 may be substantially constant. Note that the “extending portion with a substantially constant width” includes portions where the width slightly changes in the curved portion and portions where the width changes due to manufacturing variations, but does not include portions where the width is intentionally changed such as a stepped shape. In this embodiment, the extending portion includes the plurality of curved portions described above. The conductor layer 636 further includes two connection portions 636b and 636c connected to the extending portion 636a at both longitudinal ends of the extending portion 636a. Through holes are connected to the two connection portions 636b and 636c, respectively.

[0119] The first overlap portion 647B overlaps with the extending portion 636a of the conductor layer 636 when viewed in the stacking direction T. As shown in FIG. 15, the extending portion 636a includes a second overlap portion 636A that overlaps with the first overlap portion 647B of the conductor layer 647 when viewed in the stacking direction T and forms a capacitor C9 together with the first overlap portion 647B. In FIG. 15, hatching is applied to the second overlap portion 636A for easy understanding. Note that since the extending portion 636a is a part of the conductor layer 636, it can also be said that the conductor layer 636 includes the second overlap portion 636A.

[0120] Next, an example of the characteristics of the electronic component 1 in the present embodiment is shown. FIG. 17 is a characteristic diagram showing an example of the passing attenuation characteristics of the electronic component 1. In FIG. 17, the horizontal axis represents the frequency, and the vertical axis represents the attenuation amount. From FIG. 17, it can be seen that the electronic component 1 has practically sufficient characteristics as a band-pass filter.

[0121] Next, the operation and effects of the multilayer electronic component 5 according to the present embodiment will be described. The multilayer electronic component 5 according to the present embodiment includes an inductor L3 and an inductor L6. A plurality of elements are provided between the inductor L3 and the inductor L6 in terms of circuit configuration. In such a configuration, when the inductive coupling between the inductor L3 and the inductor L6 becomes strong, the desired characteristics may not be obtained. In contrast, in the present embodiment, the inductor L3 and the inductor L6 are arranged such that the opening L3o of the inductor L3 and the opening L6o of the inductor L6 do not face each other. According to the present embodiment, it is possible to suppress the impairment of the functions of each of the inductors L3 and L6 and realize the desired characteristics.

[0122] Further, the multilayer electronic component 5 according to the present embodiment includes a capacitor C9 that realizes a capacitive jump coupling between the inductor L3 and the inductor L6. In the present embodiment, although a plurality of elements are provided between the inductor L3 and the inductor L6, the inductor L3 and the inductor L6 are arranged side by side. According to the present embodiment, it becomes easy to provide the capacitor C9 in the laminate 50 of the multilayer electronic component 5.

[0123] In addition, in the present embodiment, the conductor layer 647 forming the capacitor C9 includes a first overlapping portion 647B that overlaps with the inductor conductor layer 636 forming the inductor L6 when viewed in the stacking direction T. According to this embodiment, a capacitor C9 having a predetermined function can be realized without using a conductor layer other than the conductor layer 636 facing the conductor layer 647. Further, according to this embodiment, by opposing a part of the conductor layer 636 to the first overlapping portion 647B, the capacitor C9 can be realized without impairing the function of the inductor L6. Also, according to this embodiment, the stacked electronic component 5 can be miniaturized as compared with the case where the capacitor C9 is formed without using the conductor layer 636.

[0124] In addition, in the present embodiment, the conductor layer 647 is within a third region R3 defined by the inductors L3 and L6 when viewed in the stacking direction T. According to this embodiment, the stacked electronic component 5 can be miniaturized as compared with the case where the conductor layer 647 is outside the third region R3. Similarly, the conductor layer 647 is within a fourth region R4 defined by the inductors L3 and L6 when viewed in the -Y direction. According to this embodiment, the stacked electronic component 5 can be miniaturized as compared with the case where the conductor layer 647 is outside the fourth region R4.

[0125] In addition, in the present embodiment, the conductor layer 636 that the first overlapping portion 647B overlaps is disposed between the other two conductor layers 606 and 686 that form the inductor L6 in the stacking direction T. According to this embodiment, when the conductor layer forming the capacitor C9 is disposed closer to the second surface 50B of the stacked body 50 than the conductor layer 606, or when the conductor layer forming the capacitor C9 is disposed closer to the first surface 50A of the stacked body 50 than the conductor layer 686, the stacked electronic component 5 can be miniaturized.

[0126] Further, in the present embodiment, the conductor layer 647 includes non-overlapping portions 647A and 647C in addition to the first overlapping portion 647B. According to the present embodiment, even when the conductor layers 636 and 647 are displaced in a direction orthogonal to the stacking direction T due to stacking misalignment during manufacturing, it is possible to suppress fluctuations in the area of the first overlapping portion 647B. As a result, according to the present embodiment, it is possible to suppress displacement of the characteristics of the stacked electronic component 5 due to stacking misalignment during manufacturing.

[0127] Also, in the present embodiment, the set of inductors L2 and L3 and capacitor C3 has the same characteristics as the set of inductors L3 and L6 and capacitor C9. That is, in the present embodiment, the inductor L2 and the inductor L3 are arranged such that the opening of the inductor L2 and the opening L3o of the inductor L3 do not face each other. The conductor layer 642 constituting the capacitor C3 includes an overlapping portion that overlaps the inductor conductor layer 633 constituting the inductor L3 when viewed from the stacking direction T. According to the present embodiment, it is possible to miniaturize the stacked electronic component 5 while suppressing impairment of the functions of the inductors L2 and L3.

[0128] Next, other effects of the stacked electronic component 5 according to the present embodiment will be described. In the present embodiment, most of the opening L3o of the inductor L3 exists in the second region R2, and the entire opening L6o of the inductor L6 exists in the second region R2. According to the present embodiment, it is possible to suppress the electromagnetic field from acting on each of the inductors L3 and L6 and the mounted component 80, thereby realizing desired characteristics.

[0129] Similarly, in the present embodiment, the entire opening of each of the inductors L2 and L7 exists in the second region R2, and most of the opening of the inductor L5 exists in the second region R2. According to the present embodiment, it is possible to suppress the electromagnetic field from acting on each of the inductors L2, L5, and L7 and the mounted component 80, thereby realizing desired characteristics.

[0130] Note that the present invention is not limited to the above-described embodiments, and various modifications are possible. For example, the electronic component including the laminated electronic component of the present invention is not limited to a band-pass filter, and can be applied to other filters such as a low-pass filter and a high-pass filter, and an electronic component including a plurality of resonators such as a demultiplexer that separates a plurality of signals having different frequency bands.

[0131] As described above, the laminated electronic component according to the first aspect of the present invention includes a first inductor, a second inductor, a capacitor, and a laminate for integrating the first inductor, the second inductor, and the capacitor, the laminate including a plurality of stacked dielectric layers. The first inductor includes at least one first inductor conductor layer wound around a first axis extending in a direction parallel to the stacking direction of the plurality of dielectric layers. The second inductor includes at least one second inductor conductor layer wound around a second axis extending in a direction parallel to the stacking direction. The first inductor and the second inductor are arranged such that a first opening surrounded by at least one first inductor conductor layer and a second opening surrounded by at least one second inductor conductor layer do not overlap when viewed from the stacking direction. The capacitor includes a capacitor conductor layer. The capacitor conductor layer extends from at least one second inductor conductor layer toward at least one first inductor conductor layer when viewed from the stacking direction, and includes a first overlap portion that overlaps at least one first inductor conductor layer when viewed from the stacking direction.

[0132] In the multilayer electronic component according to the first aspect of the present invention, at least one first inductor conductor layer may be one first inductor conductor layer or a plurality of first inductor conductor layers. As long as the requirement that the whole of the plurality of first inductor conductor layers is wound around the first axis is satisfied, each of the plurality of first inductor conductor layers may have a shape that is not wound around the first axis, such as a linear shape. Similarly, at least one second inductor conductor layer may be one second inductor conductor layer or a plurality of second inductor conductor layers. As long as the requirement that the whole of the plurality of inductor conductor layers is wound around the second axis is satisfied, each of the plurality of second inductor conductor layers may have a shape that is not wound around the second axis, such as a linear shape.

[0133] In the multilayer electronic component according to the first aspect of the present invention, the capacitor conductor layer may be electrically connected to at least one second inductor conductor layer.

[0134] Further, in the multilayer electronic component according to the first aspect of the present invention, at least one first inductor conductor layer may overlap with the first overlap portion when viewed in the stacking direction and include a second overlap portion that forms a capacitor together with the first overlap portion. At least one first inductor conductor layer may include an extending portion having a predetermined length and a smooth outer edge. The second overlap portion may be a part of the extending portion.

[0135] Further, in the multilayer electronic component according to the first aspect of the present invention, the capacitor conductor layer may be within a virtual region in the shape of a rectangle having four sides when viewed in the stacking direction. Each of the four sides may overlap with the outer edge of one of at least one first inductor conductor layer and at least one second inductor conductor layer when viewed in the stacking direction, but may not overlap with a portion excluding the outer edge of the other of at least one first inductor conductor layer and at least one second inductor conductor layer.

[0136] Also, in the laminated electronic component according to the first aspect of the present invention, at least one first inductor conductor layer may be a plurality of first inductor conductor layers. The plurality of first inductor conductor layers may include a first specific inductor conductor layer and a second specific inductor conductor layer arranged at a predetermined interval in the stacking direction. The capacitor conductor layer may be arranged between the first specific inductor conductor layer and the second specific inductor conductor layer in the stacking direction. The plurality of first inductor conductor layers may further include a third specific inductor conductor layer arranged between the first specific inductor conductor layer and the second specific inductor conductor layer in the stacking direction. The first overlap portion may overlap the third specific inductor conductor layer when viewed from the stacking direction. At least one second inductor conductor layer may be a plurality of second inductor conductor layers. The plurality of second inductor conductor layers may include a third specific inductor conductor layer located at the tip in one direction parallel to the stacking direction and a fourth specific inductor conductor layer located at the tip in the direction opposite to the one direction. The capacitor conductor layer may be arranged between the third specific inductor conductor layer and the fourth specific inductor conductor layer in the stacking direction.

[0137] Also, in the laminated electronic component according to the first aspect of the present invention, the capacitor conductor layer may further include a non-overlap portion connected to the first overlap portion and overlapping the first opening when viewed from the stacking direction. The area of the non-overlap portion may be smaller than the area of the first overlap portion. The non-overlap portion may have an edge shaped along the curve of at least one first inductor conductor layer.

[0138] Also, in the laminated electronic component according to the first aspect of the present invention, the first inductor may have a first end and a second end. The capacitor may be connected between the first end and the second end of the first inductor in terms of circuit configuration.

[0139] The multilayer electronic component according to the second aspect of the present invention includes an inductor, a capacitor, and a laminate for integrating the inductor and the capacitor, the laminate including a plurality of stacked dielectric layers. The inductor includes at least one inductor conductor layer wound around an axis extending in a direction parallel to the stacking direction of the plurality of dielectric layers. The at least one inductor conductor layer has a predetermined length and includes an extending portion having a smooth outer edge. The capacitor includes a capacitor conductor layer. The capacitor conductor layer extends toward an opening surrounded by the at least one inductor conductor layer from the outside of the at least one inductor conductor layer when viewed in the stacking direction, and includes a first overlapping portion that overlaps the extending portion when viewed in the stacking direction.

[0140] In the multilayer electronic component according to the second aspect of the present invention, the at least one inductor conductor layer may be one inductor conductor layer or a plurality of inductor conductor layers. As long as the requirement that the whole of the plurality of inductor conductor layers is wound around the above axis is satisfied, each of the plurality of inductor conductor layers may have a shape that is not wound around the above axis, such as a linear shape.

[0141] In the multilayer electronic component according to the second aspect of the present invention, the extending portion may include a second overlapping portion that overlaps the first overlapping portion when viewed in the stacking direction and constitutes a capacitor together with the first overlapping portion.

[0142] Also, in the multilayer electronic component according to the second aspect of the present invention, at least one inductor conductor layer may be a plurality of inductor conductor layers. The plurality of inductor conductor layers may include a first specific inductor conductor layer and a second specific inductor conductor layer arranged at a predetermined interval in the stacking direction. The capacitor conductor layer may be arranged between the first specific inductor conductor layer and the second specific inductor conductor layer in the stacking direction. The plurality of inductor conductor layers may further include a third specific inductor conductor layer arranged between the first specific inductor conductor layer and the second specific inductor conductor layer in the stacking direction. The first overlap portion may overlap the third specific inductor conductor layer when viewed from the stacking direction.

[0143] Also, in the multilayer electronic component according to the second aspect of the present invention, the capacitor conductor layer may further include a non-overlap portion connected to the first overlap portion and overlapping the opening when viewed from the stacking direction. The area of the non-overlap portion may be smaller than the area of the first overlap portion. The non-overlap portion may have an edge shaped along the curve of at least one inductor conductor layer.

[0144] Also, in the multilayer electronic component according to the second aspect of the present invention, the inductor may have a first end and a second end. The capacitor may be connected between the first end and the second end of the inductor in terms of circuit configuration.

Explanation of Reference Numerals

[0145] 1... Electronic component, 2... First input / output terminal, 3... Second input / output terminal, 5... Multilayer electronic component, 7... Solder bump, 11~14... Signal terminals, 31, 32... Piezoelectric element, 50... Laminate, 50A... First surface, 50B... Second surface, 50C~50F... Side surfaces, 51~69... Dielectric layers, 80... Mounted component, 81~84... Signal terminals, 90... Sealing portion, 111~119, 121~124... Electrodes, 636... Conductor layer for inductor, 636A... Second overlap portion, 647... Conductor layer, 647A, 647C... Non-overlap portions, 647B... First overlap portion, C1~C11... Capacitors, L1~L7... Inductors, R1... First region, R2... Second region, R3... Third region, R4... Fourth region.

Claims

1. a first inductor; a second inductor; a capacitor; and a laminate for integrating the first inductor, the second inductor, and the capacitor, the laminate including a plurality of stacked dielectric layers, wherein the first inductor includes at least one first inductor conductor layer wound around a first axis extending in a direction parallel to the stacking direction of the plurality of dielectric layers, the second inductor includes at least one second inductor conductor layer wound around a second axis extending in a direction parallel to the stacking direction, the first inductor and the second inductor are arranged such that a first opening surrounded by the at least one first inductor conductor layer and a second opening surrounded by the at least one second inductor conductor layer do not overlap when viewed from the stacking direction, the capacitor includes a capacitor conductor layer, and the capacitor conductor layer extends from the at least one second inductor conductor layer toward the at least one first inductor conductor layer when viewed from the stacking direction and includes a first overlap portion that overlaps the at least one first inductor conductor layer when viewed from the stacking direction, a multilayer electronic component characterized in that.

2. The multilayer electronic component according to claim 1, wherein the capacitor conductor layer is electrically connected to the at least one second inductor conductor layer.

3. The multilayer electronic component according to claim 1, wherein the at least one first inductor conductor layer includes a second overlap portion that overlaps the first overlap portion when viewed from the stacking direction and constitutes the capacitor together with the first overlap portion.

4. The at least one first inductor conductor layer includes an extending portion having a predetermined length and a smooth outer edge, and the second overlap portion is a part of the extending portion, the multilayer electronic component according to claim 3.

5. The capacitor conductor layer is within a virtual rectangular region having four sides when viewed from the stacking direction, Each of the four sides overlaps with an outer edge of one of the at least one first inductor conductor layer and the at least one second inductor conductor layer when viewed from the stacking direction, but does not overlap with a portion excluding the other outer edge of the at least one first inductor conductor layer and the at least one second inductor conductor layer. The stacked electronic component according to claim 1, characterized in that.

6. The at least one first inductor conductor layer is a plurality of first inductor conductor layers, The plurality of first inductor conductor layers include a first specific inductor conductor layer and a second specific inductor conductor layer arranged at a predetermined interval in the stacking direction, The capacitor conductor layer is arranged between the first specific inductor conductor layer and the second specific inductor conductor layer in the stacking direction. The stacked electronic component according to claim 1, characterized in that.

7. The plurality of first inductor conductor layers further include a third specific inductor conductor layer arranged between the first specific inductor conductor layer and the second specific inductor conductor layer in the stacking direction, The first overlap portion overlaps with the third specific inductor conductor layer when viewed from the stacking direction. The stacked electronic component according to claim 6, characterized in that.

8. The at least one second inductor conductor layer is a plurality of second inductor conductor layers, The plurality of second inductor conductor layers include a third specific inductor conductor layer located at the tip in one direction parallel to the stacking direction and a fourth specific inductor conductor layer located at the tip in the direction opposite to the one direction, The capacitor conductor layer is arranged between the third specific inductor conductor layer and the fourth specific inductor conductor layer in the stacking direction. The stacked electronic component according to claim 6, characterized in that.

9. The capacitor conductor layer further includes a non-overlap portion connected to the first overlap portion and overlapping with the first opening when viewed from the stacking direction. The stacked electronic component according to claim 1, characterized in that.

10. The area of the non-overlap portion is smaller than the area of the first overlap portion. The stacked electronic component according to claim 9, characterized in that.

11. The laminated electronic component according to claim 9, wherein the non-overlapping portion has an edge shaped along a curve of the at least one first inductor conductor layer.

12. The first inductor has a first end and a second end, The capacitor is connected between the first end and the second end of the first inductor in terms of circuit configuration, and the laminated electronic component according to any one of claims 1 to 11.

13. An inductor, A capacitor, A laminate for integrating the inductor and the capacitor, the laminate including a plurality of dielectric layers laminated, The inductor includes at least one inductor conductor layer wound around an axis extending in a direction parallel to the lamination direction of the plurality of dielectric layers, The at least one inductor conductor layer has a predetermined length and includes an extending portion with a smooth outer edge, The capacitor includes a capacitor conductor layer, The capacitor conductor layer extends toward an opening surrounded by the at least one inductor conductor layer from the outside of the at least one inductor conductor layer when viewed in the lamination direction, and includes a first overlapping portion overlapping the extending portion when viewed in the lamination direction, and the laminated electronic component characterized in that.

14. The laminated electronic component according to claim 13, wherein the extending portion includes a second overlapping portion that overlaps the first overlapping portion when viewed in the lamination direction and constitutes the capacitor together with the first overlapping portion.

15. The at least one inductor conductor layer is a plurality of inductor conductor layers, The plurality of inductor conductor layers include a first specific inductor conductor layer and a second specific inductor conductor layer arranged at a predetermined interval in the lamination direction, The laminated electronic component according to claim 13, wherein the capacitor conductor layer is arranged between the first specific inductor conductor layer and the second specific inductor conductor layer in the lamination direction.

16. The plurality of inductor conductor layers further include a third specific inductor conductor layer arranged between the first specific inductor conductor layer and the second specific inductor conductor layer in the lamination direction, The laminated electronic component according to claim 15, wherein the first overlapping portion overlaps the third specific inductor conductor layer when viewed from the lamination direction.

17. The laminated electronic component according to claim 13, wherein the capacitor conductor layer further includes a non-overlapping portion that is connected to the first overlapping portion and overlaps the opening when viewed from the lamination direction.

18. The laminated electronic component according to claim 17, wherein the area of the non-overlapping portion is smaller than the area of the first overlapping portion.

19. The laminated electronic component according to claim 17, wherein the non-overlapping portion has an edge shaped along the curve of the at least one inductor conductor layer.

20. The inductor has a first end and a second end. The laminated electronic component according to any one of claims 13 to 19, wherein the capacitor is connected between the first end and the second end of the inductor in terms of circuit configuration.

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