Information processing device, program and neutral network architecture manufacturing method

Abstract

To evaluate the performance of a neutral network architecture without performing learning.SOLUTION: An information processing device includes an index calculation unit for acquiring prediction performance index values showing results of prediction by using performance predictors for predicting the performance of a learned AI model to be obtained by executing learning to unlearned neural network architectures without going through a learning phase, an integration processing unit for integrating the prediction performance index values of each performance predictor obtained by using a plurality of performance predictors to calculate an integrated index value about the unlearned neural network architectures, and a selection processing unit for selecting one unlearned neural network architecture on the basis of the integrated index value calculated for each of the plurality of unlearned neural network architectures.SELECTED DRAWING: Figure 10

Description

Technical Field

[0001] The present technology relates to the technical field of an information processing apparatus, a program, and a method for manufacturing a neural network architecture for selecting a neural network architecture.

Background Art

[0002] A trained AI model may be subjected to performance evaluation to determine whether it exhibits a predetermined ability. However, if the trained AI model fails to achieve a predetermined performance, it is necessary to perform performance evaluation again after obtaining another trained AI model through learning. However, since training a trained AI model takes time, there has been a problem that efficient evaluation cannot be performed. In response to such a problem, Patent Document 1 below discloses a method for evaluating the performance of a neural network architecture before learning. For evaluating the performance of a neural network architecture, a neural network that executes a task of performance prediction, that is, an AI model, is used. That is, by using an AI model for performance prediction obtained through learning, performance evaluation is realized without performing learning of the neural network architecture.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in the method in Patent Document 1, learning for obtaining an AI model that executes a task of performance prediction cannot be reduced, and there is room for improvement.

[0005] This technology has been made in view of such problems, and aims to evaluate the performance of a neural network architecture without performing learning.

Means for Solving the Problems

[0006] The information processing apparatus according to this technology includes an index calculation unit that obtains a prediction performance index value indicating the result of the prediction using a performance predictor that predicts the performance of a learned AI model obtained by performing learning on a neural network architecture before learning without going through a learning phase, an integration processing unit that integrates the prediction performance index values for each of the performance predictors obtained using a plurality of the performance predictors to calculate an integrated index value for the neural network architecture before learning, and a selection processing unit that selects one of the neural network architectures before learning based on the integrated index values calculated for each of the plurality of neural network architectures before learning. That is, the prediction performance index value is a value obtained without going through a learning phase. And the integrated index value obtained based on the prediction performance index value also does not require a learning phase.

Brief Description of the Drawings

[0007]

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Mode for Carrying Out the Invention

[0008] Hereinafter, with reference to the accompanying drawings, embodiments of an information processing apparatus according to the present technology will be described in the following order. <1. Configuration of Information Processing System> <2. Functional Configuration of Information Processing Apparatus> <3. Processing Examples> <3-1. First Processing Example> <3-2. Second Processing Example> <3-3. Third Processing Example> <4. Summary> <5. The Present Technology>

[0009] <1. Configuration of Information Processing System> A configuration example of the information processing system 1 in the present embodiment is shown in FIG. 1. The information processing system 1 includes an information processing apparatus 2, a user terminal 3, and an AI (Artificial Intelligence) processing apparatus 4. The information processing apparatus 2, the user terminal 3, and the AI processing apparatus 4 can communicate with each other via a communication network 5.

[0010] The information processing device 2 is, for example, a server device that performs various processes in response to requests from users who use the user terminal 3.

[0011] The information processing device 2 performs processes related to the generation of an AI model in order to realize a task desired by the user. Specifically, the information processing device 2 searches for a neural network architecture suitable for the task and presents it to the user.

[0012] By training the neural network architecture presented by the information processing device 2, the user can obtain a high-performance AI model specialized for the user's target task.

[0013] The user terminal 3 is a terminal device used by the user, and is, for example, a smartphone, a tablet terminal, a PC (Personal Computer) terminal, or the like. The user can provide the information processing device 2 via the user terminal 3 with the type and specifications of the task to be executed by the AI model. In the information processing device 2, a search for a neural network architecture suitable for the task type and specifications of the AI model input via the AI processing device 4 is performed.

[0014] The AI processing device 4 is a device in which a neural network model obtained by training a neural network architecture is deployed, and is a device that performs a predetermined inference process by inputting input data into the deployed neural network model.

[0015] In the following description, the neural network model may be simply described as an "AI model". And the neural network model obtained by training is described as a "trained AI model". Also, the inference process using the AI model is described as "AI processing". That is, the AI processing device 4 refers to a device that performs AI processing.

[0016] The AI processing device 4 may be, for example, a camera device, an image sensor device arranged inside the camera device, or another arithmetic device. In the case where the AI processing device 4 is a camera device, for example, inference processing is performed by inputting RAW image data output from the light receiving unit of the image sensor to an AI model, and AI processing such as semantic segmentation for classifying a subject is realized.

[0017] A configuration example of the information processing device 2 is shown in FIG. 2. The information processing device 2 includes a CPU (Central Processing Unit) 71. The CPU 71 functions as an arithmetic processing unit that performs the various processes described above, and executes various processes according to a program stored in a ROM (Read Only Memory) 72 or a non-volatile memory unit 74 such as an EEP-ROM (Electrically Erasable Programmable Read-Only Memory) for example, or a program loaded from the storage unit 79 to a RAM (Random Access Memory) 73. The RAM 73 also appropriately stores data and the like necessary for the CPU 71 to execute various processes.

[0018] The CPU 71, ROM 72, RAM 73, and non-volatile memory unit 74 are interconnected via a bus 83. An input / output interface (I / F) 75 is also connected to this bus 83.

[0019] An input unit 76 composed of an operator and an operation device is connected to the input / output interface 75. For example, as the input unit 76, various operators and operation devices such as a keyboard, a mouse, keys, a dial, a touch panel, a touch pad, and a remote controller are assumed. An operation of the user is detected by the input unit 76, and a signal corresponding to the input operation is interpreted by the CPU 71.

[0020] In addition, a display unit 77 composed of an LCD or an organic EL panel, etc., and an audio output unit 78 composed of a speaker, etc. are connected to the input / output interface 75 either integrally or separately. The display unit 77 is a display unit that performs various displays, and is configured by, for example, a display device provided on the housing of a computer device, or a separate display device connected to the computer device.

[0021] The display unit 77 executes displays of images for various image processes, moving images to be processed, etc. on the display screen based on instructions from the CPU 71. Also, based on instructions from the CPU 71, the display unit 77 performs displays such as various operation menus, icons, messages, etc., that is, displays as a GUI (Graphical User Interface).

[0022] A storage unit 79 composed of a hard disk, a solid-state memory, etc., and a communication unit 80 composed of a modem, etc. may be connected to the input / output interface 75.

[0023] The communication unit 80 performs communication processing via a transmission path such as the Internet, and communication by wired / wireless communication with various devices, bus communication, etc.

[0024] A drive 81 is also connected to the input / output interface 75 as necessary, and a removable storage medium 82 such as a magnetic disk, an optical disk, a magneto-optical disk, or a semiconductor memory is appropriately mounted.

[0025] The drive 81 can read data files such as programs used for each process from the removable storage medium 82. The read data files are stored in the storage unit 79, or images and audio included in the data files are output by the display unit 77 and the audio output unit 78. Also, computer programs, etc. read from the removable storage medium 82 are installed in the storage unit 79 as necessary.

[0026] In this computer device, for example, software for the processing of the present embodiment can be installed via network communication by the communication unit 80 or a removable storage medium 82. Alternatively, the software may be stored in advance in the ROM 72, the storage unit 79, or the like. Also, an imaging image captured by the camera or a processing result obtained by subjecting the imaging image to AI processing may be received and stored in the removable storage medium 82 via the storage unit 79 or the drive 81.

[0027] By the CPU 71 performing a processing operation based on various programs, the information processing apparatus 2 including the arithmetic processing unit described above can be realized. Note that the information processing apparatus 2 is not limited to being configured by a single computer device as shown in FIG. 2, and a plurality of computer devices may be systemized and configured. The plurality of computer devices may be systemized by a LAN (Local Area Network) or the like, or may be arranged remotely by a VPN (Virtual Private Network) or the like using the Internet or the like. The plurality of computer devices may include computer devices as a server group (cloud) that can be used by a cloud computing service.

[0028] The configuration of the user terminal 3 is the same as that of the information processing apparatus 2 shown in FIG. 2.

[0029] A configuration example in the case where the AI processing apparatus 4 is provided as a camera apparatus is shown in FIG. 3.

[0030] The AI processing apparatus 4 includes an imaging optical system 31, an optical system drive unit 32, an image sensor IS, a control unit 33, a memory unit 34, and a communication unit 35. The image sensor IS, the control unit 33, the memory unit 34, and the communication unit 35 are connected via a bus 36 and can perform data communication with each other.

[0031] The imaging optical system 31 includes lenses such as a cover lens, a zoom lens, and a focus lens, and a diaphragm (iris) mechanism. The light (incident light) from the subject is guided by this imaging optical system 31 and focused on the light receiving surface of the image sensor IS.

[0032] The optical system driving unit 32 comprehensively shows the driving units of the zoom lens, focus lens, and diaphragm mechanism that the imaging optical system 31 has. Specifically, the optical system driving unit 32 has actuators for driving these zoom lens, focus lens, and diaphragm mechanism respectively, and a driving circuit for the actuators.

[0033] The control unit 33 is configured to include a microcomputer having, for example, a CPU, a ROM, and a RAM, and performs overall control of the AI processing device 4 as a camera device by executing various processes according to a program stored in the ROM or a program loaded into the RAM by the CPU.

[0034] Also, the control unit 33 gives driving instructions for the zoom lens, focus lens, diaphragm mechanism, etc. to the optical system driving unit 32. The optical system driving unit 32 executes the movement of the focus lens and zoom lens, the opening and closing of the diaphragm blades of the diaphragm mechanism, etc. according to these driving instructions.

[0035] Also, the control unit 33 controls the writing and reading of various data to and from the memory unit 34. The memory unit 34 is a non-volatile storage device such as an HDD (Hard Disk Drive) or a flash memory device, and is used as a storage destination (recording destination) for the image data output from the image sensor IS.

[0036] Furthermore, the control unit 33 performs various data communications with an external device via the communication unit 35. The communication unit 35 in this example is configured to be able to perform data communication at least with the information processing device 2 shown in FIG. 1.

[0037] The image sensor IS is configured as, for example, a CCD (Charge Coupled Device) type image sensor or a CMOS (Complementary Metal Oxide Semiconductor) type image sensor, etc.

[0038] The image sensor IS includes an imaging unit 41, an image signal processing unit 42, an in-sensor control unit 43, an AI image processing unit 44, a memory unit 45, and a communication I / F 46, and each can communicate with each other via a bus 47 for data communication.

[0039] The imaging unit 41 includes a pixel array unit in which pixels having photoelectric conversion elements such as photodiodes are two-dimensionally arranged, and a readout circuit that reads out the electrical signals obtained by photoelectric conversion from each pixel included in the pixel array unit, and can output the electrical signals as imaging image signals.

[0040] In the readout circuit, for the electrical signals obtained by photoelectric conversion, for example, CDS (Correlated Double Sampling) processing, AGC (Automatic Gain Control) processing, etc. are executed, and further A / D (Analog / Digital) conversion processing is performed.

[0041] The image signal processing unit 42 performs preprocessing, synchronization processing, YC generation processing, resolution conversion processing, codec processing, etc. on the imaging image signal as digital data after A / D conversion processing. In the preprocessing, clamp processing for clamping the black levels of R, G, and B to a predetermined level and correction processing between the color channels of R, G, and B are performed on the imaging image signal. In the synchronization processing, color separation processing is performed so that the image data for each pixel has all color components of R, G, and B. For example, in the case of an imaging device using a Bayer array color filter, demosaicing processing is performed as the color separation processing. In the YC generation processing, a luminance (Y) signal and a color (C) signal are generated (separated) from the R, G, and B image data. In the resolution conversion processing, resolution conversion processing is executed on the image data subjected to various signal processes. In codec processing, for the image data subjected to the above various processes, for example, encoding processes for recording and communication, and file generation are performed. In codec processing, as the file format of a video, for example, file generation can be performed in formats such as MPEG-2 (MPEG: Moving Picture Experts Group) and H.264. Also, as a still image file, file generation in formats such as JPEG (Joint Photographic Experts Group), TIFF (Tagged Image File Format), and GIF (Graphics Interchange Format) is also conceivable. Note that when the image sensor IS is a distance measurement sensor, the image signal processing unit 42 calculates distance information about the subject based on, for example, two signals output from the image sensor IS as iToF (indirect Time of Flight) and outputs a distance image.

[0042] The in-sensor control unit 43 gives instructions to the imaging unit 41 to perform execution control of the imaging operation. Similarly, execution control of processing is also performed on the image signal processing unit 42.

[0043] The AI image processing unit 44 performs image recognition processing as AI image processing on the captured image. Note that AI image processing refers to AI processing on image data.

[0044] The image recognition function using AI can be realized using a programmable arithmetic processing device such as a CPU, FPGA (Field Programmable Gate Array), or DSP (Digital Signal Processor).

[0045] The image recognition functions that can be realized by the AI image processing unit 44 differ depending on the type of AI model deployed in the image sensor IS. Examples of the types of image recognition functions include the following. · Class identification · Semantic segmentation · Person detection · Vehicle detection · Target tracking · OCR (Optical Character Recognition)

[0046] These functional types of image recognition correspond to the task types described above. Among the above functional types, class identification is a function for identifying the class of a target. The "class" mentioned here is information representing the category of an object, and is used to distinguish, for example, "person", "automobile", "airplane", "ship", "truck", "bird", "cat", "dog", "deer", "frog", "horse", etc. Target tracking is a function for tracking a subject regarded as a target, and can be paraphrased as a function for obtaining the history information of the position of the subject.

[0047] The memory unit 45 is used as a storage destination for various data such as captured image data obtained by the image signal processing unit 42. In this example, the memory unit 45 can also be used for temporarily storing data used by the AI image processing unit 44 in the process of AI image processing.

[0048] In addition, information on AI applications and AI models used by the AI image processing unit 44 is stored in the memory unit 45. Note that the information on AI applications and AI models may be deployed in the memory unit 45 as a container or the like using container technology, or may be deployed using microservice technology. When the capacity of the memory unit 45 is small, the information on AI applications and AI models is deployed in a memory outside the image sensor IS, such as the memory unit 34, as a container or the like using container technology, and then only the AI model is stored in the memory unit 45 inside the image sensor IS via the communication I / F 46 described below.

[0049] The communication I / F 46 is an interface for communicating with the control unit 33, memory unit 34, etc. outside the image sensor IS. The communication I / F 46 communicates to obtain from the outside a program executed by the image signal processing unit 42, an AI application or AI model used by the AI image processing unit 44, etc., and stores them in the memory unit 45 provided in the image sensor IS. As a result, the AI model is stored in a part of the memory unit 45 provided in the image sensor IS and can be used by the AI image processing unit 44.

[0050] The AI image processing unit 44 performs predetermined image recognition processing using the AI application and AI model thus obtained to recognize a subject according to the purpose.

[0051] The recognition result information of the AI image processing is output to the outside of the image sensor IS via the communication I / F 46.

[0052] That is, from the communication I / F 46 of the image sensor IS, not only the image data output from the image signal processing unit 42 but also the recognition result information of the AI image processing is output. Note that it is also possible to output only either the image data or the recognition result information from the communication I / F 46 of the image sensor IS.

[0053] <2. Functional Configuration of Information Processing Apparatus>

[0054] The CPU 71 of the information processing apparatus 2 realizes a series of functions shown in FIG. 4 by executing a predetermined program, for example.

[0055] The CPU 71 of the information processing apparatus 2 functions as a condition acquisition unit F1, a modification processing unit F2, an index calculation unit F3, an integration processing unit F4, a selection processing unit F5, and a presentation processing unit F6.

[0056] The condition acquisition unit F1 performs a process of acquiring the task type and specifications of the AI model input via the user terminal 3. Specifically, the condition acquisition unit F1 executes a process of causing the user terminal 3 to display a predetermined input form 10, and acquires the conditions obtained via the input form 10.

[0057] Here, FIG. 5 shows an example of the input form 10 presented to the user on the user terminal 3 for inputting the task type and specifications of the AI model.

[0058] The input form 10 includes a title 11, a plurality of input fields 12, a cancel button 13, a search start button 14, and a close button 15.

[0059] A text sentence for notifying the outline of the input form 10 is displayed in the title 11. In the example shown in FIG. 5, a text sentence "Condition Input Form" is displayed as the title 11.

[0060] The input field 12 is a field for inputting information for determining the specifications of the neural network architecture presented by the information processing apparatus 2, and various modes are conceivable.

[0061] In the title 11 shown in FIG. 5, an input field 12A for inputting the upper limit number of parameters of the neural network architecture and an input field 12B for inputting the upper limit number of product-sum operations executed when performing inference processing using the neural network architecture are provided.

[0062] By inputting predetermined information into the input field 12A and the input field 12B, the AI model generated from the neural network architecture selected and presented by the information processing apparatus 2 can be made an appropriate size.

[0063] Note that other aspects of the input field 12 are also conceivable. For example, in the example shown in FIG. 6, an input field 12C for inputting the memory capacity of the device in which the learned AI model is deployed and an input field 12D for inputting information on the computing power of the device are provided.

[0064] The information about the computing power may be information on FLOPS (Floating point number Operations Per Second), or may be information such as the operating frequency or the number of cores of the arithmetic processing unit.

[0065] The cancel button 13 is an operator that is operated when canceling the condition input and not executing the search for the neural network architecture.

[0066] The search start button 14 is an operator that is operated when the condition input is completed and the search for the neural network architecture is executed. When the search start button 14 is operated, the information processing device 2 executes the search for the neural network architecture, and the search result is presented on the screen of the user terminal 3 or the like.

[0067] The close button 15 is an operator that is operated when closing the input form 10. When the close button 15 is operated, the same processing as when the cancel button 13 is operated is executed.

[0068] Note that when acquiring the type information of the task to be solved using the finally obtained learned AI model, as shown in FIG. 7, an input field 12E for inputting (selecting) the task type may be provided in the input form 10.

[0069] The modification processing unit F2 selects one neural network architecture and obtains a new neural network architecture by causing a modification (Mutation) in a part of the neural network architecture. The modification of the neural network architecture by the modification processing unit F2 is realized, for example, by causing mutations in a very small part of the structure using an evolutionary algorithm.

[0070] The neural network architecture includes a feature extractor that extracts features of input data and a subsequent classifier. The modification processing unit F2 modifies a part of the feature extractor in the modification process (see FIG. 8).

[0071] For example, the modification processing unit F2 selects one convolutional layer that constitutes the neural network architecture to be modified and changes the size of the kernel used in that layer.

[0072] Alternatively, the modification processing unit F2 selects one convolutional layer that constitutes the neural network architecture to be modified and changes the type of kernel used in that layer.

[0073] Also, the modification processing unit F2 may select one convolutional layer that constitutes the neural network architecture to be modified and change the number of channels (width) or the number of repetitions (depth).

[0074] Among other things, the modification processing unit F2 may select one layer that constitutes the neural network architecture to be modified and change the activation function used in that layer, or select one or more layers and newly provide branches such as adding residual connections, Self-attention Branch, and various skip connections.

[0075] Furthermore, the modification processing unit F2 may select one convolutional layer that constitutes the neural network architecture to be modified and change the type of layer.

[0076] By repeatedly performing such modification processing, the modification processing unit F2 obtains a neural network architecture in which a plurality of modifications have been made to the initially selected base neural network architecture (hereinafter referred to as "base architecture Ab").

[0077] The modification processing unit F2 obtains a plurality of types of neural network architectures by performing a plurality of types of modifications on the base architecture Ab. The neural network architecture subjected to the modification is referred to as "modified architecture Ac".

[0078] The modification processing unit F2 selects one of the modified architectures Ac and further modifies a part thereof. By repeating such selection and modification, not only the modified architecture Ac with a small modification to the base architecture Ab but also the modified architecture Ac with a large modification to the base architecture Ab can be obtained.

[0079] Note that when selecting the base architecture Ab, the modification processing unit F2 takes into account the conditions acquired by the condition acquisition unit F1. Specifically, the modification processing unit F2 selects the number of layers, the number of nodes, etc. of the base architecture Ab in consideration of the number of parameters and the number of multiply-accumulate operations of the modified architecture Ac so as to satisfy the conditions, or in consideration of the memory capacity of the device on which the learned AI model is deployed and the computing power of the arithmetic processing unit.

[0080] For example, the modification processing unit F2 selects so that the number of parameters and the number of multiply-accumulate operations of the base architecture Ab are less than 80% or less than 70% of the respective values allowed for the neural network architecture. Thereby, it is possible to make the number of parameters and the number of multiply-accumulate operations of the modified architecture Ac after the modification processing satisfy the conditions.

[0081] Also, the modification processing unit F2 may select the base architecture Ab based on the information on the type of user task acquired by the condition acquisition unit F1. For example, the modification processing unit F2 may vary the base architecture Ab selected when the task type is object recognition, object detection, or semantic segmentation, the base architecture Ab selected when the purpose is speech recognition, and the base architecture Ab selected when the purpose is to select the optimal procedure in a game.

[0082] The modified architecture Ac generated by the base architecture Ab or the modification processing unit F2 is regarded as a candidate for the AI model for executing the task that is the user's purpose. Here, the base architecture Ab and the modified architecture Ac are described as "candidate architectures Ap".

[0083] When the number of candidate architectures Ap belonging to the candidate architecture group exceeds a predetermined number, the modification processing unit F2 may perform a process of excluding some candidate architectures Ap from the candidate architecture group. The exclusion process of the candidate architecture Ap is performed, for example, based on the integration index value Vf described later.

[0084] The index calculation unit F3 calculates a predicted performance index value Vi, which is an index value for predicting the performance of the candidate architecture Ap. A performance predictor Pr is used to calculate the predicted performance index value Vi.

[0085] Specifically, the index calculation unit F3 uses a plurality of types of performance predictors Pr to calculate the predicted performance index value Vi of the candidate architecture Ap. As the performance predictor Pr, zero-shot NAS (Neural Architecture Search) such as MAE-NAS, NASWOT, or Zen-NAS is used.

[0086] Zero-shot NAS is a performance predictor Pr that can estimate the performance of a pre-trained AI model obtained from a neural network architecture without learning. By using zero-shot NAS to estimate the performance of neural network architectures, it becomes possible to estimate the performance of multiple neural network architectures in a short time, and the efficiency related to the determination of neural network architectures can be significantly improved.

[0087] The integration processing unit F4 calculates an integrated index value Vf by integrating using each prediction performance index value Vi calculated for each zero-shot NAS.

[0088] Specifically, the integration processing unit F4 calculates a standardized index value Vs for each zero-shot NAS by standardizing the prediction performance index value Vi for each zero-shot NAS used for calculating the integrated index value Vf. Further, the integration processing unit F4 calculates the integrated index value Vf using the standardized index value Vs for each zero-shot NAS.

[0089] The integration processing unit F4 may perform weighting according to the characteristics of each zero-shot NAS when calculating the integrated index value Vf. For example, when the task type is object recognition, the integration processing unit F4 may calculate the integrated index value Vf by increasing the weight of the prediction performance index value Vi of the zero-shot NAS that can accurately predict the performance in the field of object recognition for the pre-trained AI model obtained from the candidate architecture Ap.

[0090] The selection processing unit F5 selects one candidate architecture Ap based on the integrated index value Vf for each candidate architecture Ap calculated by the integration processing unit F4. The pre-trained AI model obtained by subjecting the selected candidate architecture Ap to predetermined learning is likely to exhibit high performance in the user's target task.

[0091] The prompt processing unit F6 executes a process of causing the display unit 77 of the user terminal 3 to display predetermined information in order to prompt the user with the candidate architecture Ap selected by the selection processing unit F5.

[0092] Due to the prompt processing of the prompt processing unit F6, a prompt screen 20 as shown in FIG. 9, for example, is displayed on the display unit 77 of the user terminal 3.

[0093] The prompt screen 20 is provided with a title 21, an image display column 22, a parameter column 23, a score column 24, and a histogram column 25.

[0094] The title 21 displays a text sentence for notifying the outline of the information displayed on the prompt screen 20. In the example shown in FIG. 9, a sentence indicating that the search for the neural network architecture has ended and is being prompted is displayed.

[0095] The image display column 22 displays an image showing the structure of the candidate architecture Ap selected by the selection processing unit F5. Instead of showing it as an image as in FIG. 9, the number of layers and the number of nodes may be shown numerically.

[0096] The parameter column 23 displays the number of parameters and the number of multiply-accumulate operations of the candidate architecture Ap selected by the selection processing unit F5. By checking the numerical values presented in the parameter column 23, the user can grasp the size and the amount of computation of the candidate architecture Ap.

[0097] The score column 24 displays the predicted performance index value Vi for each performance predictor Pr of the candidate architecture Ap selected by the selection processing unit F5, or the standardized index value Vs.

[0098] The histogram column 25 displays a histogram indicating the position of the candidate architecture Ap selected by the selection processing unit F5 among the performance predictors Pr for which the integrated index value Vf has been calculated. By checking the histogram column 25, the user can grasp the expected value of the performance of the learned AI model obtained based on the presented candidate architecture Ap. In addition, by presenting the user with basis information such as the score column 24 and the histogram column 25, the persuasive power that a high-performance learned AI model can be obtained based on the selected and presented candidate architecture Ap can be enhanced.

[0099] Note that in FIG. 9, an example is shown in which one candidate architecture Ap selected by the information processing apparatus 2 is presented. However, this is not the only case, and for each of the plurality of candidate architectures Ap selected by the information processing apparatus 2, a presentation screen 20 as shown in FIG. 9 may be generated and presented to the user. That is, the candidate architecture Ap presented to the user is not necessarily one. For example, three or five candidate architectures Ap may be presented to the user in the order in which acquisition of a high-performance learned AI model is expected.

[0100] <3. Processing example> The processing executed by the CPU 71 of the information processing apparatus 2 to realize each of the functions described above will be described.

[0101] <3-1. First processing example> The first processing example is shown in FIG. 10. The CPU 71 of the information processing apparatus 2 first determines, in step S101, the performance predictor Pr to be used. Each performance predictor Pr has its own characteristics and different architectures for which performance can be predicted. For example, for a certain performance predictor Pr, it is considered impossible to predict the performance of a neural network architecture that includes branches across layers.

[0102] Depending on the performance predictor Pr selected in step S101, the content of the modification process by the modification processing unit F2 is limited.

[0103] In step S102, the CPU 71 generates or selects the base architecture Ab. In this process, the CPU 71 selects the base architecture Ab so as to satisfy the conditions acquired by the condition acquisition unit F1. As described above, in this process, the base architecture Ab may be selected according to the user's target task.

[0104] In step S103, the CPU 71 updates the candidate architecture group. When the process of step S103 is executed for the first time, a process of adding the base architecture Ab to the candidate architecture Ap belonging to the candidate architecture group is performed.

[0105] Subsequently, the CPU 71 proceeds to step S104 and determines whether or not the process of adding the candidate architecture Ap to the candidate architecture group has been executed a predetermined number of times. That is, the process of step S104 is a process of determining whether or not a sufficient number of modified architectures Ac have been generated for the base architecture Ab.

[0106] By generating a sufficient number of modified architectures Ac, it becomes possible to present a neural network architecture for generating a higher-precision AI model to the user.

[0107] If it is determined that the predetermined number of repetitions has not been executed (step S104: No determination), the CPU 71 proceeds to step S105 and selects one candidate architecture Ap to be modified from the candidate architectures Ap belonging to the candidate architecture group.

[0108] In step S106, the CPU 71 performs a modification process on the selected candidate architecture Ap to obtain a modified architecture Ac. In the modification process of step S106, the CPU 71 performs modifications on the candidate architecture Ap such that performance prediction by the performance predictor Pr is not made impossible.

[0109] For example, when performing performance evaluation using MAE-NAS, NASWOT, and Zen-NAS as the performance predictors Pr, modification processing is performed so that the neural network architecture has a series structure and each layer of the intermediate layer is composed of a convolutional layer and ReLU (Rectified Linear Unit) as the activation function.

[0110] Note that the CPU 71 may generate a plurality of modified architectures Ac by performing different modifications on one candidate architecture Ap belonging to the candidate architecture group in step S106.

[0111] For example, as shown in FIG. 11, when the processes of step S105 and step S106 are executed for the first time, the CPU 71 selects the base architecture Ab, which is the only candidate architecture Ap belonging to the candidate architecture group, and generates modified architectures Ac1, Ac2, and Ac3 by performing different modifications respectively.

[0112] When the processes of step S105 and step S106 are executed for the second time, the CPU 71 selects the modified architecture Ac2 as one candidate architecture Ap from the candidate architectures Ap belonging to the candidate architecture group, and generates modified architectures Ac21, Ac22, and Ac23 by performing different modifications respectively.

[0113] When the processes of step S105 and step S106 are executed for the third time, the CPU 71 selects the modified architecture Ac21 as one candidate architecture Ap from the candidate architectures Ap belonging to the candidate architecture group, and generates modified architectures Ac211, Ac212, and Ac213 by performing different modifications respectively.

[0114] In this way, by repeatedly selecting and modifying the modified architecture Ac, a modified architecture Ac with a structure significantly different from the base architecture can be generated.

[0115] In the selection process of step S105, a modified architecture Ac with high performance predicted based on the integrated index value Vf may be selected. Also, in the example of FIG. 11, one modified architecture Ac was selected from the last generated modified architectures Ac. However, this is not the only case. In the selection process of step S105, the CPU 71 may select one from the candidate architectures Ap belonging to the candidate architecture group without considering the generated timing. That is, when the process of step S105 is performed again after the modified architecture Ac2 is selected, the modified architecture Ac1 or the modified architecture Ac3 may be selected.

[0116] In step S107, the CPU 71 performs a process of calculating the integrated index value Vf for the newly generated modified architecture Ac. When a plurality of modified architectures Ac are generated in step S106, the CPU 71 performs the integrated index value calculation process of step S107 for each generated modified architecture Ac.

[0117] An example of the integrated index value calculation process is shown in FIG. 12.

[0118] In step S201, the CPU 71 first selects one unselected performance predictor Pr to be used.

[0119] In step S202, the CPU 71 calculates the predicted performance index value Vi for the candidate architecture Ap selected in the previous step S105 using the performance predictor Pr selected in step S201.

[0120] In step S203, the CPU 71 determines whether the predicted performance index value Vi for the target candidate architecture Ap has been calculated using all of the performance predictors Pr to be used.

[0121] When it is determined that there is a performance predictor Pr for which the predicted performance index value Vi has not been calculated (step S203: No determination), the CPU 71 returns to step S201, selects one unselected performance predictor Pr, and executes the calculation process of step S202.

[0122] On the other hand, when it is determined that the predicted performance index value Vi has been calculated using all the performance predictors Pr (step S203: Yes determination), the CPU 71 proceeds to step S204 and performs a normalization process. This process is a process of calculating a normalized index value Vs in order to unify the range and variance that can be taken by the predicted performance index value Vi for each performance predictor Pr. As a result, the normalized index values Vs for each performance predictor Pr can be treated equally.

[0123] In step S205, the CPU 71 performs a weighting process. The weighting process is a process of weighting the normalized index value Vs for the performance predictor Pr with high prediction performance accuracy according to the type of task of the user's purpose. Note that the weighting process in step S205 is not essential.

[0124] In step S206, the CPU 71 calculates an integrated index value Vf using the normalized index value Vs after the weighting process. As a result, one index value called the integrated index value Vf is given to the candidate architecture Ap selected in the previous step S105. The integrated index value Vf is used when selecting the candidate architecture Ap to be presented to the user from the candidate architecture group.

[0125] After finishing the process of step S206, the CPU 71 proceeds to step S108 of FIG. 10. In step S108, the CPU 71 adds the new modified architecture Ac generated in step S106 to the candidate architecture group as the candidate architecture Ap. As a result, one or more of these candidate architectures Ap are added to the candidate architecture group.

[0126] Note that the candidate architecture Ap to be added to the candidate architecture group is preferably limited to the candidate architecture Ap that matches the conditions acquired by the condition acquisition unit F1. For example, as a result of repeatedly performing the modification process in step S106, for the modified architecture Ac in which the structure of the neural network architecture has become complex and the number of product-sum operations executed during inference has become larger than a predetermined value, it is desirable that it be discarded without being added to the candidate architecture group as the candidate architecture Ap. The same applies when the number of parameters exceeds a predetermined number due to modification.

[0127] In step S109, the CPU 71 determines whether the candidate architecture Ap belonging to the candidate architecture group is equal to or less than a predetermined number. This process is to save the used memory capacity by excluding the candidate architecture Ap that is less likely to be presented to the user.

[0128] If it is determined that the candidate architecture Ap belonging to the candidate architecture group is equal to or less than a predetermined number (step S109: Yes determination), the CPU 71 returns to step S104 and determines whether the process of adding (or modifying) the candidate architecture Ap to the candidate architecture group has been repeated a predetermined number of times.

[0129] On the other hand, if it is determined that the candidate architecture Ap belonging to the candidate architecture group is more than a predetermined number (step S109: No determination), the CPU 71 returns to step S103 and updates the candidate architecture group. In step S103, a process of excluding the candidate architecture Ap exceeding the predetermined number from the candidate architecture group is executed.

[0130] If it is determined that the process of adding the candidate architecture Ap to the candidate architecture group has been executed a predetermined number of times in step S104 (step S104: Yes determination), the CPU 71 proceeds to step S110 and selects one or several candidate architectures Ap to be presented.

[0131] The process of step S110 is performed by comparing the integration index value Vf for each candidate architecture Ap. For example, one or several candidate architectures Ap are selected in descending order of the integration index value Vf.

[0132] In step S111, the CPU 71 performs a process of presenting the candidate architecture Ap selected in step S110 to the user. This process is realized by the CPU 71 of the information processing apparatus 2 causing the user terminal 3 to execute a display process.

[0133] <3-2. Second Processing Example> The first processing example was described as an example of not making modifications that would make it impossible to perform performance prediction with the performance predictor Pr. The second processing example is an example in which no restrictions are placed on the modification of the neural network architecture, and the integration index value Vf is calculated using only the performance predictor Pr for which performance prediction of the modified architecture Ac after modification is possible.

[0134] A specific processing example is shown in FIG. 13. For processes similar to those shown in FIG. 10, the same step numbers are assigned and the description is omitted as appropriate.

[0135] In step S121, the CPU 71 of the information processing apparatus 2 determines the type of modification to be used for the modification process of the neural network architecture. This process determines whether to permit a modification process of newly providing a branch that spans layers.

[0136] Subsequently, in step S101, the CPU 71 determines a performance predictor Pr that can perform performance prediction for the modified architecture Ac obtained after modification. The performance predictor Pr determined here corresponds to the type of modification determined in step S121.

[0137] After generating or selecting the base architecture Ab in step S102, the CPU 71 repeatedly executes each process from step S103 to step S109. Then, after executing the modification process a predetermined number of times (step S104: Yes determination), the process proceeds to step S110, and the CPU 71 selects the candidate architecture Ap to be presented.

[0138] In step S111, the CPU 71 performs a process of presenting the candidate architecture Ap selected in step S110 to the user.

[0139] In this way, in the second processing example, by not restricting the type of modification, a neural network architecture having a more complex structure can be included as the candidate architecture Ap. Therefore, the possibility of presenting a high-performance neural network architecture to the user can be increased.

[0140] Also, a neural network architecture can be considered separately into a backbone and a head. And in a neural network architecture with a complex structure, a neck may be provided between the backbone and the head.

[0141] The backbone in a neural network architecture refers to the layers from the beginning to the middle of the network and includes layers that extract features in the input data. Also, the head in a neural network architecture refers to the layers at the end of the network and may include, for example, a fully connected layer and a softmax function. Furthermore, the neck in a neural network architecture is a layer having a function of condensing and extracting features more refined, and for example, FPN (Feature Pyramid Networks) etc. correspond to it.

[0142] In the process of step S101 in FIG. 13, by selecting a performance predictor Pr capable of estimating the performance of the entire neural network architecture including not only the backbone of the neural network architecture but also the layers corresponding to the head and the layers corresponding to the neck, it becomes possible to evaluate the entire neural network architecture.

[0143] As a result, it becomes possible to present a user with a more high-performance neural network architecture.

[0144] <3-3. Third Processing Example> The third processing example is an example in which the types of modifications are not limited and the performance predictor Pr used for performance evaluation is not determined in advance. An example is shown in FIG. 14. For the processes similar to those shown in FIG. 10, the same step numbers are assigned and the description is omitted as appropriate.

[0145] The CPU 71 of the information processing apparatus 2 generates or selects the base architecture Ab in step S102.

[0146] The CPU 71 repeats each process from step S104 to step S109 after adding the base architecture Ab to the candidate architecture group in step S103.

[0147] At this time, in calculating the integrated index value Vf in step S107, the CPU 71 calculates the respective prediction performance index values Vi using all the performance predictors Pr that can evaluate the modified architecture Ac to be evaluated. That is, the performance predictor Pr used for each modified architecture Ac is different.

[0148] The integrated index value Vf calculated in step S107 is provisional because the performance predictors Pr used for each modified architecture Ac to be evaluated are not unified.

[0149] The CPU 71 adds the candidate architecture Ap to the candidate architecture group by repeating the processes from step S104 to step S109. Then, when the number of candidate architectures Ap belonging to the candidate architecture group exceeds a predetermined number, the CPU 71 appropriately executes the process of step S103 to sort out the candidate architectures Ap based on the temporarily calculated integrated index value Vf.

[0150] When it is determined that a predetermined number of repetitions have been performed (step S104: Yes determination), the CPU 71 proceeds to step S122 and identifies the performance predictor Pr capable of evaluating all the candidate architectures Ap belonging to the candidate architecture group.

[0151] Subsequently, in step S123, the CPU 71 calculates the integrated index value Vf for each candidate architecture Ap again using those performance predictors Pr. Since the integrated index value Vf calculated here is calculated using the same performance predictor Pr for each candidate architecture Ap, accurate comparison is possible.

[0152] In step S110, the CPU 71 selects one candidate architecture Ap based on the newly calculated integrated index value Vf in step S123 and presents it to the user in step S111.

[0153] <4. Summary> As described in each of the above examples, the information processing apparatus 2 includes an index calculation unit F3 that obtains a prediction performance index value Vi indicating a prediction result using a performance predictor Pr that predicts, without going through a learning phase, the performance of a learned AI model obtained by performing learning on a neural network architecture before learning; an integration processing unit F4 that integrates the prediction performance index values Vi for each performance predictor Pr obtained using a plurality of performance predictors Pr to calculate an integrated index value Vf for the neural network architecture before learning; and a selection processing unit F5 that selects one neural network architecture before learning based on the integrated index values Vf calculated for each of the plurality of neural network architectures before learning. That is, the prediction performance index value Vi is a value obtained without going through a learning phase. Also, the integrated index value Vf obtained based on the prediction performance index value Vi does not require a learning phase. Therefore, the time required to select a neural network architecture that is a candidate for generating a high-performance learned AI model can be significantly shortened compared to the case of performing learning for each neural network architecture. Therefore, it becomes possible to easily select a neural network architecture for generating a learned AI model according to the user's purpose, and it becomes easy to generate an appropriate learned AI model according to the situation. Also, since the performance of the learned AI model is predicted using a plurality of performance predictors Pr to calculate a plurality of prediction performance index values Vi and these are integrated to calculate an integrated index value Vf, it becomes possible to improve the accuracy of the integrated index value Vf, and it becomes possible to select a neural network architecture in which a higher-performance learned AI model is generated. Furthermore, since inference processing using an AI model is not required when selecting one neural network architecture from a plurality of neural network architectures, it becomes possible to reduce the amount of computation until the neural network architecture is selected.

[0154] As described with reference to FIGS. 10 and 11 and the like, in the information processing apparatus 2, a modification process unit F2 may be provided that performs a modification process of modifying a part of the base architecture Ab using the neural network architecture before learning as the base architecture Ab to generate the neural network architecture before learning as the modified architecture Ac. And the modified architecture Ac may be at least a part of a plurality of neural network architectures before learning. Thereby, it becomes possible to easily prepare a neural network architecture that is a candidate for selection by the selection processing unit F5.

[0155] As described with reference to FIG. 4 and the like, in the information processing apparatus 2, the modification process may be a process of applying an evolutionary algorithm to the base architecture Ab. By using the evolutionary algorithm, the modified architecture Ac can be suitably generated. Note that the modification of the base architecture Ab by the evolutionary algorithm refers to, for example, a change in the type of layer constituting the neural network, a change in the number of channels (width), a change in the type or size or stride of the kernel used in the convolution operation, and further, the number of repetitions (depth) of each layer. In addition, as a modification of the base architecture Ab, a change such as newly providing a branch like a Residual path or a change in the activation function to be used may be included.

[0156] As described with reference to FIG. 4 and the like, in the information processing apparatus 2, the modification process may be a process of causing a mutation in a part of the base architecture Ab. Thereby, the integrated index value Vf is calculated for many neural network architectures derived from the base architecture Ab by only determining the base architecture Ab first. Thereby, it is possible to select a high-performance neural network architecture from many neural network architectures without spending so much manual labor cost.

[0157] As described with reference to FIGS. 10 and 11 and the like, the modification processing unit F2 in the information processing apparatus 2 may generate a modified architecture Ac in which further modification is performed on the base architecture Ab by performing modification processing on the modified architecture Ac. As a result, the modified architecture Ac may include a neural network architecture in which a major modification has been made to the base architecture Ab. Therefore, it is possible to improve the possibility that a high-performance neural network architecture is selected and presented.

[0158] As described with reference to FIGS. 10 and 11 and the like, the modification processing unit F2 in the information processing apparatus 2 may generate a plurality of modified architectures Ac by repeating the modification processing a predetermined number of times. As a result, it is possible to generate, as the modified architecture Ac, a neural network architecture in which the base architecture Ab has been modified a predetermined number of times. Therefore, it is possible to increase the possibility that a high-performance neural network architecture is generated and selected.

[0159] As described with reference to FIG. 10 and the like, when the number of neural network architectures belonging to the candidate architecture group including the base architecture Ab and the modified architecture Ac in the selection processing unit F5 in the information processing apparatus 2 exceeds a predetermined number, the selection processing unit F5 may select a predetermined number of neural network architectures from the candidate architecture group using the integrated index value Vf. As a result, the candidate architecture group can be reduced, and reduction of the memory usage amount of the information processing apparatus 2 and the like can be achieved. In addition, when presenting the neural network architectures finally remaining in the candidate architecture group to the user, it is possible to reduce the number of neural network architectures presented to the user, and the annoyance associated with the user's selection operation can be reduced.

[0160] As described with reference to FIG. 10 and the like, in the information processing apparatus 2, the modified architecture Ac may be capable of performance prediction by a performance predictor Pr used for performance prediction of the base architecture Ab. That is, the modification applied to the base architecture Ab is limited to a modification within a range that allows performance prediction by the performance predictor Pr used for performance prediction of the base architecture Ab. Thereby, it becomes possible to evaluate the base architecture Ab and the modified architecture Ac generated as a derivative thereof using the same performance predictor Pr, and it becomes possible to perform a proper evaluation of each neural network architecture.

[0161] As described with reference to FIG. 11 and the like, the integration processing unit F4 in the information processing apparatus 2 may calculate a standardized post-indicator value Vs by standardizing the predicted performance indicator value Vi corresponding to the performance predictor Pr, and calculate an integrated indicator value Vf using a plurality of standardized post-indicator values Vs. Thereby, it becomes possible to equally handle different ranges of predicted performance indicator values Vi calculated for each performance predictor Pr, and an appropriate integrated indicator value Vf can be calculated. Therefore, the possibility of proposing a neural network architecture with high performance to the user can be increased.

[0162] As described with reference to FIG. 11 and the like, the integration processing unit F4 in the information processing apparatus 2 may perform standardization so that the average value and the variance value of the standardized post-indicator value Vs match for each performance predictor Pr. Thereby, a standardized post-indicator value Vs that has been appropriately standardized can be obtained.

[0163] As described with reference to FIG. 11 and the like, the integration processing unit F4 in the information processing apparatus 2 may perform weighting corresponding to the performance predictor Pr on the standardized post-indicator value Vs and calculate the integrated indicator value Vf. For example, the importance may vary for each performance predictor Pr. In such a case, by weighting the standardized index value Vs for each prediction performance index value Vi calculated for each performance predictor Pr, the integrated index value Vf can be calculated so that the influence of the prediction result of the important performance predictor Pr becomes higher. Therefore, the possibility of proposing a neural network architecture suitable for the user can be increased.

[0164] As described with reference to FIG. 11 and the like, the integration processing unit F4 in the information processing apparatus 2 may perform weighting using the level of prediction performance of the performance predictor Pr. For example, there are performance predictors Pr that can predict the performance of an AI model generated using a neural network architecture with high accuracy, and there are also performance predictors Pr that cannot make highly accurate predictions. And the prediction accuracy of the performance predictor Pr also varies according to the type of task of the AI model. According to this configuration, for example, according to the type of task of the AI model, the weight of the standardized index value Vs for the performance predictor Pr with high prediction accuracy can be increased, and the weight of the standardized index value Vs for the performance predictor Pr with low prediction accuracy can be decreased. This makes it possible to increase the correlation between the integrated index value Vf and the predicted performance, and to increase the possibility of proposing a neural network architecture with high performance to the user.

[0165] As described with reference to FIG. 13 and the like, the index calculation unit F3 in the information processing apparatus 2 may obtain the prediction performance index value Vi using the performance predictor Pr that can predict the performance of both the base architecture Ab and the modified architecture Ac obtained by modifying the base architecture Ab. This eliminates the need to impose restrictions on the modification mode when generating the modified architecture Ac from the base architecture Ab. For example, even if the entire neural network architecture including the backbone, neck, and head is adopted as the base architecture Ab and the modified architecture Ac, by adopting a performance predictor Pr capable of predicting the performance of a neural network architecture including all of the backbone, neck, and head, it becomes possible to appropriately evaluate the neural network architecture. Therefore, it becomes possible to calculate an integrated index value Vf based on the evaluation of the entire AI model, and it is possible to increase the possibility of presenting a more appropriate neural network architecture as the neural network architecture for realizing the task desired by the user.

[0166] As described with reference to FIGS. 4 and 5, etc., the information processing apparatus 2 includes a condition acquisition unit F1 that acquires the conditions of the number of parameters and the number of multiply-accumulate operations allowed for the learned AI model, and the selection processing unit F5 may select a neural network architecture before learning based on the conditions acquired by the condition acquisition unit F1. Thereby, when a learned AI model is deployed and used in a certain device (AI processing device 4), the neural network architecture selected by the selection processing unit F5 and finally presented to the user is such that the AI model obtained after learning satisfies the conditions. Therefore, it is possible to avoid a situation where the generated learned AI model does not satisfy the specifications, and it is possible to eliminate the need for re-searching the neural network architecture, etc. Note that the condition acquisition unit F1 may make the generated learned AI model satisfy the specifications by acquiring the memory size and arithmetic processing ability (e.g., FLOPS) of the device in which deployment is planned instead of the number of parameters and the number of multiply-accumulate operations.

[0167] As described with reference to FIG. 4 and the like, in the information processing apparatus 2, a modification processing unit F2 is provided that generates a pre-learning neural network architecture as a modified architecture Ac by performing a modification process of modifying a part of the base architecture Ab, which is the pre-learning neural network architecture serving as a base. The modified architecture Ac is at least a part of a plurality of pre-learning neural network architectures, and the number of parameters and the number of multiply-accumulate operations in the base architecture Ab may be made smaller by a certain ratio or more than the conditions acquired by the condition acquisition unit F1. The base architecture Ab is a neural network architecture that serves as a base for the modified architecture Ac. A new neural network architecture obtained by modifying the neural network architecture may have a larger number of parameters and a larger number of multiply-accumulate operations than before the modification. Therefore, by adopting a neural network architecture with a margin in the required specifications as the base architecture Ab, it becomes possible to increase the possibility that the modified neural network architecture satisfies the specifications. And it becomes possible to reduce the possibility that the high-performance neural network architecture obtained after the modification does not satisfy the specifications, and it becomes possible to increase the possibility that the high-performance neural network architecture is presented to the user.

[0168] As described with reference to FIG. 9 and the like, the information processing apparatus 2 may include a presentation processing unit F6 that presents a prediction performance index value Vi and an integrated index value Vf for each performance predictor Pr for the pre-learning neural network architecture selected by the selection processing unit F5. For example, the user can select a neural network architecture while grasping the index value regarding the predicted performance of the neural network architecture selected by the selection processing unit F5. Then, by presenting to the user not only the neural network architecture finally selected by the selection processing unit F5 but also index values and the like for other neural network architectures belonging to the candidate architecture group, the user can select and learn a preferred neural network architecture from among a plurality of neural network architectures while considering the neural network architecture selected by the selection processing unit F5.

[0169] As described with reference to FIG. 9 and the like, the presentation processing unit F6 in the information processing apparatus 2 may present a histogram of the integrated index value Vf for a plurality of neural network architectures before learning. By presenting the histogram, the evaluation of the neural network architecture selected by the selection processing unit F5 can be relatively grasped, which can assist the user in selecting a neural network architecture.

[0170] The method for manufacturing a neural network architecture of the present technology includes a step of obtaining a prediction performance index value Vi indicating the result of prediction using a performance predictor Pr that predicts the performance of a learned AI model obtained by performing learning on a neural network architecture before learning without going through the learning phase, a step of calculating an integrated index value Vf for the neural network architecture before learning by integrating the prediction performance index values Vi for each performance predictor Pr obtained using a plurality of performance predictors Pr, and a step of selecting one neural network architecture before learning based on the integrated index value Vf calculated for each of the plurality of neural network architectures before learning.

[0171] The program of this technology is a program to be executed by an arithmetic processing unit, and has a function of obtaining a prediction performance index value Vi indicating the result of prediction using a performance predictor Pr that predicts the performance of a learned AI model obtained by performing learning on a neural network architecture before learning without going through the learning phase, a function of calculating an integrated index value Vf for the neural network architecture before learning by integrating the prediction performance index values Vi for each performance predictor Pr obtained using a plurality of performance predictors Pr, and a function of selecting one neural network architecture before learning based on the integrated index value Vf calculated for each of the plurality of neural network architectures before learning.

[0172] Such a signal processing method and program can also obtain the various operations and effects described above.

[0173] Note that such a program can be pre-recorded in an HDD (Hard Disk Drive) as a recording medium built into a device such as a computer device, or in a ROM in a microcomputer having a CPU. Alternatively, the program can be temporarily or permanently stored (recorded) in a removable recording medium such as a flexible disk, CD-ROM (Compact Disk Read Only Memory), MO (Magneto Optical) disk, DVD (Digital Versatile Disc), Blu-ray Disc (registered trademark), magnetic disk, semiconductor memory, memory card, etc. Such a removable recording medium can be provided as so-called packaged software. Also, such a program can be installed from a removable recording medium into a personal computer or the like, or can be downloaded via a network such as a LAN or the Internet from a download site.

[0174] Note that the effects described in this specification are merely examples and are not limited, and there may be other effects.

[0175] Further, the above-described examples may be combined in any manner, and various effects described above can be obtained even when various combinations are used.

[0176] <5. The present technology> The present technology can also adopt the following configuration. (1) An index calculation unit that obtains a prediction performance index value indicating the result of the prediction using a performance predictor that predicts the performance of a learned AI model obtained by performing learning on a neural network architecture before learning without going through a learning phase; An integration processing unit that integrates the prediction performance index values for each of the performance predictors obtained using a plurality of the performance predictors and calculates an integrated index value for the neural network architecture before learning; A selection processing unit that selects one of the neural network architectures before learning based on the integrated index values calculated for each of the plurality of neural network architectures before learning, An information processing apparatus. (2) A modification processing unit that generates the neural network architecture before learning as a modified architecture by performing a modification process of modifying a part of the base architecture using the neural network architecture before learning as the base architecture, The modified architecture is at least a part of the plurality of neural network architectures before learning The information processing apparatus according to (1) above. (3) The modification process is a process of applying an evolutionary algorithm to the base architecture The information processing apparatus according to (2) above. (4) The modification process is a process of causing a mutation in a part of the base architecture The information processing apparatus according to (3) above. (5) The modification processing unit generates the modified architecture in which further modification is performed on the base architecture by performing the modification processing on the modified architecture. The information processing apparatus according to (4) above. (6) The modification processing unit generates a plurality of the modified architectures by repeating the modification processing a predetermined number of times. The information processing apparatus according to (5) above. (7) When the number of neural network architectures belonging to the candidate architecture group including the base architecture and the modified architecture exceeds a predetermined number, the selection processing unit selects the predetermined number of neural network architectures from the candidate architecture group using the integrated index value. The information processing apparatus according to any one of (2) to (6) above. (8) The modified architecture is enabled to be performance-predicted by the performance predictor used for performance prediction of the base architecture. The information processing apparatus according to any one of (2) to (7) above. (9) The integration processing unit calculates a standardized post-index value by performing standardization of the predicted performance index value corresponding to the performance predictor, and calculates the integrated index value using a plurality of the standardized post-index values. The information processing apparatus according to any one of (1) to (8) above. (10) The integration processing unit performs the standardization so that the average value and the variance value of the standardized post-index value match for each performance predictor. The information processing apparatus according to (9) above. (11) The integration processing unit performs weighting corresponding to the performance predictor on the standardized post-index value and calculates the integrated index value. The information processing apparatus according to any one of (9) to (10) above. (12) The integration processing unit performs the weighting using the high prediction performance of the performance predictor. The information processing apparatus according to the above (11). (13) The index calculation unit obtains the prediction performance index value using the performance predictor capable of predicting the performance of both the base architecture and the modified architecture obtained by modifying the base architecture. The information processing apparatus according to any one of the above (2) to the above (7). (14) A condition acquisition unit that acquires conditions for the number of parameters and the number of multiply-accumulate operations allowed in the learned AI model, The selection processing unit selects the neural network architecture before learning based on the conditions acquired by the condition acquisition unit. The information processing apparatus according to any one of the above (1) to the above (13). (15) A modification processing unit that generates the neural network architecture before learning as a modified architecture by performing a modification process of modifying a part of the base architecture, which is the neural network architecture before learning serving as a base, The modified architecture is at least a part of the plurality of neural network architectures before learning, The number of parameters and the number of multiply-accumulate operations in the base architecture are made smaller by a certain ratio or more than the conditions acquired by the condition acquisition unit. The information processing apparatus according to the above (14). (16) A presentation processing unit that causes the prediction performance index value and the integrated index value for each performance predictor for the neural network architecture before learning selected by the selection processing unit to be presented. The information processing apparatus according to any one of the above (1) to the above (15). (17) The presentation processing unit causes a histogram of the integrated index values for the plurality of neural network architectures before learning to be presented. The information processing apparatus according to the above (16). (18) A function of obtaining a predicted performance index value indicating the result of the prediction using a performance predictor that predicts the performance of a learned AI model obtained by performing learning on a neural network architecture before learning without going through a learning phase; A function of calculating an integrated index value for the neural network architecture before learning by integrating the predicted performance index values for each of the performance predictors obtained using a plurality of the performance predictors; A function of selecting one of the neural network architectures before learning based on the integrated index values calculated for each of the plurality of neural network architectures before learning, and causing an arithmetic processing unit to execute Program. (19) A step of obtaining a predicted performance index value indicating the result of the prediction using a performance predictor that predicts the performance of a learned AI model obtained by performing learning on a neural network architecture before learning without going through a learning phase; A step of calculating an integrated index value for the neural network architecture before learning by integrating the predicted performance index values for each of the performance predictors obtained using a plurality of the performance predictors; A step of selecting one of the neural network architectures before learning based on the integrated index values calculated for each of the plurality of neural network architectures before learning, and comprising Method for manufacturing a neural network architecture.

Explanation of symbols

[0177] 2 Information processing apparatus Ab Base architecture Ac Modified architecture F1 Condition acquisition unit F2 Modification processing unit F3 Index calculation unit F4 Integration processing unit F5 Selection processing unit F6 Presentation processing unit Pr Performance predictor Vf integrated index value Vi prediction performance index value Vs standardized index value

Claims

1. An index calculation unit that obtains a prediction performance index value indicating the result of the prediction using a performance predictor that predicts, without going through a learning phase, the performance of a learned AI model obtained by performing learning on a neural network architecture before learning; An integration processing unit that integrates the prediction performance index values for each of the performance predictors obtained using a plurality of the performance predictors to calculate an integrated index value for the neural network architecture before learning; A selection processing unit that selects one of the neural network architectures before learning based on the integrated index values calculated for each of the plurality of neural network architectures before learning, the information processing apparatus comprising: An information processing apparatus.

2. A modification processing unit that generates the neural network architecture before learning as a modified architecture by performing a modification process of modifying a part of the base architecture using the neural network architecture before learning as the base architecture; The modified architecture is at least a part of the plurality of neural network architectures before learning The information processing apparatus according to claim 1.

3. The modification process is a process of applying an evolutionary algorithm to the base architecture The information processing apparatus according to claim 2.

4. The modification process is a process of causing a mutation in a part of the base architecture The information processing apparatus according to claim 3.

5. The modification processing unit generates a modified architecture in which a further modification is made to the base architecture by performing the modification process on the modified architecture The information processing apparatus according to claim 4.

6. The modification processing unit generates a plurality of the modified architectures by repeating the modification process a predetermined number of times The information processing apparatus according to claim 5.

7. When the number of neural network architectures belonging to a candidate architecture group consisting of the base architecture and the modified architecture exceeds a predetermined number, the selection processing unit selects the predetermined number of neural network architectures from the candidate architecture group using the integrated index value The information processing apparatus according to claim 2.

8. The modified architecture enables performance prediction by the performance predictor used for performance prediction of the base architecture. The information processing apparatus according to claim 2.

9. The integrated processing unit calculates a standardized post-index value by standardizing the predicted performance index value according to the performance predictor, and calculates the integrated index value using a plurality of the standardized post-index values. The information processing apparatus according to claim 1.

10. The integrated processing unit performs the standardization so that the average value and the variance value of the standardized post-index value match for each performance predictor. The information processing apparatus according to claim 9.

11. The integrated processing unit weights the standardized post-index value according to the performance predictor and calculates the integrated index value. The information processing apparatus according to claim 9.

12. The integrated processing unit performs the weighting using the level of predicted performance of the performance predictor. The information processing apparatus according to claim 11.

13. The index calculation unit obtains the predicted performance index value using a performance predictor capable of predicting the performance of both the base architecture and the modified architecture obtained by modifying the base architecture. The information processing apparatus according to claim 2.

14. Comprising a condition acquisition unit that acquires conditions for the number of parameters and the number of multiply-accumulate operations allowed in the learned AI model, The selection processing unit selects the neural network architecture before learning based on the conditions acquired by the condition acquisition unit. The information processing apparatus according to claim 1.

15. Comprising a modification processing unit that generates a neural network architecture before learning as a modified architecture by performing a modification process of modifying a part of the base architecture, which is the neural network architecture before learning serving as a base, The modified architecture is at least a part of the plurality of neural network architectures before learning, The number of parameters and the number of multiply-accumulate operations in the base architecture are made smaller by a certain ratio or more than the conditions acquired by the condition acquisition unit. The information processing apparatus according to claim 14.

16. Comprising a presentation processing unit that presents the predicted performance index value and the integrated index value for each performance predictor for the neural network architecture before learning selected by the selection processing unit. The information processing apparatus according to claim 1.

17. The presentation processing unit causes a histogram of the integrated index values for the plurality of neural network architectures before learning to be presented. The information processing apparatus according to claim 16.

18. A function of obtaining a prediction performance index value indicating the result of the prediction using a performance predictor that predicts the performance of a learned AI model obtained by performing learning on a neural network architecture before learning without going through a learning phase; A function of calculating an integrated index value for the neural network architecture before learning by integrating the prediction performance index values for each of the performance predictors obtained using a plurality of the performance predictors; A function of selecting one of the neural network architectures before learning based on the integrated index values calculated for each of the plurality of neural network architectures before learning, and causing the arithmetic processing unit to execute the function. Program.

19. A step of obtaining a prediction performance index value indicating the result of the prediction using a performance predictor that predicts the performance of a learned AI model obtained by performing learning on a neural network architecture before learning without going through a learning phase; A step of calculating an integrated index value for the neural network architecture before learning by integrating the prediction performance index values for each of the performance predictors obtained using a plurality of the performance predictors; A step of selecting one of the neural network architectures before learning based on the integrated index values calculated for each of the plurality of neural network architectures before learning, and comprising the step. A method for manufacturing a neural network architecture.

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