Manufacturing method for quantum bit device

Abstract

To provide a manufacturing method for a quantum bit device that can prevent a member covering the quantum bit from peeling off from a substrate.SOLUTION: A manufacturing method for a quantum bit device includes the steps of: forming a first conductive film on a first surface of a quantum bit substrate; forming a quantum bit on the first surface; forming at least one through hole in the quantum bit substrate that penetrates the quantum bit substrate; forming a resist from the first surface to cover the quantum bit and the through hole; forming a second conductive film on the first conductive film and the resist; forming a first member on the second conductive film; and removing the resist from the second surface of the quantum bit substrate through the through hole after the step of forming the first member.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a qubit device.

Background Art

[0002] There is known a qubit device in which a member having a recess is joined to a substrate provided with qubits using a bonding material such as a bump, and the qubits are arranged in a void formed by the recess (for example, Patent Documents 1 and 2). In addition, a configuration in which vias are formed in a substrate provided with qubits is also known (for example, Patent Documents 1-3).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] When joining a member having a recess to a substrate provided with qubits using a plurality of bonding materials, the heights of the plurality of bonding materials may not be uniform due to manufacturing variations or the like. In this case, the bonding material with a low height may not sufficiently contribute to the bonding between the substrate and the member, and the member may peel off from the substrate.

[0005] On one side, an object is to suppress the peeling of the member covering the qubits from the substrate.

Means for Solving the Problems

[0006] In one aspect, a method for manufacturing a qubit device includes a step of forming a first conductive film on a first surface of a qubit substrate, a step of forming qubits on the first surface, a step of forming at least one through-hole penetrating the qubit substrate in the qubit substrate, a step of forming a resist on the first surface so as to cover the qubits and the through-hole, a step of forming a second conductive film on the first conductive film and the resist, a step of forming a first member on the second conductive film, and a step of removing the resist from a second surface of the qubit substrate through the through-hole after the step of forming the first member.

Advantages of the Invention

[0007] As one aspect, it is possible to suppress the peeling of the member covering the qubits from the substrate.

Brief Description of the Drawings

[0008]

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DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

Embodiment

[0010] FIG. 1 is a plan view of a quantum bit device 100 according to an embodiment. FIGS. 2(a) and 2(b) are cross-sectional views of the quantum bit device 100 according to the embodiment. In FIG. 1, a first member 18 provided on a quantum bit substrate 10 and a part of a conductive film 17 are shown in a perspective view, and hatching is applied to the conductive film for clarity of the drawing.

[0011] As shown in FIGS. 1, 2(a), and 2(b), in the quantum bit device 100 according to the embodiment, a quantum bit 20 and a coupling wiring 40 are provided on a quantum bit substrate 10. The quantum bit device 100 is used for a quantum computer that operates in a superconducting state at an extremely low temperature of, for example, several tens of millikelvin (mK). The quantum bit 20 includes a Josephson junction element 30 connected between a central electrode 21 and an outer peripheral electrode 22, and a capacitor 23 formed by opposing the central electrode 21 and the outer peripheral electrode 22.

[0012] FIG. 3(a) is a plan view of the Josephson junction element 30 in the embodiment, FIG. 3(b) is a cross-sectional view taken along line A-A of FIG. 3(a), and FIG. 3(c) is a cross-sectional view taken along line B-B of FIG. 3(a). In FIG. 3(a), illustration of the insulating film 33 provided on the surface of the superconducting film 31 is omitted. As shown in FIGS. 3(a) to 3(c), the Josephson junction element 30 includes a superconducting film 31 extending in the X-axis direction, a superconducting film 32 extending in the Y-axis direction, and an insulating film 33 provided therebetween in a region where the superconducting film 31 and the superconducting film 32 overlap. The insulating film 33 is provided, for example, so as to cover the surface of the superconducting film 31. A region where the superconducting film 31 and the superconducting film 32 overlap via the insulating film 33 becomes the Josephson junction 34. The superconducting films 31 and 32 are, for example, aluminum films. The insulating film 33 is, for example, an aluminum oxide film. The Josephson junction element 30 is connected between the central electrode 21 and the outer peripheral electrode 22 by connecting one of the superconducting film 31 and the superconducting film 32 to the central electrode 21 and the other to the outer peripheral electrode 22.

[0013] As shown in FIGS. 1, 2(a), and 2(b), the coupling wiring 40 is electrostatically coupled to the quantum bit 20 and is a wiring that couples between adjacent quantum bits 20. Connection between the quantum bit 20 and the coupling wiring 40 is made at a high frequency. A conductive film 13 is provided around the quantum bit 20 and the coupling wiring 40 on the upper surface 11 of the quantum bit substrate 10, and on the lower surface 12 of the quantum bit substrate 10.

[0014] A plurality of through holes 14 are provided around the quantum bit 20. The through holes 14 are provided so as to penetrate from the upper surface 11 to the lower surface 12 of the quantum bit substrate 10. A conductive film 15 is provided on the inner wall of the through hole 14 from the upper surface 11 to the lower surface 12 of the quantum bit substrate 10. That is, the conductive film 15 is a via wiring that penetrates the quantum bit substrate 10. The conductive film 15 is in direct contact with the conductive films 13 on the upper surface 11 and the lower surface 12 of the quantum bit substrate 10. In the through hole 14, a gap 19 is formed inside the conductive film 15.

[0015] On the quantum bit substrate 10, a conductive film 17 with an uneven shape is provided so that a gap 16 in which the quantum bit 20 is exposed is formed between the quantum bit substrate 10. The conductive film 17 is provided in direct contact with the conductive film 13. The conductive film 17 is supplied with a ground potential through the conductive film 13 provided on the lower surface 12 of the quantum bit substrate 10, the conductive film 15 provided in the through hole 14, and the conductive film 13 provided on the upper surface 11 of the quantum bit substrate 10. The gap 16 is connected to the gap 19 of the through hole 14. On the conductive film 17, a first member 18 is provided to cover the conductive film 17. The quantum bit 20 is protected by the laminate of the conductive film 17 and the first member 18.

[0016] The quantum bit substrate 10 is a semiconductor substrate or an insulating substrate such as a silicon substrate or a sapphire substrate. The central electrode 21, the outer peripheral electrode 22, the coupling wiring 40, the conductive film 13, the conductive film 15, and the conductive film 17 are, for example, superconducting films, and are formed of, for example, aluminum (Al), titanium nitride (TiN), niobium (Nb), or tantalum (Ta). The first member 18 is a film containing, for example, a resin or an inorganic insulator, and is, for example, an epoxy resin film, a polyimide resin film, or a silicon oxide film.

[0017] FIG. 2(a) shows a case where the gaps 16 in which the adjacent quantum bits 20 are respectively exposed are separately formed, and FIG. 2(b) shows a case where the adjacent quantum bits 20 are exposed in a common gap 16. A plurality of quantum bits 20 are provided in the quantum bit device 100. Each of all the quantum bits 20 may be exposed in an individual gap 16, or all the quantum bits 20 may be exposed in a common gap 16. Also, some of the quantum bits 20 may be respectively exposed in individual gaps 16, and some or all of the other quantum bits 20 may be exposed in a common gap 16. By at least some of the quantum bits 20 being respectively exposed in individual gaps 16, the mechanical strength of the laminate of the conductive film 17 and the first member 18 is increased, and the gap 16 is less likely to be crushed.

[0018] [First manufacturing method] Figures 4(a) to 6(c) are cross-sectional views showing a first manufacturing method of the quantum bit device 100 according to the embodiment. As shown in FIG. 4(a), for example, using a mask layer (not shown) formed on the upper surface 11 of the quantum bit substrate 10 which is a silicon substrate as a mask, the quantum bit substrate 10 is etched to form a through hole 14 in the quantum bit substrate 10. The through hole 14 is formed to penetrate from the upper surface 11 to the lower surface 12 of the quantum bit substrate 10. The mask layer is, for example, a patterned resist. The etching of the quantum bit substrate 10 uses, for example, dry etching, and as an example, reactive ion etching using a Bosch process is used. For example, the quantum bit substrate 10 is etched using SF6 gas as a fluorine-based gas, and a protective film is formed on the inner wall of the etched hole using O2 gas as an oxygen-based gas, and this is alternately repeated to form the through hole 14. As a result, a through hole 14 having a diameter of about 100 μm to 150 μm and a depth of about 250 μm to 350 μm is formed in the quantum bit substrate 10. The inner wall of the through hole 14 is formed to be substantially vertical.

[0019] As shown in FIG. 4(b), for example, using a sputtering method, a conductive film 13 is formed on the upper surface 11 and the lower surface 12 of the quantum bit substrate 10. The conductive film 13 is, for example, a titanium nitride (TiN) film and has a thickness of about 100 nm to 300 nm.

[0020] As shown in FIG. 4(c), for example, using an oblique vacuum evaporation method using a stencil mask, a conductive film 15 is formed on the inner wall of the through hole 14. The conductive film 15 extends from the upper surface 11 of the quantum bit substrate 10 through the inner wall of the through hole 14 to the lower surface 12 and is formed in direct contact with the conductive film 13. In the through hole 14, a void 19 is formed inside the conductive film 15. The conductive film 15 is, for example, an aluminum (Al) film and has a thickness of about 300 nm to 1000 nm.

[0021] As shown in Fig. 5(a), the conductive film 13 in the region where the quantum bit 20 is formed is removed. The removal of the conductive film 13 is performed by etching the conductive film 13 using a mask layer (not shown) formed on the upper surface 11 of the quantum bit substrate 10 as a mask. At the same time, by etching the conductive film 13, the central electrode 21, the outer peripheral electrode 22, and the coupling wiring 40 (see Fig. 1) are formed. After removing the conductive film 13, the Josephson junction element 30 is formed in the region where the conductive film 13 has been removed, thereby forming the quantum bit 20.

[0022] Figs. 7(a) to 8(b) are diagrams showing a method for manufacturing the Josephson junction element 30 in the embodiment. The upper diagrams in Figs. 7(a) to 8(b) are plan views showing the method for manufacturing the Josephson junction element 30. The middle diagrams are cross-sectional views taken along line A-A of the upper diagrams, and the lower diagrams are cross-sectional views taken along line B-B of the upper diagrams. In the upper plan views in Figs. 7(b) to 8(b), for clarity of the drawing, the superconducting films 31, 32, and the insulating film 33 formed in the gap 73 are hatched.

[0023] As shown in Fig. 7(a), a mask layer 60 is formed on the quantum bit substrate 10. The mask layer 60 has an upper layer 61 and a lower layer 62. The mask layer 60 is formed of, for example, a resist. A mask pattern 70 including an opening 71, an opening 72, and a gap 73 is formed in the mask layer 60. The opening 71 extends in the X-axis direction, the opening 72 intersects the opening 71 and extends in the Y-axis direction, and both are formed in the upper layer 61. The gap 73 is formed in the lower layer 62. The gap 73 is located below the openings 71 and 72 and has a shape that enlarges the shapes of the openings 71 and 72 in plan view. The widths of the openings 71 and 72 are, for example, about 100 nm to 300 nm.

[0024] As shown in Fig. 7(b), using the mask layer 60 as a mask, a superconducting film 31 is formed on the qubit substrate 10 by an oblique vacuum evaporation method from above in the -X direction as indicated by the arrow 75. Since the superconducting film 31 is formed by the oblique vacuum evaporation method from above in the -X direction, by setting the width dimension of the opening 72 to an appropriate size, a superconducting film 31 extending in the Y-axis direction is not formed in the gap 73. Only a superconducting film 31 extending in the X-axis direction is formed in the gap 73. The superconducting film 31 is, for example, an aluminum (Al) film, with a thickness of about 30 nm to 50 nm and a width of about 100 nm to 300 nm.

[0025] As shown in Fig. 7(c), while maintaining the vacuum state when the superconducting film 31 is formed, oxygen is introduced into the chamber to oxidize the surface of the superconducting film 31, and an insulating film 33 made of, for example, aluminum oxide (Al2O3) is formed on the surface of the superconducting film 31.

[0026] As shown in Fig. 8(a), using the mask layer 60 as a mask, a superconducting film 32 is formed on the qubit substrate 10 by an oblique vacuum evaporation method from above in the +Y direction as indicated by the arrow 76. Since the superconducting film 32 is formed by the oblique vacuum evaporation method from above in the +Y direction, by setting the width dimension of the opening 71 to an appropriate size, a superconducting film 32 extending in the X-axis direction is not formed in the gap 73. Only a superconducting film 32 extending in the Y-axis direction is formed in the gap 73. The superconducting film 32 is, for example, an aluminum (Al) film, with a thickness of about 50 nm to 70 nm and a width of about 100 nm to 300 nm. Thereby, a region 74 is formed where the superconducting film 31 extending in the X-axis direction and the superconducting film 32 extending in the Y-axis direction overlap via the insulating film 33.

[0027] As shown in Fig. 8(b), the mask layer 60, the superconducting film 31 formed on the mask layer 60, the insulating film 33, and the superconducting film 32 are removed by the lift-off method. The region 74 where the superconducting film 31 extending in the X-axis direction and the superconducting film 32 extending in the Y-axis direction overlap via the insulating film 33 becomes the Josephson junction 34.

[0028] As shown in Fig. 5(b), a resist film 52 covering the quantum bit 20 is applied onto the upper surface 11 of the quantum bit substrate 10 by, for example, the spin coating method. The resist film 52 is also embedded in the void 19 in the through hole 14. The thickness of the resist film 52 is, for example, about 150 μm to 300 μm.

[0029] As shown in Fig. 5(c), patterning is performed by exposure and development or the like so as to leave the resist film 52 in the region where the void 16 (see Figs. 2(a) and 2(b)) where the quantum bit 20 is to be exposed is to be formed, thereby forming a resist pattern 54. The resist pattern 54 covers the quantum bit 20 and the through hole 14, and is formed by being embedded in the void 19 in the through hole 14.

[0030] As shown in Fig. 6(a), a conductive film 17 is formed on the conductive film 13 and the resist pattern 54 by, for example, the oblique vacuum evaporation method. The conductive film 17 is, for example, an aluminum (Al) film, and the thickness is, for example, about 400 nm to 600 nm. The conductive film 17 is formed in direct contact with the conductive film 13.

[0031] As shown in Fig. 6(b), a first member 18 is formed on the conductive film 17. The first member 18 is formed in direct contact with the conductive film 17. The first member 18 is formed under manufacturing conditions of, for example, 150 °C or lower, preferably 100 °C or lower, in order to suppress the influence on the quantum bit 20. For example, the first member 18 made of a silicon oxide film is formed by a low-temperature chemical vapor deposition (CVD) method using TEOS (tetraethoxysilane) as a raw material. For example, the first member 18 made of an epoxy resin film is formed by applying and curing a liquid epoxy resin. For example, the first member 18 made of a polyimide resin film is formed by bonding a film-shaped polyimide resin. Note that the first member 18 may be an inorganic insulating film other than the silicon oxide film, may be a resin film other than the epoxy resin film and the polyimide resin film, or may be other cases. The thickness of the first member 18 is, for example, about 5 μm to 30 μm.

[0032] As shown in FIG. 6(c), a stripping agent for removing the resist pattern 54 is introduced into the resist pattern 54 through the through hole 14 from the lower surface 12 of the qubit substrate 10 to remove the resist pattern 54. As a result, the resist pattern 54 on the qubit 20 is removed, and a gap 16 is formed in which the qubit 20 is exposed between the qubit substrate 10 and the conductive film 17. By exposing the qubit 20 to the gap 16, a decrease in the coherence time of the qubit 20 is suppressed. The gap 16 is formed to connect to the gap 19 in the through hole 14.

[0033] [Second manufacturing method] FIGS. 9(a) to 10(c) are cross-sectional views showing a second manufacturing method of the qubit device 100 according to the embodiment. As shown in FIG. 9(a), for example, using a sputtering method, a conductive film 13 is formed on the upper surface 11 and the lower surface 12 of the qubit substrate 10, which is, for example, a silicon substrate. The conductive film 13 is, for example, a titanium nitride (TiN) film and has a thickness of, for example, about 100 nm to 300 nm.

[0034] As shown in FIG. 9(b), the conductive film 13 in the region where the qubit 20 is to be formed is removed. The removal of the conductive film 13 is performed by etching the conductive film 13 using a mask layer (not shown) formed on the upper surface 11 of the qubit substrate 10 as a mask. At the same time, by etching the conductive film 13, the central electrode 21, the outer peripheral electrode 22, and the coupling wiring 40 (see FIG. 1) are formed. After removing the conductive film 13, the qubit 20 is formed by forming the Josephson junction element 30 in the region where the conductive film 13 has been removed. The Josephson junction element 30 is formed by the manufacturing method shown in FIGS. 7(a) to 8(b).

[0035] As shown in FIG. 9(c), a protective film 56 covering the conductive film 13 and the qubit 20 is formed on the upper surface 11 of the qubit substrate 10. The protective film 56 is, for example, a silicon oxide film formed by a low-temperature CVD method at 100° C. or lower. The protective film 56 is provided to protect the qubit 20. The thickness of the protective film 56 is, for example, about 5 μm to 30 μm.

[0036] As shown in Fig. 10(a), a mask layer 58 having an opening 57 is formed on the lower surface 12 of the qubit substrate 10 in a region where the through-hole 14 is to be formed. The mask layer 58 is formed of, for example, a resist.

[0037] As shown in Fig. 10(b), using the mask layer 58 as a mask, the qubit substrate 10 and the protective film 56 are etched to form a through-hole 14 that penetrates the qubit substrate 10 from the lower surface 12 to the upper surface 11. The etching of the qubit substrate 10 and the protective film 56 uses, for example, dry etching, and as an example, reactive ion etching using a Bosch process is used. As a result, a through-hole 14 having a diameter of about 100 μm to 150 μm and a depth of about 250 μm to 350 μm is formed in the qubit substrate 10. The inner wall of the through-hole 14 is formed to be substantially vertical.

[0038] As shown in Fig. 10(c), after removing the protective film 56 and the mask layer 58, the same steps as those shown in Fig. 4(c) in the first manufacturing method are performed to form a conductive film 15 on the inner wall of the through-hole 14. The conductive film 15 extends from the upper surface 11 of the qubit substrate 10 through the inner wall of the through-hole 14 to the lower surface 12 and is formed in direct contact with the conductive film 13. The conductive film 15 is, for example, an aluminum (Al) film and has a thickness of about 300 nm to 1000 nm.

[0039] Thereafter, the same steps as those shown in Figs. 5(b) to 6(c) in the first manufacturing method are performed.

[0040] [Comparative Example] Figs. 11(a) to 11(d) are cross-sectional views showing a method for manufacturing a qubit device according to a comparative example. As shown in Fig. 11(a), the same steps as those shown in Figs. 4(a) to 5(a) of the embodiment are performed. As shown in Fig. 11(b), a plurality of bonding materials 90 are formed on the conductive film 13 using, for example, vapor deposition and lift-off methods. The bonding materials 90 are, for example, bumps, and as an example, indium (In) bumps.

[0041] As shown in Fig. 11(c), a cover member 94 having a recess 92 on the surface 91 and a conductive film 93 provided on the surface 91 along the inner surface of the recess 92 is separately fabricated. The recess 92 is formed, for example, using photolithography and etching methods. The conductive film 93 is formed, for example, using a vapor deposition method. The cover member 94 is, for example, a silicon substrate, and the conductive film 93 is, for example, an aluminum (Al) film.

[0042] As shown in Fig. 11(d), the conductive film 93 of the cover member 94 is joined to a plurality of bonding materials 90. Thereby, a gap 95 in which the quantum bit 20 is exposed is formed between the quantum bit substrate 10 and the cover member 94. The quantum bit 20 is protected by the conductive film 93 and the cover member 94.

[0043] In the comparative example, as shown in Fig. 11(d), the cover member 94 is joined to the quantum bit substrate 10 by a plurality of bonding materials 90. In this case, since the bonding materials 90 are formed, for example, by vapor deposition and lift-off methods, there may be manufacturing variations in height among the plurality of bonding materials 90. In order to suppress the influence on the quantum bit 20, it is preferable to join the cover member 94 to the bonding materials 90 at a low temperature. For this purpose, since the cover member 94 is pressed against the bonding materials 90 with a small load, if there is height variation among the plurality of bonding materials 90, bonding materials 90 that do not bond to the cover member 94 will appear. In this case, the bonding force between the quantum bit substrate 10 and the cover member 94 becomes weak, and the cover member 94 may peel off from the quantum bit substrate 10.

[0044] Therefore, in the embodiment, by the manufacturing method described above, a conductive film 17 and a first member 18 for protecting the qubit 20 are formed on the qubit substrate 10. That is, as shown in FIG. 4(b) or FIG. 9(a), a conductive film 13 (first conductive film) is formed on the upper surface 11 (first surface) of the qubit substrate 10. As shown in FIG. 5(a) or FIG. 9(b), the qubit 20 is formed on the upper surface 11 of the qubit substrate 10. As shown in FIG. 4(a) or FIG. 10(b), at least one through hole 14 penetrating the qubit substrate 10 is formed in the qubit substrate 10. As shown in FIG. 5(c), a resist pattern 54 (resist) is formed on the upper surface 11 of the qubit substrate 10 so as to cover the qubit 20 and the through hole 14. As shown in FIG. 6(a), a conductive film 17 (second conductive film) is formed on the conductive film 13 and the resist pattern 54. As shown in FIG. 6(b), the first member 18 is formed on the conductive film 17. As shown in FIG. 6(c), after the first member 18 is formed, the resist pattern 54 is removed from the lower surface 12 (second surface) of the qubit substrate 10 through the through hole 14. By using such a manufacturing method, the bonding force between the conductive film 13 and the conductive film 17 and the bonding force between the conductive film 17 and the first member 18 are increased, so that the conductive film 17 and the first member 18 can be prevented from peeling off from the qubit substrate 10.

[0045] In addition, in the embodiment, a ground potential is supplied to the conductive film 17. Thereby, an effect of shielding electromagnetic waves can be imparted to the conductive film 17. Therefore, it is possible to suppress the occurrence of interference with the driving of the qubit 20 and deterioration of characteristics due to electromagnetic waves.

[0046] In addition, in the embodiment, the conductive film 17 is a superconducting film. Since the qubit device 100 is used at an extremely low temperature of, for example, several tens of millikelvin (mK), the conductive film 17 being a superconducting film enables it to enter a superconducting state and the conductive film 17 can be set to the ground potential well. Therefore, a shielding effect can be effectively imparted to the conductive film 17.

[0047] Also, in the embodiment, as shown in FIG. 4(c) or FIG. 10(c), a conductive film 15 (third conductive film) connected to the conductive film 13 is formed on the inner surface of the through hole 14. The ground potential is supplied to the conductive film 17 via the conductive film 13 and the conductive film 15. Thereby, the ground potential can be easily supplied to the conductive film 17.

[0048] Also, in the embodiment, the conductive film 13, the conductive film 15, and the conductive film 17 are superconducting films. Thereby, even when the temperature is extremely low, for example, several tens of millikelvin (mK), the ground potential can be favorably supplied to the conductive film 17 via the conductive film 13 and the conductive film 15.

[0049] Also, in the embodiment, the first member 18 is a film containing a resin or an inorganic insulator. Thereby, it is possible to suppress the conductive film 17 from being inadvertently electrically connected to other members. Also, when the first member 18 is a resin film, it becomes easier for the first member 18 to absorb an external force.

[0050] Also, in the first manufacturing method of the embodiment, as shown in FIGS. 4(a) to 5(a), before forming the qubit 20, a through hole 14 penetrating the qubit substrate 10 is formed. Thus, by forming the qubit 20 after forming the through hole 14, it is possible to suppress damaging the qubit 20 regardless of the conditions used for forming the through hole 14.

[0051] Also, in the second manufacturing method of the embodiment, as shown in FIGS. 9(b) to 10(c), after forming the qubit 20, a through hole 14 penetrating the qubit substrate 10 is formed. Thereby, since the qubit 20 can be formed in a state without the through hole 14, the ease of forming the qubit 20 is improved.

[0052] In the embodiments, the distance H (see FIGS. 2(a) and 2(b)) from the upper surface 11 of the qubit substrate 10 to the conductive film 17 is preferably 40 μm or more, more preferably 60 μm or more, and even more preferably 80 μm or more. Thereby, the electric field generated from the qubit 20 is easily drawn into the gap 16 which is free space, so that the dielectric loss is reduced. Therefore, deterioration of the characteristics of the qubit 20 can be suppressed. Also, the parasitic capacitance between the qubit 20 and the conductive film 17 is reduced. On the other hand, as the distance H increases, the device becomes larger. Therefore, the distance H is preferably 200 μm or less, more preferably 180 μm or less, and even more preferably 160 μm or less. For example, the distance H is preferably 100 times or more, more preferably 200 times or more, and even more preferably 300 times or more the thickness of the conductive film 13. The distance H is preferably 700 times or less, more preferably 600 times or less, and even more preferably 500 times or less the thickness of the conductive film 13.

[0053] As described above, the embodiments of the present invention have been described in detail. However, the present invention is not limited to such specific embodiments, and various modifications and changes are possible within the scope of the gist of the present invention described in the claims.

Explanation of Reference Numerals

[0054] 10... qubit substrate, 11... upper surface, 12... lower surface, 13... conductive film, 14... through hole, 15... conductive film, 16... gap, 17... conductive film, 18... first member, 19... gap, 20... qubit, 21... central electrode, 22... outer peripheral electrode, 23... capacitor, 30... Josephson junction element, 31... superconducting film, 32... superconducting film, 33... insulating film, 34... Josephson junction, 40... coupling wiring, 52... resist film, 54... resist pattern, 56... protective film, 57... opening, 58... mask layer, 60... mask layer, 61... upper layer, 62... lower layer, 70... mask pattern, 71... opening, 72... opening, 73... gap, 90... bonding material, 91... surface, 92... recess, 93... conductive film, 94... cover member, 95... gap, 100... qubit device

Claims

1. A step of forming a first conductive film on a first surface of a qubit substrate; A step of forming qubits on the first surface; A step of forming at least one through hole penetrating the qubit substrate in the qubit substrate; A step of forming a resist on the first surface so as to cover the qubits and the through holes; A step of forming a second conductive film on the first conductive film and the resist; A step of forming a first member on the second conductive film; A step of removing the resist from a second surface of the qubit substrate through the through hole after the step of forming the first member; A method for manufacturing a qubit device, comprising the above steps.

2. The method for manufacturing a qubit device according to claim 1, wherein the second conductive film is supplied with a ground potential.

3. The method for manufacturing a qubit device according to claim 2, wherein the first conductive film and the second conductive film are superconducting films.

4. Comprising a step of forming a third conductive film connected to the first conductive film on an inner surface of the through hole, The method for manufacturing a qubit device according to claim 1 or 2, wherein the second conductive film is supplied with a ground potential through the first conductive film and the third conductive film.

5. The method for manufacturing a qubit device according to claim 4, wherein the first conductive film, the second conductive film, and the third conductive film are superconducting films.

6. The method for manufacturing a qubit device according to claim 1 or 2, wherein the first member is a film containing a resin or an inorganic insulator.

7. The method for manufacturing a qubit device according to claim 1 or 2, wherein the step of forming the through hole is performed before the step of forming the qubits.

8. The method for manufacturing a qubit device according to claim 1 or 2, wherein the step of forming the through hole is performed after the step of forming the qubits.

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