Semiconductor storage device

Abstract

To provide a semiconductor storage device which is improved in operation speed and reliability.SOLUTION: A semiconductor storage device comprises: a bit line; a first laminate which is disposed above the bit line, in which a plurality of first insulation layers and a plurality of first conductive layers are alternately laminated and which includes a first stair region and a first bridge region; and a second laminate which is disposed above the first laminate, in which a plurality of second insulation layers and a plurality of second conductive layers are alternately laminated and which includes a second stair region and a second bridge region. A width of the first bridge region in a third direction with respect to a lowest layer in the plurality of first conductive layers is larger than a width of the second bridge region in the third direction with respect to a lowest layer in the plurality of second conductive layers.SELECTED DRAWING: Figure 7B

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a semiconductor memory device.

Background Art

[0002] A semiconductor package using a NAND-type flash memory as a semiconductor memory device is known. In order to increase the capacity of such a NAND-type flash memory, a three-dimensional NAND-type flash memory having a configuration in which many memory cells are stacked has been put into practical use. In such a stacked three-dimensional NAND-type flash memory, it is an issue to improve the operation speed and reliability.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Embodiments according to the present disclosure provide a semiconductor memory device with improved operation speed and reliability.

Means for Solving the Problems

[0005] A semiconductor memory device according to an embodiment includes a bit line; a first stack body disposed above the bit line, in which a plurality of first insulating layers and a plurality of first conductive layers are alternately stacked in a first direction, and at the center in a second direction intersecting the first direction, a first stepped region in which ends of the plurality of first conductive layers are stepped in the second direction; and a first bridge region provided adjacent to the first stepped region in a third direction intersecting the first direction and the second direction, and electrically connecting memory cell regions on both sides in the second direction across the first stepped region for each of the plurality of first conductive layers; a second stack body disposed above the first stack body, in which a plurality of second insulating layers and a plurality of second conductive layers are alternately stacked in the first direction, and at the center in the second direction, a second stepped region in which ends of the plurality of second conductive layers are stepped in the second direction; and a second bridge region provided adjacent to the second stepped region in the third direction, and electrically connecting memory cell regions on both sides in the second direction across the second stepped region for each of the plurality of second conductive layers. The width of the first bridge region in the third direction for the lowermost layer of the plurality of first conductive layers is larger than the width of the second bridge region in the third direction for the lowermost layer of the plurality of second conductive layers.

Brief Description of the Drawings

[0006]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7A

Figure 7B

Embodiments for Carrying Out the Invention

[0007] Hereinafter, the semiconductor memory device according to the present embodiment will be specifically described with reference to the drawings. In the following description, elements having substantially the same functions and configurations are denoted by the same reference numerals or reference numerals with alphabets added after the same reference numerals, and will be described redundantly only when necessary. Each of the embodiments shown below exemplifies an apparatus and a method for embodying the technical idea of this embodiment. The embodiments can be variously modified without departing from the gist of the invention. These embodiments and their modifications are included in the invention described in the claims and its equivalent scope.

[0008] For clearer explanation, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual aspect, but this is only an example and does not limit the interpretation of the present invention. In this specification and each drawing, elements having the same functions as those described with respect to the previously presented drawings may be denoted by the same reference numerals, and redundant descriptions may be omitted.

[0009] In this specification, expressions such as "α includes A, B, or C" do not exclude the case where α includes a plurality of combinations of A to C unless otherwise specified. Further, these expressions do not exclude the case where α includes other elements.

[0010] The following embodiments can be combined with each other as long as no technical contradiction occurs.

[0011] In each embodiment of the present invention, the direction from the substrate toward the memory cell is referred to as upward. Conversely, the direction from the memory cell toward the substrate is referred to as downward. Thus, for the sake of convenience of explanation, the terms upward or downward are used for explanation. However, for example, the vertical relationship between the substrate and the memory cell may be arranged to be opposite to the illustration. Also, in the following explanation, for example, the expression a memory cell on the substrate merely explains the vertical relationship between the substrate and the memory cell as described above, and other members may be arranged between the substrate and the memory cell.

[0012] [Overall Configuration of Semiconductor Memory Device] The overall configuration of the semiconductor memory device according to this embodiment will be described with reference to FIG. 1. FIG. 1 is a cross-sectional view showing a configuration example of the semiconductor memory device 1 according to this embodiment. The semiconductor memory device 1 is configured by bonding a memory chip C1 and a CMOS (Complementary Metal Oxide Semiconductor) chip C2 to each other. The memory chip C1 is a semiconductor chip including memory cell arrays 10m_1, 10m_2, and a connection region 10s. The CMOS chip C2 is a semiconductor chip including peripheral circuits. The memory chip C1 and the CMOS chip C2 are bonded at a bonding surface FB.

[0013] The memory cell array 10m_1 includes a stack 100 including a plurality of word lines WL1 stacked in the Z direction and insulated from each other, a plurality of columnar portions CL1 extending in the Z direction within the plurality of word lines WL1, and a plurality of bit lines BL1 provided on the stack 100. The columnar portion CL1 is electrically connected to any one of the bit lines BL1 via a via contact VY1. The bit line BL1 is electrically connected to the CMOS chip C2 via wiring (not shown).

[0014] The memory cell array 10m_2 includes a stack 100 including a plurality of word lines WL2 laminated in the Z direction and insulated from each other, a plurality of columnar portions CL2 extending in the Z direction within the plurality of word lines WL2, and a plurality of bit lines BL2 provided on the stack 100. Each layer of the word line WL2 corresponds to each layer of the word line WL1. The columnar portion CL2 is electrically connected to any one of the bit lines BL2 via a via contact VY2. The bit line BL2 is electrically connected to the CMOS chip C2 via a wiring (not shown). The configurations of the memory cell arrays 10m_1 and 10m_2 may be the same.

[0015] The connection region 10s is provided between the memory cell array 10m_1 and the memory cell array 10m_2. The connection region 10s is disposed substantially at the center of the memory chip C1 in the X direction. The connection region 10s includes a plurality of word lines WL3 laminated in the Z direction. The plurality of word lines WL3 are configured in a stepped manner such that they are closest to the CMOS chip C2 at the middle portion of the connection region 10s and are farther from the CMOS chip C2 at the end portions closer to the memory cell arrays 10m_1 and 10m_2 on both sides of the middle portion of the connection region 10s. That is, the plurality of word lines WL3 are configured in a stepped manner to be spaced apart from the CMOS chip C2 as they approach the memory cell arrays 10m_1 and 10m_2 from the middle portion of the connection region 10s. Note that the direction of the steps is an example and is not necessarily limited to this. For example, they may be configured to approach the CMOS chip C2 as they approach the memory cell arrays 10m_1 and 10m_2 from the middle portion of the connection region 10s. It may also be configured to approach the CMOS chip C2 as it approaches the memory cell array 10m_1 from the end portion on the memory cell array 10m_2 side of the connection region 10s, or in the reverse configuration. The plurality of word lines WL3 laminated in the Z direction are exposed from the upper (CMOS chip C2 side) word line WL3 at each step surface (terrace region) configured in a stepped manner. Note that, locally, there are also portions where the plurality of word lines WL3 are configured to approach the CMOS chip C2 as they approach the memory cell arrays 10m_1 and 10m_2 from the middle portion.

[0016] Each layer of the word line WL3 corresponds to each layer of the word line WL1 and each layer of the word line WL2, respectively. The word lines WL1 to WL3 are at substantially the same height in their corresponding layers. Each layer of the word lines WL1 to WL3 is formed by processing a continuous same material layer. For the word lines WL1 to WL3, for example, a conductive metal such as copper or tungsten is used. Hereinafter, each layer of the word lines WL1 to WL3 that correspond to each other is also referred to as a word line layer WL. A laminate 100 is also referred to as a plurality of word line layers WL laminated in the Z direction and insulated from each other.

[0017] In the word line layer WL, the word line WL3 is electrically connected to the word line WL1 and the word line WL2 via a bridge portion WLB. The bridge portion WLB is formed by processing the same material layer as the word lines WL1 to WL3. The bridge portion WLB is a layer left in the Y direction when the word line WL3 is processed in a stepped shape, and is continuously provided in the word lines WL1 to WL3. Each word line layer WL of the word lines WL1 to WL3 is electrically connected by the bridge portion WLB.

[0018] Among the plurality of word line layers WL, there may be a word line layer WL in which the bridge portion WLB is not provided. In the word line layer WL without the bridge portion WLB, a metal bridge MB is provided between the word line WL1 and the word line WL2. The metal bridge MB is a wiring layer provided separately from the word line layers WL of the word lines WL1 to WL3, and electrically connects between the word line WL1 and the word line WL2. Contact plugs CC1 and CC2 connected to the metal bridge MB are connected to the word lines WL1 and WL2 at both ends of the connection region 10s, respectively. The metal bridge MB is connected between the contact plug CC1 connected to the word line WL1 at one end of the connection region 10s and the contact plug CC2 connected to the word line WL2 at the other end of the connection region 10s. The contact plug CC1 is connected between the metal bridge MB and the word line WL1. The contact plug CC2 is connected between the metal bridge MB and the word line WL2.

[0019] The plurality of word lines WL3 are each electrically connected to a contact plug CC extending in the Z direction at each stepped surface (terrace region) configured in a stepped shape. Further, as shown in FIG. 1, the diameter of the contact plug CC (the diameter in the X or Y direction) is formed to taper so as to become narrower as it goes toward the substrate side in the stacking direction (Z direction) in the stacked body 100.

[0020] The contact plug CC connected to the word line WL3 is electrically connected to the wiring WG11 via the wiring WG1. The wiring WG11 is a wiring exposed on the bonding surface FB between the memory chip C1 and the CMOS chip C2, and is joined to the wiring WG21 on the CMOS chip C2 side at the bonding surface FB.

[0021] The CMOS chip C2 includes a plurality of switches SW, and wirings WG2 and WG21. The switch SW is a part of the row decoder module and is composed of, for example, a MOSFET (Field Effect Transistor). The switch SW is connected to the wiring WG21 via the wiring WG2 having a multilayer wiring structure.

[0022] Each switch SW applies a word line voltage to the word line layer WL (word lines WL1 to WL3) connected thereto. For example, the switch selected from the plurality of switches SW becomes conductive in a read operation, a write operation, and an erase operation, and a word line voltage can be applied to the selected word lines WL1 to WL3.

[0023] A plurality of switches SW are provided corresponding to each of the plurality of word line layers WL. The plurality of switches SW are electrically connected to contact plugs CC connected to the word line layer WL respectively. The word line WL3 is closest to the switch SW in the middle of the connection region 10s, and is configured in a stepped manner so as to move away from the switch SW in the Z direction as it goes to the end of the connection region 10s close to the memory cell arrays 10m_1 and 10m_2. The contact plug CC is in contact with a step surface (terrace region) provided on the stepped word line WL3 from the Z direction. The switch SW is electrically connected to the corresponding word line WL3 via the contact plug CC.

[0024] [Configuration of Memory Cell Array] The configuration of the memory cell array according to the present embodiment will be described with reference to FIG. 2. FIG. 2 is a perspective view showing the configuration of the memory cell array according to the present embodiment. Note that FIG. 2 shows the memory chip C1 upside down with respect to FIG. 1. Also, since the configurations of the memory cell arrays 10m_1 and 10m_2 may be the same, the memory cell array 10m_1 will be described here, and the description of the memory cell array 10m_2 will be omitted. In FIG. 2, two directions parallel to the main surface of the substrate 10 and perpendicular to each other are referred to as the X direction and the Y direction, and a plane parallel to the main surface of the substrate 10 is referred to as the XY plane. A direction perpendicular to both the X direction and the Y direction is referred to as the Z direction (lamination direction).

[0025] As shown in FIG. 2, the memory cell array 10m_1 includes a substrate 10, a laminate 100 provided on the substrate 10, a plurality of columnar body portions CL1, and a plurality of bit lines BL1 provided on the laminate 100.

[0026] The substrate 10 is, for example, a semiconductor substrate made of P-type silicon (Si) containing P-type impurities such as boron (B). On the surface of the substrate 10, for example, a P-type well region containing P-type impurities is provided. However, it is not limited thereto, a polysilicon layer may be formed between the substrate 10 and the laminate 100, and after the memory chip C1 and the CMOS chip C2 are bonded, the substrate 10 may be peeled off.

[0027] The laminate 100 includes a lower laminate T1 disposed on the substrate 10, a middle laminate T2 disposed on the side opposite to the substrate 10 of the lower laminate T1, and an upper laminate T3 disposed on the side opposite to the lower laminate T1 of the middle laminate T2 (when the lower laminate T1, the middle laminate T2, and the upper laminate T3 are not distinguished, it is referred to as the laminate 100).

[0028] The laminate 100 has a plurality of word lines WL1 laminated on the substrate 10. The plurality of word lines WL1 are periodically laminated in a direction (lamination direction) perpendicular to the main surface of the substrate 10 via a plurality of insulating layers 40. Each word line WL1 is a single layer. That is, when observing the cross-sectional shape of one word line WL1, a single material may be continuous in the film thickness direction (Z direction) of the word line WL1. Also, there may be no interface inside one word line WL1. The material of the word line WL1 may be, for example, tungsten.

[0029] An insulating layer 40 is formed between adjacent word lines WL1 in the stacking direction. The plurality of word lines WL1 and the plurality of insulating layers 40 are alternately arranged. An insulating layer 40 is also formed between the substrate 10 and the lowermost word line WL1. An insulating layer 41 is disposed at the boundary between the lower stacked body T1 and the middle stacked body T2. The film thickness of the insulating layer 41 disposed at the boundary between the lower stacked body T1 and the middle stacked body T2 in the stacking direction may be larger than the film thickness of the insulating layer 40 between other adjacent word lines WL1 in the stacking direction. An insulating layer 42 is disposed at the boundary between the middle stacked body T2 and the upper stacked body T3. The film thickness of the insulating layer 42 disposed at the boundary between the middle stacked body T2 and the upper stacked body T3 in the stacking direction may be larger than the film thickness of the insulating layer 40 between other adjacent word lines WL1 in the stacking direction. However, it is not limited thereto, and the film thickness of the insulating layer 41 and the insulating layer 42 in the stacking direction may be the same as the film thickness of the insulating layer 40 between other adjacent word lines WL1 in the stacking direction.

[0030] The adjacent word lines WL1 in the stacking direction only need to be insulated from each other, and the materials of the insulating layer 40, the insulating layer 41, and the insulating layer 42 may be, for example, silicon oxides such as silicon dioxide (SiO2) and TEOS (Tetra Ethyl Ortho Silicate). The insulating layer 40 is deposited, for example, using a CVD (Chemical Vapor Deposition) apparatus.

[0031] In the stacked body 100, a plurality of word lines WL1 insulated from each other, and slits ST and MH common to the plurality of word lines WL1 are formed. The slits ST and MH extend in the stacking direction (Z direction) and reach the substrate 10 through the stacked body 100. The slit ST extends in the X direction and separates the stacked body 100 into a plurality of blocks BLK in the Y direction. Although details will be described later, a columnar body portion CL1 is formed in the opening MH (see FIG. 3).

[0032] The columnar body portion CL1 is formed as a cylinder extending in the stacking direction within the laminate 100. The plurality of columnar body portions CL1 are, for example, arranged in a staggered pattern. Alternatively, the plurality of columnar body portions CL1 may be arranged in a square lattice along the X and Y directions.

[0033] Furthermore, as shown in FIG. 1, the diameter of the columnar portion CL1 (the diameter in the X or Y direction) is formed to taper so as to become narrower as it goes toward the substrate side in the stacking direction (Z direction) in each of the lower laminate T1, the middle laminate T2, and the upper laminate T3.

[0034] The plurality of bit lines BL1 are separated from each other in the X direction, and each bit line BL1 extends in the Y direction.

[0035] The upper end of the semiconductor layer 20 (see FIG. 3) of the columnar body portion CL1 described later is connected to the bit line BL1 via the via contact VY1. A plurality of columnar body portions CL1, each selected one by one from the respective blocks BLK separated in the Y direction by the slit ST, are connected to a common single bit line BL1.

[0036] Note that an insulating layer is formed in the slit ST, and an insulating layer is formed on the laminate 100. However, for the sake of convenience of explanation, these insulating layers are omitted in FIG. 1.

[0037] [Configuration of Memory Cell] The configuration of the memory cell according to the present embodiment will be described with reference to FIG. 3. FIG. 3 is a cross-sectional view showing the configuration of the memory cell according to the present embodiment. FIG. 3 is an enlarged cross-sectional view of the columnar body portion CL1 in FIG. 2.

[0038] As shown in FIG. 3, the columnar body portion CL1 is a structure having a memory layer 30, a semiconductor layer 20, and an insulating core layer 50. The semiconductor layer 20 extends continuously in the stacking direction (Z direction) within the stacked body 100. The material of the semiconductor layer 20 includes, for example, amorphous or polycrystalline silicon. The core layer 50 is provided inside the cylindrical semiconductor layer 20. The material of the core layer 50 includes, for example, silicon oxide. The memory layer 30 is provided between the word line WL1 and the semiconductor layer 20. The memory layer 30 surrounds the semiconductor layer 20 from the outer peripheral side of the semiconductor layer 20.

[0039] The memory layer 30 has a tunnel insulating layer 31, a charge storage layer 32, and a block insulating layer 33 (when not distinguishing between the tunnel insulating layer 31, the charge storage layer 32, and the block insulating layer 33, it is referred to as the memory layer 30). The block insulating layer 33, the charge storage layer 32, and the tunnel insulating layer 31 extend continuously in the stacking direction of the stacked body 100 together with the semiconductor layer 20. Between the word line WL1 and the semiconductor layer 20, the block insulating layer 33, the charge storage layer 32, and the tunnel insulating layer 31 are provided in this order from the word line WL1 side. The tunnel insulating layer 31 is in contact with the semiconductor layer 20. The block insulating layer 33 is in contact with the word line WL1. The charge storage layer 32 is provided between the block insulating layer 33 and the tunnel insulating layer 31.

[0040] The semiconductor layer 20, the memory layer 30, and the word line WL1 constitute a memory cell MC. In FIG. 3, one memory cell MC is schematically represented by a broken line. The memory cell MC has a vertical transistor structure in which the word line WL1 surrounds the periphery of the semiconductor layer 20 via the memory layer 30.

[0041] In the memory cell MC having the vertical transistor structure, the semiconductor layer 20 functions as a channel, and the word line WL1 functions as a control gate of the memory cell. The charge storage layer 32 functions as a data layer that stores charges injected from the semiconductor layer 20.

[0042] As described above, the plurality of memory cells MC are arranged in the stacking direction of the plurality of word lines WL1, and the plurality of word lines WL1 are each connected to the plurality of memory cells MC. The word line WL1 near the block insulating layer 33 functions as a control gate. By controlling the voltage applied to the word line WL1 connected to the memory cell MC, writing or erasing to the memory cell MC can be controlled.

[0043] The semiconductor memory device of this embodiment is a non-volatile semiconductor device that can electrically and freely write or erase data to the memory cell MC and can retain the content even when the power is turned off.

[0044] The memory cell MC is, for example, a charge trap type memory cell. The charge storage layer 32 has a large number of trap sites for capturing charges in the insulating layer. The material of the charge storage layer 32 includes, for example, silicon nitride.

[0045] The tunnel insulating layer 31 serves as a potential barrier when charges are injected from the semiconductor layer 20 into the charge storage layer 32 or when the charges accumulated in the charge storage layer 32 diffuse in the direction of the semiconductor layer 20. The material of the tunnel insulating layer 31 includes, for example, silicon oxide.

[0046] The block insulating layer 33 prevents the charges accumulated in the charge storage layer 32 from diffusing to the word line WL1. The material of the block insulating layer 33 includes, for example, silicon oxide.

[0047] As shown in FIG. 2, a source side selection transistor STS is provided in the lower layer of the stacked body 100. A drain side selection transistor STD is provided in the upper layer of the stacked body 100. For example, the lowermost word line WL1 functions as the control gate of the source side selection transistor STS. For example, the uppermost word line WL1 functions as the control gate of the drain side selection transistor STD. A plurality of memory cells MC are provided between the source side selection transistor STS and the drain side selection transistor STD.

[0048] Between the drain-side selection transistor STD and the source-side selection transistor STS, a plurality of memory cells MC are provided. These plurality of memory cells MC, the drain-side selection transistor STD, and the source-side selection transistor STS are connected in series through the semiconductor layer 20 to form one memory string. This memory string is, for example, staggeredly arranged in a plane direction parallel to the X-Y plane, and the plurality of memory cells MC are three-dimensionally provided in the X direction, Y direction, and Z direction.

[0049] [Configuration of the connection region] The configuration of the connection region according to this embodiment will be described with reference to FIGS. 4 and 5. FIG. 4 is a perspective view showing an outline of the connection region 10s of a certain block BLK. FIG. 5 is an enlarged perspective view showing an outline of the connection region 10s of a certain block BLK. Note that FIGS. 4 and 5 show the memory chip C1 upside down with respect to FIG. 1. As shown in FIG. 4, the staircase region SSA of the connection region 10s is an opening region in which the word line WL3 is formed in a staircase shape. As shown in FIG. 5, in the staircase region SSA, a terrace region TRC is provided to connect a plurality of contact plugs CC to each of the plurality of word lines WL3. In the terrace region, the plurality of word lines WL3 are each exposed from the upper-stage (CMOS chip C2 side) word line WL3. Note that a holding member HR is formed in the staircase region SSA, and an insulator 43 is formed above (the opening region) the staircase region SSA. However, for the sake of convenience of explanation, these are omitted in FIG. 4.

[0050] The bridge portion WLB is composed of a part of the plurality of word lines WL3, extends in the X direction (the extending direction of the slit ST), and electrically connects the word line WL1 of the memory cell array 10m_1 and the word line WL2 of the memory cell array 10m_2 for each word line layer WL. Therefore, in a certain word line layer WL of the bridge portion WLB, the word lines WL1 to WL3 are electrically connected across the opening region.

[0051] The bridge portion WLB is provided adjacent to the staircase region SSA in the connection region 10s in the Y direction (substantially perpendicular to the extending direction (X direction) of the slit ST). In the Y direction, it is formed in a stepped shape with a steeper slope than the staircase region SSA, while in the X direction, it is not formed in a stepped shape.

[0052] [Configuration of the bridge portion] The configuration of the bridge portion according to the present embodiment will be described with reference to FIGS. 6, 7A, and 7B. FIG. 6 is a perspective view showing a configuration example of word lines WL1 to WL3. FIG. 7A is an enlarged top view showing a part of the connection region (region A in FIG. 4). FIG. 7B is an enlarged cross-sectional view showing a part of the connection region (cross-section B - B' in FIG. 4). In FIG. 6, for the sake of convenience, three word line layers are respectively shown for the lower laminate T1, the middle laminate T2, and the upper laminate T3, but the word lines may be four or more layers. Also, in the present embodiment, the laminate group is divided into three, but it may be two or less, or four or more. As shown in FIGS. 7A and 7B, in the staircase region SSA, a holding member HR penetrating the laminate 100 and an insulator 43 embedding the upper part of the staircase region SSA are arranged.

[0053] The bridge portion WLB is arranged between the slit ST and the staircase region SSA. Further, as shown in FIG. 7A, the width of the slit ST in the Y direction (substantially perpendicular to the extending direction (X direction) of the slit ST) is formed to taper so as to become narrower as it goes toward the substrate side in the stacking direction (Z direction) in the laminate 100.

[0054] In the word line layer of the lower laminate T1 that is relatively separated from the CMOS chip C2, the distance between the word line WL3 and the word lines WL1 and WL2 is relatively narrow, and the length of the bridge portion WLB in the X direction (the connection direction between the word line WL3 and the word lines WL1 and WL2) is short. On the other hand, in the word line layer of the upper laminate T3 that is relatively close to the CMOS chip C2, the distance between the word line WL3 and the word lines WL1 and WL2 is relatively wide, and the length of the bridge portion WLB in the X direction is long. In this embodiment, the shorter the length of the bridge portion WLB in the X direction is in the word line layer of the lower laminate T1 that is farther from the switch SW etc. of the CMOS chip C2. The closer the word line layer of the upper laminate T3 is to the switch SW etc. of the CMOS chip C2, the longer the length of the bridge portion WLB in the X direction becomes. That is, the length of the bridge portion WLB in the X direction is longer in the middle laminate T2 than in the lower laminate T1, and longer in the upper laminate T3 than in the middle laminate T2.

[0055] The width of the bridge portion WLB of the present embodiment in the Y direction (the direction perpendicular to the connection direction between the word line WL3 and the word lines WL1 and WL2) is different between the middle laminate T2 and the upper laminate T3. The width W3 of the bridge portion WLB of the uppermost layer of the upper laminate T3 in the Y direction is wider than the width W2 of the bridge portion WLB of the uppermost layer of the middle laminate T2 in the Y direction. With respect to 100% of the width of the bridge portion WLB of the uppermost layer of the upper laminate T3 in the Y direction, the width of the bridge portion WLB of the uppermost layer of the middle laminate T2 in the Y direction may be in the range of 40% or more and 80% or less. Here, the uppermost layer bridge portion WLB refers to the bridge portion WLB of the uppermost word line layer WL among the word line layers WL that include the bridge portion WLB (not metal-bridged MB) in each of the middle laminate T2 and the upper laminate T3.

[0056] Since the width W3 in the Y direction of the bridge portion WLB of the upper laminate T3 is wider than the width W2 in the Y direction of the bridge portion WLB of the middle laminate T2, the length in the X direction of the bridge portion WLB of the upper laminate T3 is longer than the length in the X direction of the bridge portion WLB of the middle laminate T2, thereby suppressing an increase in the resistance of the bridge portion WLB of the upper laminate T3. By suppressing an increase in the resistance of the bridge portion WLB, the read and program operation speeds of the semiconductor memory device 1 can be improved. Since the width W2 in the Y direction of the bridge portion WLB of the middle laminate T2 is narrower than the width W3 in the Y direction of the bridge portion WLB of the upper laminate T3, a space on the staircase region SSA can be secured, and the embedding property of the insulator 43 can be improved. By improving the embedding property of the insulator 43, the occurrence of cracks in a heat treatment process or the like can be suppressed, and the reliability and manufacturing yield of the semiconductor memory device 1 can be improved.

[0057] The width in the Y direction (the direction perpendicular to the connection direction between the word line WL3 and the word lines WL1 and WL2) of the bridge portion WLB according to the present embodiment is different between the middle laminate T2 and the lower laminate T1. The width W2 in the Y direction of the topmost bridge portion WLB of the middle laminate T2 is narrower than the width W1 in the Y direction of the topmost bridge portion WLB of the lower laminate T1. The width in the Y direction of the topmost bridge portion WLB of the middle laminate T2 may be in the range of 40% or more and 80% or less with respect to 100% of the width in the Y direction of the topmost bridge portion WLB of the lower laminate T1. Here, the topmost bridge portion WLB refers to the bridge portion WLB of the topmost word line layer WL among the word line layers WL including the bridge portion WLB (not metal-bridged MB) in each of the lower laminate T1 and the middle laminate T2.

[0058] Since the width W1 in the Y direction of the bridge portion WLB of the lower laminate T1 is wider than the width W2 in the Y direction of the bridge portion WLB of the middle laminate T2, the resistance of the bridge portion WLB of the lower laminate T1 can be suppressed. By suppressing the resistance of the bridge portion WLB, the read and program operation speeds of the semiconductor memory device 1 can be further improved. Since the width W2 in the Y direction of the bridge portion WLB of the middle laminate T2 is narrower than the width W1 in the Y direction of the bridge portion WLB of the lower laminate T1, a space on the staircase region SSA can be secured, and the embedding property of the insulator 43 can be improved. By improving the embedding property of the insulator 43, the occurrence of cracks in the heat treatment process or the like can be suppressed, and the reliability and manufacturing yield of the semiconductor memory device 1 can be improved.

[0059] The width in the Y direction (the direction perpendicular to the connection direction between the word line WL3 and the word lines WL1 and WL2) of the bridge portion WLB according to the present embodiment may be different between the upper laminate T3 and the lower laminate T1. The width W3 in the Y direction of the topmost bridge portion WLB of the upper laminate T3 may be wider than the width W1 in the Y direction of the topmost bridge portion WLB of the lower laminate T1. The width in the Y direction of the topmost bridge portion WLB of the lower laminate T1 may be in the range of 50% or more and less than 100% with respect to 100% of the width in the Y direction of the topmost bridge portion WLB of the upper laminate T3. Here, the topmost bridge portion WLB refers to the bridge portion WLB of the topmost word line layer WL among the word line layers WL including the bridge portion WLB (not metal-bridged MB) in each of the lower laminate T1 and the upper laminate T3.

[0060] Since the width W3 in the Y direction of the bridge portion WLB of the upper laminate T3 is wider than the width W1 in the Y direction of the bridge portion WLB of the lower laminate T1, the length in the X direction of the bridge portion WLB of the upper laminate T3 is longer than the length in the X direction of the bridge portion WLB of the lower laminate T1, thereby suppressing an increase in the resistance of the bridge portion WLB of the upper laminate T3. By suppressing an increase in the resistance of the bridge portion WLB, the read and program operation speeds of the semiconductor memory device 1 can be improved. Since the width W1 in the Y direction of the bridge portion WLB of the lower laminate T1 is narrower than the width W3 in the Y direction of the bridge portion WLB of the upper laminate T3, a space on the staircase region SSA can be secured, and the embedding property of the insulator 43 can be improved. By improving the embedding property of the insulator 43, the occurrence of cracks in a heat treatment process or the like can be suppressed, and the reliability and manufacturing yield of the semiconductor memory device 1 can be improved.

[0061] Also, the width in the Y direction of the bridge portion WLB is wider in the lower layer farther from the CMOS chip C2 and narrower as it approaches the CMOS chip C2 in each of the lower laminate T1, the middle laminate T2, and the upper laminate T3. In the top word line layer of each of the lower laminate T1, the middle laminate T2, and the upper laminate T3, the bridge portion WLB is absent. This is because when the word line WL3 is processed in a stepped shape, the etching process and the photoresist slimming process are repeatedly executed. In the lower laminate T1, the middle laminate T2, and the upper laminate T3, the width of the bridge portion WLB becomes narrower from the lower layer to the upper layer, and the bridge portion WLB is absent in the top layer. Incidentally, the photoresist is reapplied for each of the lower laminate T1, the middle laminate T2, and the upper laminate T3, and the word line WL3 is processed for each of the lower laminate T1, the middle laminate T2, and the upper laminate T3. Therefore, the bridge portion WLB in the top layer of each of the lower laminate T1, the middle laminate T2, and the upper laminate T3 is removed. In the top word line layer, the word line WL3 is in an electrically floating state. Also, the top word lines WL1 and WL2 are not connected by the bridge portion WLB but are electrically connected via the metal bridge MB.

[0062] In this embodiment, in the top word line layer of each of the lower laminate T1, the middle laminate T2, and the upper laminate T3, a metal bridge MB electrically connects the word line WL1 and the word line WL2 instead of the bridge portion WLB. However, in a plurality of word line layers starting from the top layer of each of the lower laminate T1, the middle laminate T2, and the upper laminate T3, a metal bridge MB may electrically connect the word line WL1 and the word line WL2 instead of the bridge portion WLB.

Explanation of Reference Numerals

[0063] 1 Semiconductor memory device, 10 Substrate, 10m Memory cell array, 10s Connection region, 20 Semiconductor layer, 30 Memory layer, 40 Insulating layer, 50 Core layer, 100 Laminate

Claims

1. A bit line, which is disposed above the bit line, and in which a plurality of first insulating layers and a plurality of first conductive layers are alternately laminated in a first direction, and at the center in a second direction intersecting the first direction, a first stepped region in which ends of the plurality of first conductive layers are stepped in the second direction, and a first bridge region provided adjacent to the first stepped region in a third direction intersecting the first direction and the second direction, and for each of the plurality of first conductive layers, electrically connecting memory cell regions on both sides in the second direction with the first stepped region therebetween; a first laminate having a second laminate disposed above the first laminate, in which a plurality of second insulating layers and a plurality of second conductive layers are alternately laminated in the first direction, and at the center in the second direction, a second stepped region in which ends of the plurality of second conductive layers are stepped in the second direction, and a second bridge region provided adjacent to the second stepped region in the third direction, and for each of the plurality of second conductive layers, electrically connecting memory cell regions on both sides in the second direction with the second stepped region therebetween; provided with a semiconductor memory device, wherein a width in the third direction of the first bridge region for the lowermost layer among the plurality of first conductive layers is larger than a width in the third direction of the second bridge region for the lowermost layer among the plurality of second conductive layers.

2. The semiconductor memory device according to claim 1, wherein a width in the third direction of the second bridge region for the lowermost layer among the plurality of second conductive layers is in a range of 40% or more and 80% or less with respect to 100% of the width in the third direction of the first bridge region for the lowermost layer among the plurality of first conductive layers.

3. further comprising a third laminate disposed above the second laminate, in which a plurality of third insulating layers and a plurality of third conductive layers are alternately laminated in the first direction, and at the center in the second direction, a third stepped region in which ends of the plurality of third conductive layers are stepped in the second direction, and a third bridge region provided adjacent to the third stepped region in the third direction, and for each of the plurality of third conductive layers, electrically connecting memory cell regions on both sides in the second direction with the third stepped region therebetween. The semiconductor memory device according to claim 1, wherein the width in the third direction of the third bridge region for the lowermost layer among the plurality of third conductive layers is larger than the width in the third direction of the second bridge region for the lowermost layer among the plurality of second conductive layers.

4. The semiconductor memory device according to claim 3, wherein the width in the third direction of the second bridge region for the lowermost layer among the plurality of second conductive layers is in the range of 40% or more and 80% or less with respect to 100% of the width in the third direction of the third bridge region for the lowermost layer among the plurality of third conductive layers.

5. The semiconductor memory device according to claim 3, wherein the width in the third direction of the first bridge region for the lowermost layer among the plurality of first conductive layers is larger than the width in the third direction of the third bridge region for the lowermost layer among the plurality of third conductive layers.

6. The semiconductor memory device according to claim 5, wherein the width in the third direction of the third bridge region for the lowermost layer among the plurality of third conductive layers is in the range of 50% or more and less than 100% with respect to 100% of the width in the third direction of the first bridge region for the lowermost layer among the plurality of first conductive layers.

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