Semiconductor device

Abstract

To provide a semiconductor device having good electrical characteristics.SOLUTION: A semiconductor device includes a conductor, a first insulator in contact with a side surface of the conductor, a second insulator in contact with the top surface of the conductor and the top surface of the first insulator, and an oxide on the second insulator, and the oxide has a region overlapping the conductor via the second insulator, the maximum height (Rz) of the roughness curve on the top surface of the conductor is 6.0 nm or less, and the region contains crystals whose c-axes are oriented in the normal direction to the top surface of the conductor.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device and a manufacturing method of the semiconductor device. One aspect of the present invention relates to a semiconductor wafer, a module, and an electronic device.

[0002] In this specification and the like, a semiconductor device refers to a device that can function by utilizing semiconductor characteristics. This refers to semiconductor devices in general, including semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and memory devices. The device is one aspect of a semiconductor device. device, lighting device, electro-optical device, power storage device, memory device, semiconductor circuit, imaging device, and The sub-devices and the like may be said to have semiconductor devices.

[0003] Note that one embodiment of the present invention is not limited to the above technical fields. One aspect of the present invention relates to an object, a method, or a manufacturing method. , process, machine, manufacture, or composition of matter (This is related to the above.) [Background technology]

[0004] Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors. However, oxide semiconductors are attracting attention as other materials. For example, not only oxides of single metals such as indium oxide and zinc oxide, but also oxides of multi-component metals Among the oxides of multi-component metals, In-Ga-Zn oxide (hereinafter referred to as In-Ga-Zn oxide) is particularly Research into IGZO (Inorganic Glycerol, also known as IGZO) is currently being actively conducted.

[0005] Research on IGZO has revealed that, among oxide semiconductors, it is neither single crystal nor amorphous. AAC (c-axis aligned crystalline) structure and nc(n A crystalline structure was found (see Non-Patent Documents 1 to 3). In Non-Patent Documents 1 and 2, oxide semiconductors having a CAAC structure are used. Furthermore, a technique for fabricating a transistor using a CAAC structure and an nc structure has also been disclosed. Even oxide semiconductors with lower crystallinity than those described above have minute crystals, as reported in Non-Patent Document 4 and and Non-Patent Document 5.

[0006] Furthermore, transistors using IGZO as the active layer have extremely low off-state current (non- See Patent Document 6.) LSIs and displays that utilize these properties have been reported ( See Non-Patent Document 7 and Non-Patent Document 8. [Prior art documents] [Non-patent literature]

[0007] [Non-Patent Document 1] S. Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, p.183-186 [Non-patent document 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, Number 4S, p.04ED18-1-04ED18-10 [Non-patent document 3] S. Ito et al., “The Proceedings of AM-FPD'13 Digest of Technical Papers”, 2013, p.151-154 [Non-Patent Document 4] S. Yamazaki et al., “ECS Journal of Solid State Science and Technology”, 2014, volume 3, issue 9, p.Q3012-Q3022 [Non-Patent Document 5] S. Yamazaki, “ECS Transactions”,2014, volume 64, issue 10, p.155-164 [Non-Patent Document 6] K. Kato et al., “Japanese Journal of Applied Physics”, 2012, volume 51, p.021201-1-021201-7 [Non-Patent Document 7] S. Matsuda et al., “2015 Symposium on VLSI Technology Digest of Technical Papers”, 2015, p.T216-T217 [Non-Patent Document 8] S. Amano et al., “SID Symposium Digest of Technical Papers”, 2010, volume 41, issue 1, p.626-629 [Summary of the Invention] [Problems to be Solved by the Invention]

[0008] One aspect of the present invention is to provide a semiconductor device having a large on-current as one of the problems. Another aspect of the present invention is to provide a semiconductor device having high frequency characteristics as one of the problems. Another aspect of the present invention is to provide a semiconductor device with good reliability as one of the problems. Another aspect of the present invention is to provide a semiconductor device capable of miniaturization or high integration as one of the problems. Another aspect of the present invention is to provide a semiconductor having good electrical characteristics One of the problems is to provide a device. Also, one aspect of the present invention is a semiconductor device with high productivity One of the problems is to provide a device.

[0009] Also, one aspect of the present invention is to provide a semiconductor device capable of retaining data for a long period of time One of the problems is to provide a semiconductor device with a high information writing speed. Also, one aspect of the present invention is a semiconductor device with a high degree of design freedom. Also, one aspect of the present invention is to provide a semiconductor device capable of suppressing power consumption One of the problems is to provide a semiconductor device capable of suppressing power consumption. Also, one aspect of the present invention is to provide a semiconductor device capable of suppressing power consumption. Also, one aspect of the present invention is to provide a novel semiconductor device.

[0010] Note that the description of these problems does not prevent the existence of other problems. Note that one aspect of the present invention is not required to solve all of these problems. Note that other problems will become apparent from the descriptions in the specification, drawings, claims, etc., and it is possible to extract these other problems from the descriptions in the specification, drawings, claims, etc. drawings, claims, etc.

Means for Solving the Problems

[0011] One aspect of the present invention includes a conductor, a first insulator in contact with the side surface of the conductor, the upper surface of the conductor, a second insulator in contact with the upper surface of the first insulator, and an oxide on the second insulator, and the oxide has a region that overlaps the conductor via the second insulator, and on the upper surface of the conductor the maximum height (Rz) of the roughness curve is 6.0 nm or less, and the region contains crystals, and the c-axis of the crystals is oriented in the normal direction of the upper surface of the conductor. is a semiconductor device.

[0012] In the above, the average length (RSm) of the roughness curve elements on the upper surface of the conductor is preferably less than 60 nm.

[0013] Also, one aspect of the present invention is a semiconductor device including a conductor, a first insulator in contact with a side surface of the conductor, a second insulator in contact with an upper surface of the conductor and an upper surface of the first insulator, and an oxide on the second insulator, wherein the oxide has a region overlapping the conductor via the second insulator, the average length (RSm) of the roughness curve elements on the upper surface of the conductor is 60 nm or more, the region contains crystals, and the c-axis of the crystals is oriented in the normal direction of the upper surface of the conductor. In the above, the maximum height (Rz) of the roughness curve on the upper surface of the conductor is preferably greater than 6.0 nm.

[0014]

[0015] Also, one aspect of the present invention is a semiconductor device including a conductor, a first insulator in contact with a side surface of the conductor, a second insulator in contact with an upper surface of the conductor and an upper surface of the first insulator, and an oxide on the second insulator, wherein the oxide has a region overlapping the conductor via the second insulator, the arithmetic mean height (Ra) of the roughness curve on the upper surface of the conductor is 0.5 nm or less, the region contains crystals, and the c-axis of the crystals is oriented in the normal direction of the upper surface of the conductor.

[0016] Also, in the above, the oxide preferably contains indium (In), an element M (where M is aluminum ( Al), gallium (Ga), yttrium (Y), or tin (Sn)), and zinc (Zn).

Advantages of the Invention

[0017] ​​​​​​​​​According to one aspect of the present invention, a semiconductor device with a large on-current can be provided. Also, According to one aspect of the present invention, a semiconductor device having high frequency characteristics can be provided. Also According to one aspect of the present invention, a semiconductor device with good reliability can be provided. Also, According to one aspect of the present invention, a semiconductor device capable of miniaturization or high integration can be provided . Also, according to one aspect of the present invention, a semiconductor device having good electrical characteristics can be provided . Also, according to one aspect of the present invention, a highly productive semiconductor device can be provided .

[0018] Also, a semiconductor device capable of retaining data for a long period can be provided. Also , a semiconductor device with a high information writing speed can be provided. Also, a semiconductor device with a high degree of design freedom can be provided. Also, a semiconductor device capable of suppressing power consumption can be provided . Also, a novel semiconductor device can be provided.

[0019] Note that the description of these effects does not prevent the existence of other effects. Note that one aspect of the present invention does not necessarily have all of these effects. Note that other effects will be apparent from the description in the specification , drawings, claims, etc., and it is possible to extract these other effects from the description in the specification, drawings, claims , etc.

Brief Description of the Drawings

[0020]

Figure 1

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Figure 13

[0021] Hereinafter, embodiments will be described with reference to the drawings. It is understood that the present invention may be practiced in various different ways without departing from its spirit and scope. It will be readily apparent to those skilled in the art that various changes in form and details may be made. Therefore, the present invention should not be construed as being limited to the description of the following embodiments.

[0022] In the drawings, the size, thickness of layers, or areas may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. The examples are shown in the drawings as a schematic illustration, and are not limited to the shapes or values shown in the drawings. For example, In the actual manufacturing process, layers and resist masks are damaged by etching and other processes. However, in order to make it easier to understand, this may not be reflected in the diagram. In the drawings, the same parts or parts having similar functions are designated by the same reference numerals between different drawings. In addition, when referring to similar functions, In such cases, the hatch pattern may be the same and no particular reference numeral may be assigned.

[0023] In addition, the invention can be easily understood, especially in top views (also called "plan views") and perspective views. In order to simplify the description, some components may be omitted. The information may be omitted.

[0024] In addition, in this specification, ordinal numbers such as 1st, 2nd, etc. are used for convenience. It does not indicate the order of processes or stacking. For example, "first" may be changed to "second" The term "the" or "third" can be used interchangeably in the description. The ordinal numbers listed may not match the ordinal numbers used to identify an aspect of the present invention. There may be cases where this is the case.

[0025] In addition, in this specification, terms indicating arrangement such as "above" and "below" refer to the relationship between components. The positional relationship is used for convenience in describing the same with reference to the drawings. The relationship changes depending on the direction in which each component is depicted. The terms are not limited to those described above, and can be rephrased appropriately depending on the situation.

[0026] For example, in this specification, it is explicitly stated that X and Y are connected. In the case where X and Y are electrically connected, or where X and Y are functionally connected, or where X and Y are directly connected, are those disclosed in this specification and the like. That is to say, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or the text. Those other than the connection relationship shown in the figure or the text are also considered to be disclosed in the figure or the text. Let it be so.

[0027] Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0028] Also, the functions of the source and the drain may be interchanged when transistors of different polarities are adopted, or when the direction of the current changes during the circuit operation. For this reason, in this specification and the like, the terms of the source and the drain may be used interchangeably in some cases. Let it be so.

[0029] Note that in this specification and the like, depending on the structure of the transistor, the channel width in the region where the channel is actually formed (hereinafter also referred to as the "effective channel width"), and the channel width shown in the top view of the transistor (hereinafter also referred to as the "apparent channel width")[[]] [[[]]], may be different. For example, when the gate electrode covers the side surface of the semiconductor, the effective channel width becomes larger than the apparent channel width, and there may be a case where the influence cannot be ignored. For example, in a fine transistor where the gate electrode covers the side surface of the semiconductor, the ratio of the channel formation region formed on the side surface of the semiconductor may be large. In that case, the effective channel width is larger than the apparent channel width. [[[]]] [[[]]] [[[]]] [[[]]] [[[]]]

[0030] In such a case, it may be difficult to estimate the effective channel width by measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, when the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width.

[0031] In this specification, when simply described as the channel width, it may refer to the apparent channel width. Or, in this specification, when simply described as the channel width, it may refer to the effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, etc. can be determined by analyzing a cross-sectional TEM image or the like.

[0032] Note that the semiconductor impurities refer to, for example, elements other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic% can be said to be an impurity. When impurities are included, for example, the defect level density of the semiconductor may increase or the crystallinity may decrease. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, transition metals other than the main components of the oxide semiconductor, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. In the case of an oxide semiconductor, water may also function as an impurity. Also, in the case of an oxide semiconductor, oxygen deficiency may be formed due to the incorporation of impurities, for example. When the semiconductor is silicon, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 1 elements excluding oxygen and hydrogen. There are Group 5 elements and the like.

[0033] In addition, in this specification and the like, silicon oxynitride refers to a substance in which the oxygen content is higher than the nitrogen content in terms of its composition. Also, silicon nitride oxide refers to a substance in which the nitrogen content is higher than the oxygen content in terms of its composition.

[0034] In addition, in this specification and the like, the term "insulator" can be rephrased as an insulating film or an insulating layer. Also, the term "conductor" can be rephrased as a conductive film or a conductive layer. Further, the term "semiconductor" can be rephrased as a semiconductor film or a semiconductor layer.

[0035] In addition, in this specification and the like, "parallel" means a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Also, "substantially parallel" means a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Further, "perpendicular" means a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Also, "substantially perpendicular" means a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0036] In this specification, a barrier film refers to a film having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen. When the barrier film has conductivity, it may be called a conductive barrier film.

[0037] In this specification and the like, metal oxide refers to an oxide of a metal in a broad sense. Metal oxides include oxide insulators, oxide conductors (including transparent oxide conductors), ​ .), oxide semiconductors (also simply referred to as Oxide Semiconductor or OS) .) and the like. For example, when a metal oxide is used for the semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when described as an OS transistor , it can be paraphrased as a transistor having an oxide or an oxide semiconductor.

[0038] Also, in this specification and the like, normally off means that when no potential is applied to the gate or when the gate is given a ground potential, the drain current per 1 μm of channel width flowing through the transistor is 1×10 -20 A or less at room temperature, 1×10 -18 A or less at 85 °C , or 1×10 -16 A or less at 125 °C.

[0039] (Embodiment 1) In this embodiment, a film typified by a metal oxide according to one aspect of the present invention will be described. Note that in this specification, when the film according to one aspect of the present invention has a semiconductor function, it can be used in a region where a channel of a transistor is formed (hereinafter also referred to as a channel formation region). Hereinafter, the film according to one aspect of the present invention will be described with reference to FIG. 1.

[0040] For the transistor, it is preferable to use a metal oxide (hereinafter also referred to as an oxide semiconductor) that functions as an oxide semiconductor in the channel formation region. A transistor using a metal oxide in the channel formation region can provide a semiconductor device with extremely low leakage current in the non-conducting state, and thus low power consumption. In addition, the metal oxide can be formed into a film by using a sputtering method or the like. ​​Therefore, it can be used for a transistor that constitutes a highly integrated semiconductor device.

[0041] When metal oxide is used in the channel formation region of a transistor, it is necessary to use a metal oxide with high crystallinity. It is preferable to use a highly crystalline metal oxide for the channel formation region of a transistor. By using the crystal, the stability or reliability of the transistor can be improved. As a highly functional metal oxide, for example, CAAC-OS (c-axis aligned crystalline oxide semiconductor).

[0042] CAAC-OS has a c-axis orientation and multiple nanocrystals are connected in the ab-plane direction. Here, nanocrystals are those with a size of, for example, 1 nm or more. Small particles with periodic atomic arrangement in the region of 10 nm or less, especially in the region of 1 nm to 3 nm The nanocrystals in CAAC-OS are crystals with a layered structure. In the TEM image of a plane parallel to the c-axis, bright and dark stripes appear alternately in the c-axis direction. The image of the nanocrystals (also called lattice fringes) is observed. In the region, the lattice arrangement is changed between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement. In CAAC-OS, the direction of the However, it is difficult to identify clear grain boundaries.

[0043] By reducing the above distortion, the atomic arrangement can be improved even in the region where multiple nanocrystals are connected. In this specification, the entire structure in which multiple nanocrystals are connected may have periodicity. The region with periodic atomic arrangement is called Region A. The minimum size of Region A is nanocrystal. The size of the region A may be, for example, 30 nm. By increasing the size of the region A, the strain of the metal oxide can be reduced. The physical properties of metal oxides with reduced strain are stable. Therefore, the stability or reliability of transistors using metal oxides is improved. It can be improved.

[0044] In CAAC-OS, the region where multiple regions A are connected or the nanocrystal and the region Even in the region connected to region A, it is difficult to identify clear grain boundaries.

[0045] To increase the size of the region A, it is necessary to increase the crystallinity of the metal oxide. As a method for increasing the crystallinity of oxides, for example, the substrate temperature is increased when forming a metal oxide film. However, increasing the substrate temperature or increasing the flow rate of oxygen gas can Alternatively, by increasing the flow rate of oxygen gas, the metal oxide has a polycrystalline structure and forms grain boundaries. In addition, the crystallinity of the metal oxide is highly likely to be affected by the crystallinity of the film located under the metal oxide. Sensitive to flatness.

[0046] Therefore, it is preferable to increase the flatness of the film located below the metal oxide. By increasing the flatness, the normal direction of the upper surface of the film becomes almost uniform over a wide range. Therefore, the c-axes of the nanocrystals in the metal oxide are oriented in the normal direction, and the nanocrystals are easily aligned with each other. The metal oxide with reduced distortion and a large region A is formed. The normal direction is the direction in which the nanocrystal and the film overlap each other. It is the average direction of the normal vector to the upper surface of the film. "Oriented in the direction of the crystal grain" means that the angle between the c-axis of the nanocrystal and the normal direction is between -15 degrees and 15 degrees. This refers to the case where the angle is an angle.

[0047] In a transistor using a metal oxide for a channel formation region, The formation surface is the upper surface of an insulating film that functions as a gate insulator or an interlayer film, and The surface to be formed may be the top surface of a conductive film that functions as a gate electrode or a wiring. Examples of the conductive film include a tungsten film, a titanium nitride film, and a tantalum nitride film. The conductive film is formed by a sputtering method or the like. This is a film formation method in which particles emitted from the target are deposited. may be low.

[0048] The insulating film may be, for example, a silicon oxynitride film, an aluminum oxide film, or a halogen oxide film. The insulating film is formed by a CVD method, an ALD method, etc. The CVD and ALD methods are film formation methods in which a film is formed by a reaction on the surface of the workpiece. Therefore, the flatness of the insulating film is determined by the flatness of the conductive film on which the insulating film is formed. Sensitive to flatness.

[0049] From the above, the film located below the metal oxide is a conductive film and the conductive film In the case of a laminated structure of an insulating film on top, it is preferable to increase the flatness of the film located further downward. That is, in order to improve the flatness of the surface on which the metal oxide is formed, it is necessary to form a metal oxide film on the surface of the metal oxide. It is preferable to increase the flatness of the conductive film. The crystallinity of the metal oxide can be increased.

[0050] Hereinafter, the relationship between the size of region A of the metal oxide and the flatness of the film located below the metal oxide will be described. Here, the case where the film located below the metal oxide is a two-layer film will be shown. Here, the film located below the metal oxide is a two-layer film. will be shown.

[0051] FIGS. 1(A) to (D) are schematic views of the metal oxide and the film located below the metal oxide. In FIGS. 1(A) to (D), a film 51 is formed on a film 50, and an oxide film 52 is formed on the film 51. Further, the oxide film 52 has a plurality of regions 53. 2 is formed. Also, the oxide film 52 has a plurality of regions 53. In FIGS. 1(A) to (D), for example, the film 50 is a film that functions as a conductor, the film 51 is a film that functions as an insulator, the oxide film 52 is a metal oxide, and the region 53 is region A. Note that the films 50 and 51 may each have a laminated structure. In FIGS. 1(A) to (D), for example, the film 50 is a film that functions as a conductor, the film 51 is a film that functions as an insulator, the oxide film 52 is a metal oxide, and the region 53 is region A. Note that the films 50 and 51 may each have a laminated structure. 0 and the film 51 may each have a laminated structure.

[0052] Here, the region 53 of the oxide film 52 will be described. FIG. 1(E) is a schematic view of the region 53 of the oxide film 52. The region 53 has periodicity in the atomic arrangement. In particular, when the oxide film 52 is an In-M-Zn oxide, the region 53 has a layered crystal structure (also referred to as a layered structure) in which a layer containing indium and oxygen (hereinafter, In layer) and a layer containing element M, zinc, and oxygen (hereinafter, (M,Zn) layer) are laminated. Also, the normal direction of each layer is defined as the c-axis, and the plane formed by each layer is defined as the a-b plane. The region 53 has periodicity in the atomic arrangement. In particular, when the oxide film 52 is an In-M-Zn oxide, the region 53 has a layered crystal structure (also referred to as a layered structure) in which a layer containing indium and oxygen (hereinafter, In layer) and a layer containing element M, zinc, and oxygen (hereinafter, (M,Zn) layer) are laminated. Also, the normal direction of each layer is defined as the c-axis, and the plane formed by each layer is defined as the a-b plane. 52 is an In-M-Zn oxide, the region 53 has a layered crystal structure (also referred to as a layered structure) in which a layer containing indium and oxygen (hereinafter, In layer) and a layer containing element M, zinc, and oxygen (hereinafter, (M,Zn) layer) are laminated. Also, the normal direction of each layer is defined as the c-axis, and the plane formed by each layer is defined as the a-b plane. layer (hereinafter, In layer) and a layer containing element M, zinc, and oxygen (hereinafter, (M,Zn) layer) are laminated. Also, the normal direction of each layer is defined as the c-axis, and the plane formed by each layer is defined as the a-b plane. are laminated. Also, the normal direction of each layer is defined as the c-axis, and the plane formed by each layer is defined as the a-b plane.

[0053] The size of the region 53 in the a-b plane direction may be 30 nm depending on the film formation conditions of the oxide film 52 or the flatness of the film located below the oxide film 52. In FIG. 1, depending on the film formation conditions of the oxide film 52 or the flatness of the film located below the oxide film 52, the size may be 30 nm. Note that in FIG. 1, The size of region 53 in the c-axis direction is shown as the same size as the thickness of the oxide film 52, but this is not restrictive. Region 53 only needs to be formed at least in the channel formation region of the transistor. Therefore, the size of region 53 in the c-axis direction may be larger than the minimum size of the c-axis direction of the nanocrystal (for example, , 0.7 nm) and smaller than the thickness of the oxide film 52.

[0054] First, a method for evaluating the flatness of a film will be described. As a method for evaluating the flatness of a film, for example, a method of obtaining a roughness curve of the film and calculating roughness curve parameters can be mentioned. Here, the roughness curve is a contour curve obtained by blocking the long-wavelength component from the cross-sectional curve. The roughness curve pa rameters are obtained from the roughness curve. Note that the roughness curve parameters include the arithmetic mean height (Ra) of the roughness curve, the average length (RSm) of the roughness curve elements, the maximum height (Rz) of the roughness curve, etc. Note that the roughness curve parameters can be evaluated, for example, with an atomic force microscope (AFM: Atomic Force Microscope).

[0055] The arithmetic mean height (Ra) of the roughness curve is the average of the absolute values of the ordinate values Z(X) at the reference length. The smaller the arithmetic mean height (Ra) of the roughness curve, the higher the flatness of the film can be said. Note that the ordinate value Z(X) is the height of the roughness curve at an arbitrary position X.

[0056] Also, the average length (RSm) of the roughness curve elements is the average of the lengths ( Xs) of the contour curve elements at the reference length. The larger the average length (RSm) of the roughness curve elements, the higher the flatness of the film can be said.

[0057] Also, the maximum height (Rz) of the roughness curve is the maximum peak height Zp of the contour curve at the reference length and It is the sum with the maximum valley depth Zv. The smaller the maximum height (Rz) of the roughness curve, the higher the flatness of the film can be said to be. Note that the maximum height (Rz) of the roughness curve is sometimes referred to as the P-V value (Peak-to-Valley Roughness).

[0058] The above roughness curve parameters refer to JIS B 0601-2001 (ISO 4287- 1997), but are not limited to this. For example, the roughness curve parameters may be evaluated by performing image analysis of the TEM image. As an evaluation method by image analysis of the TEM image, for example, the contrast observed in the TEM image is regarded as the interface between layers, and the shape of the interface is assumed to be the roughness curve of the layer located below the interface. Then, from the assumed roughness curve, a parameter corresponding to the roughness curve parameter is calculated. Note that the reference length may be the length of the upper surface of the film 50 observed in the TEM image, or the length of the region where the film 50 and the oxide film 52 overlap. When using the said evaluation method, the maximum height (Rz) of the roughness curve may also be the sum of the maximum peak height and the maximum valley depth of the roughness curve assumed by the said evaluation method. Also, the average length (RSm) of the roughness curve elements may be the average of the length from the peak of the roughness curve assumed by the said evaluation method to the adjacent peak, or the average of the length from the valley to the adjacent valley.

[0059] Note that when the film located below the oxide film 52 has a function as a wiring of a transistor, the length in the short dimension direction in the shape of the film may be shorter than the reference length. In this case, by setting the direction of the reference length to the long dimension direction in the shape of the film, the

[0060] As described above, it is preferable that the size of the region 53 of the oxide film 52 is larger.

[0061] FIG. 1(A) is a schematic diagram when the film 50 is flat. When the film 50 is flat, the flatness of the film 51 is high, and the flatness of the oxide film 52 also tends to be high. At this time, a region 53 with a large size can be formed in the oxide film 52. Furthermore, different regions 53 are connected in the a-b plane direction.

[0062] To increase the size of the region 53, it is preferable that the average length (RSm) of the roughness curve elements of the film 50 located below the oxide film 52 is large. As the average length (RSm) of the roughness curve elements of the film 50, for example, 60 nm or more is preferable, and 80 nm or more

[0063] FIG. 1(B) is a schematic diagram when the average length (RSm) of the roughness curve elements of the film 50 is large. For example, when the average length (RSm) of the roughness curve elements of the film 50 is 60 nm or more, on the upper film surfaces of the film 50 and the film 51, the length from the convex portion to the concave portion (about half the length of RSm) is 3 0 nm or more, and the ratio of the area increases. The normal direction to the upper film surface of the region is substantially uniform. Therefore, when the upper film surface of the region is the surface on which the oxide film 52 is to be formed, the nanocrystals are easily connected with small strain, and a

[0064] region 53 with a large size can be formed in the oxide film 52. Also, to increase the size of the region 53, it is preferable that the maximum height (Rz) or the arithmetic mean height (Ra) of the roughness curve of the film 50 located below the oxide film 52 is small. As the maximum height (Rz) of the roughness curve of the film 50, for example, 10 nm or lessMore preferably, it is 4.0 nm or less, and even more preferably. Further, as the arithmetic mean height (Ra) of the roughness curve of the film 50, for example, 1.0 nm or less is preferable, 0.5 nm or less is more preferable ( , and 0.3 nm or less is even more preferable. ( (

[0065] ( (FIG. 1(C) is a schematic view when the maximum height (Rz) of the roughness curve of the film 50 is small. The film ( (50) By reducing the height (Rz) or the arithmetic mean height (Ra) of the roughness curve, different nanocrystals are connected with small strain at the convex or concave portions on the upper surface of the film 51 ( (, and a large-sized region 53 can be formed in the oxide film 52 ( (. ( (

[0066] ( (Note that if the average length (RSm) of the roughness curve elements of the film 50 is sufficiently large, even if the maximum height (Rz) or the arithmetic mean height (Ra) of the roughness curve of the film 50 is large, a large-sized region 5 ( (3 can be formed. For example, when the average length (RSm) of the roughness curve elements of the film 50 is 60 ( (nm or more, the maximum height (Rz) of the roughness curve of the film 50 is larger than 6.0 nm, and ( (further, the arithmetic mean height (Ra) of the roughness curve of the film 50 may be larger than 0.5 nm. ( (( (

[0067] ( (Further, if the height (Rz) or the arithmetic mean height (Ra) of the roughness curve of the film 50 is sufficiently small ( (, even if the average length (RSm) of the roughness curve elements of the film 50 is small, a large-sized region 53 can be ( (formed. For example, when the maximum height (Rz) of the roughness curve of the film 50 is 6.0 nm or less ( (, or the arithmetic mean height (Ra) of the roughness curve of the film 50 is 0.5 nm or less, the average length (RSm) of the roughness curve elements of the film 5 ( (0 may be less than 60 nm. ( (

[0068] ( (FIG. 1(D) shows that the average length (RSm) of the roughness curve elements of the film 50 is small, and the roughness curve of the film 50 ( It is a schematic diagram when the maximum height (Rz) or arithmetic mean height (Ra) of the line is large. At this time , the region where the normal direction with respect to the upper surface of the film 51 becomes substantially uniform becomes narrow, and the size of the region 53 is also presumed to become small. Further, in the region 54 on the convex or concave portion of the upper surface of the film 51 , since the strain becomes large, different nanocrystals are difficult to connect, and the crystallinity may be low .

[0069] As described above, by increasing the flatness of the film located below the metal oxide, nanocrystals can be easily connected to each other, and a region A with a large size can be formed in the metal oxide. By using the metal oxide in the channel formation region of the transistor, the stability or reliability of the transistor can be improved.

[0070] Note that, as a method for increasing the flatness of the film located below the metal oxide, CMP (Chem ical Mechanical Polishing) treatment, or a smoothing treatment using CMP may be performed.

[0071] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments, examples, etc. .

[0072] (Embodiment 2) Hereinafter, an example of a semiconductor device having a transistor 200 according to an aspect of the present invention will be described .

[0073] <Configuration example of semiconductor device> FIG. 2(A), FIG. 2(B), and FIG. 2(C) are top views and cross-sectional views of a transistor 2 00 according to an aspect of the present invention and the periphery of the transistor 200.

[0074] FIG. 2(A) is a top view of a semiconductor device having a transistor 200. Also, FIGS. 2( B), and FIG. 2(C) are cross-sectional views of the semiconductor device. Here, FIG. 2(B) is a cross-sectional view of the part shown by the dashed line A1 - A2 in FIG 2(A), and is also a cross-sectional view in the channel length direction of the transistor 200. Further, FIG. 2(C) is a cross-sectional view of the part shown by the dashed line A3 - A4 in FIG. 2(A) and is also a cross-sectional view in the channel width direction of the transistor 200. Note that, in the top view of FIG. 2(A), some elements are omitted for clarity of the drawing . .

[0075] A semiconductor device according to one aspect of the present invention includes a transistor 200 and an insulator 281 that functions as an interlayer film . It also includes a conductor 240 (conductor 240a and conductor 240b) that is electrically connected to the transistor 200 and functions as a plug . Note that an insulator 241 (insulator 241a and insulator 241b) is provided in contact with the side surface of the conductor 240 that functions as a plug

[0076] . Also, the insulator 241 is provided in contact with the inner wall of the openings formed in the insulators 254, 274, 280, and 281, and a first conductor of the conductor 240 is provided in contact with the side surface thereof, and a second conductor of the conductor 240 is further provided inside . Here, the height of the upper surface of the conductor 240 and the height of the upper surface of the insulator 281 can be made approximately the same . Note that, in the transistor 200, a configuration in which the first conductor of the conductor 240 and the second conductor of the conductor 240 are stacked is shown, but the present invention is not limited to this. For example, the conductor 240 may be provided in a single layer or a stacked structure of three or more layers . When the structure has a stacked structure, ordinal numbers may be assigned in the formation order for distinction . ​

[0077] [Transistor 200] As shown in FIG. 2, the transistor 200 includes an insulator 214 and an insulator 216 disposed on a substrate (not shown), and a conductor 205 disposed so as to be embedded in the insulator 214 and the insulator 216, an insulator 222 disposed on the insulator 216 and on the conductor 205, an insulator 224 disposed on the insulator 222, an oxide 230 (oxide 230a, oxide 230b, and oxide 230c) disposed on the insulator 224, an insulator 250 disposed on the oxide 230c, a conductor 260 (conductor 260a and conductor 260b) disposed on the insulator 250, conductors 242a and 242b in contact with a part of the upper surface of the oxide 230b, and an insulator 254 disposed in contact with the upper surface of the insulator 224, the side surfaces of the oxide 230a, the side surfaces of the oxide 230b, the side surfaces of the conductor 242a, the upper surface of the conductor 242a, the side surfaces of the conductor 242b, and the upper surface of the conductor 242b, an insulator 280 disposed on the insulator 254, and an insulator 274 disposed on the insulator 280. The conductor 260 includes a conductor 260a and a conductor 260b, and the conductor 260a is disposed so as to wrap the bottom surface and the side surfaces of the conductor 260b. Here, as shown in FIG. 2(B), the upper surface of the conductor 260 is disposed substantially flush with the upper surface of the insulator 250 and the upper surface of the oxide 230c. Further, the insulator 274 is in contact with the upper surfaces of the conductor 260, the oxide 230c, and the insulator 250, respectively, and the side surface of the insulator 241. And the insulator 222, the insulator 254, and the insulator 274 are made of hydrogen (for example, hydrogen atoms

[0078] , it preferably has a function of suppressing the diffusion of at least one such as hydrogen molecules. Also, The insulators 222, 254, and 274 preferably have a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.). For example, the insulators 222, 254, and 274 preferably have lower permeability to one or both of oxygen and hydrogen than the insulator 224 respectively. The insulators 222, 254, and 274 preferably have lower permeability to one or both of oxygen and hydrogen than the insulator 250 respectively. The insulators 222, 254, and 274 preferably have lower permeability to one or both of oxygen and hydrogen than the insulator 280 respectively. .

[0079] As shown in FIGS. 2(B) and 2(C), the insulator 254 preferably contacts the upper surface and side surface of the conductor 242a, the upper surface and side surface of the conductor 242b, the side surfaces of the oxides 230a and 230b, and the upper surface of the insulator 224. By the insulator 254 having a barrier property against hydrogen, covering the insulator 224 and the oxide 230, the insulator 280 is separated from the insulator 224 and the oxide 230 by the insulator 254. Thereby, it is possible to suppress the entry of impurities such as hydrogen from the outside of the transistor 200, so that good electrical characteristics and reliability can be given to the transistor 200. .

[0080] Also, the oxide 230 preferably has an oxide 230a disposed on the insulator 224, an oxide 230b disposed on the oxide 230a, and an oxide 230c disposed on the oxide 230b and at least a part of which contacts the upper surface of the oxide 230b.

[0081] Note that in the transistor 200, a structure in which three layers of oxide 230a, oxide 230b, and oxide 230c are stacked is shown in the channel formation region and its vicinity. However, the present invention is not limited to this. For example, a single layer of oxide 230b, a two-layer structure of oxide 230b and oxide 230a, a two-layer structure of oxide 230b and oxide 230c, or a structure having a stacked structure of four or more layers may be provided. Here, the conductor 260 functions as a gate electrode of the transistor, and the conductors 242a and 242b function as a source electrode or a drain electrode, respectively. The transistor 200 is self-aligned such that the conductor 260 functioning as a gate electrode fills an opening formed in the insulator 280 or the like. By forming the conductor 260 in this way, the conductor 260 can be surely arranged in the region between the conductors 242a and 242b without alignment.

[0082] Note that, as shown in FIG. 2, the conductor 260 preferably has a conductor 260a and a conductor 260b disposed on the conductor 260a. Note that in the transistor 200, the conductor 260 is shown as a two-layer stacked structure, but the present invention is not limited to this. For example, the conductor 260 may have a single-layer structure or a stacked structure of three or more layers. Also, the transistor 200 includes an insulator 214 disposed on a substrate (not shown), an insulator 216 disposed on the insulator 214, and the insulator 214 and the insulator 216 are buried in the insulator 214 and the insulator 216. Thus, the conductor 260 is formed self-alignedly so as to fill the opening formed in the insulator 280 or the like. By forming the conductor 260 in this way, the conductor 260 can be surely arranged in the region between the conductors 242a and 242b without alignment. Note that, as shown in FIG. 2, the conductor 260 preferably has a conductor 260a and a conductor 260b disposed on the conductor 260a. Note that in the transistor 200, the conductor 260 is shown as a two-layer stacked structure, but the present invention is not limited to this. For example, the conductor 260 may have a single-layer structure or a stacked structure of three or more layers. Note that, as shown in FIG. 2, the conductor 260 preferably has a conductor 260a and a conductor 260b disposed on the conductor 260a. Note that in the transistor 200, the conductor 260 is shown as a two-layer stacked structure, but the present invention is not limited to this. For example, the conductor 260 may have a single-layer structure or a stacked structure of three or more layers.

[0083] Note that, as shown in FIG. 2, the conductor 260 preferably has a conductor 260a and a conductor 260b disposed on the conductor 260a. Note that in the transistor 200, the conductor 260 is shown as a two-layer stacked structure, but the present invention is not limited to this. For example, the conductor 260 may have a single-layer structure or a stacked structure of three or more layers. Note that in the transistor 200, the conductor 260 is shown as a two-layer stacked structure, but the present invention is not limited to this. For example, the conductor 260 may have a single-layer structure or a stacked structure of three or more layers. Note that in the transistor 200, the conductor 260 is shown as a two-layer stacked structure, but the present invention is not limited to this. For example, the conductor 260 may have a single-layer structure or a stacked structure of three or more layers. Note that in the transistor 200, the conductor 260 is shown as a two-layer stacked structure, but the present invention is not limited to this. For example, the conductor 260 may have a single-layer structure or a stacked structure of three or more layers. Note that in the transistor 200, the conductor 260 is shown as a two-layer stacked structure, but the present invention is not limited to this. For example, the conductor 260 may have a single-layer structure or a stacked structure of three or more layers.

[0084] Also, the transistor 200 includes an insulator 214 disposed on a substrate (not shown), an insulator 216 disposed on the insulator 214, and the insulator 214 and the insulator 216 are buried in the insulator 214 and the insulator 216. The conductor 205 is arranged so as to be embedded, and the insulator 216 and the conductor 205 are arranged on the It is preferable that the insulating layer 222 is provided on the insulating layer 222. 4 is preferably placed.

[0085] The transistor 200 also includes an oxide 230 (oxide 230a) including a channel formation region. , oxide 230b, and oxide 230c), a metal oxide that functions as an oxide semiconductor It is preferable to use a semiconductor (hereinafter also referred to as an oxide semiconductor) as the insulating layer.

[0086] The transistor 200 having an oxide semiconductor in a channel formation region has a Since the leakage current (off-state current) is extremely small, a semiconductor device with low power consumption can be provided. In addition, oxide semiconductors can be deposited using a sputtering method or the like, making them suitable for highly integrated semiconductors. It can be used for the transistor 200 that constitutes the device.

[0087] For example, the oxide 230 may be an In-M-Zn oxide (wherein the element M is aluminum, gallium, etc.). Smoke, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel , germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium One or more selected from aluminum, tantalum, tungsten, magnesium, etc. In particular, the element M may be an oxide of a metal such as aluminum, gallium, or yttrium. The oxide 230 may be an In-Ga oxide, an In- Zn oxide may also be used.

[0088] In addition, in a transistor using an oxide semiconductor, a channel is formed in the oxide semiconductor. If impurities and oxygen vacancies exist in the region, the electrical characteristics are likely to fluctuate, reducing reliability. In addition, there are cases where oxygen vacancies are present in the region where a channel is formed in the oxide semiconductor. Therefore, the transistor tends to have normally-on characteristics. It is preferable that oxygen vacancies in the region to be covered are reduced as much as possible. Oxygen can be supplied to the oxide 230 via oxygen or the like to compensate for the oxygen deficiency. This transistor suppresses fluctuations in electrical characteristics, provides stable electrical characteristics, and improves reliability. A transistor can be provided.

[0089] Also, the oxide 230 is provided on the substrate 230 so as to be in contact with the oxide 230, and functions as a source electrode and a drain electrode. The elements contained in the conductor 242 (conductor 242a and conductor 242b) are oxides. When the oxide 230 has a function of absorbing oxygen, the oxide 230 is formed between the conductor 242 or between the oxide 230 and the conductor 242. In some cases, a low resistance region may be formed in part near the surface of the oxide 230. In the low resistance region, impurities (hydrogen, nitrogen, metal elements, etc.) that have entered the oxygen vacancies act as donors. In the following, oxygen vacancies may function as a barrier, increasing the carrier density. The hydrogen that has entered is called V o It may be called H.

[0090] 3A is an enlarged view of a portion of the transistor 200 shown in FIG. 2B. As shown in FIG. 3A, a conductor 242 is provided on and in contact with the oxide 230b. The oxide 230 has a low resistance region at the interface with the conductor 242 and in the vicinity thereof. (region 243a and region 243b) may be formed. A region 234 that functions as a channel formation region of the transistor 200 and a part of the region 243 are included and has a region 231 (region 231a and region 231b) that functions as a source region or a drain region. In the following drawings, even when the region 243 is not shown in an enlarged view or the like, a similar region 243 may be formed .

[0091] Note that the regions 243a and 243b show an example of being provided so as to diffuse in the depth direction in the vicinity of the conductor 242 of the oxide 230b, but the present invention is not limited to this . The regions 243a and 243b may be appropriately formed according to the required electrical characteristics of the transistor. Also, in the oxide 230, it may be difficult to clearly detect the boundaries of the respective regions . The concentration of the elements detected within each region is not limited to a stepwise change for each region, and may also change continuously (also referred to as gradation) within each region .

[0092] FIG. 3(B) is an example of a transistor in which an insulator 283 is disposed between an insulator 280 and an insulator 274 . That is, the insulator 274 and the insulator 250 are not in contact with each other . By adopting such a structure, impurities such as hydrogen contained in the insulator 280 may enter the insulator 250 through the insulator 283 . The impurities such as hydrogen that have entered the insulator 250 diffuse into the oxide 230 of the channel formation region, which may have an adverse effect on the electrical characteristics of the transistor and the reliability of the transistor .

[0093] Also, as shown in FIG. 3(A), the transistor 200 according to one aspect of the present invention has a structure in which the insulator 274 and the insulator 250 are in direct contact with each other. By adopting such a structure ​​Thus, impurities such as hydrogen contained in the insulator 280 or the like can be prevented from mixing into the insulator 250, and adverse effects on the above-described electrical characteristics and reliability can be suppressed.

[0094] Also, in FIG. 3(A), with reference to the bottom surface of the insulator 224, the height of the bottom surface of the conductor 260 in the region overlapping with the region 234 is preferably lower than the height of the upper surfaces of the conductors 242a and 242b, respectively. This allows the electric field from the conductor 260 that functions as a gate electrode to act on the entire channel formation region, which is preferable as it results in good operation of the transistor. If the difference between the height of the bottom surface of the conductor 260 in the region overlapping with the region 234 and the height of the upper surfaces of the conductors 242a and 242b, respectively, is T1, then T1 is set to 0 nm or more and 30 nm or less, preferably 0 nm or more and 15 nm or less.

[0095]

[0096] Here, an enlarged view of a partial region of the transistor 200 shown in FIG. 2(C) is shown in FIG. 4. FIG. 4 is an enlarged view of the channel formation region in the channel width direction of the transistor 200. As shown in FIG. 4, with reference to the bottom surface of the insulator 224, the height of the bottom surface of the conductor 260 in the region where the oxides 230a and 230b do not overlap with the conductor 260 is preferably lower than the height of the bottom surface of the oxide 230b.

[0096] If the difference between the height of the bottom surface of the conductor 260 in the region where the oxide 230b does not overlap with the conductor 260 and the height of the bottom surface of the oxide 230b is T2, then T2 is set to 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, more preferably 5 nm or more and 20 nm or less.

[0097]

[0097] In this way, the conductor 260 functioning as a gate electrode covers the side surface and the upper surface of the oxide 230b in the channel formation region via the oxide 230c and the insulator 250, resulting in a configuration that makes it easier for the electric field of the conductor 260 to act on the entire oxide 230b in the channel formation region. Therefore, the on-current of the transistor 200 can be increased, and the frequency characteristics can be improved.

[0098] As described above, a semiconductor device having a transistor with a large on-current can be provided. Also, a semiconductor device having a transistor with high frequency characteristics can be provided. In addition, a semiconductor device that suppresses fluctuations in electrical characteristics, has stable electrical characteristics, and has improved reliability can be provided. Also, a semiconductor device having a transistor with a small off-current can be provided.

[0099] Hereinafter, the detailed configuration of the semiconductor device having the transistor 200 according to one aspect of the present invention will be described.

[0100] The conductor 205 is arranged to overlap with the oxide 230 and the conductor 260. Also, the conductor 205 is preferably provided by being embedded in the insulator 214 and the insulator 216.

[0101] Here, the conductor 260 may function as a first gate (also referred to as a top gate) electrode. Also, the conductor 205 may function as a second gate (also referred to as a back gate) electrode. In that case, by changing the potential applied to the conductor 205 independently without linking it to the potential applied to the conductor 260, the threshold value of the transistor 200 can be changed. In particular, applying a negative potential to the conductor 205 can control the voltage (Vth). This makes it possible to increase the Vth of the transistor 200 and reduce the off-current. Therefore, applying a negative potential to the conductor 205 is more effective than not applying a negative potential. The drain current when the potential applied to the conductor 260 is 0 V can be reduced.

[0102] As shown in FIG. 2(A), the conductor 205 is formed in a region 234 of the oxide 230. In particular, as shown in FIG. 2(C), the conductor 205 is made of oxide 2 The region 234 of the channel 30 extends beyond the end portion thereof intersecting with the channel width direction. That is, it is preferable that the oxide 230 is formed on the outer side of the side surface in the channel width direction. Therefore, it is preferable that the conductor 205 and the conductor 260 overlap with each other via an insulator.

[0103] With the above configuration, the electric field of the conductor 260 that functions as the first gate electrode The electric field of the conductor 205, which functions as the second gate electrode, The first gate electrode can electrically surround the channel forming region. The electric field of the first gate electrode and the second gate electrode electrically surrounds the channel forming region. The structure of the transistor is a surrounded channel (S-channel) structure. It is called.

[0104] The conductor 205 is a conductive material mainly composed of tungsten, copper, or aluminum. Although the conductor 205 is illustrated as a single layer, it may be a laminated structure. For example, a laminate of titanium, titanium nitride and the above conductive material may be used.

[0105] The insulator 214 preferably functions as a barrier insulating film that suppresses impurities such as water and hydrogen from mixing into the transistor 200 from the substrate side. Therefore, the insulator 214 has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as N2O, NO, NO2, etc.), and copper atoms (the above impurities are difficult to permeate). It is preferable to use an insulating material. Or, it is preferable to use an insulating material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (the above oxygen is difficult to permeate).

[0106] For example, it is preferable to use silicon nitride or the like as the insulator 214. Thereby, it is possible to suppress the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200 side rather than through the insulator 214. Or, it is possible to suppress the diffusion of oxygen contained in the insulator 224 or the like to the substrate side rather than through the insulator 214.

[0107] Also, the insulators 216, 280, and 281 preferably have a lower dielectric constant than the insulator 214. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced. For example, as the insulators 216, 280, and 281, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having pores, etc. can be appropriately used.

[0108] The insulators 222 and 224 have the function as a gate insulator.

[0109] ​​​​​​​​​​​​​​ Here, the insulator 224 in contact with the oxide 230 preferably desorbs oxygen by heating. In this specification, oxygen desorbed by heating may be referred to as excess oxygen. For example, as the insulator 224, silicon oxide, silicon oxynitride, etc. may be appropriately used. By providing an oxygen-containing insulator in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced, and the reliability of the transistor 200 can be improved.

[0110] Specifically, as the insulator 224, it is preferable to use an oxide material in which some oxygen desorbs by heating. The oxide that desorbs oxygen by heating is an oxide film in which the desorption amount of oxygen in terms of oxygen atoms is 1.0×10 atoms / cm 18 or more, preferably 1.0×10 3 atoms / cm 19 or more, more preferably 2.0×10 atoms / cm 3 or more, and 19 is 3.0×10 3 atoms / cm or more in the TDS (Thermal Desorption Spectroscopy) analysis. The surface temperature of the film during the above TDS 20 analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 40 3 0°C or lower.

[0111] Also, as shown in Fig. 2(C), the insulator 224 may have a thickness in a region that does not overlap with the insulator 254 and does not overlap with the oxide 230b that is thinner than the thickness in other regions. In the insulator 224, the thickness of the region that does not overlap with the insulator 254 and does not overlap with the oxide 230b is preferably a thickness that allows sufficient diffusion of the above oxygen.

[0112] The insulator 222 prevents impurities such as water and hydrogen from diffusing into the transistor 200 from the substrate side. For example, the insulator 222 is preferably an insulating material. It is preferable that the hydrogen permeability is lower than that of the insulator 224. Therefore, by surrounding the insulator 224 and oxide 230, impurities such as water and hydrogen are prevented from escaping. This can prevent the voltage from penetrating into the transistor 200 from the other direction.

[0113] Furthermore, the insulator 222 is made of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). It is preferable that the material has a function of suppressing diffusion (i.e., the oxygen is less likely to permeate). The insulator 222 preferably has a lower oxygen permeability than the insulator 224. The oxide 230 has a function of suppressing the diffusion of atoms and impurities, and the oxygen contained in the oxide 230 acts as an insulator. It is preferable that the conductor 205 is not diffused to the insulator 216 side. 24 and the oxygen contained in the oxide 230 can be prevented.

[0114] The insulator 222 is made of one or both of aluminum and hafnium, which are insulating materials. It is recommended to use an insulator containing oxide. Oxide-containing insulators include aluminum oxide, hafnium oxide, aluminum and hafnium oxide. It is preferable to use an oxide containing hafnium (hafnium aluminate). When the insulator 222 is formed using such a material, the insulator 222 is oxidized by the oxide 230. The release of impurities and the introduction of impurities such as hydrogen into the oxide 230 from the periphery of the transistor 200 are prevented. It acts as a suppressing layer.

[0115] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, or the like may be added to these insulators. um, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, Zirconium oxide or the like may be added, or these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be laminated on the above insulator. good.

[0116] The insulator 222 may be made of, for example, aluminum oxide, hafnium oxide, tantalum oxide, Zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrT Insulators including so-called high-k materials such as (Ba,Sr)TiO3 and (Ba,Sr)TiO3 (BST) The insulating layer may be a single layer or a multilayer. However, thinning the gate insulator may cause problems such as leakage current. By using a high-k material as an insulator that functions as a body, the thickness of the This makes it possible to reduce the gate potential during transistor operation.

[0117] The insulator 222 and the insulator 224 may have a laminated structure of two or more layers. In this case, it is not limited to a laminated structure made of the same material, but may be a laminated structure made of different materials. good.

[0118] The oxide 230 is made up of an oxide 230a, an oxide 230b on the oxide 230a, and an oxide 230b. The oxide 230c is located on the surface of the oxide 230b. The oxide 230a is located under the oxide 230b. As a result, impurities from the structure formed below the oxide 230a are transferred to the oxide 230b. The diffusion can be suppressed. In addition, by having the oxide 230c on the oxide 230b, Diffusion of impurities from the structure formed above the oxide 230c to the oxide 230b can be suppressed.

[0119] Note that the oxide 230 preferably has a stacked structure with oxides having different atomic ratios of each metal atom. Specifically, in the metal oxide used for the oxide 230a, the atomic ratio of the element M in the constituent elements is preferably larger than the atomic ratio of the element M in the constituent elements in the metal oxide used for the oxide 230b. Also, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. Further, in the metal oxide used for the oxide 230b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a. Also, the metal oxide used for the oxide 230c can be the metal oxide that can be used for the oxide 230a or the oxide 230b. Also, the oxide 230b preferably has crystallinity. For example, it is preferable to use CAAC-OS described later. Oxides having crystallinity such as CAAC-OS have few impurities and defects (such as oxygen deficiencies) and have a highly crystalline and dense structure. Therefore, extraction of oxygen from the oxide 230b by the source electrode or the drain electrode can be suppressed. Thereby, even when heat treatment is performed, the extraction of oxygen from the oxide 230b can be reduced, so that the transistor 200 is stable against a high temperature (so-called thermal budget) in the manufacturing process.

[0120]

[0121] ​​​​​​​ Further, it is preferable that the energy levels of the lower ends of the conduction bands of the oxide 230a and the oxide 230c are higher than the energy level of the lower end of the conduction band of the oxide 230b. In other words, it is preferable that the electron affinities of the oxide 230a and the oxide 230c are smaller than the electron affinity of the oxide 230b.

[0122] Here, at the junctions of the oxide 230a, the oxide 230b, and the oxide 230c, the energy levels of the lower ends of the conduction bands change smoothly. In other words, the energy levels of the lower ends of the conduction bands at the junctions of the oxide 230a, the oxide 230b, and the oxide 230c can be said to change continuously or to be continuously joined. To achieve this, it is advisable to lower the density of defect energy levels in the mixed layers formed at the interfaces between the oxide 230a and the oxide 230b, and between the oxide 230b and the oxide 230c.

[0123] Specifically, as the oxide 230a, a metal oxide with In:Ga:Zn = 1:3:4 [atomic ratio], or 1:1:0.5 [atomic ratio] may be used. Also, as the oxide 230b, a metal oxide with In:Ga:Zn = 4:2:3 [atomic ratio], or 3:1:2 [atomic ratio] may be used. Further, as the oxide 230c, a metal oxide with In:Ga:Zn = 1:3:4 [atomic ratio], In:Ga:Zn = 4:2:3 [atomic ratio], Ga:Zn = 2:1 [atomic ratio], or Ga:Zn = 2:5 [atomic ratio] may be used. Also, as a specific example of the case where the oxide 230c has a stacked structure, a stacked structure of In:Ga:Zn = 4:2:3 atomic ratio] and Ga:Zn = 2:1 [atomic ratio], In:Ga:Zn = 4: atomic ratio] and Ga:Zn = 2:1 [atomic ratio], In:Ga:Zn = 4: A stacked structure with an atomic ratio of 2:3 and a stacked structure with Ga:Zn = 2:5 [atomic ratio], In:Ga:Z Examples include a stacked structure with an atomic ratio of n = 4:2:3 and gallium oxide.

[0124] At this time, the main path of the carriers becomes the oxide 230b. By configuring the oxide 230a and the oxide 2 30c as described above, the density of defect energy levels at the interface between the oxide 230a and the oxide 230b, and at the interface between the acid oxide 230b and the oxide 230c can be reduced. Therefore, the influence of interface scattering on carrier conduction is reduced, and the transistor 200 can have a high ion current and high frequency characteristics. When the oxide 230c has a stacked structure, in addition to the effect of reducing the density of defect energy levels at the interface between the above-mentioned oxide 230b and the oxide 230c, it is expected to suppress the diffusion of the constituent elements of the oxide 230c to the insulator 250 side. More specifically, by forming the oxide 230c into a stacked structure and positioning an oxide containing no In above the stacked structure, the diffusion of In that can diffuse to the insulator 250 side can be suppressed. Since the insulator 250 functions as a gate insulator, when In diffuses, it causes deterioration of the transistor characteristics. Therefore, by forming the oxide 230c into a stacked structure, it becomes possible to provide a highly reliable semiconductor device. When the oxide 230c has a stacked structure, in addition to the effect of reducing the density of defect energy levels at the interface between the above-mentioned oxide 230b and the oxide 230c, it is expected to suppress the diffusion of the constituent elements of the oxide 230c to the insulator 250 side. In addition to the effect of reducing the density of defect energy levels at the interface between the above-mentioned oxide 230b and the oxide 230c, it is expected to suppress the diffusion of the constituent elements of the oxide 230c to the insulator 250 side. More specifically, by forming the oxide 230c into a stacked structure and positioning an oxide containing no In above the stacked structure, the diffusion of In that can diffuse to the insulator 250 side can be suppressed. Since the insulator 250 functions as a gate insulator, when In diffuses, it causes deterioration of the transistor characteristics. Therefore, by forming the oxide 230c into a stacked structure, it becomes possible to provide a highly reliable semiconductor device. More specifically, by forming the oxide 230c into a stacked structure and positioning an oxide containing no In above the stacked structure, the diffusion of In that can diffuse to the insulator 250 side can be suppressed. Since the insulator 250 functions as a gate insulator, when In diffuses, it causes deterioration of the transistor characteristics. Therefore, by forming the oxide 230c into a stacked structure, it becomes possible to provide a highly reliable semiconductor device. Therefore, by forming the oxide 230c into a stacked structure, it becomes possible to provide a highly reliable semiconductor device.

[0125] It is preferable to use a metal oxide that functions as an oxide semiconductor for the oxide 230. For example, as the metal oxide in the region 234, those having a bandgap of 2 eV or more, preferably 2.5 eV or more are preferably used. By using such a metal oxide with a large bandgap, the off-current of the transistor can be reduced. In this way, by using a metal oxide with a large bandgap, the off-current of the transistor can be reduced. By using such a metal oxide with a large bandgap, the off-current of the transistor can be reduced. By using transistors, a semiconductor device with low power consumption can be provided.

[0126] On the oxide 230b, a conductor 242 that functions as a source electrode and a drain electrode (conductor 242a and conductor 242b) is provided. The film thickness of the conductor 242 is, for example 1 nm or more and 50 nm or less, preferably 2 nm or more and 25 nm or less.

[0127] As the conductor 242, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel lum, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium ium, lanthanum, or an alloy containing the above-described metal element as a component or an alloy combining the above-described metal elements is preferably used. For example, titanium nitride tantalum, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and al uminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium an oxide containing lanthanum and nickel, etc. are preferably used. Further, tantalum nitride titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum a nitride, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium an oxide, an oxide containing lanthanum and nickel are preferred because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when they absorb oxygen.

[0128] The insulator 254 functions as a barrier insulating film that suppresses impurities such as water or hydrogen from entering the transistor 200 from the insulator 2 80 side, similar to the insulator 214. is preferred. For example, the insulator 254 preferably has lower hydrogen permeability than the insulator 224. Furthermore, as shown in FIGS. 2(B) and 2(C), the insulator 254 preferably contacts the upper surface and the side surface of the conductor 242a, the upper surface and the side surface of the conductor 242b, the side surfaces of the oxides 230a and 230b, and the upper surface of the insulator 224. With such a configuration, it is possible to suppress hydrogen contained in the insulator 280 from entering the channel formation region of the oxide 230.

[0129] Furthermore, the insulator 254 preferably has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.). (The above oxygen is difficult to permeate.) For example, the insulator 254 preferably has lower oxygen permeability than the insulator 224.

[0130] The insulator 254 is preferably formed by a sputtering method. By forming the insulator 254 by a sputtering method in an atmosphere containing oxygen, oxygen can be added in the vicinity of the region where the insulator 254 contacts the insulator 224. Thereby, oxygen can be supplied from the region into the oxide 230 through the insulator 224. Here, since the insulator 254 has a function of suppressing the upward diffusion of oxygen, it is possible to prevent oxygen from diffusing from the oxide 230 to the insulator 280. Further, since the insulator 222 has a function of suppressing the downward diffusion of oxygen, it is possible to prevent oxygen from diffusing from the oxide 230 to the insulator 216. In this way, oxygen is supplied to the region 234 that functions as the channel formation region of the oxide 230. Thereby, the oxygen deficiency of the oxide 230 can be reduced, and the normal ionization of the transistor can be suppressed. ​​​​​​​​​​​​​​​

[0131] In addition, the insulator 254 can have a multi-layer structure of two or more layers. For example, as the insulator 25 4, the first layer is formed by sputtering in an oxygen-containing atmosphere, and then the second layer is formed by ALD method to form a two-layer structure. Since the ALD method is a film-forming method with good coverage it is possible to prevent the formation of steps or the like due to the unevenness of the first layer.

[0132] As the insulator 254, for example, an insulator containing one or both of aluminum and hafnium oxides may be formed. Note that as the insulator containing one or both of aluminum and hafnium oxides, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. are preferably used.

[0133] The insulator 250 functions as a gate insulator. The insulator 250 is preferably disposed in contact with the upper surface of the oxide 230c. The insulator 250 can be silicon oxide, silicon oxynitride oxynitride silicon, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon silicon oxide with added carbon and nitrogen, silicon oxide with pores, etc. can be used. In particular, silicon oxide and silicon oxynitride are preferred because they are stable against heat

[0134] Like the insulator 224, the insulator 250 is preferably formed using an insulator that releases oxygen upon heating. By providing an insulator that releases oxygen upon heating as the insulator 250 in contact with the upper surface of the oxide 230c, it is effective for the region 234 of the oxide 230b ​​​​​​can supply oxygen. Also, similar to the insulator 224, it is preferable that the concentration of impurities such as water and hydrogen in the insulator 250 is reduced. The film thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

[0135] Also, a metal oxide may be provided between the insulator 250 and the conductor 260. The metal oxide preferably suppresses the diffusion of oxygen from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. That is, it is possible to suppress a decrease in the amount of oxygen supplied to the oxide 230. Also, it is possible to suppress the oxidation of the conductor 260 by the oxygen in the insulator 250.

[0136] Also, the metal oxide may function as part of the gate insulator. Therefore, when using silicon oxide or silicon oxynitride for the insulator 250, it is preferable to use a metal oxide which is a high-k material having a high relative permittivity as the metal oxide. By forming the gate insulator into a laminated structure of the insulator 250 and the metal oxide, a laminated structure that is stable against heat and has a high relative permittivity can be obtained. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. Also, it is possible to thin the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator.

[0137] Specifically, it is selected from hafnium, aluminum, gallium, yttrium, zirconium, tantalum, tungsten, titanium, nickel, germanium, magnesium, etc. ​​​​​​​​​​​​One kind or two or more kinds of metal oxides can be used. In particular, aluminum oxide, which is an insulator containing one or both oxides of aluminum or hafnium, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate ) and the like are preferably used.

[0138] The conductor 260a preferably uses a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as N2O, NO, NO2, etc.) and copper atoms. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0139] In addition, since the conductor 260a has a function of suppressing the diffusion of oxygen, it is possible to suppress the oxidation of the conductor 260b by the oxygen contained in the insulator 250 and the decrease in conductivity. As the conductive material having a function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. are preferably used.

[0140] In addition, since the conductor 260 also functions as a wiring, it is preferable to use a conductor having high conductivity. For example, the conductor 260b can use a conductive material mainly composed of tungsten, copper, or aluminum. The conductor 260b may also have a laminated structure, for example, a laminated structure of titanium, titanium nitride, and the above conductive material.

[0141] The insulator 280 is connected to the insulator 224, the oxide 230, and the conductor via the insulator 254. It is provided on 242. For example, as the insulator 280, silicon oxide, silicon oxynitride , silicon nitride oxide, silicon oxide added with fluorine, silicon oxide added with carbon, car bon and silicon oxide added with nitrogen, silicon oxide having pores, etc. are preferably used. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having pores are preferable because they can easily form a region containing oxygen desorbed by heating.

[0142] It is preferable that the concentration of impurities such as water and hydrogen in the insulator 280 is reduced. Also, the upper surface of the insulator 280 may be planarized.

[0143] The insulator 274 preferably functions as a barrier insulating film that suppresses impurities such as water and hydrogen from entering the insulator 280 from above, similar to the insulator 214. As the insulator 2 74, for example, an insulator that can be used for the insulator 214, the insulator 254, etc. can be used.

[0144] Also, it is preferable to provide an insulator 281 that functions as an interlayer film on the insulator 274. Similar to the insulator 224, the insulator 281 preferably has a reduced concentration of impurities such as water and hydrogen in the film.

[0145] Also, conductors 240a and 240b are arranged in the openings formed in the insulator 281, the insulator 274, the insulator 280, and the insulator 254. The conductors 240a and the conductors 240b are provided facing each other with the conductor 260 interposed therebetween. Note that the conductors 240a and the conductors 240b The height of the upper surface of 240b may be flush with the upper surface of the insulator 281.

[0146] The insulating layers 281, 274, 280, and 254 are formed on the insulating layers 281, 274, 280, and 254. An insulator 241a is provided in contact with the inner wall of the opening, and a conductor 240a is formed in contact with the side surface of the insulator 241a. A conductor 242a is located at least partially on the bottom of the opening. The conductor 240a contacts the conductor 242a. Similarly, the insulator 281, the insulator 274, the insulator 280, and an insulator 241b is provided in contact with the inner wall of the opening formed in the insulator 254. The opening has a bottom surface at least partly formed with a conductor 240b in contact with the side surface. A conductor 242b is located at the portion, and the conductor 240b contacts the conductor 242b.

[0147] The conductors 240a and 240b are mainly made of tungsten, copper, or aluminum. It is preferable to use a conductive material containing the conductive material 240a and the conductive material 240b. 0b may have a laminated structure.

[0148] In addition, when the conductor 240 has a laminated structure, the oxide 230a, the oxide 230b, the conductor 242, conductors in contact with insulators 254, 280, 274, and 281 For this purpose, it is preferable to use a conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen. Examples of suitable materials include tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, and ruthenium oxide. It is preferable to use aluminum or the like. In addition, it is preferable to use aluminum or the like which has the function of suppressing the permeation of impurities such as water and hydrogen. The conductive material having the above structure may be used in a single layer or a laminated layer. The oxygen added to the insulator 280 is absorbed by the conductors 240a and 240b. can be prevented. Also, impurities such as water and hydrogen can be suppressed from mixing into the oxide 230 from above the insulator 281 through the conductor 240a and the conductor 24 0b.

[0149] As the insulator 241a and the insulator 241b, for example, an insulator that can be used for the insulator 254 or the like may be used. Since the insulator 241a and the insulator 241b are provided in contact with the insulator 254, impurities such as water and hydrogen can be suppressed from mixing into the oxide 230 from the insulator 280 or the like through the conductor 240a and the conductor 240 b. Also, oxygen contained in the insulator 280 can be prevented from being absorbed by the conductor 240a and the conductor 240b.

[0150] Although not shown, conductors that function as wiring may be arranged in contact with the upper surfaces of the conductor 240a and the conductor 240b. The conductor that functions as wiring preferably uses a conductive material mainly composed of tungsten, copper, or aluminum. Also, the conductor may have a laminated structure, for example, a laminate of titanium, titanium nitride, and the above conductive material. Note that the conductor may be formed to be embedded in an opening provided in an insulator.

[0151] <Constituent Materials of Semiconductor Device> Hereinafter, constituent materials that can be used for a semiconductor device will be described.

[0152] <<Substrate>> As the substrate on which the transistor 200 is formed, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. As the insulator substrate, for example, a glass substrate, a quartz substrate, a s ​​​​​​​​​​A fire substrate, a stabilized zirconia substrate (such as a yttria-stabilized zirconia substrate), a resin substrate, etc. There are substrates such as these. As semiconductor substrates, for example, semiconductor substrates such as silicon, germanium, or compound semiconductor substrates composed of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Furthermore, there are semiconductor substrates having an insulator region inside the aforementioned semiconductor substrates, such as, for example, an SOI (Silicon On Insulator) substrate. As conductor substrates, there are graphite substrates, metal substrates, alloy substrates, conductive resin substrates, etc. Or, there are substrates having a metal nitride, substrates having a metal oxide, etc. Furthermore, there are substrates in which a conductor or semiconductor is provided on an insulator substrate, substrates in which a conductor or insulator is provided on a semiconductor substrate, substrates in which a semiconductor or insulator is provided on a conductor substrate, etc. Or, those in which elements are provided on these substrates may also be used. As elements provided on the substrate, there are capacitor elements, resistor elements, switch elements, light-emitting elements, memory elements, etc.

[0153] <<Insulator>> As insulators, there are oxides having insulating properties, nitrides, oxynitrides, nitroxides, metal oxides, metal oxynitrides, metal nitroxides, etc.

[0154] For example, as the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulator film. By using a high-k material for the insulator that functions as a gate insulator, it is possible to lower the operating voltage of the transistor while maintaining the physical film thickness. On the other hand, for insulators that function as interlayer films, materials with a low relative permittivity are used. This can reduce the parasitic capacitance generated between the wirings. Therefore, the material may be selected according to the function of the insulator.

[0155] In addition, examples of insulators with a high relative permittivity include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, nitrides containing silicon and hafnium, and the like.

[0156] In addition, examples of insulators with a low relative permittivity include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with pores, resins, and the like.

[0157] In addition, a transistor using an oxide semiconductor can have its electrical characteristics stabilized by surrounding it with an insulator (such as insulator 214, insulator 222, insulator 254, insulator 274, etc.) having a function of suppressing the permeation of impurities such as hydrogen and oxygen. Examples of insulators having a function of suppressing the permeation of impurities such as hydrogen and oxygen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum, which may be used singly or in a laminated structure. Specifically, as an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, hafnium, or tantalum may be used. ​​​​​​​​​​​Zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide such as metal oxides, aluminum nitride, aluminum titanium nitride, titanium nitride, silicon oxynitride

[0158] In addition, the insulator that functions as the gate insulator preferably has a region containing oxygen that desorbs upon heating. For example, by forming a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that desorbs upon heating is in contact with the oxide 230, the oxygen deficiency of the oxide 230 can be compensated for.

[0159] <<Conductor>> As the conductor, metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or alloys containing the above-described metal elements as components, or alloys combining the above-described metal elements are preferably used. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. Further, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, and an oxide containing lanthanum and nickel are conductive materials that are difficult to oxidize, or oxygen-absorbing materials. ​​​​​​​​​​​​​​Since it is a material that maintains conductivity even when [conditions are met], it is preferable. Also, it contains impurity elements such as phosphorus Semiconductors with high electrical conductivity typified by polycrystalline silicon containing [such impurity elements], silicides such as nickel silicide, etc. may be used.

[0160] Also, a plurality of conductive layers formed of the above materials may be laminated and used. For example, a laminated structure combining the material containing a metal element and the conductive material containing oxygen may be used. Also, a laminated structure combining the material containing the above-mentioned metal element and the conductive material containing nitrogen may be used. Also, a laminated structure combining the material containing the above-mentioned metal element, the conductive material containing oxygen, and the conductive material containing nitrogen may be used.

[0161] In addition, when an oxide is used in the channel formation region of the transistor, for the conductor that functions as the gate electrode, the material containing the above-mentioned metal element and the conductive material containing oxygen are preferably combined and used. In this case, it is preferable to provide the conductive material containing oxygen on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region. Specifically, as the conductor that functions as the gate electrode, it is preferable to use the conductive material containing the metal element and oxygen contained in the metal oxide in which the channel is formed. Also, the

[0162] conductive material containing the above-mentioned metal element and nitrogen may be used. For example, conductive materials containing nitrogen such as titanium nitride and tantalum nitride may be used. Also, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, titanium oxide etc. such as indium zinc oxide containing tungsten oxide, titanium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide containing indium, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon may be used. Further, indium gallium zinc oxide containing nitrogen may be used. By using such a material, hydrogen contained in the metal oxide in which the channel is formed may be captured. Or, hydrogen mixed from an external insulator or the like may be captured. It is preferable to use, as the oxide 230, a metal oxide that functions as an oxide semiconductor. Hereinafter, the metal oxide applicable to the oxide 230 according to the present invention will be described. The metal oxide preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. Further, in addition to them, it is preferable that aluminum, gallium, yttrium, tin, etc. are contained. Also, one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. may be contained. Here, consider the case where the metal oxide is an In-M-Zn oxide having indium, element M and zinc. Note that element M is aluminum, gallium, yttrium, tin, etc. Applicable elements for other element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. However, as element M, the aforementioned

[0163] <<Metal Oxide>>

[0164]

[0165] ​ There may be cases where a plurality of elements can be combined.

[0166] In the present specification and the like, a metal oxide containing nitrogen may also be collectively referred to as a metal oxide (metal ox ide). Further, a metal oxide containing nitrogen may be referred to as a metal oxynitride (me tal oxynitride).

[0167] [Structure of Metal Oxide] An oxide semiconductor (metal oxide) can be divided into a single crystal oxide semiconductor and other non-single crystal oxide semi conductors. Examples of the non-single crystal oxide semiconductor include CAAC-OS, polycrystalline oxide semi conductor, nc-OS (nanocrystalline oxide semi conductor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous us-like oxide semiconductor), and amorphous oxide semi conductor, etc.

[0168] CAAC-OS has a c-axis orientation, and in the a-b plane direction, a plurality of nanocrystals are connected to form a crystal structure with strain. Note that strain refers to a region where the lattice arrays are aligned between a region where the lattice arrays are aligned and another region where the lattice arrays are aligned in the region where a plurality of nanocrystals are connected and the direction of the lattice array changes.

[0169] Nanocrystals are based on hexagons, but are not necessarily regular hexagons and may be non-regular hexagons in some cases. Also, in the strain, there may be cases where lattice arrays such as pentagons and heptagons are present. Note that in CAAC-OS, it is difficult to confirm a clear grain boundary (also called a grain boundary ー) even near the strain. That is, due to the strain of the lattice array, the grain boundary ​It can be seen that the formation of is suppressed. This is because CAAC-OS can tolerate strain due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction and the interatomic bond distance changes when a metal element substitutes. and so on.

[0170] In addition, CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium and oxygen (hereinafter referred to as the In layer) and a layer containing element M, zinc, and oxygen (hereinafter referred to as the (M,Zn) layer) are laminated. Note that indium and element M are mutually substitutable. When element M in the (M,Zn) layer is substituted with indium, it can also be represented as an (In,M,Zn) layer. Also, when indium in the In layer is substituted with element M, it can also be represented as an (In,M) layer.

[0171] CAAC-OS is a highly crystalline metal oxide. On the other hand, since it is difficult to confirm distinct crystal grain boundaries in CAAC-OS, it can be said that a decrease in electron mobility due to crystal grain boundaries is unlikely to occur. Also, since the crystallinity of metal oxides may decrease due to the incorporation of impurities or the generation of defects, it can be said that CAAC-OS is a metal oxide with few impurities and defects (such as oxygen deficiencies). Therefore, the metal oxide having CAAC-OS has stable physical properties. For this reason, the metal oxide having CAAC-OS is heat-resistant and highly reliable.

[0172] nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Also, nc-OS does not show regularity in the crystal orientation between different nano crystals. Therefore, no orientation is seen in the entire film. ​​​​​​​​​​​​​Therefore, depending on the analysis method, nc-OS may not be distinguishable from a-like OS or amorphous oxide semiconductors.

[0173] Note that indium-gallium-zinc oxide (hereinafter referred to as IGZO), which is a kind of metal oxide having indium, gallium, and zinc, may have a stable structure by forming the above-described nanocrystals. In particular, since IGZO tends to be difficult to grow crystals in the air, a crystal smaller than a large crystal (here, a crystal of several mm or several cm), for example, the above-described nanocrystal, may be structurally more stable.

[0174] a-like OS is a metal oxide having a structure between nc-OS and amorphous oxide semiconductors. a-like OS has a loose or low-density region. That is, a-like OS has lower crystallinity than nc-OS and CAAC-OS.

[0175] Oxide semiconductors (metal oxides) have various structures and each has different characteristics. The oxide semiconductor according to one aspect of the present invention may have two or more of amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, nc-OS, and CAAC-OS.

[0176] [Impurities] Here, the influence of each impurity in the metal oxide will be described.

[0177] In addition, when an alkali metal or an alkaline earth metal is contained in a metal oxide, defect levels may be formed and carriers may be generated. Therefore, a transistor using a metal oxide containing an alkali metal or an alkaline earth metal in a channel formation region is normally on. ​​​​​​​​​It tends to have such characteristics. Therefore, it is preferable to reduce the concentration of alkali metals or alkaline earth metals in the metal oxide. Specifically, the concentration of alkali metals or alkaline earth metals in the metal oxide obtained by secondary ion mass spectrometry (SIMS) is set to 1×10 atoms / cm 18 or less, preferably 2×10 3 atoms / cm or less. 16 3

[0178] In addition, since hydrogen contained in the metal oxide reacts with oxygen bonded to metal atoms to form water, oxygen vacancies may be formed. When hydrogen enters the oxygen vacancies, carriers, electrons, may be generated. Also, part of the hydrogen may bond with oxygen bonded to metal atoms to generate carriers, electrons. Therefore, a transistor using a metal oxide containing hydrogen tends to have normally-on characteristics.

[0179] Therefore, it is preferable that the hydrogen in the metal oxide is reduced as much as possible. Specifically, in the metal oxide, the hydrogen concentration obtained by SIMS is set to less than 1×10 20 atoms / cm 3 , preferably less than 1×10 19 atoms / cm 3 , more preferably less than 5×1 0 18 atoms / cm 3 , still more preferably less than 1×10 18 atoms / cm 3 . By using a metal oxide with sufficiently reduced impurities in the channel formation region of the transistor, stable electrical characteristics can be imparted.

[0180] As a metal oxide used for a semiconductor of a transistor, it is preferable to use a highly crystalline thin film. By using this thin film, the stability or reliability of the transistor can be improved. Examples of such a thin film include a single crystal metal oxide thin film or a polycrystalline metal oxide thin film. However, to form a single crystal metal oxide thin film or a polycrystalline metal oxide thin film on a substrate, a high-temperature or laser heating process is required. Therefore, the cost of the manufacturing process increases, and furthermore, the throughput also decreases. In 2009, it was reported in Non-Patent Document 1 and Non-Patent Document 2 that an In-Ga-Zn oxide having a CAAC structure (referred to as CAAC-IGZO) was discovered. Here, it is reported that CAAC-IGZO has a c-axis orientation, no clearly confirmed grain boundaries, and can be formed on a substrate at a low temperature. Furthermore, it is reported that a transistor using CAAC-IGZO has excellent electrical characteristics and reliability. Also, in 2013, an In-Ga-Zn oxide having an nc structure (referred to as nc-IGZO) was discovered (see Non-Patent Document 3). Here, it is reported that nc-IGZO has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 3 nm or less), and no regularity is observed in the crystal orientation between different such regions.

[0181] In Non-Patent Document 4 and Non-Patent Document 5, the average crystal size of each of the above-mentioned CAAC-IGZO, nc-IGZO, and IGZO thin films with low crystallinity due to electron beam irradiation is... (referred to as CAAC-IGZO).) was reported in Non-Patent Document 1 and Non-Patent Document 2. Here, it is reported that CAAC-IGZO has a c-axis orientation, no clearly confirmed grain boundaries, and can be formed on a substrate at a low temperature. Furthermore, it is reported that a transistor using CAAC-IGZO has excellent electrical characteristics and reliability. Here, it is reported that CAAC-IGZO has a c-axis orientation, no clearly confirmed grain boundaries, and can be formed on a substrate at a low temperature. Furthermore, it is reported that a transistor using CAAC-IGZO has excellent electrical characteristics and reliability. Furthermore, it is reported that a transistor using CAAC-IGZO has excellent electrical characteristics and reliability.

[0182] Also, in 2013, an In-Ga-Zn oxide having an nc structure (referred to as nc-IGZO).) was discovered (see Non-Patent Document 3). Here, it is reported that nc-IGZO has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 3 nm or less), and no regularity is observed in the crystal orientation between different such regions. it is reported that nc-IGZO has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 3 nm or less), and no regularity is observed in the crystal orientation between different such regions. it is reported that nc-IGZO has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 3 nm or less), and no regularity is observed in the crystal orientation between different such regions.

[0183] In Non-Patent Document 4 and Non-Patent Document 5, for each of the above-mentioned CAAC-IGZO, nc-IGZO, and IGZO thin films with low crystallinity, the average crystal size due to electron beam irradiation is... The transition of the haze is shown. In the IGZO thin film with low crystallinity, even before the electron beam irradiation, crystalline IGZO of about 1 nm has been observed. Therefore, it has been reported that in IGZO here, the existence of a completely amorphous structure could not be confirmed. Furthermore, compared with the thin film of IGZO with low crystallinity, the thin films of CAAC-IGZO and nc-IGZO have been shown to have high stability against electron beam irradiation. Therefore, it is preferable to use the thin film of CAAC-IGZO or nc-IGZO as the semiconductor of the transistor. Even before, crystalline IGZO of about 1 nm has been observed. Therefore, in IGZO here, it has been reported that the existence of a completely amorphous structure could not be confirmed. Furthermore, compared with the thin film of IGZO with low crystallinity, the thin films of CAAC-IGZO and nc-IGZO have been shown to have high stability against electron beam irradiation. Therefore, it is preferable to use the thin film of CAAC-IGZO or nc-IGZO as the semiconductor of the transistor.

[0184] A transistor using a metal oxide has an extremely small leakage current in the non-conducting state. Specifically, it is shown in Non-Patent Document 6 that the off-current per 1 μm of the channel width of the transistor is on the order of yA / μm (10 -2 4 A / μm). For example, a low-power consumption CPU etc. that applies the characteristic of low leakage current of a transistor using a metal oxide has been disclosed (see Non-Patent Document 7).

[0185] In addition, the application of the transistor using a metal oxide to a display device that utilizes the characteristic of low leakage current of the transistor has been reported (see Non-Patent Document 8). In the display device, the displayed image is switched dozens of times per second. The number of times of image switching per second is called the refresh rate. Also, the refresh rate is sometimes called the driving frequency. Such a high-speed switching of the screen that is difficult for the human eye to perceive is considered to be the cause of eye fatigue. Therefore, the refresh rate of the display device is lowered to reduce the image switching speed, which is difficult for the human eye to perceive, and is considered to be the cause of eye fatigue. Therefore, the refresh rate of the display device is lowered to reduce the image It has been proposed to reduce the number of rewrites. Also, by reducing the refresh rate driving, it is possible to reduce the power consumption of the display device. Such a driving method is referred to as idling stop (IDS) driving.

[0186] The discovery of the CAAC structure and the nc structure has led to improvements in the electrical characteristics and reliability of transistors using metal oxides having the CAAC structure or the nc structure, as well as cost reduction in the manufacturing process and improvement in throughput. In addition, research on the application of the transistor to display devices and LSIs using the characteristic of low leakage current of the transistor is underway .

[0187] <Modification example of semiconductor device> In FIG. 2, a configuration example of a semiconductor device having a transistor 200 in which a conductor 242 functioning as a source electrode or a drain electrode is formed in contact with an oxide 23 0 will be described. However, the configuration of the semiconductor device is not limited to this. Hereinafter, an example of a semiconductor device having a transistor 200A according to one aspect of the present invention will be described with reference to FIG. 5.

[0188] FIG. 5(A) is a top view of a semiconductor device having a transistor 200A. Also, FIGS. 5 (B) and FIG. 5(C) are cross-sectional views of the semiconductor device. Here, FIG. 5(B) is a cross-sectional view of the portion indicated by the dashed line A1 - A2 in FIG. 5 (A), and is also a cross-sectional view in the channel length direction of the transistor 200A. Also, FIG. 5(C) is a cross-sectional view of the portion indicated by the dashed line A3 - A4 in FIG. 5 (A), and is also a cross-sectional view in the channel width direction of the transistor 200A . Note that in the top view of FIG. 5(A), some elements are omitted for clarity of the figure.

[0189] In the semiconductor device shown in FIG. 5, the semiconductor device shown in <Configuration Example of Semiconductor Device> is structurally configured with the same functions and the same reference numerals are added.

[0190] Hereinafter, the configuration of the semiconductor device will be described with reference to FIG. 5. Also in this section, as the constituent material of the semiconductor device, the materials described in detail in <Configuration Example of Semiconductor Device> can be used. This is possible.

[0191] Note that the transistor 200A included in the semiconductor device shown in FIG. 5 is a modified example of the transistor 200 included in the semiconductor device shown in <Configuration Example of Semiconductor Device>. Therefore, in order to avoid redundant explanations, mainly, the differences from the transistor 200 shown in <Configuration Example of Semiconductor Device> will be described. from the transistor 200 shown in <Configuration Example of Semiconductor Device> will be described. will be described.

[0192] The transistor 200A shown in FIG. 5 does not have the conductor 242 and the insulator 254, unlike the transistor 200 shown in <Configuration Example of Semiconductor Device>. Instead, it has the insulator 244 and the insulator 245. The transistor 200A shown in FIG. 5 does not have the conductor 242, and by selectively reducing the resistance of the oxide 230, a source region or a drain region is provided in the oxide 230b. region is provided. region is provided. region is provided.

[0193] Similar to the transistor 200 shown in FIG. 2, the transistor 200A shown in FIG. 5 can use a metal oxide that functions as an oxide semiconductor for the oxide 230 including the channel formation region. formation region. This is possible.

[0194] The oxide 230 is doped with an element that forms oxygen vacancies or an element that binds to oxygen vacancies. By doing so, the carrier density may increase and the resistance may decrease. To reduce the resistance of the oxide 230 Typical elements for this purpose include boron or phosphorus. Further, hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, noble gases, etc. may be used. Representative examples of noble gases include helium, neon, argon, krypton, xenon, etc.

[0195] The concentration of the above elements may be measured using SIMS or the like.

[0196] In particular, boron and phosphorus are preferable because the equipment for manufacturing amorphous silicon or low-temperature polysilicon lines can be used. By diverting the equipment of the manufacturing line, capital investment can be suppressed.

[0197] The region 243 (region 243a and region 243b) shown in FIG. 5 is a region where the above elements are added to the oxide 230b. The region 243 can be formed, for example, using a dummy gate.

[0198] For example, a dummy gate is provided on the oxide 230b, and using the dummy gate as a mask, it is advisable to add an element that reduces the resistance of the oxide 230b. That is, the element is added to the region where the oxide 230 does not overlap with the dummy gate, and the region 243 is formed. As the method for adding the element, an ion implantation method in which an ionized source gas is mass-separated and added, an ion doping method in which an ionized source gas is added without mass separation, a plasma immersion ion implantation method, etc. can be used.

[0199] An insulator is provided between the oxide 230b and the dummy gate, and the dummy gate is It may be used as a mask, and an element for reducing the resistance of the oxide 230b may be added. To this insulator For example, the same material as that of the insulator 224 can be used.

[0200] Subsequently, an insulating film that becomes the insulator 244 and an insulating film that becomes the insulator 245 may be formed on the oxide 230b and the dummy gate. By laminating the insulating film that becomes the insulator 244 and the insulating film that becomes the insulator 245, a region where the region 243, the oxide 230c, and the insulator 250 overlap can be provided.

[0201] Specifically, after providing an insulating film that becomes the insulator 280 on the insulating film that becomes the insulator 245, by performing CMP processing on the insulating film that becomes the insulator 280, a part of the insulating film that becomes the insulator 280 is removed to expose the dummy gate. Subsequently, when removing the dummy gate, a part of the insulating film that becomes the insulator 244 in contact with the dummy gate may also be removed. Therefore, the insulator 2 45 and the insulator 244 are exposed on the side surface of the opening provided in the insulator 280, and a part of the region 243 provided in the oxide 230b is exposed on the bottom surface of the opening. Next, an oxide film that becomes the oxide 230c, an insulating film that becomes the insulator 250, and a conductive film that becomes the conductor 26 0 are sequentially formed in the opening, and then, until the insulator 280 is exposed, by CMP processing or the like, a part of the oxide film that becomes the oxide 230c, the insulating film that becomes the insulator 250, and the conductive film that becomes the conductor 260 is removed, whereby the transistor 200A shown in FIG. 5 can be formed. .

[0202] The insulators 244 and 245 have a function of suppressing the permeation of impurities such as hydrogen and oxygen and oxygen. It is preferable to use an insulator having energy. Note that the insulators 244 and 245 are not essential components. They may be appropriately designed according to the required transistor characteristics.

[0203] The transistor 200A shown in FIG. 5 can reuse existing devices. Further, since no conductor 242 is provided unlike the transistor 200 shown in FIG. 2, cost reduction can be achieved.

[0204] As described above, the configurations, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments and examples.

[0205] (Embodiment 3) In this embodiment, one form of the semiconductor device will be described with reference to FIGS. 6 and 7.

[0206] [Memory device 1] An example of a semiconductor device (memory device) using a capacitive element, which is one aspect of the present invention, is shown in FIG. 6. A semiconductor device according to one aspect of the present invention includes a capacitive element 100, a transistor 200, and a transistor 300. The transistor 200 is provided above the transistor 300, and the capacitive element 100 is provided above the transistor 300 and the transistor 200. Note that, as the transistor 200, the transistor 200 described in the previous embodiment can be used.

[0207] The transistor 200 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. Since the transistor 200 has a small off-current, using this in a memory device makes it possible to retain the stored content for a long time. That is, a refresh operation ​​​​It does not require operations or has an extremely low refresh operation frequency, so the power consumption of the memory device can be sufficiently reduced.

[0208] In the semiconductor device shown in FIG. 6, wiring 1001 is electrically connected to the source of transistor 300 and wiring 1002 is electrically connected to the drain of transistor 300. Also, wiring 1003 is electrically connected to one of the source and drain of transistor 200 and wiring 1004 is electrically connected to the first gate of transistor 200, and wiring 10 06 is electrically connected to the second gate of transistor 200. Then, the gate of transistor 300, and the other of the source and drain of transistor 200 are electrically connected to one of the electrodes of capacitor element 100, and wiring 1005 is electrically connected to the other of the electrodes of capacitor element 100.

[0209] Also, the memory device shown in FIG. 6 can form a memory cell array by being arranged in a matrix.

[0210] <Transistor 300> Transistor 300 is provided on substrate 311 and has a conductor 3 16 that functions as a gate electrode, an insulator 315 that functions as a gate insulator, a semiconductor region 313 that is part of substrate 311, and low-resistance regions 314a and 314b that function as a source region or a drain region. Transistor 300 can be either p-channel type or n-channel type.

[0211] Here, the transistor 300 shown in FIG. 6 has a semiconductor region 313 (base A part of the plate 311 has a convex shape. Also, the side surface and the upper surface of the semiconductor region 313 are provided so as to be covered with a conductor 316 via an insulator 315. Note that the conductor 316 may be made of a material that adjusts the work function. Since such a transistor 300 utilizes the convex portion of the semiconductor substrate, it is also called a FIN-type transistor. Note that an insulator that functions as a mask for forming the convex portion may be provided in contact with the upper portion of the convex portion. Also, although the case where a convex portion is formed by processing a part of the semiconductor substrate has been shown here, an SOI substrate may be processed to form a semiconductor film having a convex shape. The transistor 300 shown in FIG. 6 is an example, and the present invention is not limited to the structure thereof, and an appropriate transistor may be used according to the circuit configuration and the driving method. The capacitor element 100 has a conductor 110 that functions as a first electrode, a conductor 120 that functions as a second electrode, and an insulator 130 that functions as a dielectric. For example, the conductor 110 can be formed simultaneously with the conductor 112 provided on the conductor 246. Note that the conductor 112 functions as a plug or wiring that is electrically connected to the capacitor element 100, the transistor 200, or the transistor 300. In FIG. 6, the conductor 112 and the conductor 110 are shown having a single-layer structure, but the present invention is not limited to this configuration, and a stacked structure of two or more layers may be used. For example, a conductor having a barrier property and a conductor having high conductivity may be formed between a conductor having a barrier property and a conductor having high adhesiveness to the conductor having high conductivity. In the case where a convex portion is formed by processing a part of the semiconductor substrate as described above, a semiconductor film having a convex shape may be formed by processing an SOI substrate. Note that the transistor 300 shown in FIG. 6 is an example, and the present invention is not limited to the structure thereof, and an appropriate transistor may be used according to the circuit configuration and the driving method.

[0212] Note that the transistor 300 shown in FIG. 6 is an example, and the present invention is not limited to the structure thereof, and an appropriate transistor may be used according to the circuit configuration and the driving method. Note that the transistor 300 shown in FIG. 6 is an example, and the present invention is not limited to the structure thereof, and an appropriate transistor may be used according to the circuit configuration and the driving method.

[0213] <Capacitor element 100> The capacitor element 100 has a conductor 110 that functions as a first electrode, a conductor 120 that functions as a second electrode, and an insulator 130 that functions as a dielectric. The capacitor element 100 has a conductor 110 that functions as a first electrode, a conductor 120 that functions as a second electrode, and an insulator 130 that functions as a dielectric.

[0214] For example, the conductor 110 can be formed simultaneously with the conductor 112 provided on the conductor 246. Note that the conductor 112 functions as a plug or wiring that is electrically connected to the capacitor element 100, the transistor 200, or the transistor 300. Note that the conductor 112 functions as a plug or wiring that is electrically connected to the capacitor element 100, the transistor 200, or the transistor 300.

[0215] In FIG. 6, the conductor 112 and the conductor 110 are shown having a single-layer structure, but the present invention is not limited to this configuration, and a stacked structure of two or more layers may be used. For example, a conductor having a barrier property and a conductor having high conductivity may be formed between a conductor having a barrier property and a conductor having high adhesiveness to the conductor having high conductivity. For example, a conductor having a barrier property and a conductor having high conductivity may be formed between a conductor having a barrier property and a conductor having high adhesiveness to the conductor having high conductivity. For example, a conductor having a barrier property and a conductor having high conductivity may be formed between a conductor having a barrier property and a conductor having high adhesiveness to the conductor having high conductivity.

[0216] The insulator 130 may be, for example, silicon oxide, silicon oxynitride, or silicon nitride oxide. , silicon nitride, aluminum oxide, aluminum oxide nitride, aluminum nitride oxide, nitride Aluminum oxide, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride The material may be aluminum or the like, and may be provided as a laminated layer or a single layer.

[0217] For example, the insulator 130 may be made of a material with high dielectric strength such as silicon oxynitride and a material with high dielectric strength such as silicon oxynitride. It is preferable to use a laminated structure with a high-k material. The element 100 has a high dielectric constant (high-k) insulator, which ensures sufficient capacitance. By using an insulator with a high dielectric strength, the dielectric strength is improved, and the electrostatic breakdown of the capacitance element 100 is prevented. This can suppress the destruction.

[0218] In addition, oxide is used as an insulator for high dielectric constant (high-k) materials (materials with high relative dielectric constant). Contains gallium, hafnium oxide, zirconium oxide, aluminum and hafnium Oxide, Oxynitride with Aluminum and Hafnium, Silicon and Hafnium oxides having silicon and hafnium; oxide nitrides having silicon and hafnium; Nitrides containing ammonium.

[0219] On the other hand, materials with high dielectric strength (materials with low dielectric constant) include silicon oxide and oxynitride. silicon dioxide, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, carbon Doped silicon oxide, carbon and nitrogen doped silicon oxide, silicon oxide with vacancies There are various types of resins, such as kon and resin.

[0220] <Wiring layer> A wiring layer provided with an interlayer film, wiring, plugs, etc. may be provided between the respective structures. Also, a plurality of wiring layers can be provided according to the design. Here, there are cases where conductors having the function of plugs or wiring are given the same reference numeral in a lump for a plurality of structures. Moreover, in this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductor functions as wiring and a part of the conductor functions as a plug. For example, on the transistor 300, as an interlayer film, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are laminated in this order. Also, a capacitor element 100, or conductors 328 and 330 etc. electrically connected to the transistor 300 are embedded in the insulator 320, the insulator 322, the insulator 324, and the insulator 326. Note that the conductors 328 and 330 function as plugs or wiring.

[0221] Furthermore, the insulator functioning as the interlayer film may function as a planarization film covering the uneven shape below it. For example, the upper surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to enhance flatness. An insulator 350, an insulator 352, and an insulator 354 are laminated in this order. Also, a conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or wiring. A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. 6,

[0222]

[0223] ​​​​​​​

[0224] Similarly, the insulators 210, 212, 214, and 216 are electrically conductive. The conductive material 218 and the conductive material (conductive material 205) that constitutes the transistor 200 are embedded. Note that the conductor 218 is electrically connected to the capacitor 100 or the transistor 300. The conductor 120 and the insulator 130 function as a plug or wiring. An insulator 150 is provided on 130 .

[0225] Insulators that can be used as the interlayer film include oxides, nitrides, and oxides that have insulating properties. Examples of such materials include metal nitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides.

[0226] For example, by using a material with a low relative dielectric constant for the insulator that functions as an interlayer film, Therefore, depending on the function of the insulator, the material It is recommended to select:

[0227] For example, the insulators 150, 212, 352, and 354 have a relative dielectric constant It is preferable to use an insulator with a low resistance. For example, the insulator may be silicon oxide, oxynitride, or the like. Silicon, silicon oxynitride, silicon nitride, silicon oxide doped with fluorine, and carbon doped silicon oxide doped with carbon and nitrogen, silicon oxide with vacancies Preferably, the insulator comprises silicon oxide, oxynitride, or the like. Silicon, silicon oxynitride, silicon nitride, silicon oxide doped with fluorine, and carbon doped silicon oxide doped with carbon and nitrogen, or silicon oxide with vacancies. It is preferable that the insulating film has a laminated structure of silicon oxide and resin. Since recon is thermally stable, when combined with a resin, it can form a thermally stable laminated structure with a low relative dielectric constant. Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic. Also, a transistor using an oxide semiconductor can have its electrical characteristics stabilized by surrounding it with an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen. Therefore, for the insulator 210, insulator 350, etc., an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen can be used. Examples of the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum, which can be used either as a single layer or in a laminated structure. Specifically, as the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, silicon oxynitride, silicon nitride, etc. can be used.

[0228] For the conductor that can be used for wiring and plugs, there are aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium. Since recon is thermally stable, when combined with a resin, it can form a thermally stable laminated structure with a low relative dielectric constant. Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic. Also, a transistor using an oxide semiconductor can have its electrical characteristics stabilized by surrounding it with an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen. Therefore, for the insulator 210, insulator 350, etc., an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen can be used. Examples of the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum, which can be used either as a single layer or in a laminated structure.

[0229] Specifically, as the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, silicon oxynitride, silicon nitride, etc. can be used. For the conductor that can be used for wiring and plugs, there are aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium. Since recon is thermally stable, when combined with a resin, it can form a thermally stable laminated structure with a low relative dielectric constant. Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic. Also, a transistor using an oxide semiconductor can have its electrical characteristics stabilized by surrounding it with an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen. Therefore, for the insulator 210, insulator 350, etc., an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen can be used. Examples of the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum, which can be used either as a single layer or in a laminated structure. Specifically, as the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, silicon oxynitride, silicon nitride, etc. can be used. For the conductor that can be used for wiring and plugs, there are aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium. Since recon is thermally stable, when combined with a resin, it can form a thermally stable laminated structure with a low relative dielectric constant. Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic.

[0230] For the conductor that can be used for wiring and plugs, there are aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium. For the conductor that can be used for wiring and plugs, there are aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium. Materials containing one or more metal elements selected from germanium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. can be used. Also, a semiconductor with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, etc., or silicides such as nickel silicide may be used. For example, as the conductors 328, 330, 356, 218, 112, etc., conductive materials such as metal materials, alloy materials, metal nitride materials, and metal oxide materials formed of the above materials can be used alone or in a stacked manner. It is preferable to use high melting point materials such as tungsten and molybdenum that can achieve both heat resistance and conductivity, and it is

[0231] preferable to use tungsten. Or, it is preferable to form it with a low resistance conductive material such as aluminum or copper. By using a low resistance conductive material, the wiring resistance can be reduced. <<Wiring or plug of the layer provided with the oxide semiconductor>> In addition, when an oxide semiconductor is used for the transistor 200, an insulator having an excess oxygen region may be provided in the vicinity of the oxide semiconductor. In that case, it is preferable to provide an insulator having barrier properties between the insulator having the excess oxygen region and the conductor provided on the insulator having the excess oxygen region. For example, in FIG. 6, it is advisable to provide an insulator 276 between the insulator 224 having excess oxygen and the conductor 246. By providing the insulator 276 in contact with the insulator 222 and the insulator 274, the insulator 224 and the transistor 200 are insulated with barrier properties.

[0232]

[0233] ​​​​​​​​​The body can be configured to be sealed. Further, the insulator 276 preferably contacts the insulator 280. Since the insulator 276 extends up to the insulator 280, the diffusion of oxygen and impurities can be further suppressed. That is, by providing the insulator 276, it is possible to suppress the absorption of excess oxygen in the insulator 224 by the conductor 246. Also, by having the insulator 276, it is possible to suppress the diffusion of hydrogen, which is an impurity, to the transistor 200 through the conductor 246.

[0234]

[0235] Note that as the insulator 276, an insulating material having a function of suppressing the diffusion of impurities such as water and hydrogen and oxygen may be used. For example, it is preferable to use aluminum oxide, hafnium oxide, etc. Also, alternatively, for example, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, tantalum oxide, silicon oxynitride, silicon nitride, etc. can be used.

[0236] The above is the description of the configuration example. By using this configuration, in a semiconductor device using a transistor having an oxide semiconductor, fluctuations in electrical characteristics can be suppressed and the reliability can be improved. Or, a transistor having an oxide semiconductor with a large on-current can be provided. Or, a transistor having an oxide semiconductor with a small off-current can be provided. Or, a semiconductor device with reduced power consumption can be provided.

[0237] [Memory device 2] ​​​​​​​​​​​​​​​An example of a memory device using the semiconductor device according to one aspect of the present invention is shown in FIG. 7. As shown in FIG. 7 The memory device has, in addition to the semiconductor device having the transistor 200, the transistor 300, and the capacitor element 100, a transistor 400.

[0238] The transistor 400 can control the second gate voltage of the transistor 200 For example, the first gate and the second gate of the transistor 400 are source-dioded connected, and the source of the transistor 400 is connected to the second gate of the transistor 200 configured. When the negative potential of the second gate of the transistor 200 is held in this configuration, the voltage between the first gate and the source of the transistor 400 and the voltage between the second gate and the source of the transistor 400 become 0V. In the transistor 400, since the drain current when the second gate voltage and the first gate voltage are 0V is very small, even without supplying power to the transistor 200 and the transistor 400 the negative potential of the second gate of the transistor 200 can be maintained for a long time . Thus, the memory device having the transistor 200 and the transistor 400 can retain the stored content for a long time. Therefore, in FIG. 7, the wiring 1001 is electrically connected to the source of the transistor 300

[0239] and the wiring 1002 is electrically connected to the drain of the transistor 300. Also, the wiring 1003 is electrically connected to one of the source and the drain of the transistor 200, the wiring 1004 is electrically connected to the first gate of the transistor 200, and the wiring 1006 is electrically connected to the second gate of the transistor 200 . And the transistor 30 ​The gate of the transistor 200 and the other of the source and drain of the transistor 200 are connected to the capacitance element 10 The wiring 1005 is electrically connected to one of the electrodes of the capacitor 100. The wiring 1007 is electrically connected to the source of the transistor 400. The wiring 1008 is electrically connected to the first gate of the transistor 400, and the wiring 1009 is The wiring 1010 is electrically connected to the second gate of the transistor 400. 00. Here, the wiring 1006, the wiring 1007, the wiring 1008 and wiring 1009 are electrically connected.

[0240] 7 is arranged in a matrix, similar to the storage device shown in FIG. By doing so, a memory cell array can be configured. Therefore, the second gate voltages of the plurality of transistors 200 can be controlled. The number of transistors 400 provided may be smaller than the number of transistors 200 provided.

[0241] <Transistor 400> The transistor 400 is formed in the same layer as the transistor 200 and is fabricated in parallel. The transistor 400 has a first gate electrode and a second gate electrode. The conductor 460 (conductor 460a and conductor 460b) functions as a gate electrode. Conductor 405 functions as a gate electrode, insulator 222 functions as a gate insulator, and insulator 2 24, and an insulator 450, an oxide 430c having a region where a channel is to be formed, and The conductor 442a, which functions as either a source or a drain, the oxide 431a, and the oxide The oxide 431b and the conductor 442b functioning as the other of the source and drain are 2a, and oxide 432b, and conductor 440 (conductor 440a and conductor 440b ).

[0242] In transistor 400, conductor 405 and conductor 205 are formed in the same layer . Oxide 431a, oxide 432a, and oxide 230a are formed in the same layer , oxide 431b, oxide 432b, and oxide 230b are formed in the same layer . Conductor 442 and conductor 242 are formed in the same layer. Oxide 430c and oxide 230c are formed in the same layer. Insulator 450 and insulator 250 are formed in the same layer . Conductor 460 and conductor 260 are formed in the same layer

[0243] Note that structures formed in the same layer can be formed simultaneously. For example, oxide 4 30c can be formed by processing the oxide film that becomes oxide 230c

[0244] Oxide 430c, which functions as the active layer of transistor 400, is the same as oxide 230 etc , with reduced oxygen deficiency and reduced impurities such as hydrogen and water. As a result, the threshold voltage of transistor 400 can be made larger, the off-current can be reduced, and the drain current when the second gate voltage and the first gate voltage are 0V can be made very small .

[0245] <Dicing line> In the following, a dicing line (which may also be called a scribing line, a dividing line , or a cutting line) provided when a large-area substrate is divided into chips for each semiconductor element to extract a plurality of semiconductor devices will be described. As a dividing method, for example, ​Next, after forming a groove (dicing line) for dividing the semiconductor element on the substrate, dicing is performed at the dicing line to divide (split) the substrate into a plurality of semiconductor devices. Here, for example, as shown in FIG. 7, it is preferable to design the region where the insulator 254 and the insulator 222 are in contact as the dicing line. That is, openings are provided in the insulator 224 in the vicinity of the region that becomes the dicing line provided at the outer edges of the memory cell having the plurality of transistors 200 and the transistor 400. Further, an insulator 254 is provided so as to cover the side surface of the insulator 224.

[0246] That is, at the opening provided in the insulator 224, the insulator 222 and the insulator 254 are in contact. For example, at this time, the insulator 222 and the insulator 254 may be formed using the same material and the same method. By providing the insulator 222 and the insulator 254 with the same material and the same method, the adhesion can be enhanced. For example, it is preferable to use aluminum oxide. With this structure, the insulator 222 and the insulator 254 can wrap the insulator 224, the transistor 200, and the transistor 400. Since the insulator 222 and the insulator 254 have a function of suppressing the diffusion of oxygen, hydrogen, and water, even if the substrate is processed into a plurality of chips by dividing each circuit region in which the semiconductor element shown in the present embodiment is formed, impurities such as hydrogen and water can be prevented from entering from the side surface direction of the divided substrate and diffusing into the transistor 200 and the transistor 400. That is, at the opening provided in the insulator 224, the insulator 222 and the insulator 254 are in contact. For example, at this time, the insulator 222 and the insulator 254 may be formed using the same material and the same method. By providing the insulator 222 and the insulator 254 with the same material and the same method, the adhesion can be enhanced. For example, it is preferable to use aluminum oxide. Here, for example, as shown in FIG. 7, it is preferable to design the region where the insulator 254 and the insulator 222 are in contact as the dicing line. That is, openings are provided in the insulator 224 in the vicinity of the region that becomes the dicing line provided at the outer edges of the memory cell having the plurality of transistors 200 and the transistor 400. Further, an insulator 254 is provided so as to cover the side surface of the insulator 224. That is, at the opening provided in the insulator 224, the insulator 222 and the insulator 254 are in contact. For example, at this time, the insulator 222 and the insulator 254 may be formed using the same material and the same method. By providing the insulator 222 and the insulator 254 with the same material and the same method, the adhesion can be enhanced. For example, it is preferable to use aluminum oxide.

[0247] That is, at the opening provided in the insulator 224, the insulator 222 and the insulator 254 are in contact. For example, at this time, the insulator 222 and the insulator 254 may be formed using the same material and the same method. By providing the insulator 222 and the insulator 254 with the same material and the same method, the adhesion can be enhanced. For example, it is preferable to use aluminum oxide. That is, at the opening provided in the insulator 224, the insulator 222 and the insulator 254 are in contact. For example, at this time, the insulator 222 and the insulator 254 may be formed using the same material and the same method. By providing the insulator 222 and the insulator 254 with the same material and the same method, the adhesion can be enhanced. For example, it is preferable to use aluminum oxide. With this structure, the insulator 222 and the insulator 254 can wrap the insulator 224, the transistor 200, and the transistor 400. Since the insulator 222 and the insulator 254 have a function of suppressing the diffusion of oxygen, hydrogen, and water, even if the substrate is processed into a plurality of chips by dividing each circuit region in which the semiconductor element shown in the present embodiment is formed, impurities such as hydrogen and water can be prevented from entering from the side surface direction of the divided substrate and diffusing into the transistor 200 and the transistor 400. That is, at the opening provided in the insulator 224, the insulator 222 and the insulator 254 are in contact. For example, at this time, the insulator 222 and the insulator 254 may be formed using the same material and the same method. By providing the insulator 222 and the insulator 254 with the same material and the same method, the adhesion can be enhanced. For example, it is preferable to use aluminum oxide. Here, for example, as shown in FIG. 7, it is preferable to design the region where the insulator 254 and the insulator 222 are in contact as the dicing line. That is, openings are provided in the insulator 224 in the vicinity of the region that becomes the dicing line provided at the outer edges of the memory cell having the plurality of transistors 200 and the transistor 400. Further, an insulator 254 is provided so as to cover the side surface of the insulator 224.

[0248] With this structure, the insulator 222 and the insulator 254 can wrap the insulator 224, the transistor 200, and the transistor 400. Since the insulator 222 and the insulator 254 have a function of suppressing the diffusion of oxygen, hydrogen, and water, even if the substrate is processed into a plurality of chips by dividing each circuit region in which the semiconductor element shown in the present embodiment is formed, impurities such as hydrogen and water can be prevented from entering from the side surface direction of the divided substrate and diffusing into the transistor 200 and the transistor 400. That is, at the opening provided in the insulator 224, the insulator 222 and the insulator 254 are in contact. For example, at this time, the insulator 222 and the insulator 254 may be formed using the same material and the same method. By providing the insulator 222 and the insulator 254 with the same material and the same method, the adhesion can be enhanced. For example, it is preferable to use aluminum oxide. Here, for example, as shown in FIG. 7, it is preferable to design the region where the insulator 254 and the insulator 222 are in contact as the dicing line. That is, openings are provided in the insulator 224 in the vicinity of the region that becomes the dicing line provided at the outer edges of the memory cell having the plurality of transistors 200 and the transistor 400. Further, an insulator 254 is provided so as to cover the side surface of the insulator 224. With this structure, the insulator 222 and the insulator 254 can wrap the insulator 224, the transistor 200, and the transistor 400. Since the insulator 222 and the insulator 254 have a function of suppressing the diffusion of oxygen, hydrogen, and water, even if the substrate is processed into a plurality of chips by dividing each circuit region in which the semiconductor element shown in the present embodiment is formed, impurities such as hydrogen and water can be prevented from entering from the side surface direction of the divided substrate and diffusing into the transistor 200 and the transistor 400. That is, at the opening provided in the insulator 224, the insulator 222 and the insulator 254 are in contact. For example, at this time, the insulator 222 and the insulator 254 may be formed using the same material and the same method. By providing the insulator 222 and the insulator 254 with the same material and the same method, the adhesion can be enhanced. For example, it is preferable to use aluminum oxide. Here, for example, as shown in FIG. 7, it is preferable to design the region where the insulator 254 and the insulator 222 are in contact as the dicing line. That is, openings are provided in the insulator 224 in the vicinity of the region that becomes the dicing line provided at the outer edges of the memory cell having the plurality of transistors 200 and the transistor 400. Further, an insulator 254 is provided so as to cover the side surface of the insulator 224.

[0249] In addition, due to this structure, the excess oxygen in the insulator 224 can be prevented from diffusing to the outside of the insulator 254 and the insulator 222 . Therefore, the excess oxygen in the insulator 224 is efficiently supplied to the oxide in which the channel in the transistor 200 or the transistor 400 is formed . By this oxygen, the oxygen deficiency of the oxide in which the channel in the transistor 200 or the transistor 400 is formed can be reduced. As a result, the oxide in which the channel in the transistor 200 or the transistor 400 is formed can be made into an oxide semiconductor having stable characteristics with a low defect level density. That is, the variation in the electrical characteristics of the transistor 200 or the transistor 400 can be suppressed, and the reliability can be improved . .

[0250] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments, examples, etc .

[0251] (Embodiment 4) In this embodiment, using FIGS. 8 and 9, a transistor using an oxide as a semiconductor (hereinafter sometimes referred to as an OS transistor) according to one aspect of the present invention, and a memory device to which a capacitor element (hereinafter sometimes referred to as an OS memory device) is applied will be described . The OS memory device is a memory device having at least a capacitor element and an OS transistor that controls the charge and discharge of the capacitor element. Since the off-current of the OS transistor is extremely small, the OS memory device has excellent holding characteristics and can function as a non-volatile memory .

[0252] <Configuration example of memory device> FIG. 8(A) shows an example of the configuration of the OS memory device. The memory device 1400 includes a peripheral circuit 14​​​​ 11. and has a memory cell array 1470. The peripheral circuit 1411 includes a row circuit 1420 , a column circuit 1430, an output circuit 1440, and a control logic circuit 1460. It has.

[0253] The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, etc. The precharge circuit has a function of precharging the wiring. The sense a mplifier has a function of amplifying the data signal read from the memory cell. Note that the above wiring is the wiring connected to the memory cells of the memory cell array 1470, which will be described in detail later. The amplified data signal is output to the outside of the storage device 1400 as the data signal RDA TA via the output circuit 1440. Also, the row circuit 1420 includes, for example, a row decoder, a word line driver circuit, etc., and can select the row to be accessed.

[0254] The storage device 1400 is supplied with a low power supply voltage (VSS) as a power supply voltage from the outside, a high power supply voltage (VDD) for the peripheral circuit 14 11, and a high power supply voltage (VIL) for the memory cell array 1470. Also, control signals (CE, WE, RE), an address signal ADDR, and a data signal WDATA are input to the storage device 1400 from the outside. The address signal ADDR is input to the row decoder and the column decoder, and the data signal WDATA is input to the write circuit. It is.

[0255] The control logic circuit 1460 processes the control signals (CE, WE, RE) from the outside and generates control signals for the row decoder and the column decoder. The control signal CE is the chip enable signal. The control signal WE is a write enable signal, and the control signal RE is a read enable signal. The signal processed by the control logic circuit 1460 is However, the present invention is not limited to this, and other control signals may be input as required.

[0256] The memory cell array 1470 includes a plurality of memory cells MC arranged in a matrix and a plurality of The wiring connecting the memory cell array 1470 and the row circuit 1420 is The number of lines is determined by the configuration of the memory cells MC, the number of memory cells MC in one row, etc. The number of wirings connecting the memory cell array 1470 and the column circuit 1430 is It is determined by the configuration of the memory cells MC, the number of memory cells MC in one row, etc.

[0257] In FIG. 8A, the peripheral circuit 1411 and the memory cell array 1470 are arranged on the same plane. Although the example of forming the above has been shown, the present embodiment is not limited to this. For example, As shown in FIG. 8B, a memory cell array 1470 is provided on a part of the peripheral circuit 1411. For example, the memory cell array 1470 may be provided so as to overlap the memory cell array 1470. A sense amplifier may be provided in addition to the signal line.

[0258] FIG. 9 illustrates an example of the configuration of a memory cell that can be applied to the above-described memory cell MC.

[0259] [DOSRAM] 9A to 9C show examples of circuit configurations of memory cells in a DRAM. DRAM using a memory cell with one OS transistor and one capacitor element is called DOSRAM. (registered trademark)(Dynamic Oxide Semiconductor Random (m Access Memory). The memory cell 1 shown in Fig. 9(A) 471 has a transistor M1 and a capacitive element CA. Note that the transistor M1 has a gate (which may be called a top gate) and a back gate.

[0260] The first terminal of the transistor M1 is connected to the first terminal of the capacitive element CA, and the second terminal of the transistor M 1 is connected to the wiring BIL, the gate of the transistor M1 is connected to the wiring WOL continuously, and the back gate of the transistor M1 is connected to the wiring BGL. The second terminal of the capacitive element C A is connected to the wiring CAL.

[0261] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitive element CA. During data writing and reading, it is preferable to apply a low-level potential to the wiring CAL. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M1 can be increased or decreased.

[0262] Also, the memory cell MC is not limited to the memory cell 1471, and the circuit configuration can be changed. For example, the memory cell MC may have a configuration in which the back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1472 shown in Fig. 9(B). Also, for example, the memory cell MC may be a transistor with a single-gate structure, that is, a transistor without a back gate, as in the memory cell 1473 shown in Fig. 9(C). ​It may also be a memory cell composed of the transistor M1.

[0263] When the semiconductor device shown in the above embodiment is used for the memory cell 1471 or the like, the transistor 200 can be used as the transistor M1, and the capacitor element 100 can be used as the capacitor element CA. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be made very small. That is, since the written data can be held by the transistor M1 for a long time, the refresh frequency of the memory cell can be reduced. In addition, the refresh operation of the memory cell can be made unnecessary. Further, since the leakage current is very small, multi-valued data or analog data can be held in the memory cell 1471, the memory cell 147 2, and the memory cell 1473.

[0264] Also, in the DOSRAM, as described above, if the sense amplifier is provided so as to overlap under the memory cell array 1470, the bit line can be shortened. As a result, the bit line capacitance becomes small, and the holding capacitance of the memory cell can be reduced.

[0265] [NOSRAM] Figures 9(D) to (G) show circuit configuration examples of a gain cell type memory cell of 2 transistors and 1 capacitor element. The memory cell 1474 shown in Figure 9(D) has a transistor M2, a transistor M3, and a capacitor element CB. Note that the transistor M2 has a gate (sometimes called a top gate). In this specification and the like, a storage device having a gain cell type memory cell using an OS transistor for the transistor M2 , sometimes referred to as NOSRAM (registered trademark) (Nonvolatile Oxide Semiconductor RAM). The first terminal of transistor M2 is connected to the first terminal of capacitor element CB, the second terminal of transistor M

[0266] 2 is connected to wiring WBL, the gate of transistor M2 is connected to wiring WOL, and the back gate of transistor M2 is connected to wiring BGL. The second terminal of capacitor element C B is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring R BL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M 3 is connected to the first terminal of capacitor element CB.

[0267] Wiring WBL functions as a write bit line, wiring RBL functions as a read bit line, and wiring WOL functions as a word line. Wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of capacitor element CB. During data writing, during data retention, and during data reading, it is preferable to apply a low-level potential to wiring CAL. Wiring BGL functions as a wiring for applying a potential to the back gate of transistor M2. By applying an arbitrary potential to wiring BGL, the threshold voltage of transistor M2 can be increased or decreased.

[0268] Also, memory cell MC is not limited to memory cell 1474, and the circuit configuration can be appropriately changed. For example, memory cell MC can be like memory cell 1475 shown in FIG. 9(E), where the back gate of transistor M2 is connected to wiring WOL instead of wiring BGL. ​​​​​​​It may be configured. Also, for example, the memory cell MC may be a memory cell 14 shown in FIG. 9(F) 76, that is, a memory cell composed of a single-gate structure transistor, i.e., a transistor M2 without a back gate . Also, for example, the memory cell MC may be a configuration in which the wiring WBL and the wiring RBL are combined into a single wiring B IL as shown in the memory cell 1477 of FIG. 9(G).

[0269] When the semiconductor device shown in the above embodiment is used for the memory cell 1474 or the like, the transistor 200 can be used as the transistor M2, and the transistor 300 can be used as the transistor M3 , and the capacitor element 100 can be used as the capacitor element CB. By using an OS transistor as the transistor M2 , the leakage current of the transistor M2 can be made very small . As a result, the written data can be held by the transistor M2 for a long time , so that the frequency of refreshing the memory cell can be reduced . Also, the refresh operation of the memory cell can be made unnecessary. Also, since the leakage current is extremely small , the memory cell 1474 can hold multi-valued data or analog data . The same applies to the memory cells 1475 to 1477

[0270] . Note that the transistor M3 may be a transistor having silicon in the channel formation region (hereinafter , sometimes referred to as an Si transistor). The conductivity type of the Si transistor may be an n-channel type or a p-channel type. The Si transistor may have a higher field-effect mobility than the OS transistor . Therefore, the read transistor ​As the transistor M3 that functions as, an Si transistor may be used. Also, by using an Si transistor for the transistor M3, the transistor M2 can be provided stacked on the transistor M3, so that the occupied area of the memory cell can be reduced and the high integration of the memory device can be achieved.

[0271] Also, the transistor M3 may be an OS transistor. When OS transistors are used for the transistors M2 and M3, the memory cell array 1470 can be configured using only n-type transistors.

[0272] Also, FIG. 9(H) shows an example of a gain cell type memory cell of a three transistor one capacitor element. The memory cell 1478 shown in FIG. 9(H) has transistors M4 to M6 and a capacitor element CC. The capacitor element CC is provided as appropriate. The memory cell 1478 is electrically connected to wiring BIL, RWL, WWL, BGL, and GNDL. The wiring GNDL is a wiring that gives a low level potential. Note that the memory cell 1478 may be electrically

[0273] connected to wirings RBL and WBL instead of the wiring BIL. The transistor M4 is an OS transistor having a back gate, and the back gate is electrically connected to the wiring BGL. Note that the back gate and the gate of the transistor M4 may be electrically connected to each other.

[0274] Alternatively, the transistor M4 may not have a back gate. Alternatively, the transistors M5 and M6 may each be an n-channel type Si It may also be a standby. In this case, the memory cell array 1470 can be configured with only n-type transistors. The circuit can be configured.

[0275] When the semiconductor device shown in the above embodiment is used for the memory cell 1478, the transistor 200 is used as the transistor M4, and the transistors 300 are used as the transistors M5 and M6. The capacitor element 100 can be used as the capacitor element CC. By using the OS transistor as the transistor M4, the leakage current of the transistor M4 can be made very small.

[0276] Note that the configurations of the peripheral circuit 1411, the memory cell array 1470, etc. shown in this embodiment are not limited to the above. The arrangements or functions of these circuits, the wirings connected to the circuits, the circuit elements, etc. may be changed, deleted, or added as necessary.

[0277] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments, examples, etc.

[0278] (Embodiment 5) In this embodiment, an example of the chip 1200 on which the semiconductor device of the present invention is mounted is shown using FIG. 10. A plurality of circuits (systems) are mounted on the chip 1200. In this way, the technology of integrating a plurality of circuits (systems) on one chip is sometimes called a system on chip (SoC).

[0279] As shown in FIG. 10(A), the chip 1200 includes a CPU (Central Processing Unit) 1211, a GPU (Graphics Processing Unit) 1212, one or more analog operation units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network working circuits 1216, etc.

[0280] The chip 1200 is provided with bumps (not shown), and as shown in Fig. 10(B), it is connected to the first surface of the printed circuit board (PCB) 1201. Also, on the back surface of the first surface of the PCB 1201, a plurality of bumps 1202 are provided and connected to the motherboard 1203.

[0281] The motherboard 1203 may be provided with storage devices such as DRAM 1221 and flash memory 1222. For example, DOSRAM shown in the previous embodiment can be used for the DRAM 1221. Also, for example, NOSRAM shown in the previous embodiment can be used for the flash memory 1222. It is preferable that the CPU 1211 has a plurality of CPU cores. Also, it is preferable that the GPU 1212 has a plurality of GPU cores. Also, the CPU 1211 and the GPU 1 212 may each have a memory for temporarily storing data. Or, a memory common to the CPU 1211 and the GPU 1212 may be provided on the chip 1200. The above-mentioned NOSRAM or DOSRAM can be used for this memory.

[0282] The GPU 1212 is suitable for parallel calculation of a large number of data and can be used for image processing and multiplication-accumulation operations. An image processing circuit using the oxide semiconductor of the present invention or can be used for the GPU 1212. Also, the CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Or, a memory common to the CPU 1211 and the GPU 1212 may be provided on the chip 1200. The above-mentioned NOSRAM or DOSRAM can be used for this memory. The CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Or, a memory common to the CPU 1211 and the GPU 1212 may be provided on the chip 1200. The above-mentioned NOSRAM or DOSRAM can be used for this memory. Also, the GPU 1212 is suitable for parallel calculation of a large number of data and can be used for image processing and multiplication-accumulation operations. An image processing circuit using the oxide semiconductor of the present invention or can be used for the GPU 1212. For the GPU 1212, an image processing circuit using the oxide semiconductor of the present invention or , by providing a multiplication-accumulation circuit, it becomes possible to execute image processing and multiplication-accumulation operations with low power consumption. This becomes possible.

[0283] Also, since the CPU 1211 and the GPU 1212 are provided on the same chip, the wiring between the CPU 1211 and the GPU 1212 can be shortened, and data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and the GPU 1212, and after the operation in the GPU 1212, the transfer of the operation result from the GPU 1212 to the CPU 1211 can be performed at high speed.

[0284] The analog operation unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. Also, the above multiplication-accumulation circuit may be provided in the analog operation unit 1213. The analog operation unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. Also, the multiplication-accumulation circuit may be provided in the analog operation unit 1213. The multiplication-accumulation circuit may be provided in the analog operation unit 1213.

[0285] The memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222.

[0286] The interface 1215 has an interface circuit with external connection devices such as a display device, a speaker, a microphone, a camera, and a controller. The controller includes a mouse, a keyboard, a game controller, etc. As such an interface, USB (Universal Serial Bus), HDMI (registered trademark) (High-Definition Multimedia Interface), etc. can be used. As such an interface, USB (Universal Serial Bus), HDMI (registered trademark) (High-Definition Multimedia Interface), etc. can be used.

[0287] The network circuit 1216 has a network circuit such as a LAN (Local Area Network). It may also have a circuit for network security.

[0288] It is possible to form the above circuit (system) on the chip 1200 using the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.

[0289] A PCB 1201 provided with a chip 1200 having a GPU 1212, a DRAM 122 1, and a motherboard 1203 provided with a flash memory 1222 can be called a GPU module 1204.

[0290] Since the GPU module 1204 has a chip 1200 using SoC technology, its size can be reduced. Also, since it is excellent in image processing, it is suitable for use in portable electronic devices such as smart phones, tablet terminals, laptop PCs, and portable (portable) game machines. Also, due to the multiply-accumulate circuit using the GPU 1212, it is possible to execute methods such as deep neural networks (DNN), convolutional neural networks (CNN), recurrent neural networks (RNN), autoencoders, deep Boltzmann machines (DBM), and deep belief networks (DBN). Therefore, the chip 1200 can be used as an AI chip, or the GPU module 1204 can be used as an AI system module .

[0291] The configuration shown in this embodiment can be appropriately combined with the configurations shown in other embodiments, examples, etc.​​​ It can be used.

[0292] (Embodiment 6) In this embodiment, an application example of a memory device using the semiconductor device shown in the previous embodiment will be described. The semiconductor device shown in the previous embodiment can be applied to, for example, memory devices of various electronic devices (such as information terminals, computers, smartphones, e-book terminals, digital cameras (including video cameras), video recording / playback devices, navigation systems, etc.). Here, the computer includes not only tablet-type computers, notebook-type computers, and desktop-type computers but also large-scale computers such as server systems. Or, the semiconductor device shown in the previous embodiment can be applied to various removable storage devices such as memory cards (e.g., SD cards), USB memories, and SSDs (solid-state drives). Some configuration examples of the removable storage device are schematically shown in FIG. 11. For example, the semiconductor device shown in the previous embodiment is processed into a packaged memory chip and used in various storage devices and removable memories. Here, the computer includes not only tablet-type computers, notebook-type computers, and desktop-type computers but also large-scale computers such as server systems. Or, the semiconductor device shown in the previous embodiment can be applied to various removable storage devices such as memory cards (e.g., SD cards), USB memories, and SSDs (solid-state drives). Some configuration examples of the removable storage device are schematically shown in FIG. 11. For example, the semiconductor device shown in the previous embodiment is processed into a packaged memory chip and used in various storage devices and removable memories. terminals, computers, smartphones, e-book terminals, digital cameras (including video cameras), video recording / playback devices, navigation systems, etc.). Here, the computer includes not only tablet-type computers, notebook-type computers, and desktop-type computers but also large-scale computers such as server systems. Or, the semiconductor device shown in the previous embodiment can be applied to various removable storage devices such as memory cards (e.g., SD cards), USB memories, and SSDs (solid-state drives). Some configuration examples of the removable storage device are schematically shown in FIG. 11. For example, the semiconductor device shown in the previous embodiment is processed into a packaged memory chip and used in various storage devices and removable memories. including), video recording / playback devices, navigation systems, etc.). Here, the computer includes not only tablet-type computers, notebook-type computers, and desktop-type computers but also large-scale computers such as server systems. Or, the semiconductor device shown in the previous embodiment can be applied to various removable storage devices such as memory cards (e.g., SD cards), USB memories, and SSDs (solid-state drives). Some configuration examples of the removable storage device are schematically shown in FIG. 11. For example, the semiconductor device shown in the previous embodiment is processed into a packaged memory chip and used in various storage devices and removable memories. Here, the computer includes not only tablet-type computers, notebook-type computers, and desktop-type computers but also large-scale computers such as server systems. Or, the semiconductor device shown in the previous embodiment can be applied to various removable storage devices such as memory cards (e.g., SD cards), USB memories, and SSDs (solid-state drives). Some configuration examples of the removable storage device are schematically shown in FIG. 11. For example, the semiconductor device shown in the previous embodiment is processed into a packaged memory chip and used in various storage devices and removable memories. In addition to desktop-type computers, large-scale computers such as server systems are also included. Or, the semiconductor device shown in the previous embodiment can be applied to various removable storage devices such as memory cards (e.g., SD cards), USB memories, and SSDs (solid-state drives). Some configuration examples of the removable storage device are schematically shown in FIG. 11. For example, the semiconductor device shown in the previous embodiment is processed into a packaged memory chip and used in various storage devices and removable memories. In addition to desktop-type computers, large-scale computers such as server systems are also included. Or, the semiconductor device shown in the previous embodiment can be applied to various removable storage devices such as memory cards (e.g., SD cards), USB memories, and SSDs (solid-state drives). Some configuration examples of the removable storage device are schematically shown in FIG. 11. For example, the semiconductor device shown in the previous embodiment is processed into a packaged memory chip and used in various storage devices and removable memories. In addition to desktop-type computers, large-scale computers such as server systems are also included. Or, the semiconductor device shown in the previous embodiment can be applied to various removable storage devices such as memory cards (e.g., SD cards), USB memories, and SSDs (solid-state drives). Some configuration examples of the removable storage device are schematically shown in FIG. 11. For example, the semiconductor device shown in the previous embodiment is processed into a packaged memory chip and used in various storage devices and removable memories. In addition to desktop-type computers, large-scale computers such as server systems are also included. Or, the semiconductor device shown in the previous embodiment can be applied to various removable storage devices such as memory cards (e.g., SD cards), USB memories, and SSDs (solid-state drives). Some configuration examples of the removable storage device are schematically shown in FIG. 11. For example, the semiconductor device shown in the previous embodiment is processed into a packaged memory chip and used in various storage devices and removable memories. In addition to desktop-type computers, large-scale computers such as server systems are also included. Or, the semiconductor device shown in the previous embodiment can be applied to various removable storage devices such as memory cards (e.g., SD cards), USB memories, and SSDs (solid-state drives). Some configuration examples of the removable storage device are schematically shown in FIG. 11. For example, the semiconductor device shown in the previous embodiment is processed into a packaged memory chip and used in various storage devices and removable memories. In addition to desktop-type computers, large-scale computers such as server systems are also included. Or, the semiconductor device shown in the previous embodiment can be applied to various removable storage devices such as memory cards (e.g., SD cards), USB memories, and SSDs (solid-state drives). Some configuration examples of the removable storage device are schematically shown in FIG. 11. For example, the semiconductor device shown in the previous embodiment is processed into a packaged memory chip and used in various storage devices and removable memories.

[0293] FIG. 11(A) is a schematic diagram of a USB memory. The USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a substrate 1104. The substrate 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the substrate 1104. The semiconductor device shown in the previous embodiment can be incorporated into the memory chip 1105 or the like. FIG. 11(A) is a schematic diagram of a USB memory. The USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a substrate 1104. The substrate 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the substrate 1104. The semiconductor device shown in the previous embodiment can be incorporated into the memory chip 1105 or the like. FIG. 11(A) is a schematic diagram of a USB memory. The USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a substrate 1104. The substrate 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the substrate 1104. The semiconductor device shown in the previous embodiment can be incorporated into the memory chip 1105 or the like. FIG. 11(A) is a schematic diagram of a USB memory. The USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a substrate 1104. The substrate 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the substrate 1104. The semiconductor device shown in the previous embodiment can be incorporated into the memory chip 1105 or the like. FIG. 11(A) is a schematic diagram of a USB memory. The USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a substrate 1104. The substrate 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the substrate 1104. The semiconductor device shown in the previous embodiment can be incorporated into the memory chip 1105 or the like.

[0294] FIG. 11(B) is a schematic diagram of the appearance of an SD card, and FIG. 11(C) is the internal It is a schematic diagram of the structure. The SD card 1110 has a housing 1111, a connector 1112, and a base board 1113. The substrate 1113 is housed in the housing 1111. For example, on the substrate 11 13, a memory chip 1114 and a controller chip 1115 are attached. By providing a memory chip 1114 also on the back side of the substrate 1113, the capacity of the SD card 1110 can be increased. Also, a wireless chip having a wireless communication function may be provided on the substrate 1113 . Thereby, by wireless communication between the host device and the SD card 1110, data of the memory chip 1114 can be read and written. A semiconductor device shown in the previous embodiments can be incorporated into the memory chip 1114 and the like.

[0295] FIG. 11(D) is a schematic diagram of the appearance of the SSD, and FIG. 11(E) is a schematic diagram of the internal structure of the SSD. The SSD 1150 has a housing 1151, a connector 1152, and a substrate 1153 . The substrate 1153 is housed in the housing 1151. For example, on the substrate 1153, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are attached . The memory chip 1155 is a work memory of the controller chip 1156, and for example, a DOSRAM chip may be used. By providing a memory chip 11 54 also on the back side of the substrate 1153, the capacity of the SSD 1150 can be increased. A semiconductor device shown in the previous embodiments can be incorporated into the memory chip 115 4 and the like.

[0296] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments, examples, etc.

[0297] (Embodiment 7)​​ The semiconductor device according to one aspect of the present invention can be used for processors such as CPUs and GPUs, or chips. FIG. 12 shows a specific example of an electronic device including a processor such as a CPU or GPU, or a chip according to one aspect of the present invention.

[0298] <Electronic device / system> The GPU or chip according to one aspect of the present invention can be mounted on various electronic devices. Examples of electronic devices include television devices, desktop or notebook personal computers, monitors for computers, etc., digital signage, large game machines such as pachinko machines, etc., which have relatively large screens. In addition to these, there are also digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, portable information terminals, audio playback devices, etc. Further, by providing the integrated circuit or chip according to one aspect of the present invention in an electronic device, it is possible to install artificial intelligence in the electronic device.

[0299] The electronic device according to one aspect of the present invention may have an antenna. By receiving signals with the antenna, it is possible to display images, information, etc. on the display unit. Further, when the electronic device has an antenna and a secondary battery, the antenna may be used for non-contact power transmission.

[0300] The electronic device according to one aspect of the present invention may have a sensor (including a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotation number, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays).

[0301] An electronic device according to an aspect of the present invention can have various functions. For example, various information (such as still images, moving images, text images, etc.) can be displayed on the display unit, a touch panel function, a camera , a function of displaying a calendar, date, or time, etc., a function of executing various software (programs), a wireless communication function, a function of reading a program or data recorded on a recording medium , etc. can be provided. FIG. 12 shows an example of an electronic device. FIG. 12 shows an example of an electronic device.

[0302] [Mobile phone] FIG. 12(A) shows a mobile phone (smartphone), which is a type of information terminal. The information terminal 5500 has a housing 5510 and a display unit 5511. As an input interface, a touch panel is provided on the display unit 5511, and buttons are provided on the housing 551 0. The information terminal 5500 can execute an application using artificial intelligence by applying a chip according to an aspect of the present invention. Examples of applications using artificial intelligence

[0303] include, for example, an application that recognizes a conversation and displays the conversation content on the display unit 5511, an application that recognizes characters, figures, etc. input by a user on the touch panel provided on the display unit 5511 and displays them on the display unit 5511, and an application that performs biometric authentication such as fingerprint or voiceprint . For example, an application that recognizes a conversation and displays the conversation content on the display unit 5511, an application that recognizes characters, figures, etc. input by a user on the touch panel provided on the display unit 5511 and displays them on the display unit 5511, and an application that performs biometric authentication such as fingerprint or voiceprint include, for example, an application that recognizes a conversation and displays the conversation content on the display unit 5511, an application that recognizes characters, figures, etc. input by a user on the touch panel provided on the display unit 5511 and displays them on the display unit 5511, and an application that performs biometric authentication such as fingerprint or voiceprint . Examples include applications for performing biometric authentication such as fingerprint or voiceprint.

[0304] [Information terminal] FIG. 12(B) shows a desktop-type information terminal 5300. The desktop type information terminal 5300 has a main body 5301 of the information terminal, a display 5302, and a keyboard 5303.

[0305] Similar to the information terminal 5500 described above, the desktop information terminal 5300 can execute applications utilizing artificial intelligence by applying a chip according to one aspect of the present invention. Examples of applications utilizing artificial intelligence include, for example, design support software, writing correction software, menu automatic generation software, and the like. Further, by using the desktop type information terminal 5300, new artificial intelligence can be developed.

[0306] In the above description, smartphones and desktop information terminals are exemplified as electronic devices and are illustrated in FIGS. 12(A) and (B), respectively. However, information terminals other than smartphones and desktop type information terminals can be applied. Examples of information terminals other than smartphones and desktop type information terminals include, for example, PDAs (Personal Digital Assistants), notebook type information terminals, workstations, and the like.

[0307] [Household Appliance] FIG. 12(C) shows an electric refrigerator-freezer 5800, which is an example of a household appliance. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

[0308] By applying a chip according to one aspect of the present invention to the electric refrigerator-freezer 5800, an electric refrigerator-freezer 5800 having artificial intelligence can be realized. By utilizing artificial intelligence, the electric refrigerator-freezer 5800 can have a function of automatically generating a menu based on the food ingredients stored in the electric refrigerator-freezer 5800, the expiration dates of the food ingredients, and the like, and the food ingredients stored in the electric refrigerator-freezer 5800. It can have functions such as automatically adjusting to a temperature suitable for the ingredients.

[0309] In this example, an electric refrigerator was described as an electric appliance, but for other electric appliances such as, for example, a vacuum cleaner, a microwave oven, an electric oven, a rice cooker, a water heater, an IH cooker , a water server, air-conditioning appliances including an air conditioner, a washing machine, a dryer, an audio-visual device, etc. can be mentioned.

[0310] [Game console] FIG. 12(D) shows a portable game console 5200 which is an example of a game console. The portable game console has a housing 5201, a display unit 5202, buttons 5203, etc.

[0311] By applying the GPU or chip of one aspect of the present invention to the portable game console 5200, a portable game console 5200 with low power consumption can be realized. Also, due to the low power consumption, heat generation from the circuit can be reduced, so the influence on the circuit itself, peripheral circuits, and modules due to heat generation can be minimized.

[0312] Furthermore, by applying the GPU or chip of one aspect of the present invention to the portable game console 5200 a portable game console 5200 having artificial intelligence can be realized.

[0313] Originally, the expression of the progress of the game, the speech and actions of the creatures appearing in the game, the phenomena occurring in the game, etc. is determined by the program that the game has, but by applying artificial intelligence to the portable game console 520 0, expressions not limited to the game program become possible. For example, the content asked by the player, the progress of the game, the time, the creatures appearing in the game Expressions such as changes in the behavior of a person can be made possible.

[0314] In addition, when playing a game that requires multiple players on the portable game machine 5200, since an artificial intelligence can anthropomorphically configure game players, by setting the opponent to be a game player by the artificial intelligence, a game can be played even by one person. to the game player by the artificial intelligence, a game can be played even by one person. to the game player by the artificial intelligence, a game can be played even by one person.

[0315] In FIG. 12(D), a portable game machine is illustrated as an example of a game machine, but the game machine to which the GPU or chip of one aspect of the present invention is applied is not limited thereto. Examples of the game machine to which the GPU or chip of one aspect of the present invention is applied include, for example, a home stationary game machine, an arcade game machine installed in an entertainment facility (such as a game center, an amusement park, etc.), a pitching machine for batting practice installed in a sports facility, and the like. to the game player by the artificial intelligence, a game can be played even by one person. to the game player by the artificial intelligence, a game can be played even by one person. to the game player by the artificial intelligence, a game can be played even by one person. to the game player by the artificial intelligence, a game can be played even by one person.

[0316] [Mobile body] The GPU or chip of one aspect of the present invention can be applied to a moving body, an automobile, and the periphery of the driver's seat of the automobile. The GPU or chip of one aspect of the present invention can be applied to a moving body, an automobile, and the periphery of the driver's seat of the automobile.

[0317] FIG. 12(E1) shows an automobile 5700 which is an example of a moving body, and FIG. 12(E2) is a view showing the periphery of the windshield in the interior of the automobile. In FIG. 12(E1), in addition to the display panels 5701, 5702, and 5703 attached to the dashboard, the display panel 5704 attached to the pillar is illustrated. The GPU or chip of one aspect of the present invention can be applied to a moving body, an automobile, and the periphery of the driver's seat of the automobile. The GPU or chip of one aspect of the present invention can be applied to a moving body, an automobile, and the periphery of the driver's seat of the automobile. The GPU or chip of one aspect of the present invention can be applied to a moving body, an automobile, and the periphery of the driver's seat of the automobile.

[0318] The display panels 5701 to 5703 provide various information by displaying a speedometer, a tachometer, a travel distance, a fuel gauge, a gear state, an air conditioner setting, and the like. The GPU or chip of one aspect of the present invention can be applied to a moving body, an automobile, and the periphery of the driver's seat of the automobile. It is possible. Also, the display items and layout displayed on the display panel can be appropriately changed according to the user's preferences, and it is possible to enhance the designability. The display panel 5701 to the display panel 5703 can also be used as a lighting device.

[0319] On the display panel 5704, the image from an imaging device (not shown) provided in the vehicle 5700 can be projected to complement the visual field (blind spot) blocked by the pillar. That is, by displaying the image from the imaging device provided outside the vehicle 5700 , the blind spot can be compensated and the safety can be enhanced. Also, by projecting the image that complements the invisible part, it is possible to perform safety confirmation more naturally without a sense of discomfort. The display panel 57 04 can also be used as a lighting device.

[0320] Since the GPU or chip of one aspect of the present invention can be applied as a component of artificial intelligence, for example, the chip can be used in the automatic driving system of the vehicle 5700. Also, the chip can be used in a system that performs road guidance, danger prediction, etc. The display panel 57 01 to the display panel 5704 may be configured to display information such as road guidance and danger prediction.

[0321] In the above description, the vehicle is described as an example of the moving body, but the moving body is not limited to the vehicle. For example, as the moving body, a train, a monorail, a ship, an aircraft (helicopter, unmanned aerial vehicle (drone), airplane, rocket), etc. can also be mentioned, and the chip of one aspect of the present invention can be applied to these moving bodies to provide a system using artificial intelligence.

[0322] [Broadcast system] The GPU or chip according to one aspect of the present invention can be applied to a broadcast system.

[0323] FIG. 12(F) schematically shows data transmission in a broadcast system. Specifically, , FIG. 12(F) shows the path of the radio wave (broadcast signal) transmitted from the broadcasting station 5680 until it reaches the television reception device (TV) 5600 of each household. The TV 5600 is equipped with a reception device (not shown), and the broadcast signal received by the antenna 5650 is transmitted to the TV 5600 via the reception device.

[0324] In FIG. 12(F), the antenna 5650 is shown as a UHF (Ultra High Frequency) antenna, but as the antenna 5650, a BS·110°CS antenna, a CS antenna, etc. can also be applied.

[0325] The radio waves 5675A and 5675B are broadcast signals for terrestrial digital television broadcasting, and the radio tower 5670 amplifies the received radio wave 5675A and transmits the radio wave 5675B. In each household, by receiving the radio wave 5675B with the antenna 5650, terrestrial digital television broadcasting can be viewed on the TV 5600 . Note that the broadcast system is not limited to the terrestrial digital television broadcasting shown in FIG. 12(F), and it may also be satellite broadcasting using artificial satellites, data broadcasting using optical fibers, etc. The above-described broadcast system may be a broadcast system using artificial intelligence by applying the chip according to one aspect of the present invention. When transmitting broadcast data from the broadcasting station 5680 to the TV 5600 of each household, the broadcast data is compressed by an encoder, and the antenna 5650 transmits the broadcast

[0326] data. ​​When data is received, the decoder of the receiving device included in the TV 5600 restores the broadcast data. By using artificial intelligence, for example, in motion compensation prediction which is one of the compression methods of the encoder, it is possible to recognize the display pattern included in the display image. Also, it is possible to perform in-frame prediction using artificial intelligence. Also, for example, when receiving broadcast data with low resolution and displaying the broadcast data on the TV 5600 with high resolution, in restoring the broadcast data by the decoder, interpolation processing of the image such as up-conversion can be performed. The broadcast system using artificial intelligence described above is suitable for ultra-high-definition television (UHDTV: 4K, 8K) broadcasts in which the amount of broadcast data increases. Also, as an application of artificial intelligence on the TV 5600 side, for example, a recording device having artificial intelligence may be provided in the TV 5600. By configuring it in this way, by having the artificial intelligence learn the user's preferences in the recording device, it is possible to automatically record programs according to the user's preferences. The electronic devices, the functions of the electronic devices, application examples of artificial intelligence, and the effects described in this embodiment can be appropriately combined with the descriptions of other electronic devices. This embodiment can be implemented in appropriate combination with the configurations described in other embodiments, examples, etc.

Example

[0327] When receiving broadcast data with low resolution and displaying the broadcast data on the TV 5600 with high resolution, in restoring the broadcast data by the decoder, interpolation processing of the image such as up-conversion can be performed. The broadcast system using artificial intelligence described above is suitable for ultra-high-definition television (UHDTV: 4K, 8K) broadcasts in which the amount of broadcast data increases.

[0328] Also, as an application of artificial intelligence on the TV 5600 side, for example, a recording device having artificial intelligence may be provided in the TV 5600. By configuring it in this way, by having the artificial intelligence learn the user's preferences in the recording device, it is possible to automatically record programs according to the user's preferences. The electronic devices, the functions of the electronic devices, application examples of artificial intelligence, and the effects described in this embodiment can be appropriately combined with the descriptions of other electronic devices. This embodiment can be implemented in appropriate combination with the configurations described in other embodiments, examples, etc.

Example

[0329] In this example, a transistor (referred to as sample A1) according to one aspect of the present invention was fabricated, and gold The electronic devices, the functions of the electronic devices, application examples of artificial intelligence, and the effects described in this embodiment can be appropriately combined with the descriptions of other electronic devices.

[0330] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments, examples, etc.

Example

Example

[0331] In this example, a transistor (referred to as sample A1) according to one aspect of the present invention was fabricated, and gold A cross-sectional TEM image of the vicinity of the channel-forming region of the oxide was obtained. For comparison, samples A2 and A3 were prepared with manufacturing methods different from that of sample A1, and cross-sectional TEM images of the vicinity of the channel-forming region of the metal oxide were obtained. The manufacturing methods of samples A1 to A3 will be described below. First, the manufacturing method of sample A1 will be described. On the substrate, a silicon oxide film and a first aluminum oxide film were successively formed.

[0332] Next, a first tungsten film was formed on the first aluminum oxide film by sputtering. Then, the first tungsten film was processed by lithography to form a conductor. Next, a first silicon oxynitride film was formed on the first aluminum oxide film and the above conductor by CVD. Then, by the first CMP process, the first silicon oxynitride film was polished until it reached the upper surface of the conductor.

[0333] Next, a second aluminum oxide film was formed on the first silicon oxynitride film and the above conductor by ALD with a film thickness of 5 nm, and a second silicon oxynitride film was formed on the second aluminum oxide film by CVD with a film thickness of 35 nm. Then, planarization polishing was performed on the second silicon oxynitride film.

[0334] Next, an oxide film that becomes the first oxide and an oxide film that becomes the second oxide were continuously formed. As the oxide film that becomes the first oxide, In-Ga-Zn oxide was formed by sputtering with a thickness of 5 nm.

[0335] Next, on the first aluminum oxide film and the above conductor, a first silicon oxynitride film was formed by CVD. Then, by the first CMP process, the first silicon oxynitride film was polished until it reached the upper surface of the conductor.

[0336] Next, on the first silicon oxynitride film and the above conductor, a second aluminum oxide film was formed by ALD with a film thickness of 5 nm, and a second silicon oxynitride film was formed on the second aluminum oxide film by CVD with a film thickness of 35 nm. Then, planarization polishing was performed on the second silicon oxynitride film. Next, an oxide film that becomes the first oxide and an oxide film that becomes the second oxide were continuously formed. As the oxide film that becomes the first oxide, In-Ga-Zn oxide was formed by sputtering with a thickness of 5

[0337] nm. ​​​​​​The oxide film that becomes the first oxide is In:Ga:Zn=1:3:4[ An In-Ga-Zn oxide target with a [atomic ratio] was used, and the oxygen gas flow rate was 45 sccm. The film was formed under conditions of a pressure of 0.7 Pa and a substrate temperature of 200°C.

[0338] The second oxide film is formed by sputtering an In-Ga-Zn oxide film. The oxide film to be the second oxide was formed with a thickness of 20 nm. Using an In-Ga-Zn oxide target with an atomic ratio of 2:4.1, argon gas flow Conditions: flow rate of 30 sccm, oxygen gas flow rate of 15 sccm, pressure of 0.7 Pa, substrate temperature of 200°C The film was formed as follows.

[0339] Next, a first heat treatment was carried out in a nitrogen-containing atmosphere at a temperature of 400°C. The treatment was carried out for 1 hour, followed by treatment in an oxygen-containing atmosphere at 400°C for 1 hour. .

[0340] Next, a tantalum nitride film was formed on the oxide film that would become the second oxide. Processing the tantalum film, the oxide film that will become the second oxide, and the oxide film that will become the first oxide. The second oxide and the first oxide were formed.

[0341] Next, a third aluminum oxide film and a third silicon oxynitride film were formed in this order. Thereafter, the upper surface of the third silicon oxynitride film was flattened by a second CMP process.

[0342] Next, the third silicon oxynitride film is processed to form a third oxide film. An opening was formed in the opening, reaching the top surface of the aluminum oxide film. The aluminum film and a part of the tantalum nitride film were etched.

[0343] Next, as the oxide film that becomes the third oxide, In-Ga-Z n oxide was formed with a film thickness of 5 nm. The oxide film that becomes the third oxide has In:Ga:Zn = 4:2:4.1 [atomic ratio]. Using an In-Ga-Zn oxide target, an oxygen gas flow rate of 45 sccm, a pressure of 0.7 Pa, and a substrate temperature of 130 °C, the film was formed.

[0344] Next, on the oxide film that becomes the third oxide, a fourth silicon oxynitride film was formed by CVD method. A titanium nitride film was formed on the fourth silicon oxynitride film, and on the titanium nitride film a second tungsten film was formed.

[0345] Next, by the third CMP process, until reaching the upper surface of the third silicon oxynitride film, the second tungsten film, the titanium nitride film, the fourth silicon oxynitride film, and the oxide film that becomes the third oxide were polished to form the third oxide.

[0346] Thus, sample A1 was fabricated.

[0347] Next, the method for fabricating sample A2 will be described.

[0348] On the substrate, a silicon oxide film and a first aluminum oxide film were sequentially formed.

[0349] Next, on the first aluminum oxide film, a first silicon oxynitride film was formed by CVD method. Next, a first tungsten film was formed by sputtering method. After that, by lithography method, the first tungsten film was processed to form the first hard mask. formed.

[0350] Next, using the first hard mask, the first silicon oxynitride film was processed to form an opening in the first silicon oxynitride film.

[0351] Next, a first tantalum nitride film was formed by sputtering, a first titanium nitride film was formed on the first tantalum nitride film by ALD, and a second tungsten film was formed on the first titanium nitride film by CVD.

[0352] Next, by the first CMP process, the second tungsten film, the first titanium nitride film, and the first tantalum nitride film were polished until reaching the upper surface of the first silicon oxynitride film, and the first hard mask was removed. Thus, a conductor was formed within the opening of the first silicon oxynitride film.

[0353] Next, a second silicon oxynitride film was formed at a film thickness of 10 nm by CVD on the first silicon oxynitride film and the above-mentioned conductor, a hafnium oxide film was formed at a film thickness of 20 nm by ALD on the second silicon oxynitride film, and a third silicon oxynitride film was formed at a film thickness of 30 nm by CVD on the hafnium oxide film.

[0354] Next, an oxide film that becomes the first oxide and an oxide film that becomes the second oxide were formed continuously. As the oxide film that becomes the first oxide, an In-Ga-Zn oxide was formed at a film thickness of 5 nm by sputtering. The oxide film that becomes the first oxide was formed under the same conditions as sample A1.

[0355] As the oxide film that becomes the second oxide, an In-Ga-Zn oxide was formed by sputtering. A film was formed with a thickness of 15 nm. The oxide film serving as the second oxide was formed using an In-Ga-Zn oxide target with an atomic ratio of In:Ga:Zn = 4: 2:4.1 at an argon gas flow rate of 40 sccm, an oxygen gas flow rate of 5 sccm, a pressure of 0.7 Pa, and a substrate temperature of 130 °C. The film was formed under these conditions.

[0356] Next, the first heat treatment was performed. The first heat treatment was carried out at a temperature of 400 °C for 1 hour in an atmosphere containing nitrogen, and then at a temperature of 400 °C for 1 hour in an atmosphere containing oxygen.

[0357] Next, a second tantalum nitride film was formed on the oxide film serving as the second oxide. Thereafter, the second tantalum nitride film, the oxide film serving as the second oxide, and the oxide film serving as the first oxide were processed to form the first oxide and the second oxide.

[0358] Next, as the oxide film serving as the third oxide, an In-Ga-Zn oxide was formed with a thickness of 5 nm by sputtering. The oxide film serving as the third oxide was formed under the same conditions as sample A1. Thereafter, a fourth silicon oxynitride film was formed on the oxide film serving as the third oxide by CVD. Thereafter, the oxide film serving as the third oxide was processed to form the third oxide.

[0359] Thus, sample A2 was fabricated.

[0360] The method for fabricating sample A3 will be described below. The steps until an opening is formed in the first silicon oxynitride film and a conductor is formed in the opening are the same as those of sample A2.

[0361] Next, a second oxide was formed by CVD on the first silicon oxynitride film and the above-mentioned conductor.​​​​​​​​​​ A silicon oxynitride film was formed with a film thickness of 5 nm. On the second silicon oxynitride film, a hafnium oxide film was formed with a film thickness of 10 nm by ALD method. On the hafnium oxide film, a third silicon oxynitride film was formed with a film thickness of 30 nm by CVD method.

[0362] Next, the oxide film serving as the first oxide and the oxide film serving as the second oxide were formed continuously. By sputtering method, indium-gallium-zinc oxide was formed with a film thickness of 5 nm as the oxide film serving as the first oxide, and indium-gallium-zinc oxide was formed with a film thickness of 15 nm as the oxide film serving as the second oxide. Note that the oxide film serving as the first oxide and the oxide film serving as the second oxide were formed under the same conditions as those of sample A1.

[0363] Next, the first heat treatment was performed. The first heat treatment was carried out at a temperature of 400 °C for 1 hour in an atmosphere containing nitrogen, and then at a temperature of 400 °C for 1 hour in an atmosphere containing oxygen.

[0364] Next, a second tantalum nitride film was formed on the oxide film serving as the second oxide. Then, by processing the second tantalum nitride film, the oxide film serving as the second oxide, and the oxide film serving as the first oxide, the first oxide and the second oxide were formed.

[0365] Next, indium-gallium-zinc oxide was formed with a film thickness of 5 nm as the oxide film serving as the third oxide by sputtering method. The oxide film serving as the third oxide was formed under the same conditions as those of sample A1. Then, a fourth silicon oxynitride film was formed on the oxide film serving as the third oxide by CVD method. Then, by processing the oxide film serving as the third oxide, the third oxide was formed. ​

[0366] As described above, Sample A3 was fabricated.

[0367] The crystallinity of the oxide was evaluated for the fabricated Samples A1 to A3. Fig. 13 shows a high-resolution TEM image of the cross-section of the oxide observed from a direction substantially parallel to the plane. The high-resolution TEM image was observed using a spherical aberration corrector function. For the acquisition of the high-resolution TEM image, an electron beam with an acceleration voltage of 200 kV was irradiated using a JEOL JEM-ARM200F atomic-resolution analytical electron microscope manufactured by JEOL Ltd.

[0368] Fig. 13(A) is a TEM image of the cross-section of Sample A1, Fig. 13(B) is a TEM image of the cross-section of Sample A2 and Fig. 13(C) is a TEM image of the cross-section of Sample A3. The bright regions observed above and below Fig. 13 are silicon oxynitride films, and the dark region observed near the center of Fig. 13 is an oxide. Among the dark regions, the first oxide is located at the bottom, the second oxide is located in the center, and the third oxide is located at the top . In Fig. 13(A), a region with an aligned lattice arrangement was observed over a wide range from the second oxide to the third oxide.

[0369] This example can be implemented in appropriate combination with at least a part of it and other embodiments described in this specification.

Description of Reference Numerals

[0370] 50: film, 51: film, 52: oxide film, 53: region, 54: region, 100: capacitor element, 11 ​​​​​​0: Conductor, 112: Conductor, 120: Conductor, 130: Insulator, 150: Insulator, 20 0: Transistor, 200A: Transistor, 205: Conductor, 210: Insulator, 212 : Insulator, 214: Insulator, 216: Insulator, 218: Conductor, 222: Insulator, 224 : Insulator, 230: Oxide, 230a: Oxide, 230b: Oxide, 230c: Oxide, 231: Region, 231a: Region, 231b: Region, 234: Region, 240: Conductor, 24 0a: Conductor, 240b: Conductor, 242: Conductor, 242a: Conductor, 242b: Conduc tor, 241: Insulator, 241a: Insulator, 241b: Insulator, 243: Region, 243a: Region, 243b: Region, 244: Insulator, 245: Insulator, 246: Conductor, 250: Ins ulator, 254: Insulator, 260: Conductor, 260a: Conductor, 260b: Conductor, 274 : Insulator, 276: Insulator, 280: Insulator, 281: Insulator, 283: Insulator, 300 : Transistor, 311: Substrate, 313: Semiconductor Region, 314a: Low-Resistance Region, 314b : Low-Resistance Region, 315: Insulator, 316: Conductor, 320: Insulator, 322: Insulator, 3 24: Insulator, 326: Insulator, 328: Conductor, 330: Conductor, 350: Insulator, 3 52: Insulator, 354: Insulator, 356: Conductor, 400: Transistor, 405: Conduc tor, 430c: Oxide, 431a: Oxide, 431b: Oxide, 432a: Oxide, 43 2b: Oxide, 440: Conductor, 440a: Conductor, 440b: Conductor, 442: Conductor 、442a: Conductor, 442b: Conductor, 450: Insulator, 460: Conductor, 460a: Conductor, 460b: Conductor, 1001: Wiring, 1002: Wiring, 1003: Wiring, 100 4: Wiring, 1005: Wiring, 1006: Wiring, 1007: Wiring, 1008: Wiring, 100 9: Wiring, 1010: Wiring

Claims

1. A semiconductor device comprising a first transistor, a second transistor having a channel formation region in an oxide semiconductor layer, and a capacitor element, wherein the second transistor has a first gate electrode and a second gate electrode overlapping the oxide semiconductor layer, the second transistor has a first insulating layer above the second gate electrode, the first insulating layer has a first conductive layer above it, the first conductive layer is electrically connected to the oxide semiconductor layer and functions as one electrode of the capacitor element, the first conductive layer has a second insulating layer above it, the second insulating layer has a second conductive layer above it, the second conductive layer functions as the other electrode of the capacitor element, the gate electrode of the first transistor is electrically connected to the first conductive layer, and the second conductive layer has a region overlapping the gate electrode of the first transistor.

2. The semiconductor device according to claim 1, wherein the oxide semiconductor layer contains a crystalline metal oxide.

3. The semiconductor device according to claim 1 or claim 2, wherein an average length (RSm) of roughness curve elements on the upper surface of the first gate electrode is 60 nm or more, and a maximum height (Rz) of the roughness curve is greater than 6.0 nm.

4. The semiconductor device according to claim 1 or claim 2, wherein an average length (RSm) of roughness curve elements on the upper surface of the first gate electrode is less than 60 nm, and a maximum height (Rz) of the roughness curve is 6.0 nm or less.

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