Imaging apparatus

Abstract

To provide an imaging apparatus having an image processing function and capable of high-speed operation.SOLUTION: In an imaging apparatus having an additional function such as image processing, image data acquired in an imaging operation is binarized in a pixel unit, and product-sum operation is performed by using the binarized data. A memory circuit is provided in the pixel portion, and holds a weighting coefficient used for the product-sum operation. Therefore, the calculation can be performed without reading the weighting coefficient from the outside every time, and the power consumption can be reduced. In addition, by laminating the pixel circuit, the memory circuit, and the like, the product-sum operation circuit, and the like, the wiring length between the circuits can be reduced, and low-power consumption operation and high-speed operation can be performed.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] One aspect of the present invention relates to an imaging device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. The technical field of one aspect of the invention disclosed in this specification or the like relates to an article, a method, or a manufacturing method. Or, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one aspect of the present invention disclosed in this specification include a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, a power storage device, a storage device, an imaging device, an operation method thereof, or a manufacturing method thereof.

[0003] Note that in this specification or the like, the semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one aspect of the semiconductor device. In addition, a storage device, a display device, an imaging device, and an electronic device may include a semiconductor device.

Background Art

[0004] Techniques for configuring a transistor using an oxide semiconductor thin film formed on a substrate have attracted attention. For example, Patent Document 1 discloses an imaging device configured to use a transistor having an extremely low off-current with an oxide semiconductor in a pixel circuit.

[0005] In addition, Patent Document 2 discloses a technique for adding an arithmetic function to an imaging device.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0007] In imaging devices mounted on mobile devices and the like, the function of being able to acquire high-resolution images has become widespread. In the next generation, it is required to further equip the imaging device with more intelligent functions.

[0008] Image data (analog data) acquired by an imaging device is converted into digital data, and after being taken out externally, image processing is performed as needed. If the processing can be performed within the imaging device, the cooperation with external devices will be faster, and the convenience for the user will be improved. Also, the load and power consumption of peripheral devices and the like can be reduced.

[0009] In addition, when adding functions to an imaging device, it is preferable to stack elements such as circuits that increase. For example, by providing a plurality of circuits so as to overlap with the pixel circuit, an increase in area can be suppressed, and a highly functional and compact imaging device can be formed. Also, between the stacked circuits, the wiring length can be shortened, and high-speed and low-power consumption operation can be realized.

[0010] Therefore, one of the objects of one aspect of the present invention is to provide an imaging device capable of performing image processing. Or, one of the objects is to provide a highly functional and compact imaging device. Or, one of the objects is to provide an imaging device capable of performing high-speed operation. Or, one of the objects is to provide an imaging device with low power consumption. Or, one of the objects is to provide a highly reliable imaging device. Or, one of the objects is to provide a novel imaging device and the like. Or, one of the objects is to provide a driving method for the above imaging device. Or, one of the objects is to provide a novel semiconductor device and the like.

[0011] Note that the description of these problems does not preclude the existence of other problems. Note that one aspect of the present invention does not need to solve all of these problems. Note that other problems will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract these other problems from the description in the specification, drawings, claims, etc.

Means for Solving the Problems

[0012] One aspect of the present invention relates to an imaging device having an image processing function and capable of high-speed operation.

[0013] One aspect of the present invention is an imaging device having a plurality of pixel blocks, wherein each pixel block has a first layer and a second layer, the first layer has an area overlapping with the second layer, the pixel block has a plurality of pixel circuits and a plurality of first storage circuits in the first layer, and a plurality of product-sum operation circuits, a plurality of first binarization circuits, and a plurality of second binarization circuits in the second layer, and the pixel circuits and the first storage circuits are imaging devices having transistors with metal oxides in the channel formation region.

[0014] Another aspect of the present invention is an imaging device having a plurality of pixel blocks, wherein each pixel block has a first layer, a second layer, and a third layer, the first layer is located between the second layer and the third layer, or the third layer is located between the first layer and the second layer, the first to third layers have areas overlapping with each other, the pixel block has a plurality of pixel circuits in the first layer, a plurality of product-sum operation circuits, a plurality of first binarization circuits, and a plurality of second binarization circuits in the second layer, and a plurality of first storage circuits in the third layer, and the pixel circuits and the first storage circuits are imaging devices having transistors with metal oxides in the channel formation region.

[0015] The product-sum operation circuit, the first binarization circuit, and the second binarization circuit preferably have transistors with silicon in the channel formation region.

[0016] The number of pixel circuits is the same as that of the first binarization circuits, and each pixel circuit can be electrically connected to one first binarization circuit.

[0017] One first binarization circuit can be electrically connected to a plurality of product-sum operation circuits.

[0018] One first memory circuit can be electrically connected to a plurality of product-sum operation circuits.

[0019] The number of product-sum operation circuits is the same as that of the second binarization circuits, and each product-sum operation circuit can be electrically connected to one second binarization circuit.

[0020] The drive circuits of the pixel circuits and the drive circuits of the first memory circuits can be provided in the second layer.

[0021] Furthermore, it may have a second memory circuit, the input terminal of the second memory circuit is electrically connected to a plurality of second binarization circuits, and the output terminal of the second memory circuit is electrically connected to a plurality of product-sum operation circuits.

[0022] Furthermore, it may have a third memory circuit and a third binarization circuit, and the third memory circuit may be electrically connected to a plurality of product-sum operation circuits via the third binarization circuit.

[0023] The second memory circuit, the third memory circuit, and the third binarization circuit can be provided in the second layer.

[0024] The metal oxide preferably contains In, Zn, and M (M is one or more of Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, or Hf).

Advantages of the Invention

[0025] By using one aspect of the present invention, an imaging device capable of performing image processing can be provided. Or, a highly functional and compact imaging device can be provided. Or, an imaging device capable of performing high-speed operation can be provided. Or, an imaging device with low power consumption can be provided. Or, a highly reliable imaging device can be provided. Or, a novel imaging device or the like can be provided. Or, a driving method for the above imaging device can be provided. Or, a novel semiconductor device or the like can be provided.

Brief Description of Drawings

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Best Mode for Carrying Out the Invention

[0027] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same reference numerals are commonly used among different drawings for the same part or parts having the same or similar functions, and the repeated description thereof may be omitted. In addition, the hatching of the same elements constituting the drawings may be appropriately omitted or changed among different drawings.

[0028] Also, even if an element is shown as a single element on the circuit diagram, the element may be composed of a plurality of elements as long as there is no functional inconvenience. For example, transistors operating as switches may be connected in series or in parallel in some cases. Also, a capacitor may be divided and arranged at a plurality of positions.

[0029] Also, a single conductor may have a plurality of functions such as wiring, electrodes, and terminals, and in this specification, a plurality of names may be used for the same element. Also, even if the elements are shown as being directly connected on the circuit diagram, in actuality, the elements may be connected via one or a plurality of conductors, and such a configuration is also included in the category of direct connection in this specification.

[0030] (Embodiment 1) In this embodiment, an imaging device, which is an aspect of the present invention, will be described with reference to the drawings.

[0031] One aspect of the present invention is an imaging device having additional functions such as image processing. The imaging device binarizes analog data (image data) acquired in an imaging operation in a pixel unit, and performs a sum-of-products operation using the binarized data. A storage circuit is provided in the pixel unit to hold weight coefficients (also called weight data or filters) used in the sum-of-products operation. Therefore, the operation can be performed without repeatedly reading the weight coefficients from the outside, and the power consumption can be reduced.

[0032] Also, in the imaging device according to one aspect of the present invention, by laminating a pixel circuit, a storage circuit, etc. and a sum-of-products operation circuit, etc., the wiring length between the circuits can be shortened, and low-power consumption operation and high-speed operation can be performed. Further, a highly functional and compact imaging device can be provided.

[0033] <Imaging device> FIG. 1 is a perspective view for explaining an imaging device according to one aspect of the present invention. The imaging device has a layer 10 and a layer 20. The layer 10 can be provided on the layer 20. The imaging device has a pixel unit 11 in which a pixel circuit, a storage circuit, etc. are provided. The pixel unit 11 has elements provided in the layer 10 and elements provided in the layer 20.

[0034] A pixel circuit and a storage circuit can be provided in the layer 10. In the layer 20, a drive circuit for the circuits included in the layer 10, an arithmetic circuit for the data acquired by the circuits included in the layer 10, a data conversion circuit, a storage circuit, etc. can be provided. For example, in the layer 20, an arithmetic unit 21, a load driver 31 and a column driver 32 for driving the pixel circuit, a load driver 33 and a column driver 34 for driving the storage circuit, etc. can be provided. Further, in the layer 20, circuits 35, 36, etc. having a data selection function, a holding function, a conversion function, a readout function, etc. may be provided as necessary.

[0035] The circuits included in the layer 10 and the circuits included in the layer 20 can be electrically connected by electrodes, wirings, etc. passing through the layer 10. Note that some of the circuits described above can also be provided in a layer opposite to the above description or outside the imaging device.

[0036] FIG. 2A is a diagram for explaining the details of the pixel section 11. The pixel section 11 has a plurality of pixel blocks 12 arranged in a matrix. Further, the pixel block 12 has pixel blocks 13 arranged in a 3×3 pattern. Further, the pixel block 13 has 3×3 pixels 14. That is, the pixel block 12 has 9×9 pixels 14. The pixel 14 has a pixel circuit 15 and a memory circuit 16.

[0037] In one aspect of the present invention, various operations and the like are performed on the premise that the pixel block 13 has 3×3 pixels 14, but the number of pixels is not limited to the above, and for example, it can be 2×2, 4×4, 5×5, 25×25, etc. Alternatively, the number of pixels 14 in the horizontal and vertical directions may be different. Also, some of the pixel blocks 13 can be shared by adjacent pixel blocks 12. Also, some of the pixels 14 can be shared by adjacent pixel blocks 13. Note that the number of pixel blocks 13 included in the pixel block 12 can also be appropriately changed.

[0038] The pixel 14 shown in FIG. 2A is an example in which the pixel circuit 15 and the memory circuit 16 are provided side by side in layer 10, but as shown in FIG. 2B, the pixel circuit 15 may be provided overlapping the memory circuit 16. Alternatively, as shown in FIG. 2C, the memory circuit 16 may be provided overlapping the pixel circuit 15.

[0039] FIG. 3 is a diagram for explaining the components of the pixel block 13. The pixel block 13 has 3×3 pixels 14. Therefore, the pixel block 13 has nine pixel circuits 15 and nine memory circuits 16 in layer 10. Also, in a region (layer 20) overlapping the pixel circuit 15 or the memory circuit 16, a plurality of binarization circuits 22, a plurality of multiplication and accumulation circuits 23, and a plurality of binarization circuits 24 are provided as an arithmetic unit 21.

[0040] The binarization circuit 22 is provided in the same number as the pixel circuit 15, that is, nine. The binarization circuit 22 is provided at a position having an area overlapping with the pixel circuit 15. FIG. 4 is a diagram showing the connection relationship between the pixel circuit 15 and the binarization circuit 22. One pixel circuit 15 is electrically connected to one binarization circuit 22 having an overlapping area.

[0041] The binarization circuit 22 is a circuit that determines and binarizes the image data (analog data) acquired by the pixel circuit 15 with a preset threshold value. For example, a comparator can be used.

[0042] A plurality of product-sum operation circuits 23 are provided in one pixel block 13. In this embodiment, an example of providing six product-sum operation circuits 23 is shown. Note that the number of product-sum operation circuits 23 can be appropriately increased or decreased according to the purpose. The input terminals of the product-sum operation circuit 23 are electrically connected to the storage circuit 16 and the binarization circuit 22.

[0043] FIG. 5 is a diagram showing the connection relationship between the product-sum operation circuit 23, the storage circuit 16, and the binarization circuit 22. In order to clearly show the connection relationship, nine binarization circuits 22 are extracted and shown in the figure.

[0044] The pixel block 13 has nine storage circuits 16, each of which has a plurality of memory cells. A 1-bit weight coefficient can be written in advance in each of the plurality of memory cells. Each of the nine storage circuits 16 is electrically connected to each of the six product-sum operation circuits 23. Therefore, a weight coefficient of 9 bits can be supplied to each of the product-sum operation circuits 23. Since a weight coefficient can be supplied from one storage circuit 16 to six product-sum operation circuits 23, here, if at least 1 bit of weight coefficient is written in one storage circuit 16, the operation can be performed.

[0045] Each of the binarization circuits 22 can output image data converted to 1 bit. Each of the nine binarization circuits 22 is electrically connected to each of the six multiplication-and-addition circuits 23. Since image data can be supplied from one binarization circuit 22 to the six multiplication-and-addition circuits 23, 9-bit image data is supplied to each of the multiplication-and-addition circuits 23.

[0046] FIG. 6A is a diagram for briefly explaining the configuration and operation of the multiplication-and-addition circuit 23. The multiplication-and-addition circuit 23 can be configured to have, for example, nine multipliers 23a and one adder 23b. Image data (X1 to X9) converted to 1 bit by the binarization circuit 22 and 1-bit weight coefficients (W1 to W9) read from the storage circuit 16 are input to each multiplier 23a, and a multiplication operation is performed to output 1-bit data to the adder 23b. The adder 23b adds the data input from each multiplier 23a and outputs it to the binarization circuit 24. Here, since the data output from the adder 23b (multiplication-and-addition circuit 23) takes values from 0 to 9, it becomes 4-bit data.

[0047] Six binarization circuits 24, the same number as the multiplication-and-addition circuits 23, are provided. As shown in FIGS. 6A, 6B, and 7, one binarization circuit 24 is electrically connected to one multiplication-and-addition circuit 23. As shown in FIGS. 6A and 6B, the data input to the binarization circuit 24 is 4-bit digital data corresponding to 0 to 9. The binarization circuit 24 outputs 1 when it determines that the input data is 5 or more, and outputs 0 when it determines that the input data is 4 or less. That is, the binarization circuit 24 is a circuit having a function of converting 4-bit data to 1 bit.

[0048] As shown in FIG. 7, 6-bit arithmetic data can be output from one pixel block 13. FIG. 8 is a diagram for explaining the reading of arithmetic data from the pixel block 12 (pixel blocks 13[1,1] to 13[3,3]).

[0049] The six binarization circuits 24 included in the pixel block 13 each have a selection transistor 24S that controls the output. The gates of the six selection transistors 24S are electrically connected to a wiring RSEL (wiring RSEL[0], wiring RSEL[1], wiring RSEL[2]). The wiring RSEL is shared by the pixel blocks 13 provided in the row direction. Also, the six output lines OUT (OUT[0] to OUT[5]) to which the six binarization circuits 24 are electrically connected are shared by the pixel blocks 13 provided in the column direction.

[0050] A readout circuit 40 is electrically connected to the six output lines OUT. The readout circuit 40 has switches 40S, 41S, and 42S that are electrically connected to the six output lines OUT of each column, respectively.

[0051] The switches 40S to 42S each have a plurality of transistors. The gate of the transistor included in the switch 40S is electrically connected to the wiring CSEL[0]. The gate of the transistor included in the switch 42S is electrically connected to the wiring CSEL[1]. The gate of the transistor included in the switch 42S is electrically connected to the wiring CSEL[2].

[0052] The output-side wirings of the switches 40S to 42S are electrically connected to one output line OUT for every three. With such a configuration, it is possible to output data for each pixel block 13.

[0053] Note that the readout circuit 40 can be provided in the layer 20 as an element of the circuit 35 or the circuit 36 shown in FIG. 1.

[0054] FIG. 9 is a timing chart for explaining the reading of arithmetic data from pixel block 12 (pixel blocks 13[1,1] to 13[3,3]). It is assumed that all the operations are completed in each pixel block 13 before time T1, and the arithmetic data is held in the binarization circuit 24. In the following description, the potential (high potential) that makes the transistor conductive is represented as "H", and the potential (low potential) that makes the transistor non-conductive is represented as "L".

[0055] At time T1, when the potential of wiring RSEL[0] is set to "H", all the selection transistors 24S of the binarization circuits 24 in the pixel block 13 arranged in the 0th row become conductive, and the arithmetic data is output to the readout circuit 40.

[0056] Also, at time T1, when the potential of wiring CSEL[0] is set to "H", the switch 40S whose gate is electrically connected to wiring CSEL[0] becomes conductive, and the arithmetic data of pixel block 13[1,1] is output to output lines OUT[0] to OUT[5].

[0057] At time T2, when the potential of wiring CSEL[0] is set to "L" and the potential of wiring CSEL[1] is set to "H", the switch 40S becomes non-conductive, and the switch 41S whose gate is electrically connected to wiring CSEL[1] becomes conductive, and the arithmetic data of pixel block 13[1,2] is output to output lines OUT[0] to OUT[5].

[0058] At time T3, when the potential of wiring CSEL[1] is set to "L" and the potential of wiring CSEL[2] is set to "H", the switch 41S becomes non-conductive, and the switch 42S whose gate is electrically connected to wiring CSEL[2] becomes conductive, and the arithmetic data of pixel block 13[1,3] is output to output lines OUT[0] to OUT[5].

[0059] At time T4, the potential of wiring RSEL[0] is set to "L" and the potential of wiring CSEL[2] is set to "L", and the output of the arithmetic data of the pixel block 13 in the 0th row (pixel blocks 13[1,1] to 13[1,3]) is terminated.

[0060] At times T4 to T7, the potential of wiring RSEL[1] is set to “H”, and by performing the same operation as above, the arithmetic data of the pixel blocks 13 in the first row (pixel blocks 13[2,1] to pixel blocks 13[2,3]) is output.

[0061] Also, at times T7 to T10, the potential of wiring RSEL[2] is set to “H”, and by performing the same operation as above, the arithmetic data of the pixel blocks 13 in the second row (pixel blocks 13[3,1] to pixel blocks 13[3,3]) is output.

[0062] Here, if the arithmetic operation is completed in one clock and the read operation of one pixel block 13 is performed in one clock, one pixel block 12 can be read in a total of 10 clocks. By providing read circuits 40 equal in number to the columns of pixel blocks 12, the pixel blocks 12 for one row can be read in parallel.

[0063] <Pixel circuit> As shown in FIG. 10A, the pixel circuit 15 can include a photoelectric conversion device 101, a transistor 102, a transistor 103, a transistor 104, a transistor 105, and a capacitor 106.

[0064] One electrode of the photoelectric conversion device 101 is electrically connected to one of the source or drain of the transistor 102. The other of the source or drain of the transistor 102 is electrically connected to one of the source or drain of the transistor 103, one electrode of the capacitor 106, and the gate of the transistor 104. One of the source or drain of the transistor 104 is electrically connected to one of the source or drain of the transistor 105.

[0065] The other electrode of the photoelectric conversion device 101 is electrically connected to the wiring 111. The gate of the transistor 102 is electrically connected to the wiring 114. The other of the source or drain of the transistor 103 is electrically connected to the wiring 112. The gate of the transistor 103 is electrically connected to the wiring 115. The other of the source or drain of the transistor 104 is electrically connected to the wiring 113. The other of the source or drain of the transistor 105 is electrically connected to the wiring 117. The gate of the transistor 105 is electrically connected to the wiring 116.

[0066] Here, an electrical connection point (wiring) between the other of the source or drain of the transistor 102, one of the source or drain of the transistor 103, one electrode of the capacitor 106, and the gate of the transistor 104 is defined as the node N.

[0067] The wirings 111, 112, and 113 can function as power supply lines. For example, the wiring 111 can function as a low-potential power supply line, and the wirings 112 and 113 can function as high-potential power supply lines. Note that the wirings 112 and 113 may be electrically connected. The wirings 114, 115, and 116 can function as signal lines for controlling the conduction of each transistor. The wiring 117 can function as a wiring for electrically connecting the pixel circuit 15 and the binarization circuit 22.

[0068] As the photoelectric conversion device 101, a photodiode can be used. When it is desired to enhance the light detection sensitivity in low illumination, it is preferable to use an avalanche photodiode.

[0069] The transistor 102 can have a function of controlling the potential of the node N. The transistor 103 can have a function of initializing the potential of the node N. The transistor 104 can have a function of passing a current according to the potential of the node N. The transistor 105 can have a function of selecting a pixel.

[0070] Note that the connection direction of the pair of electrodes included in the photoelectric conversion device 101 may be reversed. In this case, the wiring 111 may function as a high-potential power line, and the wirings 112 and 113 may function as low-potential power lines.

[0071] For the transistors 102 and 103, it is preferable to use transistors (OS transistors) in which a metal oxide is used for the channel formation region. The OS transistor has the characteristic of an extremely low off-current. By using the OS transistor for the transistors 102 and 103, the period during which charges can be held at the node N can be made extremely long. In addition, a global shutter method in which the charge accumulation operation is performed simultaneously for all pixels can be applied without complicating the circuit configuration and the operation method.

[0072] On the other hand, in some cases, it may be desired that the transistor 104 has excellent amplification characteristics. Also, in some cases, it may be preferable to use a transistor having a high mobility enabling high-speed operation for the transistor 105. Therefore, a transistor (Si transistor) in which silicon is used for the channel formation region may be applied to the transistors 104 and 105.

[0073] Note that the present invention is not limited to the above, and the OS transistor and the Si transistor may be arbitrarily combined and applied. Also, all the transistors may be OS transistors. Alternatively, all the transistors may be Si transistors. Examples of the Si transistor include a transistor having amorphous silicon, and a transistor having crystalline silicon (microcrystalline silicon, low-temperature polysilicon, single-crystalline silicon).

[0074] Further, as shown in FIG. 10B, a configuration in which a back gate (second gate) is provided for the transistor may be adopted. By electrically connecting the back gate to the front gate, the on-current of the transistor can be increased. Further, by supplying an appropriate constant potential to the back gate, the threshold voltage of the transistor can be controlled. Note that the configuration in which a back gate is provided for the transistor can also be applied to other circuits in this specification. Further, a circuit may be configured by mixing transistors with and without a back gate.

[0075] Further, as shown in FIG. 10C, a configuration in which transistors 107 and 108 are added to the configuration of FIG. 10A may be adopted. The gate of transistor 107 is electrically connected to the gate of transistor 104. One of the source or drain of transistor 107 is electrically connected to one of the source or drain of transistor 108. The other of the source or drain of transistor 107 is electrically connected to wiring 113. The gate of transistor 108 is electrically connected to wiring 118. The other of the source or drain of transistor 108 is electrically connected to wiring 119.

[0076] Here, wiring 118 can function as a signal line for controlling the conduction of transistor 108. Further, wiring 119 can be electrically connected to circuit 60. Circuit 60 is an image reading circuit and can use, for example, a CDS circuit (correlated double sampling circuit). By using this configuration, image data can be output to wiring 117 and wiring 119. The image data output to wiring 117 is input to binarization circuit 22, and then a product-sum operation is performed. The image data output to wiring 119 is read out to the outside via circuit 60. These operations can be performed in parallel. Further, only the operation (image processing) or only the reading of the image data can be performed.

[0077] Note that circuit 60 can be provided in layer 20 as an element of circuit 35 or circuit 36 shown in FIG. 1.

[0078] <Memory circuit> As shown in FIG. 2, the memory circuit 16 is provided in the pixel 14. The memory circuit 16 has a plurality of memory cells, and 1-bit data corresponding to the weight coefficient is stored in the memory cells.

[0079] FIG. 11A is a diagram showing the connection relationship of the memory cell 150, the load driver 33, and the column driver 34. It is preferable to use an OS transistor for the transistors constituting the memory cell 150. The plurality of memory cells 150 are provided in the layer 10 as the memory circuit 16. The load driver 33 and the column driver 34 are driving circuits for the memory cell 150 and can be provided in the layer 20.

[0080] The memory circuit 16 has a total of m×n memory cells 150, where m (m is an integer of 1 or more) are arranged in a column and n (n is an integer of 1 or more) are arranged in a row, and the memory cells 150 are arranged in a matrix.

[0081] FIGS. 11B and 11C are diagrams for explaining the memory cell 150a and the memory cell 150b applicable to the memory cell 150. In the following description, the bit lines can be connected to the column driver 34. Also, the word lines can be connected to the load driver 33. The bit lines are also electrically connected to the product-sum operation circuit 23, but are not shown here.

[0082] For the load driver 33 and the column driver 34, for example, a decoder or a shift register can be used. Note that a plurality of load drivers 33 and column drivers 34 may be provided.

[0083] FIG. 11B shows a circuit configuration example of the gain cell type (also referred to as "2Tr1C type") memory cell 150a having two transistors and one capacitor. The memory cell 150a has a transistor 273, a transistor 272, and a capacitor 274.

[0084] One of the source or drain of transistor 273 is connected to one electrode of capacitor 274, the other of the source or drain of transistor 273 is connected to wiring WBL, the gate of transistor 273 is connected to wiring WL, and the back gate of transistor 273 is connected to wiring BGL. The other electrode of capacitor 274 is connected to wiring RL. One of the source or drain of transistor 272 is connected to wiring RBL, the other of the source or drain of transistor 272 is connected to wiring SL, and the gate of transistor 272 is connected to one electrode of capacitor 274.

[0085] Wiring WBL functions as a write bit line. Wiring RBL functions as a read bit line. Wiring WL functions as a word line. Wiring RL functions as a wiring for applying a predetermined potential to the other electrode of capacitor 274. When writing data, during data retention, it is preferable to apply a reference potential to wiring RL.

[0086] Wiring BGL functions as a wiring for applying a potential to the back gate of transistor 273. By applying an arbitrary potential to wiring BGL, the threshold voltage of transistor 273 can be increased or decreased.

[0087] Data writing is performed by applying a high-level potential to wiring WL, turning transistor 273 on, and electrically connecting wiring WBL and one electrode of capacitor 274. Specifically, when transistor 273 is on, a potential corresponding to the information to be recorded is applied to wiring WBL, and this potential is written to one electrode of capacitor 274 and the gate of transistor 272. Then, by applying a low-level potential to wiring WL and turning transistor 273 off, the potential of one electrode of capacitor 274 and the potential of the gate of transistor 272 are held.

[0088] Data reading is performed by applying a predetermined potential to wiring RL and wiring SL. Since the current flowing between the source and drain of transistor 272 and the potential of one of the source or drain of transistor 273 are determined by the potential of the gate of transistor 272 and the potential of the other of the source or drain of transistor 273, by reading the potential of wiring RBL connected to one of the source or drain of transistor 272, the potential held at one electrode of capacitor 274 (or the gate of transistor 272) can be read. That is, the information written in this memory cell can be read from the potential held at one electrode of capacitor 274 (or the gate of transistor 272). Or, it is possible to know whether the information written in this memory cell is present or not.

[0089] Also, as shown in FIG. 11C, a configuration in which wiring WBL and wiring RBL are combined into a single wiring BIL may be used. Memory cell 150b shown in FIG. 11C has a configuration in which wiring WBL and wiring RBL of memory cell 150a are combined into a single wiring BIL, and the other of the source or drain of transistor 273 and one of the source or drain of transistor 272 are connected to wiring BIL. That is, memory cell 150b has a configuration in which it operates with a single wiring BIL as both the write bit line and the read bit line.

[0090] In memory cells 150a and 150b as well, it is preferable to use an OS transistor for transistor 273. When an OS transistor is used for transistor 273, a storage device using a 2Tr1C type memory cell such as memory cells 150a and 150b is called a NOSRAM (Non-volatile Oxide Semiconductor Random Access Memory). Note that the configuration of the circuit of the memory cell can be changed as appropriate.

[0091] <Layout> FIG. 12A and FIG. 12B are examples of layouts (top views) that can be used for the pixel circuit according to an aspect of the present invention. FIGS. 12A and 12B are the layouts of the pixel circuit shown in FIG. 10B. In FIG. 12A, the back gate wiring 170, the metal oxide layer 175, and the source-drain wiring 180 are shown. Here, the metal oxide layer 175 is the layer where the channel formation region of the OS transistor is provided.

[0092] In order to improve the resolution of the imaging device, miniaturization of the pixel circuit is required. In the miniaturization process, since adjacent structures affect each other, arranging the structures randomly promotes variations such as wiring width. Therefore, as shown in FIG. 12A, it is preferable to arrange the structures at equal intervals in the horizontal direction (X direction) and the vertical direction (Y direction).

[0093] FIG. 12B shows a configuration in which the gate wiring 185 and the wiring 190 electrically connected to the gate wiring 185 are added to FIG. 12A. By overlapping each element in this way, the transistors 102, 103, 104, and 105 shown in FIG. 10B are formed. In addition, a plurality of transistors 109 are formed. The transistor 109 is a dummy transistor that is not involved in the circuit operation, but with such a configuration, the uniformity of the wiring width and the like can be improved, and variations in transistor characteristics and the like can be suppressed.

[0094] According to an aspect of the present invention described in this embodiment, an imaging device having an image processing function and capable of high-speed operation can be provided.

[0095] This embodiment can be appropriately combined with the descriptions of other embodiments.

[0096] (Embodiment 2) In this embodiment, an imaging device having a configuration different from that of the first embodiment will be described with reference to the drawings. The imaging device described in the first embodiment was configured to perform a single multiplication-accumulation operation on image data and extract the operation data. In contrast, the imaging device described in this embodiment has a configuration that performs a plurality of multiplication-accumulation operations on image data and extracts the operation data.

[0097] Since the basic configurations of pixel 14 and pixel blocks (pixel block 12, pixel block 13) are common to those in the first embodiment, detailed descriptions thereof are omitted.

[0098] The imaging device has two registers as elements for performing a plurality of multiplication-accumulation operations and extracting the operation data. FIG. 13 is a diagram for explaining the connection relationship between pixel block 12 and register 51, which is one of the two registers (register 51, register 52). A selection circuit may be provided between pixel block 13 and register 51 to reduce the number of wirings.

[0099] Pixel block 12 shown in FIG. 13 is a simplified diagram of pixel block 12 shown in FIG. 8, indicating that the operation data output from each pixel block 13 after the first multiplication-accumulation operation is 6 bits (1 bit × 6). The 6-bit operation data output from each pixel block 13 is input to and stored in register 51. Here, since the 6-bit operation data output from 9 pixel blocks 13 is input to register 51, a total of 54 bits (6 bits × 9) of operation data will be stored.

[0100] Next, as shown in FIG. 14, the 54-bit operation data stored in register 51 is redistributed to each pixel block 13. Six multiplication-accumulation circuits 23 capable of processing 9-bit data as shown in FIG. 6A are provided in each pixel block 13, and 9-bit operation data is distributed to each multiplication-accumulation circuit 23. In addition, 9-bit weight coefficients are supplied from the 9 storage circuits 16 included in pixel block 13 to each multiplication-accumulation circuit 23. Therefore, each multiplication-accumulation circuit 23 can perform a second multiplication-accumulation operation.

[0101] Next, as shown in FIG. 15A, the 4-bit arithmetic data output by each of the sum-of-products arithmetic circuits 23 is input to circuits 25 provided in the same number as the pixel block 13. Here, since there are six sum-of-products arithmetic circuits 23, the arithmetic data input to the circuits 25 is 24 bits (4 bits × 6).

[0102] FIG. 15B is a diagram for explaining the circuit 25. The circuit 25 includes an addition circuit 26a and a binarization circuit 26b. Since 4-bit (corresponding to 0 to 9) arithmetic data is input from each of the six sum-of-products arithmetic circuits 23 to the addition circuit 26a, the output of the addition circuit 26a is 6-bit (corresponding to 0 to 54) arithmetic data. The 6-bit data is input to the binarization circuit 26b. The binarization circuit 26b can convert the input data into 1 bit, and outputs 1 when the data is 28 or more, and outputs 0 when the data is 27 or less. In FIG. 15, the circuit 25 is shown inside the pixel block 12, but it may be provided outside the pixel block 12.

[0103] The 1-bit arithmetic data (a total of 9 bits of data) output by each circuit 25 is input to and stored in the register 52. Here, 9 bits of arithmetic data can be read out as necessary. A selection circuit may be provided between the circuit 25 and the register 52 to reduce the number of wirings.

[0104] In the present embodiment, an operation of repeating the sum-of-products operation by changing the weight coefficient will be further described. After the above operation, 54 bits of arithmetic data redistributed from the register 51 are held in the sum-of-products arithmetic circuit 23 included in the pixel block 13. By changing the weight coefficient supplied from the storage circuit 16, the sum-of-products operation is performed again, and different arithmetic data can be obtained. Then, the arithmetic data is stored in the register 52 in the same manner as the arithmetic data obtained in the previous sum-of-products operation. Therefore, a total of 18 bits of arithmetic data are stored in the register 52.

[0105] FIG. 16A is a diagram for explaining a read circuit 41 connected to the output side of the register 52. A plurality of six output lines are provided on the output side of the register 52 so that arithmetic data can be read every 6 bits. The read circuit 41 is electrically connected to the six output lines. The read circuit 41 includes switches 43S, 44S, and 45S that are electrically connected to the six output lines, respectively.

[0106] The switches 43S to 45S each have a plurality of transistors. The gate of the transistor included in the switch 43S is electrically connected to the wiring CSEL[0]. The gate of the transistor included in the switch 44S is electrically connected to the wiring CSEL[1]. The gate of the transistor included in the switch 45S is electrically connected to the wiring CSEL[2].

[0107] The output-side wirings of the switches 43S to 45S are electrically connected to one output line OUT (OUT[0] to OUT[5]) every three. With this configuration, arithmetic data can be output every 6 bits.

[0108] Note that the register 51, the register 52, and the read circuit 41 can be provided in the layer 20 as elements of the circuit 35 or the circuit 36 shown in FIG. 1.

[0109] FIG. 16B is a timing chart for explaining the reading of the arithmetic data stored in the register 52. It is assumed that all the arithmetic data (for 18 bits) is held in the register 52 before time T1. In the following description, the potential (high potential) that makes the transistor conductive is expressed as “H”, and the potential (low potential) that makes the transistor non-conductive is expressed as “L”.

[0110] When the potential of the wiring CSEL[0] is set to “H” at time T1, the switch 43S whose gate is electrically connected to the wiring CSEL[0] conducts, and the first 6-bit arithmetic data is output to the output lines OUT[0] to OUT[5].

[0111] When the potential of wiring CSEL[0] is set to "L" and the potential of wiring CSEL[1] is set to "H" at time T2, switch 43S becomes non-conductive, and switch 44S with its gate electrically connected to wiring CSEL[1] becomes conductive, and the operation data for the second 6 bits, which is different from the first-time data, is output to output lines OUT[0] to OUT[5].

[0112] When the potential of wiring CSEL[1] is set to "L" and the potential of wiring CSEL[2] is set to "H" at time T3, switch 44S becomes non-conductive, and switch 45S with its gate electrically connected to wiring CSEL[2] becomes conductive, and the operation data for the third 6 bits, which is different from the first-time and second-time data, is output to output lines OUT[0] to OUT[5].

[0113] Here, it is assumed that storing the operation data for 54 bits in register 51 is performed in the first clock, storing the operation data for the first 9 bits in register 52 is performed in the second clock, and storing the operation data for the second 9 bits in register 52 is performed in the third clock. Then, if reading the operation data for the first 6 bits from register 52 is performed in the fourth clock, reading the operation data for the second 6 bits is performed in the fifth clock, and reading the operation data for the third 6 bits is performed in the sixth clock, all operations can be completed in 6 clocks.

[0114] The operations in the first to third clocks and the operations in the fourth to sixth clocks can be performed in parallel. If the period from time T1 to time T2 in the timing chart shown in Fig. 16B corresponds to the fourth clock, the period from time T2 to time T3 corresponds to the fifth clock, and the period from time T3 to time T4 corresponds to the sixth clock, then at times T4 to T7, the next 18-bit operation data can be read. Also, at times T7 to T10, the next 18-bit operation data can be read.

[0115] Note that the operation of reading out the arithmetic data from the pixel block 12 in the first embodiment and the present embodiment corresponds to the operation with a stride of 3 and omits the pooling process. However, the pooling process may be performed to further compress the arithmetic data.

[0116] According to one aspect of the present invention described in the present embodiment, an imaging device having an image processing function and capable of high-speed operation can be provided.

[0117] The present embodiment can be appropriately combined with the descriptions of other embodiments.

[0118] (Embodiment 3) In the present embodiment, a structural example of an imaging device according to one aspect of the present invention will be described.

[0119] <Structural example> FIG. 17A is a diagram showing an example of the structure of pixels of the imaging device, and can have a stacked structure of layer 561 and layer 563.

[0120] Layer 561 has a photoelectric conversion device 101. The photoelectric conversion device 101 can have layer 565a and layer 565b as shown in FIG. 18A. In some cases, the layer may be rephrased as a region.

[0121] The photoelectric conversion device 101 shown in FIG. 18A is a pn junction type photodiode. For example, a p-type semiconductor can be used for layer 565a and an n-type semiconductor can be used for layer 565b. Alternatively, an n-type semiconductor can be used for layer 565a and a p-type semiconductor can be used for layer 565b.

[0122] The above pn junction type photodiode can typically be formed using single crystal silicon. A photodiode having a single crystal silicon as a photoelectric conversion layer has relatively wide spectral sensitivity characteristics from ultraviolet light to near infrared light, and can detect light of various wavelengths by combining with an optical conversion layer described later.

[0123] In addition, a compound semiconductor may be used as the photoelectric conversion layer of the pn junction photodiode. Examples of the compound semiconductor include gallium-arsenic-phosphorus compound (GaAsP), gallium-phosphorus compound (GaP), indium-gallium-arsenic compound (InGaAs), lead-sulfur compound (PbS), lead-selenium compound (PbSe), indium-arsenic compound (InAs), indium-antimony compound (InSb), mercury-cadmium-tellurium compound (HgCdTe), and the like.

[0124] The compound semiconductor is preferably a compound semiconductor having group 13 elements (such as aluminum, gallium, indium, etc.) and group 15 elements (such as nitrogen, phosphorus, arsenic, antimony, etc.) (also referred to as 3-5 group compound semiconductors), or a compound semiconductor having group 12 elements (such as magnesium, zinc, cadmium, mercury, etc.) and group 16 elements (such as oxygen, sulfur, selenium, tellurium, etc.) (also referred to as 2-6 group compound semiconductors).

[0125] Since the bandgap of the compound semiconductor can be changed according to the combination of constituent elements and their atomic ratio, a photodiode having sensitivity in various wavelength ranges from ultraviolet light to infrared light can be formed.

[0126] Note that the wavelength of ultraviolet light can generally be defined as being in the vicinity of 0.01 μm to 0.38 μm, the wavelength of visible light as being in the vicinity of 0.38 μm to 0.75 μm, the wavelength of near-infrared light as being in the vicinity of 0.75 μm to 2.5 μm, the wavelength of mid-infrared light as being in the vicinity of 2.5 μm to 4 μm, and the wavelength of far-infrared light as being in the vicinity of 4 μm to 1000 μm.

[0127] For example, to form a photodiode having photosensitivity from ultraviolet light to visible light, GaP or the like can be used for the photoelectric conversion layer. Also, to form a photodiode having photosensitivity from ultraviolet light to near-infrared light, silicon or GaAsP or the like can be used for the photoelectric conversion layer. Further, to form a photodiode having photosensitivity from visible light to mid-infrared light, InGaAs or the like can be used for the photoelectric conversion layer. Also, to form a photodiode having photosensitivity from near-infrared light to mid-infrared light, PbS or InAs or the like can be used for the photoelectric conversion layer. Further, to form a photodiode having photosensitivity from mid-infrared light to far-infrared light, PbSe, InSb, HgCdTe or the like can be used for the photoelectric conversion layer.

[0128] Note that the photodiode using the above compound semiconductor may be a pin junction as well as a pn junction. Also, the pn junction and the pin junction are not limited to a homojunction structure and may be a heterojunction structure.

[0129] For example, in a heterojunction, a first compound semiconductor can be used for one layer of the pn junction structure, and a second compound semiconductor different from the first compound semiconductor can be used for the other layer. Also, a first compound semiconductor can be used for any one layer or two layers of the pin junction structure, and a second compound semiconductor different from the first compound semiconductor can be used for the other layers. Note that one of the first compound semiconductor or the second compound semiconductor may be a single semiconductor such as silicon.

[0130] Note that the photoelectric conversion layer of the photodiode may be formed using different materials for each pixel. By using this configuration, an imaging device having any two types of pixels, such as pixels for detecting ultraviolet light, pixels for detecting visible light, and pixels for detecting infrared light, or three types of pixels can be formed.

[0131] In addition, as shown in FIG. 18B, the photoelectric conversion device 101 included in layer 561 may be a laminate of layer 566a, layer 566b, layer 566c, and layer 566d. The photoelectric conversion device 101 shown in FIG. 18B is an example of an avalanche photodiode. Layer 566a and layer 566d correspond to electrodes, and layer 566b and 566c correspond to a photoelectric conversion section.

[0132] Layer 566a is preferably a low-resistance metal layer or the like. For example, aluminum, titanium, tungsten, tantalum, silver, or a laminate thereof can be used.

[0133] For layer 566d, it is preferable to use a conductive layer having high transmittance for visible light. For example, indium oxide, tin oxide, zinc oxide, indium-tin oxide, gallium-zinc oxide, indium-gallium-zinc oxide, or graphene can be used. Note that a configuration in which layer 566d is omitted is also possible.

[0134] Layers 566b and 566c of the photoelectric conversion section can be configured as a pn junction type photodiode having, for example, a selenium-based material as a photoelectric conversion layer. As layer 566b, it is preferable to use a selenium-based material that is a p-type semiconductor, and as layer 566c, it is preferable to use gallium oxide or the like that is an n-type semiconductor.

[0135] A photoelectric conversion device using a selenium-based material has a characteristic of high external quantum efficiency for visible light. In this photoelectric conversion device, by utilizing avalanche multiplication, the amplification of electrons with respect to the amount of incident light can be increased. In addition, since the selenium-based material has a high light absorption coefficient, it has production advantages such as being able to fabricate the photoelectric conversion layer as a thin film. The thin film of the selenium-based material can be formed using a vacuum evaporation method, a sputtering method, or the like.

[0136] As selenium-based materials, crystalline selenium (single-crystalline selenium, polycrystalline selenium), and amorphous selenium can be used. These have photosensitivity from ultraviolet light to visible light. Also, compounds of copper, indium, and selenium (CIS), or compounds of copper, indium, gallium, and selenium (CIGS), etc. can be used. These have photosensitivity from ultraviolet light to near-infrared light.

[0137] The n-type semiconductor is preferably formed of a material having a wide bandgap and being transparent to visible light. For example, zinc oxide, gallium oxide, indium oxide, tin oxide, or oxides in which they are mixed, etc. can be used. Also, these materials also have a function as a hole injection blocking layer and can also reduce dark current.

[0138] Also, as shown in FIG. 18C, the photoelectric conversion device 101 included in layer 561 may be a laminate of layer 567a, layer 567b, layer 567c, layer 567d, and layer 567e. The photoelectric conversion device 101 shown in FIG. 18C is an example of an organic photoconductive film. Layer 567a is a lower electrode, layer 567e is a transparent upper electrode, and layers 567b, 567c, and 567d correspond to the photoelectric conversion part.

[0139] Either one of layers 567b and 567d of the photoelectric conversion part can be a hole transport layer, and the other can be an electron transport layer. Also, layer 567c can be a photoelectric conversion layer.

[0140] As the hole transport layer, for example, molybdenum oxide, etc. can be used. As the electron transport layer, for example, C 60 , C 70 such as fullerenes, or their derivatives, etc. can be used.

[0141] As the photoelectric conversion layer, a mixed layer (bulk heterojunction structure) of an n-type organic semiconductor and a p-type organic semiconductor can be used. There are various types of organic semiconductors, and a material having photosensitivity to the target wavelength can be selected for the photoelectric conversion layer.

[0142] As the layer 563 shown in FIG. 17A, for example, a silicon substrate can be used. The silicon substrate has Si transistors and the like. Using the Si transistors, in addition to the pixel circuit, circuits for driving the pixel circuit, image signal reading circuits, image processing circuits, neural networks, communication circuits, etc. can be formed. Also, a memory circuit such as a DRAM (Dynamic Random Access Memory), a CPU (Central Processing Unit), an MCU (Micro Controller Unit), etc. may be formed. In the present embodiment, the circuits other than the pixel circuit are called functional circuits.

[0143] For example, in the transistors included in the functional circuits (arithmetic unit 21, load driver 31, column driver 32, load driver 33, column driver 34, circuit 35, circuit 36, etc.) provided in the layer 20 described in Embodiment 1, part or all of them can be provided in the layer 563.

[0144] Also, as shown in FIG. 17B, the layer 563 may be a stack of multiple layers. In FIG. 17B, three layers of layer 563a, 563b, and 563c are illustrated, but it may be two layers. Or the layer 563 may be a stack of four or more layers. These layers can be stacked using, for example, a bonding process or the like. With such a configuration, the pixel circuit and the functional circuit can be dispersed in multiple layers and the pixel circuit and the functional circuit can be provided in an overlapping manner, so that a small and highly functional imaging device can be manufactured.

[0145] Also, the pixel may have a stacked structure of layer 561, layer 562, and layer 563 as shown in FIG. 17C.

[0146] Layer 562 corresponds to layer 10 described in Embodiment 1 and can have OS transistors. One or more of the above-described functional circuits may be formed by OS transistors. Alternatively, one or more of the functional circuits may be formed using the Si transistors of layer 563 and the OS transistors of layer 562. Alternatively, layer 563 may be used as a support substrate such as a glass substrate, and pixel circuits and functional circuits may be formed by the OS transistors of layer 562.

[0147] For example, a normally-off CPU (also referred to as "NoffCPU (registered trademark)") can be realized using OS transistors and Si transistors. Note that a NoffCPU is an integrated circuit including a normally-off type transistor that is in a non-conductive state (also referred to as an off state) even when the gate voltage is 0V.

[0148] The NoffCPU can stop power supply to circuits that are not required to operate within the NoffCPU and put the circuits in a standby state. No power is consumed in the circuits where power supply is stopped and which are in the standby state. Thus, the NoffCPU can minimize power consumption. In addition, the NoffCPU can retain information necessary for operations such as set conditions for a long period even when power supply is stopped. To resume from the standby state, it is only necessary to resume power supply to the circuits, and rewriting such as set conditions is not required. That is, a high-speed resume from the standby state is possible. In this way, the NoffCPU can reduce power consumption without significantly reducing the operation speed.

[0149] In addition, layer 562 may be a stack of a plurality of layers as shown in FIG. 17D. In FIG. 17D, two layers, layer 562a and layer 562b, are illustrated, but a stack of three or more layers may be used. These layers can be formed, for example, so as to be stacked on layer 563. Alternatively, a layer formed on layer 563 and a layer formed on layer 561 may be bonded together to form the layer.

[0150] As a semiconductor material used for an OS transistor, a metal oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more can be used. Typically, an oxide semiconductor containing indium, etc. can be used, for example, CAAC-OS or CAC-OS described later can be used. In CAAC-OS, the atoms constituting the crystal are stable, and it is suitable for transistors that emphasize reliability. Further, since CAC-OS exhibits high mobility characteristics, it is suitable for transistors that perform high-speed driving.

[0151] Since the energy gap of the semiconductor layer of the OS transistor is large, it exhibits an extremely low off-current characteristic of several yA / μm (current value per 1 μm channel width). Further, the OS transistor has characteristics different from those of Si transistors, such as no occurrence of impact ionization, avalanche breakdown, and short-channel effect, and a high withstand voltage and highly reliable circuit can be formed. Also, variations in electrical characteristics due to non-uniformity of crystallinity, which is a problem in Si transistors, are less likely to occur in OS transistors.

[0152] The semiconductor layer of the OS transistor can be, for example, a film represented by an In-M-Zn-based oxide containing one or more (selected from metals such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium) of indium, zinc, and M. The In-M-Zn-based oxide can typically be formed by a sputtering method. Alternatively, it may be formed using an ALD (Atomic layer deposition) method.

[0153] For forming an In-M-Zn-based oxide by sputtering, the atomic ratio of the metal elements in the sputtering target used is preferably such that In ≥ M and Zn ≥ M. Such atomic ratios of the metal elements in the sputtering target include, for example, In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, etc. are preferable. Note that the atomic ratio of the semiconductor layer formed includes fluctuations of plus or minus 40% of the atomic ratio of the metal elements contained in the above sputtering target.

[0154] As the semiconductor layer, an oxide semiconductor with a low carrier density is used. For example, the carrier density of the semiconductor layer is 1×10 17 / cm 3 or less, preferably 1×10 15 / cm 3 or less, more preferably 1×10 13 / cm 3 or less, still more preferably 1×10 11 / cm 3 or less, and even more preferably 1×10 10 / cm 3 less, and an oxide semiconductor with a carrier density of 1×10 -9 / cm 3 or more can be used. Such an oxide semiconductor is called a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. It can be said that the oxide semiconductor has a low density of defect levels and stable characteristics.

[0155] Note that it is not limited to these, and those with an appropriate composition may be used according to the required semiconductor characteristics and electrical characteristics (such as field-effect mobility, threshold voltage, etc.) of the transistor. Also, in order to obtain the required semiconductor characteristics of the transistor, it is preferable to make the carrier density, impurity concentration, defect density, atomic ratio of metal elements and oxygen, interatomic distance, density, etc. of the semiconductor layer appropriate.

[0156] In an oxide semiconductor constituting a semiconductor layer, when silicon or carbon, which is one of the Group 14 elements, is contained, oxygen deficiency increases and the semiconductor becomes n-type. Therefore, the concentration of silicon or carbon in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is set to 2×10 18 atoms / cm 3 or less, preferably 2×10 17 atoms / cm 3 or less.

[0157] In addition, when an alkali metal or an alkaline earth metal combines with an oxide semiconductor, carriers may be generated, and the off-current of the transistor may increase. Therefore, the concentration of the alkali metal or alkaline earth metal in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is set to 1×10 18 atoms / cm 3 or less, preferably 2×10 16 atoms / cm 3 or less.

[0158] Further, when nitrogen is contained in the oxide semiconductor constituting the semiconductor layer, electrons as carriers are generated, the carrier density increases, and the semiconductor easily becomes n-type. As a result, a transistor using an oxide semiconductor containing nitrogen tends to have normally-on characteristics. Therefore, the nitrogen concentration in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is preferably set to 5×10 18 atoms / cm 3 or less.

[0159] In addition, when the oxide semiconductor constituting the semiconductor layer contains hydrogen, it reacts with oxygen that binds to metal atoms to form water, and thus oxygen vacancies may be formed in the oxide semiconductor. If the channel formation region in the oxide semiconductor contains oxygen vacancies, the transistor may exhibit normally-on characteristics. Furthermore, defects in which hydrogen enters oxygen vacancies may function as donors, and electrons, which are carriers, may be generated. Also, a part of hydrogen may bind to oxygen that binds to metal atoms to generate electrons, which are carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen tends to have normally-on characteristics.

[0160] Defects in which hydrogen enters oxygen vacancies can function as donors in the oxide semiconductor. However, it is difficult to quantitatively evaluate such defects. Therefore, in the oxide semiconductor, it may be evaluated by carrier concentration instead of donor concentration. Thus, in this specification and the like, as a parameter of the oxide semiconductor, carrier concentration assuming a state where no electric field is applied may be used instead of donor concentration. That is, the "carrier concentration" described in this specification and the like may be able to be paraphrased as the "donor concentration".

[0161] Therefore, it is preferable that hydrogen in the oxide semiconductor is reduced as much as possible. Specifically, in the oxide semiconductor, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS) is less than 1×10 20 atoms / cm 3 , preferably less than 1×10 19 atoms / cm 3 , more preferably less than 5×10 18 atoms / cm 3 , still more preferably less than 1×10 18 atoms / cm 3 . By using an oxide semiconductor in which impurities such as hydrogen are sufficiently reduced in the channel formation region of the transistor, stable electrical characteristics can be imparted.

[0162] Further, the semiconductor layer may have, for example, a non-single crystal structure. The non-single crystal structure includes, for example, CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) having crystals oriented along the c-axis, a polycrystalline structure, a microcrystalline structure, or an amorphous structure. In the non-single crystal structure, the amorphous structure has the highest density of defect levels, and CAAC-OS has the lowest density of defect levels.

[0163] The oxide semiconductor film having an amorphous structure has, for example, a disordered atomic arrangement and no crystal component. Or, the oxide film having an amorphous structure is, for example, a completely amorphous structure and has no crystal part.

[0164] Note that the semiconductor layer may be a mixed film having two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. The mixed film may have, for example, a single layer structure or a laminated structure including any two or more of the above-described regions.

[0165] Hereinafter, the configuration of CAC (Cloud-Aligned Composite)-OS, which is one aspect of the non-single crystal semiconductor layer, will be described.

[0166] CAC-OS is, for example, a configuration of a material in which the elements constituting the oxide semiconductor are unevenly distributed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or in the vicinity thereof. Hereinafter, in the oxide semiconductor, a state in which one or more metal elements are unevenly distributed and the regions having the metal elements are mixed in a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less, or in the vicinity thereof is also referred to as a mosaic state or a patch state.

[0167] Note that the oxide semiconductor preferably contains at least indium. In particular, it preferably contains indium and zinc. In addition to these, one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium may be contained.

[0168] For example, in the In-Ga-Zn oxide, CAC-OS (among CAC-OS, the In-Ga-Zn oxide may be particularly referred to as CAC-IGZO.) refers to indium oxide (hereinafter, InO X1 (Let X1 be a real number greater than 0).), or indium zinc oxide (hereinafter, In X2 Zn Y2 O Z2 (Let X2, Y2, and Z2 be real numbers greater than 0).), and gallium oxide (hereinafter, GaO X3 (Let X3 be a real number greater than 0).), or gallium zinc oxide (hereinafter, Ga X4 Zn Y4 O Z4 (Let X4, Y4, and Z4 be real numbers greater than 0).) and the like, and the materials are separated to form a mosaic shape, and the mosaic-shaped InO X1 , or In X2 Zn Y2 O Z2 is distributed uniformly in the film (hereinafter, also referred to as a cloud shape).

[0169] That is, CAC-OS is a composite oxide semiconductor having a structure in which a region mainly composed of GaO X3 and a region mainly composed of In X2 Zn Y2 O Z2 , or InO X1 are mixed. In this specification, for example, when the atomic ratio of indium to the element M in the first region is greater than the atomic ratio of indium to the element M in the second region, it is said that the concentration of indium in the first region is higher than that in the second region.

[0170] Note that IGZO is a common name and may refer to a single compound of In, Ga, Zn, and O. As a representative example, InGaO3(ZnO) m1 (m1 is a natural number), or In (1+x0) Ga (1-x0) O3(ZnO) m0 (-1 ≦ x0 ≦ 1, m0 is an arbitrary number). Examples of crystalline compounds include those represented by this formula

[0171] The above crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. Note that the CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis orientation and are connected without orientation in the a-b plane

[0172] On the other hand, CAC-OS relates to the material composition of the oxide semiconductor. CAC-OS refers to a structure in which in a material composition containing In, Ga, Zn, and O, regions observed as nanoparticle-like regions with Ga as a main component and regions observed as nanoparticle-like regions with In as a main component are randomly dispersed in a mosaic pattern. Therefore, in CAC-OS, the crystal structure is a secondary element

[0173] Note that CAC-OS does not include a laminated structure of two or more types of films with different compositions. For example, a structure composed of two layers of a film with In as a main component and a film with Ga as a main component is not included

[0174] Note that GaO X3 in the region where it is the main component and In X2 Zn Y2 O Z2 , or InO X1 in the region where it is the main component may not have a clear boundary

[0175] In addition, when one or more selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium are included instead of gallium, CAC-OS refers to a structure in which regions observed as nanoparticles mainly composed of the metal element and regions observed as nanoparticles mainly composed of In are randomly dispersed in a mosaic pattern, respectively.

[0176] CAC-OS can be formed by a sputtering method, for example, under conditions where the substrate is not intentionally heated. Also, when forming CAC-OS by the sputtering method, any one or more selected from inert gases (typically argon), oxygen gas, and nitrogen gas may be used as the film-forming gas. Further, the lower the flow rate ratio of oxygen gas to the total flow rate of the film-forming gas during film formation, the more preferable it is. For example, it is preferable that the flow rate ratio of oxygen gas is 0% or more and less than 30%, preferably 0% or more and 10% or less.

[0177] CAC-OS has the characteristic that no distinct peak is observed when measured using θ / 2θ scan by the Out-of-plane method, which is one of the X-ray diffraction (XRD) measurement methods. That is, it can be seen from the X-ray diffraction measurement that there is no orientation in the a-b plane direction and the c-axis direction of the measurement region.

[0178] Also, in the electron diffraction pattern obtained by irradiating an electron beam with a probe diameter of 1 nm (also referred to as a nano-beam electron beam), a region with high luminance in a ring shape (ring region) and a plurality of bright spots are observed in the ring region. Therefore, it can be seen from the electron diffraction pattern that the crystal structure of CAC-OS has an nc (nano-crystal) structure without orientation in the plane direction and the cross-sectional direction.

[0179] Also, for example, in CAC-OS in In-Ga-Zn oxide, regions where GaO X3 is the main component and regions where In X2 Zn Y2 O Z2 , or InO X1 is the main component are unevenly distributed and mixed, and it can be confirmed that they have a structure.

[0180] CAC-OS has a structure different from that of an IGZO compound in which metal elements are uniformly distributed and has properties different from those of an IGZO compound. That is, CAC-OS has regions where components such as GaO X3 are the main component and regions where In X2 Zn Y2 O Z2 , or InO X1 is the main component, and they are phase-separated from each other, and the regions with each element as the main component have a mosaic-like structure.

[0181] Here, regions where In X2 Zn Y2 O Z2 , or InO X1 is the main component are regions with higher conductivity compared to regions where components such as GaO X3 are the main component. That is, when carriers flow through regions where In X2 Zn Y2 O Z2 , or InO X1 is the main component, conductivity as an oxide semiconductor is exhibited. Therefore, when regions where In X2 Zn Y2 O Z2 , or InO X1 is the main component are distributed in a cloud-like manner in the oxide semiconductor, high field-effect mobility (μ) can be realized.

[0182] On the other hand, regions where components such as GaO X3 are the main component are In X2 Zn Y2 O Z2 , or InOX1 is a region with high insulation compared to the region where it is the main component. That is, the region where X3 such as is the main component is distributed in the oxide semiconductor, suppressing the leakage current and enabling a good switching operation.

[0183] Therefore, when CAC-OS is used in a semiconductor device, the insulation due to X3 such as and the conductivity due to X2 In Y2 Zn Z2 O X1 or InO on act complementarily to realize a high on-current (I

[0184] Also, the semiconductor device using CAC-OS has high reliability. Therefore, CAC-OS is suitable as a constituent material for various semiconductor devices.

[0185] <Stacked Structure 1> Next, the stacked structure of the imaging device will be described using a cross-sectional view. Note that the elements such as the insulating layer and the conductive layer shown below are examples, and other elements may be further included. Or, some of the elements shown below may be omitted. Also, the stacked structure shown below can be formed using a bonding process, a polishing process, etc. as necessary.

[0186] FIG. 19 is an example of a cross-sectional view of a laminate having layer 560, layer 561, layer 563, and having a bonding surface between layer 563a and layer 563b that constitute layer 563.

[0187] <Layer 563b> Layer 563b can have a functional circuit provided on a silicon substrate 611. Here, as some of the transistors included in the functional circuit, transistor 223, transistor 224, and transistor 225 are shown. Note that transistor 225 is exemplified as a transistor included in binarization circuit 22.

[0188] The layer 563b is provided with a silicon substrate 611, insulating layers 612, 613, 614, 616, 617, 618. The insulating layer 612 has a function as a protective film. The insulating layers 613, 614, 616, 617 have functions as an interlayer insulating film and a planarization film. The insulating layer 618 and the conductive layer 619 have functions as a bonding layer. The conductive layer 619 is electrically connected to the gate of the transistor 225.

[0189] As the protective film, for example, a silicon nitride film, a silicon oxide film, an aluminum oxide film, etc. can be used. As the interlayer insulating film and the planarization film, for example, an inorganic insulating film such as a silicon oxide film, an organic insulating film such as an acrylic resin or a polyimide resin can be used. As the dielectric layer of the capacitor, a silicon nitride film, a silicon oxide film, an aluminum oxide film, etc. can be used. The bonding layer will be described later.

[0190] In addition, as the conductor that can be used as the wiring, electrode, and plug for the electrical connection between devices, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements, etc. can be appropriately selected and used. The conductor is not limited to a single layer and may be a plurality of layers composed of different materials.

[0191] <Layer 563a> The layer 563a has the elements of the pixel 14. It may also have the elements of the functional circuit. Here, as a part of the elements of the pixel 14, the transistors 102 and 105 included in the pixel circuit 15 are shown. In the cross-sectional view shown in FIG. 19, the electrical connection between the two is not shown.

[0192] On layer 563a, a silicon substrate 632, insulating layers 631, 633, 634, 635, 637, 638 are provided. Also, conductive layers 636, 639 are provided.

[0193] Insulating layer 631 and conductive layer 639 have the function as a bonding layer. Insulating layers 634, 635, 637 have the function as an interlayer insulating film and a planarizing film. Insulating layer 633 has the function as a protective film. Insulating layer 638 has the function of insulating silicon substrate 632 and conductive layer 639. Insulating layer 638 can be formed of the same material as other insulating layers. Also, insulating layer 638 may be formed of the same material as insulating layer 631.

[0194] Conductive layer 639 is electrically connected to the other of the source or drain of transistor 105 and conductive layer 619. Also, conductive layer 636 is electrically connected to wiring 111 (see FIG. 10A).

[0195] The Si transistor shown in FIG. 19 is a fin type having a channel formation region on a silicon substrate (silicon substrates 611, 632). A cross-section in the channel width direction (the cross-section of A1 - A2 shown in layer 563a of FIG. 19) is shown in FIG. 20A. Note that the Si transistor may be a planar type as shown in FIG. 20B.

[0196] Or, as shown in FIG. 20C, it may be a transistor having a semiconductor layer 545 of a silicon thin film. Semiconductor layer 545 can be, for example, single-crystalline silicon (SOI (Silicon on Insulator)) formed on insulating layer 546 on silicon substrate 632.

[0197] <layer 561> Layer 561 has a photoelectric conversion device 101. Photoelectric conversion device 101 can be formed on layer 563a. In FIG. 19, as photoelectric conversion device 101, a configuration using the organic photoconductive film shown in FIG. 18C as a photoelectric conversion layer is shown. Here, layer 567a is used as the cathode and layer 567e is used as the anode.

[0198] The layer 561 is provided with insulating layers 651, 652, 653, 654, and a conductive layer 655.

[0199] The insulating layers 651, 653, 654 have functions as an interlayer insulating film and a planarization film. Further, the insulating layer 654 is provided to cover an end portion of the photoelectric conversion device 101 and also has a function of preventing a short circuit between the layer 567e and the layer 567a. The insulating layer 652 has a function as an element isolation layer. As the element isolation layer, it is preferable to use an organic insulating film or the like.

[0200] The layer 567a corresponding to the cathode of the photoelectric conversion device 101 is electrically connected to one of the source or drain of the transistor 102 included in the layer 563a. The layer 567e corresponding to the anode of the photoelectric conversion device 101 is electrically connected to the conductive layer 636 included in the layer 563a via the conductive layer 655.

[0201] <layer 560> The layer 560 is formed on the layer 561. The layer 560 has a light-shielding layer 671, an optical conversion layer 672, and a microlens array 673.

[0202] The light-shielding layer 671 can suppress the inflow of light into adjacent pixels. As the light-shielding layer 671, a metal layer such as aluminum or tungsten can be used. Further, a dielectric film having a function as an antireflection film may be laminated on the metal layer.

[0203] When the photoelectric conversion device 101 has sensitivity to visible light, a color filter can be used for the optical conversion layer 672. By assigning colors such as R (red), G (green), B (blue), Y (yellow), C (cyan), M (magenta) to each pixel of the color filter, a color image can be obtained. For example, as shown in the perspective view (including a cross section) of FIG. 28A, the color filter 672R (red), the color filter 672G (green), and the color filter 672B (blue) can be assigned to different pixels, respectively.

[0204] Also, in a combination of an appropriate photoelectric conversion device 101 and an optical conversion layer 672, if a wavelength cut filter is used for the optical conversion layer 672, an imaging device capable of obtaining images in various wavelength regions can be achieved.

[0205] For example, if an infrared filter that blocks light with a wavelength equal to or less than that of visible light is used for the optical conversion layer 672, an infrared imaging device can be achieved. Also, if a filter that blocks light with a wavelength equal to or less than that of near-infrared light is used for the optical conversion layer 672, a far-infrared imaging device can be achieved. Further, if an ultraviolet filter that blocks light with a wavelength equal to or greater than that of visible light is used for the optical conversion layer 672, an ultraviolet imaging device can be achieved.

[0206] Note that a plurality of different optical conversion layers may be arranged in one imaging device. For example, as shown in FIG. 28B, a color filter 672R (red), a color filter 672G (green), a color filter 672B (blue), and an infrared filter 672IR can be assigned to different pixels. With this configuration, a visible light image and an infrared light image can be acquired simultaneously.

[0207] Alternatively, as shown in FIG. 28C, a color filter 672R (red), a color filter 672G (green), a color filter 672B (blue), and an ultraviolet filter 672UV can be assigned to different pixels. With this configuration, a visible light image and an ultraviolet light image can be acquired simultaneously.

[0208] Also, if a scintillator is used for the optical conversion layer 672, an imaging device capable of obtaining an image in which the intensity of radiation used in an X-ray imaging device or the like is visualized can be achieved. When radiation such as X-rays transmitted through a subject is incident on the scintillator, it is converted into light (fluorescence) such as visible light or ultraviolet light by the photoluminescence phenomenon. Then, the image data is acquired by detecting the light with the photoelectric conversion device 101. Also, the imaging device having this configuration may be used for a radiation detector or the like.

[0209] A scintillator contains a substance that absorbs the energy of radiation such as X-rays or gamma rays and emits visible light or ultraviolet light. For example, substances such as Gd2O2S:Tb, Gd2O2S:Pr, Gd2O2S:Eu, BaFCl:Eu, NaI, CsI, CaF2, BaF2, CeF3, LiF, LiI, ZnO dispersed in resin or ceramics can be used.

[0210] By performing imaging with infrared light or ultraviolet light, inspection functions, security functions, sensor functions, etc. can be imparted to an imaging device. For example, by performing imaging with infrared light, non-destructive inspection of products, sorting of agricultural products (such as a refractometer function), vein authentication, medical inspections, etc. can be performed. Also, by performing imaging with ultraviolet light, ultraviolet light emitted from a light source or a flame can be detected, and management of light sources, heat sources, production equipment, etc. can be performed.

[0211] A microlens array 673 is provided on the optical conversion layer 672. Light passing through each lens of the microlens array 673 passes through the optical conversion layer 672 directly below and is irradiated onto the photoelectric conversion device 101. By providing the microlens array 673, the condensed light can be incident on the photoelectric conversion device 101, so that photoelectric conversion can be performed efficiently. The microlens array 673 is preferably formed of resin, glass, etc. that have high light transmittance for light of the target wavelength.

[0212] <Lamination> Next, the lamination of layer 563b and layer 563a will be described.

[0213] An insulating layer 618 and a conductive layer 619 are provided on layer 563b. The conductive layer 619 has a region embedded in the insulating layer 618. Also, the surfaces of the insulating layer 618 and the conductive layer 619 are flattened so that their heights are the same.

[0214] An insulating layer 631 and a conductive layer 639 are provided in layer 563a. The conductive layer 639 has a region embedded in the insulating layer 631. Also, the surfaces of the insulating layer 631 and the conductive layer 639 are flattened so that their heights match respectively.

[0215] Here, it is preferable that the main components of the conductive layer 619 and the conductive layer 639 are the same metal element. Also, it is preferable that the insulating layer 618 and the insulating layer 631 are composed of the same components.

[0216] For example, for the conductive layers 619, 639, Cu, Al, Sn, Zn, W, Ag, Pt, Au, etc. can be used. From the viewpoint of ease of bonding, preferably Cu, Al, W, or Au is used. Also, for the insulating layers 618, 631, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, titanium nitride, etc. can be used.

[0217] That is, it is preferable to use the same metal material shown above for each of the conductive layer 619 and the conductive layer 639. Also, it is preferable to use the same insulating material shown above for each of the insulating layer 618 and the insulating layer 631. With such a configuration, bonding can be performed with the boundary between layer 563b and layer 563a as the bonding position.

[0218] Note that the conductive layer 619 and the conductive layer 639 may have a multilayer structure of multiple layers. In that case, it is only necessary that the surface layer (bonding surface) is the same metal material. Also, the insulating layer 618 and the insulating layer 631 may also have a multilayer structure of multiple layers. In that case, it is only necessary that the surface layer (bonding surface) is the same insulating material.

[0219] By this bonding, electrical connection of the conductive layer 619 and the conductive layer 639 can be obtained. Also, a connection having the mechanical strength of the insulating layer 618 and the insulating layer 631 can be obtained.

[0220] For the bonding between metal layers, a surface activation bonding method can be used, in which the oxide film on the surface and the adsorbed layer of impurities are removed by sputtering or the like, and the cleaned and activated surfaces are brought into contact with each other for bonding. Alternatively, a diffusion bonding method or the like in which the surfaces are bonded together using a combination of temperature and pressure can be used. Since bonding occurs at the atomic level in both cases, excellent bonding can be obtained not only electrically but also mechanically.

[0221] In addition, for the bonding between insulating layers, after obtaining high flatness by polishing or the like, a hydrophilic bonding method or the like can be used, in which the surfaces that have been subjected to hydrophilic treatment with oxygen plasma or the like are brought into contact with each other for temporary bonding, and permanent bonding is performed by dehydration through heat treatment. Since bonding also occurs at the atomic level in the hydrophilic bonding method, excellent mechanical bonding can be obtained.

[0222] When laminating layer 563b and layer 563a, since the insulating layer and the metal layer are mixed on each bonding surface, for example, a combination of the surface activation bonding method and the hydrophilic bonding method can be used.

[0223] For example, a method can be used in which the surface is cleaned after polishing, an antioxidant treatment is performed on the surface of the metal layer, and then a hydrophilic treatment is performed for bonding. Also, the surface of the metal layer can be made of a metal with poor oxidation resistance such as Au, and a hydrophilic treatment can be performed. In addition, a bonding method other than the methods described above may be used.

[0224] By the above lamination, the circuit included in layer 563b and the elements of pixel 14 included in layer 563a can be electrically connected.

[0225] <Modification Example of Stacked Structure 1> FIG. 21 is a modification example of the stacked structure shown in FIG. 19, in which the configuration of the photoelectric conversion device 101 included in layer 561 and a partial configuration of layer 563a are different, and there is also a bonding surface between layer 561 and layer 563a.

[0226] Layer 561 includes a photoelectric conversion device 101, insulating layers 661, 662, 664, 665, and conductive layers 685, 686.

[0227] The photoelectric conversion device 101 is a pn junction type photodiode and has a layer 565b corresponding to a p-type region and a layer 565a corresponding to an n-type region. Here, an example in which a pn junction type photodiode is formed on a silicon substrate is shown. The photoelectric conversion device 101 is an embedded type photodiode, and the dark current can be suppressed and the noise can be reduced by a thin p-type region (a part of the layer 565b) provided on the surface side (current extraction side) of the layer 565a.

[0228] The insulating layer 661, the conductive layers 685 and 686 have a function as a bonding layer. The insulating layer 662 has a function as an interlayer insulating film and a planarizing film. The insulating layer 664 has a function as an element isolation layer.

[0229] A groove for separating pixels is provided in the silicon substrate, and the insulating layer 665 is provided on the upper surface of the silicon substrate and in the groove. By providing the insulating layer 665, carriers generated in the photoelectric conversion device 101 can be suppressed from flowing out to adjacent pixels. In addition, the insulating layer 665 also has a function of suppressing the intrusion of stray light. Therefore, color mixing can be suppressed by the insulating layer 665. Note that an antireflection film may be provided between the upper surface of the silicon substrate and the insulating layer 665.

[0230] The insulating layer 664 can be formed using the LOCOS (LOCal Oxidation of Silicon) method. Alternatively, it may be formed using the STI (Shallow Trench Isolation) method or the like. As the insulating layer 665, for example, an inorganic insulating film such as silicon oxide or silicon nitride, or an organic insulating film such as a polyimide resin or an acrylic resin can be used. Note that the insulating layer 665 may have a multilayer structure. Also, a space may be provided in a part of the insulating layer 665. The space may contain a gas such as air or an inert gas. Also, the space may be in a reduced pressure state.

[0231] The layer 565a (n-type region, corresponding to the cathode) of the photoelectric conversion device 101 is electrically connected to the conductive layer 685. The layer 565b (p-type region, corresponding to the anode) is electrically connected to the conductive layer 686. The conductive layers 685 and 686 have regions embedded in the insulating layer 661. Also, the surfaces of the insulating layer 661 and the conductive layers 685 and 686 are flattened so that their heights match respectively.

[0232] In the layer 563a, an insulating layer 638 is formed on the insulating layer 637. Also, a conductive layer 683 electrically connected to one of the source or drain of the transistor 102, and a conductive layer 684 electrically connected to the conductive layer 636 are formed.

[0233] The insulating layer 638 and the conductive layers 683 and 684 function as a bonding layer. The conductive layers 683 and 684 have regions embedded in the insulating layer 638. Also, the surfaces of the insulating layer 638 and the conductive layers 683 and 684 are flattened so that their heights match respectively.

[0234] Here, the conductive layers 683, 684, 685, and 686 are the same bonding layers as the conductive layers 619 and 639 described above. Also, the insulating layers 638 and 661 are the same bonding layers as the insulating layers 618 and 631 described above.

[0235] Therefore, by bonding the conductive layer 683 and the conductive layer 685, one of the source or drain of the transistor 102 can be electrically connected to the layer 565a (n-type region, corresponding to the cathode) of the photoelectric conversion device 101. Also, by bonding the conductive layer 684 and the conductive layer 686, the layer 565b (p-type region, corresponding to the anode) of the photoelectric conversion device 101 can be electrically connected to the wiring 111 (see FIG. 10A). Also, by bonding the insulating layer 638 and the insulating layer 661, electrical and mechanical bonding between the layer 561 and the layer 563a can be performed.

[0236] Further, FIG. 22 shows a modified example different from the above, in which the transistor 102 is provided in the layer 561. In this configuration, one of the source or drain of the transistor 102 is directly connected to the photoelectric conversion device 101, and the other of the source or drain acts as the node N. In this configuration, complete transfer of the charges accumulated in the photoelectric conversion device 101 is possible, and an imaging device with less noise can be obtained.

[0237] Here, the other of the source or drain of the transistor 102 included in the layer 561 is electrically connected to the conductive layer 692. Also, the gate of the transistor 104 included in the layer 563 is electrically connected to the conductive layer 691. The conductive layers 691 and 692 are the same bonding layers as the conductive layers 619 and 639 described above.

[0238] <Stacked Structure 2> FIG. 23 is an example of a cross-sectional view of a laminate having layers 560, 561, 562, and 563 and not having a bonding surface. An Si transistor is provided in the layer 563. An OS transistor is provided in the layer 562. Since the configurations of the layer 563, the layer 561, and the layer 560 are the same as those shown in FIG. 19, the description thereof is omitted here.

[0239] <Layer 562> The layer 562 is formed on the layer 563. The layer 562 has an OS transistor. Here, the transistor 102 and the transistor 105 are shown. In the cross-sectional view shown in FIG. 23, the electrical connection between the two is not shown.

[0240] The layer 562 is provided with insulating layers 621, 622, 623, 624, 625, 626, and 628. Also, a conductive layer 627 is provided. The conductive layer 627 can be electrically connected to the wiring 111 (see FIG. 10A).

[0241] The insulating layer 621 has a function as a blocking layer. The insulating layers 622, 623, 625, 626, and 628 have functions as an interlayer insulating film and a planarizing film. The insulating layer 624 has a function as a protective film.

[0242] As the blocking layer, it is preferable to use a film having a function of preventing the diffusion of hydrogen. In an Si device, hydrogen is required to terminate dangling bonds, but hydrogen in the vicinity of an OS transistor becomes one of the factors for generating carriers in the oxide semiconductor layer and reduces reliability. Therefore, it is preferable to provide a hydrogen blocking film between the layer where the Si device is formed and the layer where the OS transistor is formed.

[0243] As the blocking film, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia (YSZ), etc. can be used.

[0244] The other of the source or drain of transistor 105 is electrically connected to the gate of transistor 225 via a plug. Also, conductive layer 627 is electrically connected to wiring 111 (see FIG. 10A).

[0245] One of the source or drain of transistor 102 is electrically connected to the cathode of the photoelectric conversion device 101 included in layer 561. Conductive layer 627 is electrically connected to the anode of the photoelectric conversion device 101 included in layer 561.

[0246] The details of the OS transistor are shown in FIG. 24A. The OS transistor shown in FIG. 24A has a self-aligned structure in which an insulating layer is provided on a stack of an oxide semiconductor layer and a conductive layer, and source electrode 705 and drain electrode 706 are formed by providing an opening reaching the oxide semiconductor layer.

[0247] The OS transistor can be configured to include a channel formation region 708, a source region 703, and a drain region 704 formed in an oxide semiconductor layer, as well as a gate electrode 701 and a gate insulating film 702. At least the gate insulating film 702 and the gate electrode 701 are provided in the opening. An oxide semiconductor layer 707 may further be provided in the opening.

[0248] As shown in FIG. 24B, the OS transistor may have a self-aligned structure in which the source region 703 and the drain region 704 are formed in the semiconductor layer using the gate electrode 701 as a mask.

[0249] Alternatively, as shown in FIG. 24C, it may be a non-self-aligned top-gate transistor having a region where the source electrode 705 or the drain electrode 706 overlaps with the gate electrode 701.

[0250] Although the OS transistor is shown having a back gate 735, it may also have a structure without a back gate. The back gate 735 may be electrically connected to the front gate of the transistors provided opposite to each other, as in the cross-sectional view in the channel width direction of the transistor shown in FIG. 24D. Note that FIG. 24D shows an example of the cross-section of B1 - B2 of the transistor in FIG. 24A, and the same applies to transistors with other structures. Also, it may be configured such that a fixed potential different from that of the front gate can be supplied to the back gate 735.

[0251] <Modification Example of Stacked Structure 2> FIG. 25 is a modification example of the stacked structure shown in FIG. 23, in which the configuration of the photoelectric conversion device 101 included in layer 561 and a partial configuration of layer 562 are different, and there is a bonding surface between layer 561 and layer 562.

[0252] The photoelectric conversion device 101 included in layer 561 is a pn junction type photodiode, which is the same as the configuration shown in FIG. 21.

[0253] In layer 562, an insulating layer 648 is formed on the insulating layer 628. Also, a conductive layer 688 electrically connected to one of the source or drain of the transistor 102, and a conductive layer 689 electrically connected to the conductive layer 627 are formed.

[0254] The insulating layer 648, and the conductive layers 688 and 689 function as bonding layers. The conductive layers 688 and 689 have regions embedded in the insulating layer 648. Also, the surfaces of the insulating layer 648 and the conductive layers 688 and 689 are planarized so that their heights match respectively.

[0255] Here, the conductive layers 688 and 689 are the same bonding layers as the conductive layers 619 and 639 described above. Also, the insulating layer 648 is the same bonding layer as the insulating layers 618 and 631 described above.

[0256] Therefore, by bonding the conductive layer 688 and the conductive layer 685, one of the source or drain of the transistor 102 can be electrically connected to the layer 565a (n-type region, corresponding to the cathode) of the photoelectric conversion device 101. Also, by bonding the conductive layer 689 and the conductive layer 686, the layer 565b (p-type region, corresponding to the anode) of the photoelectric conversion device 101 can be electrically connected to the wiring 111 (see FIG. 10A). Also, by bonding the insulating layer 648 and the insulating layer 661, electrical and mechanical bonding between the layer 561 and the layer 562 can be performed.

[0257] When stacking a plurality of Si devices, a polishing process and a bonding process are required multiple times. Therefore, there are problems such as a large number of processes, the need for dedicated equipment, and low yield, and the manufacturing cost is also high. Since the OS transistor can be formed by stacking on a semiconductor substrate on which the device is formed, the bonding process can be reduced.

[0258] Note that a configuration in which the transistor 102 is provided in the layer 561 shown in FIG. 22 may be applied to the said configuration.

[0259] In addition, the memory cell 150 can be provided, for example, in the layer 562. FIG. 26 shows a configuration in which transistors 102, 105, etc. that are elements of the pixel circuit and transistors 273, etc. that are elements of the memory cell 150 are provided on the same plane of the layer 562.

[0260] Further, FIG. 27 shows a stacked configuration in which, in the layer 562, regions where transistors 102, 104, 105, etc. that are elements of the pixel circuit and transistors 272, 273, etc. that are elements of the memory cell 150 overlap are provided. With this configuration, the circuit area can be reduced, and a highly functional and compact imaging device can be formed. In addition, since the wiring length of the wiring for electrically connecting between the stacked elements can be shortened, operation at high speed and with low power consumption becomes possible.

[0261] Note that the configuration in which the transistor 102 is provided in the layer 561 shown in FIG. 22 may be applied to the configurations shown in FIGS. 26 and 27. Also, the configuration of the photoelectric conversion device 101 shown in FIG. 23 may be applied.

[0262] <Package, Module> FIG. 29A is an external perspective view of a package containing an image sensor chip. The package is a CSP (Chip Size Package) and includes a bare chip 450 of the image sensor, a cover glass 440, an adhesive 430 for bonding the two, and the like.

[0263] The electrode pads 425 provided outside the pixel array 455 are electrically connected to the back surface electrodes 415 via the through electrodes 420. The electrode pads 425 are electrically connected to the circuit constituting the image sensor by wiring or wires. Note that the bare chip 450 may be a stacked chip stacked with circuits having various functions.

[0264] FIG. 29 illustrates a BGA (Ball Grid Array) in which bumps 410 are formed on the back electrode 415 using solder balls. Note that the present invention is not limited to BGA, and an LGA (Land Grid Array) or a PGA (Pin Grid Array) may be used instead. Alternatively, a package in which the bare chip 450 is mounted on a QFN (Quad Flat No-lead package) or a QFP (Quad Flat Package) may be used.

[0265] FIG. 29B is an external perspective view of the upper surface side of a camera module combining an image sensor chip and a lens. The camera module includes a lens cover 460, a plurality of lenses 470, etc. on the configuration of FIG. 29A. An optical filter 480 that absorbs light of a specific wavelength is provided between the lens 470 and the cover glass 440 as needed. As the optical filter 480, for example, an infrared cut filter or the like can be used in the case of an image sensor mainly for visible light imaging.

[0266] By housing the image sensor chip in a package of the above-described form, mounting on a printed circuit board or the like becomes easy, and the image sensor chip can be incorporated into various semiconductor devices and electronic equipment.

[0267] This embodiment can be appropriately combined with the descriptions of other embodiments.

[0268] (Embodiment 4) Examples of electronic devices that can use the imaging device according to an aspect of the present invention include display devices, personal computers, image storage devices or image playback devices equipped with recording media, mobile phones, game machines including portable types, portable data terminals, e-book terminals, video cameras, cameras such as digital still cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, printer multifunction devices, automated teller machines (ATMs), vending machines, and the like. Specific examples of these electronic devices are shown in FIGS. 30A to 30F.

[0269] FIG. 30A shows an example of a mobile phone, which includes a housing 981, a display unit 982, operation buttons 983, an external connection port 984, a speaker 985, a microphone 986, a camera 987, and the like. The mobile phone is provided with a touch sensor on the display unit 982. Any operation such as making a call or inputting characters can be performed by touching the display unit 982 with a finger or a stylus. The imaging device and its operation method according to an aspect of the present invention can be applied to the mobile phone.

[0270] FIG. 30B is a portable data terminal, which includes a housing 911, a display unit 912, a speaker 913, a camera 919, and the like. Information can be input and output by the touch panel function of the display unit 912. Also, characters and the like can be recognized from the image acquired by the camera 919, and the characters can be output as audio by the speaker 913. The imaging device and its operation method according to an aspect of the present invention can be applied to the portable data terminal.

[0271] FIG. 30C is a surveillance camera, which includes a support base 951, a camera unit 952, a protective cover 953, etc. A rotation mechanism and the like are provided in the camera unit 952, and by installing it on the ceiling, it is possible to capture images of the entire surrounding area. The imaging device and its operation method according to an aspect of the present invention can be applied to the elements for image acquisition in the camera unit. Note that the surveillance camera is a common name and does not limit the use. For example, a device having the function of a surveillance camera is also called a camera or a video camera.

[0272] FIG. 30D is a drive recorder, which includes a frame 941, a camera 942, an operation button 943, mounting parts 944, etc. By installing it on the front window of an automobile via the mounting parts 944, it is possible to record the scenery in front during driving. A display panel for displaying the recorded image is provided on the back surface (not shown). The imaging device and its operation method according to an aspect of the present invention can be applied to the camera 942.

[0273] FIG. 30E is a digital camera, which includes a housing 961, a shutter button 962, a microphone 963, a light emitting part 967, a lens 965, etc. The imaging device and its operation method according to an aspect of the present invention can be applied to the digital camera.

[0274] FIG. 30F is a wristwatch-type information terminal, which includes a display part 932, a housing-cum-wristband 933, a camera 939, etc. The display part 932 is provided with a touch panel for operating the information terminal. The display part 932 and the housing-cum-wristband 933 have flexibility and excellent wearability on the body. The imaging device and its operation method according to an aspect of the present invention can be applied to the information terminal.

[0275] FIG. 31A is a drone, which is an example of a mobile body, and includes a frame 921, arms 922, rotors 923, blades 924, a camera 925, a battery 926, etc., and has functions such as autonomous flight and hovering in the air. The imaging device and its operation method according to an aspect of the present invention can be applied to the camera 925.

[0276] FIG. 31B illustrates an external view of an automobile as an example of a moving body. The automobile 890 has a plurality of cameras 891 and the like, and can acquire information about the front, rear, left, right, and above of the automobile 890. The imaging device and its operation method according to an aspect of the present invention can be applied to the camera 891. In addition, the automobile 890 is provided with various sensors (not shown) such as an infrared radar, a millimeter-wave radar, and a laser radar. The automobile 890 analyzes the images acquired by the camera 891 in a plurality of imaging directions 892, determines the surrounding traffic conditions such as the presence or absence of guardrails or pedestrians, and can perform automatic driving. Further, it can be used in a system for performing road guidance, danger prediction, and the like.

[0277] In the imaging device according to an aspect of the present invention, by performing arithmetic processing such as a neural network on the obtained image data, for example, processes such as increasing the resolution of the image, reducing image noise, face recognition (for security purposes, etc.), object recognition (for the purpose of automatic driving, etc.), image compression, image correction (widening the dynamic range), image restoration of a lensless image sensor, positioning, character recognition, and reducing specular reflections can be performed.

[0278] Note that in the above description, the automobile may be any of an automobile having an internal combustion engine, an electric vehicle, a hydrogen vehicle, and the like. Further, the moving body is not limited to an automobile. For example, examples of the moving body include a train, a monorail, a ship, and an aircraft (helicopter, unmanned aerial vehicle, airplane, rocket), and a computer according to an aspect of the present invention can be applied to these moving bodies to provide a system using artificial intelligence.

Explanation of Reference Numerals

[0279] 10: Layer, 11: Pixel section, 12: Pixel block, 13: Pixel block, 14: Pixel, 15: Pixel circuit, 16: Memory circuit, 20: Layer, 21: Arithmetic unit, 22: Binarization circuit, 23: Multiplication and addition circuit, 23a: Multiplier, 23b: Adder, 24: Binarization circuit, 24S: Selection transistor, 25: Circuit, 26a: Addition circuit, 26b: Binarization circuit, 31: Load driver, 32: Column driver, 33: Load driver, 34: Column driver, 35: Circuit, 36: Circuit, 40: Circuit, 40S: Switch, 41: Circuit, 41S: Switch, 42S: Switch, 43S: Switch, 44S: Switch, 45S: Switch, 51: Register, 52: Register, 60: Circuit, 101: Photoelectric conversion device, 102: Transistor, 103: Transistor, 104: Transistor, 105: Transistor, 106: Capacitor, 107: Transistor, 108: Transistor, 109: Transistor, 111: Wiring, 112: Wiring, 113: Wiring, 114: Wiring, 115: Wiring, 116: Wiring, 117: Wiring, 118: Wiring, 119: Wiring, 150: Memory cell, 150a: Memory cell, 150b: Memory cell, 170: Back gate wiring, 175: Metal oxide layer, 180: Source-drain wiring, 185: Gate wiring, 190: Wiring, 223: Transistor, 224: Transistor, 225: Transistor, 272: Transistor, 273: Transistor, 274: Capacitor, 410: Bump, 415: Back electrode, 420: Through electrode, 425: Electrode pad, 430: Adhesive, 440: Cover glass, 450: Bare chip, 455: Pixel array, 460: Lens cover, 470: Lens, 480: Optical filter, 545: Semiconductor layer, 546: Insulating layer, 560: Layer, 561: Layer, 562: Layer, 562a: Layer, 562b: Layer, 563: Layer, 563a: Layer, 563b: Layer, 563c: Layer, 565a: Layer, 565b: Layer, 566a: Layer, 566b: Layer, 566c: Layer, 566d: Layer, 567a: Layer, 567b: Layer, 567c: Layer, 567d: Layer, 567e: Layer, 611: Silicon substrate, 612: Insulating layer, 613: Insulating layer, 614: Insulating layer, 616: Insulating layer, 617: Insulating layer, 618: Insulating layer, 619: Conductive layer, 621: Insulating layer, 622: Insulating layer, 623: Insulating layer, 624: Insulating layer, 625: Insulating layer, 626: Insulating layer, 627: Conductive layer, 628: Insulating layer,631: Insulating layer, 632: Silicon substrate, 633: Insulating layer, 634: Insulating layer, 635: Insulating layer, 636: Conductive layer, 637: Insulating layer, 638: Insulating layer, 639: Conductive layer, 648: Insulating layer, 651: Insulating layer, 652: Insulating layer, 653: Insulating layer, 654: Insulating layer, 655: Conductive layer, 661: Insulating layer, 662: Insulating layer, 664: Insulating layer, 665: Insulating layer, 671: Light-shielding layer, 672: Optical conversion layer, 672B: Color filter, 672G: Color filter, 672IR: Infrared filter, 672R: Color filter, 672UV: Ultraviolet filter, 673: Microlens array, 683: Conductive layer, 684: Conductive layer, 685: Conductive layer, 686: Conductive layer, 688: Conductive layer, 689: Conductive layer, 691: Conductive layer, 692: Conductive layer, 701: Gate electrode, 702: Gate insulating film, 703: Source region, 704: Drain region, 705: Source electrode, 706: Drain electrode, 707: Oxide semiconductor layer, 708: Channel formation region, 735: Back gate, 890: Automobile, 891: Camera, 892: Imaging direction, 911: Housing, 912: Display unit, 913: Speaker, 919: Camera, 921: Frame, 922: Arm, 923: Rotor, 924: Blade, 925: Camera, 926: Battery, 932: Display unit, 933: Housing and wristband, 939: Camera, 941: Frame, 942: Camera, 943: Operation button, 944: Component, 951: Support base, 952: Camera unit, 953: Protective cover, 961: Housing, 962: Shutter button, 963: Microphone, 965: Lens, 967: Light-emitting part, 981: Housing, 982: Display unit, 983: Operation button, 984: External connection port, 985: Speaker, 986: Microphone, 987: Camera,

Claims

Claim 1 An imaging device having a plurality of pixel blocks, wherein the pixel block has a first layer and a second layer, the first layer has a region overlapping with the second layer, the pixel block, the first layer has a plurality of pixel circuits and a plurality of first storage circuits, the second layer has a plurality of multiply-accumulate circuits, a plurality of first binarization circuits, and a plurality of second binarization circuits, the pixel circuit and the first storage circuit are an imaging device having a transistor having a metal oxide in a channel formation region.

Images