Method for manufacturing active matrix substrate, method for manufacturing liquid crystal display device, active matrix substrate, and liquid crystal display device

Abstract

To provide an active matrix substrate that is suitably used for a liquid crystal display panel of an in-cell type touch panel and a manufacturing method thereof.SOLUTION: A method for manufacturing an active matrix substrate comprises the steps of: (A) forming a plurality of TFTs on a substrate; (B) forming an interlayer insulating layer covering the plurality of TFTs; (C) forming a plurality of touch wires on the interlayer insulating layer; (D) forming a first dielectric layer covering the plurality of touch wires; (E) forming a common electrode on the first dielectric layer; (F) forming a second dielectric layer covering the common electrode; and (G) forming a plurality of pixel electrodes on the second dielectric layer. The interlayer insulating layer includes an organic insulating layer, and the step (B) includes the step of (B1) forming, using a multi-tone photomask, an organic insulating layer having a plurality of openings and a plurality of bump portions protruding upward.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing an active matrix substrate and a method for manufacturing a liquid crystal display device. The present invention also relates to an active matrix substrate and a liquid crystal display device. [Background technology]

[0002] In a liquid crystal display device equipped with an active matrix substrate, a pixel electrode and a switching element are provided for each pixel. Thin film transistors (hereinafter referred to as "TFTs") are widely used as switching elements. In each pixel, the TFT is electrically connected to the pixel electrode.

[0003] It has also been proposed to use oxide semiconductors as the material for the active layer of TFTs, instead of amorphous silicon or polycrystalline silicon. In this specification, the portions of the active matrix substrate that correspond to the pixels of a liquid crystal display device are referred to as "pixel regions" or "pixels." The TFTs provided as switching elements in each pixel are referred to as "pixel TFTs," and the connection portions that electrically connect the pixel TFTs and pixel electrodes in each pixel are referred to as "pixel contact portions."

[0004] A horizontal electric field mode such as FFS (Fringe Field Switching) mode is sometimes adopted as a display mode for liquid crystal display devices. In the horizontal electric field mode, a pair of electrodes (a pixel electrode and a common electrode) is provided on an active matrix substrate, and a horizontal electric field is applied to the liquid crystal molecules.

[0005] An active matrix substrate used in a lateral electric field mode liquid crystal display device may have a structure in which a common electrode is arranged above a pixel electrode (hereinafter referred to as a "common upper layer structure"), or a structure in which a common electrode is arranged below a pixel electrode (hereinafter referred to as a "common lower layer structure"). An active matrix substrate having a common lower layer structure is described in, for example, Patent Document 1.

[0006] Meanwhile, in recent years, display devices equipped with touch sensors (called "touch panels") have been widely used in smartphones, tablets, etc. There are various types of touch sensors known, including resistive, capacitive, and optical types.

[0007] Touch panels are broadly divided into two types: those in which the touch sensor is attached externally to the display device ("external type"), and those in which the touch sensor is built into the display device ("internal type"). Internal touch panels are advantageous over external touch panels in that they are thinner and lighter, and have the advantage of higher light transmittance.

[0008] There are two types of built-in touch panels: "on-cell" and "in-cell." Here, "cell" refers to the display panel. In the "in-cell" type, a layer that performs the touch sensor function is placed inside the display panel. In the "on-cell" type, the layer that performs the touch sensor function is placed between the display panel and a polarizing plate provided on the viewer side of the display panel.

[0009] In principle, the in-cell type can realize the thinnest and lightest touch panel. An in-cell type touch panel, in which a touch sensor is built into a lateral electric field mode liquid crystal display device, is disclosed in Patent Document 2, for example. [Prior art documents] [Patent documents]

[0010] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-109347 [Patent Document 2] International Publication No. 2016 / 136271 Summary of the Invention [Problem to be solved by the invention]

[0011] In an in-cell touch panel, the display panel is frequently pressed by a finger, etc. Therefore, if the display panel is a liquid crystal display panel, it is desirable to ensure a sufficient cell gap (thickness of the liquid crystal layer) even when the display panel is pressed.

[0012] The embodiments of the present invention have been made in view of the above problems, and an object of the present invention is to provide an active matrix substrate that is suitable for use in a liquid crystal display panel for an in-cell touch panel, and a method for manufacturing the same. [Means for solving the problem]

[0013] This specification discloses a method for manufacturing an active matrix substrate, a method for manufacturing a liquid crystal display device, an active matrix substrate, and a liquid crystal display device, as described in the following items.

[0014] [Item 1] A substrate; a plurality of thin film transistors supported by the substrate, each of the thin film transistors including an oxide semiconductor layer; an interlayer insulating layer covering the plurality of thin film transistors; a plurality of pixel electrodes disposed above the interlayer insulating layer; a common electrode disposed between the pixel electrodes and the interlayer insulating layer, the common electrode including a plurality of segments that can function as a plurality of touch sensor electrodes; a first dielectric layer disposed between the interlayer insulating layer and the common electrode; a second dielectric layer disposed between the common electrode and the plurality of pixel electrodes; a plurality of touch wirings arranged between the interlayer insulating layer and the common electrode, each of the plurality of touch wirings electrically connected to a corresponding one of the plurality of touch sensor electrodes; A method for manufacturing an active matrix substrate comprising: (A) forming the plurality of thin film transistors on the substrate; (B) forming an interlayer insulating layer covering the plurality of thin film transistors; (C) forming the plurality of touch wirings on the interlayer insulating layer; (D) forming the first dielectric layer covering the plurality of touch wirings; (E) forming the common electrode on the first dielectric layer; (F) forming the second dielectric layer to cover the common electrode; (G) forming the plurality of pixel electrodes on the second dielectric layer; It encompasses the interlayer insulating layer includes an organic insulating layer, The step (B) (B1) A method for producing an active matrix substrate, comprising the step of forming the organic insulating layer having a plurality of openings and a plurality of upwardly protruding bumps using a multi-tone photomask.

[0015] [Item 2] 2. The method for producing an active matrix substrate according to item 1, wherein in the step (B1), the organic insulating layer is formed from a photosensitive resin material.

[0016] [Item 3] 3. The method for manufacturing an active matrix substrate according to item 1 or 2, wherein the step (B1) is performed so that each of the plurality of bump portions at least partially overlaps each of the plurality of thin film transistors in a plan view.

[0017] [Item 4] Each of the plurality of thin film transistors further includes a gate electrode, a source electrode, and a drain electrode; the active matrix substrate further includes a plurality of pixel contact portions, each of which electrically connects one pixel electrode of the plurality of pixel electrodes to a corresponding thin film transistor of the plurality of thin film transistors; each of the plurality of pixel contact units includes a connection electrode that electrically connects the one pixel electrode and the drain electrode of the one thin film transistor; 4. The method for manufacturing an active matrix substrate according to any one of items 1 to 3, wherein the connection electrodes are formed in the step (C) from the same conductive film as the plurality of touch wirings.

[0018] [Item 5] 5. The method for manufacturing an active matrix substrate according to any one of items 1 to 4, wherein each of the plurality of thin film transistors has a bottom gate structure.

[0019] [Item 6] 6. The method for manufacturing an active matrix substrate according to any one of items 1 to 5, wherein the oxide semiconductor layer contains an In—Ga—Zn—O-based semiconductor.

[0020] [Item 7] an active matrix substrate; an opposing substrate disposed opposite the active matrix substrate; a liquid crystal layer provided between the active matrix substrate and the counter substrate; A method for manufacturing a liquid crystal display device comprising: (a) providing the active matrix substrate; (b) preparing the opposing substrate; It encompasses 7. A method for producing a liquid crystal display device, wherein the step (a) is carried out by the method according to any one of items 1 to 6.

[0021] [Item 8] the opposing substrate has a plurality of columnar spacers that define the thickness of the liquid crystal layer; 8. The method for manufacturing a liquid crystal display device according to item 7, wherein the plurality of bump portions of the organic insulating layer include two or more bump portions arranged so as to overlap the plurality of columnar spacers in a plan view.

[0022] [Item 9] A substrate; a plurality of thin film transistors supported by the substrate, each of the thin film transistors including an oxide semiconductor layer; an interlayer insulating layer covering the plurality of thin film transistors; a plurality of pixel electrodes disposed above the interlayer insulating layer; a common electrode disposed between the pixel electrodes and the interlayer insulating layer, the common electrode including a plurality of segments that can function as a plurality of touch sensor electrodes; a first dielectric layer disposed between the interlayer insulating layer and the common electrode; a second dielectric layer disposed between the common electrode and the plurality of pixel electrodes; a plurality of touch wirings arranged between the interlayer insulating layer and the common electrode, each of the plurality of touch wirings electrically connected to a corresponding one of the plurality of touch sensor electrodes; An active matrix substrate comprising: the interlayer insulating layer includes an organic insulating layer, The organic insulating layer has a plurality of openings and a plurality of bumps protruding upward.

[0023] [Item 10] Item 10. The active matrix substrate according to item 9, wherein each of the plurality of bump portions is arranged so as to at least partially overlap each of the plurality of thin film transistors in a plan view.

[0024] [Item 11] further comprising a plurality of pixel contact portions, each of which electrically connects one pixel electrode of the plurality of pixel electrodes to a corresponding thin film transistor of the plurality of thin film transistors; Each of the plurality of thin film transistors further includes a gate electrode, a source electrode, and a drain electrode; Item 11. The active matrix substrate according to item 9 or 10, wherein each of the plurality of pixel contact portions includes a connection electrode that electrically connects the one pixel electrode and the drain electrode of the one thin film transistor, the connection electrode being formed from the same conductive film as the plurality of touch wirings.

[0025] [Item 12] 12. The active matrix substrate according to any one of items 9 to 11, wherein the protruding height of the plurality of bumps on the organic insulating layer is 0.5 μm or more.

[0026] [Item 13] 13. The active matrix substrate according to any one of items 9 to 12, wherein each of the plurality of thin film transistors has a bottom gate structure.

[0027] [Item 14] 14. The active matrix substrate according to any one of items 9 to 13, wherein the oxide semiconductor layer includes an In—Ga—Zn—O-based semiconductor.

[0028] [Item 15] An active matrix substrate according to any one of items 9 to 14, an opposing substrate disposed opposite the active matrix substrate; a liquid crystal layer provided between the active matrix substrate and the counter substrate; A liquid crystal display device comprising:

[0029] [Item 16] the opposing substrate has a plurality of columnar spacers that define the thickness of the liquid crystal layer; Item 16. The liquid crystal display device according to item 15, wherein the plurality of bump portions of the organic insulating layer include two or more bump portions arranged so as to overlap the plurality of columnar spacers in a plan view. [Effects of the Invention]

[0030] According to an embodiment of the present invention, there is provided an active matrix substrate suitable for use in a liquid crystal display panel for an in-cell touch panel, and a method for manufacturing the same. [Brief explanation of the drawings]

[0031] [Figure 1] FIG. 1 is a diagram schematically illustrating the general structure of an active matrix substrate 101 according to an embodiment of the present invention. [Figure 2]1 is a plan view illustrating an example of the arrangement relationship between touch sensor electrodes TX and touch wirings TL on an active matrix substrate 101. FIG. [Figure 3] 1 is a cross-sectional view schematically showing an active matrix substrate 101, showing a cross section including a TFT 30, a pixel contact portion PC, and a touch wiring contact portion TC. [Figure 4] FIG. 1 is a cross-sectional view schematically showing an active matrix substrate 101, and shows imaginary columnar spacers SP. [Figure 5] 1 is a cross-sectional view that schematically shows an in-cell touch panel (liquid crystal display device) 1000 that uses an active matrix substrate 101. FIG. [Figure 6A] 1A to 1C are cross-sectional views showing steps in an example of a method for manufacturing the active matrix substrate 101. [Figure 6B] 1A to 1C are cross-sectional views showing steps in an example of a method for manufacturing the active matrix substrate 101. [Figure 6C] 1A to 1C are cross-sectional views showing steps in an example of a method for manufacturing the active matrix substrate 101. [Figure 6D] 1A to 1C are cross-sectional views showing steps in an example of a method for manufacturing the active matrix substrate 101. [Figure 6E] 1A to 1C are cross-sectional views showing steps in an example of a method for manufacturing the active matrix substrate 101. [Figure 6F] 1A to 1C are cross-sectional views showing steps in an example of a method for manufacturing the active matrix substrate 101. [Figure 6G] 1A to 1C are cross-sectional views showing steps in an example of a method for manufacturing the active matrix substrate 101. [Figure 6H] 1A to 1C are cross-sectional views showing steps in an example of a method for manufacturing the active matrix substrate 101. [Figure 6I] 1A to 1C are cross-sectional views showing steps in an example of a method for manufacturing the active matrix substrate 101. [Figure 6J] 1A to 1C are cross-sectional views showing steps in an example of a method for manufacturing the active matrix substrate 101. [Figure 7] 10 is a table showing an example of a method for manufacturing the active matrix substrate 101. [Figure 8] FIG. 9 is a cross-sectional view schematically showing an active matrix substrate 901 of a comparative example, showing a cross section including a TFT 30, a pixel contact portion PC, and a touch wiring contact portion TC. [Figure 9] 9 is a cross-sectional view showing a schematic view of an active matrix substrate 901, in which columnar spacers SP are shown imaginarily. [Figure 10A] 9A to 9C are cross-sectional views showing the steps of a method for manufacturing an active matrix substrate 901. [Figure 10B] 9A to 9C are cross-sectional views showing the steps of a method for manufacturing an active matrix substrate 901. [Figure 10C] 9A to 9C are cross-sectional views showing the steps of a method for manufacturing an active matrix substrate 901. [Figure 10D] 9A to 9C are cross-sectional views showing the steps of a method for manufacturing an active matrix substrate 901. [Figure 10E] 9A to 9C are cross-sectional views showing the steps of a method for manufacturing an active matrix substrate 901. [Figure 10F] 9A to 9C are cross-sectional views showing the steps of a method for manufacturing an active matrix substrate 901. [Figure 10G] 9A to 9C are cross-sectional views showing the steps of a method for manufacturing an active matrix substrate 901. [Figure 11] 9 is a table showing a manufacturing method of the active matrix substrate 901. DETAILED DESCRIPTION OF THE INVENTION

[0032] Hereinafter, embodiments of the present invention will be described with reference to the drawings, but the present invention is not limited to the following embodiments.

[0033] [Schematic structure of active matrix substrate] First, with reference to FIGS. 1 and 2, a schematic structure of an active matrix substrate 101 according to an embodiment of the present invention will be described. The active matrix substrate 101 can be used in an in-cell touch panel using an FFS mode liquid crystal display panel. The touch sensor built into the touch panel can be, for example, of a mutual capacitance type or a self-capacitance type. FIG. 1 is a diagram schematically showing the schematic structure of the active matrix substrate 101. FIG. 2 is a plan view illustrating an example of the arrangement relationship between touch sensor electrodes TX and touch wiring TL in the active matrix substrate 101.

[0034] 2, the active matrix substrate 101 has a display area DR and a non-display area FR located around the display area DR. The non-display area FR is also called a "peripheral area" or a "frame area."

[0035] As shown in Fig. 1, the display region DR includes a plurality of gate bus lines (scanning wiring) GL extending in the row direction, a plurality of source bus lines (signal wiring) SL extending in the column direction, and a plurality of pixel regions PIX arranged in a matrix. Here, the column direction is a direction that intersects with the row direction and may be perpendicular to the row direction. The pixel regions PIX are regions corresponding to each pixel of the liquid crystal display device. In the example shown in Fig. 1, each pixel region PIX is defined by two adjacent gate bus lines GL and two adjacent source bus lines SL.

[0036] Each pixel region PIX is provided with a TFT (pixel TFT) 30 and a pixel electrode PE. The gate electrode of the TFT 30 is electrically connected to the corresponding gate bus line GL, and the source electrode of the TFT 30 is electrically connected to the corresponding source bus line SL. The drain electrode of the TFT 30 is electrically connected to the corresponding pixel electrode PE at a pixel contact portion PC described later.

[0037] The active matrix substrate 101 is also provided with a common electrode CE. The common electrode CE is divided into a plurality of segments TX. Each segment TX functions as a touch sensor electrode. In the example shown in FIG. 1, each touch sensor electrode TX is provided corresponding to two or more pixel regions PIX.

[0038] 2, the active matrix substrate 101 has a plurality of touch wirings TL. Each touch wiring TL is electrically connected to a corresponding touch sensor electrode TX. Hereinafter, a connection portion TC between the touch wiring TL and the touch sensor electrode TX is referred to as a "touch wiring contact portion."

[0039] The touch wiring TL is connected to a touch drive unit TD provided in the non-display region FR. The touch drive unit TD is configured to switch, for example, between a display mode in which a plurality of touch sensor electrodes TX function as common electrodes CE and a touch detection mode in which they function as touch sensor electrodes TX in a time-division manner. For example, in the display mode, the touch drive unit TD applies a common signal to the touch sensor electrodes TX (common electrodes CE) via the touch wiring TL. On the other hand, in the touch detection mode, the touch drive unit TD applies a touch drive signal to the touch sensor electrodes TX via the touch wiring TL.

[0040] 2, the touch wirings TL extend in the column direction (the direction in which the source bus lines SL extend). Some of the touch wirings TL extend to the corresponding touch sensor electrodes TX, crossing one or more other touch sensor electrodes TX.

[0041] Although not shown, in addition to the touch drive unit TD, the non-display region FR of the active matrix substrate 101 is provided with drive circuits such as a gate driver that supplies scanning signals to the TFTs 30 via gate bus lines GL and a source driver that supplies display signals to the TFTs 30 via source bus lines SL. These drive circuits may be mounted on the active matrix substrate 101 or may be formed integrally (monolithically). A semiconductor chip including some or all of the drive circuits may be mounted on the non-display region FR.

[0042] In the above description, an example has been shown in which the touch panel includes a self-capacitance touch sensor. However, a mutual capacitance touch sensor may be included instead. In this case, another electrode for the touch sensor may be provided on a counter substrate disposed opposite the active matrix substrate 101 with a liquid crystal layer sandwiched therebetween. For example, the touch sensor electrode TX may extend in one direction (e.g., the row direction), and an electrode for the touch sensor provided on the counter substrate may extend in another direction (e.g., the column direction), and a change in capacitance at an intersection of these electrodes (touch detection unit) may be detected. Specific structures and driving methods of mutual capacitance and self-capacitance touch sensors are described in, for example, JP 2018-5484 A, International Application No. 2018 / 092758, International Application No. 2017 / 126603, JP 2016-126336 A, JP 2009-244958 A, and the like, and are publicly known, so detailed description thereof will be omitted. For reference, the entire disclosures of JP 2018-5484 A, International Application No. 2018 / 092758, International Application No. 2017 / 126603, JP 2016-126336 A, and JP 2009-244958 A are incorporated herein by reference.

[0043] In this specification, regardless of the touch sensor type, the electrode for the touch sensor arranged on the active matrix substrate 101 side is simply called the "touch sensor electrode TX," and the wiring for the touch sensor electrically connected to the touch sensor electrode TX is called the "touch wiring."

[0044] [Structure of the pixel area on the active matrix substrate] Next, the structure of the pixel region PIX of the active matrix substrate 101 will be described with reference to Fig. 3. Fig. 3 is a cross-sectional view schematically showing the active matrix substrate 101, illustrating a cross section including the TFT 30, the pixel contact portion PC, and the touch wiring contact portion TC.

[0045] In this specification, the layer M1 including electrodes and wiring formed using the same conductive film (first conductive film) as the gate bus lines GL is referred to as the "first metal layer," and the layer M2 including electrodes and wiring formed using the same conductive film (second conductive film) as the source bus lines SL is referred to as the "second metal layer." The layer M3 including electrodes and wiring formed using the same conductive film (third conductive film) as the touch lines TL is referred to as the "third metal layer." Furthermore, the layer T1 including electrodes and wiring formed using the same conductive film (first transparent conductive film) as the common electrode CE is referred to as the "first transparent conductive layer," and the layer T2 including electrodes and wiring formed using the same conductive film (second transparent conductive film) as the pixel electrodes PE is referred to as the "second transparent conductive layer." In the drawings, a symbol indicating a metal layer or transparent conductive layer may be added in parentheses after the reference symbol of each component. For example, the reference symbol of an electrode or wiring formed in the first metal layer M1 may be followed by "(M1)."

[0046] As shown in Figure 3, the active matrix substrate 101 comprises a substrate 1, a plurality of TFTs 30 supported on the substrate 1, an interlayer insulating layer 13 covering the TFTs 30, a plurality of pixel electrodes PE arranged above the interlayer insulating layer 13, and a common electrode CE arranged between the pixel electrodes PE and the interlayer insulating layer 13.

[0047] Each of the plurality of TFTs 30 is disposed corresponding to each of the plurality of pixel regions PIX. A part of the TFT 30 may be located outside the corresponding pixel region PIX.

[0048] Each TFT 30 includes a gate electrode GE, an oxide semiconductor layer 7, a gate insulating layer 5 disposed between the oxide semiconductor layer 7 and the gate electrode GE, and a source electrode SE and a drain electrode DE electrically connected to the oxide semiconductor layer 7.

[0049] In the illustrated example, the TFT 30 has a bottom-gate structure, and the gate electrode GE is disposed between the oxide semiconductor layer 7 and the substrate 1. The gate electrode GE overlaps at least a portion of the oxide semiconductor layer 7 via the gate insulating layer 5. The gate insulating layer 5 covers the gate electrode GE.

[0050] The oxide semiconductor layer 7 is disposed on the gate insulating layer 5 so as to overlap the gate electrode GE via the gate insulating layer 5. The oxide semiconductor layer 7 includes a source contact region 7s, a drain contact region 7d, and a channel region 7c.

[0051] The source contact region 7s is electrically connected to the source electrode SE, and the drain contact region 7d is electrically connected to the drain electrode DE. The source electrode SE may be in direct contact with the source contact region 7s, and the drain electrode DE may be in direct contact with the drain contact region 7d. The channel region 7c is located between the source contact region 7s and the drain contact region 7d and overlaps with the gate electrode GE.

[0052] The gate electrode GE is electrically connected to the corresponding gate bus line GL, the source electrode SE is electrically connected to the corresponding source bus line SL, and the drain electrode DE is electrically connected to the corresponding pixel electrode PE at the pixel contact portion PC.

[0053] The gate electrode GE may be formed in the same layer (first metal layer M1) as the gate bus line GL. The gate electrode GE may be part of the corresponding gate bus line GL. The source electrode SE and drain electrode DE may be formed in the same layer (second metal layer M2) as the source bus line SL. The source electrode SE may be part of the corresponding source bus line SL.

[0054] The TFT 30 is covered with an interlayer insulating layer 13. The interlayer insulating layer 13 includes an organic insulating layer 12. The organic insulating layer 12 has a thickness (e.g., 1 μm or more) that allows it to function as a planarizing film. In the example shown, the interlayer insulating layer 13 has a layered structure including an inorganic insulating layer (passivation film) 11 and an organic insulating layer 12 disposed on the inorganic insulating layer 11.

[0055] A plurality of touch wirings TL are provided on the interlayer insulating layer 13. In the example shown, each touch wiring TL is arranged so as to overlap one of the plurality of source bus lines SL via the interlayer insulating layer 13, and extends over and along the source bus line SL (i.e., in the column direction) in plan view.

[0056] A first dielectric layer 17 is disposed on the interlayer insulating layer 13 so as to cover the third metal layer M3 including the touch wiring TL. A common electrode CE is provided on the first dielectric layer 17. Therefore, it can be said that the first dielectric layer 17 is disposed between the interlayer insulating layer 13 and the common electrode CE. It can also be said that the touch wiring TL is disposed between the interlayer insulating layer 13 and the common electrode CE.

[0057] The common electrode CE is divided into a plurality of segments that can function as a plurality of touch sensor electrodes TX. Each touch sensor electrode TX is typically associated with two or more pixel regions PIX (i.e., has a size corresponding to two or more pixel regions PIX).

[0058] Each touch sensor electrode TX is connected to a corresponding touch wiring TL at a touch wiring contact portion TC within an opening 17p formed in the first dielectric layer 17. At least one touch wiring contact portion TC needs to be provided for one touch sensor electrode TX, and two or more touch wiring contact portions TC may be provided.

[0059] The common electrode CE (touch sensor electrode TX) is covered with a second dielectric layer 18. The pixel electrode PE is provided on the second dielectric layer 18. Therefore, it can be said that the second dielectric layer 18 is disposed between the common electrode CE and the pixel electrode PE.

[0060] At least one slit s is formed in the pixel electrode PE. The pixel electrode PE is arranged to partially overlap the common electrode CE with a second dielectric layer 18 interposed therebetween (the overlapping area between the two is not shown in FIG. 3). The pixel electrode PE is electrically connected to the TFT 30 at a pixel contact portion PC.

[0061] [Pixel contact section] The active matrix substrate 101 includes a plurality of pixel contact portions PC, each electrically connecting one of the plurality of pixel electrodes PE to a corresponding one of the plurality of TFTs 30. In the example shown, in each pixel contact portion PC, the pixel electrode PE is electrically connected to the drain electrode DE of the TFT 30 by a connection electrode TE formed using the same third conductive film as the touch wiring TL (i.e., in the third metal layer M3).

[0062] 3, the pixel contact portion PC includes a part of the drain electrode DE of the TFT 30, a part of the pixel electrode PE, and a connection electrode TE. A lower opening p1 exposing a part of the drain electrode DE is formed in the interlayer insulating layer 13, and the connection electrode TE is electrically connected to the drain electrode DE within the lower opening p1. In the illustrated example, the connection electrode TE is in direct contact with the exposed part of the drain electrode DE within the lower opening p1.

[0063] An upper opening p2 exposing a portion of the connection electrode TE is formed in the first dielectric layer 17 and the second dielectric layer 18, and the pixel electrode PE is electrically connected to the connection electrode TE within the upper opening p2. In the illustrated example, the pixel electrode PE is in direct contact with the exposed portion of the connection electrode TE within the upper opening p2.

[0064] In the illustrated example, the third metal layer M3 including the touch wiring TL is disposed closer to the substrate 1 than the common electrode CE. Therefore, the pixel contact portion PC can be formed using the third metal layer M3. Specifically, when forming the pixel contact portion PC, the first transparent conductive film is patterned with the drain electrode DE covered with the connection electrode TE, to form the common electrode CE. Therefore, in the process of patterning the first transparent conductive film to form the common electrode CE, damage to the drain electrode DE caused by contact of an etching solution (e.g., oxalic acid) with the drain electrode DE can be suppressed.

[0065] In the illustrated example, the connection electrode TE includes a first portion t1 in contact with a portion of the upper surface of the interlayer insulating layer 13, a second portion t2 in contact with the side surface of the lower opening p1, and a third portion t3 in contact with the exposed portion of the drain electrode DE. This more effectively protects the exposed portion of the drain electrode DE exposed by the lower opening p1. In particular, when the interlayer insulating layer 13 includes the organic insulating layer 12, the connection electrode TE preferably covers not only the exposed portion of the drain electrode DE but also the side surface of the organic insulating layer 12. This more effectively prevents the etching solution from seeping into the drain electrode DE. It also effectively prevents corrosion of the drain electrode DE due to moisture contained in the organic insulating layer 12. The side surface of the lower opening p1 includes the side surface of the inorganic insulating layer 11 and the side surface of the organic insulating layer 12. As illustrated, the second portion t2 of the connection electrode TE may cover the entire side surface of the lower opening p1. In this case, the first dielectric layer 17 does not need to contact the side surface of the lower opening p1.

[0066] [Structure of organic insulating layer] The structure of the organic insulating layer 12 will be described with reference to Fig. 4. Like Fig. 3, Fig. 4 is a cross-sectional view schematically showing the active matrix substrate 101, but it also shows imaginary columnar spacers SP that are provided on the opposing substrate side in a liquid crystal display device and define the thickness of the liquid crystal layer. Also shown is an alignment film (first alignment film) AF1 located on the outermost surface of the active matrix substrate 101.

[0067] The organic insulating layer 12 has a plurality of openings 12p. Each of the openings 12p is located in the pixel contact portion PC of each pixel region PIX, and is part of the lower opening p1 of the interlayer insulating layer 11.

[0068] The organic insulating layer 12 further has a plurality of bumps (protrusions) 12b that protrude upward. The outermost surface of the active matrix substrate 101 has protrusions pr that correspond to the bumps 12b (reflecting the protrusions of the bumps 12b).

[0069] In the illustrated example, each of the plurality of bump portions 12b is arranged so as to at least partially overlap, in plan view, each of the plurality of TFTs 30. The plurality of bump portions 12b also includes two or more bump portions 12b arranged so as to overlap, in plan view, with a plurality of columnar spacers SP provided on the opposing substrate side. While Fig. 4 shows the bump portions 12b overlapping the columnar spacers SP, some of the bump portions 12b may not overlap the columnar spacers SP.

[0070] The organic insulating layer 12 can be formed from, for example, a photosensitive resin material. As will be described later, by using a multi-tone photomask in the process of forming the organic insulating layer 12, the organic insulating layer 12 having the bump portion 12b in addition to the opening portion 12p can be easily formed (with the same number of steps as when forming an organic insulating layer without the bump portion).

[0071] As described above, in the active matrix substrate 101 according to the embodiment of the present invention, the organic insulating layer 12 has a plurality of bump portions 12b, and therefore protrusions pr corresponding to the bump portions 12b are formed on the outermost surface of the active matrix substrate 101. The protrusions pr can function as structures (pedestals) that support the columnar spacers SP, so that in a liquid crystal display panel using the active matrix substrate 101, a sufficient cell gap is ensured even when the panel is pressed by a finger or the like. Therefore, the active matrix substrate 101 is suitable for use in a liquid crystal display panel for an in-cell touch panel.

[0072] There is no particular restriction on the protruding height h of the bump portion 12b, but from the viewpoint of ensuring a sufficient cell gap when the liquid crystal display panel is pressed, the protruding height h of the bump portion 12b is preferably 0.5 μm or more.

[0073] The shape of the bump portion 12b in plan view is not particularly limited, and may be various shapes such as a substantially circular shape, a substantially elliptical shape, a substantially rectangular shape, a substantially regular polygonal shape, etc. The size of the bump portion 12 in plan view is also not particularly limited, but the circle-equivalent diameter of the bump portion 12b in plan view is, for example, 10 μm or more and 40 μm or less.

[0074] [Touch panel configuration] The active matrix substrate 101 according to the embodiment of the present invention is suitable for use in an in-cell touch panel.

[0075] 5 is a cross-sectional view that schematically shows a touch panel (liquid crystal display device) 1000 that uses an active matrix substrate 101. As shown in FIG. 5, the touch panel 1000 includes the active matrix substrate 101, a counter substrate 201 that is arranged to face the active matrix substrate 101, and a liquid crystal layer LC that is provided between the active matrix substrate 101 and the counter substrate 201.

[0076] The counter substrate 201 has a substrate 211, a color filter layer 212 supported by the substrate 211, and a plurality of columnar spacers SP provided on the color filter layer 212. A second alignment film AF2 is provided on the outermost surface of the counter substrate 201 on the liquid crystal layer LC side.

[0077] The color filter layer 212 includes, for example, a red color filter, a green color filter, and a blue color filter, and typically further includes a black matrix (light-shielding layer).

[0078] In the illustrated example, the plurality of columnar spacers SP include a first spacer SP1 and a second spacer SP2 that is lower than the first spacer SP1. The first spacer SP1 may be referred to as a “main spacer,” and the second spacer SP2 may be referred to as a “sub-spacer.”

[0079] As already explained, the protrusions pr located on the top surface of the active matrix substrate 101 function as structures (bases) that support the columnar spacers SP, thereby ensuring a sufficient cell gap even when the panel surface is pressed.

[0080] [Method of manufacturing active matrix substrate] A method for manufacturing active matrix substrate 101 will be described with reference to Figures 6A to 6J and 7. Figures 6A to 6J are cross-sectional views showing steps in an example of a method for manufacturing active matrix substrate 101. Figure 7 is a table showing an example of a method for manufacturing active matrix substrate 101.

[0081] Formation of the first metal layer M1 (Figure 6A) As shown in FIG. 6A, a first metal layer M1 is formed on a substrate 1. First, a first conductive film (thickness: for example, 50 nm to 500 nm) is deposited on the substrate 1 by, for example, sputtering. Next, a resist mask is formed by a known photolithography process, and the first conductive film is patterned (for example, by wet etching). Thereafter, the resist mask is peeled off. In this way, a first metal layer M1 including a gate bus line GL and a gate electrode GE is formed.

[0082] As the substrate 1, a transparent and insulating substrate such as a glass substrate, a silicon substrate, or a heat-resistant plastic substrate (resin substrate) can be used.

[0083] The material of the first conductive film is not particularly limited, and metals such as aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), copper (Cu), alloys containing these metals, or nitrides of these metals can be used as appropriate. The first conductive film may be a single layer or may have a multilayer structure.

[0084] Formation of gate insulating layer 5 and oxide semiconductor layer 7 (FIG. 6B) As shown in FIG. 6B, a gate insulating layer 5 (thickness: for example, 200 nm to 600 nm) is formed to cover the first metal layer M1, and then an oxide semiconductor layer 7 is formed on the gate insulating layer 5.

[0085] The gate insulating layer 5 is formed by, for example, a CVD method. Examples of materials that can be used for the gate insulating layer 5 include silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON; x>y), and silicon nitride oxide (SiNO; x>y). The gate insulating layer 5 may be a single layer or may have a multilayer structure. For example, a silicon nitride layer or a silicon nitride oxide layer may be formed on the substrate 1 side (lower layer) to prevent the diffusion of impurities from the substrate 1, and a silicon oxide layer or a silicon oxynitride layer may be formed on top of that (upper layer) to ensure insulation. Here, the gate insulating layer 5 is formed as a multilayer film having a silicon nitride layer (thickness: for example, 50 nm to 600 nm) as the lower layer and a silicon oxide layer (thickness: for example, 50 nm to 600 nm) as the upper layer. When an oxide layer such as a silicon oxide layer is used as the gate insulating layer 5 (or as the uppermost layer when the gate insulating layer 5 has a stacked structure), the oxide layer can reduce oxidation defects that occur in the channel region of the oxide semiconductor layer to be formed later, thereby preventing the resistance of the channel region from decreasing.

[0086] The oxide semiconductor layer 7 can be formed, for example, as follows. First, an oxide semiconductor film is deposited on the gate insulating layer 5 by, for example, sputtering. The oxide semiconductor film may then be annealed. The thickness of the oxide semiconductor film is, for example, 15 nm to 200 nm. Here, an In-Ga-Zn-O-based semiconductor film (thickness: 50 nm) containing In, Ga, and Zn is deposited as the oxide semiconductor film. Next, a resist mask is formed by a known photolithography process, and the oxide semiconductor film is patterned (for example, by wet etching). The resist mask is then peeled off. This forms the oxide semiconductor layer 7, which will be the active layer of the TFT 30, in each pixel region PIX.

[0087] Formation of an opening in the gate insulating layer 5 A resist mask is formed by a known photolithography process, and the gate insulating layer 5 is patterned (e.g., dry etching). The resist mask is then peeled off, thereby forming openings at predetermined positions in the gate insulating layer 5. The openings formed here are used, for example, to electrically connect wiring formed in the first metal layer M1 and wiring formed in the second metal layer M2.

[0088] Formation of the second metal layer M2 (Figure 6C) As shown in FIG. 6C, the second metal layer M2 is formed. First, a second conductive film (thickness: for example, 50 nm to 500 nm) is deposited on the oxide semiconductor layer 7 by, for example, sputtering. Next, a resist mask is formed by a known photolithography process, and the second conductive film is patterned (for example, by dry etching). Thereafter, the resist mask is peeled off. In this way, the second metal layer M2 including the source bus line SL, the source electrode SE, and the drain electrode DE is formed.

[0089] The material of the second conductive film is not particularly limited, and metals such as aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), copper (Cu), alloys containing these metals, or nitrides of these metals can be used as appropriate. The second conductive film may be a single layer or may have a multilayer structure.

[0090] By performing the steps from the step of forming the first metal layer M1 (FIG. 6A) to the step of forming the second metal layer M2 (FIG. 6C), a plurality of TFTs 30 can be formed on the substrate 1.

[0091] Formation of inorganic insulating layer 11 (FIG. 6D) 6D, an inorganic insulating layer 11 (thickness: for example, 0.1 μm or more and 1 μm or less) covering the TFT 30 is formed by, for example, a CVD method. Materials that can be used for the inorganic insulating layer 11 include silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, and tantalum oxide. The inorganic insulating layer 11 may be a single layer or may have a multilayer structure.

[0092] Formation of organic insulating layer 12 (FIG. 6E) As shown in FIG. 6E, an organic insulating layer 12 (thickness: e.g., 2 μm to 4 μm) having multiple openings 12p and multiple bumps 12b is formed on an inorganic insulating layer 11. The organic insulating layer 12 can be formed, for example, by first applying a positive photosensitive resin material (e.g., an acrylic resin material) to the inorganic insulating layer 11, then performing a photolithography process (exposure and development) using a multi-tone photomask, and then baking. FIG. 6E illustrates a half-tone mask 40 as an example of the multi-tone photomask. The half-tone mask 40 has a transmissive region 41 that transmits light, a light-shielding region 42 that substantially does not transmit light, and a semi-transmissive region 43 made of a semi-transmissive film that transmits light with a lower transmittance than the transmissive region 41. Openings 12p are formed corresponding to the transmissive region 41, and bumps 12b are formed corresponding to the light-shielding region 42. In this way, by using a multi-tone photomask such as halftone mask 40, an organic insulating layer 12 having multiple openings 12p and multiple bump portions 12b (i.e., having three different heights) can be easily formed.

[0093] The multi-tone photomask is not limited to the half-tone mask 40. A gray-tone mask may also be used as the multi-tone photomask. The gray-tone mask has a transmissive region that transmits light, a light-shielding region that substantially blocks light, and a semi-transmissive region in which slits equal to or smaller than the resolution of the exposure machine are formed and which transmits light with a lower transmittance than the transmissive region. Even when a gray-tone mask is used, the organic insulating layer 12 having a plurality of openings 12p and a plurality of bump portions 12b can be formed.

[0094] Formation of openings 11p in the inorganic insulating layer 11 (FIG. 6F) 6F, an opening 11p is formed in the inorganic insulating layer 11 by, for example, dry etching using the organic insulating layer 12 as a mask. The opening 11p in the inorganic insulating layer 11 is formed so as to be continuous with the opening 12p in the organic insulating layer 12, so that the interlayer insulating layer 13 has a lower opening p1 that includes the opening 11p in the inorganic insulating layer 11 and the opening 12p in the organic insulating layer 12.

[0095] By performing the steps from the step of forming inorganic insulating layer 11 (FIG. 6D) to the step of forming openings 11p in inorganic insulating layer 11 (FIG. 6F), interlayer insulating layer 13 that covers multiple TFTs 30 can be formed.

[0096] Formation of the third metal layer M3 (Fig. 6G) As shown in FIG. 6G, a third metal layer M3 is formed. First, a third conductive film (thickness: e.g., 50 nm to 500 nm) is deposited on the interlayer insulating layer 13 and in the lower opening p1 by, for example, sputtering. Next, a resist mask is formed by a known photolithography process, and the third conductive film is patterned (e.g., wet etching). Thereafter, the resist mask is peeled off. In this manner, a third metal layer M3 including a plurality of touch wirings TL and a plurality of connection electrodes TE is formed.

[0097] The materials for the third conductive film can be the same as those exemplified as the materials for the first conductive film and the second conductive film. The third conductive film can be a single layer or can have a laminated structure. The third conductive film can also be a laminated film including, for example, a transparent conductive film (thickness: for example, 10 nm to 50 nm) and a metal film (thickness: for example, 100 nm to 400 nm) disposed on the transparent conductive film. The materials for the transparent conductive film can be the same as those for the first transparent conductive film or the second transparent conductive film described below. The materials for the metal film can be the same as those exemplified as the materials for the first conductive film and the second conductive film.

[0098] Formation of the first dielectric layer 17 (FIG. 6H) As shown in FIG. 6H, a first dielectric layer 17 is formed to cover the third metal layer M3. First, a first dielectric film (thickness: for example, 100 nm or more and 500 nm or less) is deposited by, for example, a CVD method so as to cover the third metal layer M3. Next, a resist mask is formed by a known photolithography process, and the first dielectric film is patterned (for example, by dry etching). Thereafter, the resist mask is peeled off. In this manner, the first dielectric layer 17 covering the third metal layer M3 is formed. The first dielectric layer 17 has an opening 17p that exposes a portion of the touch wiring TL. When patterning the first dielectric film, the gate insulating layer 5 may also be patterned to form an opening that exposes a portion of the gate bus line GL.

[0099] The first dielectric film may be made of a suitable material such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, etc. The first dielectric film may be a single layer or may have a multilayer structure.

[0100] Formation of the first transparent conductive layer T1 (FIG. 6I) As shown in FIG. 6I, a first transparent conductive layer T1 including a common electrode CE is formed on the first dielectric layer 17. First, a first transparent conductive film (thickness: e.g., 20 nm to 300 nm) is deposited on the first dielectric layer 17 and in the opening 17p by, for example, sputtering. Next, a resist mask is formed by a known photolithography process, and the first transparent conductive film is patterned (e.g., wet etching). Thereafter, the resist mask is peeled off. In this manner, the first transparent conductive layer T1 including the common electrode CE is formed.

[0101] The first transparent conductive film can be made of a metal oxide such as indium tin oxide (ITO), indium zinc oxide, or ZnO.

[0102] Formation of the second dielectric layer 18 (FIG. 6J) As shown in FIG. 6J, a second dielectric layer 18 is formed to cover the first transparent conductive layer T1 including the common electrode CE. First, a second dielectric film (thickness: e.g., 80 nm to 250 nm) is deposited by, for example, CVD so as to cover the first transparent conductive layer T1. Next, a resist mask is formed by a known photolithography process, and the second dielectric film is patterned (e.g., dry etching). Thereafter, the resist mask is peeled off. In this way, the second dielectric layer 18 is formed to cover the first transparent conductive layer T1. When the second dielectric film is patterned, the first dielectric layer 17 is also patterned, and an upper opening p2 is formed that exposes a portion of the connection electrode TE.

[0103] The second dielectric film may be made of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, etc. The second dielectric film may be a single layer or may have a multilayer structure.

[0104] Formation of the second transparent conductive layer T2 (Figure 3) A second transparent conductive layer T2 including a plurality of pixel electrodes PE is formed on the second dielectric layer 18. First, a second transparent conductive film (thickness: e.g., 20 nm to 300 nm) is deposited on the second dielectric layer 18 and in the upper opening p2 by, for example, sputtering. Next, a resist mask is formed by a known photolithography process, and the second transparent conductive film is patterned (e.g., wet etching). Thereafter, the resist mask is peeled off. In this manner, the second transparent conductive layer T2 including a plurality of pixel electrodes PE is formed.

[0105] The second transparent conductive film may be made of a metal oxide such as indium tin oxide (ITO), indium zinc oxide, or ZnO.

[0106] In this way, the active matrix substrate 101 shown in FIG. 3 is obtained.

[0107] [Comparative active matrix substrate] An active matrix substrate 901 of the comparative example will be described with reference to Fig. 8. Fig. 8 is a cross-sectional view that schematically shows the active matrix substrate 901 of the comparative example.

[0108] The active matrix substrate 901 of the comparative example differs from the active matrix substrate 101 according to the embodiment of the present invention in that the organic insulating layer 12 of the interlayer insulating layer 13 does not have a bump portion. The active matrix substrate 901 of the comparative example also differs from the active matrix substrate 101 according to the embodiment of the present invention in that it has a plurality of bumps Bp formed on the second dielectric layer 18. The bumps Bp are formed from, for example, a negative resist material.

[0109] 9 is a cross-sectional view schematically illustrating an active matrix substrate 901 of the comparative example, similar to FIG. 8, but showing the columnar spacers SP in a virtual form, and also illustrating an alignment film AF1 located on the outermost surface of the active matrix substrate 901 of the comparative example.

[0110] The outermost surface of the active matrix substrate 901 of the comparative example has protrusions pr corresponding to the bumps Bp. The protrusions pr can function as structures (bases) that receive the columnar spacers SP, so that a sufficient cell gap is ensured even when the liquid crystal display panel using the active matrix substrate 901 of the comparative example is pressed by a finger or the like.

[0111] [Comparative Example: Manufacturing Method of Active Matrix Substrate] A method for manufacturing active matrix substrate 901 of the comparative example will be described with reference to Figures 10A to 10G and 11. Figures 10A to 10G are cross-sectional views showing the manufacturing process steps for manufacturing active matrix substrate 901 of the comparative example. Figure 11 is a table showing the manufacturing method for active matrix substrate 901 of the comparative example.

[0112] Formation of the first metal layer M1 to formation of the inorganic insulating layer 11 In the same manner as described with reference to Figures 6A to 6D for the active matrix substrate 101, a first metal layer M1, a gate insulating layer 5, an oxide semiconductor layer 7, a second metal layer M2, and an inorganic insulating layer 11 are formed in this order.

[0113] Formation of organic insulating layer 12 (FIG. 10A) 10A, an organic insulating layer 12 having a plurality of openings 12p is formed on an inorganic insulating layer 11. The organic insulating layer 12 can be formed, for example, by first applying a positive photosensitive resin material onto the inorganic insulating layer 11, then performing a photolithography process (exposure and development), and then baking.

[0114] Formation of openings 11p in the inorganic insulating layer 11 (FIG. 10B) 10B, an opening 11p is formed in the inorganic insulating layer 11 by, for example, dry etching using the organic insulating layer 12 as a mask. The opening 11p in the inorganic insulating layer 11 is formed so as to be continuous with the opening 12p in the organic insulating layer 12, so that the interlayer insulating layer 13 has a lower opening p1 that includes the opening 11p in the inorganic insulating layer 11 and the opening 12p in the organic insulating layer 12.

[0115] Formation of the third metal layer M3 (Figure 10C) As shown in FIG. 10C, a third metal layer M3 is formed. First, a third conductive film is deposited on the interlayer insulating layer 13 and in the lower opening p1, for example, by sputtering. Next, a resist mask is formed by a known photolithography process, and the third conductive film is patterned (for example, by wet etching). After that, the resist mask is peeled off. In this way, a third metal layer M3 including a plurality of touch wirings TL and a plurality of connection electrodes TE is formed.

[0116] Formation of the first dielectric layer 17 (FIG. 10D) As shown in FIG. 10D, a first dielectric layer 17 is formed to cover the third metal layer M3. First, a first dielectric film is deposited by, for example, a CVD method so as to cover the third metal layer M3. Next, a resist mask is formed by a known photolithography process, and the first dielectric film is patterned (for example, by dry etching). After that, the resist mask is peeled off. In this way, the first dielectric layer 17 is formed to cover the third metal layer M3. The first dielectric layer 17 has an opening 17p that exposes a part of the touch wiring TL.

[0117] Formation of the first transparent conductive layer T1 (FIG. 10E) As shown in FIG. 10E, a first transparent conductive layer T1 including a common electrode CE is formed on the first dielectric layer 17. First, a first transparent conductive film is deposited on the first dielectric layer 17 and in the opening 17p by, for example, sputtering. Next, a resist mask is formed by a known photolithography process, and the first transparent conductive film is patterned (for example, by wet etching). After that, the resist mask is peeled off. In this way, the first transparent conductive layer T1 including the common electrode CE is formed.

[0118] Formation of the second dielectric layer 18 (FIG. 10F) As shown in FIG. 10F, a second dielectric layer 18 is formed to cover the first transparent conductive layer T1 including the common electrode CE. First, a second dielectric film is deposited, for example, by CVD, so as to cover the first transparent conductive layer T1. Next, a resist mask is formed using a known photolithography process, and the second dielectric film is patterned (for example, by dry etching). The resist mask is then peeled off. In this manner, the second dielectric layer 18 is formed to cover the first transparent conductive layer T1. When patterning the second dielectric film, the first dielectric layer 17 is also patterned, and an upper opening p2 is formed that exposes a portion of the connection electrode TE.

[0119] Formation of the second transparent conductive layer T2 (FIG. 10G) A second transparent conductive layer T2 including a plurality of pixel electrodes PE is formed on the second dielectric layer 18. First, a second transparent conductive film is deposited on the second dielectric layer 18 and in the upper opening p2, for example, by sputtering. Next, a resist mask is formed by a known photolithography process, and the second transparent conductive film is patterned (for example, by wet etching). After that, the resist mask is peeled off. In this way, the second transparent conductive layer T2 including a plurality of pixel electrodes PE is formed.

[0120] Bump Bp formation (Figure 8) A plurality of bumps Bp are formed on the second dielectric layer 18. The bumps Bp can be formed, for example, by first applying a negative resist material onto the second dielectric layer 18, then performing a photolithography process (exposure and development), and then baking.

[0121] In this manner, the active matrix substrate 901 of the comparative example shown in FIG. 8 is obtained.

[0122] As already explained, even in a liquid crystal display panel using the active matrix substrate 901 of the comparative example, a sufficient cell gap can be ensured when pressed by a finger, etc. However, as can be seen from a comparison between Figures 7 and 11, by adopting a configuration in which the organic insulating layer 12 of the interlayer insulating layer 13 has a plurality of bump portions 12b, as in the active matrix substrate 101 according to the embodiment of the present invention, it is possible to reduce the number of processes.

[0123] [Oxide semiconductor] The oxide semiconductor (also referred to as a metal oxide or an oxide material) contained in the oxide semiconductor layer of the TFT may be an amorphous oxide semiconductor or a crystalline oxide semiconductor having a crystalline portion. Examples of the crystalline oxide semiconductor include a polycrystalline oxide semiconductor, a microcrystalline oxide semiconductor, and a crystalline oxide semiconductor whose c-axis is oriented substantially perpendicular to the layer surface.

[0124] The oxide semiconductor layer may have a stacked structure of two or more layers. When the oxide semiconductor layer has a stacked structure, the oxide semiconductor layer may include an amorphous oxide semiconductor layer and a crystalline oxide semiconductor layer. Alternatively, the oxide semiconductor layer may include multiple crystalline oxide semiconductor layers with different crystal structures. Furthermore, the oxide semiconductor layer may include multiple amorphous oxide semiconductor layers. When the oxide semiconductor layer has a two-layer structure including an upper layer and a lower layer, the energy gap of the oxide semiconductor included in the layer located on the gate electrode side (the lower layer in the case of a bottom-gate structure, or the upper layer in the case of a top-gate structure) may be smaller than the energy gap of the oxide semiconductor included in the layer located on the opposite side of the gate electrode (the upper layer in the case of a bottom-gate structure, or the lower layer in the case of a top-gate structure). However, when the difference in energy gap between these layers is relatively small, the energy gap of the oxide semiconductor included in the layer located on the gate electrode side may be larger than the energy gap of the oxide semiconductor included in the layer located on the opposite side of the gate electrode.

[0125] The materials, structures, film formation methods, and configurations of oxide semiconductor layers having a stacked structure of the amorphous oxide semiconductor and the above-mentioned crystalline oxide semiconductors are described in, for example, JP 2014-0073911 A. The entire disclosure of JP 2014-0073911 A is incorporated herein by reference.

[0126] The oxide semiconductor layer may contain at least one metal element selected from the group consisting of In, Ga, and Zn. In this embodiment, the oxide semiconductor layer contains, for example, an In—Ga—Zn—O-based semiconductor (e.g., indium gallium zinc oxide). Here, the In—Ga—Zn—O-based semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and the ratio (composition ratio) of In, Ga, and Zn is not particularly limited, and includes, for example, In:Ga:Zn=2:2:1, In:Ga:Zn=1:1:1, In:Ga:Zn=1:1:2, etc. Such an oxide semiconductor layer can be formed from an oxide semiconductor film containing an In—Ga—Zn—O-based semiconductor.

[0127] The In-Ga-Zn-O based semiconductor may be amorphous or crystalline, and a crystalline In-Ga-Zn-O based semiconductor in which the c-axis is oriented approximately perpendicular to the layer plane is preferred as the crystalline In-Ga-Zn-O based semiconductor.

[0128] The crystal structure of crystalline In-Ga-Zn-O-based semiconductors is disclosed, for example, in the aforementioned Japanese Patent Application Laid-Open Nos. 2014-0073911, 2012-134475, and 2014-2090627. For reference, the entire disclosures of Japanese Patent Application Laid-Open Nos. 2012-134475 and 2014-2090627 are incorporated herein by reference. TFTs having an In-Ga-Zn-O-based semiconductor layer have high mobility (more than 20 times that of an a-Si TFT) and low leakage current (less than one-hundredth that of an a-Si TFT). Therefore, they are suitable for use as driver TFTs (e.g., TFTs included in a driver circuit provided on the same substrate as a display area, around a display area including multiple pixels) and pixel TFTs (TFTs provided in pixels).

[0129] The oxide semiconductor layer may contain other oxide semiconductors instead of In-Ga-Zn-O-based semiconductors. For example, it may contain In-Sn-Zn-O-based semiconductors (e.g., In2O3-SnO2-ZnO; InSnZnO). In-Sn-Zn-O-based semiconductors are ternary oxides of In (indium), Sn (tin), and Zn (zinc). Alternatively, the oxide semiconductor layer may include an In-Al-Zn-O based semiconductor, an In-Al-Sn-Zn-O based semiconductor, a Zn-O based semiconductor, an In-Zn-O based semiconductor, a Zn-Ti-O based semiconductor, a Cd-Ge-O based semiconductor, a Cd-Pb-O based semiconductor, CdO (cadmium oxide), an Mg-Zn-O based semiconductor, an In-Ga-Sn-O based semiconductor, an In-Ga-O based semiconductor, a Zr-In-Zn-O based semiconductor, an Hf-In-Zn-O based semiconductor, an Al-Ga-Zn-O based semiconductor, a Ga-Zn-O based semiconductor, an In-Ga-Zn-Sn-O based semiconductor, an In-W-Zn-O based semiconductor, or the like. [Industrial Applicability]

[0130] According to an embodiment of the present invention, there is provided an active matrix substrate suitable for use in a liquid crystal display panel for an in-cell touch panel, and a method for manufacturing the same. [Explanation of symbols]

[0131] 1 board 5 Gate insulating layer 7. Oxide semiconductor layer 7c Channel region 7s Source Contact Area 7d Drain contact area 11 Inorganic insulating layer 11p Opening in inorganic insulating layer 12 Organic insulating layer 12p Opening in organic insulating layer 12b Bump part of organic insulating layer 13 Interlayer insulating layer 17 First dielectric layer 17p Opening in the first dielectric layer 18 Second dielectric layer 101 Active matrix substrate 201 Opposing substrate 1000 Touch panel (liquid crystal display device) AF1 First alignment film AF2 Second alignment film CE common electrode DE drain electrode DR display area FR hidden area GE gate electrode GL Gate Bus Line LC liquid crystal layer M1 First metal layer M2 Second metal layer M3 Third metal layer p1 Lower opening p2 Top opening pr convex part PC pixel contact part PE pixel electrode PIX Pixel area SE source electrode SL Source bus line SP column spacer T1 First transparent conductive layer T2 Second transparent conductive layer TC touch wiring contact part TE connection electrode TL Touch Wiring TX touch sensor electrode

Claims

1. A substrate; a plurality of thin film transistors supported by the substrate, each of the thin film transistors including an oxide semiconductor layer; an interlayer insulating layer covering the plurality of thin film transistors; a plurality of pixel electrodes disposed above the interlayer insulating layer; a common electrode disposed between the pixel electrodes and the interlayer insulating layer, the common electrode including a plurality of segments that can function as a plurality of touch sensor electrodes; a first dielectric layer disposed between the interlayer insulating layer and the common electrode; a second dielectric layer disposed between the common electrode and the plurality of pixel electrodes; a plurality of touch wirings arranged between the interlayer insulating layer and the common electrode, each of the plurality of touch wirings electrically connected to a corresponding one of the plurality of touch sensor electrodes; A method for manufacturing an active matrix substrate comprising: (A) forming the plurality of thin film transistors on the substrate; (B) forming an interlayer insulating layer covering the plurality of thin film transistors; (C) forming the plurality of touch wirings on the interlayer insulating layer; (D) forming the first dielectric layer covering the plurality of touch wirings; (E) forming the common electrode on the first dielectric layer; (F) forming the second dielectric layer covering the common electrode; (G) forming the plurality of pixel electrodes on the second dielectric layer; It encompasses the interlayer insulating layer includes an organic insulating layer, The step (B) (B1) A method for manufacturing an active matrix substrate, comprising the step of forming the organic insulating layer having a plurality of openings and a plurality of upwardly protruding bump portions using a multi-tone photomask.

2. 2. The method for manufacturing an active matrix substrate according to claim 1, wherein in the step (B1), the organic insulating layer is formed from a photosensitive resin material.

3. 3. The method for manufacturing an active matrix substrate according to claim 1, wherein the step (B1) is performed so that each of the plurality of bump portions at least partially overlaps each of the plurality of thin film transistors in a plan view.

4. Each of the plurality of thin film transistors further includes a gate electrode, a source electrode, and a drain electrode; the active matrix substrate further includes a plurality of pixel contact portions, each of which electrically connects one pixel electrode of the plurality of pixel electrodes to a corresponding thin film transistor of the plurality of thin film transistors; each of the plurality of pixel contact portions includes a connection electrode that electrically connects the one pixel electrode and the drain electrode of the one thin film transistor; The method for manufacturing an active matrix substrate according to claim 1 , wherein the connection electrodes are formed in the step (C) from the same conductive film as the plurality of touch wirings.

5. The method for manufacturing an active matrix substrate according to claim 1 , wherein each of the plurality of thin film transistors has a bottom gate structure.

6. 3. The method for manufacturing an active matrix substrate according to claim 1, wherein the oxide semiconductor layer includes an In--Ga--Zn--O based semiconductor.

7. an active matrix substrate; an opposing substrate disposed opposite the active matrix substrate; a liquid crystal layer provided between the active matrix substrate and the counter substrate; A method for manufacturing a liquid crystal display device comprising: (a) providing the active matrix substrate; (b) preparing the counter substrate; It encompasses 3. A method for manufacturing a liquid crystal display device, wherein the step (a) is carried out by the manufacturing method according to claim 1.

8. the opposing substrate has a plurality of columnar spacers that define the thickness of the liquid crystal layer; The method for manufacturing a liquid crystal display device according to claim 7 , wherein the plurality of bump portions of the organic insulating layer include two or more bump portions that are arranged so as to overlap the plurality of columnar spacers in a plan view.

9. A substrate; a plurality of thin film transistors supported by the substrate, each of the thin film transistors including an oxide semiconductor layer; an interlayer insulating layer covering the plurality of thin film transistors; a plurality of pixel electrodes disposed above the interlayer insulating layer; a common electrode disposed between the pixel electrodes and the interlayer insulating layer, the common electrode including a plurality of segments that can function as a plurality of touch sensor electrodes; a first dielectric layer disposed between the interlayer insulating layer and the common electrode; a second dielectric layer disposed between the common electrode and the plurality of pixel electrodes; a plurality of touch wirings arranged between the interlayer insulating layer and the common electrode, each of the plurality of touch wirings electrically connected to a corresponding one of the plurality of touch sensor electrodes; An active matrix substrate comprising: the interlayer insulating layer includes an organic insulating layer, The organic insulating layer has a plurality of openings and a plurality of bumps protruding upward.

10. 10. The active matrix substrate according to claim 9, wherein each of the plurality of bump portions is arranged so as to at least partially overlap each of the plurality of thin film transistors in a plan view.

11. a plurality of pixel contact portions each electrically connecting one pixel electrode of the plurality of pixel electrodes to a corresponding one thin film transistor of the plurality of thin film transistors; Each of the plurality of thin film transistors further includes a gate electrode, a source electrode, and a drain electrode; 11. The active matrix substrate according to claim 9, wherein each of the plurality of pixel contact portions includes a connection electrode that electrically connects the one pixel electrode and the drain electrode of the one thin film transistor, the connection electrode being formed from the same conductive film as the plurality of touch wirings.

12. 11. The active matrix substrate according to claim 9, wherein the plurality of bumps on the organic insulating layer have a protruding height of 0.5 [mu]m or more.

13. 11. The active matrix substrate according to claim 9, wherein each of the plurality of thin film transistors has a bottom gate structure.

14. 11. The active matrix substrate according to claim 9, wherein the oxide semiconductor layer includes an In--Ga--Zn--O based semiconductor.

15. an active matrix substrate according to claim 9 or 10; an opposing substrate disposed opposite the active matrix substrate; a liquid crystal layer provided between the active matrix substrate and the counter substrate; A liquid crystal display device comprising:

16. the opposing substrate has a plurality of columnar spacers that define the thickness of the liquid crystal layer; 16. The liquid crystal display device according to claim 15, wherein the plurality of bump portions of the organic insulating layer include two or more bump portions that are arranged so as to overlap the plurality of columnar spacers in a plan view.

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