Semiconductor device, control method for semiconductor device, and program

Abstract

To provide a semiconductor device capable of performing signal processing efficiently, a control method for the semiconductor device, and a program.SOLUTION: A semiconductor device 10 comprises a first signal processing unit 11, a second signal processing unit 12, and a control unit 20. The control unit 20 includes: a detection unit 21 which detects an amount of processing of second processing executed by either the first signal processing unit 11 or the second signal processing unit 12; a prediction unit 22 which predicts, on the basis of the detected amount of processing of the second processing, an amount of processing of next second processing to be executed; and a distribution unit 23 which distributes first processing to the first signal processing unit and the second signal processing unit according to the predicted amount of processing of the second processing.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, a control method for a semiconductor device, and a program. [Background technology]

[0002] For example, Non-Patent Document 1 is known as a technology related to signal processing of a radar device. Non-Patent Document 1 describes a method for processing a received signal based on a reflected wave received by an FMCW (Frequency Modulated Continuous Wave) radar. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] Marcio L. Lima de Oliveira, Marco JG Bekooij, “Deep Convolutional Autoencoder Applied for Noise Reduction in Range-Doppler Maps of FMCW Radars”, 2020 IEEE International Radar Conference (RADAR), 2020, p.630-635 Summary of the Invention [Problem to be solved by the invention]

[0004] Non-Patent Document 1 describes that a radar device performs signal processing such as FFT (Fast Fourier Transform) processing, CFAR (Constant False Alarm Rate) / peak detection processing, etc. It is desirable to perform such signal processing efficiently.

[0005] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] According to one embodiment, a semiconductor device includes a first signal processing unit, a second signal processing unit, and a control unit. The first signal processing unit and the second signal processing unit are capable of executing a first process and a second process that is executed based on a result of the first process. The control unit includes a detection unit, a prediction unit, and a distribution unit. The detection unit detects the processing amount of the second process executed by the first signal processing unit or the second signal processing unit. The prediction unit predicts the processing amount of the second process to be executed next based on the detected processing amount of the second process. The distribution unit distributes the first process to the first signal processing unit and the second signal processing unit according to the predicted processing amount of the second process. [Effects of the Invention]

[0007] According to the embodiment, signal processing can be performed efficiently. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a configuration diagram showing an example of the configuration of a related radar signal processing system. [Figure 2A] FIG. 10 is a diagram showing a specific example of a related allocation method. [Figure 2B] FIG. 10 is a diagram showing a specific example of a related allocation method. [Figure 3] 1 is a configuration diagram showing a schematic configuration of a semiconductor device according to an embodiment; [Figure 4A] 10A and 10B are diagrams illustrating a specific example of a method for allocating semiconductor devices according to an embodiment; [Figure 4B] 10A and 10B are diagrams illustrating a specific example of a method for allocating semiconductor devices according to an embodiment; [Figure 5] 1 is a configuration diagram showing an example of the hardware configuration of a semiconductor device according to a first embodiment. [Figure 6] 1 is a configuration diagram showing an example of the configuration of a functional block of a semiconductor device according to a first embodiment; [Figure 7]4 is a flowchart showing an example of the operation of the semiconductor device according to the first embodiment. [Figure 8] 4 is a graph showing an example of a weighting coefficient determination table according to the first embodiment. [Figure 9] 10 is a graph showing an example of the number of detected peak points for each frame according to the first embodiment. [Figure 10] 4 is a graph showing an example of a DSP allocation rate determination table according to the first embodiment. [Figure 11] FIG. 10 is a configuration diagram showing an example of the configuration of functional blocks of a semiconductor device according to a modification of the first embodiment. [Figure 12] 10 is a graph showing an example of a DSP processing time for each frame according to a modification of the first embodiment. [Figure 13] 10 is a graph showing an example of a DSP allocation rate determination table according to a modification of the first embodiment. [Figure 14] FIG. 10 is a configuration diagram showing an example of the configuration of a functional block of a semiconductor device according to a second embodiment. [Figure 15] FIG. 10 is a diagram showing a specific example of object disappearance according to the second embodiment. [Figure 16] 10 is a graph showing an example of the number of detected peak points for each frame according to the second embodiment. [Figure 17] FIG. 10 is a configuration diagram showing a configuration example of a functional block of a semiconductor device according to a third embodiment. [Figure 18] 11 is a graph showing an example of the number of detected peak points for each frame according to the third embodiment. [Figure 19] 11 is a graph showing an example of a DSP allocation rate determination table according to the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments will be described with reference to the drawings. Note that, for clarity of explanation, the following description and drawings have been omitted and simplified as appropriate. In addition, the same elements in each drawing are given the same reference numerals, and duplicate explanations are omitted as necessary.

[0010] (Review of related technologies) 1 shows an example of the configuration of a related radar signal processing system 90. The radar signal processing system 90 is a system that processes received signals based on reflected waves received by a radar device.

[0011] For example, the radar signal processing system 90 has a configuration similar to the functional blocks described in Non-Patent Document 1. As shown in Fig. 1, the radar signal processing system 90 includes an FFT processing unit 91, a CFAR / peak detection processing unit 92, an object detection processing unit 93, and a tracking processing unit 94.

[0012] The FFT processing unit 91 performs FFT processing on radar reception data (reception signals) received by the radar device. The radar device transmits transmission waves and receives reflected waves reflected by an object. The radar device performs AD (Analog-Digital) conversion on the received reflected wave signals to generate radar reception data. In the FFT processing, a Fourier transform is performed on the radar reception data in the range direction and Doppler direction to generate a range-Doppler (RD) map. In the RD map, the reception signal level is associated with a two-dimensional map of the distance (range) and relative velocity (Doppler velocity) between the radar device and the object.

[0013] The CFAR / peak detection processor 92 performs CFAR / peak detection processing on the RD map generated by FFT processing. In the CFAR / peak detection processing, CFAR processing is used to detect peaks (peak points) of signal levels in the RD map. CFAR processing is signal processing that suppresses reflected waves (noise) other than those of the target, making it easier to identify the target.

[0014] The peaks detected by the CFAR / peak detection process are represented as points on a plane. A collection of these points (point cloud) is estimated to be an object. The object detection processing unit 93 performs object detection processing on the point cloud based on the peaks (peak points) detected by the CFAR / peak detection process. In the object detection processing, the point cloud is grouped (clustered) to detect objects. By performing object detection, the position, movement direction, and movement speed of the object can be determined.

[0015] The tracking processing unit 94 performs tracking processing based on the object detected by the object detection processing. In the tracking processing, the movement of the detected object is tracked in a time series of frames. A frame is a unit of data detected for each measurement cycle (scan) of the radar device. For each frame, FFT processing, CFAR / peak detection processing, and object detection processing are performed, and tracking processing is performed on the object detection results for multiple frames.

[0016] The inventors have considered methods for implementing the processes shown in Fig. 1 in a semiconductor device. Because the load of each process in Fig. 1 is high if it is performed by a CPU (Central Processing Unit) alone, by having a DSP (Digital Signal Processor) mounted on an SoC (System on Chip) perform the process, it is possible to realize each process on the SoC while reducing the processing load on the CPU. In this case, it is necessary to consider how to allocate each process to the DSP / CPU.

[0017] The inventors have found that the signal processing of the received signal of the radar device of FIG. 1 can be classified into the following three types of processing. Processing A: This is a process that has a constant amount of processing regardless of the received signal and can be divided among multiple DSPs. For example, FFT processing for speed detection corresponds to processing A. Processing B: This is processing whose processing volume varies depending on the received signal and is dependent on the preceding processing (processing A) and cannot be divided. For example, CFAR / peak detection processing that depends on the preceding processing A (FFT processing) corresponds to processing B. Process C: This is a process that does not depend on the previous process (process A or process B). For example, pre-processing for object detection corresponds to process C. Pre-processing for object detection is a process that is required before object detection processing.

[0018] In signal processing, it is common to use DSPs to reduce CPU load. For example, one method of allocating processing to multiple DSPs is to allocate evenly processes that can be divided, such as process A, while allocating processes that cannot be divided, such as processes B and C, using priorities or round robin.

[0019] The inventors have studied the problems that arise when the above processes A to C are allocated to multiple DSPs using such related allocation methods. For example, when process A is allocated to multiple DSPs and process B is executed after process A, the processing time of process B may result in idle time in the DSPs.

[0020] 2A and 2B show an example of allocating processes A to C to DSP1 and DSP2 using a related allocation method. In Figures 2A and 2B, process A is first allocated evenly to DSP1 and DSP2, and then process B is allocated to DSP1 and process C is allocated to DSP2.

[0021] Figure 2A shows an example where the processing volume (processing time) of process B is greater than the processing volume of process C. As shown in Figure 2A, when the processing volume of process B is large, free time occurs in DSP2. In this case, the total processing time is determined by the processing time of DSP1, and is 120 ms, consisting of 50 ms for process A and 70 ms for process B.

[0022] Figure 2B shows an example where the processing volume of process B is smaller than that of process C. As shown in Figure 2B, when the processing volume of process B is small, free time occurs in DSP1. In this case, the total processing time is determined by the processing time of DSP2, and is 100 ms, consisting of 50 ms for process A and 50 ms for process C.

[0023] In this way, when processes are allocated using related allocation methods, there is a problem that the amount of processing varies depending on the DSP, and the overall processing time is determined by the DSP that takes the longest processing time. To solve this problem, it is possible to change the proportion of processing A allocated to each DSP, but since the processing amount of processing B cannot be known unless processing A is performed, it is not possible to allocate it in advance.

[0024] (Outline of the embodiment) 3 shows a schematic configuration of a semiconductor device 10 according to an embodiment. For example, the semiconductor device 10 is a semiconductor device that processes received signals from a radar device, but may also be a semiconductor device that processes other signals. As shown in FIG. 3, the semiconductor device 10 includes a first signal processing unit 11, a second signal processing unit 12, and a control unit 20.

[0025] The first signal processing unit 11 and the second signal processing unit 12 perform predetermined processing on the input signal. For example, the first signal processing unit 11 and the second signal processing unit 12 may be configured with a DSP. The first signal processing unit 11 and the second signal processing unit 12 are capable of performing a first processing and a second processing that is performed based on the result of the first processing. The first processing is the above-mentioned processing A and may be, for example, FFT processing. The second processing is the above-mentioned processing B and may be, for example, CFAR / peak detection processing. The first signal processing unit 11 and the second signal processing unit 12 may further be capable of performing a third processing. The third processing is the above-mentioned processing C and may be, for example, object detection preprocessing.

[0026] The control unit 20 controls the processing executed by the first signal processing unit 11 and the second signal processing unit 12. For example, the control unit 20 may be configured with a CPU (and a program). The control unit 20 includes a detection unit 21, a prediction unit 22, and a distribution unit 23.

[0027] The detection unit 21 detects the amount of processing of the second processing executed by the first signal processing unit 11 or the second signal processing unit 12. For example, the second processing is assigned to the first signal processing unit 11 or the second signal processing unit 12, and the assigned signal processing unit executes the second processing. The detection unit 21 may detect the processing time of the executed second processing as the amount of processing of the second processing, or may detect the number of peaks (peak points) detected by the CFAR / peak detection processing, which is the second processing.

[0028] The prediction unit 22 predicts the processing amount of the second process to be executed next, based on the processing amount of the second process detected by the detection unit 21. For example, the prediction unit 22 may include a storage unit that stores the detected processing amount of the second process, and the prediction unit 22 may predict the processing amount of the second process to be executed next, based on the detected processing amount of the second process and the processing amount of the second process stored in the past. For example, the prediction unit 22 may predict the processing time of the second process to be executed next, or may predict the number of peaks to be detected next.

[0029] The allocating unit 23 allocates the first processing to be executed next to the first signal processing unit 11 and the second signal processing unit 12 in accordance with the second processing amount predicted by the predicting unit 22. The allocating unit 23 determines the processing amount of the first processing to be allocated to the first signal processing unit 11 and the processing amount of the first processing to be allocated to the second signal processing unit 12 in accordance with the predicted processing amount of the second processing. For example, the allocating unit 23 may determine an allocation ratio (proportion of the processing amount to be allocated) for the first signal processing unit 11 and the second signal processing unit 12 in accordance with the predicted processing amount of the second processing, and allocate the first processing to the first signal processing unit and the second signal processing unit based on the determined allocation ratio.

[0030] In this manner, in the embodiment, when a signal processing unit such as a DSP executes a second process following a first process, the first process to be executed next is allocated to the signal processing unit based on the amount of processing of the executed second process. By predicting the amount of processing of the second process to be executed next from the amount of processing of the executed second process and allocating the first process according to the prediction result, the processing efficiency of the signal processing unit can be improved and the processing time can be shortened.

[0031] 4A and 4B show an example in which processes A to C are allocated to DSP1 and DSP2 using the allocation method of the semiconductor device according to the embodiment. FIG. 4A is an example in which the embodiment is applied to FIG. 2A, and similarly to FIG. 2A, it is an example in which the processing amount (processing time) of process B is larger than the processing amount of process C. In the example of FIG. 4A, the semiconductor device according to the embodiment detects that the processing amount of process B is large and predicts that the processing amount of the next process B will be large. Therefore, for process A, the processing amount allocated to DSP1 is reduced from 50 ms to 40 ms, and the processing amount allocated to DSP2 is increased from 50 ms to 60 ms. As a result, there is no free time for DSP2, and the total processing time by DSP1 and DSP2 is 110 ms, thereby shortening the total processing time compared to FIG. 2A.

[0032] FIG. 4B shows an example in which the embodiment is applied to FIG. 2B, and similarly to FIG. 2B, it shows an example in which the processing amount of process B is smaller than the processing amount of process C. In the example of FIG. 4B, the semiconductor device according to the embodiment detects that the processing amount of process B is small and predicts that the processing amount of the next process B will be small. Therefore, for process A, the processing amount allocated to DSP1 is increased from 50 ms to 70 ms, and the processing amount allocated to DSP2 is reduced from 50 ms to 30 ms. This eliminates the idle time of DSP1, and the total processing time by DSP1 and DSP2 is 80 ms, thereby shortening the total processing time compared to FIG. 2B.

[0033] (Embodiment 1) Next, a description will be given of Embodiment 1. In this embodiment, an example will be described in which DSP processing is allocated based on the number of peak points detected by CFAR / peak detection processing.

[0034] 5 shows an example of the hardware configuration of a semiconductor device 100 according to this embodiment. The semiconductor device 100 processes a received signal of a radar. The semiconductor device 100 is configured, for example, by an SoC equipped with multiple DSPs. The radar applied to the semiconductor device 100 is, for example, an in-vehicle radar, but may be any other radar.

[0035] 5, the semiconductor device 100 includes, as its hardware configuration, a CPU 110, two DSPs 120 (120a and 120b), a radar sensor 130, and a ROM / RAM 140. The CPU 110, the DSPs 120a and 120b, and the ROM / RAM 140 are connected to a bus 101. The radar sensor 130 is connected to the bus 101 via an I / F (interface) 131.

[0036] The ROM (Read Only Memory) / RAM (Random Access Memory) 140 stores data and programs necessary for the operation of the semiconductor device 100, the results of each process, etc. The ROM / RAM 140 is an example of a storage unit that stores data, etc., and may include either or both of a ROM and a RAM, or may include other types of storage devices.

[0037] The radar sensor 130 is a radar device that detects objects using radio waves. The radar sensor 130 may be an FMCW radar or another type of radar. For example, the radar sensor 130 includes a transmitting antenna and multiple receiving antennas. A transmitting wave is transmitted from the transmitting antenna, and the reflected wave reflected by an object is received by the multiple receiving antennas. The radar sensor 130 performs AD conversion on the signals of the reflected waves received by the multiple receiving antennas to generate radar reception data. The radar sensor 130 stores the generated radar reception data in the ROM / RAM 140 via the I / F 131.

[0038] The DSP 120a (e.g., a first signal processing unit) and the DSP 120b (e.g., a second signal processing unit) perform predetermined digital signal processing on the radar reception data received by the radar sensor 130. The DSPs 120a and 120b acquire the radar reception data stored in the ROM / RAM 140, perform digital signal processing on the acquired radar reception data, and store the processing results in the ROM / RAM 140. The DSPs 120a and 120b perform the assigned processing in accordance with the control of the CPU 110.

[0039] The CPU 110 is a control unit that controls the operation of each unit of the semiconductor device 100. For example, the functions of the CPU 110 are realized by executing a program stored in the ROM / RAM 140. The CPU 110 controls the allocation (processing content and processing amount) of processing to be performed by the DSPs 120a and 120b. The CPU 110 may execute software processing as necessary on the processing results of the DSPs 120a and 120b stored in the ROM / RAM 140, and store the processing results in the ROM / RAM 140.

[0040] 5 shows the case of two DSPs, this embodiment can be similarly applied to the case of three or more DSPs. Furthermore, this embodiment can be similarly applied not only to DSPs but also to hardware accelerators, multi-core CPUs, and other devices that perform software processing.

[0041] Fig. 6 shows an example of the configuration of functional blocks of the semiconductor device 100 (CPU and DSP) of Fig. 5. As shown in Fig. 6, the semiconductor device 100 includes, as functional blocks, an FFT processing unit 201, a CFAR / peak detection processing unit 202, an object detection preprocessing unit 203, and an object detection processing unit 204. Furthermore, the semiconductor device 100 includes a DSP processing allocator 111, a peak point weighting unit 112, a detected peak number increase / decrease calculation unit 113, and a detected peak number prediction unit 114.

[0042] In this example, the FFT processing unit 201, the CFAR / peak detection processing unit 202, and the object detection preprocessing unit 203 are included in the DSP 120 (120a and 120b). The other processing units, namely, the object detection processing unit 204, the DSP processing allocation unit 111, the peak point weighting unit 112, the detected peak number increase / decrease calculation unit 113, and the detected peak number prediction unit 114 are included in the CPU 110.

[0043] The FFT processing unit 201, CFAR / peak detection processing unit 202, object detection preprocessing unit 203, and object detection processing unit 204 are the same functional blocks as those in Fig. 1. That is, the FFT processing unit 201 performs FFT processing on radar reception data received by the radar sensor 130. The FFT processing unit 201 acquires one frame of radar reception data, performs Fourier transforms on the acquired radar reception data in the range direction and Doppler direction, and generates an RD map. The FFT processing can be divided and executed by multiple DSPs. For example, the FFT processing units 201 of the DSPs 120a and 120b are assigned a processing amount (e.g., range) for FFT processing by the DSP processing allocation unit 111, and each performs FFT processing on the assigned amount of data.

[0044] The CFAR / peak detection processor 202 performs CFAR / peak detection processing on the RD map generated by the FFT processor 201. The CFAR / peak detection processor 202 uses CFAR processing to detect peaks (peak points) of signal levels in the RD map of one frame. The CFAR / peak detection processing is performed following the FFT processing. The CFAR / peak detection processing cannot be divided and executed by multiple DSPs. For example, one of the CFAR / peak detection processors 202 of the DSPs 120a and 120b is assigned by the DSP processing allocation unit 111 to perform the CFAR / peak detection processing, and the CFAR / peak detection processing is executed according to the assignment.

[0045] The object detection pre-processing unit 203 performs object detection pre-processing required before object detection processing. The object detection pre-processing unit 203 may perform, for example, calculation processing for angle estimation (processing for determining the direction of the peak point) as object detection pre-processing. The object detection pre-processing can be performed at any timing before the object detection processing. For example, the object detection pre-processing may be performed following FFT processing. The object detection pre-processing cannot be divided and executed by multiple DSPs. For example, one of the object detection pre-processing units 203 of the DSPs 120a and 120b is assigned by the DSP processing allocation unit 111 to perform the object detection pre-processing, and performs the object detection pre-processing according to the assignment.

[0046] The object detection processing unit 204 performs object detection processing based on peak points in one frame (RD map) detected by the CFAR / peak detection processing unit 202. The object detection processing is performed after the CFAR / peak detection processing and object detection pre-processing. The object detection processing unit 204 outputs object data of the detected object. For example, the object detection processing unit 204 stores the object data in the ROM / RAM 140.

[0047] The peak point weighting unit 112 weights the peak points in one frame (RD map) detected by the CFAR / peak detection processing unit 202. The peak point weighting unit 112 determines a weighting coefficient according to the moving speed of the peak point, and multiplies the peak point by the determined weighting coefficient. The moving speed of the peak point can be extracted from one frame of radar reception data. For example, the moving speed of the peak point can be extracted based on the phase difference of reflected waves received by multiple receiving antennas.

[0048] The detected peak number increase / decrease calculation unit 113 calculates the increase / decrease rate of the number of detected peak points from the number of detected peak points in the current frame and the number of detected peak points in multiple past frames. The increase / decrease rate is the rate at which the number of detected peak points in the next frame increases or decreases compared to the number of detected peak points in the previous frame. The detected peak number increase / decrease calculation unit 113 counts the number of detected peak points in a frame using the number of detected peak points weighted by the peak point weighting unit 112. The detected peak number increase / decrease calculation unit 113 also serves as a detection unit that detects the amount of processing (number of peak points) in the CFAR / peak detection process. Note that the number of detected peak points detected by the CFAR / peak detection processing unit 202 may be used directly to calculate the increase / decrease rate.

[0049] The detected peak number prediction unit 114 predicts the number of detected peak points in the next frame based on the rate of increase or decrease in the number of detected peak points calculated by the detected peak number increase / decrease calculation unit 113. For example, since the increase / decrease trend in the number of detected peak points can be grasped from the rate of increase / decrease in the number of detected peak points between frames, the detected peak number prediction unit 114 predicts the number of detected peak points in the next frame based on the increase / decrease trend.

[0050] The DSP processing allocator 111 allocates DSP processing for the next frame based on the number of detected peak points for the next frame predicted by the peak detection number predictor 114. For example, the DSP processing allocator 111 determines an allocation ratio for FFT processing to be executed by the DSPs 120a and 120b according to the predicted number of detected peak points, and allocates the processing load of the FFT processing to the DSPs 120a and 120b according to the allocation ratio. The allocation ratio is the proportion of the processing load allocated (allocated) to the DSPs 120a and 120b, respectively. The DSP processing allocator 111 also allocates CFAR / peak detection processing and object detection pre-processing to either the DSPs 120a or 120b, respectively. The DSP processing allocator 111 allocates CFAR / peak detection processing to one of the DSPs 120a and 120b, and allocates object detection pre-processing to the other of the DSPs 120a and 120b. The allocation of CFAR / peak detection processing and object detection pre-processing may be preset.

[0051] 7 shows an example of operation of the semiconductor device 100 according to this embodiment. As shown in FIG. 7, first, the DSP processing allocation unit 111 allocates processing for the first frame to each DSP (S101). The DSP processing allocation unit 111 allocates FFT processing equally to the DSPs 120a and 120b. For example, the DSP processing allocation unit 111 allocates FFT processing for 50% of the range of one frame of radar reception data to the DSP 120a, and allocates FFT processing for the remaining 50% of the range of one frame of radar reception data to the DSP 120b. Furthermore, the DSP processing allocation unit 111 allocates CFAR / peak detection processing to the DSP 120a, and object detection pre-processing to the DSP 120b, for example.

[0052] Next, the FFT processing units 201 of the DSPs 120a and 120b perform FFT processing on the radar reception data of one frame (for example, the first frame) that is input (S102). The FFT processing units 201 of the DSPs 120a and 120b perform FFT processing on the radar reception data of the ranges allocated by the DSP processing allocation unit 111, respectively, and generate RD maps for the corresponding ranges.

[0053] Next, the CFAR / peak detection processing unit 202 of one of the DSPs 120a and 120b performs CFAR / peak detection processing (S103). For example, the CFAR / peak detection processing unit 202 of the DSP 120a performs CFAR / peak detection processing on the RD map generated by the FFT processing unit 201 of the DSPs 120a and 120b to detect peak points of one frame. That is, when the FFT processing unit 201 of the DSP 120a finishes, the CFAR / peak detection processing unit 202 of the DSP 120a performs CFAR / peak detection processing on the RD map generated by the FFT processing unit 201 of the DSP 120a, and when the FFT processing unit 201 of the DSP 120b finishes, the CFAR / peak detection processing unit 202 of the DSP 120a performs CFAR / peak detection processing on the RD map generated by the FFT processing unit 201 of the DSP 120b.

[0054] Furthermore, the object detection pre-processing unit 203 of the other of the DSPs 120a and 120b performs object detection pre-processing (S104). For example, the object detection pre-processing unit 203 of the DSP 120b performs object detection pre-processing after the FFT processing of the DSP 120b.

[0055] When all of the DSPs 120a and 120b have completed processing in steps S102 to S104, the DSP processing for one frame is complete. Subsequently, the object detection processing unit 204 performs object detection processing based on the peak point detection results for one frame (S105). For example, the object detection processing unit 204 performs CFAR / peak detection processing by the CFAR / peak detection processing unit 202 of the DSP 120a and object detection pre-processing by the DSP 120b, followed by object detection processing to detect objects in one frame.

[0056] Furthermore, following the CFAR / peak detection processing of one of the DSPs 120a and 120b, the peak point weighting unit 112 weights the peak points detected from one frame (S201). For example, the peak points of one frame detected by the CFAR / peak detection processing unit 202 of the DSP 120a are multiplied by a weighting coefficient according to the moving speed of the peak points. The peak point weighting unit 112 extracts the moving speed of the peak points from one frame of radar reception data and determines a weighting coefficient for the peak points according to the extracted moving speed. The number of peak points multiplied by the determined weighting coefficient is counted as the number of detections of that point.

[0057] FIG. 8 is a graph showing an example of a weighting coefficient determination table. For example, as shown in FIG. 8, the peak point weighting unit 112 derives a weighting coefficient according to the moving speed of the peak point using a table with the horizontal axis representing the moving speed of the peak point and the vertical axis representing the weighting coefficient. Using a table like that shown in FIG. 8, the weighting coefficient is reduced when the moving speed of the peak point is fast and increased when the moving speed of the peak point is slow, thereby reducing the influence of points with high moving speeds. By counting peak points with fast moving speeds using a small weighting coefficient, the accuracy of predicting the number of detected peak points can be improved. For example, the weighting coefficient can be said to indicate the reliability of the detected peak points.

[0058] Next, the detected peak number increase / decrease calculation unit 113 calculates the rate of increase / decrease in the number of detected peak points based on the weighted peak point values in multiple frames (S202). Fig. 9 shows an example of the number of detected peak points in multiple frames. As shown in Fig. 9, the detected peak number increase / decrease calculation unit 113 counts the number of detected peak points weighted by the peak point weighting unit 112 and stores the counting result for that frame in ROM / RAM 140. The detected peak number increase / decrease calculation unit 113 calculates the rate of increase / decrease in the number of detected peak points from the number of detected peak points in the current frame and the number of detected peak points in multiple past frames stored in ROM / RAM 140.

[0059] Next, the detected peak number prediction unit 114 predicts the number of detected peak points in the next frame based on the calculated rate of increase or decrease in the number of detected peak points (S203). For example, the detected peak number prediction unit 114 predicts the rate of increase or decrease in the number of detected peak points in the next frame based on the rate of increase or decrease in the number of detected peak points calculated from the current and past counting results. The rate of increase or decrease can be predicted simply by using the difference from the previous frame or the average of the differences over multiple frames. The detected peak number prediction unit 114 predicts the number of detected peak points in the next frame according to the predicted rate of increase or decrease.

[0060] Next, the DSP processing allocation unit 111 allocates the DSP processing for the next frame based on the predicted number of detected peak points for the next frame (S204). FIG. 10 is a graph showing an example of a DSP allocation rate determination table. As shown in FIG. 10, the DSP processing allocation unit 111 converts the predicted number of detected peak points into a DSP allocation rate using a conversion table or formula with the horizontal axis representing the predicted number of detected peak points and the vertical axis representing the DSP allocation rate. The DSP allocation rate indicates the ratio of FFT processing allocated to the DSP 120a and the DSP 120b. For example, as the number of detected peak points (the processing amount of the DSP 120a) increases, the ratio of processing allocated to the DSP 120b increases and the ratio of processing allocated to the DSP 120a decreases. Conversely, as the number of detected peak points (the processing amount of the DSP 120a) decreases, the ratio of processing allocated to the DSP 120a increases and the ratio of processing allocated to the DSP 120b decreases. 10, the horizontal axis represents the predicted number of detected peak points, but the horizontal axis may represent the rate of increase or decrease in the predicted number of detected peak points. The DSP processing allocation unit 111 allocates the DSP processing (FFT processing) for the next frame according to the converted DSP allocation rate. From S102 onwards, the DSPs 120a and 120b execute each process according to the allocation. For example, as shown in FIGS. 4A and 4B, the initial state is one in which the amount of calculation processing for process A (FFT processing) is allocated to the DSPs 120a and 120b in a ratio of 50:50, and the amount of calculation processing allocated to each of the DSPs 120a and 120b is distributed according to the allocation rate, and each DSP is caused to perform processing.

[0061] As described above, in this embodiment, in a semiconductor device that processes radar signals, the allocation of each DSP process is performed based on the number of detected peak points in the past. Specifically, the number of detected peak points in the next frame is predicted based on the rate of increase or decrease in the number of detected peak points in multiple past frames, and the allocation of processes is determined according to the predicted number of detected peak points. This improves the efficiency of DSP usage and shortens the overall processing time. Because the number of detected peak points is predicted using information from multiple past frames, it is possible to eliminate the influence of noise, such as a single frame being out of the ordinary, and improve the accuracy of prediction.

[0062] (Modification of the first embodiment) In the modification of the first embodiment, the DSP processing is allocated based on the processing time of the CFAR / peak detection processing.

[0063] Fig. 11 shows an example of the configuration of functional blocks of semiconductor device 100 according to a modification of embodiment 1. In the example of Fig. 11, semiconductor device 100 includes a DSP processing time increase / decrease calculation unit 113a and a DSP processing time prediction unit 114a, instead of peak point weighting unit 112, detected peak number increase / decrease calculation unit 113, and detected peak number prediction unit 114, as compared to Fig. 6.

[0064] The DSP processing time increase / decrease calculation unit 113a calculates the increase / decrease rate of the processing time of the DSP 120. For example, the DSP processing time increase / decrease calculation unit 113a measures the processing time of the CFAR / peak detection processing for one frame executed by the CFAR / peak detection processing unit 202 of either DSP 120a or 120b. The DSP processing time increase / decrease calculation unit 113a also serves as a detection unit that detects the processing amount (processing time) of the CFAR / peak detection processing. The DSP processing time increase / decrease calculation unit 113a calculates the increase / decrease rate of the processing time of the CFAR / peak detection processing for one frame from the processing time of the CFAR / peak detection processing for the current frame by the CFAR / peak detection processing unit 202 and the processing times of the CFAR / peak detection processing for multiple past frames.

[0065] 12 shows an example of the DSP processing time for a plurality of frames. As shown in FIG. 12, DSP processing time increase / decrease calculation unit 113a measures the processing time of the CFAR / peak detection processing (DSP processing time) for one frame executed by CFAR / peak detection processing unit 202, and stores the measurement result for that frame in ROM / RAM 140. DSP processing time increase / decrease calculation unit 113a calculates the increase / decrease rate of the CFAR / peak detection processing processing time from the CFAR / peak detection processing processing time for the current frame and the CFAR / peak detection processing processing times for a plurality of past frames stored in ROM / RAM 140.

[0066] The DSP processing time prediction unit 114a predicts the processing time for the next frame based on the rate of increase or decrease in the processing time for one frame calculated by the DSP processing time increase or decrease calculation unit 113a. For example, the DSP processing time prediction unit 114a predicts the rate of increase or decrease and processing time for the CFAR / peak detection processing for the next frame based on the rate of increase or decrease in the CFAR / peak detection processing calculated from the current and past processing times for the CFAR / peak detection processing.

[0067] The DSP processing allocation unit 111 allocates the DSP processing for the next frame based on the processing time for the next frame predicted by the DSP processing time prediction unit 114a. The method of allocating the processing is the same as in embodiment 1. For example, the DSP processing allocation unit 111 determines an allocation ratio for the FFT processing to be executed by the DSPs 120a and 120b according to the predicted processing time for the CFAR / peak detection processing, and allocates the FFT processing to the DSPs 120a and 120b according to the determined allocation ratio.

[0068] 13 is a graph showing an example of a DSP allocation rate determination table. As shown in FIG. 13, DSP processing allocation unit 111 converts the processing time of the predicted CFAR / peak detection processing (DSP processing time) into a DSP allocation rate using a conversion table or formula in which the horizontal axis represents the processing time of the predicted CFAR / peak detection processing (DSP processing time) and the vertical axis represents the DSP allocation rate.

[0069] As described above, instead of counting the number of detected peak points, the processing time of each DSP may be measured to calculate the rate of increase or decrease in the DSP processing time for each frame, and the DSP processing allocation rate may be determined from the rate of increase or decrease in the processing time. In this case, the bias in each DSP processing can be grasped and each DSP processing can be appropriately allocated without counting the number of detected peak points.

[0070] (Embodiment 2) Next, a description will be given of a second embodiment. In this embodiment, an example will be described in which the predicted result of the number of detected peak points is corrected based on the tracking result of the object.

[0071] Fig. 14 shows an example of the configuration of functional blocks of the semiconductor device 100 according to this embodiment. In the example of Fig. 14, the semiconductor device 100 includes a tracking processing unit 205, an object disappearance prediction unit 206, and a point cloud number estimation unit 207 in addition to the configuration of Fig. 6. Note that although the peak point weighting unit 112 is omitted in Fig. 14, the peak point weighting unit 112 may be included as in Fig. 6.

[0072] In the object detection process of the object detection processing unit 204, multiple points (point clouds) that are close to each other and have the same moving direction and speed are treated as the same object. At this time, the number of points that are treated as the same object is stored in the ROM / RAM 140.

[0073] The tracking processing unit 205 is the same as the tracking processing unit in Fig. 1. That is, the tracking processing unit 205 performs tracking processing based on objects detected by the object detection processing unit 204. The tracking processing unit 205 tracks objects based on object detection results for multiple frames. For example, the object detection results for each frame are stored in the ROM / RAM 140, and in the tracking processing, tracking is performed on an object that has been identified as the same object based on the position, movement direction, and movement speed of the object detected in the current frame and the object in past frames.

[0074] The object disappearance prediction unit 206 predicts an object that will go out of the radar detection range (disappear) in the next frame based on the moving direction and moving speed of the object tracked by the tracking processing unit 205. For example, if the radar sensor 130 is an on-vehicle radar, it predicts that a detected object will frame out (disappear) from the radar detection range due to the passing of the host vehicle and an oncoming vehicle as shown in Fig. 15 .

[0075] The point cloud number estimation unit 207 estimates the number of point clouds (the number of peak points) corresponding to an object that goes out of the radar detection range based on the prediction result of the object disappearance prediction unit 206. For example, the value stored in the ROM / RAM 140 at the time of object detection is used as the point cloud number of the disappearing object.

[0076] When predicting the number of detected peak points in the next frame based on the rate of increase or decrease in the number of detected peak points calculated by the detected peak number increase / decrease calculation unit 113, the detected peak number prediction unit 114 subtracts the number of point clouds that will disappear estimated by the point cloud number estimation unit 207 from the predicted number of detected peak points. That is, the detected peak number prediction unit 114 corrects the predicted number of detected peak points based on the tracking result. For example, as shown in Fig. 16 , the number of detected peak points in the next frame is determined by subtracting the number of point clouds that will disappear from the number of detected peak points predicted based on the number of detected peak points in multiple frames.

[0077] As in embodiment 1, the DSP processing allocation unit 111 calculates a DSP allocation rate from the number of detected peak points in the next frame based on the value obtained by subtracting the number of point groups that will disappear, and allocates DSP processing for the next frame using the calculated allocation rate.

[0078] For example, in the first embodiment, tracking is not possible when the number of detected points changes suddenly, such as when a detected object goes out of frame and disappears, as in the case of passing cars, as shown in Figure 15. In this embodiment, an object is detected from the detected point cloud, and from the tracking process results that follow the movement of the object, it is predicted that the object will disappear in the next frame (disappearance detection), and the number of disappearing point clouds is estimated, thereby predicting the number of detections in the next frame. This makes it possible to improve the accuracy of prediction of the number of detected peak points.

[0079] (Embodiment 3) Next, a description will be given of a third embodiment. In this embodiment, an example will be described in which the number of detected peak points is learned and predicted using a learning model.

[0080] Fig. 17 shows an example of the configuration of functional blocks of the semiconductor device 100 according to this embodiment. In the example of Fig. 17, the semiconductor device 100 includes a time-series prediction learning unit 115 and a predicted detection number recording unit 116 instead of the peak detection number prediction unit 114, as compared to the configuration of Fig. 6. Note that although the peak point weighting unit 112 is omitted in Fig. 17, the peak point weighting unit 112 may also be included as in Fig. 6.

[0081] The predicted detection number recording unit 116 records (stores) the number of detections predicted by the time-series prediction learning unit 115. The predicted detection number recording unit 116 may be included in the ROM / RAM 140.

[0082] The time series prediction learning unit 115 learns using time series prediction to obtain a predicted value for the number of detected peak points. The time series prediction learning unit 115 learns and predicts the number of detected peak points in the next frame based on the rate of increase or decrease in the number of detected peak points obtained by the detected peak number increase / decrease calculation unit 113. The time series prediction learning unit 115 learns the predicted value for the number of detected peak points while recording the numbers of detected peak points predicted in the past in the predicted detection number recording unit 116.

[0083] 18, the difference between the actual number of detected peak points and the number of detected peak points predicted in the past, as well as the trend of this difference, is learned by time series prediction, and the predicted value is corrected as needed, thereby reducing the prediction error of subsequent frames. An autoregressive model (AR model), a moving average model (MA model), or the like can be applied to the time series prediction of the time series prediction learning unit 115.

[0084] As in the first embodiment, the DSP processing allocation unit 111 calculates a DSP allocation rate from the predicted number of detected peak points in the next frame, and allocates DSP processing for the next frame using the calculated allocation rate.

[0085] In the first embodiment, if the prediction of the number of detected peak points is wrong, it takes more processing time than expected. In the present embodiment, the amount of prediction error can be reduced by using time series prediction to correct the prediction error of the number of detected peak points as needed.

[0086] This embodiment may be applied to a modification of the first embodiment or to the second embodiment. For example, in the modification of the first embodiment, the DSP processing time may be learned and predicted in the same way as in this embodiment. When learning the DSP processing time, the processing time of the CFAR / peak detection processing may be learned, or the free time of the DSP processing may be learned. By learning and predicting the difference between the time when the CFAR / peak detection processing ends and the time when the object detection pre-processing ends, it is possible to allocate the DSP processing so as to minimize the difference.

[0087] (Modification of the third embodiment) As a modification of the third embodiment, a table for deriving the DSP allocation rate from the predicted value of the number of detected peak points may be modified as needed.

[0088] FIG. 19 shows an example of a DSP allocation rate determination table according to a modification of the third embodiment. As shown in FIG. 19, a table or formula that calculates a DSP allocation rate from a predicted value of the number of detected peak points may be shifted upward or downward on a graph. The up and down direction of the graph is the vertical axis direction indicating the DSP allocation rate. By shifting the table or formula upward or downward, the allocation rate for the predicted value of the number of detected peak points can be changed. For example, the time series prediction learning unit 115 or the DSP processing allocation unit 111 may learn to obtain an optimal DSP allocation rate by shifting the table or formula that calculates the DSP allocation rate.

[0089] In this way, even with a configuration in which the table for deriving the DSP allocation rate from the predicted value of the number of detected peak points is corrected as needed, the same effects as those of the third embodiment can be obtained.

[0090] Each element shown and described in the drawings as a functional block performing various processes can be configured in hardware by a CPU, memory, and other circuits, and can be realized in software by a program loaded into memory, etc. Therefore, it will be understood by those skilled in the art that these functional blocks can be realized in various forms by hardware alone, software alone, or a combination thereof, and are not limited to any one of them.

[0091] The above program can be stored and supplied to a computer using various types of non-transitory computer-readable media. Non-transitory computer-readable media include various types of tangible storage media. Examples of non-transitory computer-readable media include magnetic storage media (e.g., flexible disks, magnetic tapes, hard disk drives), magneto-optical storage media (e.g., magneto-optical disks), CD-ROMs (Read Only Memory), CD-Rs, CD-R / Ws, and semiconductor memories (e.g., mask ROMs, PROMs (Programmable ROMs), EPROMs (Erasable PROMs), flash ROMs, and RAMs (Random Access Memory)). The program may also be supplied to a computer by various types of transitory computer-readable media. Examples of transitory computer-readable media include electrical signals, optical signals, and electromagnetic waves. The transitory computer-readable media can supply the program to a computer via a wired communication path such as an electric wire or optical fiber, or via a wireless communication path.

[0092] The invention made by the inventor has been specifically described above based on the embodiments, but it goes without saying that the present invention is not limited to the embodiments already described, and various modifications are possible within the scope of the gist of the invention. [Explanation of symbols]

[0093] 10 Semiconductor device 11 First signal processing section 12 Second signal processing section 20 Control Unit 21 Detection unit 22 Prediction Department 23 Distribution Department 100 Semiconductor device 101 Bus 110 CPU 111 DSP processing allocation unit 112 Peak point weighting section 113 Peak detection number increase / decrease calculation unit 113a DSP processing time increase / decrease calculation unit 114 Peak detection number prediction section 114a DSP processing time prediction unit 115 Time Series Prediction Learning Unit 116 Predicted detection number recording section 120, 120a, 120b DSP 130 Radar Sensor 131 Interface 140 ROM / RAM 201 FFT processing section 202 CFAR / Peak detection processing section 203 Object detection preprocessing section 204 Object detection processing unit 205 Tracking processing unit 206 Object Loss Prediction Unit 207 Point Cloud Number Estimation Unit

Claims

1. a first signal processing unit, a second signal processing unit, and a control unit; the first signal processing unit and the second signal processing unit are capable of executing a first process and a second process that is executed based on a result of the first process, The control unit a detection unit that detects a processing amount of the second processing executed by the first signal processing unit or the second signal processing unit; a prediction unit that predicts a processing amount of the second process to be executed next based on the detected processing amount of the second process; a distribution unit that distributes the first processing to the first signal processing unit and the second signal processing unit according to the predicted processing amount of the second processing; A semiconductor device comprising:

2. the allocating unit allocates the second processing to the first signal processing unit or the second signal processing unit; The semiconductor device according to claim 1 .

3. the first signal processing unit and the second signal processing unit are further capable of executing a third process; the allocating unit allocates the second processing to one of the first signal processing unit and the second signal processing unit, and allocates the third processing to the other of the first signal processing unit and the second signal processing unit. The semiconductor device according to claim 2 .

4. a storage unit for storing the detected processing amount of the second processing; the prediction unit predicts the throughput of the second process to be executed next based on the detected throughput of the second process and the throughput of the second process stored in the past. The semiconductor device according to claim 1 .

5. the allocating unit determines an allocation ratio of the first processing to the first signal processing unit and the second signal processing unit according to the predicted processing amount of the second processing. The semiconductor device according to claim 1 .

6. the processing amount of the second processing is a processing time of the second processing; The semiconductor device according to claim 1 .

7. the first processing is FFT processing on radar reception data, the second processing is a peak detection processing for the result of the FFT processing, the processing amount of the second processing is the number of peaks detected by the peak detection processing; The semiconductor device according to claim 1 .

8. the detection unit weights the peaks detected by the peak detection process in accordance with the moving speed of the peaks. The semiconductor device according to claim 7 .

9. an object detection unit that detects an object based on the peaks detected by the peak detection processing; a tracking unit that tracks the detected object, the prediction unit corrects the predicted number of detected peaks based on the tracking result. The semiconductor device according to claim 7 .

10. When it is predicted from the tracking result that the detected object will disappear from the detection range of the radar, the prediction unit subtracts the number of peaks corresponding to the disappearing object from the predicted number of detected peaks. The semiconductor device according to claim 9 .

11. the prediction unit includes a learning model that learns a processing amount of the second process to be executed next based on the detected processing amount of the second process. The semiconductor device according to claim 1 .

12. a storage unit for storing the processing amount of the second processing predicted by the learning model; the learning model performs the learning based on the detected processing amount of the second process and the processing amount of the second process stored in the past. The semiconductor device according to claim 11.

13. A method for controlling a semiconductor device including a first signal processing unit and a second signal processing unit, the first signal processing unit and the second signal processing unit are capable of executing a first process and a second process that is executed based on a result of the first process, The control method includes: Detecting a processing amount of the second processing executed by the first signal processing unit or the second signal processing unit; predicting a processing amount of the second process to be executed next based on the detected processing amount of the second process; allocating the first processing to the first signal processing unit and the second signal processing unit according to the predicted processing amount of the second processing; A method for controlling a semiconductor device.

14. A program for causing a computer to execute a control method for a semiconductor device including a first signal processing unit and a second signal processing unit, the first signal processing unit and the second signal processing unit are capable of executing a first process and a second process that is executed based on a result of the first process, The control method includes: Detecting a processing amount of the second processing executed by the first signal processing unit or the second signal processing unit; predicting a processing amount of the second process to be executed next based on the detected processing amount of the second process; allocating the first processing to the first signal processing unit and the second signal processing unit according to the predicted processing amount of the second processing; program.

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