Storage device

Abstract

To provide a highly reliable storage device.SOLUTION: A storage device comprises a first conductor, a second conductor above the first conductor, a third conductor above the second conductor, a fourth conductor above the third conductor, a fifth conductor above the fourth conductor, a sixth conductor above the fifth conductor, a seventh conductor, a first insulator, a second insulator, a first semiconductor and a second semiconductor. At least the third conductor and the fourth conductor have an opening. The first insulator, the first semiconductor, the second insulator, and the second semiconductor are sequentially arranged in this order from the inner lateral surface of the opening. The seventh conductor is arranged between the first semiconductor and the second insulator in a region between the third conductor and the second insulator. The first semiconductor is electrically connected to the second conductor and the fifth conductor. The second semiconductor is electrically connected to the first conductor and the sixth conductor.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a semiconductor device and a manufacturing method thereof.

[0002] Note that one aspect of the present invention is not limited to the above-mentioned technical fields. The technical fields of the inventions disclosed in this specification relate to products, methods, or manufacturing methods. Alternatively, one aspect of the present invention relates to processes, machines, manufactures, or compositions of matter.

[0003] In this specification and the like, a semiconductor device generally refers to anything that can function by utilizing semiconductor characteristics. Therefore, semiconductor elements such as transistors and diodes, and circuits including semiconductor elements are semiconductor devices. Furthermore, display devices, light-emitting devices, lighting devices, electro-optical devices, memory devices, imaging devices, communication devices, and electronic devices may also include semiconductor elements and semiconductor circuits. Furthermore, display devices, light-emitting devices, lighting devices, electro-optical devices, memory devices, imaging devices, communication devices, and electronic devices may also be referred to as semiconductor devices. One embodiment of the present invention particularly relates to a memory device and a manufacturing method thereof. [Background technology]

[0004] In recent years, with the increase in the amount of data handled, there has been a demand for semiconductor devices with larger storage capacities. Stacking memory cells is an effective way to increase the storage capacity per unit area (see Patent Documents 1 and 2). Stacking memory cells makes it possible to increase the storage capacity per unit area in accordance with the number of stacked memory cells. Patent Documents 3 and 4 disclose memory devices using oxide semiconductors. Patent Document 5 discloses a semiconductor memory using an oxide semiconductor as a charge storage layer.

[0005] Furthermore, Non-Patent Document 1 discloses CAAC-IGZO as a crystalline oxide semiconductor, and also discloses the growth mechanism of CAAC-IGZO. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] US Patent Publication No. 2011 / 0065270A1 [Patent Document 2] U.S. Patent Publication No. 9634097B2 [Patent Document 3] Japanese Patent Application Publication No. 2018-207038 [Patent Document 4] Japanese Patent Application Publication No. 2019-8862 [Patent Document 5] Japanese Patent Application Publication No. 2018-157205 [Non-patent literature]

[0007] [Non-Patent Document 1] Noboru Kimizuka and Shunpei Yamazaki, “PHYSICS AND TECHNOLOGY OF CRYSTALLINE OXIDE SEMICONDUCTOR CAAC-IGZO” FUNDAMENTALS (USA), Wiley-SID Series in Display Technology, 2017, p.94-97 Summary of the Invention [Problem to be solved by the invention]

[0008] In Patent Documents 1 and 2, a plurality of storage elements (also called memory cells) are stacked and connected in series to form a three-dimensional memory cell array (also called memory string).

[0009] In Patent Document 1, a columnar semiconductor is in contact with an insulator having a charge storage layer. In Patent Document 2, a columnar semiconductor is in contact with an insulator that functions as a tunnel dielectric. In both Patent Documents 1 and 2, information is written to a memory cell by extracting and injecting charges through the insulator. In this case, trap centers may be formed at the interface between the semiconductor and the insulator. The trap centers may capture electrons and cause the threshold voltage of the transistor to fluctuate. Furthermore, the extraction and injection of charges may cause deterioration of either or both the interior of the insulator and the interface between the semiconductor and the insulator, resulting in leakage and loss of charges stored in the charge storage layer. This may adversely affect the reliability of the memory device.

[0010] Therefore, an object of one embodiment of the present invention is to provide a highly reliable memory device.Another object of one embodiment of the present invention is to provide a memory device with a large storage capacity.Another object of one embodiment of the present invention is to provide a memory device with a small occupation area.Another object of one embodiment of the present invention is to provide a memory device with low manufacturing costs.Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device.Another object of one embodiment of the present invention is to provide a semiconductor device with low manufacturing costs.Another object of one embodiment of the present invention is to provide a novel semiconductor device.

[0011] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other problems from the description in the specification, drawings, claims, etc. [Means for solving the problem]

[0012] One aspect of the present invention is a memory device having a first conductor, a second conductor above the first conductor, a third conductor above the second conductor, a fourth conductor above the third conductor, a fifth conductor above the fourth conductor, a sixth conductor above the fifth conductor, a seventh conductor, a first insulator, a second insulator, a first semiconductor, and a second semiconductor, wherein at least the third conductor and the fourth conductor have openings, and the first insulator, the first semiconductor, the second insulator, and the second semiconductor are provided in that order from the inner side of the opening, and a seventh conductor is provided between the first semiconductor and the second insulator in the region between the third conductor and the second insulator, and the first semiconductor is electrically connected to the second conductor and the fifth conductor, and the second semiconductor is electrically connected to the first conductor and the sixth conductor.

[0013] In the above, it is preferable that the first insulator, the first semiconductor, the seventh conductor, the second insulator, and the second semiconductor are each provided as concentric layers inside the opening of the third conductor.

[0014] In the above, it is preferable that the first insulator, the first semiconductor, the second insulator, and the second semiconductor are provided as concentric layers inside the opening of the fourth conductor.

[0015] In the above, the first semiconductor is preferably a first oxide semiconductor.

[0016] In the above, the first oxide semiconductor preferably contains indium, an element M (the element M is one or more selected from aluminum, gallium, yttrium, tin, and titanium), and zinc.

[0017] In the above, the second semiconductor is preferably a second oxide semiconductor.

[0018] In the above, the first oxide semiconductor preferably contains indium, an element M (the element M is one or more selected from aluminum, gallium, yttrium, tin, and titanium), and zinc.

[0019] In the above, it is preferable that openings are also provided in the second conductor and the fifth conductor, a second insulator is provided between the second conductor and the second semiconductor, and a second insulator is provided between the fifth conductor and the second semiconductor.

[0020] Another embodiment of the present invention is a method for manufacturing a memory device, comprising steps of forming a first conductor, forming a second conductor above the first conductor, forming a first semiconductor electrically connected to the second conductor, forming openings in the first semiconductor and the second conductor, forming an insulator covering side surfaces of the first semiconductor and the second conductor within the openings, and forming a second semiconductor electrically connected to the first conductor, wherein an insulator is provided between the first semiconductor and the second semiconductor and an insulator is provided between the second conductor and the second semiconductor.

[0021] In the above, the first semiconductor is preferably a first oxide semiconductor.

[0022] In the above, the first oxide semiconductor preferably contains indium, an element M (the element M is one or more selected from aluminum, gallium, yttrium, tin, and titanium), and zinc.

[0023] In the above, the second semiconductor is preferably a second oxide semiconductor.

[0024] In the above, the second oxide semiconductor preferably contains indium, an element M (the element M is one or more selected from aluminum, gallium, yttrium, tin, and titanium), and zinc.

[0025] Another embodiment of the present invention is a method for manufacturing a memory device, comprising steps of forming a first conductor, forming a second conductor above the first conductor, processing the first conductor and the second conductor so that the width of the second conductor is shorter than the width of the first conductor, forming a third conductor above the second conductor, forming openings in the third conductor, the second conductor, and the first conductor, forming an insulator in the openings, and forming a semiconductor in the openings, wherein the insulator is provided between the first conductor and the semiconductor and the insulator is provided between the second conductor and the semiconductor.

[0026] In the above, the semiconductor is preferably an oxide semiconductor.

[0027] In the above, the oxide semiconductor preferably contains indium, an element M (the element M is one or more selected from aluminum, gallium, yttrium, tin, and titanium), and zinc. [Effects of the Invention]

[0028] In fabricating a three-dimensional memory cell array in which multiple memory elements are stacked and connected in series, the total number of steps can be made less than the product of the number of stacked memory elements and the number of steps required to fabricate one memory element, which is preferable. In other words, the number of steps required to fabricate the memory cell array is not proportional to the number of stacked memory elements. For example, when comparing the number of steps required to fabricate memory cell array A, which has four layers of memory elements, with the number of steps required to fabricate memory cell array B, which has 32 layers of memory elements, the number of steps required to fabricate memory cell array B can be significantly less than eight times the number of steps required to fabricate memory cell array A, even though the number of stacked memory elements is eight times as large.

[0029] According to one embodiment of the present invention, a highly reliable memory device can be provided. According to another embodiment of the present invention, a memory device with a large memory capacity can be provided. According to one embodiment of the present invention, a memory device with a small occupation area can be provided. According to one embodiment of the present invention, a memory device with low manufacturing costs can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device with low manufacturing costs can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided.

[0030] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract other effects from the description in the specification, drawings, claims, etc. [Brief explanation of the drawings]

[0031] [Figure 1] 1A and 1B are perspective views of a storage device. [Figure 2] FIG. 2 is a cross-sectional view of the storage device. [Figure 3] FIG. 3 is a cross-sectional view of a memory string. [Figure 4] FIG. 4 is a circuit diagram of a memory string. [Figure 5] 5A and 5B are cross-sectional views of a memory string. [Figure 6] FIG. 6 is a cross-sectional view of a memory element. [Figure 7] 7A and 7B are cross-sectional views of a memory string. [Figure 8] FIG. 8 is a cross-sectional view of a memory string. [Figure 9] Figure 9A is a diagram explaining the classification of crystal structures, Figure 9B is a diagram explaining the XRD spectrum of a CAAC-IGZO film, and Figure 9C is a diagram explaining the micro-electron diffraction pattern of a CAAC-IGZO film. [Figure 10] 10A to 10C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 11] 11A to 11C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 12] 12A to 12C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 13] 13A to 13C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 14] 14A to 14C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 15] 15A to 15C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 16] 16A to 16C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 17] 17A to 17C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 18] 18A to 18C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 19] 19A to 19C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 20] 20A to 20C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 21] 21A to 21C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 22] 22A to 22C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 23] 23A to 23C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 24] 24A to 24C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 25] 25A to 25C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 26] 26A to 26C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 27] 27A to 27C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 28] 28A to 28C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 29] 29A to 29C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 30] 30A to 30C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 31] 31A to 31C are cross-sectional views illustrating a manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 32] Fig. 32A is a schematic diagram of a multi-chamber film forming apparatus, and Fig. 32B is a cross-sectional view of a film forming chamber. [Figure 33] 33A to 33C are diagrams illustrating an example of the configuration of an ALD apparatus. [Figure 34] FIG. 34 is a diagram illustrating an example of the circuit configuration of a memory string. [Figure 35] FIG. 35 is a diagram illustrating an example of the circuit configuration of a memory string. [Figure 36] FIG. 36 is a diagram illustrating an example of the circuit configuration of a memory string. [Figure 37] FIG. 37 is a diagram illustrating an example of the circuit configuration of a memory string. [Figure 38] FIG. 38 is a diagram illustrating an example of the circuit configuration of a memory string. [Figure 39]FIG. 39 is a timing chart illustrating an example of a write operation of a memory string. [Figure 40] 40A and 40B are circuit diagrams illustrating an example of a write operation of a memory string. [Figure 41] 41A and 41B are circuit diagrams illustrating an example of a write operation of a memory string. [Figure 42] FIG. 42 is a timing chart illustrating an example of a read operation of a memory string. [Figure 43] 43A and 43B are circuit diagrams illustrating an example of a read operation of a memory string. [Figure 44] 44A and 44B are circuit diagrams illustrating an example of a read operation of a memory string. [Figure 45] FIG. 45 is a circuit diagram illustrating an example of a read operation of a memory string. [Figure 46] FIG. 46 is a block diagram illustrating a configuration example of a semiconductor device. [Figure 47] 47A to 47C are perspective views illustrating configuration examples of a semiconductor device. [Figure 48] FIG. 48 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 49] FIG. 49 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 50] FIG. 50A is a perspective view illustrating an example of the configuration of a computer, and FIG. 50B is a perspective view illustrating a monolithic IC. [Figure 51] 51A and 51B are diagrams illustrating the memory hierarchy of a computer, a monolithic IC, respectively. [Figure 52] Fig. 52A is a schematic diagram of a semiconductor device, and Fig. 52B is a perspective view of the semiconductor device. [Figure 53] 53A to 53E are diagrams for explaining an example of a storage device. [Figure 54] 54A to 54G are diagrams for explaining an example of an electronic device. DETAILED DESCRIPTION OF THE INVENTION

[0032] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various modifications in form and detail can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same parts or parts having similar functions will be denoted by the same reference numerals in different drawings, and repeated descriptions thereof will be omitted.

[0033] Furthermore, the position, size, range, etc. of each component shown in the drawings, etc. may not represent the actual position, size, range, etc. in order to facilitate understanding of the invention. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings, etc. For example, in an actual manufacturing process, a resist mask, etc. may be unintentionally eroded by a process such as etching, but this may not be reflected in the drawings in order to facilitate understanding.

[0034] In addition, in the drawings and the like, the illustration of some components may be omitted in order to make the explanation easier to understand.

[0035] Furthermore, the terms "electrode" and "wiring" used in this specification and elsewhere do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where multiple "electrodes" or "wirings" are integrally formed.

[0036] In addition, in this specification, a "terminal" in an electric circuit refers to a part where a current is input or output, a voltage is input or output, or a signal is received or transmitted. Therefore, a part of a wiring or an electrode may function as a terminal.

[0037] In this specification, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below, and being in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not necessarily mean that electrode B is formed on insulating layer A in direct contact with it, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0038] In addition, the functions of the source and drain are interchangeable depending on operating conditions, such as when transistors of different polarities are used or when the direction of current changes during circuit operation, making it difficult to define which is the source and which is the drain. For this reason, the terms source and drain can be used interchangeably in this specification.

[0039] Furthermore, in this specification, "electrically connected" includes both direct connection and connection via "something that has some kind of electrical effect." Here, "something that has some kind of electrical effect" is not particularly limited as long as it allows electrical signals to be transmitted and received between the connected objects. Therefore, even when the expression "electrically connected" is used, in an actual circuit, there may be no physical connection and only wiring may be extended.

[0040] Furthermore, in this specification and elsewhere, "parallel" refers to, for example, a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases in which the angle is -5° or more and 5° or less. Furthermore, "perpendicular" and "orthogonal" refer to, for example, a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases in which the angle is 85° or more and 95° or less.

[0041] In this specification and elsewhere, when referring to counting values and measurement values, or to objects, methods, and events that can be converted into counting values or measurement values, terms such as "identical," "same," "equal," or "uniform" are intended to include an error of plus or minus 20%, unless otherwise specified.

[0042] Furthermore, voltage often refers to the potential difference between a certain potential and a reference potential (for example, ground potential or source potential). Therefore, voltage and potential can often be used interchangeably. In this specification and elsewhere, unless otherwise specified, voltage and potential can be used interchangeably.

[0043] It should be noted that even when written as "semiconductor," if the conductivity is sufficiently low, it will have the properties of an "insulator." Therefore, it is also possible to use "semiconductor" instead of "insulator." In this case, the boundary between "semiconductor" and "insulator" is vague, and it is difficult to strictly distinguish between the two. Therefore, "semiconductor" and "insulator" described in this specification may be read interchangeably.

[0044] Furthermore, even when written as "semiconductor," if the conductivity is sufficiently high, it will have the properties of a "conductor." Therefore, it is also possible to use "semiconductor" instead of "conductor." In this case, the boundary between "semiconductor" and "conductor" is vague, and it is difficult to strictly distinguish between the two. Therefore, "semiconductor" and "conductor" described in this specification may be read interchangeably.

[0045] Note that ordinal numbers such as "first" and "second" used in this specification are used to avoid confusion between components, and do not indicate any order or ranking, such as the order of processes or stacking. Furthermore, even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims to avoid confusion between components. Furthermore, even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Furthermore, even if a term has an ordinal number in this specification, the ordinal number may be omitted in the claims.

[0046] In this specification and the like, the "on state" of a transistor refers to a state in which the source and drain of the transistor are considered to be electrically short-circuited (also referred to as a "conductive state"). The "off state" of a transistor refers to a state in which the source and drain of the transistor are considered to be electrically disconnected (also referred to as a "non-conductive state").

[0047] In this specification, the term "on-state current" may refer to a current that flows between the source and drain of a transistor when the transistor is on, and the term "off-state current" may refer to a current that flows between the source and drain of a transistor when the transistor is off.

[0048] In this specification, the high power supply potential VDD (hereinafter simply referred to as "VDD," "H potential," or "H") refers to a power supply potential that is higher than the low power supply potential VSS (hereinafter simply referred to as "VSS," "L potential," or "L"). VSS refers to a power supply potential that is lower than VDD. Ground potential (hereinafter simply referred to as "GND" or "GND potential") can also be used as VDD or VSS. For example, when VDD is the ground potential, VSS is a potential lower than the ground potential, and when VSS is the ground potential, VDD is a potential higher than the ground potential.

[0049] Unless otherwise specified, the transistors described in this specification and the like are enhancement-type (normally-off) n-channel field-effect transistors. Therefore, their threshold voltages (also referred to as "Vth") are assumed to be greater than 0 V. Unless otherwise specified, "supplying an H potential to the gate of a transistor" may be synonymous with "turning the transistor on." Unless otherwise specified, "supplying an L potential to the gate of a transistor" may be synonymous with "turning the transistor off."

[0050] In this specification and the like, a gate refers to a gate electrode and a part or all of a gate wiring, and a gate wiring refers to a wiring for electrically connecting the gate electrode of at least one transistor to another electrode or another wiring.

[0051] In this specification, the term "source" refers to a source region, a source electrode, and part or all of a source wiring. The term "source region" refers to a region of a semiconductor layer whose resistivity is equal to or less than a certain value. The term "source electrode" refers to a conductive layer connected to the source region. The term "source wiring" refers to wiring that electrically connects the source electrode of at least one transistor to another electrode or wiring.

[0052] In this specification, the term "drain" refers to a part or all of the drain region, drain electrode, and drain wiring. The term "drain region" refers to a region of the semiconductor layer whose resistivity is equal to or less than a certain value. The term "drain electrode" refers to a conductive layer connected to the drain region. The term "drain wiring" refers to wiring that electrically connects the drain electrode of at least one transistor to another electrode or wiring.

[0053] In addition, in drawings, etc., to make the potential of wiring, electrodes, etc. easier to understand, an "H" indicating an H potential or an "L" indicating an L potential may be written next to the wiring, electrode, etc. Furthermore, wiring, electrodes, etc. where a potential change has occurred may be written with "H" or "L" enclosed in letters. Furthermore, when a transistor is in an off state, an "x" symbol may be written next to the transistor.

[0054] Generally, a "capacitance" has a configuration in which two electrodes face each other via an insulator (dielectric). In this specification, etc., the term "capacitance element" includes the above-mentioned "capacitance." That is, in this specification, etc., the term "capacitance element" includes a configuration in which two electrodes face each other via an insulator, a configuration in which two wires face each other via an insulator, or a configuration in which two wires are arranged via an insulator.

[0055] Furthermore, in this specification and the like, when the same reference numeral is used for multiple elements, and when it is particularly necessary to distinguish between them, the reference numeral may be accompanied by an identifying symbol such as "_1," "_2," "[n]," "[m,n]," etc. For example, the second conductor WWL may be written as conductor WWL[2].

[0056] (Embodiment 1) 1A is a perspective view of a semiconductor device 200 including a memory device 100 and a driver circuit 2000 according to one embodiment of the present invention. The memory device 100 has a three-dimensional stacked structure.

[0057] The drive circuit 2000 includes a WSL driver 2001, a WBL driver 2002, an RSL driver 2003, an RBL driver 2004, a WWL driver 2005, an RWL driver 2006, and a SEL driver 2007. The RBL driver 2004 may have a sense amplifier function. The RSL driver 2003 may be connected to ground.

[0058] The WSL driver 2001 connects to the storage device 100 via the wiring WSL_A. The WBL driver 2002 connects to the storage device 100 via the wiring WBL_A. The RSL driver 2003 connects to the storage device 100 via the wiring RSL_A. The RBL driver 2004 connects to the storage device 100 via the wiring RBL_A. The WWL driver 2005 connects to the storage device 100 via one or both of the wiring WWL_A and the wiring SG_A. The RWL driver 2006 connects to the storage device 100 via the wiring RWL_A. The SEL driver 2007 connects to the storage device 100 via the wiring SEL_A. Furthermore, the wiring BG_A connects to the back gate of the storage device 100.

[0059] The memory device 100 is preferably provided above a layer in which the driver circuit 2000 is provided. Furthermore, as shown in FIG. 1B, the memory device 100 is preferably provided so as to overlap a portion of the driver circuit, since this reduces the area occupied by the semiconductor device 200. When the memory device 100 and the driver circuit are overlapped, the entire driver circuit may overlap with the memory device 100, or may overlap with a portion of the driver circuit. Furthermore, the memory device 100 may overlap with a specific circuit included in the driver circuit. For example, a sense amplifier may be disposed so that the memory device 100 overlaps with the sense amplifier.

[0060] Although one feature of the semiconductor device 200 according to one embodiment of the present invention is that it includes a wiring WSL_A that functions as a write source line and a wiring RSL_A that functions as a read source line, the semiconductor device 200 is not limited to this. The wiring WSL_A and the wiring RSL_A may be connected to each other and connected to a driver circuit that functions as a source line driver.

[0061] Although one feature of the semiconductor device 200 according to one embodiment of the present invention is that it includes a wiring WBL_A that functions as a write bit line and a wiring RBL_A that functions as a read bit line, the semiconductor device 200 is not limited to this. The wiring WBL_A and the wiring RBL_A may be connected to each other and connected to a driver circuit that functions as a bit line driver.

[0062] In FIG. 1A and other figures, arrows indicating the X, Y, and Z directions may be used. The X, Y, and Z directions are perpendicular to each other. In this specification and other figures, one of the X, Y, and Z directions may be referred to as the "first direction" or "first direction." The other may be referred to as the "second direction" or "second direction." The remaining may be referred to as the "third direction" or "third direction." In this specification and other figures, the direction perpendicular to the upper surface of the base 121, which will be described later, is defined as the Z direction.

[0063] Fig. 2 shows a cross section in the XZ plane. Fig. 2 is a cross section of the portion A1-A2 indicated by the dashed dotted line in Fig. 1 and the connection portion between the conductor SEL and the wiring. As mentioned above, some components may be omitted in Figs. 1 and 2 to make the explanation easier to understand.

[0064] <Storage device configuration example> A memory device 100 according to one embodiment of the present invention includes a memory cell array 110. The memory cell array 110 includes a plurality of memory strings 120. The memory strings 120 extend in the Z direction and are arranged in a matrix on the XY plane.

[0065] FIG. 3 shows an example of a cross-sectional structure of a memory string 120 according to one embodiment of the present invention, and FIG. 4 shows a corresponding circuit diagram. The memory string 120 has a configuration in which multiple storage elements MC (also referred to as "memory cells") are connected in series. Although this embodiment illustrates the case in which five storage elements MC are connected in series, the number of storage elements MC included in the memory string 120 is not limited to five. When the number of storage elements MC included in the memory string 120 is n, n may be an integer of 2 or greater.

[0066] The memory string 120 also has a plurality of conductors WWL, a plurality of conductors RWL, a conductor SG, and a conductor SEL. The conductor WWL functions as part of the wiring WWL_A, the conductor RWL functions as part of the wiring RWL_A, the conductor SG functions as part of the wiring SG_A, and the conductor SEL functions as part of the wiring SEL_A. The plurality of conductors WWL and the plurality of conductors RWL are alternately stacked with an insulator 123 interposed therebetween. The conductor SG is provided in a layer below the plurality of conductors WWL and the plurality of conductors RWL. A conductor WSL is provided below the conductor SG, and a conductor RSL is provided below the conductor WSL. The conductor SEL is provided in a layer above the plurality of conductors WWL and the plurality of conductors RWL. A conductor WBL is provided above the conductor SEL, and a conductor RBL is provided above the conductor WBL.

[0067] 3 and 4, the five storage elements MC are denoted as storage elements MC[1] to MC[5]. Note that when describing matters common to the storage elements MC[1] to MC[5], they are simply referred to as "storage element MC." The same applies to other components such as the conductor WWL, the conductor RWL, and the insulator 123.

[0068] The memory string 120 has a transistor STr1 connected to the storage element MC[1] and a transistor STr2 connected to the storage element MC[5].

[0069] The conductors WWL, RWL, SG, and SEL extend in the X-axis direction beyond the memory cell array 110. The conductors WWL, RWL, SG, and SEL are stacked in a stepped manner outside the memory cell array 110 (see FIGS. 1 and 2). On the other hand, the conductors WSL, RSL, WBL, and RBL extend in the Y-axis direction beyond the memory cell array 110 (see FIGS. 1 and 3).

[0070] Figure 5A shows a cross section of the XY plane including the portion B1-B2 indicated by the dashed-dotted line in Figure 3, as seen from the Z direction. Figure 5B shows a cross section of the XY plane including the portion C1-C2 indicated by the dashed-dotted line in Figure 3, as seen from the Z direction. Figure 6 shows an enlarged view of region 105 indicated by the two-dot-dash line in Figure 3. Figure 6 corresponds to a cross section of memory element MC.

[0071] The memory string 120 has a conductor RSL that functions as part of the wiring RSL_A on a base 121, and a conductor WSL that functions as part of the wiring WSL_A on the conductor RSL via an insulator 118. The base 121 may be, for example, an insulator. Also, on the conductor WSL, there are insulator 123[1], conductor SG, insulator 123[2], conductor RWL[1], insulator 123[3], conductor WWL[1], insulator 123[4], conductor RWL[2], insulator 123[5], conductor WWL[2], insulator 123[6], conductor RWL[3], insulator 123[7], conductor WWL[3], insulator 123[8], conductor RWL[4], insulator 123[9], conductor WWL[4], insulator 123

[10] , conductor RWL[5], insulator 123

[11] , conductor WWL[5], insulator 123

[12] , and conductor SEL (see Figure 3). In addition, a conductor WBL that functions as part of the wiring WBL_A is provided on the conductor SEL via an insulator 138, and a conductor RBL that functions as part of the wiring RBL_A is provided on the conductor WBL via an insulator 186.

[0072] The memory string 120 includes an insulator 118, a conductor WSL, an insulator 123 [1], a conductor SG, an insulator 123 [2], a conductor RWL [1], an insulator 123 [3], a conductor WWL [1], an insulator 123 [4], a conductor RWL [2], an insulator 123 [5], a conductor WWL [2], an insulator 123 [6], a conductor RWL [3], an insulator 123 [7], a conductor WWL [3], an insulator 123 [8], a conductor RWL [4], an insulator 123 [9], a conductor WWL [4], an insulator 123

[10] , a conductor RWL [5], an insulator 123

[11] , a conductor WWL [5], an insulator 123

[12] , a conductor SEL, an insulator 138, and a conductor WBL. The insulator 186 and the conductor RBL each have an opening 141 formed by removing a portion thereof.

[0073] The opening 141 extends in the Z direction and reaches the conductors WSL and RSL. In addition, the diameter of a region 142 of the opening 141 that overlaps with the conductor RWL is larger than the diameter of a region 143 that overlaps with the conductor WWL. Therefore, the side surface of the opening 141 has an uneven shape.

[0074] An insulator 124 and a semiconductor 125 are provided along the side surface of the opening 141. The semiconductor 125 has a region that overlaps with the side surface of the opening 141 with the insulator 124 interposed therebetween.

[0075] The memory string 120 also has a conductor 130 extending in the Z direction. The conductor 130 is provided at or near the center of the opening 141. An insulator 129, a semiconductor 127, and an insulator 126 are provided in a region of the conductor 130 that overlaps with a side surface of the opening 141. The semiconductor 127 has a region that overlaps with a side surface of the conductor 130 via the insulator 129. The insulator 126 has a region that overlaps with a side surface of the conductor 130 via the insulator 129 and the semiconductor 127. At the bottom of the opening 141, the semiconductor 127 has a region that is electrically connected to the conductor RSL, and at the top of the opening 141, the semiconductor 127 has a region that is electrically connected to the conductor RBL. At the bottom of the opening 141, the semiconductor 125 has a region that is electrically connected to the conductor WSL, and at the top of the opening 141, the semiconductor 125 has a region that is electrically connected to the conductor WBL. At the bottom of the opening 141, the conductor 130 has a region that overlaps with the conductor RSL via the insulator 129 and the semiconductor 127. In addition, in the region where the conductor RWL and the conductor 130 overlap, the conductor 128 is provided between the semiconductor 125 and the insulator 126.

[0076] Between the conductor WWL and the conductor 130, an insulator 124, a semiconductor 125, an insulator 126, a semiconductor 127, and an insulator 129 are provided in this order from the conductor WWL side (see FIG. 5A). Between the conductor RWL and the conductor 130, an insulator 124, a semiconductor 125, a conductor 128, an insulator 126, a semiconductor 127, and an insulator 129 are provided in this order from the conductor RWL side (see FIG. 5B).

[0077] The memory element MC has a transistor WTr and a transistor RTr (see FIG. 6). The region where the conductor WWL and the conductor 130 overlap functions as the transistor WTr. The conductor WWL functions as the gate electrode of the transistor WTr, and the conductor 130 functions as the back gate electrode of the transistor WTr. A part of the semiconductor 125 functions as a semiconductor layer in which the channel of the transistor WTr is formed. The semiconductor layer in which the channel of the transistor WTr is formed overlaps with the gate electrode (conductor WWL) via a part of the insulator 124. Note that in the present embodiment and the like, an example is shown in which a part of the conductor WWL functions as the gate electrode, but the gate electrode and the conductor WWL may be provided independently and electrically connected to each other.

[0078] The overlapping region of the conductor 128, the conductor RWL, and the conductor 130 functions as the transistor RTr. The conductor RWL functions as the gate electrode of the transistor RTr. The conductor 130 functions as the back gate electrode of the transistor RTr. A portion of the semiconductor 127 functions as a semiconductor layer in which the channel of the transistor RTr is formed. The semiconductor layer in which the channel of the transistor RTr is formed overlaps with the gate electrode (conductor RWL) via portions of the insulator 126, the conductor 128, the semiconductor 125, and the insulator 124. The semiconductor layer in which the channel of the transistor RTr is formed overlaps with the back gate electrode (conductor 130) via a portion of the insulator 129.

[0079] One of the source and drain of transistor STr1 is electrically connected to the semiconductor 125 of transistor WTr. The other of the source and drain of transistor STr1 is electrically connected to the conductor WSL. One of the source and drain of transistor STr2 is electrically connected to the semiconductor 127 of transistor RTr. The other of the source and drain of transistor STr2 is electrically connected to the conductor RBL. One of the source and drain of transistor STr3 is electrically connected to the semiconductor 125 of transistor WTr. The other of the source and drain of transistor STr3 is electrically connected to the conductor WBL. Here, the conductor SEL functions as the gates of transistors STr2 and STr3 (see Figures 3 and 4). A part of the semiconductor 127 functions as a semiconductor layer in which a channel of transistor STr2 is formed, and a part of the semiconductor 125 functions as a semiconductor layer in which a channel of transistor STr3 is formed.

[0080] Here, we will explain the back gate. The gate and back gate are arranged so that they overlap with each other via the channel formation region of the semiconductor layer. The back gate can function in the same way as the gate. In addition, by changing the potential of the back gate, the threshold voltage of the transistor can be changed. Either the gate or the back gate may be called the "first gate" or "first gate," and the other may be called the "second gate" or "second gate."

[0081] The gate and back gate are formed from conductive layers or semiconductor layers with low resistivity, and therefore have the function of preventing external electric fields from acting on the semiconductor layer where the channel is formed (particularly, electrostatic shielding against static electricity). In other words, it is possible to prevent fluctuations in the electrical characteristics of the transistor due to the influence of external electric fields such as static electricity.

[0082] The threshold voltage of the transistor can be controlled by controlling the potential of the back gate, which may be the same potential as the gate, a ground potential (GND potential), or any other potential.

[0083] The semiconductor layers in which the channels of the transistors WTr and RTr are formed can be made of single-crystal semiconductors, polycrystalline semiconductors, microcrystalline semiconductors, amorphous semiconductors, or the like, either singly or in combination. Examples of semiconductor materials that can be used include silicon and germanium. Compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, oxide semiconductors, and nitride semiconductors can also be used. The same applies to the transistors STr1, STr2, and STr3.

[0084] Note that the semiconductor layers used in the transistor may be stacked. When the semiconductor layers are stacked, semiconductors having different crystal states or different semiconductor materials may be used for the respective layers.

[0085] The semiconductor layers used in the transistors WTr, RTr, STr1, STr2, and STr3 are preferably oxide semiconductors containing metal oxide. Transistors using metal oxide in their semiconductor layers have higher field-effect mobility than transistors using amorphous silicon in their semiconductor layers. Furthermore, transistors using polycrystalline silicon in their semiconductor layers may have grain boundaries in their semiconductor layers. Carriers are likely to be captured at the grain boundaries, resulting in a decrease in the on-state current and field-effect mobility of the transistor. On the other hand, as will be described in detail later, oxide semiconductors can achieve a crystal structure with no clear grain boundaries or with very few grain boundaries. Using such oxide semiconductors in the semiconductor layers is advantageous because it enables the realization of transistors with favorable electrical characteristics, such as high on-state current and field-effect mobility.

[0086] In this embodiment, an oxide having a composition of In:Ga:Zn=1:3:4 (atomic ratio) or a composition thereof in the vicinity thereof, an In:Ga:Zn=4:2:3 (atomic ratio) or a composition thereof in the vicinity thereof, an In:Ga:Zn=1:1:1 (atomic ratio) or a composition thereof in the vicinity thereof, or an In:Ga:Zn=1:1:0.5 (atomic ratio) or a composition thereof in the vicinity thereof is used as the oxide semiconductor.

[0087] Furthermore, oxide semiconductors, particularly the crystalline oxide semiconductor CAAC-IGZO, have a characteristic structure in which nanoclusters of a few nanometers (e.g., 1 to 3 nm) are connected together, with their c-axes oriented perpendicular to the surface on which they are formed. This makes it possible to form a crystalline structure in which no clear grain boundaries are visible, even within openings extending in the Z direction.

[0088] In particular, the transistor WTr is preferably a transistor (also referred to as an "OS transistor") that uses an oxide semiconductor, which is a type of metal oxide, for a semiconductor layer in which a channel is formed. The band gap of an oxide semiconductor is 2 eV or more, and therefore the off-state current is significantly small. Here, a node where the conductor 128 is electrically connected to one of the source and drain of the transistor WTr is referred to as a node ND. When an OS transistor is used as the transistor WTr, charge written to the node ND can be held for a long period of time. When an OS transistor is used as a transistor constituting the memory element MC, the memory element MC can be referred to as an "OS memory." The memory string 120 including the memory element MC can also be referred to as an "OS memory." The memory device 100 can also be referred to as an "OS memory."

[0089] OS memory can retain written information for more than one year, or even more than ten years, even if the power supply is cut off, so OS memory can also be considered non-volatile memory.

[0090] Furthermore, since the amount of charge written into the OS memory is unlikely to change over a long period of time, the OS memory can hold not only binary (1-bit) information but also multi-value (multi-bit) information.

[0091] Furthermore, because OS memory writes charge to nodes via transistors, it does not require the high voltages required by conventional flash memory, enabling high-speed write operations. Furthermore, OS memory does not require the erase operation required by flash memory before rewriting data. Furthermore, because no charge is injected or extracted from the floating gate or charge trapping layer, OS memory allows for virtually unlimited data write and read operations. OS memory is less susceptible to degradation than conventional flash memory, making it highly reliable.

[0092] In addition, OS memory does not involve atomic-level structural changes like magnetoresistive random access memory (MRAM) or resistive random access memory (ReRAM), and therefore has better rewrite endurance than magnetoresistive random access memory and resistive random access memory.

[0093] Furthermore, the off-state current of an OS transistor hardly increases even in a high-temperature environment. Specifically, the off-state current hardly increases even in an ambient temperature range of room temperature to 200°C. Furthermore, the on-state current is unlikely to decrease even in a high-temperature environment. A storage device including an OS memory operates stably and has high reliability even in a high-temperature environment. Furthermore, an OS transistor has a high withstand voltage between the source and drain. By using an OS transistor as a transistor constituting a semiconductor device, a semiconductor device that operates stably and has high reliability even in a high-temperature environment can be realized.

[0094] The semiconductor 127 is preferably an n-type semiconductor. Also, the region of the semiconductor 125 that overlaps with the conductor WWL is preferably an i-type or substantially i-type semiconductor. In this case, the transistor WTr is an enhancement type (normally off type) transistor, and the transistor RTr is a depletion type (normally on type) transistor.

[0095] Note that the semiconductor 125 and the semiconductor 127 may be made of the same material or different materials. For example, the semiconductor 125 and the semiconductor 127 may each be an oxide semiconductor. Alternatively, the semiconductor 125 and the semiconductor 127 may each be a semiconductor containing silicon. Alternatively, the semiconductor 125 may be an oxide semiconductor, and the semiconductor 127 may be a semiconductor containing silicon. Alternatively, the semiconductor 125 may be a semiconductor containing silicon, and the semiconductor 127 may be an oxide semiconductor.

[0096] 5A corresponds to the XY plane at or near the center of the transistor WTr, and FIG. 5B corresponds to the XY plane at or near the center of the transistor RTr. In FIGS. 5A and 5B, when the cross-sectional shape of the conductor 130 is circular, the insulator 129 is provided as a concentric layer outside the conductor 130, the semiconductor 127 is provided as a concentric layer outside the insulator 129, the insulator 126 is provided as a concentric layer outside the semiconductor 127, the semiconductor 125 is provided as a concentric layer outside the insulator 126, and the insulator 124 is provided as a concentric layer outside the semiconductor 125. The conductor 128 is provided as a concentric layer between the insulator 126 and the semiconductor 125.

[0097] Furthermore, the cross-sectional shape of the conductor 130 is not limited to a circle. As shown in Fig. 7A, the cross-sectional shape of the conductor 130 may be rectangular. Furthermore, as shown in Fig. 7B, the cross-sectional shape of the conductor 130 may be triangular.

[0098] In addition, in the above example, at the bottom of the memory string 120, the semiconductor 125 is electrically connected to the conductor WSL, and the semiconductor 127 is electrically connected to the conductor RSL, but this embodiment is not limited to this.

[0099] 8, two memory strings adjacent to each other in the Y-axis direction can be electrically connected to form a single memory string 120A. In the memory string 120A, memory strings 120_1 and 120_2 are electrically connected by conductors 119 and 122.

[0100] At the top of the memory string 120_1, the semiconductor 125 and the conductor WSL are electrically connected, and the semiconductor 127 and the conductor RSL are electrically connected. At the top of the memory string 120_2, the semiconductor 125 and the conductor WBL are electrically connected, and the semiconductor 127 and the conductor RBL are electrically connected. At the bottom of the memory strings 120_1 and 120_2, the semiconductors 125 are electrically connected via the conductors 119, and the semiconductors 127 are electrically connected via the conductors 122.

[0101] The memory string 120A includes memory elements MC[1] to MC

[10] arranged from the conductors WSL and RSL toward the conductors WBL and RBL. The memory elements MC[5] and MC[6] are electrically connected via the conductors 119 and 122.

[0102] The memory string 120 can also be called a memory device, and the memory element MC can also be called a memory device.

[0103] [Constituent materials of semiconductor device] Next, constituent materials that can be used for the storage device 100 will be described.

[0104] [substrate] The storage device 100 is provided on a base 121. Substrates that can be used as the base 121 include, for example, insulating substrates, semiconductor substrates, and conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include those having an insulating region within the aforementioned semiconductor substrate, such as an SOI (Silicon On Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Other examples include substrates containing metal nitrides and substrates containing metal oxides. Further, there are substrates in which a conductor or a semiconductor is provided on an insulating substrate, substrates in which a conductor or an insulator is provided on a semiconductor substrate, and substrates in which a semiconductor or an insulator is provided on a conductive substrate. Alternatively, these substrates may be provided with elements. The elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0105] [Insulator] Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, all of which have insulating properties.

[0106] In this specification and the like, the term "oxynitride" refers to a material that contains more oxygen than nitrogen as a main component. For example, "silicon oxynitride" refers to a material that contains more oxygen than nitrogen and that contains silicon, nitrogen, and oxygen. In this specification and the like, the term "nitride oxide" refers to a material that contains more nitrogen than oxygen as a main component. For example, "aluminum nitride oxide" refers to a material that contains more nitrogen than oxygen and that contains aluminum, nitrogen, and oxygen.

[0107] For example, as transistors become more miniaturized and highly integrated, thinner gate insulators can cause problems such as leakage current. Using a high-k material for the gate insulator allows for lower voltage operation of the transistor while maintaining the physical film thickness. On the other hand, using a material with a low dielectric constant for the interlayer insulator can reduce the parasitic capacitance between wiring. Therefore, it is best to select materials based on the insulator's function.

[0108] Furthermore, examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0109] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with voids, and resin.

[0110] Furthermore, the electrical characteristics of an OS transistor can be stabilized by surrounding it with an insulator that has a function of suppressing the permeation of impurities such as hydrogen and oxygen. Examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0111] When an oxide semiconductor is used for the semiconductor 125 and / or the semiconductor 127, the insulator functioning as a gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the semiconductor 125 and / or the semiconductor 127, oxygen vacancies in the semiconductor 125 and / or the semiconductor 127 can be compensated for.

[0112] [conductor] The conductor is preferably a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above metal elements as a component, or an alloy combining the above metal elements. For example, tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0113] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0114] When an oxide semiconductor, which is a type of metal oxide, is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing the metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0115] In particular, a conductive material containing oxygen and a metal element contained in the oxide semiconductor in which a channel is formed is preferably used as a conductor functioning as a gate electrode. Alternatively, a conductive material containing the above-described metal element and nitrogen may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Alternatively, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon is added may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. By using such a material, hydrogen contained in the oxide semiconductor in which a channel is formed may be captured. Alternatively, hydrogen introduced from an external insulator may be captured.

[0116] [Oxide semiconductor] A metal oxide (oxide semiconductor) that functions as a semiconductor is preferably used as the semiconductor 125 and the semiconductor 127. Oxide semiconductors that can be used for the semiconductor 125 and the semiconductor 127 will be described below.

[0117] The oxide semiconductor preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. It is also preferable that it contains aluminum, gallium, yttrium, tin, or the like in addition to these. It may also contain one or more elements selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and the like.

[0118] Here, we consider a case where the oxide semiconductor is an In-M-Zn oxide containing indium, an element M, and zinc. The element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc. Other elements that can be used for the element M include boron, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt. However, there are cases where the element M may be a combination of two or more of the above elements.

[0119] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0120] [Classification of crystal structures] First, classification of crystal structures in oxide semiconductors will be described with reference to Fig. 9A. Fig. 9A is a diagram illustrating classification of crystal structures of oxide semiconductors, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0121] As shown in FIG. 9A, oxide semiconductors are broadly classified into "amorphous," "crystalline," and "crystal." "Amorphous" includes completely amorphous. "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC) (excluding single crystal and polycrystal). "Crystalline" excludes single crystal, polycrystal, and completely amorphous. "Crystalline" includes single crystal and polycrystal.

[0122] The structure within the bold frame in Figure 9A is an intermediate state between "amorphous" and "crystal," and is a structure that belongs to a new boundary region (new crystalline phase). In other words, this structure can be described as a structure that is completely different from the energetically unstable "amorphous" or "crystal."

[0123] The crystalline structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 9B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline." The GIXD method is also known as the thin-film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by GIXD measurement shown in Figure 9B will be simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 9B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 9B is 500 nm.

[0124] As shown in Figure 9B, a clear peak indicating crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ = 31° in the XRD spectrum of the CAAC-IGZO film. As shown in Figure 9B, the peak near 2θ = 31° is asymmetric with respect to the angle at which the peak intensity is detected.

[0125] The crystalline structure of a film or substrate can be evaluated by the diffraction pattern (also called the nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). Figure 9C shows the diffraction pattern of a CAAC-IGZO film. Figure 9C shows a diffraction pattern observed by NBED, in which an electron beam is incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 9C is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. In the nanobeam electron diffraction method, electron diffraction is performed using a probe diameter of 1 nm.

[0126] As shown in Figure 9C, multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0127] [Oxide semiconductor structure] Note that oxide semiconductors may be classified differently from those shown in FIG. 9A when focusing on their crystal structures. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OSs), amorphous oxide semiconductors, and the like.

[0128] Next, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be explained in detail.

[0129] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction can be the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, a crystalline region can also be a region with a uniform lattice arrangement. Furthermore, CAAC-OS has a region where multiple crystalline regions are connected in the ab-plane direction, and the region may have distortion. Note that distortion refers to a location where the lattice arrangement changes between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement in the region where multiple crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor with a c-axis aligned but no clear orientation in the ab-plane direction.

[0130] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be several tens of nm.

[0131] In the In-M-Zn oxide, the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing the element M, zinc (Zn), and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. Note that indium and the element M are mutually substituted. Therefore, the (M, Zn) layer may contain indium. The In layer may contain the element M. The In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0132] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD apparatus, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metallic elements constituting the CAAC-OS.

[0133] Furthermore, for example, in the electron diffraction pattern of the CAAC-OS film, multiple bright spots are observed, and the spots are observed at positions that are point-symmetric with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0134] When the crystalline region is observed from the specific direction, the lattice arrangement within the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. Furthermore, the distortion may have a pentagonal, heptagonal, or other lattice arrangement. In the CAAC-OS, no clear grain boundaries are observed even near the distortion. This indicates that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is thought to be because the CAAC-OS can tolerate distortion due to the lack of close-packed oxygen atom arrangement in the ab-plane direction and the change in interatomic bond distance caused by metal atom substitution.

[0135] A crystal structure with clear grain boundaries is called polycrystalline. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in the on-state current and field-effect mobility of a transistor. Therefore, CAAC-OS, which lacks clear grain boundaries, is one of the crystalline oxides with a crystal structure suitable for use in the semiconductor layer of a transistor. Zn is preferred for use in CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0136] CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to grain boundaries. Furthermore, since the crystallinity of an oxide semiconductor can be reduced by impurities or defects, the CAAC-OS can be said to be an oxide semiconductor with few impurities or defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors with CAAC-OS are heat-resistant and highly reliable. Furthermore, the CAAC-OS is stable even under high temperatures (so-called thermal budget) during the manufacturing process. Therefore, using a CAAC-OS for an OS transistor can increase the flexibility of the manufacturing process.

[0137] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystalline structures. The size of the microcrystalline structures is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore these microcrystalline structures are also called nanocrystalline structures. Furthermore, the nc-OS exhibits no regularity in the crystal orientation between different nanocrystalline structures. Therefore, the entire film lacks orientation. Therefore, depending on the analytical method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structural analysis of an nc-OS film is performed using an XRD system, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Furthermore, when an nc-OS film is subjected to electron diffraction (also known as selected-area electron diffraction) using an electron beam with a probe diameter larger than that of nanocrystalline structures (e.g., 50 nm or larger), a halo-like diffraction pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystals (for example, 1 nm to 30 nm), an electron diffraction pattern can be obtained in which multiple spots are observed within a ring-shaped region centered on the direct spot.

[0138] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a pore or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0139] [Oxide semiconductor composition] Next, the above-mentioned CAC-OS will be described in detail, which relates to the material composition.

[0140] [CAC-OS] CAC-OS is a material structure in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range. Hereinafter, a metal oxide in which one or more metal elements are unevenly distributed and the regions containing the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range, is also referred to as a mosaic or patch state.

[0141] Furthermore, CAC-OS has a mosaic structure in which the material is separated into first and second regions, and the first regions are distributed throughout the film (hereinafter also referred to as a cloud structure). That is, CAC-OS is a composite metal oxide having a structure in which the first and second regions are mixed.

[0142] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0143] Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. The second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. In other words, the first region can be rephrased as a region whose main component is In. The second region can be rephrased as a region whose main component is Ga.

[0144] It should be noted that there are cases where a clear boundary between the first region and the second region cannot be observed.

[0145] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) confirms that the CAC-OS has a structure in which a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed.

[0146] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act in a complementary manner, thereby providing the CAC-OS with a switching function (the ability to turn on and off). In other words, CAC-OS has a conductive function in part of the material and an insulating function in part of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), high field-effect mobility (μ), and good switching behavior can be achieved.

[0147] Oxide semiconductors have a variety of structures, each with different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0148] [Transistor Having an Oxide Semiconductor] Next, a case where the oxide semiconductor is used in a transistor will be described.

[0149] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0150] An oxide semiconductor with a low carrier concentration is preferably used for a channel formation region of a transistor. For example, the carrier concentration of the channel formation region of an oxide semiconductor is preferably 1×10 18 cm -3 Preferably, it is 1×10 or less. 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm-3 It is more preferable that the carrier concentration of the oxide semiconductor film is less than 1000 . Note that in order to reduce the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, an oxide semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. In addition, being highly purified intrinsic or substantially highly purified intrinsic may be referred to as an i-type or substantially i-type.

[0151] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states may also be low.

[0152] Furthermore, charges trapped in the trap states of an oxide semiconductor take a long time to disappear and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0153] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0154] 〔impurities〕 Here, the influence of each impurity in an oxide semiconductor will be described.

[0155] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the concentrations of silicon and carbon in the channel formation region of the oxide semiconductor and the silicon and carbon near the interface with the channel formation region of the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry (SIMS)) are calculated to be 2×10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0156] Furthermore, when an oxide semiconductor contains an alkali metal or alkaline earth metal, defect states may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0157] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the channel formation region of an oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm3 Do the following:

[0158] Furthermore, hydrogen contained in an oxide semiconductor may react with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce the amount of hydrogen in the channel formation region of the oxide semiconductor as much as possible. Specifically, the hydrogen concentration measured by SIMS in the channel formation region of the oxide semiconductor is 1×10 20 atoms / cm 3 Less than 5 x 10 19 atoms / cm 3 less than 1×10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0159] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0160] [Other semiconductor materials] The semiconductor material that can be used for the semiconductor 125 and the semiconductor 127 is not limited to the oxide semiconductors described above. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may also be used for the semiconductor 125 and the semiconductor 127. For example, a semiconductor of an element such as silicon, a compound semiconductor such as gallium arsenide, or a layered material that functions as a semiconductor (also referred to as an atomic layer material, a two-dimensional material, or the like) may also be used as the semiconductor material. In particular, it is preferable to use a layered material that functions as a semiconductor as the semiconductor material.

[0161] In this specification, a layered material is a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals forces. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0162] Layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen. Chalcogen is a general term for elements in Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Chalcogenides also include transition metal chalcogenides and Group 13 chalcogenides.

[0163] It is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor as semiconductor 125 and semiconductor 127. Specific examples of transition metal chalcogenides that can be used as semiconductor 125 and semiconductor 127 include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum tellurium (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten tellurium (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0164] <Example of how to make a memory device> Next, an example of a method for fabricating a memory device according to the present invention will be described with reference to FIGS. 10A to 31C. In each of FIGS. 10A to 31C, A is a top view seen from the Z direction, B is a cross-sectional view of the portion indicated by the dashed line A1-A2 in A, and C is a cross-sectional view of the portion indicated by the dashed line A3-A4 in A. While this fabrication method illustrates an example in which two memory strings 120 each having two (also referred to as "two stages") memory elements MC are fabricated, this embodiment is not limited to this. The memory string 120 may have three or more stages of memory elements MC. For example, the memory string 120 preferably has 32 or more stages, preferably 64 or more stages, more preferably 128 or more stages, and even more preferably 256 or more stages of memory elements MC.

[0165] First, a conductor 122 is formed on a substrate 121 having an insulating surface, and an insulator 132 is formed around the conductor 122 (see FIGS. 10A to 10C).

[0166] Specifically, a conductive film is formed and then processed using lithography to form the conductor 122. Next, an insulating film is formed on the base 121 so as to cover the conductor 122. Next, it is preferable to perform planarization treatment on the insulating film. In the planarization treatment, it is preferable to polish the insulating film until the surface of the conductor 122 is exposed. The insulator 132 can be formed by the above method. However, the method for forming the conductor 122 and the insulator 132 is not limited to this. The insulator 132 may be formed on the base 121, and unnecessary portions of the insulator 132 may be removed to form grooves or openings, and the conductor 122 may be embedded in the grooves or openings. Such a method for forming a conductor is sometimes called a damascene method (single damascene method, dual damascene method). The above method can obtain the structures shown in Figures 10A to 10C.

[0167] The conductor 122 and the insulator 132 can be formed using a sputtering method, a CVD method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like.

[0168] CVD methods can be classified into plasma-enhanced CVD (PECVD), which uses plasma, thermal CVD (TCVD), which uses heat, and photo-CVD (Photo-CVD), which uses light. They can also be further divided into metal CVD (MCVD) and metal-organic CVD (MOCVD), depending on the source gas used.

[0169] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, because the thermal CVD method does not use plasma, it is a film formation method that can minimize plasma damage to the workpiece. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device may become charged up by receiving electric charge from the plasma. In this case, the accumulated electric charge may destroy the wiring, electrodes, elements, etc. included in the semiconductor device. On the other hand, the thermal CVD method, which does not use plasma, does not cause such plasma damage, and therefore can increase the yield of semiconductor devices. Furthermore, because the thermal CVD method does not cause plasma damage during film formation, it can produce films with fewer defects.

[0170] The ALD method includes a thermal ALD method in which the reaction between a precursor and a reactant is carried out using only thermal energy, and a plasma enhanced ALD (PEALD) method in which a plasma-excited reactant is used.

[0171] In addition, the ALD method utilizes the self-regulating properties of atoms to deposit atoms layer by layer, which allows for the formation of ultrathin films, films with high aspect ratios, films with few defects such as pinholes, films with excellent coverage, and films at low temperatures.The PEALD method uses plasma, which can be preferable in some cases because it allows for film formation at even lower temperatures.

[0172] Unlike film formation methods in which particles emitted from a target or the like are deposited, CVD and ALD are film formation methods in which a film is formed by a reaction on the surface of the workpiece. Therefore, these film formation methods are less affected by the shape of the workpiece and have good step coverage. In particular, ALD has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of openings with high aspect ratios. However, because ALD has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as CVD, which has a faster film formation rate.

[0173] The CVD method can control the composition of the resulting film by adjusting the flow rate ratio of the source gases. For example, the CVD method can form a film of any composition by adjusting the flow rate ratio of the source gases. Furthermore, for example, the CVD method can form a film with a continuously changing composition by changing the flow rate ratio of the source gases while forming the film. When forming a film while changing the flow rate ratio of the source gases, the time required for film formation can be shortened by the time required for transportation and pressure adjustment compared to when forming a film using multiple film formation chambers. Therefore, the productivity of semiconductor devices can sometimes be increased.

[0174] Furthermore, in the ALD method, multiple precursors with different compositions can be introduced simultaneously, or multiple precursors with different compositions can be used to deposit films with any composition by controlling the number of cycles for each precursor.

[0175] In lithography, a resist is first exposed through a photomask. The exposed area is then removed or left using a developer to form a resist mask. A conductor, semiconductor, or insulator can then be processed into a desired shape by etching through the resist mask. For example, a resist mask can be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, or EUV (Extreme Ultraviolet) light. An immersion technique can also be used, in which a liquid (e.g., water) is filled between the substrate and the projection lens for exposure. An electron beam or an ion beam can also be used instead of the light described above. When an electron beam or an ion beam is used, a photomask is not required. The resist mask can be removed by dry etching such as ashing, wet etching, or a combination of dry etching and wet etching. When a combination of dry etching and wet etching is used, the wet etching may be performed after the dry etching, or the dry etching may be performed after the wet etching.

[0176] Alternatively, a hard mask made of an insulator or a conductor may be used instead of the resist mask. In the case of using a hard mask, an insulating film or a conductive film that serves as a hard mask material is formed on a conductive film, a resist mask is formed thereon, and the hard mask material is etched, whereby a hard mask having a desired shape can be formed.

[0177] The above processing can be performed by dry etching or wet etching, and processing by dry etching is suitable for fine processing.

[0178] The dry etching apparatus may be a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high frequency power supply to one of the parallel plate electrodes. Alternatively, it may be configured to apply multiple different high frequency power supplies to one of the parallel plate electrodes. Alternatively, it may be configured to apply a high frequency power supply of the same frequency to each of the parallel plate electrodes. Alternatively, it may be configured to apply a high frequency power supply of different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high density plasma source may be used. For example, an inductively coupled plasma (ICP) etching apparatus may be used as the dry etching apparatus having a high density plasma source.

[0179] When a hard mask is used for etching a conductive film, the etching process may be performed after removing the resist mask used for forming the hard mask, or may be performed while leaving the resist mask. In the latter case, the resist mask may be lost during etching. The hard mask may be removed by etching after etching the conductive film. On the other hand, if the material of the hard mask does not affect subsequent processes or can be used in subsequent processes, it is not necessarily necessary to remove the hard mask.

[0180] The conductive film to be the conductor 122 is preferably formed by a sputtering method using a conductive film containing a metal element. Alternatively, the conductive film can also be formed by a CVD method.

[0181] If necessary, the surface of the insulator 132 is preferably subjected to planarization treatment, which can be performed by chemical mechanical polishing (CMP) or reflow.

[0182] The insulator 118 is formed on the conductor 122 and the insulator 132. The insulator 118 can be formed of a material that can be used for the insulator 132 and by a method that can be used for forming the insulator 132.

[0183] A conductor 119 and an insulator 117 are formed on the insulator 118 (see FIGS. 10A to 10C). The conductor 119 and the insulator 117 can be formed using the same materials and methods that can be used to form the conductor 122 and the insulator 132, respectively.

[0184] An insulating film 123A, a conductive film 134A, and a conductive film 136A are alternately stacked over the conductor 119 and the insulator 117. In this embodiment, an example is shown in which the insulating film 123A is formed over the conductor 119 and the insulator 117, the conductive film 134A is formed over the insulating film 123A, the insulating film 123A is formed over the conductive film 134A, and the conductive film 136A is formed over the insulating film 123A (see FIGS. 10A to 10C). The conductive film 134A, the conductive film 136A, and the insulating film 123A can be formed by a CVD method. Alternatively, a sputtering method may be used.

[0185] The conductor 122, the conductor 119, the conductive film 134A, and the conductive film 136A can be made of a conductive material such as silicon doped with impurities or a metal. Because the conductor 136 needs to be selectively etched relative to the conductors 119 and 134 in a later step, the conductive film 136A is preferably made of a different material from the conductors 122, 119, and 134A. The conductors 122, 119, and 134A may be made of the same material or different materials. When silicon doped with impurities is used for the conductor 122, the conductor 119, the conductive film 134A, or the conductive film 136A, amorphous silicon or polysilicon can be used. Furthermore, p-type impurities or n-type impurities can be used as the impurities added to the silicon. As a conductive material containing silicon, a silicide containing titanium, cobalt, or nickel can be used for the conductor 122, the conductive film 134A, or the conductive film 136A. When a metal material is used for the conductor 122, the conductive film 134A, or the conductive film 136A, a material containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, and the like can be used.

[0186] Alternatively, one of the conductive films 134A and 136A may be a dummy layer. The dummy layer is preferably made of a material that can be selectively etched with respect to the conductor 122, the insulator 118, the conductor 119, the insulator 123, and the other of the conductive films 134A and 136A, and for example, silicon nitride or silicon nitride oxide can be used. In a later step, the dummy layer is removed and a conductor is formed in the region where the dummy layer has been removed, thereby forming one of the conductor 134 and the conductor 136.

[0187] For the insulators 132, 118, and 117, and the insulating film 123A, an insulating oxide, nitride, oxynitride, nitride oxide, metal oxide, metal oxynitride, metal nitride oxide, or the like can be used. Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide or resin having pores, aluminum oxide, gallium oxide, hafnium oxide, zirconium oxide, oxide containing aluminum and hafnium, oxynitride containing aluminum and hafnium, oxide containing silicon and hafnium, oxynitride containing silicon and hafnium, nitride containing silicon and hafnium, or the like can be used.

[0188] In a later step, the conductor 136 needs to be selectively etched with respect to the conductors 137, 134, 119, the insulator 138, and the insulator 123. Therefore, the conductive film 136A is preferably made of a material that can be selectively etched with respect to the conductive film 134A, the conductive film 134A, the insulator 138, and the insulating film 123A. For example, the conductive film 136A is preferably made of a different material from the conductive film 134A, and the insulator 138 and the insulating film 123A are preferably made of silicon oxide or silicon oxynitride.

[0189] Although the present embodiment has shown an example in which six insulating films 123A, three conductive films 134A, and two conductive films 136A are formed, the number of stacked layers is not limited to this. Each of these layers can be formed depending on the desired performance of the semiconductor device. If the number of stacked conductive films 134A is m (m is an integer of 2 or more), the number of stacked insulating films 123A is 2×m, and the number of stacked conductive films 136A is m−1. For example, m can be 33 or more, preferably 65 or more, more preferably 129 or more, and even more preferably 257 or more.

[0190] A conductive film 137A is formed on the uppermost insulating film 123A, and an insulating film 138A is formed on the conductive film 137A. The conductive film 137A can be formed using the same method and from the same material as the conductive film 134A. The insulating film 138A can be formed using the same method and from the same material as the insulating film 123A.

[0191] Next, the insulating film 138A, the conductive film 137A, the insulating film 123A, the conductive film 134A, and the conductive film 136A are processed to form the stepped insulator 138B, the conductor 137B, the insulator 123B, the conductor 134B, and the conductor 136B as shown in FIG. 11B (see FIGS. 11A to 11C). In processing the insulating film 138A, the conductive film 137A, the insulating film 123A, the conductive film 134A, and the conductive film 136A, etching of the insulating film 138A, the conductive film 137A, the insulating film 123A, the conductive film 134A, and the conductive film 136A and slimming of the mask are alternately performed, thereby forming the stepped insulator 138B, the conductor 137B, the insulator 123B, the conductor 134B, and the conductor 136B.

[0192] Next, the insulator 150 is formed (see FIGS. 11A to 11C). The insulator 150 can be formed using a CVD method. The insulator 150 is preferably subjected to a planarization process using a CMP method or a reflow method.

[0193] Next, grooves are formed by processing the insulator 150, the insulator 138B, the conductor 137B, the insulator 123B, the conductor 134B, and the conductor 136B to obtain the insulator 138, the conductor 137, the insulator 123, the conductor 134, and the conductor 136 (see FIGS. 12A to 12C).

[0194] If a dummy layer is used for either the conductive film 134A or the conductive film 136A, the dummy layer may be removed from the side surface exposed by the above processing, and a conductor may be formed in the region where the dummy layer has been removed. At this time, if a conductor is also formed inside the trench, this conductor is removed. Note that the removal of the dummy layer and the formation of the conductor may be performed in a later process.

[0195] Next, an insulator 152 is formed so as to fill the groove portion (see FIGS. 12A to 12C). The insulator 152 can be formed using a CVD method or an ALD method. In particular, the ALD method is preferable because it allows a film of uniform thickness to be formed even in grooves or openings with a large aspect ratio. Alternatively, the insulator 152 may be formed by combining the ALD method and the CVD method. The insulator 152 is preferably planarized using a CMP method or a reflow method.

[0196] Next, conductor 184 and insulator 185 are formed on insulator 138, insulator 150, and insulator 152 (see FIGS. 13A to 13C). Conductor 184 and insulator 185 can be formed using a material that can be used for conductor 122 and insulator 132, respectively, and a method that can be used for forming conductor 122 and insulator 132.

[0197] Next, an insulator 186 is formed on the conductor 184 and the insulator 185 (see FIGS. 14A to 14C). The insulator 186 can be formed from a material that can be used for the insulator 132 and by a method that can be used for forming the insulator 132.

[0198] Next, a conductor 187 and an insulator 188 are formed on the insulator 186 (see FIGS. 14A to 14C). The conductor 187 and the insulator 188 can be formed using a material that can be used for the conductor 122 and the insulator 132, respectively, and a method that can be used for forming the conductor 122 and the insulator 132.

[0199] Next, an insulator 189 is formed on the conductor 187 and the insulator 188 (see FIGS. 14A to 14C). The insulator 189 can be formed of a material that can be used for the insulator 132 and by a method that can be used for forming the insulator 132.

[0200] Next, a mask is formed on insulator 189, and insulator 189, conductor 187, insulator 186, conductor 184, insulator 138, conductor 137, insulator 123, conductor 134, and conductor 136 are processed using lithography to form a first opening to expose conductor 119 (see Figures 15A to 15C).

[0201] Here, when a dummy layer is used for either the conductor 134 or the conductor 136, the dummy layer may be removed from the side surface exposed by the above processing, and the conductor may be formed in the region from which the dummy layer has been removed. At this time, if a conductor is also formed inside the first opening, this conductor is removed.

[0202] Next, isotropic etching is performed on the conductor 136 to widen the diameter of the opening of the conductor 136 (see FIGS. 16A to 16C). This process makes the diameter of the opening of the conductor 136 larger than the diameters of the openings of the insulator 138, the conductor 137, the insulator 123, and the conductor 134. It can also be said that the conductor 136 has a recess on the side surface of the insulator 138, the conductor 137, the insulator 123, or the conductor 134 located above or below it. For this type of processing, isotropic etching by dry etching using gas, radicals, plasma, or the like, or isotropic etching by wet etching using a liquid can be used. The liquid used in wet etching is sometimes called an etchant. When isotropic etching is performed using dry etching, gas, radicals, plasma, or the like containing at least one of chlorine, bromine, and fluorine can be used. It is preferable to perform isotropic etching without removing the mask used to form the first opening. The first opening obtained by the above process corresponds to the opening 141 shown in FIG.

[0203] Next, the insulating film 124A is formed on the insulator 189 and inside the first opening (see FIGS. 17A to 17C). Note that, although not shown, the insulating film 124A may have a layered structure. The insulating film 124A can be formed by a CVD method or an ALD method. In particular, the ALD method is preferable because it allows a film of uniform thickness to be formed even in grooves or openings with a high aspect ratio. In particular, the PEALD method may be preferable because it uses plasma, allowing film formation at a lower temperature. Alternatively, the insulating film 124A may be formed by combining the ALD method and the CVD method. When the insulating film 124A has a layered structure, each insulating film may be formed using the same film formation apparatus or different film formation apparatuses.

[0204] The insulating film 124A formed by the above method has good coverage, and can be formed even in the recessed portion of the conductor 136. That is, the insulating film 124A can be formed so as to contact not only the side surfaces of the insulator 123, the conductor 134, and the conductor 136, but also part of the upper surface and part of the lower surface of the insulator 123.

[0205] Next, the insulating film 124A formed on the bottom of the first opening is removed to obtain the insulator 124B. Anisotropic etching is preferably used to remove the insulating film 124A. At this time, the insulating film 124A on the insulator 189 is also removed, so that the insulator 124B is provided only on the sidewall of the first opening (see FIGS. 18A to 18C). By removing the insulating film 124A on the bottom of the first opening, the conductor 119 is exposed again.

[0206] Next, in the XY plane shown in FIGS. 18A to 18C, the insulator 124B overlapping with the conductor 184 and the conductor 187 is removed. To remove the insulator 124B, first, a material 180 (also called a sacrificial layer) that can be easily removed in a subsequent process is formed so as to fill the first opening, and then removed to a desired depth within the first opening by etching or the like (see FIGS. 19A to 19C). Next, using the material 180 as a mask, the insulator 124B exposed by the etching is removed, thereby obtaining the insulator 124 (see FIGS. 20A to 20C). After the insulator 124B is removed, the material 180 is removed.

[0207] Next, a semiconductor film 125A and a conductive film 128A are formed over the insulator 189 and inside the first opening (see FIGS. 21A to 21C). The semiconductor film 125A is preferably provided so as to be in contact with at least the conductor 119, the insulator 124, and the conductor 184 inside the first opening.

[0208] The semiconductor film 125A can be formed using a CVD method or an ALD method. The ALD method is particularly preferable because it allows for the formation of a film of uniform thickness even in grooves or openings with a high aspect ratio. The PEALD method, in particular, may be preferable because it allows for film formation at lower temperatures by using plasma. Alternatively, the semiconductor film 125A may be formed by combining an ALD method and a CVD method. The semiconductor film 125A is preferably an oxide semiconductor having a CAAC structure. When the semiconductor film 125A is an oxide semiconductor having a CAAC structure, the c-axis of the semiconductor film 125A is aligned in the normal direction to the formation surface within the first opening. In this case, the c-axis of the semiconductor film 125A located on the side surfaces of the insulator 138, the conductor 137, the insulator 123, the conductor 134, and the conductor 136, via the insulator 124, is aligned from the formation surface toward the axis 178 shown in FIGS. 21B and 21C. The axis 178 can be referred to as the central axis of the first opening. As a result, the c-axis of the semiconductor 125 located above is oriented toward the axis 178 from the surface on which it is formed.

[0209] Here, when a metal oxide is formed as the semiconductor film 125A using the ALD method, it is preferable to form an In—Ga—Zn oxide using a precursor containing indium, a precursor containing gallium, and a precursor containing zinc.

[0210] Examples of precursors containing indium include triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate), cyclopentadienylindium, and indium(III) chloride. Examples of precursors containing gallium include trimethylgallium, triethylgallium, tris(dimethylamido)gallium, gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate), dimethylchlorogallium, diethylchlorogallium, and gallium(III) chloride. Examples of precursors containing zinc include dimethylzinc, diethylzinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), and zinc chloride.

[0211] The conductive film 128A only needs to be formed to fill the recessed portion of the conductor 136 via the insulator 124 and the semiconductor film 125A, and does not necessarily need to fill the entire inside of the first opening. The conductive film 128A can be formed using a CVD method or an ALD method. The ALD method is particularly preferred because it allows a film of uniform thickness to be formed even in grooves or openings with a high aspect ratio. In particular, the PEALD method may be preferred because it uses plasma, allowing film formation at a lower temperature. Alternatively, the conductive film 128A may be formed by combining the ALD method and the CVD method.

[0212] Next, the conductive film 128A is processed to form the conductor 128 (see FIGS. 22A to 22C). The conductive film 128A can be processed by isotropic etching or anisotropic etching. When forming the conductive film 128A, if the conductive film 128A fills the recess and does not completely fill the first opening, as shown in FIGS. 21A to 21C, it is preferable to use isotropic etching to process the conductive film 128A. On the other hand, if the conductive film 128A is formed so as to fill the recess and the first opening, it is preferable to use anisotropic etching. By the above processing, the conductor 128 can be formed inside the recess.

[0213] Next, a material 181 is formed inside the first opening (see FIGS. 22A to 22C). The material 181 is used as a sacrificial layer for protecting the semiconductor film 125A when the semiconductor film 125A, the conductor 119, the insulator 118, and the like are processed. The material 181 is preferably formed using an insulating material; however, one embodiment of this embodiment is not limited thereto. The material 181 may also be a conductive material. The material 181 is a material that can be used for the insulating film 124A and can be formed using a method that can be used for forming the insulating film 124A.

[0214] Next, it is preferable to increase the resistance of a part of the semiconductor film 125A using the conductor 128 as a mask to form a high-resistance region (I-type region). The high-resistance region can be formed by irradiating the semiconductor film 125A with microwaves to remove hydrogen contained in the semiconductor film 125A. Furthermore, microwave irradiation in an oxygen-containing atmosphere is preferable because oxygen is supplied to the semiconductor film 125A. In this embodiment, part of the semiconductor film 125A is irradiated with microwaves in an oxygen- and argon-containing atmosphere to increase the resistance of a first region of the semiconductor film 125A that is not covered with the conductor 128.

[0215] Here, heat treatment may be performed. The heat treatment is preferably performed in a nitrogen-containing atmosphere at a temperature of 200°C to 500°C, preferably 300°C to 400°C. The atmosphere in which the heat treatment is performed is not limited to the above, and the heat treatment may be performed in an atmosphere containing at least one of nitrogen, oxygen, and argon. The heat treatment may be performed in a reduced pressure atmosphere or an atmospheric pressure atmosphere.

[0216] The heat treatment reduces the resistance of a second region of the semiconductor film 125A in contact with the conductor 128, thereby forming a low-resistance region (n-type region). By performing heat treatment while the semiconductor film 125A and the conductor 128 are in contact with each other, a metal compound layer containing a metal element of the conductor 128 and a component of the semiconductor film 125A may be formed at the interface between the conductor 128 and the semiconductor film 125A. Forming the metal compound layer is preferable because it reduces the resistance of the semiconductor film 125A in the region in contact with the conductor 128. Furthermore, the conductor 128 may absorb oxygen contained in the semiconductor film 125A. By performing heat treatment while the semiconductor film 125A and the conductor 128 are in contact with each other, the resistance of the semiconductor film 125A can be further reduced. The heat treatment may be performed before the microwave treatment. The second region, which has been made to have a low resistance by the heat treatment, is covered with the conductor 128 and is therefore not affected by the microwaves, and can maintain a low resistance value even after the microwave treatment.

[0217] The carrier concentration of the first region after the microwave treatment and heat treatment was 1×10 18 / cm 3 Less than 1 x 10, preferably 17 / cm 3 or less, more preferably 1×10 16 / cm 3 The carrier concentration of the second region is preferably 1×10 or less. 18 / cm 3 More than 1×10 19 / cm 3 More preferably, 1×10 20 / cm 3 It is preferable that this is equal to or greater than this.

[0218] The step of increasing the resistance of the semiconductor film 125A is not limited to being performed after the formation of the material 181. The process may be performed before the formation of the material 181. The process may be performed before the formation of the insulating film 126A, which will be described later, or after the formation of the insulating film 126A.

[0219] Next, the material 181, the semiconductor film 125A, the conductor 119, and the insulator 118 formed on the bottom of the first opening are removed to obtain the semiconductor 125B. Anisotropic etching is preferably used to remove the semiconductor film 125A, the material 181, the conductor 119, and the insulator 118. At this time, the semiconductor film 125A and the material 181 on the insulator 189 are also removed, so that the semiconductor 125B is provided only on the sidewall of the first opening (see FIGS. 23A to 23C). By removing the semiconductor film 125A, the material 181, the conductor 119, and the insulator 118 on the bottom of the first opening, the conductor 122 is exposed.

[0220] Next, in the XY plane shown in Figures 24A to 24C, material 181 overlapping with conductor 187 and semiconductor 125B are removed. To remove semiconductor 125B, first, material 182 (also called a sacrificial layer) that can be easily removed in a subsequent process is formed so as to fill the first opening, and then removed to a desired depth within the first opening by etching or the like (see Figures 24A to 24C). Next, material 182 is used as a mask to remove material 181 and semiconductor 125B exposed by the etching, thereby obtaining semiconductor 125 (see Figures 24A to 24C). After semiconductor 125B is removed, material 182 and material 181 are removed.

[0221] Next, the insulating film 126A is formed on the insulator 189 and inside the first opening (see FIGS. 25A to 25C). Although not shown, the insulating film 126A may have a layered structure. The insulating film 126A can be formed by a CVD method or an ALD method. The ALD method is particularly preferable because it allows a film of uniform thickness to be formed even in grooves or openings with a high aspect ratio. The PEALD method is particularly preferable in some cases because it uses plasma, allowing film formation at lower temperatures. Alternatively, the insulating film 126A may be formed by combining the ALD method and the CVD method. When the insulating film 126A has a layered structure, each insulating film may be formed using the same film formation apparatus or different film formation apparatuses.

[0222] Next, the insulating film 126A formed on the bottom of the first opening is removed to obtain the insulator 126B. Anisotropic etching is preferably used to remove the insulating film 126A. At this time, the insulating film 126A on the insulator 189 is also removed, so that the insulator 126B is provided only on the sidewall of the first opening (see FIGS. 26A to 26C). By removing the insulating film 126A on the bottom of the first opening, the conductor 122 is exposed again.

[0223] Next, in the XY plane shown in Figures 27A to 27C, the insulator 126B overlapping with the conductor 187 is removed. To remove the insulator 126B, first, a material 183 (also called a sacrificial layer) that can be easily removed in a subsequent process is formed so as to fill the first opening, and then removed to a desired depth within the first opening by etching or the like (see Figures 27A to 27C). Next, using the material 183 as a mask, the insulator 126B exposed by the etching is removed, thereby obtaining the insulator 126 (see Figures 27A to 27C). After the insulator 126B is removed, the material 183 is removed.

[0224] Next, the semiconductor film 127A is formed in the first opening so as to be in contact with the conductor 122 (see FIGS. 28A to 28C). The semiconductor film 127A can be formed by a CVD method or an ALD method. In particular, the ALD method is preferable because a film with a uniform thickness can be formed even in a groove or an opening with a high aspect ratio. In particular, the PEALD method may be preferable because it enables film formation at a lower temperature by using plasma. Alternatively, the semiconductor film 127A may be formed by combining the ALD method and the CVD method. In this case, the semiconductor film 127A is preferably formed so as to be in contact with the conductor 187. Furthermore, the semiconductor film 127A is preferably an oxide semiconductor having a CAAC structure. When the semiconductor film 127A is an oxide semiconductor having a CAAC structure, the c-axis of the semiconductor film 127A is aligned in the normal direction to the formation surface inside the first opening. At this time, the c-axis of semiconductor film 127A located on the side surface of the first opening is oriented from the formation surface toward axis 178 shown in Figures 28B and 28C. As a result, the c-axis of semiconductor 127 located above is oriented from the formation surface toward axis 178.

[0225] Here, when a metal oxide is formed as the semiconductor film 127A by the ALD method, it is preferable to form an In—Ga—Zn oxide using a precursor containing indium, a precursor containing gallium, and a precursor containing zinc.

[0226] Examples of precursors containing indium include triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate), cyclopentadienylindium, and indium(III) chloride. Examples of precursors containing gallium include trimethylgallium, triethylgallium, tris(dimethylamido)gallium, gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate), dimethylchlorogallium, diethylchlorogallium, and gallium(III) chloride. Examples of precursors containing zinc include dimethylzinc, diethylzinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), and zinc chloride.

[0227] Next, the semiconductor film 127A formed on the insulator 189 is removed. To remove the semiconductor film 127A, first, a material 179 (also called a sacrificial layer) that can be easily removed in a later process is formed inside the first opening so as to be embedded inside the semiconductor film 127A. Next, the semiconductor film 127A is removed using the material 179 as a mask, thereby obtaining the semiconductor 127 (see Figures 29A to 29C). The semiconductor film 127A can be removed by etching, CMP, or the like. When removing the semiconductor film 127A by etching, either dry etching or wet etching may be used. After removing the semiconductor film 127A, the material 179 is removed.

[0228] Next, the insulator 129 is formed on the insulator 189 and inside the semiconductor 127, and the conductor 130 is formed inside the insulator 129 (see FIGS. 30A to 30C). The insulator 129 and the conductor 130 can be formed by a CVD method or an ALD method. The CVD method or the ALD method is preferable because it allows a film of uniform thickness to be formed even in a groove or an opening with a high aspect ratio. Alternatively, the ALD method and the CVD method may be combined. Different film formation methods and film formation apparatuses may be used for each film to be formed. For example, the insulator 129 can be made of a material that can be used for the insulating film 124A, and a method that can be used for forming the insulating film 124A can be used. The conductor 130 can be made of a material that can be used for the conductive film 128A, and a method that can be used for forming the conductive film 128A can be used.

[0229] Here, the semiconductor 127 may be subjected to resistance-increasing treatment similar to that performed on the semiconductor film 125A. When the semiconductor 127 is subjected to resistance-increasing treatment, the resistance-increasing treatment is preferably performed before forming the conductor 130 or before forming the insulator 129. When the resistance of the first region of the semiconductor 125 can also be increased by performing resistance-increasing treatment on the semiconductor film 127A, the resistance-increasing treatment in the previous step may be omitted.

[0230] Next, heat treatment is performed. The heat treatment is preferably performed in a nitrogen-containing atmosphere at a temperature of 200°C to 500°C, preferably 300°C to 400°C. The atmosphere in which the heat treatment is performed is not limited to the above, and the heat treatment may be performed in an atmosphere containing at least one of nitrogen, oxygen, and argon. The heat treatment may be performed in a reduced pressure atmosphere or an atmospheric pressure atmosphere.

[0231] The conductor 130 can be obtained by forming a conductive film on and inside the insulator 129 and then removing the conductive film by a CMP method or the like until the surface of the insulator 129 is exposed (see FIGS. 30A to 30C). Note that the heat treatment described above may be performed after the conductor 130 is formed.

[0232] Next, the insulator 156 is formed over the conductor 130 and the insulator 129 (see FIGS. 31A to 31C). The insulator 156 can be formed by a CVD method, an ALD method, a sputtering method, or the like.

[0233] Next, insulators 156, 129, 189, 188, 186, 185, 138, 150, and 123 are processed using lithography to form second openings so as to expose conductors 134, 136, 130, and 137. The second openings are formed for conductors 134 and 136, which are formed in a stepped pattern (see FIGS. 31A to 31C). Although not shown, openings exposing conductors 184 and 187 and openings exposing conductors 119 and 122 may be formed in the above process.

[0234] Next, conductor 161, which is electrically connected to conductor 134, conductor 162, which is electrically connected to conductor 136, conductor 163, which is electrically connected to conductor 130, and conductor 164, which is electrically connected to conductor 137, are formed so as to fill the second opening (see FIGS. 31A to 31C). Conductors 161, 162, 163, and 164 can be formed using a CVD method or an ALD method. ALD is particularly preferred because it allows for the formation of a film with a uniform thickness even in grooves and openings with a high aspect ratio. Alternatively, the conductors may be formed by combining an ALD method and a CVD method. Conductors 161, 162, 163, and 164 may each have a multi-layer structure consisting of multiple layers. The conductors 161, 162, 163, and 164 can be formed by forming a conductive film on the insulator 156 and inside the second opening, and then removing unnecessary conductive film by a CMP method or the like. Although not shown, conductors electrically connected to the conductors 184, 187, 119, and 122 may be formed in the above steps.

[0235] Next, conductor 171 electrically connected to conductor 161, conductor 172 electrically connected to conductor 162, conductor 173 electrically connected to conductor 163, and conductor 174 electrically connected to conductor 164 are formed (see Figures 31A to 31C). Conductors 171, 172, 173, and 174 can be formed by forming a conductive film on insulator 156 and processing it using lithography. This processing can be performed using dry etching or wet etching. Processing using dry etching is suitable for fine processing.

[0236] Conductor 171, conductor 161, and conductor 134 can function as conductor SG or conductor WWL. Conductor 172, conductor 162, and conductor 136 can function as conductor RWL. Conductor 173, conductor 163, and conductor 130 can function as conductor BG. Conductor 174, conductor 164, and conductor 137 can function as conductor SEL. Conductor 184 can function as conductor WBL. Conductor 187 can function as conductor RBL. Through the above steps, it is possible to manufacture a transistor STr1 having the semiconductor 125 functioning as a channel formation region and the conductor 134 functioning as a gate, a transistor STr2 having the semiconductor 127 functioning as a channel formation region and the conductor 137 functioning as a gate, a transistor STr3 having the semiconductor 125 functioning as a channel formation region and the conductor 137 functioning as a gate, a transistor WTr having the semiconductor 125 functioning as a channel formation region and the conductor 134 functioning as a gate, and a transistor RTr having the semiconductor 127 functioning as a channel formation region, the conductor 136 functioning as a gate, the conductor 130 functioning as a back gate, and the conductor 128 between the semiconductor 127 and the conductor 136. In addition, it is possible to manufacture a memory device including the transistor STr1, the transistor STr2, the transistor STr3, the transistor WTr, and the transistor RTr.

[0237] <Configuration example of film formation equipment> 32A and 32B, the configuration of a film formation apparatus 4000 will be described as an example of an apparatus capable of forming a film using the ALD method. Fig. 32A is a schematic diagram of a multi-chamber type film formation apparatus 4000, and Fig. 32B is a cross-sectional view of an ALD apparatus that can be used for the film formation apparatus 4000.

[0238] The film formation apparatus 4000 includes a loading / unloading chamber 4002, a loading / unloading chamber 4004, a transfer chamber 4006, a film formation chamber 4008, a film formation chamber 4009, a film formation chamber 4010, and a transfer arm 4014. The loading / unloading chamber 4002, the loading / unloading chamber 4004, and the film formation chambers 4008 to 4010 are each independently connected to the transfer chamber 4006. This allows continuous film formation in the film formation chambers 4008 to 4010 without exposure to the atmosphere, preventing impurities from being mixed into the film. Furthermore, contamination of the interface between the substrate and the film and the interface between each film is reduced, resulting in clean interfaces.

[0239] In addition, it is preferable that the loading / unloading chamber 4002, the loading / unloading chamber 4004, the transfer chamber 4006, and the film forming chambers 4008 to 4010 are filled with an inert gas (nitrogen gas, etc.) with a controlled dew point to prevent moisture from adhering, and it is desirable to maintain a reduced pressure.

[0240] In addition, an ALD apparatus can be used in the film formation chambers 4008 to 4010. Also, a configuration may be adopted in which a film formation apparatus other than the ALD apparatus is used in any one of the film formation chambers 4008 to 4010. Examples of the film formation apparatus that can be used in the film formation chambers 4008 to 4010 include a sputtering apparatus, a plasma CVD (PECVD: Plasma Enhanced CVD) apparatus, a thermal CVD (TCVD: Thermal CVD) apparatus, a photo CVD apparatus, a metal CVD (MCVD: Metal CVD) apparatus, a metal organic CVD (MOCVD: Metal Organic CVD) apparatus, and the like. Further, a device having a function other than the film formation apparatus may be provided in any one or more of the film formation chambers 4008 to 4010. Examples of such a device include a heating device (typically, a vacuum heating device), a plasma generation device (typically, a microwave plasma generation device), and the like.

[0241] For example, when the film formation chamber 4008 is an ALD apparatus, the film formation chamber 4009 is a PECVD apparatus, and the film formation chamber 4010 is a metal CVD apparatus, a metal oxide can be formed in the film formation chamber 4008, an insulating film that functions as a gate insulating film can be formed in the film formation chamber 4009, and a conductive film that functions as a gate electrode can be formed in the film formation chamber 4010. At this time, the metal oxide, the insulating film thereon, and the conductive film thereon can be continuously formed without exposing them to the atmosphere.

[0242] Also, although the film formation apparatus 4000 is configured to include the loading / unloading chamber 4002, the loading / unloading chamber 4004, and the film formation chambers 4008 to 4010, the present invention is not limited thereto. The film formation apparatus 4000 may be configured to have four or more film formation chambers. Further, the film formation apparatus 4000 may be a single wafer type or a batch type in which a plurality of substrates are film-formed collectively.

[0243] <ALD apparatus> Next, the configuration of an ALD apparatus that can be used in the film formation apparatus 4000 will be described with reference to Fig. 32B. The ALD apparatus includes a film formation chamber (chamber 4020), raw material supply units 4021 (raw material supply units 4021a and 4021b), raw material supply unit 4031, high-speed valves 4022 (high-speed valves 4022a and 4022b) that serve as introduction amount controllers, raw material inlets 4023 (raw material inlets 4023a and 4023b), raw material inlets 4033, raw material outlet 4024, and exhaust unit 4025. Raw material inlets 4023a, 4023b, and 4033 installed in chamber 4020 are connected to raw material supply units 4021a, 4021b, and 4031, respectively, via supply pipes and valves, and raw material outlet 4024 is connected to exhaust unit 4025 via an exhaust pipe, valve, and pressure regulator.

[0244] Furthermore, as shown in FIG. 32B, by connecting a plasma generator 4028 to the chamber 4020, film formation can be performed by the plasma ALD method in addition to the thermal ALD method. The plasma generator 4028 is preferably an ICP-type plasma generator using a coil 4029 connected to a high-frequency power source. The high-frequency power source can output power having a frequency of 10 kHz to 100 MHz, preferably 1 MHz to 60 MHz, and more preferably 10 MHz to 60 MHz. For example, it can output power having a frequency of 13.56 MHz or 60 MHz. The plasma ALD method allows film formation without reducing the film formation rate even at low temperatures, so it is suitable for use in single-wafer film formation equipment with low film formation efficiency.

[0245] A substrate holder 4026 is placed inside the chamber, and a substrate 4030 is placed on the substrate holder 4026. The substrate holder 4026 may be provided with a mechanism for applying a constant potential or high frequency. Alternatively, the substrate holder 4026 may be floating or grounded. A heater 4027 is provided on the outer wall of the chamber, and is capable of controlling the temperature of the interior of the chamber 4020, the substrate holder 4026, the surface of the substrate 4030, and the like. The heater 4027 can preferably control the temperature of the surface of the substrate 4030 to a temperature of 100°C or higher and 500°C or lower, preferably 200°C or higher and 400°C or lower, and the temperature of the heater 4027 itself can preferably be set to a temperature of 100°C or higher and 500°C or lower.

[0246] In the raw material supply units 4021a, 4021b, and 4031, a raw material gas is formed from a solid raw material or a liquid raw material by a vaporizer, a heating means, etc. Alternatively, the raw material supply units 4021a, 4021b, and 4031 may be configured to supply a gaseous raw material gas.

[0247] 32B shows an example in which two raw material supply units 4021 and one raw material supply unit 4031 are provided, but this embodiment is not limited to this. One, or three or more raw material supply units 4021 may be provided. Also, two or more raw material supply units 4031 may be provided. Also, high-speed valves 4022a and 4022b can be precisely controlled in terms of time, and are configured to control the supply of raw material gas supplied from raw material supply unit 4021a and raw material supply unit 4021b.

[0248] 32B, a substrate 4030 is loaded onto a substrate holder 4026, and the chamber 4020 is sealed. Then, the heater 4027 heats the substrate 4030 to a desired temperature (for example, 100°C to 500°C, preferably 200°C to 400°C). A thin film is formed on the substrate surface by repeating the following steps: supplying a source gas from a source supply unit 4021a, exhausting the gas by an exhaust unit 4025, and supplying a source gas from a source supply unit 4031, and exhausting the gas by an exhaust unit 4025. Furthermore, in forming the thin film, a source gas from a source supply unit 4021b may be supplied, and exhausting the gas by an exhaust unit 4025 may be performed. The temperature of the heater 4027 may be determined as appropriate depending on the type of film to be formed, the source gas, the desired film quality, and the heat resistance of the substrate and the films and elements provided thereon. For example, the temperature of the heater 4027 may be set to 200° C. or higher and 300° C. or lower during film formation, or may be set to 300° C. or higher and 500° C. or lower during film formation.

[0249] By forming a film while heating the substrate 4030 using the heater 4027, it is possible to omit a heat treatment of the substrate 4030 that is required in a later step. That is, by using the chamber 4020 or the film formation apparatus 4000 provided with the heater 4027, the formation of a film on the substrate 4030 and the heat treatment of the substrate 4030 can be performed at the same time.

[0250] In the film formation apparatus shown in FIG. 32B, a metal oxide can be formed by appropriately selecting raw materials (such as volatile organometallic compounds) used in raw material supply units 4021 and 4031. When forming an In-Ga-Zn oxide containing indium, gallium, and zinc as the metal oxide, it is preferable to use a film formation apparatus provided with at least three raw material supply units 4021 and at least one raw material supply unit 4031. It is preferable that a precursor containing indium is supplied from the first raw material supply unit 4021, a precursor containing gallium is supplied from the second raw material supply unit 4021, and a precursor containing zinc is supplied from the third raw material supply unit 4021. When a precursor containing gallium and zinc is used to form the metal oxide, at least two raw material supply units 4021 may be provided. The precursors described above can be used as the precursor containing indium, the precursor containing gallium, and the precursor containing zinc.

[0251] Furthermore, a reactant is supplied from the raw material supply unit 4031. As the reactant, an oxidizing agent containing at least one of ozone, oxygen, and water can be used.

[0252] Furthermore, by appropriately selecting the raw materials (e.g., volatile organometallic compounds) used in the raw material supply units 4021a, 4021b, and 4031, it is possible to form an insulating layer containing an oxide (including composite oxides) containing one or more elements selected from hafnium, aluminum, tantalum, zirconium, etc. Specifically, it is possible to form an insulating layer containing hafnium oxide, an insulating layer containing aluminum oxide, an insulating layer containing hafnium silicate, or an insulating layer containing aluminum silicate. Furthermore, by appropriately selecting the raw materials (e.g., volatile organometallic compounds) used in the raw material supply units 4021a, 4021b, and 4031, it is also possible to form thin films such as metal layers such as tungsten layers and titanium layers, and nitride layers such as titanium nitride layers.

[0253] For example, when forming a hafnium oxide layer using an ALD system, a first source gas is used, which is a vaporized liquid containing a solvent and a hafnium precursor compound (such as hafnium alkoxide or hafnium amide, such as tetrakisdimethylamidohafnium (TDMAHf)), and a second source gas is used, which is ozone (O) and oxygen (O) as oxidizers. In this case, the first source gas supplied from the source supply unit 4021a is TDMAHf, and the second source gas supplied from the source supply unit 4031 is ozone and oxygen. The chemical formula of tetrakisdimethylamidohafnium is Hf[N(CH)]. Other examples of source liquids include tetrakis(ethylmethylamido)hafnium. Water can also be used as the second source gas.

[0254] When forming an aluminum oxide layer using an ALD system, a first source gas is used, which is a vaporized liquid containing a solvent and an aluminum precursor compound (e.g., trimethylaluminum (TMA)), and a second source gas containing ozone (O3) and oxygen (O2) as oxidants. In this case, the first source gas supplied from the source supply unit 4021a is TMA, and the second source gas supplied from the source supply unit 4031 is ozone and oxygen. The chemical formula for trimethylaluminum is Al(CH3)3. Other source liquids include tris(dimethylamido)aluminum, triisobutylaluminum, and aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate). Water can also be used as the second source gas.

[0255] 33A to 33C, a description will be given of different configurations of an ALD apparatus that can be used for the film formation apparatus 4000. Note that detailed description of the same configurations and functions as those of the ALD apparatus shown in FIG. 32B may be omitted.

[0256] FIG. 33A is a schematic diagram showing one embodiment of a plasma ALD apparatus. The plasma ALD apparatus 4100 includes a reaction chamber 4120 and a plasma generation chamber 4111 above the reaction chamber 4120. The reaction chamber 4120 can be referred to as a chamber. Alternatively, the reaction chamber 4120 and the plasma generation chamber 4111 can be collectively referred to as a chamber. The reaction chamber 4120 has a raw material inlet 4123 and a raw material outlet 4124, and the plasma generation chamber 4111 has a raw material inlet 4133. Furthermore, a plasma generation device 4128 can apply high frequency waves such as RF or microwaves to gas introduced into the plasma generation chamber 4111 to generate plasma 4131 within the plasma generation chamber 4111. When generating plasma 4131 using microwaves, microwaves with a frequency of 2.45 GHz are typically used. Plasma generated using such microwaves is sometimes called ECR (Electron Cyclotron Resonance) plasma. The reaction chamber 4120 also has a substrate holder 4126, on which a substrate 4130 is placed. The source gas introduced through the source gas inlet 4123 is decomposed by heat from a heater installed in the reaction chamber 4120 and deposited on the substrate 4130. The source gas introduced through the source gas inlet 4133 is converted into a plasma state by the plasma generator 4128. The source gas in the plasma state recombines with electrons and other molecules before reaching the surface of the substrate 4130, becoming a radical state that reaches the substrate 4130. An ALD apparatus that uses radicals to form a film in this way is sometimes called a radical-enhanced ALD (radical-enhanced ALD) apparatus. While the plasma ALD apparatus 4100 has a configuration in which the plasma generation chamber 4111 is installed above the reaction chamber 4120, this embodiment is not limited to this. The plasma generation chamber 4111 may also be installed adjacent to the side of the reaction chamber 4120.

[0257] FIG. 33B is a schematic diagram showing one embodiment of a plasma ALD apparatus. The plasma ALD apparatus 4200 includes a chamber 4220. The chamber 4220 includes an electrode 4213, a raw material outlet 4224, and a substrate holder 4226, on which a substrate 4230 is placed. The electrode 4213 includes a raw material inlet 4223 and a showerhead 4214 that supplies the introduced raw material gas into the chamber 4220. The electrode 4213 is connected to a power supply 4215 capable of applying high-frequency power via a capacitor 4217. The substrate holder 4226 may be provided with a mechanism for applying a constant potential or high-frequency power. Alternatively, the substrate holder 4226 may be floating or grounded. The electrode 4213 and the substrate holder 4226 function as an upper electrode and a lower electrode, respectively, for generating a plasma 4231. The raw material gas introduced from the raw material inlet 4223 is decomposed by heat from a heater provided in the chamber 4220 and deposited on the substrate 4230. Alternatively, the raw material gas introduced from the raw material inlet 4223 becomes a plasma state between the electrode 4213 and the substrate holder 4226. The raw material gas in a plasma state is incident on the substrate 4230 due to a potential difference (also called an ion sheath) generated between the plasma 4231 and the substrate 4230.

[0258] FIG. 33C is a schematic diagram showing an embodiment of a plasma ALD apparatus different from that shown in FIG. 33B. The plasma ALD apparatus 4300 includes a chamber 4320. The chamber 4320 includes an electrode 4313, a raw material outlet 4324, and a substrate holder 4326, on which a substrate 4330 is placed. The electrode 4313 includes a raw material inlet 4323 and a showerhead 4314 that supplies the introduced raw material gas into the chamber 4320. The electrode 4313 is connected to a power supply 4315 capable of applying high-frequency power via a capacitor 4317. The substrate holder 4326 may be provided with a mechanism for applying a constant potential or high-frequency power. Alternatively, the substrate holder 4326 may be floating or grounded. The electrode 4313 and the substrate holder 4326 function as an upper electrode and a lower electrode, respectively, for generating a plasma 4331. The plasma ALD apparatus 4300 differs from the plasma ALD apparatus 4200 in that it includes a mesh 4319 connected to a power supply 4321 capable of applying high-frequency voltage via a capacitor 4322 between an electrode 4313 and a substrate holder 4326. The provision of the mesh 4319 allows the plasma 4231 to be separated from the substrate 4130. The source gas introduced through the source gas inlet 4323 is decomposed by heat from a heater provided in the chamber 4320 and deposited on the substrate 4330. Alternatively, the source gas introduced through the source gas inlet 4323 becomes a plasma between the electrode 4313 and the substrate holder 4326. The charge of the plasma-state source gas is removed by the mesh 4319, and the source gas reaches the substrate 4130 in an electrically neutral state, such as in the form of radicals. This allows for film formation with reduced ion incidence and plasma damage.

[0259] By forming the semiconductor 125 or the semiconductor 127 using the ALD method, it may be possible to form a metal oxide having a CAAC structure in which the c-axis is oriented approximately parallel to the normal direction of the deposition surface.

[0260] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes.

[0261] (Embodiment 2) In this embodiment, a description will be given of the circuit configuration and operation of a memory string 120, which is a memory device. Fig. 34 shows an example of the circuit configuration of the memory string 120. Fig. 35 shows an equivalent circuit diagram of a memory element MC.

[0262] In addition, in drawings and the like, to make it easier to understand the potential of a wiring, electrode, conductor, etc., an "H" indicating an H potential or an "L" indicating an L potential may be written next to the wiring, electrode, conductor, etc. Furthermore, a wiring, electrode, conductor, etc. in which a potential change has occurred may be written with "H" or "L" enclosed in letters. Furthermore, when a transistor is in an off state, an "x" symbol may be written over the transistor.

[0263] <Memory string circuit configuration example> FIG. 34 shows an example circuit configuration of a memory string 120 including five memory elements MC. The memory elements MC include a transistor WTr and a transistor RTr. In FIG. 34, the transistor WTr included in the memory element MC[1] is shown as transistor WTr[1], and the transistor RTr included in the memory element MC[1] is shown as transistor RTr[1]. Therefore, the memory string 120 shown in FIG. 34 includes transistors WTr[1] to WTr[5] and transistors RTr[1] to RTr[5]. The memory string 120 shown in FIG. 34 also includes transistors STr1, STr2, and STr3. The memory string 120 is a NAND-type memory device.

[0264] In an equivalent circuit diagram, the symbol "OS" may be added to the circuit symbol of a transistor to indicate that the transistor is an OS transistor. Similarly, the symbol "Si" may be added to the circuit symbol of a transistor to indicate that the transistor is a Si transistor (a transistor that uses silicon in the semiconductor layer in which the channel is formed). In FIG. 34, the transistors WTr and RTr are shown to be OS transistors.

[0265] A NAND-type storage device that includes an OS memory is also called an "OS NAND type" or "OS NAND type storage device." Additionally, an OS NAND type storage device with multiple OS memories stacked in the Z direction is also called a "3D OS NAND type" or "3D OS NAND type storage device."

[0266] The transistor WTr is a normally-off transistor. The transistor RTr is a normally-on transistor. As described in the above embodiment, the transistor RTr includes a conductor 128 between the gate and the semiconductor layer. The conductor 128 can function as a floating gate of the transistor RTr. For example, the conductor 128 included in the transistor RTr[1] is called the conductor 128[1].

[0267] The node where the conductor 128 and either the source or the drain of the transistor WTr are electrically connected is referred to as a node ND. For example, the node where the conductor 128[1] and either the source or the drain of the transistor WTr[1] are electrically connected is referred to as a node ND[1].

[0268] One of the source or drain of transistor RTr[1] is electrically connected to conductor RSL, and the other is electrically connected to one of the source or drain of transistor RTr[2]. The gate of transistor RTr[1] is electrically connected to conductor RWL[1]. The back gate of transistor RTr[1] is electrically connected to conductor BG. One of the source or drain of transistor WTr[1] is electrically connected to conductor 128[1], and the other is electrically connected to conductor 128[2]. The gate of transistor WTr[1] is electrically connected to conductor WWL[1]. In addition, one of the source or drain of transistor STr1 is electrically connected to conductor WSL, and the other is electrically connected to conductor 128[1], and the gate is electrically connected to conductor SG.

[0269] 35, the transistor RTr can be expressed by replacing it with a capacitance Cs and a transistor Tr. The gate of the transistor Tr is electrically connected to the conductor RWL via the capacitance Cs.

[0270] In addition, one of the source or drain of transistor RTr[5] is electrically connected to the other of the source or drain of transistor RTr[4], and the other is electrically connected to one of the source or drain of transistor STr2. The gate of transistor RTr[5] is electrically connected to conductor RWL[5]. The back gate of transistor RTr[5] is electrically connected to conductor BG. One of the source or drain of transistor WTr[5] is electrically connected to conductor 128[5], and the other is electrically connected to one of the source or drain of transistor STr3. The gate of transistor WTr[5] is electrically connected to conductor WWL[5]. In addition, the other of the source or drain of transistor STr2 is electrically connected to conductor RBL, and the gate is electrically connected to conductor SEL. In addition, the other of the source or drain of transistor STr3 is electrically connected to conductor WBL, and the gate is electrically connected to conductor SEL.

[0271] When the memory string 120 has n memory elements MC (n is an integer equal to or greater than 1), in the i-th memory element MC[i] (i is an integer equal to or greater than 2 and equal to or less than n-1), excluding the first and n-th memory elements MC, one of the source or drain of the transistor RTr[i] is electrically connected to the other of the source or drain of the transistor RTr[i-1], and the other is electrically connected to one of the source or drain of the transistor RTr[i+1]. The gate of the transistor RTr[i] is electrically connected to the conductor RWL[i]. The back gate of the transistor RTr[i] is electrically connected to the conductor BG. One of the source or drain of the transistor WTr[i] is electrically connected to the conductor 128[i], and the other is electrically connected to the conductor 128[i+1]. The gate of the transistor WTr[i] is electrically connected to the conductor WWL[i]. Note that the connection relationships between the first and nth memory elements MC and other elements and conductors can refer to the connection relationships described for the memory elements MC[1] and MC[5] above.

[0272] The transistors STr1, STr2, and STr3 may be, for example, OS transistors or Si transistors. At least one of the transistors STr1, STr2, and STr3 may be an OS transistor, and the others may be Si transistors. Note that when both the transistors WTr and RTr are formed of OS transistors, it is preferable that the transistors STr1, STr2, and STr3 are also formed of OS transistors. By using the same semiconductor material for the transistors, the productivity of semiconductor devices can be improved.

[0273] Alternatively, an OS transistor may be used as the transistor WTr and a Si transistor may be used as the transistor RTr. An equivalent circuit diagram of the memory string 120 in the case where an OS transistor is used as the transistor WTr and a Si transistor is used as the transistor RTr is shown in FIG.

[0274] When the transistor RTr is a Si transistor, polycrystalline silicon, for example, may be used for the semiconductor 125. When the transistor WTr is an OS transistor, CAAC-IGZO, for example, may be used for the semiconductor 127. In this case, it is preferable to use OS transistors for the transistors STr1 and STr3 and a Si transistor for the transistor STr2.

[0275] As shown in FIG. 37, depending on the purpose or application, a Si transistor may be used as the transistor WTr and an OS transistor may be used as the transistor RTr. In this case, it is preferable to use Si transistors for the transistors STr1 and STr3 and an OS transistor for the transistor STr2. Furthermore, as shown in FIG. 38, depending on the purpose or application, Si transistors may be used for both the transistor WTr and the transistor RTr. When Si transistors are used for both the transistor WTr and the transistor RTr, it is preferable to use Si transistors for the transistors STr1, STr2, and STr3 as well.

[0276] <Memory string operation example> Next, an example of the operation of the memory string 120 shown in FIG. 34 will be described.

[0277] [Write operation] An example of an operation for writing an H potential or an L potential to a memory element MC will be described below. Fig. 39 is a timing chart illustrating the write operation. Fig. 40A to Fig. 41B are circuit diagrams illustrating the write operation.

[0278] In the initial state, an L potential is written to the memory elements MC[1] to MC[5]. Also, an L potential is supplied to the conductors WWL[1] to WWL[5], the conductors RWL[1] to RWL[5], the conductor SEL, the conductor BG, the conductor WBL, the conductor RBL, the conductor SG, the conductor WSL, and the conductor RSL. The conductor BG can control the threshold voltage of the transistor RTr. The potential supplied to the conductor BG may be adjusted as appropriate so that the transistor RTr becomes a desired normally-on transistor. Although the conductor SEL is described as being a common conductor for the gates of the transistors STr2 and STr3, it may be a different conductor.

[0279] [Period T1] During period T1, while conductor WWL[3] is kept at L potential, H potential is supplied to conductor WWL[1], conductor WWL[2], conductor WWL[4], conductor WWL[5], conductor SG, and conductor SEL (see FIG. 40A). In addition, any one of H potential and L potential is supplied to conductor WSL and conductor WBL, respectively. Then, the potential of conductor WSL is supplied to nodes ND[1] to ND[3], and the potential of conductor WBL is supplied to nodes ND[4] and ND[5].

[0280] [Period T2] In period T2, an L potential is supplied to the conductors WWL[2] and WWL[4] (see FIG. 40B). Then, the transistors WTr[2] and WTr[4] are turned off, and the charges written to the nodes ND[3] and ND[4] are retained.

[0281] [Period T3] During the period T3, the potential of the conductor WSL is supplied to the nodes ND[1] and ND[2], and the potential of the conductor WBL is supplied to the node ND[5] (see FIG. 40B).

[0282] [Period T4] In period T4, an L potential is supplied to the conductors WWL[1] and WWL[5] (see FIG. 41A). Then, the transistors WTr[1] and WTr[5] are turned off, and the charges written to the nodes ND[2] and ND[5] are retained.

[0283] [Period T5] In a period T5, the potential of the conductor WSL is supplied to the node ND[1] (see FIG. 41A).

[0284] [Period T6] In a period T6, an L potential is supplied to the conductor SG (see FIG. 41B). Then, the transistor STr1 is turned off, and the charge written to the node ND[1] is held. At this time, an L potential may be supplied to the conductor SEL.

[0285] In this way, information can be written to the memory element MC.

[0286] In the memory string 120, information can be written from both the conductor WSL and the conductor WBL. That is, information can be written to the storage element MC[3] and the storage element MC[4] simultaneously. Furthermore, after writing to the storage element MC[3] and the storage element MC[4], information can be written to the storage element MC[2] and the storage element MC[5] simultaneously. In this way, since information can be written to multiple storage elements MC in one memory string 120 simultaneously, the information writing speed can be increased. Furthermore, the supply of charge corresponding to the information to be written can be more reliably performed.

[0287] Furthermore, when writing information to the i-th memory element MC, if i is close to n, the information is written from the conductor WBL side, thereby omitting the operation of writing information to the 1st to (i-1)th memory elements MC. Furthermore, if i is close to 1, the information is written from the conductor WSL side, thereby omitting the operation of writing information to the (i+1)th to nth memory elements MC. In the memory string 120, the time and power consumption required for the write operation can be reduced.

[0288] In this embodiment, an example is shown in which an L potential is always supplied to the conductor WWL[3] during the write operation, the write to the storage elements MC[1] to MC[3] is performed from the conductor WSL side, and the write to the storage elements MC[4] and MC[5] is performed from the conductor WBL side. However, the present invention is not limited to this. With an arbitrary conductor WWL[i] as the boundary, the write to the storage elements MC[1] to MC[i] may be performed from the conductor WSL side, and the write to the storage elements MC[i+1] to MC[n] may be performed from the conductor WBL side. Furthermore, the write to the storage elements MC[1] to MC[n] may be performed from the conductor WSL side, or the write to the storage elements MC[1] to MC[n] may be performed from the conductor WBL side.

[0289] [Read operation] An example of a read operation of the memory string 120 having the above circuit configuration will be described. As an initial state, assume that an L potential is supplied to conductor WWL[1] to conductor WWL[5], conductor RWL[1] to conductor RWL[5], conductor SG, conductor SEL, conductor BG, conductor WSL, conductor RSL, conductor WBL, and conductor RBL. Figure 42 is a timing chart illustrating the read operation. Figures 43A to 45 are circuit diagrams for illustrating the read operation.

[0290] In this embodiment, an operation of sequentially reading data from the storage elements MC[1] to MC[5] will be described.

[0291] [Period T7] In a period T7, an H potential is supplied to the conductors RWL[2] to RWL[5], the conductor SEL, and the conductor RSL (see FIG. 43A). As a result, the transistors RTr[2] to RTr[5] are turned on. In addition, the transistor STr2 is turned on, and the semiconductor 127 included in the transistor RTr and the conductor RBL are electrically connected to each other.

[0292] At this time, if the node ND[1] of the memory element MC[1] is held at an H potential, the transistor RTr[1] is turned on even if the potential supplied to the conductor RWL[1] is at an L potential. Therefore, the conductors RSL and RBL are electrically connected via the transistors RTr[1] to RTr[5], and the H potential supplied to the conductor RSL can be detected on the conductor RBL side. In other words, it can be detected that the potential held at the node ND[1] of the memory element MC[1] is at an H potential. Note that the conductor RBL is preferably functionally connected to an RBL driver 2004 equipped with a sense amplifier or the like (see FIGS. 1A and 1B).

[0293] On the other hand, when the node ND[1] of the memory element MC[1] is held at an L potential, the potential supplied to the conductor RWL[1] is at an L potential, and the transistor RTr[1] is turned off. Therefore, the conductors RSL and RBL are not electrically connected, and the H potential supplied to the conductor RSL cannot be detected on the conductor RBL side. Therefore, on the conductor RBL side, it can be detected that the node ND[1] of the memory element MC[1] is held at an L potential.

[0294] [Period T8] Next, in period T8, an H potential is supplied to the conductor RWL[1], and an L potential is supplied to the conductor RWL[2] (see FIG. 43B). At this time, if an H potential is held at the node ND[2] of the memory element MC[2], even if the potential supplied to the conductor RWL[2] is an L potential, the transistor RTr[2] is turned on. Therefore, the conductors RSL and RBL are in a conductive state via the transistors RTr[1] to RTr[5], and the H potential supplied to the conductor RSL can be detected on the conductor RBL side. In other words, it can be detected that the potential held at the node ND[2] of the memory element MC[2] is an H potential.

[0295] On the other hand, when the node ND[2] of the memory element MC[2] is held at an L potential, the potential supplied to the conductor RWL[2] is at an L potential, and the transistor RTr[2] is turned off. Therefore, the conductors RSL and RBL are not electrically connected, and the H potential supplied to the conductor RSL cannot be detected on the conductor RBL side. Therefore, on the conductor RBL side, it can be detected that the node ND[2] of the memory element MC[2] is held at an L potential.

[0296] [Period T9] Next, in period T9, an H potential is supplied to the conductor RWL[2] and an L potential is supplied to the conductor RWL[3] (see FIG. 44A). At this time, if an H potential is held at the node ND[3] of the memory element MC[3], even if the potential supplied to the conductor RWL[3] is an L potential, the transistor RTr[3] is turned on. Therefore, the conductors RSL and RBL are in a conductive state via the transistors RTr[1] to RTr[5], and the H potential supplied to the conductor RSL can be detected on the conductor RBL side. In other words, it can be detected that the potential held at the node ND[3] of the memory element MC[3] is an H potential.

[0297] On the other hand, when the node ND[3] of the memory element MC[3] is held at an L potential, the potential supplied to the conductor RWL[3] is at an L potential, and the transistor RTr[3] is turned off. Therefore, the conductors RSL and RBL are not electrically connected, and the H potential supplied to the conductor RSL cannot be detected on the conductor RBL side. Therefore, on the conductor RBL side, it can be detected that the node ND[3] of the memory element MC[3] is held at an L potential.

[0298] [Period T10] Next, in period T10, an H potential is supplied to the conductor RWL[3], and an L potential is supplied to the conductor RWL[4] (see FIG. 44B). At this time, if an H potential is held at the node ND[4] of the memory element MC[4], even if the potential supplied to the conductor RWL[4] is an L potential, the transistor RTr[4] is turned on. Therefore, the conductors RSL and RBL are in a conductive state via the transistors RTr[1] to RTr[5], and the H potential supplied to the conductor RSL can be detected on the conductor RBL side. In other words, it can be detected that the potential held at the node ND[4] of the memory element MC[4] is an H potential.

[0299] On the other hand, when the node ND[4] of the memory element MC[4] is held at an L potential, the potential supplied to the conductor RWL[4] is at an L potential, and the transistor RTr[4] is turned off. Therefore, the conductors RSL and RBL are not electrically connected, and the H potential supplied to the conductor RSL cannot be detected on the conductor RBL side. Therefore, on the conductor RBL side, it can be detected that the node ND[4] of the memory element MC[4] is held at an L potential.

[0300] [Period T11] Next, in period T11, an H potential is supplied to the conductor RWL[4], and an L potential is supplied to the conductor RWL[5] (see FIG. 45). At this time, if an H potential is held at the node ND[5] of the memory element MC[5], even if the potential supplied to the conductor RWL[5] is an L potential, the transistor RTr[5] is turned on. Therefore, the conductors RSL and RBL are in a conductive state via the transistors RTr[1] to RTr[5], and the H potential supplied to the conductor RSL can be detected on the conductor RBL side. In other words, it can be detected that the potential held at the node ND[5] of the memory element MC[5] is an H potential.

[0301] On the other hand, when the node ND[5] of the memory element MC[5] is held at an L potential, the potential supplied to the conductor RWL[5] is at an L potential, and the transistor RTr[5] is turned off. Therefore, the conductors RSL and RBL are not electrically connected, and the H potential supplied to the conductor RSL cannot be detected on the conductor RBL side. Therefore, on the conductor RBL side, it can be detected that the node ND[5] of the memory element MC[5] is held at an L potential.

[0302] In this way, by detecting the potentials held in the nodes ND[1] to ND[5], information can be read from the storage elements MC[1] to MC[5]. Note that, although an example in which information is sequentially read from the storage element MC[1] to the storage element MC[5] has been described in this embodiment, the present invention is not limited to this. Information may be sequentially read from the storage element MC[5] to the storage element MC[1].

[0303] Furthermore, it is not necessary to read the information from the storage elements MC[1] to MC[5], and the information from any storage element MC[i] can be read. In this case, an L potential is supplied to the conductor RWL[i], an H potential is supplied to the other conductors RWL, and the potential held in the node ND[i] of the storage element MC[i] is detected based on whether the potential of the conductor RSL can be detected on the conductor RBL side, and the information from the storage element MC[i] can be read.

[0304] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes.

[0305] (Embodiment 3) In this embodiment, a configuration example of a semiconductor device 200 including a memory device 100 will be described.

[0306] 46 is a block diagram illustrating a configuration example of a semiconductor device 200 according to one embodiment of the present invention. The semiconductor device 200 illustrated in FIG. 46 includes a driver circuit 210 and a memory array 220. The memory array 220 includes one or more memory devices 100. FIG. 46 illustrates an example in which the memory array 220 includes a plurality of memory devices 100 arranged in a matrix.

[0307] The drive circuit 210 has a PSW 241 (power switch), a PSW 242, and a peripheral circuit 215. The peripheral circuit 215 has a peripheral circuit 211, a control circuit 212, and a voltage generation circuit 228. The semiconductor device 200 has elements or circuits having various functions, such as a memory array 220, PSWs 241 and 242, the peripheral circuit 211, the control circuit 212, and the voltage generation circuit 228. Therefore, the semiconductor device 200 may be referred to as a system or a subsystem.

[0308] In the semiconductor device 200, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0309] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 212.

[0310] The control circuit 212 is a logic circuit having a function of controlling the overall operation of the semiconductor device 200. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the semiconductor device 200. Alternatively, the control circuit 212 generates a control signal for the peripheral circuit 211 so that this operation mode is executed.

[0311] The voltage generation circuit 228 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generation circuit 228. For example, when an H-level signal is given as the signal WAKE, the signal CLK is input to the voltage generation circuit 228, and the voltage generation circuit 228 generates a negative voltage.

[0312] The peripheral circuit 211 is a circuit for writing and reading data to and from the memory device 100. The peripheral circuit 211 has a row decoder 221, a column decoder 222, a row driver 223, a column driver 224, an input circuit 225, an output circuit 226, and a sense amplifier 227.

[0313] The row decoder 221 and the column decoder 222 have the function of decoding the signal ADDR. The row decoder 221 is a circuit for specifying a row to be accessed, and the column decoder 222 is a circuit for specifying a column to be accessed. The row driver 223 has the function of selecting the conductor WWL specified by the row decoder 221. The column driver 224 has the function of writing data to the memory device 100, reading data from the memory device 100, and holding the read data.

[0314] The input circuit 225 has a function of holding a signal WDA. The data held by the input circuit 225 is output to the column driver 224. The output data of the input circuit 225 is data (Din) to be written to the memory device 100. The data (Dout) read from the memory device 100 by the column driver 224 is output to the output circuit 226. The output circuit 226 has a function of holding Dout. In addition, the output circuit 226 has a function of outputting Dout to the outside of the semiconductor device 200. The data output from the output circuit 226 is a signal RDA.

[0315] PSW241 is the V to the peripheral circuit 215 DD The PSW 242 has the function of controlling the supply of V to the row driver 223. HM Here, the high power supply voltage of the semiconductor device 200 is V DD and the low power supply voltage is GND (ground potential). HM is the high supply voltage used to drive the word line high, and V DD The signal PON1 controls the on / off of the PSW 241, and the signal PON2 controls the on / off of the PSW 242. In FIG. 46, in the peripheral circuit 215, V DD Although the number of power domains to which power is supplied is set to one, it is also possible to set multiple power domains. In this case, a power switch should be provided for each power domain.

[0316] The drive circuit 210 and the memory array 220 may be provided on the same plane. Alternatively, as shown in FIG. 47A, the drive circuit 210 and the memory array 220 may be provided overlapping each other. By providing the drive circuit 210 and the memory array 220 overlapping each other, the signal propagation distance can be shortened. Alternatively, as shown in FIG. 47B, the memory array 220 may be provided in multiple layers on the drive circuit 210.

[0317] Furthermore, as shown in FIG. 47C , memory arrays 220 may be provided above and below the drive circuit 210. FIG. 47C shows an example in which one memory array 220 is provided above and one memory array 220 below the drive circuit 210. By arranging the drive circuit 210 so that the multiple memory arrays 220 sandwich the drive circuit 210, the signal propagation distance can be further shortened. Note that the number of memory arrays 220 stacked above the drive circuit 210 and the number of memory arrays 220 stacked below the drive circuit 210 may each be one or more. It is preferable that the number of memory arrays 220 stacked above the drive circuit 210 is equal to the number of memory arrays 220 stacked below the drive circuit 210.

[0318] <Example of Cross-Sectional Configuration of Semiconductor Device 200> Fig. 48 shows an example of a cross-sectional configuration of the semiconductor device 200 shown in Fig. 47A. Fig. 48 shows a part of the semiconductor device 200 shown in Fig. 47A.

[0319] In FIG. 48, a transistor 301, a transistor 302, and a transistor 303 included in the driving circuit 210 are shown. The transistors 301 and 302 function as part of the sense amplifier 227. The transistor 303 functions as a column selection switch. Specifically, the conductor RBL included in the memory array 220 is electrically connected to one of the source and drain of the transistor 301, the gate of the transistor 301 is electrically connected to one of the source and drain of the transistor 302, and the gate of the transistor 302 is electrically connected to one of the source and drain of the transistor 301. The source and drain of the transistor 301 and the gate of the transistor 302 are electrically connected to one of the source and drain of the transistor 303, which functions as a column selection switch. This reduces the layout area of the semiconductor device 200. Note that FIG. 48 shows an example in which five memory elements MC are provided per memory string. However, the number of memory elements MC provided in one memory string is not limited to this. For example, the number of memory elements MC provided in one memory string may be 32, 64, 128, or 200 or more.

[0320] The conductor RBL of the memory array 220 is electrically connected to the sense amplifier 227 and the transistor 303 functioning as a column selection switch via a conductor 752 formed to be embedded in the conductors 715, 714, 705, and the insulators 726 and 722. Note that the circuits and transistors included in the driver circuit 210 are merely examples, and the circuit configuration and transistor structure are not limited thereto. In addition to the above, appropriate circuits and transistors, such as a control circuit, a row decoder, a row driver, a source line driver, and an input / output circuit, can be provided depending on the configuration of the semiconductor device 200 and its driving method.

[0321] The transistors 301, 302, and 303 are provided on a substrate 311, and each includes a conductor 316, an insulator 315, a semiconductor region 313 made of part of the substrate 311, and a low-resistance region 314a and a low-resistance region 314b that function as a source region or a drain region. Note that, as shown in FIG. 48, one low-resistance region may be shared by the transistors 301 and 302 as both the source region or the drain region of one and the source region or the drain region of the other.

[0322] In the transistors 301, 302, and 303, a semiconductor region 313 (a part of the substrate 311) in which a channel is formed has a convex shape. A conductor 316 is provided to cover the side and top surfaces of the semiconductor region 313 with an insulator 315 interposed therebetween. The conductor 316 may be made of a material that adjusts the work function. The transistors 301, 302, and 303 are also called FIN transistors because they utilize the convex portions of the semiconductor substrate. An insulator that functions as a mask for forming the convex portions may be provided in contact with the tops of the convex portions. While the case where the convex portions are formed by processing a part of the semiconductor substrate has been described here, a semiconductor film having a convex shape may also be formed by processing an SOI substrate.

[0323] The transistors 301, 302, and 303 may each be a p-channel or n-channel transistor. The transistors 301 and 302 may have the same conductivity type or may have different conductivity types.

[0324] The region where the channel of the semiconductor region 313 is formed, the region nearby, the low-resistance region 314a that serves as the source region or the drain region, and the low-resistance region 314b preferably contain a semiconductor such as a silicon-based semiconductor, and preferably contain single-crystal silicon. Alternatively, they may be formed of a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may also be used. Alternatively, by using GaAs and GaAlAs, the transistors 301, 302, and 303 may be configured as HEMTs (High Electron Mobility Transistors).

[0325] The low resistance region 314a and the low resistance region 314b contain, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0326] The insulator 315 functions as a gate insulating film for the transistor 301 , the transistor 302 , and the transistor 303 .

[0327] The conductor 316 functioning as the gate electrode can be made of a conductive material such as a semiconductor material, metal material, alloy material, or metal oxide material, such as silicon containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0328] Since the work function is determined by the material of the conductor, the threshold voltage can be adjusted by changing the material of the conductor. Specifically, it is preferable to use materials such as titanium nitride and tantalum nitride for the conductor. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use metal materials such as tungsten and aluminum as a laminate for the conductor, and tungsten is particularly preferable in terms of heat resistance.

[0329] An insulator 317, which functions as an etch stopper, is preferably provided above the conductor 316. An insulator 318, which functions as a spacer, is preferably provided on the side of the insulator 315. By providing the insulators 317 and 318, the regions where the low-resistance regions 314a and 314b are electrically connected to the conductor 328 can be determined in a self-aligned manner. Therefore, even if misalignment occurs when forming openings to expose portions of the low-resistance regions 314a and 314b, openings can be formed to expose the intended regions. Forming the conductor 328 in the openings thus formed results in good contact with the conductor 328, with reduced contact resistance, and thus a contact between the low-resistance regions 314a and 314b and the conductor 328. The contact formed in this manner between the low-resistance regions 314a and 314b and the conductor 328 is sometimes referred to as a self-aligned contact. In addition, a conductor 329 electrically connected to the conductor 316 may be provided so as to be embedded in the insulator 317 and the insulator 322 .

[0330] An insulator 320, an insulator 322, an insulator 324, an insulator 326, and an insulator 327 are stacked in this order to cover the transistor 301, the transistor 302, and the transistor 303.

[0331] The insulators 320, 322, 324, 326, and 327 can be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, or aluminum nitride.

[0332] The insulator 320 and the insulator 322 may function as a planarizing film that flattens steps caused by the transistor 301 or the like provided thereunder. For example, the top surfaces of one or both of the insulator 320 and the insulator 322 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to improve the planarity.

[0333] The insulator 324 is preferably a film having a barrier property that prevents hydrogen or impurities from diffusing from the substrate 311 or the transistor 301 to a region where the memory array 220 is provided.

[0334] An example of a film having a barrier property against hydrogen is silicon nitride formed by a CVD method. Here, hydrogen diffusion into a semiconductor element having an oxide semiconductor, such as the memory element MC, may degrade the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the memory element MC and the transistor 301 or the like. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0335] The amount of desorption of hydrogen can be analyzed using, for example, thermal desorption spectroscopy (TDS). For example, the amount of desorption of hydrogen from the insulator 324 is calculated as 10×10 per area of the insulator 324 when the surface temperature of the film is in the range of 50° C. to 500° C. in TDS analysis. 15 atoms / cm 2 Less than or equal to 5 x 10 15 atoms / cm 2 The following is fine.

[0336] Note that the insulators 326 and 327 preferably have a lower dielectric constant than the insulator 324. For example, the dielectric constant of the insulators 326 and 327 is preferably less than 4, and more preferably less than 3. Furthermore, for example, the dielectric constant of the insulators 326 and 327 is preferably 0.7 times or less, and more preferably 0.6 times or less, the dielectric constant of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced.

[0337] Furthermore, conductors 328, 329, 330, etc., which are electrically connected to the memory array 220, are embedded in the insulators 320, 322, 324, 326, and 327. The conductors 328, 329, and 330 function as plugs or wiring. Furthermore, for conductors that function as plugs or wiring, multiple structures may be collectively assigned the same reference numeral. Furthermore, in this specification, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a portion of the conductor functions as wiring, and cases where a portion of the conductor functions as a plug.

[0338] The materials for each plug and wiring (such as conductor 328, conductor 329, and conductor 330) can be a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material, and can be used in a single layer or a laminated layer. High-melting-point materials such as tungsten and molybdenum, which have both heat resistance and conductivity, are preferably used, and tungsten is preferred. Alternatively, they are preferably formed from a low-resistance conductive material such as aluminum or copper. The use of a low-resistance conductive material can reduce the wiring resistance.

[0339] A wiring layer may be provided over the insulator 327 and the conductor 330. For example, in FIG. 48, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. A conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring. The conductor 356 can be formed using a material similar to that of the conductors 328, 329, and 330.

[0340] Note that, for example, the insulator 350 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 356 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 350 having a barrier property against hydrogen. With this structure, the transistor 301 and the like can be separated from the memory element MC by a barrier layer, and diffusion of hydrogen from the transistor 301 and the like to the memory element MC can be suppressed.

[0341] Note that, for example, tantalum nitride or the like is preferably used as a conductor having a barrier property against hydrogen. Stacking tantalum nitride and highly conductive tungsten can suppress diffusion of hydrogen from the transistor 301 and the like while maintaining the conductivity of the wiring. In this case, a structure in which the tantalum nitride layer having a barrier property against hydrogen is in contact with the insulator 350 having a barrier property against hydrogen is preferable.

[0342] A wiring layer may be provided over the insulator 354 and the conductor 356. For example, in FIG. 48, an insulator 360, an insulator 362, and an insulator 364 are stacked in this order. A conductor 366 is formed in the insulator 360, the insulator 362, and the insulator 364. The conductor 366 functions as a plug or a wiring. The conductor 366 can be formed using a material similar to that of the conductors 328, 329, and 330.

[0343] Note that, for example, the insulator 360 preferably uses an insulator having a barrier property against hydrogen, similar to the insulator 324. The conductor 366 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening of the insulator 360 having a barrier property against hydrogen. With this structure, the transistor 301 and the like can be separated from the memory element MC by a barrier layer, and diffusion of hydrogen from the transistor 301 and the like to the memory element MC can be suppressed.

[0344] An insulator 722 is provided on the insulator 364 and the conductor 366, and the memory array 220 is provided above the insulator 722. A barrier film made of a material similar to that of the insulator 324 may be provided between the insulator 364 and the insulator 722.

[0345] Although the above describes an example in which the memory device 100 has the memory string 120, the present embodiment is not limited to this. As shown in Fig. 49, the memory device 100 may have a memory string 120A as described in Fig. 8.

[0346] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes.

[0347] (Fourth embodiment) In this embodiment, an application example of a data processing device according to one embodiment of the present invention will be described.

[0348] Generally, a computer has components such as a processor, main memory, and storage on a motherboard, and these components are electrically connected by, for example, bus wiring. Therefore, the longer the bus wiring, the greater the parasitic resistance, and therefore the more power consumed to transmit signals.

[0349] Specifically, a computer may have a configuration such as that shown in Fig. 50A. The computer has a motherboard BD, on which are provided an arithmetic processing unit (processor, CPU, etc.) 10, a main memory (DRAM (Dynamic Random Access Memory), etc.) 30, storage (a three-dimensional NAND storage device, a 3D OS NAND storage device, etc.) 40, an interface 60, etc. Fig. 50 also shows SRAM (Static Random Access Memory) 20, which also functions as main memory, but it does not necessarily have to be provided on the motherboard BD.

[0350] 50 shows a configuration in which the arithmetic processing unit 10 has a register 11.

[0351] 50A, the arithmetic processing device 10 is electrically connected to the SRAM 20, the main memory 30, the storage 40, and the interface 60. The main memory 30 is also electrically connected to the SRAM 20 and the storage 40.

[0352] 50A are electrically connected by bus wiring BSH. In other words, the more components of the computer there are, or the larger the motherboard BD, the longer the bus wiring BSH that is routed, and the more power consumption is required to transmit signals.

[0353] Incidentally, the computer of Fig. 50A may be configured such that the components of the computer are integrated into a single chip to form a monolithic integrated circuit (IC). In this case, the information processing device described in the above embodiment can be applied as the main memory 30 and storage 40. Fig. 50B shows the computer of Fig. 50A configured as a monolithic IC.

[0354] 50B has a circuit layer LGC on a semiconductor substrate made of Si, a memory layer STR on top of the circuit layer LGC, and a circuit layer OSC on top of the memory layer STR.

[0355] The circuit layer LGC has, for example, a plurality of circuits including Si transistors formed on a semiconductor substrate SBT having Si. Parts of the plurality of circuits may be, for example, the arithmetic processing device 10, the SRAM 20, etc. in FIG. 50A. Furthermore, when the information processing device is applied as the main memory 30 and the storage 40, part of the plurality of circuits may be the controller 1197 included in the information processing device 50.

[0356] In particular, the SRAM 20 can increase the driving frequency of the SRAM by using Si transistors, for example.

[0357] The memory layer STR functions as a memory unit having Si transistors and / or OS transistors. The memory layer STR can be, for example, a three-dimensional NAND memory circuit, a 3D OS NAND memory circuit, or the like. Therefore, the memory layer STR includes the memory unit 1196 in the information processing device, the storage 40 in FIG. 50A, or the like.

[0358] It should be noted that by using a 3D OS NAND type memory circuit, the power consumption of the monolithic IC of FIG. 50B can be reduced.

[0359] The circuit layer OSC includes, for example, a plurality of circuits including OS transistors. Some of the circuits may be circuits other than those included in the circuit layer LGC, such as the arithmetic processing unit 10 and the SRAM 20.

[0360] The monolithic IC in Figure 50B does not have bus wiring BSH for routing on the motherboard, so the wiring that electrically connects each component is short, which reduces the power consumption required for signal transmission.

[0361] 50B also includes an information processing device 50. Therefore, the information processing device 50 functions as the storage 40 and the main memory 30 in FIG. 50A. Therefore, in the monolithic IC in FIG. 50B, the memory unit 1196 of the memory layer STR can have the function of the main memory 30.

[0362] Because bus wiring BSH is not provided and storage unit 1196 is used instead of main memory 30, the monolithic IC in FIG. 50B can reduce the circuit area more than the computer in FIG. 50A.

[0363] Next, examples of memory hierarchies for the computer of FIG. 50A and the monolithic IC of FIG. 50B are shown in FIGS. 51A and 51B, respectively.

[0364] Generally, in the memory hierarchy, the higher the memory device is located, the faster the operating speed is required, and the lower the memory device is located, the larger the memory capacity and the higher the recording density are required. In Figure 51A, as an example, from the top, a register included in the CPU (arithmetic processing unit 10), an SRAM, a DRAM included in the main memory 30, and a three-dimensional NAND-type memory circuit included in the storage 40 are shown.

[0365] The registers and SRAM included in the arithmetic processing device 10 are used for temporary storage of calculation results, and are therefore frequently accessed by the arithmetic processing device 10. Therefore, a high operating speed is required rather than a large memory capacity. The registers also have the function of storing setting information for the arithmetic processing device.

[0366] The DRAM included in the main memory 30 has a function of storing programs and data read from the storage 40. The recording density of the DRAM is approximately 0.1 to 0.3 Gbit / mm 2 is.

[0367] The storage 40 has the function of storing data that requires long-term storage, various programs used by the processing unit, etc. Therefore, the storage 40 is required to have a large storage capacity and a high recording density rather than an operating speed. The recording density of the memory device used for the storage 40 is approximately 0.6 to 6.0 Gbit / mm 2 For this reason, the storage 40 may be a three-dimensional NAND type memory circuit, a hard disk drive (HDD), or the like.

[0368] Incidentally, the monolithic IC in FIG. 50B has the roles of storage 40 and main memory 30 in FIG. 50A, so the memory hierarchy of the monolithic IC in FIG. 50B is as shown in FIG. 51B.

[0369] That is, in the monolithic IC of Fig. 50B, the memory cells included in the storage unit of the information processing device 50 can be treated not only as cache memory of the storage unit but also as main memory 30 in the computer of Fig. 50A. Therefore, the monolithic IC of Fig. 50B does not need to provide a main memory 30 such as DRAM, so the circuit area of the monolithic IC of Fig. 50B can be reduced, and the power consumption required to operate the main memory 30 such as DRAM can also be reduced.

[0370] Note that the configuration of the monolithic IC shown in Fig. 50B is an example and is not limited to one aspect of the present invention. The configuration of the monolithic IC shown in Fig. 50B may be changed depending on the situation. For example, in the monolithic IC of Fig. 50B, if a high-speed memory of 1 GHz or more is required as the SRAM, the SRAM may be integrated into the arithmetic processing unit.

[0371] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0372] (Embodiment 5) In this embodiment, an example of a chip 1200, which is a type of semiconductor device on which a memory device of the present invention is mounted, is shown using Figures 52A and 52B. A plurality of circuits (systems) are mounted on the chip 1200. A technology for integrating a plurality of circuits (systems) on a single chip in this way is sometimes called a system on chip (SoC).

[0373] As shown in FIG. 52A, the chip 1200 includes a CPU 1211, a GPU 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

[0374] Chip 1200 is provided with bumps (not shown), which are connected to a first surface of a printed circuit board (PCB) 1201, as shown in Fig. 52B. In addition, a plurality of bumps 1202 are provided on the backside of the first surface of PCB 1201, which is connected to a motherboard 1203.

[0375] The motherboard 1203 may be provided with a sensor 1221, a power supply circuit 1222, and the like.

[0376] The CPU 1211 preferably has multiple CPU cores. The GPU 1212 preferably has multiple GPU cores. The CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided in the chip 1200. The GPU 1212 is suitable for parallel calculation of a large amount of data, and can be used for image processing and multiply-and-accumulate operations. By providing the GPU 1212 with an image processing circuit and a multiply-and-accumulate operation circuit, it becomes possible to perform image processing and multiply-and-accumulate operations with low power consumption.

[0377] Furthermore, by providing the CPU 1211 and GPU 1212 on the same chip, the wiring between the CPU 1211 and GPU 1212 can be shortened, enabling high-speed data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and GPU 1212, and transfer of the calculation results from the GPU 1212 to the CPU 1211 after calculation in the GPU 1212.

[0378] The analog calculation unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. The analog calculation unit 1213 may also be provided with the above-mentioned product-sum calculation circuit.

[0379] The memory controller 1214 includes a circuit that functions as a controller and an interface for a memory device according to one embodiment of the present invention.

[0380] The interface 1215 has an interface circuit with externally connected devices such as a display device, speaker, microphone, camera, and controller. Controllers include a mouse, keyboard, game controller, etc. As such an interface, a USB (Universal Serial Bus), HDMI (registered trademark) (High-Definition Multimedia Interface), etc. can be used.

[0381] The network circuit 1216 includes a network circuit for connecting to a LAN (Local Area Network), etc. It may also include a circuit for network security.

[0382] The above circuits (systems) can be formed in the same manufacturing process on the chip 1200. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.

[0383] The PCB 1201 on which the chip 1200 having the GPU 1212 is mounted, the sensor 1221, and the motherboard 1203 on which the power supply circuit 1222 is mounted can be called a GPU module 1204.

[0384] The GPU module 1204 includes the chip 1200 using SoC technology, allowing for a small size. Furthermore, due to its superior image processing capabilities, it is suitable for use in portable electronic devices such as smartphones, tablet devices, laptop PCs, and portable (portable) game consoles. Furthermore, a multiply-and-accumulate circuit using the GPU 1212 can execute techniques such as deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), autoencoders, deep Boltzmann machines (DBMs), and deep belief networks (DBNs). Therefore, the chip 1200 can be used as an AI chip, and the GPU module 1204 can be used as an AI system module.

[0385] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments.

[0386] (Embodiment 6) In this embodiment, an application example of a semiconductor device using the storage device described in the previous embodiment will be described. The storage device described in the previous embodiment can be applied to various removable storage devices such as memory cards (e.g., SD cards), USB memories, and SSDs (solid state drives). Figures 53A to 53E schematically show several configuration examples of removable storage devices. For example, the semiconductor device described in the previous embodiment is processed into a packaged memory chip and used in various storage devices and removable memories.

[0387] 53A is a schematic diagram of a USB memory. The USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a board 1104. The board 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the board 1104. The memory device or the semiconductor device described in the above embodiments can be incorporated into the memory chip 1105 or the like.

[0388] FIG. 53B is a schematic diagram of the appearance of an SD card, and FIG. 53C is a schematic diagram of the internal structure of the SD card. The SD card 1110 has a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113. The capacity of the SD card 1110 can be increased by providing a memory chip 1114 on the back side of the substrate 1113. A wireless chip with a wireless communication function may also be provided on the substrate 1113. This enables reading and writing of data from and to the memory chip 1114 through wireless communication between a host device and the SD card 1110. The memory device or semiconductor device described in the above embodiments can be incorporated into the memory chip 1114 or the like.

[0389] FIG. 53D is a schematic diagram of the appearance of an SSD, and FIG. 53E is a schematic diagram of the internal structure of the SSD. SSD 1150 has a housing 1151, a connector 1152, and a board 1153. Board 1153 is housed in housing 1151. For example, memory chip 1154, memory chip 1155, and controller chip 1156 are attached to board 1153. Memory chip 1155 is a work memory for controller chip 1156, and may be, for example, a DOSRAM chip. By providing memory chip 1154 on the back side of board 1153, the capacity of SSD 1150 can be increased. The storage device or semiconductor device described in the previous embodiments can be incorporated into memory chip 1154 or the like.

[0390] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes.

[0391] (Embodiment 7) 54A to 54G illustrate specific examples of electronic devices equipped with a memory device or a semiconductor device according to one embodiment of the present invention.

[0392] <Electronic devices and systems> A memory device or a semiconductor device according to one embodiment of the present invention can be incorporated into various electronic devices. Examples of the electronic devices include information terminals, computers, smartphones, e-book readers, televisions, digital signage, large game machines such as pachinko machines, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, recording and playback devices, navigation systems, and audio playback devices. Note that the term "computer" as used herein includes tablet computers, notebook computers, desktop computers, and large computers such as server systems.

[0393] The electronic device of one embodiment of the present invention may include an antenna. By receiving a signal through the antenna, images, information, and the like can be displayed on a display portion. When the electronic device includes an antenna and a secondary battery, the antenna may be used for contactless power transmission.

[0394] An electronic device according to one embodiment of the present invention may have a sensor (including a function for measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0395] The electronic device of one embodiment of the present invention can have various functions, such as a function to display various information (still images, videos, text images, etc.) on a display portion, a touch panel function, a function to display a calendar, date, time, etc., a function to execute various software (programs), a wireless communication function, a function to read programs or data recorded on a recording medium, etc.

[0396] [Information terminal] A memory device for storing programs of a microcontroller can be formed using a memory device or a semiconductor device according to one embodiment of the present invention, and therefore, according to one embodiment of the present invention, the size of a microcontroller chip can be reduced.

[0397] FIG. 54A illustrates a mobile phone (smartphone), which is one type of information terminal. The information terminal 5100 includes a housing 5101 and a display portion 5102. As input interfaces, a touch panel is provided on the display portion 5102 and buttons are provided on the housing 5101. By using a miniaturized microcontroller according to one embodiment of the present invention, the limited space inside the mobile phone can be effectively utilized. Furthermore, a storage device according to one embodiment of the present invention may be used for storage of the mobile phone. This allows the storage capacity per unit area of the storage to be increased.

[0398] FIG. 54B illustrates a notebook information terminal 5200. The notebook information terminal 5200 includes a main body 5201 of the information terminal, a display unit 5202, and a keyboard 5203. By using a miniaturized microcontroller according to one embodiment of the present invention, the limited space inside the notebook information terminal can be effectively utilized. Furthermore, a storage device according to one embodiment of the present invention may be used for storage of the notebook information terminal. This allows the storage capacity per unit area of the storage to be increased.

[0399] In the above description, a smartphone and a notebook information terminal are illustrated as examples of electronic devices in Figures 54A and 54B, respectively, but information terminals other than smartphones and notebook information terminals can also be applied. Examples of information terminals other than smartphones and notebook information terminals include PDAs (Personal Digital Assistants), desktop information terminals, and workstations.

[0400] [Game consoles] FIG. 54C illustrates a portable game console 5300, which is an example of a game console. The portable game console 5300 includes a housing 5301, a housing 5302, a housing 5303, a display portion 5304, a connection portion 5305, operation keys 5306, and the like. The housings 5302 and 5303 can be detached from the housing 5301. By attaching the connection portion 5305 of the housing 5301 to another housing (not shown), the video displayed on the display portion 5304 can be output to another video device (not shown). In this case, the housings 5302 and 5303 can each function as an operation portion. This allows multiple players to play a game simultaneously. A memory device or a semiconductor device according to one embodiment of the present invention can be incorporated into chips provided on the substrates of the housings 5301, 5302, and 5303.

[0401] 54D shows an example of a game machine, a stationary game machine 5400. A controller 5402 is connected to the stationary game machine 5400 wirelessly or via a wire.

[0402] By using a miniaturized microcontroller according to one embodiment of the present invention in a game console such as a portable game console 5300 or a stationary game console 5400, it is possible to effectively utilize the limited space inside the game console. Furthermore, a storage device or a semiconductor device according to one embodiment of the present invention may be used for storage in the portable game console. This allows the storage capacity per unit area of the storage to be increased.

[0403] 54C and 54D illustrate a portable game machine and a stationary game machine as examples of game machines, but game machines to which the microcontroller of one embodiment of the present invention is applied are not limited to these. Examples of game machines to which the microcontroller of one embodiment of the present invention is applied include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.

[0404] [Mainframe Computer] A memory device or a semiconductor device according to one embodiment of the present invention can be applied to a large-scale computer.

[0405] 54E is a diagram showing a supercomputer 5500, which is an example of a mainframe computer. FIG. 54F is a diagram showing a rack-mounted computer 5502 included in the supercomputer 5500.

[0406] The supercomputer 5500 includes a rack 5501 and a plurality of rack-mounted computers 5502. The plurality of computers 5502 are stored in the rack 5501. The computer 5502 is provided with a plurality of boards 5504, and a microcontroller according to one embodiment of the present invention can be mounted on the board. By using a miniaturized microcontroller according to one embodiment of the present invention, the limited space of a large computer can be effectively utilized. Furthermore, a storage device or a semiconductor device according to one embodiment of the present invention may be used for storage of the large computer. This allows the storage capacity per unit area of the storage to be increased.

[0407] 54E and 54F illustrate a supercomputer as an example of a mainframe computer, but the mainframe computer to which the microcontroller according to an embodiment of the present invention is applied is not limited to this. Examples of mainframe computers to which the microcontroller according to an embodiment of the present invention is applied include computers that provide services (servers) and mainframe computers (mainframes).

[0408] [electric appliances] 54G shows an example of an electric appliance, an electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

[0409] A memory device or a semiconductor device according to one embodiment of the present invention can also be applied to an electric refrigerator-freezer 5800. For example, by applying a miniaturized microcontroller according to one embodiment of the present invention to the electric refrigerator-freezer 5800, the limited space of the electric refrigerator-freezer can be effectively utilized.

[0410] Although electric refrigerator-freezers have been described as an example of electrical appliances, other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audio-visual equipment.

[0411] The electronic devices, functions, effects, and the like described in this embodiment can be combined as appropriate with descriptions of other electronic devices.

[0412] This embodiment mode can be implemented in appropriate combination with any of the structures described in other embodiment modes. [Explanation of symbols]

[0413] 100 memory device, 110 memory cell array, 117 insulator, 118 insulator, 119 conductor, 120 memory string, 121 substrate, 122 conductor, 123 insulator, 124 insulator, 125 semiconductor, 126 insulator, 127 semiconductor, 128 conductor, 129 insulator, 130 conductor, 132 insulator, 134 conductor, 136 conductor, 137 conductor, 138 insulator, 141 opening, 150 insulator, 152 insulator, 156 insulator, 161 conductor, 162 conductor, 163 conductor, 1 64 conductor, 171 conductor, 172 conductor, 173 conductor, 174 conductor, 179 material, 180 material, 181 material, 182 material, 183 material, 184 conductor, 185 insulator, 186 insulator, 187 conductor, 188 insulator, 189 insulator, 200 semiconductor device, 2000 driver circuit, 2001 WSL driver, 2002 WBL driver, 2003 RSL driver, 2004 RBL driver, 2005 WWL driver, 2006 RWL driver, 2007 SEL driver

Claims

1. a first conductor; a first insulator above the first conductor; a second conductor above the first insulator; a second insulator above the second conductor; a third conductor above the second insulator; a third insulator above the third conductor; a fourth conductor above the third insulator; a fourth insulator above the fourth conductor; a fifth conductor above the fourth insulator; a sixth conductor above the fifth conductor; a sixth insulator above the sixth conductor; a seventh conductor above the sixth insulator; an eighth conductor; and a seventh insulator; and an eighth insulator; and a first semiconductor; and a second semiconductor; At least the fourth conductor and the fifth conductor each have an opening; the seventh insulator, the first semiconductor, the eighth insulator, and the second semiconductor are provided in this order from an inner side surface in each of the openings, the eighth conductor is provided between the first semiconductor and the eighth insulator in a region between the fourth conductor and the eighth insulator; the first semiconductor contacts an upper surface of the second conductor and a side surface of the sixth conductor; the second semiconductor contacts an upper surface of the first conductor and a side surface of the seventh conductor; the third conductor has a region overlapping with the fourth conductor and a region not overlapping with the fourth conductor, the fourth conductor has a region overlapping with the fifth conductor and a region not overlapping with the fifth conductor, the fifth conductor has a region overlapping with the sixth conductor and a region not overlapping with the sixth conductor, the sixth conductor has a region overlapping with the seventh conductor and a region not overlapping with the seventh conductor, the fourth conductor functions as a gate electrode of a first transistor; the second semiconductor has a region in which a channel of the first transistor is formed; the fifth conductor functions as a gate electrode of a second transistor; The first semiconductor has a region in which a channel of the second transistor is formed.

2. In claim 1, A memory device in which the seventh insulator, the first semiconductor, the eighth conductor, the eighth insulator, and the second semiconductor are provided as concentric layers inside the opening of the fourth conductor.

3. In claim 1 or claim 2, a fifth conductor, the seventh insulator, the first semiconductor, the eighth insulator, and the second semiconductor being provided as concentric layers inside the opening of the fifth conductor;

4. In any one of claims 1 to 3, The memory device, wherein the first semiconductor is a first oxide semiconductor.

5. In claim 4, The first oxide semiconductor contains indium, an element M (the element M is one or more selected from aluminum, gallium, yttrium, tin, and titanium), and zinc.

6. In any one of claims 1 to 5, The memory device, wherein the second semiconductor is a second oxide semiconductor.

7. In claim 6, The second oxide semiconductor contains indium, an element M (the element M is one or more selected from aluminum, gallium, yttrium, tin, and titanium), and zinc.

8. In any one of claims 1 to 7, the openings are also provided in the second conductor and the sixth conductor; the second insulator is provided between the second conductor and the second semiconductor; The eighth insulator is provided between the sixth conductor and the second semiconductor.

Images