Memory device and method of manufacturing the same

Abstract

To provide a memory device in which the structural stability of a stacked body can be ensured.SOLUTION: A memory device 100 according to an embodiment of the present invention may include: a cell region CR; a contact region CTR extending from the cell region CR in a first direction X, and including a stepped structure arranged along a second direction Y that intersects the first direction X; and a support pattern SP separating the contact region CTR into a first contact region GCTR coupled to the cell region CR and a second contact region PCTR separated from the cell region CR. The support pattern SP may include sub-support patterns SSP1-SSP4 extending in the first direction X and contacting both sides of the second contact region PCTR. At least one of the sub-support patterns SSP1-SSP4 may be formed to overlap with at least a portion of the stepped structure, and the second contact region PCTR may be formed not to overlap with the stepped structure.SELECTED DRAWING: Figure 4b

Description

[Technical Field]

[0001] The present invention relates to a memory device and a manufacturing method thereof, and more particularly to a memory device including a memory block with a three-dimensional structure and a manufacturing method thereof. [Background technology]

[0002] Memory devices may include nonvolatile memory devices that retain stored data even when power is cut off. Nonvolatile memory devices are classified into two-dimensional and three-dimensional structures depending on the arrangement of memory cells. Memory cells of nonvolatile memory devices with two-dimensional structures may be arranged in a single layer on a substrate, while memory cells of nonvolatile memory devices with three-dimensional structures may be stacked vertically on a substrate. Because the integration density of nonvolatile memory devices with three-dimensional structures is higher than that of nonvolatile memory devices with two-dimensional structures, electronic devices using nonvolatile memory devices with three-dimensional structures have been increasing in recent years. Summary of the Invention [Problem to be solved by the invention]

[0003] SUMMARY OF THE INVENTION An embodiment of the present invention provides a memory device and a method for manufacturing the same that can ensure the structural stability of a stack. [Means for solving the problem]

[0004] A memory device according to an embodiment of the present invention may include a cell region, a contact region including a staircase structure extending from the cell region in a first direction and arranged along a second direction intersecting the first direction, and a support pattern separating the contact region into a first contact region connected to the cell region and a second contact region separated from the cell region. Each of the support patterns may include sub-support patterns extending in the first direction and contacting both sides of the second contact region. Any one of the sub-support patterns may overlap at least a portion of the staircase structure, and the second contact region may not overlap the staircase structure.

[0005] A method for manufacturing a memory device according to an embodiment of the present invention may include: forming a pre-laminate including first and second material layers, forming a cell plug in a cell region of the pre-laminate, forming a staircase structure arranged along a second direction intersecting the first direction in a contact region extending from the cell region in a first direction, and forming a support pattern including sub-support patterns that penetrate the contact region and each extend in the first direction, thereby separating the contact region into a first contact region and a second contact region surrounded by the support pattern. In forming the support pattern, any one of the sub-support patterns may overlap at least a portion of the staircase structure, and the second contact region may be formed so as not to overlap the staircase structure. [Effects of the Invention]

[0006] This technology can ensure the stability of the stack by adjusting the step structure of the stack in the contact region and the position of the support pattern. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a diagram illustrating a memory device according to an embodiment of the present invention; [Figure 2] 1 is a diagram for schematically illustrating a memory device according to an embodiment of the present invention; [Figure 3a] 1 is a diagram illustrating a cell region and a contact region according to an embodiment of the present invention; [Figure 3b] 1 is a diagram illustrating a cell region and a contact region according to an embodiment of the present invention; [Figure 3c] 1 is a diagram illustrating a cell region and a contact region according to an embodiment of the present invention; [Figure 4a] 5A and 5B are diagrams illustrating support patterns superimposed on the staircase structure according to the first embodiment of the present invention. [Figure 4b]5A and 5B are diagrams illustrating support patterns superimposed on the staircase structure according to the first embodiment of the present invention. [Figure 5a] 10A and 10B are diagrams illustrating support patterns superimposed on a staircase structure according to a second embodiment of the present invention. [Figure 5b] 10A and 10B are diagrams illustrating support patterns superimposed on a staircase structure according to a second embodiment of the present invention. [Figure 6a] 1A to 1C are diagrams illustrating a method of manufacturing a memory device according to an embodiment of the present invention; [Figure 6b] 1A to 1C are diagrams illustrating a method of manufacturing a memory device according to an embodiment of the present invention; [Figure 6c] 1A to 1C are diagrams illustrating a method of manufacturing a memory device according to an embodiment of the present invention; [Figure 6d] 1A to 1C are diagrams illustrating a method of manufacturing a memory device according to an embodiment of the present invention; [Figure 6e] 1A to 1C are diagrams illustrating a method of manufacturing a memory device according to an embodiment of the present invention; [Figure 7] 1 is a diagram illustrating a memory card system to which a memory device according to the present invention is applied; [Figure 8] 1 is a diagram illustrating an SSD (Solid State Drive) system to which a memory device according to the present invention is applied; DETAILED DESCRIPTION OF THE INVENTION

[0008] Specific structural or functional descriptions of embodiments according to the inventive concepts disclosed in this specification or application are provided solely for purposes of illustrating embodiments according to the inventive concepts, and embodiments according to the inventive concepts may be embodied in various forms and should not be construed as being limited to the embodiments described in this specification or application.

[0009] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings to enable a person skilled in the art to which the present invention pertains to carry out the technical concept of the present invention.

[0010] FIG. 1 is a diagram illustrating a memory device according to an embodiment of the present invention.

[0011] Referring to FIG. 1, a memory device 100 may include a memory cell array 110, a peripheral circuit 170, and a control circuit 180.

[0012] The memory cell array 110 may include first to i-th memory blocks BLK1 to BLKi. Each of the first to i-th memory blocks BLK1 to BLKi may include memory cells capable of storing data. A drain select line DSL, a word line WL, a source select line SSL, and a source line SL may be connected to each of the first to i-th memory blocks BLK1 to BLKi, and a bit line BL may be commonly connected to the first to i-th memory blocks BLK1 to BLKi.

[0013] The first to i-th memory blocks BLK1 to BLKi may be formed in a three-dimensional structure. A memory block having a three-dimensional structure may include memory cells stacked in a direction perpendicular to a substrate.

[0014] A memory cell can store one or more bits of data depending on the programming method. For example, a method in which one bit of data is stored in one memory cell is called a single-level cell method, and a method in which two bits of data are stored in one memory cell is called a multi-level cell method. A method in which three bits of data are stored in one memory cell is called a triple-level cell method, and a method in which four bits of data are stored is called a quad-level cell method. In addition, five or more bits of data can be stored in one memory cell.

[0015] The peripheral circuit 170 may be configured to perform a program operation to store data in the memory cell array 110, a read operation to output data stored in the memory cell array 110, and an erase operation to erase data stored in the memory cell array 110. For example, the peripheral circuit 170 may include a voltage generator 120, a row decoder 130, a page buffer group 140, a column decoder 150, and an input / output circuit 160.

[0016] The voltage generator 120 can generate various operating voltages Vop used for program, read, or erase operations in response to an operation code OPCD. For example, the voltage generator 120 can be configured to generate program voltages, turn-on voltages, turn-off voltages, negative voltages, precharge voltages, verify voltages, read voltages, pass voltages, or erase voltages in response to the operation code OPCD. The operating voltages Vop generated by the voltage generator 120 can be applied to the drain select line DSL, word line WL, source select line SSL, and source line SL of a selected memory block via a row decoder 130.

[0017] The program voltage is a voltage applied to a selected word line from the word lines WL during a program operation and can be used to raise the threshold voltage of a memory cell connected to the selected word line. The turn-on voltage can be applied to a drain select line DSL or a source select line SSL and can be used to turn on a drain select transistor or a source select transistor. The turn-off voltage can be applied to a drain select line DSL or a source select line SSL and can be used to turn off a drain select transistor or a source select transistor. For example, the turn-off voltage can be set to 0V. The pre-charge voltage is a voltage higher than 0V and can be applied to a bit line during a read operation. The verify voltage can be used during a verify operation to determine whether the threshold voltage of a selected memory cell has risen to a target level. The verify voltage can be set to various levels depending on the target level and can be applied to a selected word line.

[0018] The read voltage may be applied to a selected word line during a read operation of a selected memory cell. For example, the read voltage may be set to various levels depending on a program scheme for the selected memory cell. The pass voltage is a voltage applied to unselected word lines among the word lines WL during a program or read operation and may be used to turn on memory cells connected to the unselected word lines. The erase voltage may be applied to a source line SL during an erase operation to erase memory cells included in a selected memory block.

[0019] The row decoder 130 may be configured to transmit an operating voltage Vop to drain select lines DSL, word lines WL, source select lines SSL, and source lines SL connected to a memory block selected in response to a row address RADD. For example, the row decoder 130 may be connected to the voltage generator 120 via global lines, and may be connected to the first through i-th memory blocks BLK1 through BLKi via the drain select lines DSL, word lines WL, source select lines SSL, and source lines SL.

[0020] The page buffer group 140 may include page buffers (not shown) connected to the first through i-th memory blocks BLK1 through BLKi, respectively. Each of the page buffers (not shown) may be connected to the first through i-th memory blocks BLK1 through BLKi via a bit line BL. During a read operation, the page buffer (not shown) may sense the current or voltage of the bit line, which varies depending on the threshold voltage of the selected memory cell, in response to a page buffer control signal PBSIG, and temporarily store the sensed data.

[0021] The column decoder 150 may be configured to transmit data between the page buffer group 140 and the input / output circuit 160 in response to a column address CADD. For example, the column decoder 150 may be connected to the page buffer group 140 via column lines CL and may transmit an enable signal via the column lines CL. A page buffer (not shown) included in the page buffer group 140 may receive or output data via data lines DL in response to the enable signal.

[0022] The input / output circuit 160 may be configured to receive or output a command CMD, an address ADD, or data via the input / output lines I / O. For example, the input / output circuit 160 may transmit a command CMD and an address ADD received from an external controller to the control circuit 180 via the input / output lines I / O, and may transmit data received from an external controller to the page buffer group 140 via the input / output lines I / O. Alternatively, the input / output circuit 160 may output data transmitted from the page buffer group 140 to the external controller via the input / output lines I / O.

[0023] The control circuit 180 may output at least one of an operation code OPCD, a row address RADD, a page buffer control signal PBSIG, or a column address CADD in response to the command CMD and the address ADD. For example, if the command CMD input to the control circuit 180 corresponds to a program operation, the control circuit 180 may control the peripheral circuit 170 to perform a program operation on a memory block selected by the address ADD. If the command CMD input to the control circuit 180 corresponds to a read operation, the control circuit 180 may control the peripheral circuit 170 to perform a read operation on a memory block selected by the address and output the read data. If the command CMD input to the control circuit 180 corresponds to an erase operation, the control circuit 180 may control the peripheral circuit 170 to perform an erase operation on a selected memory block.

[0024] FIG. 2 is a diagram for schematically illustrating a memory device according to an embodiment of the present invention.

[0025] 2, the memory device 100 may include a peripheral circuit structure PC and memory blocks BLK1 to BLKi arranged on a substrate SUB. The memory blocks BLK1 to BLKi may overlap the peripheral circuit structure PC.

[0026] The substrate SUB may be a single-crystal semiconductor film, such as a bulk silicon substrate, a silicon-on-insulator substrate, a germanium substrate, a germanium-on-insulator substrate, a silicon-germanium substrate, or an epitaxial thin film formed by selective epitaxial growth.

[0027] The peripheral circuit structure PC may include a row decoder 130, a column decoder 150, a page buffer group 140, and a control circuit 180, which constitute circuits for controlling the operation of the memory blocks BLK1 to BLKi. For example, the peripheral circuit structure PC may include NMOS transistors, PMOS transistors, resistors, and capacitors electrically connected to the memory blocks BLK1 to BLKi. The peripheral circuit structure PC may be disposed between the substrate SUB and the memory blocks BLK1 to BLKi.

[0028] Each of the memory blocks BLK1 to BLKi may include a source structure, a bit line, a cell string electrically connected to the source structure and the bit line, a word line electrically connected to the cell string, and a select line electrically connected to the cell string. Each of the cell strings may include a memory cell and a select transistor connected in series by a cell plug. Each of the select lines may be used as the gate electrode of the corresponding select transistor, and each of the word lines may be used as the gate electrode of the corresponding memory cell.

[0029] In another embodiment, the substrate SUB, the peripheral circuit structure PC, and the memory blocks BLK1 to BLKi may be stacked in the reverse order to that shown in Figure 2. For example, the peripheral circuit structure PC may be disposed on the memory blocks BLK1 to BLKi.

[0030] In another embodiment, the peripheral circuit structure PC may be arranged on a part of the substrate SUB that does not overlap with the memory blocks BLK1 to BLKi, unlike the example shown in Figure 2. For example, the peripheral circuit structure PC and the memory blocks BLK1 to BLKi may be arranged on regions of the substrate SUB that do not overlap with each other.

[0031] 3a to 3c are diagrams illustrating a cell region and a contact region according to an embodiment of the present invention. FIG. 3a is a diagram illustrating a layout of a memory device according to an embodiment of the present invention. FIG. 3b is a cross-sectional view showing a cross section AA' of FIG. 3a. FIG. 3c is a cross-sectional view showing a cross section BB' of FIG. 3a.

[0032] Referring to FIG. 3A, the memory device 100 may include slits SLI. The slits SLI may extend in the X direction. The slits SLI may be spaced apart from each other in the Y direction. The slits SLI may insulate memory blocks (e.g., memory blocks BLK1 to BLKi in FIG. 2) from each other. For example, a first memory block BLK1 and a second memory block BLK2 may be separated based on any one of the slits SLI.

[0033] The memory device 100 may include a cell region CR and a contact region CTR. The contact region CTR may be located in the X direction of the cell region CR. The contact region CTR may extend from the cell region CR in the X direction. A cell plug CPL may be located in the cell region CR.

[0034] A support pattern SP may be arranged in the contact region CTR. The support pattern SP may divide the contact region CTR into a first contact region GCTR and a second contact region PCTR. The support pattern SP may surround at least three sides of the second contact region PCTR (e.g., in the Y direction, the side opposite the Y direction, and the side opposite the X direction). For example, each support pattern SP may include sub-support patterns SSP extending in the X direction. The sub-support patterns SSP may contact both sides of the second contact region PCTR in the Y direction. The first contact region GCTR may be located in the Y direction and the side opposite the Y direction of the second contact region PCTR across the support pattern SP. That is, the support pattern SP may be arranged between the second contact region PCTR and the first contact region GCTR. The support pattern SP may also be arranged between the second contact region PCTR and the cell region CR.

[0035] The first contact region GCTR may be connected to the cell region CR. The first contact region GCTR may extend from the cell region CR. The first contact region GCTR may be electrically connected to the cell region CR. The first contact GCT may be located in the first contact region GCTR. The first contact GCT may be connected to a gate line (e.g., the drain select line DSL, the word line WL, and the source select line SSL in FIG. 1), respectively.

[0036] The second contact region PCTR may be isolated from the cell region CR. The second contact region PCTR may be insulated from the cell region CR and the first contact region GCTR by the support pattern SP. The second contact PCT may be located in the second contact region PCTR. The second contact PCT may be connected to a peripheral circuit structure (e.g., the peripheral circuit structure PC in FIG. 2).

[0037] 3b, the memory device 100 may include a gate stack GST and a dummy stack DST. The cell region CR of the memory device 100 may include the gate stack GST, and the second contact region PCTR may include the dummy stack DST. The gate stack GST may be located in the cell region CR, and the dummy stack DST may be located in the second contact region PCTR. The gate stack GST may be spaced apart from the dummy stack DST across a support pattern SP. An upper insulating film UIL may be disposed on the gate stack GST and the dummy stack DST. The upper insulating film UIL may cover the gate stack GST and the dummy stack DST.

[0038] The gate stack GST may include a conductive film CD and an interlayer insulating film IIL. The conductive film CD and the interlayer insulating film IIL may be alternately stacked along the Z direction. The conductive film CD may be made of at least one of tungsten (W), cobalt (Co), nickel (Ni), molybdenum (Mo), silicon (Si), or polysilicon (poly-Si). The interlayer insulating film IIL may be made of an oxide film (e.g., a silicon oxide film). The conductive film CD may correspond to a gate line (e.g., a drain select line DSL, a word line WL, or a source select line SSL in FIG. 1).

[0039] The dummy stack DST may include a sacrificial film SF and an interlayer insulating film IIL. The sacrificial film SF and the interlayer insulating film IIL may be alternately stacked along the Z direction. The sacrificial film SF may include an insulator having an etching selectivity with respect to the interlayer insulating film IIL. For example, the interlayer insulating film IIL may include an oxide film (e.g., a silicon oxide film), and the sacrificial film SF may include a nitride film. The sacrificial film SF of the dummy stack DST may be located at the same level as the conductive film CD of the gate stack GST. The sacrificial film SF may be spaced apart from the conductive film CD across the support pattern SP. The interlayer insulating film IIL of the dummy stack DST may be located at the same level as the interlayer insulating film IIL of the gate stack GST and may include the same material.

[0040] A source structure SC may be disposed below the gate stack GST and the dummy stack DST. The source structure SC may include an upper source structure USC, an interlayer source structure FSC, and a lower source structure LSC. The interlayer source structure FSC may be disposed on the lower source structure LSC, and the upper source structure USC may be disposed on the interlayer source structure FSC. Each of the upper source structure USC, the interlayer source structure FSC, and the lower source structure LSC may include a semiconductor material (e.g., silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), aluminum gallium arsenide (AlGaAs), and mixtures thereof). Each of the upper source structure USC, the interlayer source structure FSC, and the lower source structure LSC may include at least one of n-type impurities and p-type impurities. For example, at least one of the upper source structure USC, the interlayer source structure FSC, and the lower source structure LSC may include a polysilicon film doped with n-type impurities.

[0041] An insulating pattern IP may be disposed below the dummy stacked structure DST. The insulating pattern IP may overlap at least a portion of the dummy stacked structure DST. The insulating pattern IP may penetrate the source structure SC. The insulating pattern IP may be located at the same level as the source structure SC. The upper surface of the insulating pattern IP may be located at the same level as the upper surface of the upper source structure USC, and the lower surface of the insulating pattern IP may be located at the same level as the lower surface of the lower source structure LSC. The insulating pattern IP may include an insulator (e.g., oxide, nitride).

[0042] A peripheral circuit structure PC and a substrate SUB may be located below the source structure SC and the insulating pattern IP. The peripheral circuit structure PC may be located on the substrate SUB. The peripheral circuit structure PC may include transistors TR, peripheral contact plugs PPL, and peripheral lines PLN. The transistors TR, peripheral contact plugs PPL, and peripheral lines PLN may have various patterns depending on the configuration of the peripheral circuit. For example, the number or positions of the transistors TR, peripheral contact plugs PPL, and peripheral lines PLN may vary. A lower insulating film LIL may be located between the transistors TR, peripheral contact plugs PPL, and peripheral lines PLN. For example, the transistors TR, peripheral contact plugs PPL, and peripheral lines PLN may be formed inside the lower insulating film LIL.

[0043] The cell plug CPL may be formed in the cell region CR. The cell plug CPL may penetrate the gate stack GST. The cell plug CPL may extend in the Z direction. A memory cell and a select transistor may be formed at each intersection of the cell plug CPL and the conductive layer CD.

[0044] The cell plug CPL may include a memory film ML, a channel film CH, a core pillar CO, and a capping film CAP. The memory film ML may be cylindrical. The memory film ML may be in contact with the gate stack GST. Although not shown, the memory film ML may include a blocking film, a charge trapping film, and a tunnel insulating film. The channel film CH may be formed along the inner wall of the memory film ML. The core pillar CO may be cylindrical and surrounded by the channel film CH. The capping film CAP may be connected to the channel film CH on the core pillar CO.

[0045] The blocking film and tunnel insulating film included in the memory film ML may be made of an oxide film (e.g., a silicon oxide film) or an oxynitride film (e.g., a silicon oxynitride film), or a combination thereof. The charge trapping film included in the memory film ML may include a nitride film or a variable resistance material. The channel film CH and the capping film CAP may be made of an undoped silicon film or a doped silicon film. Since the capping film CAP and the channel film CH are made of the same material or the same type of material, their interface may not be clearly observed. The core pillar CO may be made of an insulating film or a conductive film.

[0046] The cell plug CPL may be in contact with the source structure SC. The cell plug CPL may extend into the source structure SC through the gate stack GST. The cell plug CPL may be in contact with the upper source structure USC and the interlayer source structure FSC, and may extend into the lower source structure LSC. The memory film ML may be disposed between the channel film CH and the upper source structure USC, and between the channel film CH and the lower source structure LSC. The memory film ML may not be disposed between the channel film CH and the interlayer source structure FSC. Therefore, the channel film CH may be in direct contact with the interlayer source structure FSC.

[0047] The second contact PCT may be formed in the second contact region PCTR. The second contact PCT may penetrate the dummy stack DST. The second contact PCT may penetrate the sacrificial film SF and the interlayer insulating film IIL of the dummy stack DST. The second contact PCT may penetrate the insulating pattern IP. The second contact PCT may be connected to the peripheral circuit structure PC. For example, the second contact PCT may be directly connected to the peripheral line PLN of the peripheral circuit structure PC. The second contact PCT may be understood as a peripheral circuit connecting contact. The second contact PCT may include a conductor.

[0048] In FIG. 3c, the description of the configurations described in relation to FIGS. 3a and 3b may be omitted or simplified.

[0049] The gate stack GST may extend from the cell region CR to the first contact region GCTR. The first contact region GCTR may include the gate stack GST. The gate stack GST may include a staircase structure arranged along the X direction in the first contact region GCTR. The first contact region GCTR may include a staircase structure arranged along the X direction. For example, the conductive layers CD included in the gate stack GST may have different lengths in the X direction. In FIG. 3c, the conductive layers CD included in the gate stack GST may be referred to as the first conductive layer CD1, the second conductive layer CD2, and the third conductive layer CD3, starting from the uppermost conductive layer CD. The first conductive layer CD1 may have a shorter length in the X direction than the second conductive layer CD2, and the second conductive layer CD2 may have a shorter length in the X direction than the third conductive layer CD3. The second conductive layer CD2 may protrude further in the X direction than the first conductive layer CD1. The third conductive layer CD3 may protrude further in the X direction than the second conductive layer CD2. Ends of the conductive layers CD may be exposed on the gate stack GST. For example, an end portion of the first conductive film CD1, an end portion of the second conductive film CD2, and an end portion of the third conductive film CD3 may contact the upper insulating film UIL. Although not shown, the conductive film CD disposed below the third conductive film CD3 may also include a staircase structure arranged along the X direction. In this disclosure, when describing the staircase structure, the conductive film CD (or the sacrificial film SF) will be mainly described. However, as shown in FIG. 3c, each staircase may include the conductive film CD (or the sacrificial film SF) and the interlayer insulating film IIL. That is, even if a description that each staircase included in the staircase structure includes the interlayer insulating film IIL is omitted, it can be understood that each staircase includes the interlayer insulating film IIL.

[0050] The first contacts GCT may be formed in the first contact region GCTR. The first contacts GCT may be connected to the conductive films CD of the gate stack GST. The first contacts GCT may be in contact with the ends of the conductive films CD. For example, the first contacts GCT1, GCT2, and GCT3 may be in direct contact with the first to third conductive films CD1, CD2, and CD3, respectively. The first contacts GCT may be understood as gate line connecting contacts. The first contacts GCT may include a conductor.

[0051] 4a and 4b are diagrams illustrating a support pattern superimposed on a staircase structure according to a first embodiment of the present invention. Fig. 4a is a cross-sectional view showing a cross section CC' of Fig. 3a. Fig. 4b is a cross-sectional view showing a cross section DD' of Fig. 3a. Of the configurations shown in Figs. 4a and 4b, the configurations described in relation to Figs. 3a to 3c may be omitted or simplified in their description.

[0052] 4a and 4b, each of the contact regions CTR may be divided into a first contact region GCTR and a second contact region PCTR by a support pattern SP (e.g., sub-support patterns SSP1 to SSP4). The support pattern SP (e.g., sub-support patterns SSP1 to SSP4) may be disposed between the first contact region GCTR and the second contact region PCTR. The first contact region GCTR and the second contact region PCTR may be spaced apart by the support pattern SP. The first contact region GCTR may be disposed adjacent to the second contact region PCTR across the support pattern SP. The first contact region GCTR may be located on both sides of the second contact region PCTR. For example, the first contact region GCTR may be located in the Y direction of the second contact region PCTR and in the opposite direction to the Y direction.

[0053] The contact regions CTR1 and CTR2 included in different memory blocks (e.g., the first and second memory blocks BLK1 and BLK2 in FIG. 3a) may be separated from each other by slits SLI. The contact regions CTR1 and CTR2 may be insulated from each other by the slits SLI. The slits SLI may penetrate the upper insulating film UIL and the gate stack GST and extend into the source structure SC. The slits SLI may be made of a single film (e.g., a silicon film, an insulating film) or a multi-layer film (e.g., a conductive film surrounded by an insulating film, a silicon film surrounded by an insulating film).

[0054] Comparing FIGS. 4a and 4b, the contact region CTR may include a staircase structure arranged along the X direction. As described with reference to FIG. 3c, the third conductive film CD3 protrudes further in the X direction than the second conductive film CD2, so the second conductive film CD2 shown in FIG. 4a may not be shown in FIG. 4b. Similarly, the third sacrificial film SF3 protrudes further in the X direction than the second sacrificial film SF2, so the second sacrificial film SF2 shown in FIG. 4a may not be shown in FIG. 4b. When describing the staircase structure of the present disclosure, a conductive film and a sacrificial film (e.g., the second conductive film CD2 and the second sacrificial film SF2) arranged at the same level may be referred to as a stacked film (e.g., the second stacked film CD2, SF2). For example, the length of the third stacked film CD3, SF3 in the X direction may be longer than the length of the second stacked film CD2, SF2 in the X direction.

[0055] 4a and 4b, the contact region CTR may include a staircase structure arranged in not only the X direction but also the Y direction. At least some of the stacked films CD and SF included in the contact region CTR may include a staircase structure arranged in the Y direction. For example, at least some of the stacked films CD and SF may have different lengths in the Y direction. In the contact region CTR1 on the right side of FIG. 4a, the third stacked films CD3 and SF3 may protrude further in the Y direction from the second stacked films CD2 and SF2, the fourth stacked films CD4 and SF4 may protrude further in the Y direction from the third stacked films CD3 and SF3, and the fifth stacked films CD5 and SF5 may protrude further in the Y direction from the fourth stacked films CD4 and SF4. In the contact region CTR1 on the right side of Figure 4a, the second stacked films CD2 and SF2 may be shorter in the Y direction than the third stacked films CD3 and SF3, which may be shorter in the Y direction than the fourth stacked films CD4 and SF4, which may be shorter in the Y direction than the fifth stacked films CD5 and SF5. In the present disclosure, the number of stacked films CD and SF including a staircase structure arranged along the X or Y direction is not limited by the illustrations in Figures 4a and 4b. For example, while Figure 4a shows a four-layer stacked film having a staircase structure in the Y direction, five or more stacked films may also have a staircase structure in the Y direction.

[0056] The Y-direction staircase structure formed in the contact region CTR may have a symmetrical shape with respect to the slit SLI. For example, in the contact region CTR2 on the left side of FIG. 4a, the third stacked films CD3 and SF3 may protrude further in the opposite direction of the Y-direction from the second stacked films CD2 and SF2, the fourth stacked films CD4 and SF4 may protrude further in the opposite direction of the Y-direction from the third stacked films CD3 and SF3, and the fifth stacked films CD5 and SF5 may protrude further in the opposite direction of the Y-direction from the fourth stacked films CD4 and SF4. In the present disclosure, the specific shape of the staircase structure arranged along the X-direction or the Y-direction is not limited by the illustrations of FIGS. 4a and 4b. For example, although FIG. 4a illustrates the Y-direction staircase structure as having a symmetrical shape with respect to the slit SLI, the Y-direction staircase structure may have an asymmetrical shape with respect to the slit SLI, or may be formed only in one of the contact regions CTR1 or CTR2 with respect to the slit SLI.

[0057] The upper insulating film UIL may cover the gate stack GST and the dummy stack DST. Ends of the stack films CD and SF may be in contact with the upper insulating film UIL. For example, the upper insulating film UIL may be in contact with the top and side surfaces of the ends of the stack films CD and SF that form the staircase structure.

[0058] 4a and 4b, at least a portion of the support pattern SP may overlap at least a portion of a staircase structure arranged along the Y direction. One of the sub-support patterns SSP1 and SSP2 included in the contact region CTR1 on the right side of Fig. 4a may overlap at least a portion of the staircase structure in the Y direction. Also, one of the sub-support patterns SSP3 and SSP4 included in the contact region CTR2 on the left side of Fig. 4a may overlap at least a portion of the staircase structure in the Y direction. For example, the second sub-support pattern SSP2 and the third sub-support pattern SSP3 may overlap at least a portion of the staircase structure in the Y direction.

[0059] 4a and 4b, the second contact region PCTR may not overlap with the staircase structure arranged along the Y direction. In the contact region CTR1 on the right side of FIG. 4a, the second contact region PCTR may not overlap with the staircase structure in the Y direction. In the contact region CTR2 on the left side of FIG. 4a, the second contact region PCTR may not overlap with the staircase structure in the Y direction.

[0060] With reference to the contact region CTR1 on the right side of FIG. 4a, the staircase structure arranged along the Y direction overlaps the second sub-support pattern SSP2, but to avoid overlapping with the second contact region PCTR, the second sub-support pattern SSP2 may be disposed to overlap the starting point of the staircase structure arranged along the Y direction. The starting point of the staircase structure arranged along the Y direction may be the point where the end of the uppermost stacked film (e.g., the second stacked film CD2, SF2 in FIG. 4a) is located in a specific cross section. Therefore, in FIG. 4a, the second sub-support pattern SSP2 may overlap the ends of the second stacked film CD2, SF2. Also, in FIG. 4b, the second sub-support pattern SSP2 may overlap the ends of the third stacked film CD3, SF3.

[0061] 4a and 4b, the first contact regions GCTR may overlap other portions of the staircase structure arranged along the Y direction. Any one of the first contact regions GCTR included in the contact region CTR1 on the right side of FIG. 4a may overlap at least a portion of the staircase structure in the Y direction. Any one of the first contact regions GCTR included in the contact region CTR2 on the left side of FIG. 4a may overlap at least a portion of the staircase structure in the Y direction. For example, the first contact region GCTR arranged adjacent to the slit SLI shown in FIG. 4a may overlap at least a portion of the staircase structure in the Y direction.

[0062] At least some of the conductive films CD included in the first contact region GCTR may have different lengths in the Y direction. For example, referring to Fig. 4a, in the first contact region GCTR adjacent to the slit SLI, the second to fifth conductive films CD2 to CD5 may have different lengths in the Y direction. Also, referring to Fig. 4b, in the first contact region GCTR adjacent to the slit SLI, the third to sixth conductive films CD3 to CD6 may have different lengths in the Y direction.

[0063] The sacrificial films SF included in the second contact region PCTR may have the same length in the Y direction. For example, referring to Figure 4a, the second to fifth sacrificial films SF2 to SF5 and the sacrificial film SF located under the fifth sacrificial film SF5 may have the same length in the Y direction. Also, referring to Figure 4b, the third to sixth sacrificial films SF3 to SF6 and the sacrificial film SF located under the sixth sacrificial film SF6 may have the same length in the Y direction.

[0064] 5a and 5b are diagrams illustrating a support pattern superimposed on a staircase structure according to a second embodiment of the present invention. Fig. 5a is a cross-sectional view showing a cross section CC' of Fig. 3a. Fig. 5b is a cross-sectional view showing a cross section DD' of Fig. 3a. Of the components shown in Fig. 5a and 5b, the components described in relation to Figs. 3a, 3b, 3c, 4a, and 4b may be omitted or simplified in their description.

[0065] 5a and 5b, the contact region CTR can include a staircase structure arranged along the X direction. As described in FIG. 3c, the third conductive layer CD3 protrudes further in the X direction than the second conductive layer CD2, so the second conductive layer CD2 shown in FIG. 5a may not be shown in FIG. 5b.

[0066] 5a and 5b, the contact region CTR may include a staircase structure arranged along the Y direction. At least some of the conductive layers CD included in the contact region CTR may include a staircase structure arranged along the Y direction. For example, at least some of the conductive layers CD may have different lengths in the Y direction. In the contact region CTR1 on the right side of FIG. 5a, the third conductive layer CD3 may protrude further in the Y direction than the second conductive layer CD2, the fourth conductive layer CD4 may protrude further in the Y direction than the third conductive layer CD3, and the fifth conductive layer CD5 may protrude further in the Y direction than the fourth conductive layer CD4. In the contact region CTR1 on the right side of FIG. 5a, the second conductive layer CD2 may have a shorter length in the Y direction than the third conductive layer CD3, the third conductive layer CD3 may have a shorter length in the Y direction than the fourth conductive layer CD4, and the fourth conductive layer CD4 may have a shorter length in the Y direction than the fifth conductive layer CD5.

[0067] The Y-direction staircase structure formed in the contact region CTR may have a symmetrical shape with respect to the slit SLI. For example, in the contact region CTR2 on the left side of FIG. 5a, the third conductive layer CD3 may further protrude in the opposite direction of the Y-direction from the second conductive layer CD2, the fourth conductive layer CD4 may further protrude in the opposite direction of the Y-direction from the third conductive layer CD3, and the fifth conductive layer CD5 may further protrude in the opposite direction of the Y-direction from the fourth conductive layer CD4.

[0068] The upper insulating film UIL may cover the gate stack GST and the dummy stack DST. Ends of the stack films CD and SF may be in contact with the upper insulating film UIL. For example, the upper insulating film UIL may be in contact with the top and side surfaces of the ends of the conductive films CD constituting the staircase structure.

[0069] 5a and 5b, at least a portion of the support pattern SP may overlap at least a portion of a staircase structure arranged along the Y direction. One of the sub-support patterns SSP1 and SSP2 included in the contact region CTR1 on the right side of Fig. 5a may overlap at least a portion of the staircase structure in the Y direction. Also, one of the sub-support patterns SSP3 and SSP4 included in the contact region CTR2 on the left side of Fig. 5a may overlap at least a portion of the staircase structure in the Y direction. For example, the first sub-support pattern SSP1 and the fourth sub-support pattern SSP4 may overlap at least a portion of the staircase structure in the Y direction.

[0070] 5a and 5b, the second contact region PCTR may not overlap with the staircase structure arranged along the Y direction. In the contact region CTR1 on the right side of Fig. 5a, the second contact region PCTR may not overlap with the staircase structure in the Y direction. In the contact region CTR2 on the left side of Fig. 5a, the second contact region PCTR may not overlap with the staircase structure in the Y direction.

[0071] Referring to the contact region CTR1 on the right side of Figure 5a, the staircase structure arranged along the Y direction overlaps the first sub-support pattern SSP1, but in order to avoid overlapping with the second contact region PCTR, the first sub-support pattern SSP1 may be arranged to overlap the end of the staircase structure arranged along the Y direction. Therefore, in Figure 5a, the first sub-support pattern SSP1 may overlap an end of the fifth conductive layer CD5. Also, in Figure 5b, the first sub-support pattern SSP1 may overlap an end of the sixth conductive layer CD6.

[0072] 5a and 5b, the first contact regions GCTR may overlap other portions of the staircase structure arranged along the Y direction. Any one of the first contact regions GCTR included in the contact region CTR1 on the right side of FIG. 5a may overlap at least a portion of the staircase structure in the Y direction. Any one of the first contact regions GCTR included in the contact region CTR2 on the left side of FIG. 5a may overlap at least a portion of the staircase structure in the Y direction. For example, the first contact region GCTR arranged further away from the slit SLI shown in FIG. 5a may overlap at least a portion of the staircase structure in the Y direction.

[0073] At least some of the conductive films CD included in the first contact region GCTR may have different lengths in the Y direction. For example, referring to Fig. 5a, in the first contact region GCTR disposed further away from the slit SLI, the second to fifth conductive films CD2 to CD5 may have different lengths in the Y direction. Also, referring to Fig. 5b, in the first contact region GCTR disposed further away from the slit SLI, the third to sixth conductive films CD3 to CD6 may have different lengths in the Y direction.

[0074] The sacrificial films SF included in the second contact region PCTR may have the same length in the Y direction. For example, referring to Fig. 5a, the sixth to eighth sacrificial films SF6 to SF8 may have the same length in the Y direction. Also, referring to Fig. 5b, the seventh and eighth sacrificial films SF7 and SF8 may have the same length in the Y direction.

[0075] According to the present disclosure, the stability of the stack can be ensured by adjusting the relative positions of the support pattern SP and the staircase structure of the stack (e.g., the gate stack GST and the dummy stack DST) in the contact region CTR. By arranging the sub-support pattern SSP to partially overlap the staircase structure arranged along the Y direction in the contact region CTR and the second contact region PCTR so that the sub-support pattern SSP does not overlap, the structural stability of the second contact region PCTR can be ensured. For example, unlike the present disclosure, if a slope occurs between the dummy stack DST and the upper insulating film UIL in the second contact region PCTR, defects such as bending of the second contact region PCTR may occur due to differences in material properties between different materials (e.g., oxide and nitride). However, by eliminating the slope between the dummy stack DST and the upper insulating film UIL in the second contact region PCTR as in the present disclosure, the bending of the second contact region PCTR in the Y direction can be prevented.

[0076] 6a to 6e are diagrams illustrating a method for manufacturing a memory device according to an embodiment of the present invention. Figures 6a to 6e are cross-sectional views showing a cross section taken along CC' in Figure 3a. Figures 6a to 6e will be described based on the second embodiment of the first embodiment of Figure 4a and the second embodiment of Figure 5a. However, the following description can also be applied to the first embodiment, except for the relative positions of the staircase structure and the sub-support pattern SSP.

[0077] 6a, a preliminary source structure pSC may be formed by sequentially stacking a lower source structure LSC, a source sacrificial layer SSF, and an upper source structure USC on a substrate (e.g., the substrate SUB in FIGS. 3b and 3c) or a sacrificial substrate (not shown) including a peripheral circuit (e.g., the peripheral circuit structure PC in FIGS. 3b and 3c). The preliminary source structure pSC may further include at least one of a lower passivation layer LPL between the lower source structure LSC and the source sacrificial layer SSF, and an upper passivation layer UPL disposed between the source sacrificial layer SSF and the upper source structure USC. The preliminary source structure pSC may include a top surface extending in the X and Y directions, which intersect with each other.

[0078] Next, an insulating pattern IP may be formed through the preliminary source structure pSC. The insulating pattern IP may extend along the X direction. For example, the insulating pattern IP may be formed at a position overlapping at least a portion of the second contact region PCTR shown in FIG. 3a.

[0079] Next, a preliminary stack STK may be formed on the preliminary source structures pSC and the insulating pattern IP. The preliminary stack STK may include sacrificial layers SF and interlayer insulating layers IIL alternately stacked along the Z direction. For example, after the interlayer insulating layer IIL is stacked on the insulating pattern IP and the preliminary source structures pSC, the sacrificial layer SF may be stacked on the interlayer insulating layer IIL. The sacrificial layer SF may have an etch selectivity with respect to the interlayer insulating layer IIL. In one example, the interlayer insulating layer IIL may include an oxide such as a silicon oxide layer, and the sacrificial layer SF may include a nitride such as a silicon nitride layer.

[0080] Next, although not shown, a cell plug (e.g., cell plug CPL in FIGS. 3a to 3c) may be formed through the preliminary stack STK. For example, the cell plug may be formed in a cell region (e.g., cell region CR in FIG. 3a) of the preliminary stack STK. The cell plug may extend through the preliminary stack STK into the preliminary source structure pSC. For example, the cell plug may penetrate the upper source structure USC and the source sacrificial layer SSF.

[0081] Referring to FIG. 6b, staircase structures arranged along the X and Y directions may be formed in a contact region (e.g., the contact region CTR in FIG. 3a) of the preliminary laminate STK. The staircase structures arranged along the X and Y directions may be formed by etching a portion of the preliminary laminate STK. In one embodiment, the staircase structure may be formed such that an interlayer insulating film IIL and a sacrificial film SF stacked adjacent to each other form one staircase. For example, in FIG. 6b, any one sacrificial film SF and an interlayer insulating film IIL in contact with the lower surface of the sacrificial film SF may correspond to one staircase. Although FIG. 6b illustrates only the staircase structures arranged along the Y direction among the staircase structures included in the preliminary laminate STK, the preliminary laminate STK may also include staircase structures arranged along the X direction, as described with reference to FIGS. 3c, 4a, 4b, 5a, and 5b.

[0082] Next, an upper insulating film UIL may be formed to cover the preliminary laminate STK. The upper insulating film UIL may cover the staircase structure of the preliminary laminate STK. For example, the upper insulating film UIL may cover the staircase structure in the X and Y directions included in the preliminary laminate STK. Therefore, the upper insulating film UIL may be in direct contact with the ends of each staircase (e.g., the ends of the sacrificial film SF) included in the preliminary laminate STK.

[0083] Referring to FIG. 6c, a support pattern SP may be formed that penetrates a contact region (e.g., contact region CTR in FIG. 3a) of the preliminary laminate STK. The support pattern SP may include sub-support patterns SSP1 to SSP4 extending in the X direction. At least one of the sub-support patterns SSP1 to SSP4 may overlap at least a portion of a staircase structure along the Y direction. For example, the first sub-support pattern SSP1 and the fourth sub-support pattern SSP4 may overlap an end of the sacrificial layer SF in the Y direction. Furthermore, the sub-support patterns SSP1 to SSP4 may be formed such that a staircase structure along the Y direction is not located between the sub-support patterns SSP1 and SSP2 or between SSP3 and SSP4 included in one support pattern SP. For example, the end of the sacrificial layer SF in the Y direction may not be located between the first sub-support pattern SSP1 and the second sub-support pattern SSP2. Furthermore, the end of the sacrificial layer SF in the Y direction may not be located between the third sub-support pattern SSP3 and the fourth sub-support pattern SSP4. However, a staircase structure along the X direction can also be located between sub-support patterns SSP1 and SSP2, or between sub-support patterns SSP3 and SSP4 included in one support pattern SP.

[0084] By forming the support pattern SP in one region of the pre-layer stack STK, the contact region (e.g., the contact region CTR in FIG. 3a) of the pre-layer stack STK may be separated into a first contact region (e.g., the first contact region GCTR in FIG. 3a) and a second contact region (e.g., the second contact region PCTR in FIG. 3a). For example, the region between the first and second sub-support patterns SSP1 and SSP2 and the region between the third and fourth sub-support patterns SSP3 and SSP4 may be the second contact region (e.g., the second contact region PCTR in FIG. 3a). In addition, the region other than the second contact region (e.g., the second contact region PCTR in FIG. 3a) may be the first contact region (e.g., the first contact region GCTR in FIG. 3a). The second contact region (e.g., the second contact region PCTR in FIG. 3a) may be formed to be surrounded by the support pattern SP.

[0085] Referring to FIG. 6d, an opening OP may be formed through the pre-layer stack STK. A side surface of the source sacrificial layer SSF may be exposed through the opening OP. The source sacrificial layer SSF may be removed through the opening OP. Although not shown, a portion of the memory layer (e.g., the memory layer ML in FIG. 3b) of the cell plug (e.g., the cell plug CPL in FIG. 3b) may be removed through the opening OP. While the portion of the memory layer ML is removed through the opening OP, the upper passivation layer UPL and the lower passivation layer LPL may be removed. Then, an interlayer source structure FSC may be filled between the upper source structure USC and the lower source structure LSC through the opening OP. By filling the interlayer source structure FSC, a source structure SC including the upper source structure USC, the interlayer source structure FSC, and the lower source structure LSC may be formed.

[0086] In addition, a portion of the sacrificial film SF may be exposed through the opening OP. The sacrificial film SF exposed through the opening OP may be removed. For example, the sacrificial film SF located in the cell region CR and the first contact region GCTR of FIG. 3a may be removed. A conductive film CD may be filled into the space formed by the removal of the sacrificial film SF through the opening OP.

[0087] While a portion of the sacrificial film SF is removed, another portion of the sacrificial film SF that is not exposed through the opening OP may remain unremoved. For example, the sacrificial film SF located in the second contact region PCTR in FIG. 3a may not be removed because it is surrounded by the support pattern SP. The sacrificial film disposed between the first sub-support pattern SSP1 and the second sub-support pattern SSP2 may not be removed. In addition, the sacrificial film disposed between the third sub-support pattern SSP3 and the fourth sub-support pattern SSP4 may not be removed.

[0088] Therefore, a portion of the preliminary stack STK may be a gate stack GST including a conductive film CD and an interlayer insulating film IIL, and another portion of the preliminary stack STK may be a dummy stack DST including a sacrificial film SF and an interlayer insulating film IIL. Referring to FIG. 6d, the dummy stack DST may not include a staircase structure arranged along the Y direction, while the gate stack GST may include a staircase structure arranged along the Y direction. For example, in a region surrounded by each support pattern SP (e.g., the second contact region PCTR in FIG. 3a), the support patterns SP are formed so as not to overlap with the staircase structure along the Y direction, so the dummy stack DST may not include a staircase structure arranged along the Y direction. Also, in a region not surrounded by each support pattern SP (e.g., the first contact region GCTR in FIG. 3a), the support patterns SP are formed so as to overlap with the staircase structure along the Y direction, so the gate stack GST may include a staircase structure arranged along the Y direction. Although not shown, both the gate stack GST and the dummy stack DST may include a staircase structure along the X direction.

[0089] After a portion of the sacrificial film SF is replaced with the conductive film CD through the opening OP, a slit SLI may be formed inside the opening OP. The slit SLI may include at least one material filled in the opening OP.

[0090] 6e, a second contact PCT may be formed through the dummy stack DST. The second contact PCT may penetrate the upper insulating film UIL, the dummy stack DST, and the insulating pattern IP. The second contact PCT may be in direct contact with a peripheral circuit structure (e.g., the peripheral circuit structure PC in FIGS. 3b and 3c) located below the insulating pattern IP.

[0091] FIG. 7 is a diagram illustrating a memory card system to which the memory device of the present invention is applied.

[0092] Referring to FIG. 7, the memory card system 3000 includes a controller 3100, a memory device 3200, and a connector 3300.

[0093] The controller 3100 may be connected to the memory device 3200. The controller 3100 may be configured to access the memory device 3200. For example, the controller 3100 may be configured to control a program operation, a read operation, or an erase operation of the memory device 3200, or to control a background operation. The controller 3100 may be configured to provide an interface between the memory device 3200 and a host. The controller 3100 may be configured to run firmware for controlling the memory device 3200. For example, the controller 3100 may include components such as a random access memory (RAM), a processing unit, a host interface, a memory interface, and an error correction unit.

[0094] The controller 3100 can communicate with an external device via the connector 3300. The controller 3100 can communicate with an external device (e.g., a host) according to a specific communication standard. For example, the controller 3100 can be configured to communicate with an external device via at least one of various communication standards, such as Universal Serial Bus (USB), multimedia card (MMC), embedded MMC (eMMC), peripheral component interconnection (PCI), PCI-express (PCI-E), Advanced Technology Attachment (ATA), Serial-ATA, Parallel-ATA, small computer system interface (SCSI), enhanced small disk interface (ESDI), Integrated Drive Electronics (IDE), Firewire, Universal Flash Storage (UFS), WIFI, Bluetooth, or NVMe. For example, the connector 3300 can be defined by at least one of the various communication standards mentioned above.

[0095] Memory device 3200 may include multiple memory cells and may be configured similarly to memory device 100 shown in FIG.

[0096] The controller 3100 and the memory device 3200 may be integrated into a single semiconductor device to form a memory card, such as a PC card (PCMCIA, personal computer memory card international association), a CompactFlash card (CF), a SmartMedia card (SM, SMC), a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro, eMMC), an SD card (SD, miniSD, microSD, SDHC), or a universal flash storage device (UFS).

[0097] FIG. 8 is a diagram illustrating an SSD (Solid State Drive) system to which the memory device of the present invention is applied.

[0098] 8, an SSD system 4000 may include a host 4100 and an SSD 4200. The SSD 4200 may transmit and receive signals to and from the host 4100 via a signal connector 4001, and may receive power via a power connector 4002. The SSD 4200 may include a controller 4210, a plurality of memory devices 4221 to 422n, an auxiliary power supply 4230, and a buffer memory 4240.

[0099] The controller 4210 can control the plurality of memory devices 4221-422n in response to signals received from the host 4100. For example, the signals can be signals based on the interfaces of the host 4100 and the SSD 4200. For example, the signals can be signals defined by at least one of interfaces such as Universal Serial Bus (USB), multimedia card (MMC), embedded MMC (eMMC), peripheral component interconnection (PCI), PCI-express (PCI-E), Advanced Technology Attachment (ATA), Serial-ATA, Parallel-ATA, small computer system interface (SCSI), enhanced small disk interface (ESDI), Integrated Drive Electronics (IDE), Firewire, Universal Flash Storage (UFS), WIFI, Bluetooth, or NVMe.

[0100] The plurality of memory devices 4221-422n may include a plurality of memory cells configured to store data. Each of the plurality of memory devices 4221-422n may be configured similarly to the memory device 100 shown in Figure 1. The plurality of memory devices 4221-422n may communicate with the controller 4210 via channels CH1-CHn.

[0101] The auxiliary power supply 4230 can be connected to the host 4100 via a power connector 4002. The auxiliary power supply 4230 can receive a power supply voltage from the host 4100 and charge. The auxiliary power supply 4230 can provide a power supply voltage to the SSD 4200 when power supply from the host 4100 is not smooth. For example, the auxiliary power supply 4230 can be located inside the SSD 4200 or outside the SSD 4200. For example, the auxiliary power supply 4230 can be located on a main board and provide auxiliary power to the SSD 4200.

[0102] The buffer memory 4240 can operate as a buffer memory for the SSD 4200. For example, the buffer memory 4240 can temporarily store data received from the host 4100 or data received from the plurality of memory devices 4221-422n, or temporarily store metadata (e.g., a mapping table) of the memory devices 4221-422n. The buffer memory 4240 can include volatile memory such as DRAM, SDRAM, DDR SDRAM, or LPDDR SDRAM, or non-volatile memory such as FRAM (registered trademark), ReRAM, STT-MRAM, or PRAM. [Explanation of symbols]

[0103] GST Gate Stack CD conductive film IIL Interlayer insulating film DST dummy laminate SF sacrificial film GCTR First Contact Area PCTR 2nd contact area SLI Slit SP Support Pattern SSP Sub-Support Pattern SC Source Structure USC upper source structure FSC interlayer source structure LSC lower source structure IP insulation pattern

Claims

1. A cell area; a contact region including a staircase structure extending from the cell region in a first direction and arranged along a second direction intersecting the first direction; a support pattern that separates the contact region into a first contact region connected to the cell region and a second contact region separated from the cell region, each of the support patterns includes a sub-support pattern extending in the first direction and contacting both sides of the second contact region; Any one of the sub-support patterns overlaps at least a portion of the staircase structure; The second contact region does not overlap the staircase structure.

2. The memory device of claim 1 , wherein the contact region further includes a staircase structure arranged along the first direction.

3. The cell region and the first contact region are a gate stack body in which conductive films and interlayer insulating films are alternately stacked; a source structure disposed beneath the gate stack.

4. 4. The memory device of claim 3, further comprising a cell plug in the cell region that passes through the gate stack and contacts the source structure.

5. The memory device of claim 3 , further comprising a first contact connected to at least one of the conductive films in the first contact region.

6. The second contact region is a dummy laminate in which sacrificial films and interlayer insulating films are alternately laminated; an insulating pattern disposed below the dummy laminate; 2. The memory device according to claim 1, further comprising: a peripheral circuit structure disposed below the insulating pattern.

7. The memory device of claim 6 , further comprising a second contact that penetrates the dummy stack and the insulating pattern and is connected to the peripheral circuit structure.

8. The memory device of claim 1 , wherein the first contact region overlaps another portion of the staircase structure.

9. The first contact region is The memory device according to claim 1 , wherein the support pattern is located in the second direction of the second contact region and in a direction opposite to the second direction.

10. 2. The memory device of claim 1, wherein widths in the second direction of at least some of the conductive layers included in the first contact region are different from each other.

11. 2. The memory device of claim 1, wherein the widths of the sacrificial layers included in the second contact regions in the second direction are equal to each other.

12. forming a pre-laminate including first and second material films; forming a cell plug in a cell region of the pre-laminate; forming a staircase structure arranged along a second direction intersecting the first direction in a contact region extending from the cell region in a first direction; forming a support pattern including sub-support patterns that penetrate the contact region and each extend in the first direction, separating the contact region into a first contact region and a second contact region surrounded by the support pattern; In the step of forming the support pattern, any one of the sub-support patterns overlaps at least a portion of the staircase structure, and the second contact region is formed so as not to overlap the staircase structure.

13. Prior to the step of forming the pre-laminate, forming a preliminary source structure; 13. The method of claim 12, further comprising: forming an insulating pattern through the preliminary source structure.

14. After the step of separating the contact region into the first contact region and the second contact region, forming a slit through the pre-laminate; removing the second material film in the cell region and the first contact region exposed through the slit; 13. The method of claim 12, further comprising: filling a space from which the second material film is removed with a third material film to form a gate stack.

15. In the step of forming the gate stack, The method of claim 14 , wherein the gate stack in the first contact region is formed to include the staircase structure arranged along the second direction.

16. In the step of removing the second material film, The method of claim 14 , wherein the second material film in the second contact region remains to form a dummy stack.

17. In the step of forming the dummy stack, The method of manufacturing a memory device according to claim 16 , wherein the dummy stacked layer in the second contact region is formed so as not to include the staircase structure arranged along the second direction.

18. After the step of forming the dummy stack, The method of claim 16 , further comprising forming a peripheral circuit connection contact that penetrates the dummy stacked layer in the second contact region.

19. In the step of forming the support pattern, The method of claim 12 , wherein the first contact region is formed to overlap the staircase structure.

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