Semiconductor device and manufacturing method for semiconductor device

Abstract

To provide a semiconductor device in which the bonding strength of a device for a wiring board can be improved, and a manufacturing method for the semiconductor device.SOLUTION: A semiconductor device A10 includes a first terminal 21, a semiconductor element 10 that exists on one side of the first terminal 21 in a first direction z and that is electrically connected to the first terminal 21, and a protection layer 50 that is a conductor and covers a part of the first terminal 21. The first terminal 21 includes a first surface 211, a second surface 212, a third surface 213, and a fourth surface 214. The first surface 211 faces a side where the semiconductor element 10 exists in the first direction z. The second surface 212 faces a side opposite to the first surface 211 in the first direction z. The third surface 213 faces one side in a second direction x. The fourth surface 214 exists between the second surface 212 and the third surface 213 in the first direction z. When viewed in the first direction z, the fourth surface 214 overlaps with the first surface 211. The protection layer 50 covers the second surface 212 and the fourth surface 214.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same. [Background technology]

[0002] Patent Document 1 discloses an example of a semiconductor device including a first lead and a second lead, a semiconductor element conductively bonded to the first lead and the second lead, and a sealing resin covering the semiconductor element. The second lead carries the semiconductor element. A portion of each of the first lead and the second lead is exposed from the sealing resin. The portions of the first lead and the second lead exposed from the sealing resin are covered with an exterior plating layer. The exterior plating layer contains tin. This allows solder to more easily adhere to the portions of the first lead and the second lead exposed from the sealing resin when the semiconductor device is mounted on a wiring board. This increases the contact area of each of the first lead and the second lead with the solder.

[0003] However, in the semiconductor device disclosed in Patent Document 1, the end faces of the first and second leads facing the first direction that are exposed from the sealing resin are not covered with an exterior plating layer. Therefore, when the semiconductor device is mounted on a wiring board, solder is less likely to creep up to the end faces of the first and second leads. Therefore, in the semiconductor device, it is difficult to further increase the contact area of the first and second leads with the solder. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-168553

[0005] [overview] In view of the above-mentioned circumstances, an object of the present disclosure is to provide a semiconductor device that can improve the bonding strength of the device to a wiring board, and a method for manufacturing the same.

[0006] A first aspect of the present disclosure provides a semiconductor device comprising: a first terminal; a semiconductor element located on one side of the first terminal in a first direction and electrically connected to the first terminal; and a protective layer that is a conductor and covers a portion of the first terminal. The first terminal has a first surface, a second surface, a third surface, and a fourth surface. The first surface faces the side where the semiconductor element is located in the first direction. The second surface faces the opposite side from the first surface in the first direction. The third surface faces one side in a second direction perpendicular to the first direction. The fourth surface is located between the second surface and the third surface in the first direction. When viewed in the first direction, the fourth surface overlaps the first surface. The protective layer covers the second surface and the fourth surface.

[0007] A second aspect of the present disclosure provides a method for manufacturing a semiconductor device, comprising: a first step of forming a first lead having a first surface and a second surface facing opposite each other in a first direction; a second step of forming a protective layer covering the first lead; a third step of arranging a semiconductor element conductive to the first lead; and a fourth step of forming a sealing resin covering the semiconductor element. The protective layer is a conductor. The first step includes a step of forming a first opening in the first lead that is recessed from the second surface. The fourth step includes a step of sealing the first opening with a removable base material before forming the sealing resin.

[0008] Other features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present disclosure. [Figure 2] FIG. 2 is a plan view corresponding to FIG. 1, showing the sealing resin and omitting the protective layer. [Figure 3] FIG. 3 is a bottom view of the semiconductor device shown in FIG. [Figure 4] FIG. 4 is a front view of the semiconductor device shown in FIG. [Figure 5] FIG. 5 is a right side view of the semiconductor device shown in FIG. [Figure 6] FIG. 6 is a left side view of the semiconductor device shown in FIG. [Figure 7] FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. [Figure 8] FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. [Figure 9] FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. [Figure 10] FIG. 10 is a partially enlarged view of FIG. 7, showing the third surface of the first terminal and its vicinity. [Figure 11] FIG. 11 is a partially enlarged view of FIG. 7, showing the second surface of the first terminal and its vicinity. [Figure 12] FIG. 12 is a bottom view illustrating a first step in the manufacturing process of the semiconductor device shown in FIG. [Figure 13] FIG. 13 is a cross-sectional view taken along line XIII-XIII in FIG. [Figure 14] FIG. 14 is a cross-sectional view illustrating a second step in the manufacturing process of the semiconductor device shown in FIG. [Figure 15] FIG. 15 is a cross-sectional view illustrating a third step in the manufacturing process of the semiconductor device shown in FIG. [Figure 16] FIG. 16 is a bottom view illustrating a fourth step in the manufacturing process of the semiconductor device shown in FIG. [Figure 17] FIG. 17 is a cross-sectional view illustrating a fourth step in the manufacturing process of the semiconductor device shown in FIG. [Figure 18] FIG. 18 is a bottom view illustrating a fifth step in the manufacturing process of the semiconductor device shown in FIG. [Figure 19] FIG. 19 is a plan view of the semiconductor device according to the second embodiment of the present disclosure, showing the sealing resin and omitting the protective layer. [Figure 20] FIG. 20 is a cross-sectional view taken along the line XX-XX in FIG. [Figure 21] FIG. 21 is a plan view of the semiconductor device according to the third embodiment of the present disclosure, showing the sealing resin and omitting the protective layer. [Figure 22] FIG. 22 is a bottom view of the semiconductor device shown in FIG. [Figure 23] 23 is a right side view of the semiconductor device shown in FIG. [Figure 24] FIG. 24 is a plan view of the semiconductor device according to the fourth embodiment of the present disclosure, showing the sealing resin and omitting the protective layer. [Figure 25] FIG. 25 is a bottom view of the semiconductor device shown in FIG. [Figure 26] FIG. 26 is a right side view of the semiconductor device shown in FIG. [Figure 27] FIG. 27 is a plan view of the semiconductor device according to the fifth embodiment of the present disclosure, showing the sealing resin and omitting the protective layer. [Figure 28] FIG. 28 is a bottom view of the semiconductor device shown in FIG. [Figure 29] FIG. 29 is a right side view of the semiconductor device shown in FIG. [Figure 30] FIG. 30 is a plan view of the semiconductor device according to the sixth embodiment of the present disclosure, showing the sealing resin and omitting the protective layer. [Figure 31] FIG. 31 is a bottom view of the semiconductor device shown in FIG. [Figure 32] FIG. 32 is a front view of the semiconductor device shown in FIG. [Figure 33] FIG. 33 is a right side view of the semiconductor device shown in FIG.

[0010] [Detailed explanation] The details of the present disclosure will be described with reference to the accompanying drawings.

[0011] [First embodiment] A semiconductor device A10 according to a first embodiment of the present disclosure will be described with reference to FIGS. 1 to 11. The semiconductor device A10 includes a semiconductor element 10, a first terminal 21, a second terminal 22, a conductive member 30, a sealing resin 40, and a protective layer 50. The semiconductor device A10 is a resin package that is surface-mounted on a wiring board. For ease of understanding, FIG. 2 shows a perspective view of the sealing resin 40 and omits the protective layer 50. In FIG. 2, the sealing resin 40 is indicated by an imaginary line (a two-dot chain line).

[0012] In the description of the semiconductor device A10, for convenience, the direction in which a first surface 211 of a first terminal 21 (described later) faces (the normal direction of the first surface 211) is referred to as the "first direction z." A direction perpendicular to the first direction z is referred to as the "second direction x." A direction perpendicular to each of the first direction z and the second direction x is referred to as the "third direction y."

[0013] As shown in FIGS. 7 to 9, the sealing resin 40 covers the semiconductor element 10, the conductive member 30, and a portion of each of the first terminal 21 and the second terminal 22. The sealing resin 40 has electrical insulation properties. The sealing resin 40 is made of a material containing, for example, a black epoxy resin. As shown in FIGS. 3 to 5, the sealing resin 40 has a top surface 41, a bottom surface 42, a first side surface 43, two second side surfaces 44, and a third side surface 45.

[0014] 7 and 8, the top surface 41 faces the same side in the first direction z as a first surface 211 of the first terminal 21, which will be described later. The bottom surface 42 faces the opposite side to the top surface 41 in the first direction z.

[0015] As shown in FIGS. 1, 3, and 4, the first side surface 43 and the second side surface 44 face opposite each other in the second direction x. The first side surface 43 includes two peripheral edges 43A. The two peripheral edges 43A are spaced apart from each other in the second direction x. The two peripheral edges 43A extend in the first direction z. The two peripheral edges 43A are bounded by two second side surfaces 44. As shown in FIGS. 1, 3, and 6, the two second side surfaces 44 face opposite each other in the third direction y. The first side surface 43, the two second side surfaces 44, and the third side surface 45 are each connected to the top surface 41 and the bottom surface 42.

[0016] 7 and 9, the semiconductor element 10 is mounted on the second terminal 22. The semiconductor element 10 is electrically connected to both the first terminal 21 and the second terminal 22. In the semiconductor device A10, the semiconductor element 10 is a Schottky barrier diode. Alternatively, the semiconductor element 10 may be a diode other than a Schottky barrier diode, a transistor, or any other suitable element.

[0017] The semiconductor element 10 has a first electrode 11 and a second electrode 12. The first electrode 11 and the second electrode 12 are located on opposite sides of each other in the first direction z. The second electrode 12 faces a second terminal 22. The first electrode 11 is electrically connected to a first terminal 21. The second electrode 12 is electrically connected to the second terminal 22. The first terminal 21 is an anode. The second terminal 22 is a cathode. The first electrode 11 is formed, for example, by laminating a nickel (Ni) layer and a palladium (Pd) layer in this order on an aluminum (Al) layer. In the semiconductor device A10, a metal thin film is interposed between the semiconductor layer constituting the semiconductor element 10 and the first electrode 11, thereby forming a Schottky barrier. The metal thin film is made of, for example, molybdenum (Mo) or titanium (Ti).

[0018] 1 and 2, the first terminal 21 and the second terminal 22 are spaced apart from each other in the second direction x. The first terminal 21 and the second terminal 22 form a conductive path between the semiconductor element 10 and a wiring board on which the semiconductor device A10 is mounted. The first terminal 21 and the second terminal 22 are obtained from the same lead frame 80 (details of which will be described later). Each of the first terminal 21 and the second terminal 22 contains copper (Cu).

[0019] 2 and 3, the first terminal 21 has a first surface 211, a second surface 212, a third surface 213, a fourth surface 214, and two first end surfaces 215. As shown in FIG. 7, the first surface 211 faces the side where the semiconductor element 10 is located in the first direction z. The second surface 212 faces the opposite side from the first surface 211 in the first direction z. The second surface 212 is exposed from the bottom surface 42 of the sealing resin 40. The second surface 212 is located between the bottom surface 42 of the sealing resin 40 and the first surface 211 in the first direction z. In the first direction z, the second surface 212 is located closer to the bottom surface 42 than the first surface 211.

[0020] As shown in FIGS. 2 and 3, the third surface 213 faces one side in the second direction x. The third surface 213 is connected to the first surface 211. As shown in FIG. 5, the third surface 213 is exposed to the outside from the first side surface 43 of the sealing resin 40. The third surface 213 is located inward from the two peripheral edges 43A of the first side surface 43 of the sealing resin 40 in the third direction y. The third surface 213 includes two first edges 213A. The two first edges 213A are spaced apart from each other in the third direction y. The two first edges 213A extend in the first direction z. The two first edges 213A are connected to the first surface 211. In the semiconductor device A10, the two first edges 213A are also connected to the second surface 212.

[0021] As shown in FIGS. 5 and 7 , the fourth surface 214 is located between the second surface 212 and the third surface 213 in the first direction z. The fourth surface 214 is connected to the second surface 212 and the third surface 213. As viewed in the first direction z, the fourth surface 214 overlaps the first surface 211. As viewed in the second direction x, the fourth surface 214 is surrounded by the second surface 212 and the third surface 213. The fourth surface 214 curves inward of the first terminal 21. The fourth surface 214 is located inward of the two first edges 213A of the third surface 213 in the third direction y. As shown in FIGS. 2 and 8 , the two first end surfaces 215 face opposite each other in the third direction y. As shown in FIGS. 4 and 8 , the two first end surfaces 215 are individually exposed to the outside from the two second side surfaces 44 of the sealing resin 40.

[0022] 10, the surface roughness of the fourth surface 214 is smaller than the surface roughness of the third surface 213. As shown in Fig. 11, the surface roughness of the fourth surface 214 is smaller than the surface roughness of the second surface 212. The surface roughness of the second surface 212 is smaller than the surface roughness of the third surface 213.

[0023] As shown in Figures 2, 3, 5, 7, and 8, the first terminal 21 has a first opening 216. The first opening 216 is recessed from the second surface 212 and the third surface 213. The first opening 216 is defined by the fourth surface 214 and two first inner surfaces 216A. The two first inner surfaces 216A are spaced apart from each other in the third direction y. The two first inner surfaces 216A are individually connected to both sides of the fourth surface 214 in the third direction y.

[0024] As shown in Figures 2, 3, and 7, first terminal 21 is provided with a first indentation 217 and a second indentation 218. First indentation 217 and second indentation 218 are located on the opposite side of third surface 213 and first opening 216 in second direction x. First indentation 217 is recessed from first surface 211. Second indentation 218 is recessed from second surface 212. One side of second indentation 218 in the first direction z is connected to first indentation 217.

[0025] As shown in FIGS. 2 and 3 , the second terminal 22 has a fifth surface 221, a sixth surface 222, a seventh surface 223, an eighth surface 224, and two second end surfaces 225. As shown in FIGS. 7 and 9 , the fifth surface 221 faces the side on which the semiconductor element 10 is located in the first direction z. The fifth surface 221 faces the second electrode 12 of the semiconductor element 10. The second electrode 12 is conductively bonded to the mounting surface 211A via a bonding layer 19. The bonding layer 19 is, for example, solder. This allows the second electrode 12 to be electrically connected to the second terminal 22. The sixth surface 222 faces the opposite side from the fifth surface 221 in the first direction z. The sixth surface 222 is exposed from the bottom surface 42 of the sealing resin 40. The sixth surface 222 is located between the bottom surface 42 of the sealing resin 40 and the fifth surface 221 in the first direction z. In the first direction z, the sixth surface 222 is located closer to the bottom surface 42 than the fifth surface 221.

[0026] 2 and 3, the seventh surface 223 faces the opposite side to the third surface 213 of the first terminal 21 in the second direction x. The seventh surface 223 is connected to the fifth surface 221. As shown in FIG. 6, the seventh surface 223 is exposed to the outside from the third side surface 45 of the sealing resin 40. The seventh surface 223 is located inward from the two peripheral edges 43A of the first side surface 43 of the sealing resin 40 in the third direction y.

[0027] As shown in FIGS. 6 and 7 , the eighth surface 224 is located between the sixth surface 222 and the seventh surface 223 in the first direction z. The eighth surface 224 is connected to the sixth surface 222 and the seventh surface 223. As viewed in the first direction z, the eighth surface 224 overlaps the fifth surface 221. As viewed in the second direction x, the eighth surface 224 is surrounded by the sixth surface 222 and the seventh surface 223. The eighth surface 224 curves toward the inside of the second terminal 22. As shown in FIGS. 2 and 9 , the two second end surfaces 225 face opposite each other in the third direction y. As shown in FIGS. 4 and 9 , the two second end surfaces 225 are individually exposed to the outside from the two second side surfaces 44 of the sealing resin 40.

[0028] As shown in Figures 2, 3, 6, and 7, the second terminal 22 has a second opening 226. The second opening 226 is recessed from the sixth surface 222 and the seventh surface 223. The second opening 226 is defined by an eighth surface 224 and two second inner surfaces 226A. The two second inner surfaces 226A are spaced apart from each other in the third direction y. The two second inner surfaces 226A are individually connected to both sides of the eighth surface 224 in the third direction y.

[0029] 3, 7, and 9, the second terminal 22 has a recessed portion 227. The recessed portion 227 is located on the opposite side of the seventh surface 223 and the second opening 226 in the second direction x. The recessed portion 227 is recessed from the sixth surface 222.

[0030] The conductive member 30 is conductively bonded to the first surface 211 of the first terminal 21 and the first electrode 11 of the semiconductor element 10. This allows the first electrode 11 to be electrically connected to the first terminal 21. In the semiconductor device A10, the conductive member 30 is a wire. The conductive member 30 contains gold or copper. Alternatively, the conductive member 30 may be a metal clip. In this case, the conductive member 30 is conductively bonded to each of the first surface 211 and the first electrode 11 via the bonding layer 19.

[0031] As shown in FIGS. 7 to 9 , the protective layer 50 covers a portion of each of the first terminal 21 and the second terminal 22. The protective layer 50 covers the entire first terminal 21 except for the third surface 213 and the two first end surfaces 215. Additionally, the protective layer 50 covers the entire second terminal 22 except for the seventh surface 223 and the two second end surfaces 225. The protective layer 50 is a conductor. The protective layer 50 includes a first portion 501, a second portion 502, a third portion 503, and a fourth portion 504. The first portion 501 covers the second surface 212, the fourth surface 214, and the two first inner surface surfaces 216A of the first terminal 21. The second portion 502 covers the first surface 211 of the first terminal 21. The third portion 503 covers the sixth surface 222, the eighth surface 224, and the two first inner side surfaces 216A of the second terminal 22. The fourth portion 504 covers the fifth surface 221 of the second terminal 22. The sealing resin 40 covers the second portion 502 and the fourth portion 504. The first portion 501, the second portion 502, the third portion 503, and the fourth portion 504 all have the same composition. These compositions include, for example, gold. Alternatively, these compositions may include nickel, palladium, and gold. These compositions preferably include a metal that improves solder wettability and absorbs impacts, such as those that occur when conductively joining the conductive member 30 to the first surface 211 of the first terminal 21.

[0032] Next, an example of a method for manufacturing the semiconductor device A10 will be described with reference to Figures 12 to 18. Here, Figures 14, 15, and 17 each correspond to Figure 13.

[0033] First, the first step shown in FIGS. 12 and 13 is performed. In the first step, a first lead 82 and a second lead 83 are formed in a lead frame 80 including a frame body 81. The lead frame 80 contains copper. The first lead 82 and the second lead 83 are supported by the frame body 81. The first lead 82 corresponds to the first terminal 21 of the semiconductor device A10. The second lead 83 corresponds to the second terminal 22 of the semiconductor device A10. The first lead 82 and the second lead 83, together with the frame body 81, are components of the lead frame 80. The first lead 82 and the second lead 83 are formed by punching and etching.

[0034] 13, lead frame 80 has a first surface 80A and a second surface 80B facing opposite each other in first direction z. In a first step, a first opening 84 recessed from the second surface 80B is formed in first lead 82 and frame body 81. At the same time, a second opening 85 recessed from the second surface 80B is formed in second lead 83 and frame body 81. The first lead 82 and second lead 83, including the first opening 84 and second opening 85, are formed by etching.

[0035] Next, the second step shown in FIG. 14 is performed. In the second step, a protective layer 50 is formed to cover the lead frame 80 including the first lead 82 and the second lead 83. The protective layer 50 is a conductor. The protective layer 50 is formed by electrolytic plating using the lead frame 80 as a conductive path. Alternatively, the protective layer 50 may be formed by electroless plating. By performing this step, the entire lead frame 80 including the first surface 80A and the second surface 80B is covered with the protective layer 50.

[0036] Next, the third step shown in Fig. 15 is performed. In the third step, the semiconductor element 10, which is electrically connected to the first lead 82, is placed on the first surface 80A of the lead frame 80. In this step, first, the second electrode 12 of the semiconductor element 10 is conductively bonded to the protective layer 50 covering the first surface 80A of the second lead 83 by die bonding using the bonding layer 19. Next, the conductive member 30 is conductively bonded to the protective layer 50 covering the first surface 80A of the first lead 82 and the first electrode 11 of the semiconductor element 10 by wire bonding. The third step is completed through the above steps.

[0037] Next, the fourth step shown in FIGS. 16 and 17 is performed. In the fourth step, the sealing resin 40 is formed to cover the semiconductor element 10, the conductive member 30, the first lead 82, and the second lead 83. The sealing resin 40 is formed by transfer molding. In this step, before the sealing resin 40 is formed, the first opening 84 and the second opening 85 are blocked with a removable base material 89, as shown in FIG. 16. In this step, the base material 89 is, for example, a peelable tape. Alternatively, a removable resin material may be embedded in each of the first opening 84 and the second opening 85. After the first opening 84 and the second opening 85 are blocked with the base material 89, the sealing resin 40 is formed. At this time, the base material 89 can prevent the molten resin from flowing into the first opening 84 and the second opening 85, as shown in FIG. 17. After the sealing resin 40 is formed, the base material 89 is removed, thereby completing the fourth step.

[0038] Finally, the fifth step shown in FIG. 18 is performed. In this step, the first lead 82 and the second lead 83 are cut from the frame body 81. In this step, a dicing blade is advanced along the cutting line CL. As a result of this step, the first lead 82 and the second lead 83 become the first terminal 21 and the second terminal 22, respectively. The first terminal 21 has a third surface 213, which is a cut surface, and two first end surfaces 215. The second terminal 22 has a seventh surface 223, which is a cut surface, and two second end surfaces 225. In this way, the semiconductor device A10 is obtained.

[0039] Next, the effects of the semiconductor device A10 will be described.

[0040] The semiconductor device A10 includes a semiconductor element 10, a first terminal 21, and a protective layer 50 that is a conductor. The first terminal 21 has a first surface 211, a second surface 212, a third surface 213, and a fourth surface 214. The fourth surface 214 is located between the second surface 212 and the third surface 213 in the first direction z. As viewed in the first direction z, the fourth surface 214 overlaps the first surface 211. The protective layer 50 covers the second surface 212 and the fourth surface 214. With this configuration, when the semiconductor device A10 is surface-mounted on a wiring board, solder creeps up the first terminal 21 from the second surface 212 toward the fourth surface 214, thereby further increasing the bonding area of the first terminal 21 with respect to the solder. Therefore, with this configuration, the semiconductor device A10 can improve the bonding strength of the semiconductor device A10 to the wiring board.

[0041] The solder creeping up onto the fourth surface 214 of the first terminal 21 makes it easier to visually confirm the state of the solder covering the first terminal 21. This makes it possible to visually check the state of mounting of the semiconductor device A10 on the wiring board.

[0042] The semiconductor device A10 further includes a sealing resin 40 having a first side surface 43 facing one side in the second direction x. The third surface 213 of the first terminal 21 is exposed to the outside from the first side surface 43. The first side surface 43 includes two peripheral edges 43A. The third surface 213 is located inward from the two peripheral edges 43A in the third direction y. This configuration makes it possible to reduce the size of metal burrs that occur on both sides of the third surface 213 in the third direction y when the first lead 82 is separated from the first lead 82 in the fifth step (see FIG. 18 ) of the manufacturing process of the semiconductor device A10.

[0043] The third surface 213 of the first terminal 21 includes two first edges 213A. The fourth surface 214 of the first terminal 21 is located inward of the two first edges 213A in the third direction y. With this configuration, the first opening 216 of the first terminal 21 is defined by the fourth surface 214 and the two first inner surfaces 216A. As a result, when the semiconductor device A10 is surface-mounted on a wiring board, the solder creeps up from the second surface 212 of the first terminal 21 toward each of the two first inner surfaces 216A. This further increases the volume of solder accommodated in the first opening 216, thereby further improving the bonding strength of the semiconductor device A10 to the wiring board. Furthermore, because a portion of the solder is accommodated in the first opening 216, it is possible to suppress the solder from spreading outward from the semiconductor device A10.

[0044] The surface roughness of the fourth surface 214 of the first terminal 21 is smaller than the surface roughness of the third surface 213 of the first terminal 21. This is because, in the manufacturing process of the semiconductor device A10, the third surface 213 is a cut surface when the first lead 82 is separated from the frame body 81, whereas the fourth surface 214 defines the first opening 84 formed by etching.

[0045] The second surface 212 of the first terminal 21 is exposed from the bottom surface 42 of the sealing resin 40. The second surface 212 is located between the bottom surface 42 and the second surface 212 of the first terminal 21 in the first direction z. Here, in the first step (see FIGS. 12 and 13 ) of the manufacturing process of the semiconductor device A10, when the first lead 82 is formed by punching, metal burrs are generated on the edge of the second surface 80B. The burrs generated on the edge of the second surface 80B remain on the edge of the second surface 212 of the first terminal 21. Therefore, by adopting this configuration, it is possible to prevent the metal burrs remaining on the edge of the second surface 212 from protruding from the bottom surface 42. As a result, when the semiconductor device A10 is mounted on a wiring board, the posture of the semiconductor device A10 with respect to the wiring board is more stable.

[0046] The protective layer 50 includes a first portion 501 that covers the second surface 212 and the fourth surface 214 of the first terminal 21, and a second portion 502 that covers the first surface 211 of the first terminal 21. The sealing resin 40 covers the second portion 502. The composition of the second portion 502 is the same as the composition of the first portion 501. This configuration is a result of the first portion 501 and the second portion 502 being integrally formed in the second step (see FIG. 14) of the manufacturing process of the semiconductor device A10. This allows for labor savings in the manufacturing process of the semiconductor device A10.

[0047] Second Embodiment A semiconductor device A20 according to a second embodiment of the present disclosure will be described with reference to Figures 19 and 20. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are given the same reference numerals, and duplicated explanations will be omitted. For ease of understanding, Figure 19 shows a perspective view of the sealing resin 40 and omits the illustration of the protective layer 50. In Figure 19, the sealing resin 40 is shown by imaginary lines.

[0048] In the semiconductor device A20, the configurations of the first terminal 21 and the second terminal 22 are different from those of the semiconductor device A10.

[0049] 20, dimension H of fourth surface 214 of first terminal 21 in the first direction z is larger than the minimum dimension h of third surface 213 of first terminal 21 in the first direction z. As shown in FIGS. 19 and 20, in the target cross section, dimension B of fourth surface 214 in the second direction x is larger than dimension b of second surface 212 in the second direction x. Here, the target cross section is a cross section that includes the first direction z and the second direction x as in-plane directions and intersects with fourth surface 214. The cross section shown in FIG. 20 corresponds to the target cross section.

[0050] Next, the effects of the semiconductor device A20 will be described.

[0051] The semiconductor device A20 includes a semiconductor element 10, a first terminal 21, and a protective layer 50 that is a conductor. The first terminal 21 has a first surface 211, a second surface 212, a third surface 213, and a fourth surface 214. The fourth surface 214 is located between the second surface 212 and the third surface 213 in the first direction z. As viewed in the first direction z, the fourth surface 214 overlaps the first surface 211. The protective layer 50 covers the second surface 212 and the fourth surface 214. Therefore, with this configuration, the semiconductor device A20 can also improve the bonding strength of the semiconductor device A20 to the wiring substrate. Furthermore, by having a configuration common to the semiconductor device A10, the semiconductor device A20 achieves the same effects as the semiconductor device A10.

[0052] In the semiconductor device A20, the dimension H of the fourth surface 214 of the first terminal 21 in the first direction z is larger than the minimum dimension h of the third surface 213 of the first terminal 21 in the first direction z. This configuration increases the dimension of the fourth surface 214 in the first direction z, thereby further increasing the volume of solder creeping up the fourth surface 214 when the semiconductor device A20 is surface-mounted on a wiring board. This further improves the bonding strength of the semiconductor device A20 to the wiring board. Furthermore, in the semiconductor device A20, in a cross section that includes the first direction z and the second direction x as in-plane directions and intersects with the fourth surface 214, the dimension B of the fourth surface 214 in the second direction x is larger than the dimension B of the second surface 212 of the first terminal 21 in the second direction x. This configuration increases the dimension of the fourth surface 214 in both the first direction z and the second direction x, thereby further increasing the volume of solder creeping up the fourth surface 214 when the semiconductor device A20 is surface-mounted on a wiring board. This further improves the bonding strength of the semiconductor device A20 to the wiring board.

[0053] Third Embodiment A semiconductor device A30 according to a third embodiment of the present disclosure will be described with reference to FIGS. 21 to 23. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are given the same reference numerals, and duplicated explanations will be omitted. For ease of understanding, FIG. 21 shows a perspective view of the sealing resin 40 and omits the illustration of the protective layer 50. In FIG. 21, the sealing resin 40 is shown by imaginary lines.

[0054] In the semiconductor device A30, the configuration of the first terminal 21 is different from that of the semiconductor device A10.

[0055] 23 , the third surface 213 of the first terminal 21 includes two second edges 213B. The two second edges 213B are spaced apart from each other in the third direction y. The two second edges 213B extend in the first direction z. The two second edges 213B are connected to the second surface 212. In the semiconductor device A30, the two first edges 213A are spaced apart from the second surface 212. The fourth surface 214 of the first terminal 21 is located inward from the two second edges 213B in the third direction y.

[0056] 23 , on the third surface 213 of the first terminal 21, the distance D2 in the third direction y between the two second edges 213B is different from the distance D1 between the two first edges 213A. In the semiconductor device A30, the distance D2 is wider than the distance D1. The dimension in the first direction z of the fourth surface 214 of the first terminal 21 is equal to the dimension in the first direction z of each of the two second edges 213B.

[0057] Next, the effects of the semiconductor device A30 will be described.

[0058] The semiconductor device A30 includes a semiconductor element 10, a first terminal 21, and a protective layer 50 that is a conductor. The first terminal 21 has a first surface 211, a second surface 212, a third surface 213, and a fourth surface 214. The fourth surface 214 is located between the second surface 212 and the third surface 213 in the first direction z. As viewed in the first direction z, the fourth surface 214 overlaps the first surface 211. The protective layer 50 covers the second surface 212 and the fourth surface 214. Therefore, with this configuration, the semiconductor device A30 can also improve the bonding strength of the semiconductor device A30 to the wiring substrate. Furthermore, by having a configuration common to the semiconductor device A10, the semiconductor device A30 achieves the same effects as the semiconductor device A10.

[0059] In the semiconductor device A30, the third surface 213 of the first terminal 21 includes two second edges 213B. The fourth surface 214 of the first terminal 21 is located inward from the two second edges 213B in the third direction y. The distance D2 between the two second edges 213B in the third direction y is wider than the distance D1 between the two first edges 213A in the third direction y. This configuration, as shown in FIG. 22 , allows the area of the second surface 212 of the first terminal 21 to be larger than the configuration of the semiconductor device A10. This makes it easier for heat generated by the semiconductor element 10 to be dissipated from the second surface 212 to the wiring board. This improves the heat dissipation performance of the semiconductor device A30.

[0060] [Fourth embodiment] A semiconductor device A40 according to a fourth embodiment of the present disclosure will be described with reference to FIGS. 24 to 26. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are given the same reference numerals, and duplicated explanations will be omitted. For ease of understanding, FIG. 24 shows a perspective view of the sealing resin 40 and omits the illustration of the protective layer 50. In FIG. 24, the sealing resin 40 is shown by imaginary lines.

[0061] In the semiconductor device A40, the configuration of the first terminal 21 differs from that of the semiconductor device A30 described above.

[0062] 26, the third surface 213 of the first terminal 21 includes two second edges 213B, similar to the semiconductor device A30. In the semiconductor device A40, the distance D2 between the two second edges 213B in the third direction y is narrower than the distance D1 between the two first edges 213A.

[0063] Next, the effects of the semiconductor device A40 will be described.

[0064] The semiconductor device A40 includes a semiconductor element 10, a first terminal 21, and a protective layer 50 that is a conductor. The first terminal 21 has a first surface 211, a second surface 212, a third surface 213, and a fourth surface 214. The fourth surface 214 is located between the second surface 212 and the third surface 213 in the first direction z. As viewed in the first direction z, the fourth surface 214 overlaps the first surface 211. The protective layer 50 covers the second surface 212 and the fourth surface 214. Therefore, with this configuration, the semiconductor device A40 can also improve the bonding strength of the semiconductor device A40 to the wiring substrate. Furthermore, by incorporating a configuration common to the semiconductor device A10, the semiconductor device A40 achieves the same effects as the semiconductor device A10.

[0065] In the semiconductor device A40, the third surface 213 of the first terminal 21 includes two second edges 213B. The fourth surface 214 of the first terminal 21 is located inward in the third direction y from the two second edges 213B. The distance D2 between the two second edges 213B in the third direction y is narrower than the distance D1 between the two first edges 213A in the third direction y. With this configuration, both sides in the first direction z of the region of the third surface 213 located between one of the two first edges 213A and one of the two closest second edges 213B are sandwiched between the first side surface 43 of the sealing resin 40. This prevents the first terminal 21 from falling off from the bottom surface 42 of the sealing resin 40.

[0066] Fifth Embodiment A semiconductor device A50 according to a fifth embodiment of the present disclosure will be described with reference to FIGS. 27 to 29. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are given the same reference numerals, and duplicated explanations will be omitted. For ease of understanding, FIG. 27 shows a perspective view of the sealing resin 40 and omits the illustration of the protective layer 50. In FIG. 27, the sealing resin 40 is shown by imaginary lines.

[0067] In the semiconductor device A50, the configurations of the first terminal 21 and the second terminal 22 are different from those of the semiconductor device A10.

[0068] 28 and 29 , the first opening 216 of the first terminal 21 extends in the third direction y. Both sides of the first opening 216 in the third direction y are open. As a result, the first terminal 21 does not have two first inner surfaces 216A that define the first opening 216. The two first edges 213A of the third surface 213 of the first terminal 21 are spaced apart from the second surface 212 of the first terminal 21.

[0069] 28, the second opening 226 of the second terminal 22 extends in the third direction y. The second opening 226 is open on both sides in the third direction y. As a result, the second terminal 22 does not have two second inner surfaces 226A that define the second opening 226.

[0070] Next, the effects of the semiconductor device A50 will be described.

[0071] The semiconductor device A50 includes a semiconductor element 10, a first terminal 21, and a protective layer 50 that is a conductor. The first terminal 21 has a first surface 211, a second surface 212, a third surface 213, and a fourth surface 214. The fourth surface 214 is located between the second surface 212 and the third surface 213 in the first direction z. As viewed in the first direction z, the fourth surface 214 overlaps the first surface 211. The protective layer 50 covers the second surface 212 and the fourth surface 214. Therefore, with this configuration, the semiconductor device A50 can also improve the bonding strength of the semiconductor device A50 to the wiring substrate. Furthermore, by having a configuration common to the semiconductor device A10, the semiconductor device A50 achieves the same effects as the semiconductor device A10.

[0072] Sixth Embodiment A semiconductor device A60 according to a sixth embodiment of the present disclosure will be described with reference to FIGS. 30 to 33. In these figures, elements that are the same as or similar to those in the semiconductor device A10 described above are given the same reference numerals, and duplicated explanations will be omitted. For ease of understanding, FIG. 30 shows a perspective view of the sealing resin 40 and omits the illustration of the protective layer 50. In FIG. 30, the sealing resin 40 is shown by imaginary lines.

[0073] In the semiconductor device A60, the configurations of the first terminal 21, the second terminal 22, and the protective layer 50 are different from those of the semiconductor device A10.

[0074] As shown in FIGS. 31 to 33 , the fourth surface 214 of the first terminal 21 reaches each of the two first edges 213A of the third surface 213 of the first terminal 21 in the third direction y. Therefore, the dimension of the fourth surface 214 in the third direction y is equal to the dimension of the third surface 213 in the third direction y. As shown in FIG. 33 , when viewed in the third direction y, the two first edges 213A of the third surface 213 individually overlap with the extension lines of the two peripheral edges 43A of the first side surface 43 of the sealing resin 40. The two first edges 213A of the third surface 213 are spaced apart from the second surface 212 of the first terminal 21. Therefore, both sides of the first opening 216 of the first terminal 21 in the third direction y are open. As a result, the first terminal 21 does not have two first inner side surfaces 216A that define the first opening 216. Furthermore, the first opening 216 penetrates the sealing resin 40 in the third direction y. As a result, the dimension of the fourth surface 214 that defines the first opening 216 in the third direction y is equal to the dimension of the first side surface 43 in the third direction y.

[0075] 31 and 32 , both sides of the second opening 226 of the second terminal 22 in the third direction y are open. As a result, the second terminal 22 does not have two second inner side surfaces 226A that define the second opening 226. The second opening 226 penetrates the sealing resin 40 in the third direction y. As a result, the dimension in the third direction y of the eighth surface 224 of the second terminal 22 that defines the second opening 226 is equal to the dimension in the third direction y of the third side surface 45.

[0076] 31 and 32, the first portion 501 of the protective layer 50 is exposed from each of the two second side surfaces 44 of the sealing resin 40. The third portion 503 of the protective layer 50 is exposed from each of the two second side surfaces 44.

[0077] Next, the effects of the semiconductor device A60 will be described.

[0078] The semiconductor device A60 includes a semiconductor element 10, a first terminal 21, and a protective layer 50 that is a conductor. The first terminal 21 has a first surface 211, a second surface 212, a third surface 213, and a fourth surface 214. The fourth surface 214 is located between the second surface 212 and the third surface 213 in the first direction z. As viewed in the first direction z, the fourth surface 214 overlaps the first surface 211. The protective layer 50 covers the second surface 212 and the fourth surface 214. Therefore, with this configuration, the semiconductor device A60 can also improve the bonding strength of the semiconductor device A60 to the wiring substrate. Furthermore, by having a configuration common to the semiconductor device A10, the semiconductor device A60 achieves the same effects as the semiconductor device A10.

[0079] In the semiconductor device A60, the fourth surface 214 of the first terminal 21 reaches each of the two first edges 213A of the third surface 213 of the first terminal 21 in the third direction y. This configuration further increases the dimension in the third direction y of the portion of the protective layer 50 that covers the fourth surface 214. This further improves the bonding strength of the semiconductor device A60 to the wiring board.

[0080] Furthermore, in the semiconductor device A60, when viewed in the third direction y, the two first edges 213A of the third surface 213 of the first terminal 21 individually overlap with the extension lines of the two peripheral edges 43A of the first side surface 43 of the sealing resin 40. With this configuration, the dimension of the fourth surface 214 of the first terminal 21 in the third direction y becomes equal to the dimension of the first side surface 43 in the third direction y. That is, the dimension of the portion of the protective layer 50 covering the fourth surface 214 in the third direction y is further increased. This can further improve the bonding strength of the semiconductor device A60 to the wiring substrate.

[0081] The present disclosure is not limited to the above-described embodiment, and the specific configuration of each part of the present disclosure can be freely modified in various ways.

[0082] The present disclosure includes the embodiments described in the appendix below. [Appendix 1] A first terminal; a semiconductor element located on one side of the first terminal in a first direction and electrically connected to the first terminal; a protective layer that is a conductor and covers a portion of the first terminal; the first terminal has a first surface, a second surface, a third surface, and a fourth surface; the first surface faces a side on which the semiconductor element is located in the first direction; the second surface faces the opposite side to the first surface in the first direction, the third surface faces one side in a second direction perpendicular to the first direction, the fourth surface is located between the second surface and the third surface in the first direction, When viewed in the first direction, the fourth surface overlaps the first surface, The semiconductor device, wherein the protective layer covers the second surface and the fourth surface. [Appendix 2] Further, a sealing resin is provided to cover the semiconductor element. 2. The semiconductor device according to claim 1, wherein the second surface, the third surface, and the fourth surface are exposed from the sealing resin. [Appendix 3] the third surface includes two first edges that are spaced apart from each other in a third direction perpendicular to each of the first direction and the second direction and extend in the first direction; the two first edges are connected to the first surface; 3. The semiconductor device according to claim 2, wherein the fourth surface is located inward from the two first edges in the third direction. [Appendix 4] the sealing resin has a first side surface facing one side in the second direction and two second side surfaces facing opposite sides to each other in the third direction; the third surface is exposed to the outside from the first side surface, the first side includes two peripheral edges spaced apart from each other in the third direction and forming boundaries with the two second side surfaces; 4. The semiconductor device according to claim 3, wherein the third surface is located inward from the two peripheral edges in the third direction. [Appendix 5] 5. The semiconductor device of claim 4, wherein the two first edges are connected to the second surface. [Appendix 6] the third surface includes two second edges spaced apart from each other in the third direction and extending in the first direction; the two second edges are connected to the second surface; the fourth surface is located inward of the two second edges in the third direction, 5. The semiconductor device according to claim 4, wherein the distance between the two second edges in the third direction is different from the distance between the two first edges in the third direction. [Appendix 7] 7. The semiconductor device of claim 6, wherein the dimension of the fourth surface in the first direction is equal to the dimension of each of the two second edges in the first direction. [Appendix 8] 7. The semiconductor device according to claim 6, wherein the distance between the two second edges in the third direction is narrower than the distance between the two first edges in the third direction. [Appendix 9] 7. The semiconductor device according to claim 6, wherein the distance between the two second edges in the third direction is wider than the distance between the two first edges in the third direction. [Appendix 10] the third surface includes two first edges that are spaced apart from each other in a third direction perpendicular to each of the first direction and the second direction and extend in the first direction; the two first edges are connected to the first surface; 3. The semiconductor device according to claim 2, wherein the fourth surface reaches each of the two first edges in the third direction. [Appendix 11] the sealing resin has a first side surface facing one side in the second direction and two second side surfaces facing opposite sides to each other in the third direction; the third surface is exposed to the outside from the first side surface, the first side includes two peripheral edges that are spaced apart from each other in the third direction and that form boundaries with the two second side surfaces; 11. The semiconductor device of claim 10, wherein, when viewed in the second direction, the two first edges individually overlap with extension lines of each of the two peripheral edges. [Appendix 12] 12. The semiconductor device according to claim 2, wherein the fourth surface has a surface roughness smaller than that of the third surface. [Appendix 13] the sealing resin has a bottom surface facing the opposite side to the side on which the semiconductor element is located with respect to the first terminal in the first direction, the second surface is exposed from the bottom surface, 13. The semiconductor device according to claim 12, wherein the second surface is located between the bottom surface and the first surface in the first direction. [Appendix 14] 14. The semiconductor device according to claim 13, wherein the fourth surface has a surface roughness smaller than the surface roughness of the second surface. [Appendix 15] 13. The semiconductor device according to claim 12, wherein the dimension of the fourth surface in the first direction is greater than the minimum dimension of the third surface in the first direction. [Appendix 16] 16. The semiconductor device of claim 15, wherein in a cross section that includes the first direction and the second direction as in-plane directions and intersects with the fourth surface, the dimension of the fourth surface in the second direction is larger than the dimension of the second surface in the second direction. [Appendix 17] the protective layer includes a first portion covering the second surface and the fourth surface and a second portion covering the first surface; 13. The semiconductor device according to claim 12, wherein the sealing resin covers the second portion. [Appendix 18] 18. The semiconductor device of claim 17, wherein the second portion has a composition identical to that of the first portion. [Appendix 19] a second terminal spaced apart from the first terminal in the second direction; the semiconductor element has a first electrode and a second electrode positioned opposite to each other in the first direction; the first electrode is electrically connected to the first terminal; 13. The semiconductor device according to claim 12, wherein the second electrode is conductively connected to the second terminal. [Appendix 20] a first step of forming a first lead having a first surface and a second surface facing opposite to each other in a first direction; a second step of forming a protective layer to cover the first lead; a third step of placing a semiconductor element electrically connected to the first lead; and a fourth step of forming a sealing resin to cover the semiconductor element. the protective layer is a conductor; the first step includes a step of forming a first opening recessed from the second surface in the first lead; The method for manufacturing a semiconductor device, wherein the fourth step includes the step of sealing the first opening with a removable base material before forming the sealing resin. [Appendix 21] 21. The method for manufacturing a semiconductor device according to claim 20, wherein in the first step, the first opening is formed by etching. [Appendix 22] the first terminal has a first end face facing one side in the third direction, 5. The semiconductor device according to claim 4, wherein the first end face is exposed to the outside from one of the two second side faces. [Appendix 23] 5. The semiconductor device according to claim 4, wherein the third surface is flush with the first side surface. [Appendix 24] 19. The semiconductor device of claim 18, wherein the first and second portions each include gold. [Appendix 25] a conductive member conductively connected to the first electrode and the first terminal; 20. The semiconductor device according to claim 19, wherein the sealing resin covers the conductive member. [Explanation of symbols]

[0083] A10 to A60: Semiconductor device 10: Semiconductor element 11,12: 1st electrode, 2nd electrode 19: Bonding layer 21: 1st terminal 211~214: 1st side~4th side 213A, 213B: First edge, second edge 215: First end surface 216: First opening 216A: 1st inner surface 217, 218: First indentation, second indentation 22: 2nd terminal 221~224:Side 5~Side 8 225: 2nd end surface 226: Second opening 226A: 2nd inner surface 227: Indentation 30: Conductive material 40: Sealing resin 41:Top surface 42: Bottom 43,44,45: 1st side, 2nd side, 3rd side 43A: Periphery 50:Protective layer 501~504: Part 1~Part 4 80: Lead frame 80A, 80B: 1st side, 2nd side 81: Frame 82, 83: 1st lead, 2nd lead 84, 85: First opening, second opening 89: Base material z,x,y: 1st direction, 2nd direction, 3rd direction

Claims

1. A first terminal; a semiconductor element located on one side of the first terminal in a first direction and electrically connected to the first terminal; a protective layer that is a conductor and covers a portion of the first terminal; the first terminal has a first surface, a second surface, a third surface, and a fourth surface; the first surface faces a side on which the semiconductor element is located in the first direction; the second surface faces an opposite side to the first surface in the first direction, the third surface faces one side in a second direction perpendicular to the first direction, the fourth surface is located between the second surface and the third surface in the first direction, When viewed in the first direction, the fourth surface overlaps the first surface, The protective layer covers the second surface and the fourth surface.

2. Further, a sealing resin is provided to cover the semiconductor element. The semiconductor device according to claim 1 , wherein the second surface, the third surface, and the fourth surface are exposed from the sealing resin.

3. the third surface includes two first edges that are spaced apart from each other in a third direction perpendicular to each of the first direction and the second direction and extend in the first direction; the two first edges are connected to the first surface; The semiconductor device according to claim 2 , wherein the fourth surface is located inward from the two first edges in the third direction.

4. the sealing resin has a first side surface facing one side in the second direction and two second side surfaces facing opposite sides to each other in the third direction; the third surface is exposed to the outside from the first side surface, the first side includes two peripheral edges spaced apart from each other in the third direction and forming boundaries with the two second side surfaces; The semiconductor device according to claim 3 , wherein the third surface is located inward from the two peripheral edges in the third direction.

5. The semiconductor device according to claim 4 , wherein the two first edges are connected to the second surface.

6. the third surface includes two second edges spaced apart from each other in the third direction and extending in the first direction; the two second edges are connected to the second surface; the fourth surface is located inward of the two second edges in the third direction, The semiconductor device according to claim 4 , wherein the distance between the two second edges in the third direction is different from the distance between the two first edges in the third direction.

7. The semiconductor device according to claim 6 , wherein the dimension of said fourth surface in said first direction is equal to the dimension of each of said two second edges in said first direction.

8. The semiconductor device according to claim 6 , wherein the distance between said two second edges in said third direction is narrower than the distance between said two first edges in said third direction.

9. The semiconductor device according to claim 6 , wherein the distance between said two second edges in said third direction is wider than the distance between said two first edges in said third direction.

10. the third surface includes two first edges that are spaced apart from each other in a third direction perpendicular to each of the first direction and the second direction and extend in the first direction; the two first edges are connected to the first surface; The semiconductor device according to claim 2 , wherein the fourth surface reaches each of the two first edges in the third direction.

11. the sealing resin has a first side surface facing one side in the second direction and two second side surfaces facing opposite sides to each other in the third direction; the third surface is exposed to the outside from the first side surface, the first side includes two peripheral edges spaced apart from each other in the third direction and forming boundaries with the two second side surfaces; The semiconductor device according to claim 10 , wherein the two first edges individually overlap extensions of the two peripheral edges when viewed in the second direction.

12. 12. The semiconductor device according to claim 2, wherein the fourth surface has a surface roughness smaller than that of the third surface.

13. the sealing resin has a bottom surface facing the opposite side to the side on which the semiconductor element is located with respect to the first terminal in the first direction; the second surface is exposed from the bottom surface, The semiconductor device according to claim 12 , wherein the second surface is located between the bottom surface and the first surface in the first direction.

14. The semiconductor device according to claim 13 , wherein the fourth surface has a surface roughness smaller than that of the second surface.

15. The semiconductor device according to claim 12 , wherein a dimension of said fourth surface in said first direction is larger than a minimum dimension of said third surface in said first direction.

16. 16. The semiconductor device according to claim 15, wherein in a cross section that includes the first direction and the second direction as in-plane directions and intersects with the fourth surface, a dimension of the fourth surface in the second direction is larger than a dimension of the second surface in the second direction.

17. the protective layer includes a first portion covering the second surface and the fourth surface and a second portion covering the first surface; The semiconductor device according to claim 12 , wherein the sealing resin covers the second portion.

18. 18. The semiconductor device according to claim 17, wherein the second portion has the same composition as the first portion.

19. a second terminal spaced apart from the first terminal in the second direction; the semiconductor element has a first electrode and a second electrode positioned opposite to each other in the first direction; the first electrode is electrically connected to the first terminal; The semiconductor device according to claim 12 , wherein the second electrode is conductively connected to the second terminal.

20. a first step of forming a first lead having a first surface and a second surface facing opposite to each other in a first direction; a second step of forming a protective layer covering the first lead; a third step of placing a semiconductor element electrically connected to the first lead; a fourth step of forming a sealing resin to cover the semiconductor element, the protective layer is a conductor; the first step includes a step of forming a first opening recessed from the second surface in the first lead; The fourth step includes the step of sealing the first opening with a removable base material before forming the sealing resin.

21. 21. The method for manufacturing a semiconductor device according to claim 20, wherein in the first step, the first opening is formed by etching.

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