Back contact battery and manufacturing method for the same

Abstract

To provide a back contact battery that is advantageous in improving the operation performance of the back contact battery in order to increase the carrier collection efficiency, and a manufacturing method for the back contact battery.SOLUTION: A back contact battery includes a silicon substrate 11, and first doped semiconductor layers 12 and second doped semiconductor layers 13 that distribute alternately at intervals on a non-light-receiving surface side of the silicon substrate. The first doped semiconductor layer and the second doped semiconductor layer have opposite conductivity type. On the non-light-receiving surface side of the silicon substrate, a region corresponding to the first doped semiconductor layer is a first region 14 and a region corresponding to the second doped semiconductor layer is a second region 15. A region existing between the first region and the second region that are adjacent is a gap region 16. A surface of the second region is depressed into the silicon substrate relative to a surface of the first region. A surface of the gap region is depressed into the silicon substrate relative to the surface of the second region. The depth depressed into the silicon substrate relative to the surface of the first region is less than 3000 nm.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to the field of photovoltaics, and in particular to back-contact cells and methods for their manufacture. [Background technology]

[0002] A back-contact battery is a solar cell in which there are no electrodes on the light-receiving surface of the battery cell, and both the positive and negative electrodes are located on the non-light-receiving surface of the battery cell. This reduces shielding of the battery cell by the electrodes, increases the short-circuit current of the battery cell, and improves the energy conversion efficiency of the battery cell. In addition, forming a surface passivation layer on the non-light-receiving surface of the back-contact battery reduces the carrier recombination rate on the non-light-receiving surface of the back-contact battery, thereby improving the photoelectric conversion efficiency of the back-contact battery.

[0003] However, the carrier collection efficiency in conventional back contact batteries is low, which is disadvantageous for improving the operating performance of back contact batteries. Summary of the Invention

[0004] The object of the present invention is to provide a back-contact battery and a manufacturing method thereof, which are advantageous in improving the operating performance of the back-contact battery by shortening the migration distance of some carriers and increasing carrier collection efficiency while preventing conduction between the first doped semiconductor layer and the second doped semiconductor layer.

[0005] To achieve the above object, in a first aspect, the present invention provides a back-contact cell including a silicon substrate and first and second doped semiconductor layers alternately distributed at intervals on a non-light-receiving side of the silicon substrate, wherein the first and second doped semiconductor layers are of opposite conductivity types. On the non-light-receiving side of the silicon substrate, a region corresponding to the first doped semiconductor layer is a first region, a region corresponding to the second doped semiconductor layer is a second region, and a region between the first region and the adjacent second region is a spacing region. The surface of the second region is recessed into the silicon substrate relative to the surface of the first region. The surface of the spacing region is recessed into the silicon substrate relative to the surface of the second region, and the depth of the recess of the surface of the spacing region into the silicon substrate relative to the surface of the first region is less than 3000 nm.

[0006] In the back-contact cell provided by the present invention, first and second doped semiconductor layers of opposite conductivity types are alternately spaced apart on the non-light-receiving side of the silicon substrate, and the spaced apart regions on the non-light-receiving side of the silicon substrate serve to separate the first and second doped semiconductor layers, thereby reducing the carrier recombination rate at the lateral boundary between the first and second doped semiconductor layers, which is beneficial to improving the photoelectric conversion efficiency of the back-contact cell. Next, if a first doped semiconductor layer is formed in a first region of the non-light-receiving surface and a second doped semiconductor layer is formed in a second region of the non-light-receiving surface, such that the surface of the second region is recessed into the silicon substrate relative to the surface of the first region and the surface of the spacing region is recessed into the silicon substrate relative to the surface of the second region, it is clear that in actual manufacturing, after the first doped semiconductor layer covering the entire non-light-receiving surface is selectively etched, not only will the portions of the first doped semiconductor layer located in the second region and the spacing region be completely removed, but the silicon substrate will also be partially etched to a certain thickness. This ensures that no first doped semiconductor layer remains in the second region and the spacing region, preventing short circuits. This is also advantageous in that the first doped semiconductor layer and the second doped semiconductor layer, which are both located on the non-light-receiving surface side of the silicon substrate and have opposite conductivity types, are at least partially offset in the thickness direction of the silicon substrate, which further reduces the risk of leakage current on the non-light-receiving surface side and improves the electrical reliability of the back-contact battery. Similarly, when the surface of the spacing region is recessed into the silicon substrate relative to the surface of the second region, it is clear that in the actual manufacturing process, after selectively etching the first doped semiconductor layer, the second region, and the second doped semiconductor layer deposited in the spacing region, not only will the portion of the second doped semiconductor layer located on the first doped semiconductor layer and the spacing region be completely removed, but the portion of the silicon substrate corresponding to the spacing region will also be etched to a certain thickness, ensuring that no second doped semiconductor layer remains in the first doped semiconductor layer and the spacing region, and preventing short circuits.

[0007] Furthermore, as can be seen from the above, the recess depth of the spacing region into the silicon substrate is greatest on the non-light-receiving surface of the silicon substrate, and the depth of the recess of the spacing region into the silicon substrate relative to the surface of the first region is less than 3000 nm. Based on this, compared to the prior art where the recess depth of the spacing region into the silicon substrate is 5 μm, in the back-contact battery provided by the present invention, the recess depth of the spacing region into the silicon substrate is smaller. In this case, carriers of the corresponding conductivity type can be collected by the first doped semiconductor layer or the second doped semiconductor layer without bypassing the deeper spacing region, thereby shortening the travel distance of some carriers and improving carrier collection efficiency, which is advantageous for improving the operating performance of the back-contact battery.

[0008] In one possible implementation, the surface of the spacing region is flat. In this case, the surface of the spacing region is relatively flat. Based on this, if the back-contact cell further includes a surface passivation layer, the thickness of the surface passivation layer formed in the spacing region with a flat surface is greater than that of the textured surface, which can enhance the passivation effect of the surface passivation layer on the spacing region and reduce the carrier recombination rate on the surface of the spacing region, which is beneficial to improving the photoelectric conversion efficiency of the back-contact cell.

[0009] In one possible implementation, the roughness of the surface of the spacing region is less than or equal to 30 μm per 10,000 square micrometers, the beneficial effects of which are similar to those of a flat surface of the spacing region and will not be described here.

[0010] In one possible embodiment, the length of the spacing region is 20 μm or more and 110 μm or less in the arrangement direction of the first region and the second region.

[0011] When the above technical solution is used, the length of the spacing region is within the above range, and the small spacing prevents leakage current between the first doped semiconductor layer and the second doped semiconductor layer, ensuring high electrical reliability of the back-contact battery. Furthermore, the large spacing reduces the formation area of the first doped semiconductor layer and / or the second doped semiconductor layer on the non-light-receiving surface side, preventing carriers on the non-light-receiving surface side from being incapable of being collected by the first doped semiconductor layer and / or the second doped semiconductor layer and being unable to be guided to the corresponding electrode, further reducing the carrier recombination rate on the non-light-receiving surface side.

[0012] In one possible implementation, the surface of the second region is flat. In this case, the relatively flat surface of the second region is advantageous for improving the formation quality of the second doped semiconductor layer formed in the second region. Furthermore, since the surface of the second doped semiconductor layer formed in the second region and the surface of the second region have similar undulations, a flat surface of the second region is also advantageous for improving the surface flatness of the second doped semiconductor layer on the side away from the silicon substrate. Based on this, if the back-contact cell further includes a surface passivation layer, the thickness of the portion of the surface passivation layer formed on the second doped semiconductor layer with high surface flatness is greater than that of the textured portion. This enhances the passivation effect of the surface passivation layer on the side away from the silicon substrate of the second doped semiconductor layer, further reducing the carrier recombination rate on the non-light-receiving side of the back-contact cell, which is advantageous for improving the photoelectric conversion efficiency of the back-contact cell.

[0013] In one possible implementation, the surface of said second region is recessed into the silicon substrate to a depth of 100 nm to 1000 nm.

[0014] When the above technical solution is used, the depth of the recess of the surface of the second region into the silicon substrate is within the above range, and the small depth of the recess of the surface of the second region into the silicon substrate prevents the degree of misalignment in the thickness direction of the silicon substrate between the first doped semiconductor layer and the second doped semiconductor layer, which are both located on the non-light-receiving surface side of the silicon substrate and have opposite conductivity types, from becoming small, thereby further reducing the risk of leakage current on the non-light-receiving surface side. Furthermore, because the spacing region is recessed into the silicon substrate relative to the second region, i.e., the spacing region is recessed deeper into the silicon substrate than the second region, when the recess depth of the surface of the second region into the silicon substrate is within the above range, the greater recess depth of the surface of the second region into the silicon substrate can prevent the spacing region from becoming deeper into the silicon substrate, ensuring a short travel distance for some carriers that bypass the spacing region and are transported to the first doped semiconductor layer or the second doped semiconductor layer. Furthermore, the greater recess depth of the second region and the spacing region into the silicon substrate can prevent the use of a thick silicon substrate, which can reduce the manufacturing cost of back-contact batteries and is advantageous for realizing sheet-type production of back-contact batteries.

[0015] In one possible implementation, the height difference between the surface of the second region and the surface of the spacing region is 300 nm or more and less than 2000 nm.

[0016] When the above technical solution is used, the height difference between the surface of the second region and the surface of the spacing region is within the above range, and the small height difference prevents the etching depth of the etchant in the spacing region of the silicon substrate from being reduced unless the etching time is strictly controlled after the portion of the second doped semiconductor layer located in the spacing region is completely removed in the actual manufacturing process, thereby reducing the difficulty of etching.The large height difference prevents the migration distance of carriers of the corresponding conductivity type from being reduced too much, thereby ensuring the possibility of improving carrier collection efficiency.

[0017] In one possible implementation, the side surfaces of the first doped semiconductor layer and the second doped semiconductor layer close to the spacing region are both substantially wavy, wherein a corresponding variation width of the side surface of the second doped semiconductor layer close to the spacing region is larger than a corresponding variation width of the side surface of the first doped semiconductor layer close to the spacing region, and / or a corresponding variation frequency of the side surface of the second doped semiconductor layer close to the spacing region is smaller than a corresponding variation frequency of the side surface of the first doped semiconductor layer close to the spacing region.

[0018] When the above technical solution is used, when the side surfaces of the first doped semiconductor layer and the second doped semiconductor layer near the spacing region are both approximately wavy, if the corresponding fluctuation range of the side surface of the second doped semiconductor layer near the spacing region is larger than the corresponding fluctuation range of the side surface of the first doped semiconductor layer near the spacing region, the roughness of the local area of the side surface of the second doped semiconductor layer near the spacing region is smaller than the roughness of the local area of the side surface of the first doped semiconductor layer near the spacing region, which is advantageous to reduce the number of defects in the portion of the second doped semiconductor layer near the spacing region and further reduce the carrier recombination rate in the portion of the second doped semiconductor layer near the spacing region, and further improve the operating performance of the back-contact battery.

[0019] In one possible embodiment, at least a portion of the sidewall of the spacing region is oblique to the horizontal plane so that the cross-sectional area of at least a portion of the spacing region gradually increases in the direction from the light-receiving surface to the non-light-receiving surface.

[0020] The above technical solution has a smaller cross-sectional area on the light-receiving side of the spacing region than on the non-light-receiving side, which is advantageous for increasing the distance between the first doped semiconductor layer and the second doped semiconductor layer of the opposite conductivity type, reducing the risk of electrical leakage on the non-light-receiving side of the back-contact cell and ensuring high electrical reliability of the back-contact cell. Furthermore, the obliquely oriented sidewall of the spacing region is advantageous for reflecting light, which allows more light to enter the silicon substrate from the non-light-receiving side of the back-contact cell under the reflection effect of the obliquely oriented sidewall of the spacing region, thereby improving the photoelectric conversion efficiency of the back-contact cell.

[0021] In one possible implementation, the back contact cell further comprises a surface passivation layer covering the first doped semiconductor layer, the second doped semiconductor layer and the spacing region.

[0022] The above technical solution allows the surface passivation layer to passivate the non-light-receiving side of the back-contact cell, reducing the carrier recombination rate on the non-light-receiving side, and the corresponding recess depth of the gap region with the greatest recess depth into the silicon substrate is less than 3000 nm, which is advantageous for reducing the undulation degree of each region on the non-light-receiving side of the back-contact cell, increasing the thickness of the surface passivation layer on the non-light-receiving side, and improving the passivation effect of the surface passivation layer on the non-light-receiving side.

[0023] In one possible implementation, the back contact cell further comprises a first passivation layer located between the first region of the silicon substrate and the first doped semiconductor layer.

[0024] When the above technical solution is used, the first passivation layer and the first doped semiconductor layer form a selective contact structure, which realizes chemical passivation for the first region of the non-light-receiving surface of the silicon substrate and realizes selective collection of carriers of the corresponding conductivity type, thereby reducing the carrier recombination rate on the non-light-receiving surface side, which is beneficial to improving the photoelectric conversion efficiency of back-contact cells.

[0025] In one possible implementation, the back contact cell further comprises a second passivation layer located between the second region of the silicon substrate and the second doped semiconductor layer.

[0026] When the above technical solution is used, the second passivation layer and the second doped semiconductor layer form a selective contact structure, which realizes chemical passivation for the second region of the non-light-receiving surface of the silicon substrate and realizes selective collection of carriers of the corresponding conductivity type, thereby reducing the carrier recombination rate on the non-light-receiving surface side, which is beneficial to improving the photoelectric conversion efficiency of back-contact cells.

[0027] In one possible implementation, when the back contact cell includes a first passivation layer, and the first passivation layer is a tunnel passivation layer, the first doped semiconductor layer is a doped polycrystalline silicon layer.

[0028] In one possible implementation, if the back contact cell includes a second passivation layer, and the second passivation layer is a tunnel passivation layer, the second doped semiconductor layer is a doped polycrystalline silicon layer.

[0029] In a second aspect, the present invention provides a method for manufacturing a back contact cell, comprising the steps of: providing a silicon substrate, the non-light-receiving surface of the silicon substrate having first and second regions distributed at intervals, and a spacing region located between the first region and the second region adjacent to the first region; forming a first doped semiconductor layer in the first region, such that surfaces of both the spacing region and the second region are recessed into the silicon substrate relative to the surface of the first region; and forming a second doped semiconductor layer in the second region, such that the surface of the spacing region is recessed into the silicon substrate relative to the surface of the second region, and the surface of the spacing region is recessed into the silicon substrate relative to the surface of the first region to a depth of less than 3000 nm.

[0030] In one possible implementation, after the above step of preparing a silicon substrate and before forming a second doped semiconductor layer in the second region, the method for manufacturing a back contact cell includes the steps of: forming, on the non-light-receiving surface of the silicon substrate, a first doped semiconductor layer provided over the entire surface thereof and a first mask layer located in a portion of the first doped semiconductor layer corresponding to the first region; and selectively removing, under the masking effect of the first mask layer, portions of the first doped semiconductor layer located in the spacing region and the second region, and recessing both surfaces of the spacing region and the second region into the silicon substrate relative to the surface of the first region.

[0031] In one possible embodiment, the material of the first doped semiconductor layer includes silicon. The step of forming the first doped semiconductor layer covering the entire surface of the silicon substrate and the first mask layer located in a portion corresponding to the first region of the first doped semiconductor layer includes the steps of: forming a first intrinsic semiconductor layer covering the entire surface of the silicon substrate; doping the first intrinsic semiconductor layer to form the first doped semiconductor layer as the first intrinsic semiconductor layer and forming a first doped silicate glass layer covering the entire surface of the first doped semiconductor layer; heat-treating the portions of the first doped silicate glass layer corresponding to the gap region and the second region by a laser etching process to form the unheated portions of the first doped silicate glass layer as the first mask layer; and removing the heat-treated portions of the first doped silicate glass layer.

[0032] When the above technical solution is used, if the material of the first doped semiconductor layer contains silicon, the material of the first intrinsic semiconductor layer used to manufacture the first doped semiconductor layer also contains silicon. Based on this, after doping the first intrinsic semiconductor layer, not only can the first doped semiconductor layer be obtained, but also a first doped silicate glass layer covering the entire surface of the first doped semiconductor layer can be formed. Then, a portion of the first doped silicate glass layer is heat-treated using a laser etching process. In this case, the laser-treated portion of the first doped silicate glass layer becomes less dense and is more easily removed. On the other hand, the portion of the first doped silicate glass layer that has not been laser-treated is highly dense and difficult to remove. Therefore, after the heat treatment, different portions of the first doped silicate glass layer have different etching selectivities, and a first mask layer for patterning the first doped semiconductor layer is obtained. This eliminates the need to additionally form other mask materials and perform other mask deposition processes to obtain the first mask layer, which is advantageous for reducing the manufacturing cost of back-contact batteries and simplifying the manufacturing process of back-contact batteries.

[0033] In one possible implementation, a wet chemical process is used to selectively remove portions of the first doped semiconductor layer located in the spacing region and the second region under the masking effect of the first mask layer, and the surfaces of both the spacing region and the second region are recessed into the silicon substrate relative to the surface of the first region, wherein the process temperature of the wet chemical process is 60°C or more and 80°C or less, and / or the process time of the wet chemical process is 40 seconds or more and 200 seconds or less, and / or the wet chemical etching solution used in the wet chemical process is an alkaline wet chemical etching solution, and the volume ratio of the alkaline component in the alkaline wet chemical etching solution is 2% or more and 20% or less, and / or the wet chemical etching solution used in the wet chemical process contains a polishing additive, and the volume ratio of the polishing additive in the wet chemical etching solution is 0.5% or more and 5% or less.

[0034] When using the above technical solution, the process temperature and process time of the wet chemical process both affect the depth to which the surfaces of both the spacing region and the second region are recessed into the silicon substrate relative to the surface of the first region. Based on this, when the process temperature of the wet chemical process is within the above range, a low process temperature can prevent the depth to which the surfaces of both the spacing region and the second region are recessed into the silicon substrate relative to the surface of the first region from becoming small. A high process temperature can also prevent the depth to which the surfaces of both the spacing region and the second region are recessed into the silicon substrate relative to the surface of the first region from becoming large. After this operation, the depth to which the surfaces of the spacing region and the second region are recessed into the silicon substrate relative to the surface of the first region is equal to the depth to which the surface of the second region is recessed into the silicon substrate relative to the surface of the first region in the formed back contact cell. For the beneficial effects of preventing the depth to which the surface of the second region is recessed into the silicon substrate relative to the surface of the first region from becoming large or small, see the preceding paragraph. Next, the beneficial effects of the process time and the volume ratio of the alkaline component within the above ranges are similar to the beneficial effects of the process temperature being 60° C. or more and 80° C. or less, and will not be described here. In addition, when the volume ratio of the polishing additive in the wet chemical etching solution is within the above range, the flatness of the surfaces of the gap region and the second region after the operation can be improved, and the passivation effect of the surface passivation layer on the gap region and the second doped semiconductor layer can be further improved.

[0035] In one possible implementation, after the above step of recessing both surfaces of the spacing region and the second region into the silicon substrate relative to the surface of the first region, the method for manufacturing a back contact cell includes the steps of depositing a second doped semiconductor layer on the first doped semiconductor layer, the spacing region, and the second region, and forming a second mask layer on a portion of the second doped semiconductor layer corresponding to the second region; and selectively removing, under the masking effect of the second mask layer, the portions of the second doped semiconductor layer corresponding to the first region and the spacing region, and recessing the surface of the spacing region into the silicon substrate relative to the surface of the second region.

[0036] In one possible embodiment, the material of the second doped semiconductor layer includes silicon. The steps of depositing the second doped semiconductor layer on the first doped semiconductor layer, the spacing region, and the second region and forming the second mask layer on the portion of the second doped semiconductor layer corresponding to the second region include: depositing a second intrinsic semiconductor layer on the first doped semiconductor layer, the spacing region, and the second region; doping the second intrinsic semiconductor layer to form the second intrinsic semiconductor layer as the second doped semiconductor layer and forming a second doped silicate glass layer covering the entire thickness of the second doped semiconductor layer; heat-treating the portion of the second doped silicate glass layer corresponding to the first region and the spacing region by a laser etching process to form the portion of the second doped silicate glass layer corresponding to the second region as the second mask layer; and removing the portion of the second doped silicate glass layer that has been heat-treated.

[0037] When the above technical solution is used, if the material of the second doped semiconductor layer contains silicon, the material of the second intrinsic semiconductor layer used to manufacture the second doped semiconductor layer also contains silicon. Based on this, after doping the second intrinsic semiconductor layer, not only can the second doped semiconductor layer be obtained, but also a second doped silicate glass layer covering the entire surface of the second doped semiconductor layer can be formed. Then, the portions of the second doped silicate glass layer corresponding to the first region and the gap region are heat-treated using a laser etching process. In this case, the laser-treated portions of the second doped silicate glass layer become less dense and are more easily removed. On the other hand, the portion of the second doped silicate glass layer corresponding to the second region is not laser-treated, and therefore is highly dense and difficult to remove. As a result, after heat treatment, different portions of the second doped silicate glass layer have different etching selectivities, and a second mask layer for patterning the second doped semiconductor layer is obtained. This eliminates the need to additionally form another mask material and perform another mask deposition process to obtain the second mask layer, which is advantageous for reducing the manufacturing cost of back-contact batteries and simplifying the manufacturing process of back-contact batteries.

[0038] In one possible embodiment, a wet chemical process is used to selectively remove portions of the second doped semiconductor layer corresponding to the first region and the spacing region under the masking effect of the second mask layer, and the surface of the spacing region is recessed into the silicon substrate relative to the surface of the second region, wherein the process temperature of the wet chemical process is 60°C or more and 80°C or less, and / or the process time of the wet chemical process is 50 seconds or more and 300 seconds or less, and / or the wet chemical etching solution used in the wet chemical process is an alkaline wet chemical etching solution, and the volume ratio of the alkaline component in the alkaline wet chemical etching solution is 2% or more and 20% or less, and / or the wet chemical etching solution used in the wet chemical process contains a polishing additive, and the volume ratio of the polishing additive in the wet chemical etching solution is 0.5% or more and 5% or less.

[0039] When using the above technical solution, the process temperature and process time of the wet chemical process both affect the depth to which the surface of the spacing region is recessed into the silicon substrate relative to the surface of the second region. Based on this, when the process temperature of the wet chemical process is within the above range, a low process temperature can prevent the depth to which the surface of the spacing region is recessed into the silicon substrate relative to the surface of the second region from becoming small. Furthermore, a high process temperature can prevent the depth to which the surface of the spacing region is recessed into the silicon substrate relative to the surface of the second region from becoming large. For the beneficial effects of reducing or preventing the depth to which the surface of the spacing region is recessed into the silicon substrate relative to the surface of the second region, please refer to the previous paragraph. The beneficial effects of the process time and the volume ratio of the alkaline component within the above range are similar to the beneficial effects of a process temperature between 60°C and 80°C, and will not be described here. In addition, when the volume ratio of the polishing additive in the wet chemical etching solution is within the above range, the flatness of the surface of the gap area after the operation can be improved, and the passivation effect of the surface passivation layer on the gap area can be further improved.

[0040] In one possible implementation, after providing the silicon substrate and before forming the first doped semiconductor layer in the first region, the method for manufacturing a back contact cell further includes forming a first passivation layer in the first region.

[0041] In one possible implementation, after both the surfaces of the spacing region and the second region are recessed into the silicon substrate relative to the surface of the first region and before forming the second doped semiconductor layer in a portion of the second region, the method for manufacturing a back contact cell further includes forming a second passivation layer in the second region.

[0042] In one possible implementation, after recessing the surface of the spacing region into the silicon substrate relative to the surface of the second region, the method for manufacturing a back contact cell further includes forming a surface passivation layer covering the first doped semiconductor layer, the second doped semiconductor layer, and the spacing region.

[0043] The beneficial effects of the second aspect of the present invention and its various embodiments can be explained by referring to the analysis of the beneficial effects of the first aspect of the present invention and its various embodiments, and will not be described here. [Brief explanation of the drawings]

[0044] The drawings described in this specification are intended to provide a further understanding of the present invention and constitute a part of the present invention, and the exemplary embodiments of the present invention and the description thereof are intended to interpret the present invention and are not intended to unduly limit the present invention. [Figure 1] FIG. 1 is a SEM diagram of a longitudinal cross section of the structure of a back-contact battery in the related art. [Figure 2] 1 is a longitudinal cross-sectional view of a back-contact battery structure according to an embodiment of the present invention; FIG. [Figure 3] FIG. 1 is an SEM image (part 1) of a partial structure of a back-contact battery provided by an embodiment of the present invention. [Figure 4]FIG. 2 is a SEM image (part 2) of a partial structure of a back-contact battery provided by an embodiment of the present invention. [Figure 5] FIG. 3 is a SEM image (part 3) of a partial structure of a back-contact battery provided by an embodiment of the present invention. [Figure 6] FIG. 4 is an SEM image (part 4) of a partial structure of a back-contact battery provided by an embodiment of the present invention. [Figure 7] FIG. 5 is an SEM image (part 5) of a partial structure of a back-contact battery provided by an embodiment of the present invention. [Figure 8] 1 is a structural diagram (part 1) of a back-contact battery according to an embodiment of the present invention during the manufacturing process; [Figure 9] FIG. 2 is a structural schematic diagram (part 2) of the back-contact battery according to the embodiment of the present invention during the manufacturing process. [Figure 10] FIG. 3 is a structural diagram (part 3) of a back-contact battery according to an embodiment of the present invention during the manufacturing process. [Figure 11] FIG. 4 is a structural schematic diagram (part 4) of the back-contact battery provided by the embodiment of the present invention during the manufacturing process. [Figure 12] FIG. 5 is a structural diagram (part 5) of a back-contact battery according to an embodiment of the present invention during the manufacturing process. [Figure 13] FIG. 6 is a structural schematic diagram (part 6) of the back-contact battery according to the embodiment of the present invention during the manufacturing process. [Figure 14] FIG. 7 is a structural schematic diagram (part 7) of the back-contact battery according to the embodiment of the present invention during the manufacturing process. [Figure 15] FIG. 8 is a structural diagram (part 8) of a back-contact battery according to an embodiment of the present invention during the manufacturing process. [Figure 16] 9 is a structural schematic diagram (part 9) of the manufacturing process of the back-contact battery provided by the embodiment of the present invention. [Figure 17] FIG. 10 is a structural schematic diagram (part 10) of the back-contact battery provided by an embodiment of the present invention during the manufacturing process. [Figure 18] FIG. 11 is a structural schematic diagram (part 11) of a back-contact battery according to an embodiment of the present invention during the manufacturing process. [Figure 19] 12 is a structural schematic diagram (part 12) of a back-contact battery according to an embodiment of the present invention during the manufacturing process. [Figure 20] FIG. 13 is a structural schematic diagram (part 13) of the manufacturing process of a back-contact battery provided by an embodiment of the present invention. [Figure 21] FIG. 14 is a structural schematic diagram (part 14) of the manufacturing process of a back-contact battery provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0045] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. However, it should be understood that these descriptions are merely illustrative and do not limit the scope of the present disclosure. In the following description, descriptions of known structures and techniques will be omitted to avoid unnecessary confusion with the concept of the present disclosure.

[0046] The drawings show various structural schematic diagrams according to embodiments of the present disclosure. These drawings are not drawn to scale, and some details may be enlarged and some details may be omitted for clarity. The shapes of various regions and layers shown in the drawings, as well as the relative sizes and positional relationships between them, are merely exemplary, and may vary in practice due to manufacturing tolerances and technical limitations. Furthermore, those skilled in the art can separately design regions / layers having different shapes, sizes, and relative positions according to actual needs.

[0047] In the context of the present disclosure, when a layer / element is described as being "on" another layer / element, this layer / element may be directly on top of this other layer / element, or there may be an intermediate layer / element therebetween. Also, if one layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, this layer / element may be "under" the other layer / element. In order to make the technical problems, technical solutions, and beneficial effects of the present invention clearer, the present invention will be described in more detail below in combination with figures and examples. It should be understood that the specific examples described herein are merely for the purpose of illustrating the present invention and are not intended to limit the present invention.

[0048] Additionally, the terms "first" and "second" are for descriptive purposes only and should not be understood to express or imply relative importance or the quantity of the technical features being described. Thus, a feature qualified as "first" or "second" may expressly or imply the inclusion of one or more of that feature. In the description of this invention, unless expressly and specifically limited, "plurality" means two or more than two. Unless expressly and specifically limited, "some" means one or more than one.

[0049] In describing the present invention, unless otherwise clearly defined or limited, the terms "attach," "couple," and "connect" should be understood in a broad sense, for example, to mean fixedly connected, detachably connected, integrally connected, mechanically connected, electrically connected, directly connected, or indirectly connected via an intermediate medium, or to mean an internal communication between two elements or an interaction between two elements. Those skilled in the art can understand the specific meaning of the above terms in the present invention according to the specific circumstances.

[0050] Currently, solar cells are widely used as a new alternative energy form. Among them, photovoltaic solar cells are devices that convert solar light energy into electrical energy. Specifically, solar cells use the principle of photovoltaic power to generate carriers, and then extract the carriers through electrodes, which is advantageous for efficient use of electrical energy.

[0051] Here, if both the positive and negative electrodes of a solar cell are located on the non-light-receiving side of the solar cell, the solar cell is called a back-contact cell. Because the light-receiving side of a back-contact cell is not affected by shielding by metal electrodes, back-contact cells have higher short-circuit current and photoelectric conversion efficiency than solar cells with shielded light-receiving sides, and are currently one of the technological trends toward high-efficiency crystalline silicon cells. Specifically, as shown in Figure 1, a conventional back-contact cell typically includes a silicon substrate 11 and first and second doped semiconductor layers 12 and 13 alternately distributed at intervals on the non-light-receiving side of the silicon substrate 11. The first and second doped semiconductor layers 12 and 13 are of opposite conductivity types.

[0052] In actual manufacturing processes, a first doped semiconductor layer is typically formed over the entire surface of the non-light-receiving surface, and then selectively etched to leave only a portion of the first doped semiconductor layer on the non-light-receiving surface. A second doped semiconductor layer is then formed over the first doped semiconductor layer and the portion of the non-light-receiving surface exposed to the first doped semiconductor layer, and the second doped semiconductor layer is selectively etched so that the first and second doped semiconductor layers are alternately distributed at intervals on the non-light-receiving surface of the silicon substrate.

[0053] 1, the first doped semiconductor layer 12 and the second doped semiconductor layer 13 have opposite conductivity types. To prevent the first doped semiconductor layer 12 and the second doped semiconductor layer 13 from shorting, a conventional manufacturing method involves forming a gap region 16 having a certain width between them by wet chemical etching or the like. However, in conventional back-contact batteries, the gap region 16 between the first doped semiconductor layer 12 and the second doped semiconductor layer 13 is recessed deeply into the silicon substrate 11 (e.g., greater than 5 μm). This means that carriers in the silicon substrate 11 must bypass the deep gap region before they can be collected by the first doped semiconductor layer 12 and the second doped semiconductor layer 13. This results in a long carrier travel distance, low carrier collection efficiency, and a high carrier recombination rate, which is detrimental to improving the operating performance of the back-contact battery.

[0054] To solve the above technical problems, in a first aspect, an embodiment of the present invention provides a back-contact cell. As shown in FIG. 2, the back-contact cell provided by the embodiment of the present invention includes a silicon substrate 11 and first doped semiconductor layers 12 and second doped semiconductor layers 13 alternately distributed at intervals on the non-light-receiving side of the silicon substrate 11. Here, the first doped semiconductor layers 12 and the second doped semiconductor layers 13 have opposite conductivity types. On the non-light-receiving side of the silicon substrate 11, the region corresponding to the first doped semiconductor layer 12 is a first region 14, the region corresponding to the second doped semiconductor layer 13 is a second region 15, and the region between the first region 14 and the adjacent second region 15 is a gap region 16. The surface of the second region 15 is recessed into the silicon substrate 11 with respect to the surface of the first region 14. The surface of the spacing region 16 is recessed into the silicon substrate 11 relative to the surface of the second region 15, and recessed into the silicon substrate 11 relative to the surface of the first region 14 to a depth of less than 3000 nm.

[0055] 2, in a back-contact cell provided by an embodiment of the present invention, first doped semiconductor layers 12 and second doped semiconductor layers 13 of opposite conductivity types are alternately distributed at intervals on the non-light-receiving surface side of a silicon substrate 11. Based on this, a spacing region 16 on the non-light-receiving surface of the silicon substrate 11 can separate the first doped semiconductor layers 12 and second doped semiconductor layers 13, thereby reducing the carrier recombination rate at the lateral boundary between the first doped semiconductor layers 12 and the second doped semiconductor layers 13, which is beneficial to improving the photoelectric conversion efficiency of the back-contact cell. Next, first doped semiconductor layer 12 is formed in first region 14 of the non-light-receiving surface, and second doped semiconductor layer 13 is formed in second region 15 of the non-light-receiving surface. Therefore, if the surface of second region 15 is recessed into silicon substrate 11 relative to the surface of first region 14 and the surface of spacing region 16 is recessed into silicon substrate 11 relative to the surface of second region 15, in the actual manufacturing process, after first doped semiconductor layer 12 covering the entire non-light-receiving surface side is selectively etched, the portions of first doped semiconductor layer 12 located in second region 15 and spacing region 16 are completely removed. It is clear that not only is the first doped semiconductor layer 12 removed, but the silicon substrate 11 is also partially etched to a certain thickness, ensuring that no first doped semiconductor layer 12 remains in the second region 15 and the spacing region 16, preventing short circuits. This is also advantageous in that the first doped semiconductor layer 12 and the second doped semiconductor layer 13, both of which are located on the non-light-receiving side of the silicon substrate 11 and have opposite conductivity types, are at least partially offset in the thickness direction of the silicon substrate 11, further reducing the risk of leakage current on the non-light-receiving side and improving the electrical reliability of the back-contact battery. Similarly, if the surface of the spacing region 16 is recessed into the silicon substrate 11 relative to the surface of the second region 15, it is clear that in the actual manufacturing process, after selectively etching the first doped semiconductor layer 12, the second region 15, and the second doped semiconductor layer 13 deposited in the spacing region 16, not only will the portions of the second doped semiconductor layer 13 located on the first doped semiconductor layer 12 and the spacing region 16 be completely removed, but the portions of the silicon substrate 11 corresponding to the spacing region 16 will also be etched to a certain thickness, ensuring that no second doped semiconductor layer 13 remains in the first doped semiconductor layer 12 and the spacing region 16, and preventing short circuits.Furthermore, as can be seen from the above, the recess depth of the spacing region 16 into the silicon substrate 11 is greatest on the non-light-receiving surface of the silicon substrate 11, and the depth to which the spacing region 16 is recessed into the silicon substrate 11 relative to the surface of the first region 14 is less than 3000 nm. Based on this, compared to the prior art where the recess depth of the spacing region into the silicon substrate is 5 μm, the back-contact battery provided by the embodiment of the present invention has a smaller recess depth of the spacing region 16 into the silicon substrate 11. In this case, carriers of the corresponding conductivity type can be collected by the first doped semiconductor layer 12 or the second doped semiconductor layer without bypassing the deeper spacing region 16, thereby shortening the travel distance of some carriers and improving carrier collection efficiency, which is beneficial to improving the operating performance of the back-contact battery.

[0056] In actual application, the light-receiving surface of the silicon substrate 11 may be flat or textured, as shown in Figure 2. Here, because the texture has a light-trapping effect, a textured light-receiving surface of the silicon substrate reduces the reflectance of the light-receiving surface, which is advantageous in that more light is refracted from the light-receiving surface into the silicon substrate and absorbed by the silicon substrate for utilization, thereby improving the photoelectric conversion efficiency of the back-contact cell.

[0057] Furthermore, from the perspective of area, the boundaries between the first region, the second region, and the spacing region on the non-light-receiving surface side of the silicon substrate are imaginary boundaries. As shown in FIG. 2 , because first doped semiconductor layer 12 is formed in first region 14, the area of first region 14 on the non-light-receiving surface side of silicon substrate 11 can be determined depending on the required area for forming first doped semiconductor layer 12 in an actual application scenario. Next, because second doped semiconductor layer 13 is formed in second region 15, the area of second region 15 on the non-light-receiving surface side of silicon substrate 11 can be determined depending on the required area for forming second doped semiconductor layer 13 in an actual application scenario. Regarding spacing region 16, as described above, spacing region 16 can isolate first doped semiconductor layer 12 and second doped semiconductor layer 13, which have opposite conductivity types, to suppress electrical leakage. Therefore, the area of spacing region 16 on the non-light-receiving surface side can be determined depending on the required distance for preventing electrical leakage between first doped semiconductor layer 12 and second doped semiconductor layer 13 in an actual application scenario.

[0058] For example, the length of the spacing region in the arrangement direction of the first and second regions is 20 μm or more and 110 μm or less. For example, the length of the spacing region may be 20 μm, 40 μm, 60 μm, 80 μm, 100 μm, or 110 μm. In this case, the length of the spacing region is within the above range, and the small spacing prevents leakage between the first doped semiconductor layer and the second doped semiconductor layer, ensuring high electrical reliability of the back-contact battery. Furthermore, the large spacing reduces the formation area of the first doped semiconductor layer and / or the second doped semiconductor layer on the non-light-receiving surface side, preventing carriers on the non-light-receiving surface side from being incapable of being collected in a timely manner by the first doped semiconductor layer and / or the second doped semiconductor layer and being unable to be guided through the corresponding electrode, further reducing the carrier recombination rate on the non-light-receiving surface side.

[0059] From the perspective of recess depth, the recess depths of the second region and the spacing region on the non-light-receiving surface of the silicon substrate into the silicon substrate, and the height difference between the surfaces of the second region and the spacing region, may be determined according to the actual application scenario, as long as the second region is recessed inward relative to the surface of the first region, the surface of the spacing region is recessed inward relative to the surface of the second region, and the depth of the surface of the spacing region recessed into the silicon substrate relative to the surface of the first region is less than 3000 nm.

[0060] Illustratively, the depth of the recess of the surface of the second region into the silicon substrate may be 100 nm or more and 1000 nm or less. For example, the depth of the recess of the surface of the second region into the silicon substrate may be 100 nm, 300 nm, 600 nm, 800 nm, 900 nm, or 1000 nm. In this case, the depth of the recess of the surface of the second region into the silicon substrate is within the above range. Since the depth of the recess of the surface of the second region into the silicon substrate is small, it is possible to prevent the degree of misalignment in the thickness direction of the silicon substrate between the first doped semiconductor layer and the second doped semiconductor layer, which are both located on the non-light-receiving surface side of the silicon substrate and have opposite conductivity types, from becoming small, thereby further reducing the risk of electrical leakage on the non-light-receiving surface side. Furthermore, because the spacing region is recessed into the silicon substrate relative to the second region, i.e., the spacing region is recessed deeper into the silicon substrate than the second region, when the recess depth of the surface of the second region into the silicon substrate is within the above range, the greater recess depth of the surface of the second region into the silicon substrate can be prevented from becoming greater, ensuring that the travel distance of some carriers that bypass the spacing region and are transported to the first doped semiconductor layer or the second doped semiconductor layer can be reduced. Furthermore, the greater recess depth of the second region and the spacing region into the silicon substrate can be prevented from requiring a thicker silicon substrate, which can reduce the manufacturing cost of back-contact batteries and is advantageous for realizing sheet-type production of back-contact batteries.

[0061] For example, the height difference between the surface of the second region and the surface of the spacing region may be 300 nm or more and less than 2000 nm. For example, the height difference between the surface of the second region and the surface of the spacing region may be 300 nm, 600 nm, 900 nm, 1200 nm, 1500 nm, 1800 nm, or 2000 nm. In this case, the height difference between the surface of the second region and the surface of the spacing region is within the above range. Because the height difference is small, it is possible to prevent the etching depth of the etchant in the spacing region of the silicon substrate from being reduced by strictly controlling the etching time after completely removing the portion of the second doped semiconductor layer located in the spacing region during actual manufacturing, thereby reducing the difficulty of etching. Because the height difference is large, it is possible to prevent the migration distance of carriers of the corresponding conductivity type from being significantly reduced, thereby ensuring the possibility of improving carrier collection efficiency.

[0062] The recess depth of the spacing region into the silicon substrate may be any value greater than the recess depth of the surface of the second region into the silicon substrate and less than 3000 nm. For example, if the recess depth of the surface of the second region into the silicon substrate is 500 nm, the depth to which the spacing region is recessed into the silicon substrate relative to the surface of the first region may be any value greater than 500 nm and less than 3000 nm (e.g., 1000 nm, 1500 nm, 1800 nm, 2000 nm, 2500 nm, 2800 nm, or 2900 nm, etc.).

[0063] From the viewpoint of surface morphology, as shown in FIG. 2 , the surface of the first region 14 on the non-light-receiving surface of the silicon substrate 11 is flat. The surface of the second region 15 may be flat or textured. Here, as shown in FIGS. 2 to 7 , if the surface of the second region 15 is flat, the surface of the second region 15 is relatively flat, which is advantageous for improving the formation quality of the second doped semiconductor layer 13 formed in the second region 15. Furthermore, since the surface of the second doped semiconductor layer 13 formed in the second region 15 and the surface of the second region 15 have similar degrees of undulation, if the surface of the second region 15 is flat, it is also advantageous for improving the surface flatness of the side of the second doped semiconductor layer 13 away from the silicon substrate 11. Based on this, when the back-contact battery further includes a surface passivation layer 17, the thickness of the portion of the surface passivation layer 17 formed on the second doped semiconductor layer 13, which has a high surface flatness, is greater than that of the texture, which enhances the passivation effect of the surface passivation layer 17 on the side of the second doped semiconductor layer 13 away from the silicon substrate 11 and further reduces the carrier recombination rate on the non-light-receiving surface side of the back-contact battery, which is advantageous for improving the photoelectric conversion efficiency of the back-contact battery.

[0064] As shown in FIGS. 2 to 7, the surface of the spacing region 16 may be flat or textured. Here, as shown in FIGS. 2 to 7, when the surface of the spacing region 16 is flat, the surface of the spacing region 16 is relatively smooth. Based on this, when the back-contact cell further includes a surface passivation layer 17, the thickness of the portion of the surface passivation layer 17 formed in the spacing region 16 with a flat surface is greater than that of a textured surface. This can enhance the passivation effect of the surface passivation layer 17 on the spacing region 16 and reduce the carrier recombination rate on the surface of the spacing region 16, which is beneficial to improving the photoelectric conversion efficiency of the back-contact cell. Specifically, the surface roughness of the spacing region 16 may be determined based on the requirements for the passivation effect of the surface passivation layer 17 on the spacing region 16 in actual application scenarios and the actual manufacturing process, and is not specifically limited herein.

[0065] Illustratively, the roughness of the surface of the spacing region within a range of 10,000 square micrometers (a range of 100 micrometers x 100 micrometers) may be 30 μm or less. For example, the roughness of the surface of the spacing region within a range of 10,000 square micrometers may be 5 μm, 10 μm, 12 μm, 15 μm, 18 μm, 20 μm, 22 μm, 25 μm, or 30 μm, etc. The beneficial effects in this case are similar to those when the surface of the spacing region is flat, and therefore will not be described here.

[0066] Here, when the surface of the second region or the spacing region is textured, the size of the texture structure on the surface may be determined according to the depth of the texture recessed into the silicon substrate, and is not specifically limited herein. It can be understood that, within a certain range, the smaller the depth of the texture recessed into the silicon substrate, the smaller the size of the texture structure on the surface. It should also be noted that when the surface of the second region or the spacing region is textured, the depth of the texture recessed into the silicon substrate of the second region or the spacing region is equal to the vertical distance from the center of the texture structure in the second region or the spacing region to the surface of the first region.

[0067] The sidewalls of the spacing region 16 may be perpendicular to the horizontal plane, as shown in Fig. 2. Alternatively, as shown in Fig. 13, at least a portion of the sidewalls of the spacing region 16 may be oblique to the horizontal plane so that the cross-sectional area of at least a portion of the spacing region 16 gradually increases in the direction from the light-receiving surface to the non-light-receiving surface. In this case, the cross-sectional area of the spacing region 16 on the light-receiving surface side is smaller than the cross-sectional area of the non-light-receiving surface side, which is advantageous for increasing the distance between the first doped semiconductor layer 12 and the second doped semiconductor layer 13 of the opposite conductivity type to the first doped semiconductor layer 12, thereby reducing the risk of electrical leakage on the non-light-receiving surface side of the back-contact battery and ensuring high electrical reliability of the back-contact battery. In addition, the portions of the side walls of the spacing region 16 that are oblique to the horizontal plane are also advantageous in reflecting light rays, and are advantageous in allowing more light rays to enter the silicon substrate 11 from the non-light-receiving surface side of the back-contact cell under the reflective action of the portions of the side walls of the spacing region 16 that are oblique to the horizontal plane, which is further advantageous in improving the photoelectric conversion efficiency of the back-contact cell.

[0068] Here, in the above case, the angle between the horizontal plane and the portion of the side wall of the spacing region that is oblique to the horizontal plane may be determined according to the actual manufacturing process and the reflection requirements for the side wall, and is not specifically limited here.

[0069] For example, the angle between the horizontal and the portion of the sidewall of the spacing region that is oblique to the horizontal may be 52° or more and 58° or less. For example, the angle between the horizontal and the portion of the sidewall of the spacing region that is oblique to the horizontal may be 52°, 53°, 54°, 55°, 56°, 57°, or 58°. In this case, if the angle is within the above range, more light can be reflected by the oblique portion of the sidewall of the spacing region and be absorbed by the silicon substrate, thereby further improving the light utilization efficiency of the back-contact cell.

[0070] Regarding the first and second doped semiconductor layers, from a material perspective, the material of the first or second doped semiconductor layer may be a semiconductor material such as silicon, germanium silicon, germanium, or gallium arsenide. From a material arrangement perspective, the crystalline phase of the first or second doped semiconductor layer may be amorphous, microcrystalline, nanocrystalline, single crystal, or polycrystalline. From a conductivity type perspective, as long as the first and second doped semiconductor layers are of opposite conductivity types, the conductivity type of the first or second doped semiconductor layer may be the same as or opposite to that of the silicon substrate. The thickness of the first and second doped semiconductor layers may be set according to actual needs and is not specifically limited herein. For example, the thickness of the first or second doped semiconductor layer may be 100 nm or more and 500 nm or less.

[0071] In actual application, the first doped semiconductor layer may be formed directly on the first region of the silicon substrate. Alternatively, as shown in Figure 2, the back-contact cell further includes a first passivation layer 18 located between the first region 14 of the silicon substrate 11 and the first doped semiconductor layer 12. In this case, the first passivation layer 18 and the first doped semiconductor layer 12 form a selective contact structure, which chemically passivates the first region 14 of the non-light-receiving surface of the silicon substrate 11 and selectively collects carriers of the corresponding conductivity type, thereby reducing the carrier recombination rate on the non-light-receiving surface side and improving the photoelectric conversion efficiency of the back-contact cell.

[0072] Specifically, the material of the first passivation layer may be determined according to the material of the first doped semiconductor layer and the type of selective contact structure consisting of the first passivation layer and the first doped semiconductor layer in the actual application scenario, and is not specifically limited here.

[0073] For example, when the selective contact structure consisting of the first passivation layer and the first doped semiconductor layer is a tunnel passivation contact structure, the first doped semiconductor layer is a doped polycrystalline silicon layer, and the first passivation layer is a tunnel passivation layer, the material of which may include silicon oxide, aluminum oxide, or titanium oxide.

[0074] Furthermore, for example, when the selective contact structure consisting of the first passivation layer and the first doped semiconductor layer is a heterogeneous contact structure, the first doped semiconductor layer is a doped amorphous silicon layer and / or a doped microcrystalline silicon layer, and the first passivation layer is an intrinsic amorphous silicon layer and / or an intrinsic microcrystalline silicon layer.

[0075] The thickness of the first passivation layer may be set according to actual needs and is not specifically limited herein, for example, the thickness of the first passivation layer may be 0.5 nm or more and 3 nm or less.

[0076] The second doped semiconductor layer may be formed directly on the second region of the silicon substrate. Alternatively, as shown in Figure 2, the back-contact cell further includes a second passivation layer 19 located between the second region 15 of the silicon substrate 11 and the second doped semiconductor layer 13. In this case, the second passivation layer 19 and the second doped semiconductor layer 13 form a selective contact structure, which chemically passivates the second region 15 of the non-light-receiving surface of the silicon substrate 11 and selectively collects carriers of the corresponding conductivity type, thereby reducing the carrier recombination rate on the non-light-receiving surface side and improving the photoelectric conversion efficiency of the back-contact cell.

[0077] Specifically, the material and thickness of the second passivation layer can be determined by referring to the material and thickness of the first passivation layer described above, and a detailed description thereof will be omitted here.

[0078] In terms of shape, the embodiments of the present invention do not specifically limit the shape of the side surfaces of the first doped semiconductor layer and the second doped semiconductor layer near the spacing region, as long as they are applicable to the back-contact battery provided by the embodiments of the present invention. Exemplarily, the side surfaces of the first doped semiconductor layer and / or the second doped semiconductor layer near the spacing region may have a linear, polygonal, arcuate, or substantially wavy shape, etc. Here, the shape of the side surface of the first doped semiconductor layer near the spacing region may be the same as or different from the shape of the side surface of the second doped semiconductor layer near the spacing region.

[0079] 3 to 7, in actual application, the side surfaces of the first doped semiconductor layer 12 and the second doped semiconductor layer 13 near the spacing region 16 may both be substantially wavy. The corresponding fluctuation width of the side surface of the second doped semiconductor layer 13 near the spacing region 16 may be larger than the corresponding fluctuation width of the side surface of the first doped semiconductor layer 12 near the spacing region 16, and the corresponding fluctuation frequency of the side surface of the second doped semiconductor layer 13 near the spacing region 16 may be smaller than the corresponding fluctuation frequency of the side surface of the first doped semiconductor layer 12 near the spacing region 16. In this case, if the corresponding variation range of the side surface of the second doped semiconductor layer 13 near the spacing region 16 is larger than the corresponding variation range of the side surface of the first doped semiconductor layer 12 near the spacing region 16, the roughness of the local area of the side surface of the second doped semiconductor layer 13 near the spacing region 16 will be smaller than the roughness of the local area of the side surface of the first doped semiconductor layer 12 near the spacing region 16, which is advantageous to reduce the number of defects in the portion of the formed second doped semiconductor layer 13 near the spacing region 16 and further reduce the carrier recombination rate in the portion of the second doped semiconductor layer 13 near the spacing region 16, thereby further improving the operating performance of the back-contact battery.

[0080] Here, the corresponding fluctuation width of the side surfaces near the spacing region of the first doped semiconductor layer and the second doped semiconductor layer refers to the undulation width of the protruding portion of the side surface relative to the lowest point of the recessed portion of the side surface. Furthermore, the corresponding fluctuation frequency of the side surfaces near the spacing region of the first doped semiconductor layer and the second doped semiconductor layer refers to the frequency at which different protruding portions of the side surfaces appear. Specifically, when the side surfaces near the spacing region of the first doped semiconductor layer and the second doped semiconductor layer are both substantially wavy, the fluctuation width and fluctuation frequency of the side surfaces near the spacing region of the first doped semiconductor layer and the second doped semiconductor layer may be determined according to the actual manufacturing process and are not specifically limited herein.

[0081] In one possible implementation, as shown in FIG. 2 , the back-contact cell may further include a surface passivation layer 17 covering the first doped semiconductor layer 12, the second doped semiconductor layer 13, and the spacing region 16. In this case, the surface passivation layer 17 passivates the non-light-receiving side of the back-contact cell and reduces the carrier recombination rate on the non-light-receiving side. Furthermore, the spacing region 16, which has the deepest recess into the silicon substrate 11, has a corresponding recess depth of less than 3000 nm, which is advantageous for reducing the degree of unevenness in each region on the non-light-receiving side of the back-contact cell and for increasing the thickness of the surface passivation layer 17 formed on the non-light-receiving side, thereby enhancing the passivation effect of the surface passivation layer 17 on the non-light-receiving side.

[0082] Specifically, the material of the surface passivation layer may be any insulating material with passivation function, such as silicon oxide, aluminum oxide, or silicon nitride, etc. The thickness of the surface passivation layer may be determined according to the actual application scenario, and is not specifically limited here.

[0083] In a second aspect, an embodiment of the present invention provides a method for fabricating a back-contact battery. The fabrication process is described below based on the cross-sectional views of the process shown in Figures 2 to 21. Specifically, the back-contact battery fabrication method includes the following steps:

[0084] First, a silicon substrate is prepared, and the non-light-receiving surface of the silicon substrate has first regions and second regions that are alternately distributed at intervals, and an interval region located between the first region and the second region adjacent to the first region itself.

[0085] Specifically, the ranges of the first region, second region, and interval region on the non-light-receiving surface side can be determined by referring to the previous paragraph, and a description thereof will be omitted here.

[0086] Next, as shown in FIGS. 12 to 14, a first doped semiconductor layer 12 is formed in the first region 14, and the surfaces of the spacing region 16 and the second region 15 are both recessed into the silicon substrate 11 relative to the surface of the first region 14.

[0087] 11, after preparing a silicon substrate 11, a first doped semiconductor layer 12 covering the entire surface of the silicon substrate 11 and a first mask layer 20 located in a portion corresponding to the first region 14 of the first doped semiconductor layer 12 can be formed on the non-light-receiving surface of the silicon substrate 11. Next, as shown in FIGS. 12 and 13, under the masking effect of the first mask layer 20, portions of the first doped semiconductor layer 12 located in the spacing region 16 and the second region 15 are selectively removed, and the surfaces of both the spacing region 16 and the second region 15 are recessed into the silicon substrate 11 relative to the surface of the first region 14.

[0088] Here, the material and thickness of the first doped semiconductor layer and the depth of the recesses into the silicon substrate of the surfaces of the gap region and the second region after the process can be referred to above. Regarding the first mask layer, the material of the first mask layer can be any material that has a masking effect, and is not specifically limited herein. Next, the specific materials of the first doped semiconductor layer and the first mask layer can be used to determine the formation process and specific formation steps of the first doped semiconductor layer and the first mask layer.

[0089] For example, when the material of the first doped semiconductor layer includes silicon, the step of forming a first doped semiconductor layer covering the entire thickness of the non-light-receiving surface of the silicon substrate and a first mask layer located in a portion of the first doped semiconductor layer corresponding to the first region may include the following steps: As shown in FIG. 8 , a first intrinsic semiconductor layer 22 covering the entire thickness of the non-light-receiving surface of the silicon substrate 11 is formed. Next, as shown in FIG. 9 , the first intrinsic semiconductor layer 22 is doped to form the first doped semiconductor layer 22 as the first doped semiconductor layer 12, and a first doped silicate glass layer 23 covering the entire thickness of the first doped semiconductor layer 12 is formed on the first doped semiconductor layer 12. Next, as shown in FIG. 10 , the portions of the first doped silicate glass layer 23 corresponding to the gap region 16 and the second region 15 are heat-treated by a laser etching process, thereby forming the unheat-treated portions of the first doped silicate glass layer 23 as the first mask layer 20. Next, as shown in FIG. 11, the heat-treated portion of the first doped silicate glass layer 23 is removed.

[0090] Specifically, the term "the material of the first doped semiconductor layer contains silicon" may mean that the material of the first doped semiconductor layer contains only silicon, or that the material of the first doped semiconductor layer contains not only silicon but also other semiconductor materials, such as germanium silicon. Next, in the actual manufacturing process, a first intrinsic semiconductor layer covering the entire surface of the non-light-receiving surface can be formed by a process such as chemical vapor deposition. Next, the first intrinsic semiconductor layer can be doped by a process such as diffusion. After the doping process, not only can the first doped semiconductor layer be obtained, but also a first doped silicate glass layer covering the entire surface of the first doped semiconductor layer can be formed. Then, a portion of the first doped silicate glass layer is heat-treated by a laser etching process. In this case, as shown in FIG. 10, the laser-treated portion of the first doped silicate glass layer becomes less dense and more easily removed. On the other hand, the portions of the first doped silicate glass layer that are not laser-treated are highly dense and difficult to remove, so that after heat treatment, different portions of the first doped silicate glass layer have different etching selectivities, resulting in a first mask layer 20 for patterning the first doped semiconductor layer 12. This eliminates the need to additionally form other mask materials and perform other mask deposition processes to obtain the first mask layer 20, which is advantageous for reducing the manufacturing cost of back-contact batteries and simplifying the manufacturing process of back-contact batteries. The specific conditions for the laser etching process may be set according to actual application scenarios and are not specifically limited herein.

[0091] For example, the laser used in the laser etching process may be a nanosecond laser, a picosecond laser, a femtosecond laser, etc. The laser etching process may be 10 W or more and 100 W or less, and the diameter of the laser spot may be 50 μm or more and 300 μm or less.

[0092] Of course, when the material of the first doped semiconductor layer contains silicon or does not contain silicon, the first doped semiconductor layer may be formed over the entire surface of the non-light-receiving surface by a process such as chemical vapor deposition and doping, and then a first mask layer having a masking effect and made of another material such as silicon nitride may be formed by a process such as chemical vapor deposition and etching.

[0093] Furthermore, after forming the first mask layer, a wet chemical process can be used to selectively remove portions of the first doped semiconductor layer located in the spacing region and the second region under the masking effect of the first mask layer, thereby recessing the surfaces of both the spacing region and the second region into the silicon substrate relative to the surface of the first region, thereby preventing damage to the silicon substrate by the high-temperature laser, which is advantageous for improving the yield rate of back-contact batteries. Specifically, the process conditions for selectively etching the first doped semiconductor layer can be determined based on the etching process used, the material of the first doped semiconductor layer, and the depth of recesses of the surfaces of the spacing region and the second region into the silicon substrate after the operation, and are not specifically limited herein.

[0094] For example, when a wet chemical process is used to selectively remove portions of the first doped semiconductor layer located in the spacing region and the second region under the masking effect of the first mask layer, and the surfaces of both the spacing region and the second region are recessed into the silicon substrate relative to the surface of the first region, the process temperature of the wet chemical process may be 60° C. or more and 80° C. or less, the process time of the wet chemical process may be 40 seconds or more and 200 seconds or less, the wet chemical etching solution used in the wet chemical process may be an alkaline wet chemical etching solution, and the volume ratio of the alkaline component (e.g., NaOH or KOH) in the alkaline wet chemical etching solution may be 2% or more and 20% or less. For example, the process temperature of the wet chemical process may be 60° C., 70° C., 75° C., 78° C., or 80° C. The process time of the wet chemical process may be 40 seconds, 60 seconds, 80 seconds, 100 seconds, 150 seconds, or 200 seconds. When the wet chemical etching solution used in the wet chemical process is an alkaline wet chemical etching solution, the volume ratio of the alkaline component in the alkaline wet chemical etching solution may be 2%, 3%, 6%, 9%, 12%, 15%, or 20%, for example. In this case, the process temperature and process time of the wet chemical process both affect the depth to which the surfaces of both the spacing region and the second region are recessed into the silicon substrate relative to the surface of the first region. Based on this, when the process temperature of the wet chemical process is within the above range, a low process temperature can prevent the depth to which the surfaces of both the spacing region and the second region are recessed into the silicon substrate relative to the surface of the first region from becoming small. Furthermore, a high process temperature can prevent the depth to which the surfaces of both the spacing region and the second region are recessed into the silicon substrate relative to the surface of the first region from becoming large. After this process, the depth to which the surfaces of the spacing region and the second region are recessed into the silicon substrate relative to the surface of the first region is equal to the depth to which the surface of the second region is recessed into the silicon substrate relative to the surface of the first region in the formed back contact cell.Here, the beneficial effects of preventing the surface of the second region from being recessed deeper into the silicon substrate relative to the surface of the first region can be seen in the above paragraphs. The beneficial effects of the process time and the volume ratio of the alkaline component being within the above ranges are similar to the beneficial effects of the process temperature being 60° C. or more and 80° C. or less, and will not be described here.

[0095] In addition, adding a polishing additive to the wet chemical etching solution can improve the flatness of the surfaces of the gap region and the second region after the etching process, and further enhance the passivation effect of the surface passivation layer on the gap region and the second doped semiconductor layer. Specifically, the components of the polishing additive and the proportion of the polishing additive in the wet chemical etching solution can be determined according to the actual application scenario and are not specifically limited here. For example, the polishing additive can include sodium benzoate, an antifoaming agent, a surfactant, etc. The volume ratio of the polishing additive in the wet chemical etching solution can be 0.5% or more and 5% or less.

[0096] It should be noted that if the fabricated back-contact battery further includes a first passivation layer located between the first region and the first doped semiconductor layer, after providing the silicon substrate and before forming the first doped semiconductor layer in the first region, the fabrication method for the back-contact battery further includes the step of first forming the first passivation layer in the first region by a deposition and etching process.

[0097] Alternatively, as shown in Fig. 8, a silicon substrate may be prepared, and then a first passivation layer 18 may be formed over the entire non-light-receiving surface side by a process such as chemical vapor deposition. Then, as shown in Figs. 11 to 13, a first mask layer 20 may be formed, and the first doped semiconductor layer 12 may be selectively etched under the masking effect of the first mask layer 20, followed by selective etching of the first passivation layer 18. In this case, there is no need to form an additional mask layer to form the first passivation layer 18, simplifying the manufacturing process of the back-contact battery.

[0098] Next, after both the surfaces of the spacing region and the second region are recessed into the silicon substrate relative to the surface of the first region, a second doped semiconductor layer 13 is formed in the second region 15, and the surface of the spacing region 16 is recessed into the silicon substrate 11 relative to the surface of the second region 15, and the depth to which the surface of the spacing region 16 is recessed into the silicon substrate 11 relative to the surface of the first region 14 is less than 3000 nm, as shown in FIG.

[0099] 18, after the surfaces of both the spacing region 16 and the second region 15 are recessed into the silicon substrate 11 relative to the surface of the first region 14, a second doped semiconductor layer 13 is deposited on the first doped semiconductor layer 12, the spacing region 16, and the second region 15, and a second mask layer 21 is formed on the portion of the second doped semiconductor layer 13 corresponding to the second region 15. Next, as shown in FIG. 19, under the masking effect of the second mask layer 21, the portions of the second doped semiconductor layer 13 corresponding to the first region 14 and the spacing region 16 are selectively removed, and the surface of the spacing region 16 is recessed into the silicon substrate 11 relative to the surface of the second region 15.

[0100] Specifically, the material and thickness of the second doped semiconductor layer and the depth of the recess of the surface of the gap region into the silicon substrate after the process can be referred to above, and will not be described here. The material of the second mask layer may be any material that has a masking function. In actual manufacturing, the formation process and specific formation process of the second doped semiconductor layer and the second mask layer may be determined depending on the materials of the second doped semiconductor layer and the second mask layer.

[0101] For example, when the material of the second doped semiconductor layer includes silicon, the step of depositing the second doped semiconductor layer in the first doped semiconductor layer, the spacing region, and the second region and forming a second mask layer in the portion of the second doped semiconductor layer corresponding to the second region may include the following steps: As shown in FIG. 15 , a second intrinsic semiconductor layer 24 is deposited in the first doped semiconductor layer 12, the spacing region 16, and the second region 15. Next, as shown in FIG. 16 , the second intrinsic semiconductor layer 24 is doped to form the second intrinsic semiconductor layer 24 as the second doped semiconductor layer 13, and a second doped silicate glass layer 25 is formed over the entire second doped semiconductor layer 13. Next, as shown in FIG. 17 , the portions of the second doped silicate glass layer 25 corresponding to the first region 14 and the spacing region 16 are heat-treated by a laser etching process to form the portion of the second doped silicate glass layer 25 corresponding to the second region 15 as the second mask layer 21. Thereafter, as shown in FIG. 18, the heat-treated portion of the second doped silicate glass layer 25 is removed.

[0102] Specifically, the term "the material of the second doped semiconductor layer contains silicon" may mean that the material of the second doped semiconductor layer contains only silicon, or that the material of the second doped semiconductor layer contains not only silicon but also other semiconductor materials, such as germanium silicon. Next, in the actual manufacturing process, a second intrinsic semiconductor layer covering the entire surface of the non-light-receiving surface side can be formed by a process such as chemical vapor deposition. Next, the second intrinsic semiconductor layer can be doped by a process such as diffusion. After the doping process, not only can the second doped semiconductor layer be obtained, but also a second doped silicate glass layer covering the entire surface of the second doped semiconductor layer can be formed on the second doped semiconductor layer. Then, the portions of the second doped silicate glass layer corresponding to the first region and the gap region can be heat-treated by a laser etching process. In this case, the laser-treated portions of the second doped silicate glass layer become less dense and are more easily removed. On the other hand, the portion of the second doped silicate glass layer corresponding to the second region is not laser-treated, and therefore is highly dense and difficult to remove. As a result, different portions of the second doped silicate glass layer have different etching selectivities after heat treatment, and a second mask layer is obtained for patterning the second doped semiconductor layer. This eliminates the need for additional mask materials and mask deposition processes to obtain the second mask layer, which is advantageous for reducing the manufacturing cost of back-contact batteries and simplifying the manufacturing process of back-contact batteries. The specific conditions for the laser etching process are described above and are not specifically limited herein.

[0103] Of course, when the material of the second doped semiconductor layer contains silicon or does not contain silicon, the second doped semiconductor layer may be formed over the entire surface of the non-light-receiving surface by a process such as chemical vapor deposition and doping, and then a second mask layer having a masking effect and made of another material such as silicon nitride may be formed by a process such as chemical vapor deposition and etching.

[0104] Furthermore, after forming the second mask layer, a wet chemical process or other process can be used to selectively remove the portions of the second doped semiconductor layer located in the spacing region and the first doped semiconductor layer under the masking effect of the second mask layer, thereby recessing the surface of the spacing region into the silicon substrate relative to the surface of the second region, thereby preventing damage to the silicon substrate by the high-temperature laser, which is advantageous for improving the yield rate of back-contact batteries. Specifically, the process conditions for selectively etching the second doped semiconductor layer can be determined based on the etching process used, the material of the second doped semiconductor layer, and the recess depth of the surface of the spacing region into the silicon substrate, and are not specifically limited here.

[0105] For example, when a wet chemical process is used to selectively remove a portion of the second doped semiconductor layer corresponding to the gap region under the masking effect of the second mask layer, and the surface of the gap region is recessed into the silicon substrate relative to the surface of the second region, the process temperature of the wet chemical process may be 60°C or more and 80°C or less, the process time of the wet chemical process may be 50 seconds or more and 300 seconds or less, the wet chemical etching solution used in the wet chemical process may be an alkaline wet chemical etching solution, and the volume ratio of the alkaline component (e.g., NaOH or KOH) in the alkaline wet chemical etching solution may be 2% or more and 20% or less. For example, the process temperature of the wet chemical process may be 60°C, 70°C, 75°C, 78°C, or 80°C, etc. The process time of the wet chemical process may be 50 seconds, 55 seconds, 60 seconds, 100 seconds, 150 seconds, 200 seconds, or 300 seconds, etc. When the wet chemical etching solution used in the wet chemical process is an alkaline wet chemical etching solution, the volume ratio of the alkaline component in the alkaline wet chemical etching solution may be 2%, 3%, 6%, 9%, 12%, 15%, or 20%, for example. In this case, the process temperature and process time of the wet chemical process both affect the depth to which the surface of the spacing region is recessed into the silicon substrate relative to the surface of the second region by the wet chemical process. Based on this, when the process temperature of the wet chemical process is within the above range, a low process temperature can prevent the depth to which the surface of the spacing region is recessed into the silicon substrate relative to the surface of the second region from becoming small. Furthermore, a high process temperature can prevent the depth to which the surface of the spacing region is recessed into the silicon substrate relative to the surface of the second region from becoming large. See the preceding paragraph for the beneficial effects of preventing the depth to which the surface of the spacing region is recessed into the silicon substrate relative to the surface of the second region from becoming small or large. Next, the beneficial effects of the process time and the volume ratio of the alkaline component being within the above ranges are similar to the beneficial effects of the process temperature being 60°C or higher and 80°C or lower, and therefore will not be explained here.

[0106] In addition, adding a polishing additive to the wet chemical etching solution can improve the surface flatness of the gap region after the operation and further enhance the passivation effect of the surface passivation layer on the gap region. Specifically, the components of the polishing additive and the proportion of the polishing additive in the wet chemical etching solution can be determined according to the actual application scenario and are not specifically limited here. For example, the polishing additive can include sodium benzoate, an antifoaming agent, a surfactant, etc. The volume ratio of the polishing additive in the wet chemical etching solution can be 0.5% or more and 5% or less.

[0107] It should be explained that if the fabricated back-contact battery further includes a second passivation layer located between the second region and the second doped semiconductor layer, after recessing the surfaces of both the spacing region and the second region into the silicon substrate relative to the surface of the first region, and before forming the second doped semiconductor layer in the portion of the second region, the fabrication method for the back-contact battery further includes the step of first forming the second passivation layer in the second region by a deposition and etching process.

[0108] Alternatively, as shown in Figure 15, after both the surfaces of the spacing region and the second region are recessed into the silicon substrate relative to the surface of the first region, a second passivation layer 19 may be deposited on the first doped semiconductor layer, the second region, and the spacing region by a process such as chemical vapor deposition before forming a second doped semiconductor layer in the second region. Thereafter, as shown in Figures 18 and 19, a second mask layer 21 is formed, and the second doped semiconductor layer is selectively etched under the masking effect of the second mask layer 21, followed by selective etching of the second passivation layer 19. In this case, there is no need to additionally form a corresponding mask layer to form the second passivation layer 19, simplifying the manufacturing process of the back-contact cell.

[0109] Furthermore, if the fabricated back-contact battery further includes a surface passivation layer covering the first doped semiconductor layer, the second doped semiconductor layer, and the spacing region, after the surface of the spacing region is recessed into the silicon substrate relative to the surface of the second region, a surface passivation layer 17 can be formed by a process such as chemical vapor deposition to cover the first doped semiconductor layer 12, the second doped semiconductor layer 13, and the spacing region 16, as shown in Figure 21. The material and thickness of the surface passivation layer 17 can be determined by reference to the preceding paragraph.

[0110] The beneficial effects of the second aspect and various embodiments of the present invention may be understood by reference to the analysis of the beneficial effects of the first aspect and various embodiments thereof, and will not be described further here.

[0111] In addition, the present invention also provides one comparative example and one example to illustrate the manufacturing process and operating performance of the back contact battery provided by the present invention. Here, Table 1 shows the test results of the back contact batteries corresponding to Example 1 and Comparative Example 1. Example 1

[0112] Step 1: A single crystal silicon wafer is subjected to alkaline polishing treatment using a 15% alkaline solution to form a smooth and clean silicon surface.

[0113] Step 2: A tunnel oxide layer and an intrinsic polysilicon layer are sequentially deposited on the surface of the single-crystal silicon wafer, where the tunnel oxide layer is 1.8 nm thick and the intrinsic polysilicon layer is 350 nm thick.

[0114] Step 3: The deposited intrinsic polysilicon layer is doped with boron to form a P-type doped polysilicon layer, and a borosilicate glass layer is formed on the P-type doped polysilicon layer, where the boron doping concentration is 8×10 19 / cm 3 is.

[0115] Step 4: The borosilicate glass layer is heat-treated through a laser etching process to form a mask layer with a specific pattern, where the laser can be a picosecond laser, the processing power can be 40W, and the spot diameter can be 200µm.

[0116] Step 5: Using the masking layer, a portion of the P-doped polycrystalline silicon layer is selectively removed. The single-crystalline silicon wafer is then subjected to a surface etching process to form a groove structure. The etching solution mainly contains alkali and polishing additives. The alkali concentration in the etching solution is 5%, the etching temperature is 82°C, the process time is 300 seconds, and the volume ratio of the polishing additive is 2%. The polishing additive mainly contains sodium benzoate, an antifoaming agent, and a surfactant.

[0117] Step 6: forming a tunnel oxide layer and an N-type doped polysilicon layer sequentially at the bottom of the trench structure, and recessing a portion of the single-crystalline silicon wafer between the P-type doped polysilicon layer and the N-type doped polysilicon layer into the silicon substrate relative to the bottom of the trench structure. The thickness of the N-type doped polysilicon layer is 150 nm or more and 180 nm or less. The thickness of the tunnel oxide layer is 0.5 nm or more and 3 nm or less. The depth of the recess into the silicon substrate of the portion of the single-crystalline silicon wafer between the P-type doped polysilicon layer and the N-type doped polysilicon layer is less than 3000 nm.

[0118] Step 7: forming a surface passivation layer covering the single crystal silicon wafer, the P-type doped polycrystalline silicon layer, and the N-type doped polycrystalline silicon layer. Comparative Example 1

[0119] The manufacturing method of Comparative Example 1 is similar to the manufacturing flow of Example 1 except for step 6. Here, the manufacturing method provided by Comparative Example 1 includes forming a tunnel oxide layer and an N-type doped polycrystalline silicon layer sequentially stacked at the bottom of the trench structure, and then recessing the portion of the single crystal silicon wafer located between the P-type doped polycrystalline silicon layer and the N-type doped polycrystalline silicon layer into the silicon substrate to a depth of more than 5 μm, and providing a textured surface at the portion of the single crystal silicon wafer located between the P-type doped polycrystalline silicon layer and the N-type doped polycrystalline silicon layer.

[0120] [Table 1]

[0121] The data shown in Table 1 show that the back-contact battery fabricated by the fabrication method provided in Example 1 has a small recess depth in the silicon substrate in the gap region, which shortens the carrier migration distance. Furthermore, if the back-contact battery further includes a surface passivation layer, the passivation effect of the surface passivation layer on the gap region can be enhanced. This results in higher operating efficiency, open-circuit voltage, short-circuit current, and fill factor than the back-contact battery obtained by the corresponding fabrication method in Comparative Example 1. That is, the back-contact battery provided by the embodiments of the present invention has better operating performance.

[0122] The above description does not provide a detailed description of the technical details of each layer, such as the structure and etching of each layer. However, those skilled in the art should understand that layers, regions, etc. of desired shapes can be formed using various technical means. Furthermore, those skilled in the art can design methods that are not completely identical to the methods described above to form the same structure. Furthermore, although each embodiment has been described separately above, this does not mean that the measures in each embodiment cannot be advantageously used together.

[0123] The above describes the embodiments of the present disclosure. However, these embodiments are merely for illustrative purposes and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is limited by the appended claims and their equivalents. Those skilled in the art can make various substitutions and modifications without departing from the scope of the present disclosure, and all of these substitutions and modifications are intended to fall within the scope of the present disclosure. [Explanation of symbols]

[0124] 11 Silicon substrate 12 First doped semiconductor layer 13 Second doped semiconductor layer 14 First area 15 Second area 16 Interval area 17 Surface passivation layer 18 First passivation layer 19 Second passivation layer 20 First mask layer 21 Second mask layer 22 first intrinsic semiconductor layer 23 First doped silicate glass layer 24 Second intrinsic semiconductor layer 25 Second doped silicate glass layer

Claims

1. The semiconductor device includes a silicon substrate, and first and second doped semiconductor layers alternately distributed at intervals on a non-light-receiving surface side of the silicon substrate, the first doped semiconductor layer and the second doped semiconductor layer are of opposite conductivity types, a region on the non-light-receiving surface of the silicon substrate corresponding to the first doped semiconductor layer is a first region, a region on the non-light-receiving surface of the silicon substrate corresponding to the second doped semiconductor layer is a second region, a region located between the first region and the second region adjacent to it is a spacing region, a surface of the second region is recessed into the silicon substrate with respect to a surface of the first region, a surface of the spacing region is recessed into the silicon substrate with respect to a surface of the second region, and a depth of the recess of the surface of the spacing region into the silicon substrate with respect to the surface of the first region is less than 3000 nm, and side surfaces of the first doped semiconductor layer and the second doped semiconductor layer near the spacing region are both substantially wavy, A back-contact battery, characterized in that the corresponding fluctuation range of the side surface of the second doped semiconductor layer near the spacing region is larger than the corresponding fluctuation range of the side surface of the first doped semiconductor layer near the spacing region, and / or the corresponding fluctuation frequency of the side surface of the second doped semiconductor layer near the spacing region is smaller than the corresponding fluctuation frequency of the side surface of the first doped semiconductor layer near the spacing region.

2. the surface of the spacing region has a roughness of 30 μm or less per 10,000 square micrometers; and / or The back-contact battery of claim 1 , wherein the length of the spacing region is 20 μm or more and 110 μm or less in the direction of arrangement of the first and second regions.

3. the surface of the second region is planar; and / or the surface of the second region is recessed into the silicon substrate to a depth of 100 nm or more and 1000 nm or less; and / or 2. The back contact battery of claim 1, wherein the height difference between the surface of the second region and the surface of the spacing region is 300 nm or more and less than 2000 nm.

4. 2. The back contact battery of claim 1, wherein at least a portion of the sidewall of the spacing region is oblique to a horizontal plane so that the cross-sectional area of at least a portion of the spacing region gradually increases in a direction from the light-receiving surface to the non-light-receiving surface.

5. and / or a surface passivation layer covering the first doped semiconductor layer, the second doped semiconductor layer and the spacing region. and / or a first passivation layer located between the first region of the silicon substrate and the first doped semiconductor layer.

5. The back contact battery of claim 1, further comprising a second passivation layer located between the second region of the silicon substrate and the second doped semiconductor layer.

6. When the back contact cell includes the first passivation layer and the first passivation layer is a tunnel passivation layer, the first doped semiconductor layer is a doped polycrystalline silicon layer; and / or 6. The back contact battery of claim 5, wherein when the back contact battery includes the second passivation layer and the second passivation layer is a tunnel passivation layer, the second doped semiconductor layer is a doped polycrystalline silicon layer.

7. preparing a silicon substrate, the non-light receiving surface of the silicon substrate having first and second regions alternately distributed at intervals, and an interval region located between the first region and the second region adjacent to the first region; forming a first doped semiconductor layer in the first region, with surfaces of the spacing region and the second region both recessed into the silicon substrate relative to a surface of the first region; forming a second doped semiconductor layer in the second region, recessing a surface of the spacing region into the silicon substrate relative to a surface of the second region, and setting a depth of the surface of the spacing region recessed into the silicon substrate relative to a surface of the first region to less than 3000 nm, wherein both sides of the first doped semiconductor layer and the second doped semiconductor layer near the spacing region are substantially wavy; A method for manufacturing a back-contact battery, characterized in that the corresponding fluctuation range of the side surface of the second doped semiconductor layer near the spacing region is larger than the corresponding fluctuation range of the side surface of the first doped semiconductor layer near the spacing region, and / or the corresponding fluctuation frequency of the side surface of the second doped semiconductor layer near the spacing region is smaller than the corresponding fluctuation frequency of the side surface of the first doped semiconductor layer near the spacing region.

8. After the step of providing a silicon substrate and before the step of forming a second doped semiconductor layer in the second region, the method for manufacturing a back-contact cell includes: forming a first doped semiconductor layer provided over the entire surface of the silicon substrate, and a first mask layer located in a portion of the first doped semiconductor layer corresponding to the first region; and selectively removing portions of the first doped semiconductor layer located in the spacing region and the second region under the masking effect of the first mask layer, and recessing surfaces of both the spacing region and the second region into the silicon substrate relative to a surface of the first region.

9. the material of the first doped semiconductor layer comprises silicon; The step of forming a first doped semiconductor layer provided over the entire surface of the silicon substrate and a first mask layer located in a portion of the first doped semiconductor layer corresponding to the first region includes: forming a first intrinsic semiconductor layer on the non-light-receiving surface of the silicon substrate, the first intrinsic semiconductor layer being provided over the entire surface of the silicon substrate; doping the first intrinsic semiconductor layer to form the first doped semiconductor layer, and forming a first doped silicate glass layer over the first doped semiconductor layer; heat-treating the portions of the first doped silicate glass layer corresponding to the gap region and the second region by a laser etching process to form the portions of the first doped silicate glass layer that have not been subjected to the heat treatment as the first mask layer; and removing the heat-treated portion of the first doped silicate glass layer.

10. selectively removing portions of the first doped semiconductor layer located in the spacing region and the second region under the masking effect of the first mask layer by a wet chemical process, and recessing surfaces of both the spacing region and the second region into the silicon substrate relative to the surface of the first region; 10. The method for manufacturing a back contact battery according to claim 8, wherein the wet chemical process has a process temperature of 60° C. or higher and 80° C. or lower; and / or the wet chemical process has a process time of 40 seconds or higher and 200 seconds or lower; and / or the wet chemical etching solution used in the wet chemical process is an alkaline wet chemical etching solution, and the volume ratio of the alkaline component in the alkaline wet chemical etching solution is 2% or higher and 20% or lower; and / or the wet chemical etching solution used in the wet chemical process contains a polishing additive, and the volume ratio of the polishing additive in the wet chemical etching solution is 0.5% or higher and 5% or lower.

11. After the step of recessing both the surfaces of the spacing region and the second region into the silicon substrate relative to the surface of the first region, the method of manufacturing the back contact battery further comprises: depositing a second doped semiconductor layer on the first doped semiconductor layer, the spacing region, and the second region, and forming a second mask layer on a portion of the second doped semiconductor layer corresponding to the second region; and selectively removing portions of the second doped semiconductor layer corresponding to the first region and the spacing region under the masking effect of the second mask layer, and recessing a surface of the spacing region into the silicon substrate relative to a surface of the second region.

12. the material of the second doped semiconductor layer comprises silicon; The step of depositing a second doped semiconductor layer on the first doped semiconductor layer, the spacing region, and the second region, and forming a second mask layer on a portion of the second doped semiconductor layer corresponding to the second region, includes: depositing a second intrinsic semiconductor layer on the first doped semiconductor layer, the spacing region, and the second region; doping the second intrinsic semiconductor layer to form the second doped semiconductor layer, and forming a full-thickness second doped silicate glass layer on the second doped semiconductor layer; heat-treating the portions of the second doped silicate glass layer corresponding to the first region and the spacing region by a laser etching process to form the portions of the second doped silicate glass layer corresponding to the second region as the second mask layer; and removing the heat-treated portion of the second doped silicate glass layer.

13. selectively removing portions of the second doped semiconductor layer corresponding to the first region and the spacing region under the masking effect of the second mask layer by a wet chemical process, and recessing a surface of the spacing region into the silicon substrate relative to a surface of the second region; 12. The method for manufacturing a back contact battery according to claim 11, wherein the wet chemical process has a process temperature of 60° C. or higher and 80° C. or lower; and / or the wet chemical process has a process time of 50 seconds or higher and 300 seconds or lower; and / or the wet chemical etching solution used in the wet chemical process is an alkaline wet chemical etching solution, and the volume ratio of the alkaline component in the alkaline wet chemical etching solution is 2% or higher and 20% or lower; and / or the wet chemical etching solution used in the wet chemical process contains a polishing additive, and the volume ratio of the polishing additive in the wet chemical etching solution is 0.5% or higher and 5% or lower.

14. After the step of providing a silicon substrate and before the step of forming a first doped semiconductor layer in the first region, the method for manufacturing a back contact cell further includes the step of forming a first passivation layer in the first region; and / or After the step of recessing surfaces of both the spacing region and the second region into the silicon substrate relative to the surface of the first region, and before the step of forming a second doped semiconductor layer in portions of the second region, the method of manufacturing a back contact cell further includes the step of forming a second passivation layer in the second region; and / or 14. The method for manufacturing a back contact battery of claim 7, wherein after the step of recessing the surface of the spacing region into the silicon substrate relative to the surface of the second region, the method for manufacturing a back contact battery further comprises the step of forming a surface passivation layer covering the first doped semiconductor layer, the second doped semiconductor layer, and the spacing region.

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