Operational amplifier

Abstract

To provide an operational amplifier capable of outputting large current.SOLUTION: A first current source CS1 is connected to a power supply line 302. A first transistor M1 has a gate connected to an input terminal IN and a source connected to a ground line 304. A second current source CS2 is connected between a first node N1 which is a drain of the first transistor M1 and the ground line. An assist current generation circuit 330 generates assist current Ib which increases as an intermediate signal Vm decreases. A current mirror circuit 350 mirrors the assist current Ib and supplies it to an output terminal OUT.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to operational amplifiers. [Background technology]

[0002] An operational amplifier (differential amplifier) is used to amplify the difference between two input voltages. The size of the output transistor in the output stage of the operational amplifier is designed according to the expected maximum output current. An operational amplifier with a large maximum output current requires a large bias current, which results in a large current consumption. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2023-95124

[0004] [overview] The present disclosure has been made in light of such a situation, and one exemplary purpose of an embodiment thereof is to provide an operational amplifier capable of outputting a large current.

[0005] One aspect of the present disclosure relates to an operational amplifier having an input stage and an output stage. the output stage includes an input terminal that receives an intermediate signal from the input stage, an output terminal, a power supply line, a ground line, a first current source connected to the power supply line, an N-channel first transistor having a gate connected to the input terminal and a source connected to the ground line, a second current source connected between a first node that is the drain of the first transistor and the ground line, a first clamp circuit connected between the first node and the output terminal and clamping the voltage of the first node, a second clamp circuit connected between the first current source and the output terminal and clamping the voltage of a connection node with the first current source, an assist current generation circuit that generates an assist current that increases as the intermediate signal decreases, a third current source connected between a second node that is the output node of the assist current generation circuit and the ground line, a third clamp circuit that clamps the voltage of the second node, a current mirror circuit that reflects the current flowing to the second node, and a fourth clamp circuit connected between the output node of the current mirror circuit and the output terminal and clamping the voltage of the output node of the current mirror circuit.

[0006] Another aspect of the present disclosure is also an operational amplifier, the output stage of which includes an input terminal receiving an intermediate signal from the input stage, an output terminal, a power supply line, a ground line, a first current source connected to the ground line, a P-channel first transistor having a gate connected to the input terminal and a source connected to the power supply line, a second current source connected between the power supply line and a first node which is the drain of the first transistor, a first clamp circuit connected between the first node and the output terminal and clamping the voltage of the first node, a second clamp circuit connected between the first current source and the output terminal and clamping the voltage of a node connecting the first current source and the output terminal, an assist current generation circuit which generates an assist current that increases as the intermediate signal increases, a third current source connected between the ground line and a second node which is the output node of the assist current generation circuit, a third clamp circuit connected between the ground line and a second node which is the output node of the assist current generation circuit, a current mirror circuit which reflects the current flowing to the second node, and a fourth clamp circuit connected between the output node of the current mirror circuit and the output terminal and clamping the voltage of the output node of the current mirror circuit.

[0007] Any combination of the above elements, or mutual substitution of elements or expressions between methods, devices, systems, etc., are also valid aspects of the present invention or the present disclosure. Furthermore, the description in this section (Means for Solving the Problems) does not explain all essential features of the present invention, and therefore, subcombinations of the described features may also constitute the present invention. [Brief explanation of the drawings]

[0008] [Figure 1] Figure 1 is a circuit diagram of an operational amplifier. [Figure 2] FIG. 2 is a circuit diagram of an output stage according to the embodiment. [Figure 3] FIG. 3 is a circuit diagram illustrating the operation of the output stage in a light load state. [Figure 4] FIG. 4 is a circuit diagram illustrating the operation of the output stage under heavy load conditions. [Figure 5] FIG. 5 is a circuit diagram of an output stage according to one embodiment. [Figure 6] FIG. 6 is a circuit diagram of an output stage according to a modified example. [Figure 7] FIG. 7 is a circuit diagram of an output stage according to one embodiment.

[0009] [Detailed explanation] (Outline of the embodiment) A summary of some exemplary embodiments of the present disclosure is provided. This summary is intended to provide a simplified overview of some concepts of one or more embodiments in order to provide a basic understanding of the embodiments as a prelude to the more detailed description that follows. It is not intended to limit the scope of the invention or disclosure. This summary is not an exhaustive overview of all possible embodiments, and is not intended to identify key elements of all embodiments or to delineate the scope of some or all aspects. For convenience, the term "one embodiment" may refer to one embodiment (example or variant) or multiple embodiments (examples or variants) disclosed herein.

[0010] An operational amplifier according to one embodiment has an input stage and an output stage. The output stage includes an input terminal receiving an intermediate signal from the input stage, an output terminal, a power supply line, a ground line, a first current source connected to the power supply line, a first N-channel transistor having a gate connected to the input terminal and a source connected to the ground line, a second current source connected between a first node (the drain of the first transistor) and the ground line, a first clamp circuit connected between the first node and the output terminal and clamping the voltage of the first node, a second clamp circuit connected between the first current source and the output terminal and clamping the voltage of a node connecting the first current source and the output terminal, an assist current generation circuit that generates an assist current that increases as the intermediate signal decreases, a third current source connected between a second node (the output node of the assist current generation circuit) and the ground line, a third clamp circuit clamping the voltage of the second node, a current mirror circuit that reflects the current flowing through the second node, and a fourth clamp circuit connected between an output node of the current mirror circuit and the output terminal and clamping the voltage of the output node of the current mirror circuit.

[0011] Under light load conditions, the assist current generated by the assist current generation circuit is zero, and the first transistor is biased by the current generated by the first current source, operating as a class A amplifier. Under heavy load conditions, the current flowing through the first transistor approaches zero, and instead the assist current increases in response to the intermediate signal, which is then reflected by the current mirror circuit and sourced to the load. This allows for large current output.

[0012] In one embodiment, the assist current generating circuit includes a second N-channel transistor having a gate connected to the input terminal and a source connected to a ground line, a fifth clamp circuit that clamps the voltage of the drain of the second transistor, a fourth current source connected to a power supply line, a sixth clamp circuit that clamps the voltage of the output node of the fourth current source, and a third N-channel transistor having a gate connected to the drain of the second transistor and a source connected to the power supply line, and the current flowing through the third transistor may be the assist current.

[0013] In one embodiment, the first clamp circuit and the third clamp circuit may each include a high-voltage NMOS transistor having a bias voltage applied to its gate.

[0014] In one embodiment, the second clamp circuit and the fourth clamp circuit may each include a high-voltage PMOS transistor having a bias voltage applied to its gate.

[0015] In one embodiment, the fifth clamp circuit may include a high-voltage NMOS transistor having a bias voltage applied to its gate, and the sixth clamp circuit may include a high-voltage PMOS transistor having a bias voltage applied to its gate.

[0016] According to one embodiment, an operational amplifier has an input stage and an output stage. The output stage includes an input terminal receiving a signal from the input stage, an output terminal, a power supply line, a ground line, a first current source connected to the ground line, a P-channel first transistor having a gate connected to the input terminal and a source connected to the power supply line, a second current source connected between the power supply line and a first node that is the drain of the first transistor, a first clamp circuit connected between the first node and the output terminal and clamping the voltage of the first node, a second clamp circuit connected between the first current source and the output terminal and clamping the voltage of a node connecting the first current source and the output terminal, an assist current generation circuit that generates an assist current that increases as the intermediate signal increases, a third current source connected between the ground line and a second node that is the output node of the assist current generation circuit, a third clamp circuit connected between the ground line and a second node that is the output node of the assist current generation circuit, a current mirror circuit that reflects the current flowing through the second node, and a fourth clamp circuit connected between an output node of the current mirror circuit and the output terminal and clamping the voltage of the output node of the current mirror circuit.

[0017] Under light load conditions, the assist current generated by the assist current generation circuit is zero, and the first transistor is biased by the current generated by the first current source, operating as a class A amplifier. Under heavy load conditions, the current flowing through the first transistor approaches zero, and instead the assist current increases in response to the intermediate signal, which is then folded back by the current mirror circuit and sunk from the load. This allows for large current output.

[0018] In one embodiment, the assist current generating circuit includes a second P-channel transistor having a gate connected to the input terminal and a source connected to a power supply line, a fifth clamp circuit that clamps the voltage of the drain of the second transistor, a fourth current source connected to the ground line, a sixth clamp circuit that clamps the voltage of the output node of the fourth current source, and a third P-channel transistor having a gate connected to the drain of the second transistor and a source connected to the power supply line, and the current flowing through the third transistor may be the assist current.

[0019] In one embodiment, the first clamp circuit and the third clamp circuit may each include a high-voltage NMOS transistor having a bias voltage applied to its gate.

[0020] In one embodiment, the second clamp circuit and the fourth clamp circuit may each include a high-voltage PMOS transistor having a bias voltage applied to its gate.

[0021] In one embodiment, the fifth clamp circuit may include a high-voltage NMOS transistor having a bias voltage applied to its gate, and the sixth clamp circuit may include a high-voltage PMOS transistor having a bias voltage applied to its gate.

[0022] In one embodiment, the operational amplifier may be monolithically integrated on a single semiconductor substrate. "Monolithically integrated" includes cases where all of the circuit components are formed on a semiconductor substrate, and cases where the main circuit components are monolithically integrated, and some resistors, capacitors, etc. for adjusting the circuit constants may be provided outside the semiconductor substrate.

[0023] (Embodiment) Preferred embodiments will be described below with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing will be given the same reference numerals, and redundant explanations will be omitted as appropriate. Furthermore, the embodiments are examples and do not limit the disclosure and invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the disclosure and invention.

[0024] In this specification, "a state in which component A is connected to component B" includes not only a case in which component A and component B are directly physically connected to each other, but also a case in which component A and component B are indirectly connected to each other via other components that do not substantially affect the electrical connection between them or that do not impair the function or effect achieved by their connection.

[0025] Similarly, "a state in which component C is connected (provided) between component A and component B" includes not only a case in which component A and component C, or component B and component C, are directly connected, but also a case in which they are indirectly connected via other components that do not substantially affect the electrical connection state between them or that do not impair the function or effect achieved by their combination.

[0026] In addition, in this specification, symbols attached to electrical signals such as voltage signals and current signals, or circuit elements such as resistors, capacitors, and inductors, represent the respective voltage values, current values, or circuit constants (resistance values, capacitance values, inductances) as necessary.

[0027] First, the basic configuration of an operational amplifier will be described with reference to FIG.

[0028] 1 is a circuit diagram of an operational amplifier 100. The operational amplifier 100 receives differential input signals Vp and Vn at differential input terminals INP and INN, and outputs an amplified output signal from an output terminal OUT. The operational amplifier 100 may be a voltage output type or a current output type transconductance amplifier. A power supply voltage V DD is supplied to the ground terminal GND, and the ground terminal GND is grounded.

[0029] The operational amplifier 100 includes an input stage 200 and an output stage 300. The input stage 200 may include a differential input stage that amplifies the potential difference between differential input signals Vp and Vn to generate a differential current, and a gain stage that further amplifies the differential current to generate an intermediate signal Vm.

[0030] The output stage 300 generates a signal corresponding to the intermediate signal Vm at the output terminal OUT. The output stage 300 functions as a buffer to prevent the operational amplifier 100 from being affected by a load (not shown) connected to the output terminal OUT.

[0031] 2 is a circuit diagram of an output stage 300 according to an embodiment. The output stage 300 includes a power supply line 302, a ground line 304, a first transistor M1, a first clamp circuit 310, a second clamp circuit 320, an assist current generating circuit 330, a third clamp circuit 340, a current mirror circuit 350, and a fourth clamp circuit 360.

[0032] A power supply voltage VDD is supplied to the power supply line 302, and the ground line 304 is grounded.

[0033] The output stage 300 is configured by a combination of a low-voltage transistor with a relatively low drain-source voltage and a high-voltage transistor with a relatively high drain-source voltage.

[0034] The first transistor M1 has a source grounded and a gate connected to the input node IN of the output stage 300. The gate of the first transistor M1 receives an intermediate signal Vm generated by the preceding input stage 200. A current Ia(Vm) that depends on the gate voltage Vm flows through the first transistor M1.

[0035] The first clamp circuit 310 is connected between the output terminal OUT and the drain of the first transistor M1. The first clamp circuit 310 clamps the drain voltage of the first transistor M1 so that it does not exceed a predetermined clamp level. The clamp level is determined taking into account the withstand voltage between the drain and source of the first transistor M1.

[0036] The first current source CS1 is connected to the power supply line 302 and sources a constant current Ic1. The first current source CS1 is configured with a low-voltage transistor.

[0037] The second clamp circuit 320 is connected between the first current source CS1 and the output terminal OUT, and clamps the voltage at the connection node with the first current source CS1 so that it does not fall below a predetermined clamp level. The clamp level is determined taking into consideration the drain-source breakdown voltage of the PMOS transistor that constitutes the first current source CS1.

[0038] The second current source CS2 is connected between the drain of the first transistor M1 and the ground line 304, and sinks a constant current Ic2. The constant current Ic2 is provided to prevent the node N1 at the drain of the first transistor M1 from becoming high impedance when the first transistor M1 is off. The second current source CS2 is composed of a low-voltage transistor.

[0039] The assist current generating circuit 330 is connected to the input node IN and receives the intermediate signal Vm. The assist current generating circuit 330 sinks an assist current Ib(Vm) corresponding to the intermediate signal Vm. The amount of the assist current Ib(Vm) has a negative correlation with the intermediate signal Vm, and the lower the intermediate signal Vm, the greater the assist current Ib(Vm).

[0040] The third clamp circuit 340 is connected to the output node of the assist current generation circuit 330. The third clamp circuit 340 clamps the voltage of the output node of the assist current generation circuit 330 so that it does not exceed a predetermined clamp level. The clamp level is determined taking into consideration the drain-source breakdown voltage of the NMOS transistor that constitutes the assist current generation circuit 330.

[0041] The third current source CS3 is connected between the output node of the assist current generating circuit 330 and the ground line 304, and sinks a constant current Ic3. The constant current Ic3 is provided to prevent the node N2 from becoming high impedance when the output of the assist current generating circuit 330 is high impedance. The third current source CS3 is composed of a low-voltage transistor.

[0042] An input current Ib(Vm)+Ic3 flows through the input node of the current mirror circuit 350. The current mirror circuit 350 reflects the input current Ib(Vm)+Ic3 and outputs a source current Is. The current mirror circuit 350 is composed of low-voltage transistors.

[0043] The fourth clamp circuit 360 is connected between the output node of the current mirror circuit 350 and the output terminal OUT. The fourth clamp circuit 360 clamps the voltage of the output node of the current mirror circuit 350 so that it does not fall below a predetermined clamp level. The clamp level is determined taking into consideration the drain-source breakdown voltage of the PMOS transistor that constitutes the current mirror circuit 350.

[0044] The above is the configuration of the output stage 300. Next, the operation of the output stage 300 in both the light load state and the heavy load state will be described.

[0045] Light load condition 3 is a circuit diagram illustrating the operation of the output stage 300 in a light-load state. The first transistor M1 is supplied with a constant current Ic1 sourced by the first current source CS1. When the intermediate signal Vm is relatively high, the assist current Ib generated by the assist current generation circuit 330 is zero, and the constant current Ic3 sunk by the third current source CS3 is reflected by the current mirror circuit 350 and supplied to the first transistor M1. In other words, in a light-load state, a constant current Ic1 + Ic3 × α is supplied to the first transistor M1 as the bias current Ibias, and the first transistor M1 operates as a class A output stage. α is the mirror ratio of the current mirror circuit 350.

[0046] Heavy load conditions 4 is a circuit diagram illustrating the operation of the output stage 300 under heavy load conditions. When the intermediate signal Vm decreases, the current Ia flowing through the first transistor M1 becomes zero. At this time, the assist current generation circuit 330 generates an assist current Ib(Vm) that increases as the intermediate signal Vm decreases. The current mirror circuit 350 mirrors the sum of the assist current Ib(Vm) and the constant current Ic3 to output the source current Is. Is = (Ib(Vm) + Ic3) × α This source current Is is the load current I OUT is supplied to the load.

[0047] This source current Is depends on the intermediate signal Vm, which means that under heavy load conditions the output stage 300 behaves like a class AB amplifier.

[0048] This is the operation of the output stage 300. The output stage 300 is driven by a high power supply voltage V DD Moreover, under heavy load conditions, it is possible to supply a source current that depends on the intermediate signal Vm.

[0049] Next, a specific example of the configuration of the output stage 300 will be described.

[0050] 5 is a circuit diagram of an output stage 300A according to one embodiment. A reference current source 306 outputs a reference current I REF The transistor M11 is a low-voltage NMOS transistor, and has its gate and drain connected to the reference current source 306 and its source connected to the ground line 304.

[0051] The transistor M12 is a low-voltage NMOS transistor and forms a current mirror circuit together with the transistor M11. The transistor M12 has a reference current I REF A current proportional to the voltage at the drain of the transistor M12 flows through the seventh clamp circuit 390.

[0052] The transistor M13 is a low-voltage PMOS transistor, and the gate and drain of the transistor M13 are connected to the transistor M12 via the seventh clamp circuit 390.

[0053] The first current source CS1 includes a transistor M4. The transistor M4 is a low-voltage PMOS transistor and is connected to a transistor M13 to form a current mirror circuit. The transistor M4 supplies a reference current I REF A constant current Ic1 proportional to

[0054] The second current source CS2 includes a transistor M5. The transistor M5 is a low-voltage NMOS transistor and is connected to the transistor M11 to form a current mirror circuit. The transistor M5 has a reference current I REF A constant current Ic2 proportional to

[0055] The third current source CS3 includes a transistor M6. The transistor M6 is a low-voltage NMOS transistor and is connected to the transistor M11 to form a current mirror circuit. The transistor M6 has a reference current I REF A constant current Ic3 proportional to

[0056] The assist current generation circuit 330 includes a second transistor M2 and a third transistor M3, which are low-voltage NMOS transistors, a fifth clamp circuit 370, a sixth clamp circuit 380, and a fourth current source CS4. The second transistor M2 receives an intermediate signal Vm at its gate and has a source connected to the ground line 304. The third transistor M3 has a gate connected to the drain of the second transistor M2 and a source connected to the ground line 304.

[0057] The fifth clamp circuit 370 clamps the drain of the second transistor M2 so that it does not exceed a predetermined clamp level.

[0058] The fourth current source CS4 sources a constant current Ic4. For example, the fourth current source CS4 includes a transistor M9. The transistor M9 is a low-voltage PMOS transistor and forms a current mirror circuit with the transistor M13. The transistor M9 supplies a reference current I REF A constant current Ic4 proportional to the

[0059] The sixth clamp circuit 380 is connected to the fourth current source CS4, and clamps the voltage at the connection node with the fourth current source CS4 so that it does not fall below a predetermined clamp level.

[0060] The first clamp circuit 310, the third clamp circuit 340, the fifth clamp circuit 370, and the seventh clamp circuit 390 can each be configured with a high-voltage NMOS transistor. A predetermined bias voltage Vbn is supplied to the gate of each NMOS transistor. The voltage level of the source of the high-voltage NMOS transistor is clamped so as not to exceed Vbn-Vthn, where Vthn is the gate threshold voltage of the NMOS transistor.

[0061] The second clamp circuit 320, the fourth clamp circuit 360, and the sixth clamp circuit 380 can be configured with high-voltage PMOS transistors. A predetermined bias voltage Vbp is supplied to the gate of each PMOS transistor. The voltage level of the source of the high-voltage PMOS transistor is clamped so as not to fall below Vbp+Vthp, where Vthp is the gate threshold voltage of the NMOS transistor.

[0062] The above is the configuration of the output stage 300A.

[0063] Fig. 6 is a circuit diagram of an output stage 300B according to a modified example. In the output stage 300 of Fig. 2, the first transistor M1 is an NMOS transistor, but in the output stage 300B of Fig. 6, the first transistor M1 is a PMOS transistor.

[0064] The configuration of the output stage 300B is the same as that of the output stage 300 in Figure 2, and includes a power supply line 302, a ground line 304, a first transistor M1, a first clamp circuit 310, a second clamp circuit 320, an assist current generating circuit 330, a third clamp circuit 340, a current mirror circuit 350, and a fourth clamp circuit 360, and has an inverted configuration, i.e., the power supply line and the ground line.

[0065] The first transistor M1 is a low-voltage PMOS transistor, and has a source connected to the power supply line 302 and a gate connected to the input node IN of the output stage 300. The gate of the first transistor M1 receives an intermediate signal Vm generated by the preceding input stage 200. A current Ia(Vm) that depends on the gate voltage Vm flows through the first transistor M1.

[0066] The first clamp circuit 310 is connected between the output terminal OUT and the drain of the first transistor M1. The first clamp circuit 310 clamps the drain voltage of the first transistor M1 so that it does not fall below a predetermined clamp level. The clamp level is determined taking into account the withstand voltage between the drain and source of the first transistor M1.

[0067] The first current source CS1 is connected to the ground line 304 and sinks the constant current Ic1. The first current source CS1 is configured with a low-voltage transistor.

[0068] The second clamp circuit 320 is connected between the first current source CS1 and the output terminal OUT, and clamps the voltage at the connection node with the first current source CS1 so that it does not exceed a predetermined clamp level. The clamp level is determined taking into consideration the withstand voltage between the drain and source of the NMOS transistor that constitutes the first current source CS1.

[0069] The second current source CS2 is connected between the drain of the first transistor M1 and the power supply line 302, and sources a constant current Ic2. The constant current Ic2 is provided to prevent the node N1 at the drain of the first transistor M1 from becoming high impedance when the first transistor M1 is off. The second current source CS2 is composed of a low-voltage transistor.

[0070] The assist current generating circuit 330 is connected to the input node IN and receives the intermediate signal Vm. The assist current generating circuit 330 sources an assist current Ib(Vm) corresponding to the intermediate signal Vm. The amount of the assist current Ib(Vm) has a positive correlation with the intermediate signal Vm, and the higher the intermediate signal Vm, the greater the assist current Ib(Vm).

[0071] The third clamp circuit 340 is connected to the output node of the assist current generation circuit 330. The third clamp circuit 340 clamps the voltage of the output node of the assist current generation circuit 330 so that it does not fall below a predetermined clamp level. The clamp level is determined taking into consideration the drain-source breakdown voltage of the PMOS transistor that constitutes the assist current generation circuit 330.

[0072] The third current source CS3 is connected between the output node of the assist current generating circuit 330 and the power supply line 302, and sources a constant current Ic3. The constant current Ic3 is provided to prevent the node N2 from becoming high impedance when the output of the assist current generating circuit 330 is high impedance. The third current source CS3 is composed of a low-voltage transistor.

[0073] An input current Ib(Vm)+Ic3 flows through the input node of the current mirror circuit 350. The current mirror circuit 350 reflects the input current Ib(Vm)+Ic3 and outputs a sink current Is. The current mirror circuit 350 is composed of low-voltage transistors.

[0074] The fourth clamp circuit 360 is connected between the output node of the current mirror circuit 350 and the output terminal OUT. The fourth clamp circuit 360 clamps the voltage of the output node of the current mirror circuit 350 so that it does not exceed a predetermined clamp level. The clamp level is determined taking into consideration the drain-source breakdown voltage of the NMOS transistor that constitutes the current mirror circuit 350.

[0075] The above is the configuration of the output stage 300B. Next, a specific configuration example of the output stage 300B will be described.

[0076] 7 is a circuit diagram of an output stage 300C according to one embodiment. A reference current source 306 outputs a reference current I REF The transistor M11 is a low-voltage PMOS transistor, and has a gate and a drain connected to the reference current source 306 and a source connected to the power supply line 302.

[0077] The transistor M12 is a low-voltage PMOS transistor and forms a current mirror circuit together with the transistor M11. REF A current proportional to the voltage at the drain of the transistor M12 flows through the seventh clamp circuit 390.

[0078] The transistor M13 is a low-voltage NMOS transistor, and its gate and drain are connected to the transistor M12 via the seventh clamp circuit 390.

[0079] The first current source CS1 includes a transistor M4. The transistor M4 is a low-voltage NMOS transistor and is connected to a transistor M13 to form a current mirror circuit. The transistor M4 supplies a reference current I REF A constant current Ic1 proportional to

[0080] The second current source CS2 includes a transistor M5. The transistor M5 is a low-voltage PMOS transistor and is connected to the transistor M11 to form a current mirror circuit. The transistor M5 supplies a reference current I REF A constant current Ic2 proportional to

[0081] The third current source CS3 includes a transistor M6. The transistor M6 is a low-voltage PMOS transistor and is connected to the transistor M11 to form a current mirror circuit. The transistor M6 has a reference current I REF A constant current Ic3 proportional to

[0082] The assist current generation circuit 330 includes a second transistor M2 and a third transistor M3, which are low-voltage PMOS transistors, a fifth clamp circuit 370, a sixth clamp circuit 380, and a fourth current source CS4. The second transistor M2 receives an intermediate signal Vm at its gate and has a source connected to the power supply line 302. The third transistor M3 has a gate connected to the drain of the second transistor M2 and a source connected to the power supply line 302.

[0083] The fifth clamp circuit 370 clamps the drain of the second transistor M2 so that it does not fall below a predetermined clamp level.

[0084] The fourth current source CS4 generates a constant current Ic4. For example, the fourth current source CS4 includes a transistor M9. The transistor M9 is a low-voltage NMOS transistor and forms a current mirror circuit with the transistor M13. The transistor M9 supplies a reference current I REF A constant current Ic4 proportional to the

[0085] The sixth clamp circuit 380 is connected to the fourth current source CS4, and clamps the voltage at the connection node with the fourth current source CS4 so that it does not fall below a predetermined clamp level.

[0086] The first clamp circuit 310, the third clamp circuit 340, the fifth clamp circuit 370, and the seventh clamp circuit 390 can each be configured with a high-voltage PMOS transistor. A predetermined bias voltage Vbp is supplied to the gate of each PMOS transistor. The voltage level of the source of the high-voltage PMOS transistor is clamped so as not to exceed Vbp+Vthp, where Vthp is the gate threshold voltage of the PMOS transistor.

[0087] The second clamp circuit 320, the fourth clamp circuit 360, and the sixth clamp circuit 380 can be configured with high-voltage NMOS transistors. A predetermined bias voltage Vbn is supplied to the gate of each NMOS transistor. The voltage level of the source of the high-voltage PMOS transistor is clamped so as not to exceed Vbn-Vthn, where Vthn is the gate threshold voltage of the NMOS transistor.

[0088] The embodiments merely illustrate the principles and applications of the present invention, and many modifications and changes in arrangement are permitted to the embodiments as long as they do not deviate from the spirit of the present invention as defined in the claims.

[0089] (Addendum) The present specification discloses the following techniques.

[0090] (Item 1) 1. An operational amplifier having an input stage and an output stage, The output stage comprises: an input terminal for receiving an intermediate signal from the input stage; An output terminal; The power line and A ground line and a first current source connected to the power supply line; a first N-channel transistor having a gate connected to the input terminal and a source connected to the ground line; a second current source connected between a first node, which is the drain of the first transistor, and the ground line; a first clamp circuit connected between the first node and the output terminal, for clamping the voltage of the first node; a second clamp circuit connected between the first current source and the output terminal, for clamping a voltage at a connection node with the first current source; an assist current generating circuit that generates an assist current that increases as the intermediate signal decreases; a third current source connected between a second node, which is an output node of the assist current generating circuit, and the ground line; a third clamp circuit that clamps the voltage of the second node; a current mirror circuit that mirrors the current flowing through the second node; a fourth clamp circuit connected between the output node of the current mirror circuit and the output terminal, for clamping the voltage of the output node of the current mirror circuit; An operational amplifier comprising:

[0091] (Item 2) The assist current generating circuit includes: a second N-channel transistor having a gate connected to the input terminal and a source connected to the ground line; a fifth clamp circuit that clamps the voltage of the drain of the second transistor; a fourth current source connected to the power supply line; a sixth clamp circuit that clamps the voltage of the output node of the fourth current source; a third N-channel transistor having a gate connected to the drain of the second transistor and a source connected to the power supply line; 2. The operational amplifier according to item 1, wherein the current flowing through the third transistor is the assist current.

[0092] (Item 3) 3. The operational amplifier according to item 1 or 2, wherein the first clamp circuit and the third clamp circuit each include a high-voltage NMOS transistor having a bias voltage applied to its gate.

[0093] (Item 4) 4. The operational amplifier according to any one of items 1 to 3, wherein the second clamp circuit and the fourth clamp circuit each include a high-voltage PMOS transistor having a bias voltage applied to its gate.

[0094] (Item 5) the fifth clamp circuit includes a high-voltage NMOS transistor having a bias voltage applied to its gate; 3. The operational amplifier according to item 2, wherein the sixth clamp circuit includes a high-voltage PMOS transistor having a bias voltage applied to its gate.

[0095] (Item 6) 1. An operational amplifier having an input stage and an output stage, The output stage comprises: an input terminal for receiving an intermediate signal from the input stage; An output terminal; The power line and A ground line and a first current source connected to the ground line; a first P-channel transistor having a gate connected to the input terminal and a source connected to the power supply line; a second current source connected between a first node, which is the drain of the first transistor, and the power supply line; a first clamp circuit connected between the first node and the output terminal, for clamping the voltage of the first node; a second clamp circuit connected between the first current source and the output terminal, for clamping a voltage at a connection node with the first current source; an assist current generating circuit that generates an assist current that increases as the intermediate signal increases; a third current source connected between a second node, which is an output node of the assist current generating circuit, and the ground line; a third clamp circuit that clamps the voltage of the second node; a current mirror circuit that mirrors the current flowing through the second node; a fourth clamp circuit connected between the output node of the current mirror circuit and the output terminal, for clamping the voltage of the output node of the current mirror circuit; An operational amplifier comprising:

[0096] (Item 7) The assist current generating circuit includes: a second P-channel transistor having a gate connected to the input terminal and a source connected to the power supply line; a fifth clamp circuit that clamps the voltage of the drain of the second transistor; a fourth current source connected to the ground line; a sixth clamp circuit that clamps the voltage of the output node of the fourth current source; a third P-channel transistor having a gate connected to the drain of the second transistor and a source connected to the power supply line; 7. The operational amplifier according to claim 6, wherein the current flowing through the third transistor is the assist current.

[0097] (Item 8) 8. The operational amplifier according to item 6 or 7, wherein the first clamp circuit and the third clamp circuit each include a high-voltage NMOS transistor having a bias voltage applied to its gate.

[0098] (Item 9) 9. The operational amplifier according to any one of items 6 to 8, wherein the second clamp circuit and the fourth clamp circuit each include a high-voltage PMOS transistor having a bias voltage applied to its gate.

[0099] (Item 10) the fifth clamp circuit includes a high-voltage NMOS transistor having a bias voltage applied to its gate; 8. The operational amplifier according to item 7, wherein the sixth clamp circuit includes a high-voltage PMOS transistor having a bias voltage applied to its gate.

[0100] (Item 11) 11. The operational amplifier according to any one of items 1 to 10, which is monolithically integrated on a single semiconductor substrate. [Explanation of symbols]

[0101] 100 Op-Amps 200 input stages 300 output stage 302 Power Line 304 Ground Line 306 Reference current source M1 First transistor M2 Second transistor M3 Third transistor CS1 1st current source CS2 2nd current source CS3 3rd current source CS4 4th current source 310 First clamp circuit 320 Second clamp circuit 330 Assist current generation circuit 340 Third clamp circuit 350 Current mirror circuit 360 4th clamp circuit 370 5th clamp circuit 380 6th clamp circuit 390 7th clamp circuit

Claims

1. 1. An operational amplifier having an input stage and an output stage, The output stage comprises: an input terminal for receiving an intermediate signal from the input stage; An output terminal; The power line and A ground line and a first current source connected to the power supply line; a first N-channel transistor having a gate connected to the input terminal and a source connected to the ground line; a second current source connected between a first node, which is the drain of the first transistor, and the ground line; a first clamp circuit connected between the first node and the output terminal, for clamping the voltage of the first node; a second clamp circuit connected between the first current source and the output terminal, for clamping a voltage at a connection node between the first current source and the output terminal; an assist current generating circuit that generates an assist current that increases as the intermediate signal decreases; a third current source connected between a second node, which is an output node of the assist current generating circuit, and the ground line; a third clamp circuit that clamps the voltage of the second node; a current mirror circuit that mirrors the current flowing through the second node; a fourth clamp circuit connected between the output node of the current mirror circuit and the output terminal, for clamping the voltage of the output node of the current mirror circuit; An operational amplifier comprising:

2. The assist current generating circuit includes: a second N-channel transistor having a gate connected to the input terminal and a source connected to the ground line; a fifth clamp circuit that clamps the voltage of the drain of the second transistor; a fourth current source connected to the power supply line; a sixth clamp circuit that clamps the voltage of the output node of the fourth current source; a third N-channel transistor having a gate connected to the drain of the second transistor and a source connected to the power supply line; 2. The operational amplifier according to claim 1, wherein the current flowing through the third transistor is the assist current.

3. 3. The operational amplifier according to claim 1, wherein the first clamp circuit and the third clamp circuit each include a high-voltage NMOS transistor having a bias voltage applied to its gate.

4. 3. The operational amplifier according to claim 1, wherein the second clamp circuit and the fourth clamp circuit each include a high-voltage PMOS transistor having a bias voltage applied to its gate.

5. the fifth clamp circuit includes a high-voltage NMOS transistor having a bias voltage applied to its gate; 3. The operational amplifier according to claim 2, wherein said sixth clamp circuit includes a high-voltage PMOS transistor having a bias voltage applied to its gate.

6. 1. An operational amplifier having an input stage and an output stage, The output stage comprises: an input terminal for receiving an intermediate signal from the input stage; An output terminal; The power line and A ground line and a first current source connected to the ground line; a first P-channel transistor having a gate connected to the input terminal and a source connected to the power supply line; a second current source connected between a first node, which is the drain of the first transistor, and the power supply line; a first clamp circuit connected between the first node and the output terminal, for clamping the voltage of the first node; a second clamp circuit connected between the first current source and the output terminal, for clamping a voltage at a connection node between the first current source and the output terminal; an assist current generating circuit that generates an assist current that increases as the intermediate signal increases; a third current source connected between a second node, which is an output node of the assist current generating circuit, and the ground line; a third clamp circuit that clamps the voltage of the second node; a current mirror circuit that mirrors the current flowing through the second node; a fourth clamp circuit connected between the output node of the current mirror circuit and the output terminal, for clamping the voltage of the output node of the current mirror circuit; An operational amplifier comprising:

7. The assist current generating circuit includes: a second P-channel transistor having a gate connected to the input terminal and a source connected to the power supply line; a fifth clamp circuit that clamps the voltage of the drain of the second transistor; a fourth current source connected to the ground line; a sixth clamp circuit that clamps the voltage of the output node of the fourth current source; a third P-channel transistor having a gate connected to the drain of the second transistor and a source connected to the power supply line; 7. The operational amplifier according to claim 6, wherein the current flowing through the third transistor is the assist current.

8. 8. The operational amplifier according to claim 6, wherein the first clamp circuit and the third clamp circuit each include a high-voltage NMOS transistor having a bias voltage applied to its gate.

9. 8. The operational amplifier according to claim 6, wherein the second clamp circuit and the fourth clamp circuit each include a high-voltage PMOS transistor having a bias voltage applied to its gate.

10. the fifth clamp circuit includes a high-voltage NMOS transistor having a bias voltage applied to its gate; 8. The operational amplifier according to claim 7, wherein the sixth clamp circuit includes a high-voltage PMOS transistor having a bias voltage applied to its gate.

11. 8. The operational amplifier according to claim 1, 2, 6, or 7, which is monolithically integrated on a single semiconductor substrate.

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