Vertical hall element

Abstract

To provide a vertical Hall element capable of removing an offset voltage with high precision.SOLUTION: A vertical Hall element 100 has: an N type epitaxial layer 30 formed on a surface of a P type semiconductor substrate; a first electrode group 110 arranged on a surface of the N type epitaxial layer 30 and formed of three or more electrodes 111 to 115; and a P type high-resistance diffusion layer 70 arranged in a ring shape at an outer periphery apart from the first electrode group 110, and comprising a second electrode group 120 capable of applying voltages so that an electric field is constant with the first electrode group 110.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a vertical Hall element. [Background technology]

[0002] Hall elements can be easily formed on the surface of a semiconductor substrate and are used in a variety of applications because they are capable of detecting position and angle as magnetic sensors without contact. Among Hall elements, horizontal Hall elements that detect magnetic field components perpendicular to the surface of a semiconductor substrate are generally well known, but various vertical Hall elements that detect magnetic field components parallel to the surface of a semiconductor substrate have also been proposed.

[0003] For example, a Hall element has been proposed in which fuses are provided in multiple contact areas that pass drive current through the magnetic detection unit, and in the event that an imbalance occurs in the potential distribution inside the element due to stress or the like, causing an offset voltage, the potential distribution inside the element can be adjusted (see Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-128399 Summary of the Invention [Problem to be solved by the invention]

[0005] An object of one aspect of the present invention is to provide a vertical Hall element that can remove an offset voltage with high precision. [Means for solving the problem]

[0006] The vertical Hall element according to one embodiment of the present invention comprises: A vertical Hall element formed on a surface of a semiconductor substrate of a first conductivity type, a second conductivity type impurity diffusion layer formed on the surface of the semiconductor substrate; a first electrode group arranged on a surface of the impurity diffusion layer and formed of three or more electrodes; a first conductivity type high resistance diffusion layer including a second electrode group arranged in a ring shape on the outer periphery at a distance from the first electrode group, to which a voltage can be applied so that an electric field between the second electrode group and the first electrode group is constant; It has. [Effects of the Invention]

[0007] According to one aspect of the present invention, it is possible to provide a vertical Hall element that can remove an offset voltage with high precision. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a schematic plan view showing a vertical Hall element according to an embodiment of the present invention. [Figure 2A] FIG. 2A is a schematic cross-sectional view taken along line II-II in FIG. [Figure 2B] FIG. 2B is an explanatory diagram showing the resistance between the electrodes in the first electrode group and the second electrode group of this embodiment. [Figure 3A] FIG. 3A is a schematic plan view showing a depletion layer and a current path generated in phase 1 of the spinning current method in the vertical Hall element of this embodiment. [Figure 3B] FIG. 3B is a circuit diagram showing connections between voltage sources and electrodes in phase 1 of the spinning current method in the vertical Hall element of this embodiment. [Figure 4] FIG. 4 is a schematic cross-sectional view showing a depletion layer and a current path generated in phase 1 of the spinning current method in the vertical Hall element of this embodiment. [Figure 5A] FIG. 5A is a schematic plan view showing a depletion layer and a current path generated in phase 2 of the spinning current method in the vertical Hall element of this embodiment. [Figure 5B]FIG. 5B is a circuit diagram showing connections between voltage sources and electrodes in phase 2 of the spinning current method in the vertical Hall element of this embodiment. [Figure 6] FIG. 6 is a schematic cross-sectional view showing a depletion layer and a current path generated in phase 2 of the spinning current method in the vertical Hall element of this embodiment. [Figure 7A] FIG. 7A is a schematic plan view showing a depletion layer and a current path generated in phase 3 of the spinning current method in the vertical Hall element of this embodiment. [Figure 7B] FIG. 7B is a circuit diagram showing connections between voltage sources and electrodes in Phase 3 of the spinning current method in the vertical Hall element of this embodiment. [Figure 8] FIG. 8 is a schematic cross-sectional view showing a depletion layer and a current path generated in phase 3 of the spinning current method in the vertical Hall element of this embodiment. [Figure 9A] FIG. 9A is a schematic plan view showing a depletion layer and a current path generated in phase 4 of the spinning current method in the vertical Hall element of this embodiment. [Figure 9B] FIG. 9B is a circuit diagram showing connections between voltage sources and electrodes in phase 4 of the spinning current method in the vertical Hall element of this embodiment. [Figure 10] FIG. 10 is a schematic cross-sectional view showing a depletion layer and a current path generated in phase 4 of the spinning current method in the vertical Hall element of this embodiment. [Figure 11] FIG. 11 is a schematic plan view showing a conventional vertical Hall element. [Figure 12A] FIG. 12A is a schematic cross-sectional view taken along line XII-XII in FIG. [Figure 12B] FIG. 12B is an explanatory diagram showing the resistance between the electrodes in the conventional first electrode group. [Figure 13A] FIG. 13A is a schematic plan view showing a depletion layer and a current path generated in phase 1 of the spinning current method in a conventional vertical Hall element. [Figure 13B]FIG. 13B is a circuit diagram showing connections between a voltage source and electrodes in phase 1 of the spinning current method in a conventional vertical Hall element. [Figure 14] FIG. 14 is a schematic cross-sectional view showing a depletion layer and a current path generated in phase 1 of the spinning current method in a conventional vertical Hall element. [Figure 15A] FIG. 15A is a schematic plan view showing a depletion layer and a current path generated in phase 2 of the spinning current method in a conventional vertical Hall element. [Figure 15B] FIG. 15B is a circuit diagram showing connections between a voltage source and electrodes in phase 2 of the spinning current method in a conventional vertical Hall element. [Figure 16] FIG. 16 is a schematic cross-sectional view showing a depletion layer and a current path generated in phase 2 of the spinning current method in a conventional vertical Hall element. [Figure 17A] FIG. 17A is a schematic plan view showing a depletion layer and a current path generated in phase 3 of the spinning current method in a conventional vertical Hall element. [Figure 17B] FIG. 17B is a circuit diagram showing connections between a voltage source and electrodes in Phase 3 of the spinning current method in a conventional vertical Hall element. [Figure 18] FIG. 18 is a schematic cross-sectional view showing a depletion layer and a current path generated in phase 3 of the spinning current method in a conventional vertical Hall element. [Figure 19A] FIG. 19A is a schematic plan view showing a depletion layer and a current path generated in phase 4 of the spinning current method in a conventional vertical Hall element. [Figure 19B] FIG. 19B is a circuit diagram showing connections between a voltage source and electrodes in phase 4 of the spinning current method in a conventional vertical Hall element. [Figure 20] FIG. 20 is a schematic cross-sectional view showing a depletion layer and a current path generated in phase 4 of the spinning current method in a conventional vertical Hall element. DETAILED DESCRIPTION OF THE INVENTION

[0009] The present invention is based on the finding that offset voltage is more likely to occur in vertical Hall elements than in horizontal Hall elements, and that it is difficult to remove the offset voltage with high precision even using the well-known spinning current method.

[0010] Specifically, while the vertical structure of the semiconductor substrate is important for vertical Hall elements, it is difficult to form a highly geometrically symmetrical structure in the semiconductor process, making them more susceptible to offset voltage than horizontal Hall elements.The spinning current method is known as a method for eliminating offset voltage, and it can eliminate offset voltage caused by structural asymmetry due to manufacturing variations by calculating a correction value from the output voltage when the current flow between each electrode is changed in four phases. However, if the current flow method is changed in each phase of the spinning current method, the distribution of the depletion layer width on the surface of the impurity diffusion layer, which serves as the current path, will differ, changing the resistance value between the electrodes and potentially reducing the accuracy of offset voltage removal.

[0011] Therefore, in the vertical Hall element of this embodiment, an electrode is separately provided to apply a voltage that makes the distribution of the depletion layer width constant in each phase, thereby enabling the offset voltage to be removed with high precision.

[0012] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, identical components are denoted by the same reference numerals, and redundant explanations may be omitted. In the drawings, the X, Y, and Z directions are perpendicular to one another. The direction including the X direction and the opposite direction of the X direction (-X direction) is referred to as the "X-axis direction," the direction including the Y direction and the opposite direction of the Y direction (-Y direction) is referred to as the "Y-axis direction," and the direction including the Z direction and the opposite direction of the Z direction (-Z direction, depth direction) is referred to as the "Z-axis direction" (height direction, thickness direction). In this regard, in the following embodiments, the surface of each film facing the Z direction may be referred to as the "surface." The drawings are schematic, and the ratios of width, length, depth, etc. are not as shown in the drawings. In the following description, the first conductivity type is defined as P type, and the second conductivity type is defined as N type.

[0013] Fig. 1 is a schematic plan view showing a vertical Hall element according to an example of an embodiment of the present invention. Fig. 2A is a schematic cross-sectional view taken along line II-II in Fig. 1. Fig. 2B is an explanatory diagram showing resistances between electrodes in a first electrode group and a second electrode group according to this embodiment. 1, the vertical Hall element 100 of this embodiment includes a first electrode group 110 and a P-type high-resistance diffusion layer 70 having a second electrode group 120 on its outer periphery. The vertical Hall element 100 further includes a P-type element isolation diffusion layer 80 arranged in a ring shape on the outer periphery of the P-type high-resistance diffusion layer 70. As shown in FIG. 2A, the vertical Hall element 100 is formed on the surface of a P-type semiconductor substrate 10, and includes N-type buried layers 20 and 50, an N-type epitaxial layer 30 as an impurity diffusion layer, and P-type buried layers 40 and 60.

[0014] The first electrode group 110 is an electrode group that enables the vertical Hall element 100 to function as a magnetic sensor, and is also used when performing correction to remove offset voltage by the spinning current method. The first electrode group 110 is formed of five electrodes 111 to 115.

[0015] The electrodes 111 to 115 are arranged in a straight line on the surface of the N-type epitaxial layer 30, and are each formed in an N-type impurity region with a higher concentration than the N-type epitaxial layer 30. The electrodes 111 to 115 all have the same structure, are rectangular in plan view, and are arranged at equal intervals along the short side. As a result, the electrodes 111 to 115 have a highly symmetric structure, and can reduce the offset voltage output even when no external magnetic field is applied.

[0016] Furthermore, the electrodes 111 to 115 are each connected to a voltage source by wiring (not shown), and a required voltage is applied to them. When the vertical Hall element 100 functions as a magnetic sensor, the electrodes 111, 113, and 115 serve as drive current supply electrodes, and the electrodes 112 and 114 serve as Hall voltage output electrodes. When performing correction to remove the offset voltage using the spinning current method, the drive current supply electrodes and the Hall voltage output electrodes may be interchanged to obtain the required output voltages Vout1 to Vout4.

[0017] The second electrode group 120 is formed on the surface of the P-type high-resistance diffusion layer 70, and a voltage is applied thereto so that the width of the depletion layer generated between the first electrode group 110 and the P-type high-resistance diffusion layer 70 becomes constant in each phase of the spinning current method. The second electrode group 120 is formed of eight electrodes 121, 122a, 122b, 123a, 123b, 124a, 124b, and 125.

[0018] The electrodes 121, 122a, 122b, 123a, 123b, 124a, 124b, and 125 are each formed in a P-type impurity region having a higher concentration than the P-type high-resistance diffusion layer 70. These eight electrodes are arranged at positions that make it easy to maintain a constant electric field between the P-type high-resistance diffusion layer 70 and the first electrode group 110. In this embodiment, the electrode 121 corresponds to the electrode 111, the electrodes 122a and 122b to the electrode 112, the electrodes 123a and 123b to the electrode 113, the electrodes 124a and 124b to the electrode 114, and the electrode 125 to the electrode 115. The electrodes 121 and 125 are arranged to cover one side of the electrodes 111 and 115. Electrodes 122a, 122b, 123a, 123b, 124a, and 124b are arranged on extensions of both ends of electrodes 112 to 114 in the long side direction, and are rectangular in shape with two opposing sides the width of electrodes 112 to 114 in plan view. These eight electrodes are each connected to a voltage source by wiring (not shown), and a voltage is applied to keep the potential difference between the electrodes constant.

[0019] The electrode 130 is formed on the surface of the P-type element isolation diffusion layer 80 as a P-type impurity region with a higher concentration than the P-type element isolation diffusion layer 80. The electrode 130 is grounded by a wiring (not shown), and the potential of the P-type element isolation diffusion layer 80 is set to 0V.

[0020] The P-type semiconductor substrate 10 is a silicon wafer doped with P-type impurities.

[0021] The N-type buried layer 20 is formed near the boundary between the P-type semiconductor substrate 10 and the N-type epitaxial layer 30 , and is disposed below the first electrode group 110 . In this embodiment, the focus is on the depletion layer generated in the current path that flows in the region near the surface of the N-type epitaxial layer 30, but there is also a current path that flows downward through the N-type epitaxial layer 30, passes through the N-type buried layer 20, and then flows upward through the N-type epitaxial layer 30. In other words, the current that flows in the in-plane direction of the P-type semiconductor substrate 10 flows throughout the N-type buried layer 20 and the N-type epitaxial layer 30. Therefore, when operating as a magnetic sensor, the N-type buried layer 20 and the N-type epitaxial layer 30 become the current path for the drive current and function as a magnetic sensing portion.

[0022] The N-type epitaxial layer 30 is provided on the P-type semiconductor substrate 10, and N-type impurities are implanted and diffused therein. Although the impurity concentration of the N-type epitaxial layer 30 is constant in this embodiment, it may be configured so that the impurity concentration increases with depth. This allows the current path to be widened in a balanced manner by providing an impurity concentration gradient such that the resistance value of the deepest current path is approximately the same as the resistance value of the current path passing through the shallower portion, thereby increasing the magnetic sensitivity of the vertical Hall element 100.

[0023] The P-type buried layer 40 is formed near the boundary between the P-type semiconductor substrate 10 and the N-type epitaxial layer 30. The P-type buried layer 40 is disposed at a position separated from the N-type buried layer 20 so as to contact the bottom surface of the P-type high-resistance diffusion layer 70.

[0024] Similar to the N-type buried layer 20, the N-type buried layer 50 is formed near the boundary between the P-type semiconductor substrate 10 and the N-type epitaxial layer 30. The N-type buried layer 50 is disposed so as to contact the P-type buried layer 40 at its side and also contact the bottom surface of the P-type high-resistance diffusion layer 70.

[0025] Similar to the P-type buried layer 40, the P-type buried layer 60 is formed near the boundary between the P-type semiconductor substrate 10 and the N-type epitaxial layer 30. The P-type buried layer 40 is disposed so as to contact the side surface of the N-type buried layer 50 and also to contact the bottom surface of the P-type element isolation diffusion layer 80.

[0026] The P-type high-resistance diffusion layer 70 is arranged in a rectangular ring shape on the outer periphery, spaced apart from the first electrode group 110. Because the P-type high-resistance diffusion layer 70 has high resistance, it can reduce the current when a voltage is applied to each electrode of the second electrode group 120. Because the P-type high-resistance diffusion layer 70 has a ring shape, it can prevent the current from the first electrode group 110 from diffusing, thereby improving the magnetic sensitivity and the accuracy of removing the offset voltage. The inner periphery of the P-type high-resistance diffusion layer 70 is preferably located a certain distance from the outer periphery of the first electrode group 110. This makes it easier to keep the electric field between the P-type high-resistance diffusion layer 70 and the first electrode group 110 constant. The outer periphery of the first electrode group 110 refers to the smallest surrounding line that can surround all of the five electrodes 111-115.

[0027] The P-type element isolation diffusion layer 80 is arranged in a ring shape on the periphery at a distance from the P-type high-resistance diffusion layer 70. The P-type element isolation diffusion layer 80 is formed deep so as to be in contact with the P-type buried layer 60. This electrically isolates the vertical Hall element 100 from other regions (not shown) on the P-type semiconductor substrate 10 around it. In a region on the P-type semiconductor substrate 10 electrically isolated from the vertical Hall element 100, elements such as transistors forming at least one of a circuit for processing an output signal from the vertical Hall element 100 and a circuit for supplying a signal to the vertical Hall element 100 are provided.

[0028] The insulating film IF is a silicon oxide film formed by a LOCOS (Local Oxidation of Silicon) method on the surface of the N-type epitaxial layer 30. The insulating film IF is provided around the first electrode group 110 and the second electrode group 120. The insulating film IF is preferably one having no conductivity type, since a depletion layer would be generated near the surface if it had a conductivity type such as a P-type electrode isolation diffusion layer.

[0029] 2B, resistors R11 to R14 represent electrical resistance in the current paths between the electrodes 111 to 115 in the first electrode group 110. The resistors R11 to R14 have approximately the same resistance value because the electrodes 111 to 115 are arranged at equal intervals.

[0030] This shows the electrical resistance in the current path between adjacent electrodes of second electrode group 120. These resistors R21a to R24b have approximately the same resistance value because the intervals between adjacent electrodes of second electrode group 120 are the same.

[0031] In this way, since the resistance values between the electrodes of each electrode group are approximately equal, the voltage applied from the voltage source can be easily divided into half.

[0032] Next, a method for manufacturing the vertical Hall element of this embodiment will be described. First, P-type or N-type impurities are selectively implanted into regions of the P-type semiconductor substrate 10 where each buried layer is to be formed, and then an N-type epitaxial layer 30 containing N-type impurities is formed thereon. The P-type impurities are selectively implanted and diffused into the surface of the N-type epitaxial layer 30 to form a P-type high-resistance diffusion layer 70 and a P-type element isolation diffusion layer 80. Then, using the insulating film IF formed on the surface of the N-type epitaxial layer 30 by the LOCOS method as a mask, N-type impurities are implanted to a high concentration from the surface of the N-type epitaxial layer 30 to form a first electrode group 110. Furthermore, using the insulating film IF as a mask, P-type impurities are implanted to a high concentration from the surfaces of the P-type high-resistance diffusion layer 70 and the P-type element isolation diffusion layer 80 to form a second electrode group 120 and an electrode 130. In this manner, the vertical Hall element 100 can be formed.

[0033] Next, the principle of detecting the −Y direction component of an external magnetic field in the vertical Hall element 100 will be described with reference to FIGS. 3A, 3B, and 4. FIG. To detect magnetism, the vertical Hall element 100 passes a driving current in the +X direction and the -X direction from the center electrode 113 to the end electrodes 111 and 115. When an external magnetic field is applied in the -Y direction with respect to this driving current, a Lorentz force is generated in the +Z direction for charged particles of the driving current in the +X direction, and in the -Z direction for charged particles of the driving current in the -X direction, generating a Hall voltage with a potential difference of opposite positive and negative. The vertical Hall element 100 outputs a voltage between the electrodes 112 and 114 so as to add the absolute values of these potential differences, thereby enabling it to sensitively detect an external magnetic field applied from the -Y direction. The electrodes 114 and 115 are arranged to remove an offset voltage, and if the only purpose is to simply detect an external magnetic field, the three electrodes 111 to 113 are sufficient.

[0034] Next, a method for removing the offset voltage of the vertical Hall element 100 by the spinning current method will be described with reference to FIGS. 3A to 10. FIG. 3B, 5B, 7B, and 9B respectively show voltage sources that generate voltages Vh and Vc, and connections to the electrodes of first electrode group 110 and second electrode group 120. Changing the connections in each phase can be achieved by switching using a switching element or the like. 4, 6, 8 and 10, a depletion layer is formed on the inner periphery side of the P-type high-resistance diffusion layer 70, but this depletion layer is not shown.

[0035] <Phase 1> 3A, 3B, and 4, electrodes 111, 113, and 115 are used as current supply electrodes, and a current flows from electrode 113 to electrodes 111 and 115. To this end, a voltage of Vh+Vc is applied to electrode 113, a voltage of Vc is applied to electrodes 111 and 115, and a voltage of (1 / 2)×Vh+Vc is applied to electrodes 112 and 114. Then, the current path becomes as shown by the dotted lines (thin lines) in the figures, and electrodes 112 and 114 are used as voltage output electrodes, and the voltage between electrodes 112 and 114 is obtained as output voltage Vout1.

[0036] At this time, a voltage that is lower by Vc than the voltage applied to the corresponding first electrode group 110 is applied to each second electrode group 120, so that the electric field generated in the N-type epitaxial layer 30 between the first electrode group 110 and the P-type high-resistance diffusion layer 70 becomes constant. Specifically, a voltage of Vh is applied to electrodes 123a and 123b corresponding to electrode 113 to which a voltage of Vh+Vc is applied. Electrodes 121 and 125 are set to 0 V, while electrodes 111 and 115 are applied with a voltage of Vc. A voltage of (½)×Vh is applied to electrodes 122a, 122b, 124a, and 124b corresponding to electrodes 112 and 114 to which a voltage of (½)×Vh+Vc is applied. This makes it possible to make constant the electric field generated in the N-type epitaxial layer 30 between the first electrode group 110 and the P-type high-resistance diffusion layer 70, and to make constant the width of the depletion layer DL indicated by the dotted line (thick line) in the figure. Note that Vc is a voltage higher than Vh.

[0037] <Phase 2> In phase 2, as shown in Figures 5A, 5B, and 6, the direction of current flow is reversed from that in Figures 3A and 4, and current flows from electrodes 111 and 115 to electrode 113. To achieve this, a voltage of Vh+Vc is applied to electrodes 111 and 115, a voltage of Vc is applied to electrode 113, and a voltage of (1 / 2) x Vh+Vc is applied to electrodes 112 and 114. This results in a current path as shown by the dotted lines (thin lines) in the figures, and as in phase 1, electrodes 112 and 114 are used as voltage output electrodes, and the voltage between electrodes 112 and 114 is obtained as output voltage Vout2.

[0038] At this time, in order to make the width of the depletion layer DL the same as in phase 1, a voltage that is lower by Vc than the voltage applied to the corresponding first electrode group 110 is applied to each of the second electrode groups 120. Specifically, a voltage of Vh is applied to electrodes 121 and 125, while a voltage of Vh+Vc is applied to electrodes 111 and 115. Electrodes 123a and 123b corresponding to electrode 113 to which a voltage of Vc is applied are set to 0 V. A voltage of (1 / 2)×Vh is applied to electrodes 122a, 122b, 124a, and 124b corresponding to electrodes 112 and 114 to which a voltage of (1 / 2)×Vh+Vc is applied.

[0039] <Phase 3> 7A, 7B, and 8, the current supply electrodes and voltage output electrodes are swapped from those in FIGS. 3A to 6, and a current flows from electrode 112 to electrodes 111 and 114, respectively, and a current flows from electrode 115 to electrode 114. To this end, a voltage of Vh+Vc is applied to electrode 112, a voltage of Vc is applied to electrode 114, and a voltage of (1 / 2)×Vh+Vc is applied to electrodes 111, 113, and 115. Then, the current path becomes as shown by the dotted lines (thin lines) in the figures, and electrodes 111, 113, and 115 are used as voltage output electrodes, and the voltage between electrode 113 and electrode 111 or electrode 115 is obtained as output voltage Vout3.

[0040] At this time, in order to make the width of the depletion layer DL the same as in phases 1 and 2, a voltage that is lower by Vc than the voltage applied to the corresponding first electrode group 110 is applied to each of the second electrode groups 120. Specifically, a voltage of Vh is applied to electrodes 122a and 122b, while a voltage of Vh+Vc is applied to electrode 112. Electrodes 124a and 124b corresponding to electrode 114 to which a voltage of Vc is applied are set to 0V. A voltage of (1 / 2)×Vh is applied to electrodes 121, 123a, 123b, and 125 corresponding to electrodes 111, 113, and 115 to which a voltage of (1 / 2)×Vh+Vc is applied.

[0041] <Phase 4> 9A, 9B, and 10, the direction of current flow is reversed from that in FIGS. 7A and 8, and current flows from electrode 114 to electrodes 112 and 115, respectively, and from electrode 111 to electrode 112. To achieve this, a voltage of Vh+Vc is applied to electrode 114, a voltage of Vc is applied to electrode 112, and a voltage of (1 / 2)×Vh+Vc is applied to electrodes 111, 113, and 115. This results in a current path as shown by the dotted lines (thin lines) in the figures, and as in phase 3, electrodes 111, 113, and 115 are used as voltage output electrodes, and the voltage between electrode 113 and electrodes 111 and 115 is obtained as output voltage Vout4.

[0042] At this time, in order to make the width of the depletion layer DL the same as in phases 1 to 3, a voltage that is lower by Vc than the voltage applied to the corresponding first electrode group 110 is applied to each of the second electrode groups 120. Specifically, Vh is applied to electrodes 124a and 124b, while a voltage of Vh+Vc is applied to electrode 114. Electrodes 122a and 122b corresponding to electrode 112 to which a voltage of Vc is applied are set to 0V. A voltage of (1 / 2)×Vh is applied to electrodes 121, 123a, 123b, and 125 corresponding to electrodes 111, 113, and 115 to which a voltage of (1 / 2)×Vh+Vc is applied.

[0043] In this way, even if the way of flowing the current is changed in each phase of the spinning current method, the width of the depletion layer DL on the surface of the N-type epitaxial layer 30, which serves as the current path, remains constant. Therefore, if the offset voltage is removed by calculating a correction value from the output voltages Vout1 to Vout4, the resistance value between the electrodes becomes equal in each phase, and the removal accuracy can be improved.

[0044] Next, in order to compare a conventional vertical Hall element with the vertical Hall element of this embodiment, a method for removing the offset voltage of the conventional vertical Hall element by the spinning current method will be described with reference to FIGS.

[0045] Fig. 11 is a schematic plan view showing a conventional vertical Hall element, Fig. 12A is a schematic cross-sectional view taken along line XII-XII in Fig. 11, and Fig. 12B is an explanatory diagram showing resistance between electrodes in a conventional first electrode group. The conventional vertical Hall element 900 has an electrode 930 and a P-type element isolation diffusion layer 90 arranged instead of the second electrode group 120 and the P-type high-resistance diffusion layer 70 in the vertical Hall element 100. Besides this, the conventional vertical Hall element 900 is similar to the vertical Hall element 100 except that the electrode 130, the P-type buried layers 40 and 60, the N-type buried layer 50 and the P-type element isolation diffusion layer 80 in the vertical Hall element 100 are not present.

[0046] When the offset voltage of this conventional vertical Hall element 900 is removed by the spinning current method, if the current flow method is changed in each phase, the width of the depletion layer DL on the surface of the N-type epitaxial layer 30 will not be constant. This will be described with reference to Figures 13A to 20. 13B, 15B, 17B, and 19B show a voltage source that generates a voltage of Vh and the connections between the voltage source and each electrode of the first electrode group 110. The connections in each phase can be changed by switching using a switching element or the like. 14, 16, 18 and 20, a depletion layer is formed on the inner periphery side of the P-type high-resistance diffusion layer 70, but this depletion layer is not shown. Furthermore, since the electrode 930 is grounded by a wiring (not shown), the potential of the P-type element isolation diffusion layer 90 is 0V.

[0047] <Phase 1> 13A, 13B, and 14, electrodes 111, 113, and 115 are used as current supply electrodes, and a current flows from electrode 113 to electrodes 111 and 115. To this end, a voltage of Vh is applied to electrode 113, electrodes 111 and 115 are set to 0 V, and a voltage of (1 / 2)×Vh is applied to electrodes 112 and 114. Then, electrodes 112 and 114 are used as voltage output electrodes, and the voltage between electrodes 112 and 114 is obtained as voltage Vout1. At this time, since the voltages applied to the electrodes 111 to 115 are different, the electric field between them and the P-type element isolation diffusion layer 90, which has a potential of 0V, is different, and the width of the depletion layer DL generated in the N-type epitaxial layer 30 is not constant.

[0048] <Phase 2> 15A, 15B, and 16, the direction of current flow is reversed from that in FIGS. 13A and 14, and current flows from electrodes 111 and 115 to electrode 113. To achieve this, a voltage of Vh is applied to electrodes 111 and 115, electrode 113 is set to 0 V, and a voltage of (1 / 2)×Vh is applied to electrodes 112 and 114. Then, electrodes 112 and 114 are used as voltage output electrodes, and the voltage between electrodes 112 and 114 is obtained as output voltage Vout2. At this time, since the voltages applied to the electrodes 111 to 115 are different, the electric field between them and the P-type element isolation diffusion layer 90, which has a potential of 0V, is different, and the width of the depletion layer DL generated in the N-type epitaxial layer 30 is not constant and is different from the width of the depletion layer DL in phase 1.

[0049] <Phase 3> 17A, 17B, and 18, the current supply electrodes and voltage output electrodes are interchanged from those in FIGS. 13A to 16, and a current flows from electrode 112 to electrodes 111 and 114, and a current flows from electrode 115 to electrode 114. To this end, a voltage of Vh is applied to electrode 112, electrode 114 is set to 0 V, and a voltage of (1 / 2)×Vh is applied to electrodes 111, 113, and 115. Then, electrodes 111, 113, and 115 are used as voltage output electrodes, and the voltage between electrode 113 and electrodes 111 and 115 is obtained as output voltage Vout3. At this time, since the voltages applied to the electrodes 111 to 115 are different, the electric field between them and the P-type element isolation diffusion layer 90, which has a potential of 0V, is different, and the width of the depletion layer DL generated in the N-type epitaxial layer 30 is not constant and is different from the width of the depletion layer DL in phase 1 or 2.

[0050] <Phase 4> 19A, 19B, and 20, the direction of current flow is reversed from that in FIGS. 17A and 18, and current flows from electrode 114 to electrodes 112 and 115, respectively, and from electrode 111 to electrode 112. To achieve this, a voltage of Vh is applied to electrode 114, electrode 112 is set to 0 V, and a voltage of (1 / 2)×Vh is applied to electrodes 111, 113, and 115. Then, electrodes 111, 113, and 115 are used as voltage output electrodes, and the voltage between electrode 113 and electrodes 111 and 115 is obtained as output voltage Vout4. At this time, since the voltages applied to the electrodes 111 to 115 are different, the electric field between them and the P-type element isolation diffusion layer 90, which has a potential of 0V, is different, and the width of the depletion layer DL generated in the N-type epitaxial layer 30 is not constant and is different from the width of any of the depletion layers DL in phases 1 to 3.

[0051] As described above, in the conventional vertical Hall element 900, when the current flow is changed in each phase, the width of the depletion layer DL on the surface of the N-type epitaxial layer 30, which serves as the current path, is not constant. Therefore, in the spinning current method, the distribution of the depletion layer width on the surface of the N-type epitaxial layer 30, which serves as the current path, varies, which changes the resistance value between the electrodes and reduces the removal accuracy.

[0052] As described above, a vertical Hall element according to one embodiment of the present invention includes a second conductivity type impurity diffusion layer formed on a surface of a first conductivity type semiconductor substrate, and a first electrode group arranged on the surface of the impurity diffusion layer and composed of three or more electrodes. The vertical Hall element further includes a first conductivity type high-resistance diffusion layer including a second electrode group arranged in a ring shape on the outer periphery at a distance from the first electrode group, to which a voltage can be applied so as to maintain a constant electric field between the first electrode group and the second electrode group. As a result, when removing the offset voltage by the spinning current method, this vertical Hall element can remove the offset voltage with high precision by separately arranging electrodes to which a voltage can be applied that makes the distribution of the depletion layer width constant in each phase.

[0053] Although the embodiment of the present invention has been described above, the present invention is not limited to the embodiment, and various modifications are possible without departing from the spirit of the present invention.

[0054] For example, although the first conductivity type has been described as P type and the second conductivity type as N type, the conductivity types may be reversed so that the first conductivity type is N type and the second conductivity type is P type.

[0055] Although the above embodiments have been described with reference to five electrodes in the first electrode group, the number of electrodes is not limited to five. For example, if the offset voltage can be made small enough or tolerated to the extent that removal of the offset voltage by the spinning current method is unnecessary, a total of three electrodes, including two drive current supply electrodes and one Hall voltage output electrode, may be sufficient. In other words, by eliminating the electrodes 114 and 115 of the vertical Hall element 100 shown in FIG. 1 and other figures, the layout area can be reduced, thereby enabling the vertical Hall element to be miniaturized. [Explanation of symbols]

[0056] 10 P-type semiconductor substrate (first conductivity type semiconductor substrate) 20, 50 N-type buried layer 30 N-type epitaxial layer (second conductivity type impurity diffusion layer) 40, 60 P-type buried layer 70 P-type high resistance diffusion layer (first conductivity type high resistance diffusion layer) 80 Element isolation diffusion layer 100 Vertical Hall element 110 First electrode group 111, 112, 113, 114, 115 electrode 120 Second electrode group 121, 122a, 122b, 123a, 123b, 124a, 124b, 125 electrode 130 electrodes

Claims

1. A vertical Hall element formed on a surface of a semiconductor substrate of a first conductivity type, a second conductivity type impurity diffusion layer formed on the surface of the semiconductor substrate; a first electrode group arranged on a surface of the impurity diffusion layer and formed of three or more electrodes; a first conductivity type high resistance diffusion layer including a second electrode group arranged in a ring shape on the outer periphery at a distance from the first electrode group, to which a voltage can be applied so that an electric field between the second electrode group and the first electrode group is constant; A vertical Hall element comprising:

2. an inner periphery of the high-resistance diffusion layer is located at a certain distance from an outer periphery of the first electrode group; 2. The vertical Hall element according to claim 1.

3. The impurity concentration of the impurity diffusion layer increases as the depth increases.

2. The vertical Hall element according to claim 1.

4. the vertical Hall element is electrically isolated from the high-resistance diffusion layer, and the vertical Hall element is electrically isolated from the high-resistance diffusion layer.

4. The vertical Hall element according to claim 1.

5. The first electrode group is arranged in a straight line.

5. The vertical Hall element according to claim 4.

6. the first electrode group has five electrodes, A driving current is applied from the electrode located at the center to the electrodes located at both ends, detecting a Hall voltage between two electrodes located between the electrode located in the center and the electrodes located at both ends; 6. The vertical Hall element according to claim 5.

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