Image sensor including through via and semiconductor device

Abstract

To provide an image sensor improved in reliability.SOLUTION: The present invention provides an image sensor including a through via and a semiconductor device. The image sensor includes: a first substrate; a first interlayer insulating film covering the first substrate; a first semiconductor chip including a first wiring and a first landing wiring disposed in the first interlayer insulating film; a second substrate including a plurality of light receiving regions; a second interlayer insulating film covering the first substrate; and a second wiring disposed in the second interlayer insulating film, and includes: a second semiconductor chip disposed on the first semiconductor chip; a first through via penetrating the first substrate and contacting the first landing wire; and at least one first mark pattern disposed in the first landing wire and overlapping the first through via.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to an image sensor and a semiconductor device, and more particularly to an image sensor and a semiconductor device including a through via. [Background technology]

[0002] An image sensor is a semiconductor device that converts an optical image into an electrical signal. Image sensors can be classified into CCD (Charge Coupled Device) type and CMOS (Complementary Metal Oxide Semiconductor) type. The CMOS type image sensor is abbreviated as CIS (CMOS image sensor). The CIS has a plurality of pixels arranged two-dimensionally. Each pixel includes a photodiode (PD). The photodiode converts incident light into an electrical signal. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent No. 11,594,571 B2 Summary of the Invention [Problem to be solved by the invention]

[0004] SUMMARY OF THE INVENTION An object of the present invention is to provide an image sensor with improved reliability.

[0005] SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device with improved reliability.

[0006] The problems to be solved by the present invention are not limited to those mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0007] To achieve the above object, the image sensor according to the present invention includes a first semiconductor chip including a first substrate, a first interlayer insulating film covering the first substrate, and a first wiring and a first landing wiring disposed in the first interlayer insulating film; a second substrate including a plurality of light receiving regions, a second interlayer insulating film covering the second substrate, and a second wiring disposed in the second interlayer insulating film, the second semiconductor chip being disposed on the first semiconductor chip; a first through via that penetrates the first substrate and contacts the first landing wiring; and at least one first mark pattern that is disposed in the first landing wiring and overlaps the first through via.

[0008] An image sensor according to one embodiment of the present invention includes a first semiconductor chip including a first substrate, a first interlayer insulating film covering the first substrate, and a first wiring and a first landing wiring disposed in the first interlayer insulating film; a second substrate including a plurality of light receiving regions, a second interlayer insulating film covering the second substrate, and a second wiring disposed in the second interlayer insulating film, and includes a second semiconductor chip disposed on the first semiconductor chip; and a first through via that penetrates the first substrate and contacts the first landing wiring, the first landing wiring including a pad portion that contacts the first through via, the pad portion having a cross shape or a line shape in a planar view, and the first through via simultaneously covering the top and side surfaces of the pad portion.

[0009] To achieve the other object, a semiconductor device according to the present invention includes a first semiconductor chip including a first substrate, a first interlayer insulating film covering the first substrate, and a first wiring and a first landing wiring disposed in the first interlayer insulating film, a second substrate, a second interlayer insulating film covering the second substrate, and a second wiring disposed in the second interlayer insulating film, and includes a second semiconductor chip disposed on the first semiconductor chip, a first through via that penetrates the first substrate and contacts the first landing wiring, and at least one first mark pattern that is disposed in the first landing wiring and overlaps the first through via. [Effects of the Invention]

[0010] In the image sensor and semiconductor device of the present invention, since the landing wiring includes a mark pattern that contacts the through via, when forming a through via hole for the through via, whether or not the via hole is not open can be determined based on whether or not the mark pattern is exposed. Therefore, the problem of not opening the through via hole can be solved, and the reliability of the image sensor and semiconductor device can be improved. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a block diagram illustrating an image sensor according to an embodiment of the present invention; [Figure 2] 1 is a circuit diagram of an image sensor according to an embodiment of the present invention; [Figure 3] 1 is a schematic exploded perspective view of an image sensor according to an embodiment of the present invention; [Figure 4] 4 is a cross-sectional view of the image sensor of FIG. 3 taken along line AA' according to an embodiment of the present invention. [Figure 5A] 5 is an enlarged view of a portion 'P1' of FIG. 4 according to an embodiment of the present invention. [Figure 5B] FIG. 5B is a plan view showing a portion of FIG. 5A. [Figure 6A] 6A to 6C are enlarged views of a portion 'P1' in FIG. 4 according to an embodiment of the present invention. [Figure 6B] 6A to 6C are enlarged views of a portion 'P1' in FIG. 4 according to an embodiment of the present invention. [Figure 6C] 6A to 6C are enlarged views of a portion 'P1' in FIG. 4 according to an embodiment of the present invention. [Figure 7A] 5 is an enlarged view of a portion 'P1' of FIG. 4 according to an embodiment of the present invention. [Figure 7B] FIG. 7B is a plan view showing a portion of FIG. 7A. [Figure 8A] 5 is an enlarged view of a portion 'P1' of FIG. 4 according to an embodiment of the present invention. [Figure 8B]FIG. 8B is a plan view showing a portion of FIG. 8A. [Figure 9A] 5 is an enlarged view of a portion 'P1' of FIG. 4 according to an embodiment of the present invention. [Figure 9B] FIG. 9B is a plan view showing a portion of FIG. 9A. [Figure 10A] 10A to 10J are cross-sectional views showing the manufacturing process of an image sensor having the cross section of FIG. [Figure 10B] 10A to 10J are cross-sectional views showing the manufacturing process of an image sensor having the cross section of FIG. [Figure 10C] 10A to 10J are cross-sectional views showing the manufacturing process of an image sensor having the cross section of FIG. [Figure 10D] 10A to 10J are cross-sectional views showing the manufacturing process of an image sensor having the cross section of FIG. [Figure 10E] 10A to 10J are cross-sectional views showing the manufacturing process of an image sensor having the cross section of FIG. [Figure 10F] 10A to 10J are cross-sectional views showing the manufacturing process of an image sensor having the cross section of FIG. [Figure 10G] 10A to 10J are cross-sectional views showing the manufacturing process of an image sensor having the cross section of FIG. [Figure 10H] 10A to 10J are cross-sectional views showing the manufacturing process of an image sensor having the cross section of FIG. [Figure 10I] 10A to 10J are cross-sectional views showing the manufacturing process of an image sensor having the cross section of FIG. [Figure 10J] 10A to 10J are cross-sectional views showing the manufacturing process of an image sensor having the cross section of FIG. [Figure 11] 4 is a cross-sectional view of the image sensor of FIG. 3 taken along line AA' according to an embodiment of the present invention. [Figure 12] 4 is a cross-sectional view of the image sensor of FIG. 3 taken along line AA' according to an embodiment of the present invention. [Figure 13A]13A to 13H are cross-sectional views sequentially illustrating a process for manufacturing the image sensor of FIG. [Figure 13B] 13A to 13H are cross-sectional views sequentially illustrating a process for manufacturing the image sensor of FIG. [Figure 13C] 13A to 13H are cross-sectional views sequentially illustrating a process for manufacturing the image sensor of FIG. [Figure 13D] 13A to 13H are cross-sectional views sequentially illustrating a process for manufacturing the image sensor of FIG. [Figure 13E] 13A to 13H are cross-sectional views sequentially illustrating a process for manufacturing the image sensor of FIG. [Figure 13F] 13A to 13H are cross-sectional views sequentially illustrating a process for manufacturing the image sensor of FIG. [Figure 13G] 13A to 13H are cross-sectional views sequentially illustrating a process for manufacturing the image sensor of FIG. [Figure 13H] 13A to 13H are cross-sectional views sequentially illustrating a process for manufacturing the image sensor of FIG. [Figure 14] 1 is a cross-sectional view of a semiconductor memory device according to an embodiment of the present invention; [Figure 15] 15 is an enlarged view of the 'P4' portion of FIG. 14. [Figure 16] 1 is a cross-sectional view of a semiconductor memory device according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0012] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to more specifically explain the present invention, embodiments of the present invention will be described in more detail below with reference to the accompanying drawings.

[0013] FIG. 1 is a block diagram illustrating an image sensor according to an embodiment of the present invention.

[0014] 1, an image sensor 1000 can receive light from an external source and generate a digital signal. An electronic device including the image sensor 1000 can display an image on a display panel based on the digital signal. For example, the electronic device including the image sensor can be implemented as one of various types of electronic devices such as a smartphone, a tablet personal computer (PC), a laptop personal computer, a wearable device, etc.

[0015] The image sensor 1000 may include an active pixel sensor array (1001), a row driver (1002), a row decoder (1003), a column decoder (1007), a timing generator (1005), a correlated double sampler (CDS) (1004), an analog to digital converter (ADC) (1006), and an input / output buffer (I / O buffer) (1008).

[0016] The active pixel sensor array 1001 includes a plurality of light-receiving areas arranged two-dimensionally and can convert optical signals into electrical signals. The active pixel sensor array 1001 can be driven by a plurality of driving signals, such as a pixel selection signal, a reset signal, and a charge transfer signal, from a row driver 1002. The converted electrical signals can be provided to a correlated double sampler 1004.

[0017] The row driver 1002 can provide a number of drive signals to the active pixel sensor array 1001 for driving a number of unit pixels according to the results of decoding by the row decoder 1003. If the unit pixels are arranged in a matrix, a drive signal can be provided for each row.

[0018] A timing generator 1005 can provide timing and control signals to the row decoder 1003 and the column decoder 1007 .

[0019] The correlated double sampler (CDS) 1004 can receive, hold, and sample the electrical signal generated by the active pixel sensor array 1001. The correlated double sampler 1004 can double sample a specific noise level and a signal level based on the electrical signal, and output a differential level corresponding to the difference between the noise level and the signal level.

[0020] An analog-to-digital converter (ADC) 1006 can convert an analog signal corresponding to the difference level output from the correlated double sampler 1004 into a digital signal and output the digital signal.

[0021] The input / output buffer 1008 latches the digital signals, and the latched signals can be sequentially output to an image signal processor (not shown) according to the decoding results of the column decoder 1007 .

[0022] 2 and 3 are circuit diagrams and a schematic exploded perspective view, respectively, of an image sensor according to an embodiment of the present invention.

[0023] 2 and 3, the image sensor 1000 according to the present embodiment includes first to third semiconductor chips CH1, CH2, and CH3 stacked in order. Through via regions RT1, RT2, and RT3 may be disposed at edges of the first to third semiconductor chips CH1, CH2, and CH3. Through vias may be disposed in the through via regions RT1, RT2, and RT3.

[0024] A logic circuit may be disposed on the first semiconductor chip CH1. The logic circuit may include a row driver (1002), a row decoder (1003), a column decoder (1007), a timing generator (1005), a correlated double sampler (CDS) (1004), an analog-to-digital converter (ADC) (1006), and an input / output buffer (I / O buffer) (1008) shown in FIG. 1. The first semiconductor chip CH1 may be connected to the second semiconductor chip CH2 via first bonding pads CP1.

[0025] 2 and 3, a pixel (or pixel group) PXL includes a plurality of transfer transistors TX, a plurality of photoelectric conversion units PD, a plurality of floating diffusion regions FD, at least one reset transistor RX, at least one source follower transistor DX, and at least one select transistor SX. Specifically, the second semiconductor chip CH2 includes a first main region MR1 and a first edge region ER1 surrounding the first main region MR1. The reset transistor RX, source follower transistor DX, and select transistor SX shown in FIG. 2 may be provided in an array shape in the first main region MR1. The reset transistor RX includes a reset gate RG. A pixel voltage VPIX may be applied to one terminal of the reset transistor RX. The other terminal of the reset transistor RX may be connected to a third bonding pad CP3. The source follower transistor DX includes a source follower gate SF. The source follower gate SF may be connected to the third bonding pad CP3. A pixel voltage VPIX may be applied to one terminal of the source follower transistor DX. The other terminal of the source follower transistor DX is connected to one terminal of the select transistor SX. The select transistor SX includes a select gate SEL. The other terminal of the select transistor SX may be connected to a second bonding pad CP2. The second bonding pad CP2 of the second semiconductor chip CH2 may be in contact with the first bonding pad CP1 of the first semiconductor chip CH1. A plurality of third bonding pads CP3 and second bonding pads CP2 may be provided and disposed in the first main region MR1.

[0026] The third semiconductor chip CH3 has a second main region MR2 and a second edge region ER2. A plurality of light receiving regions PX are two-dimensionally arranged in the second main region MR2. A photoelectric conversion unit PD and a transfer transistor TX are arranged in each light receiving region PX. The transfer transistor TX may include a transfer gate TG. One terminal of the transfer transistor TX may be connected to each photoelectric conversion unit PD, and the other terminal of the transfer transistor TX may be a floating diffusion region FD. The floating diffusion regions FD of the light receiving regions PX may be connected to each other or may be shared. At least one floating diffusion region FD is connected to a fourth bonding pad CP4. The fourth bonding pad CP4 of the third semiconductor chip CH3 may be in contact with the third bonding pad CP3 of the second semiconductor chip CH2. One reset transistor RX, one source follower transistor DX, and one select transistor SX arranged in the second semiconductor chip CH2 may be connected to the plurality of transfer transistors TX arranged in the third semiconductor chip CH3.

[0027] The first main region MR1 of the second semiconductor chip CH2 and the second main region MR2 of the third semiconductor chip CH3 may form an active pixel sensor array (1001) of FIG.

[0028] The photoelectric conversion unit PD of the third semiconductor chip CH3 can generate and accumulate photocharges in proportion to the amount of light incident from the outside. The photoelectric conversion unit PD can include a photodiode, a phototransistor, a photogate, a pinned photodiode, or a combination thereof. The transfer transistor TX can transfer the charges generated in the photoelectric conversion unit PD to the floating diffusion region FD. The floating diffusion region FD can transfer and cumulatively store the charges generated in the photoelectric conversion unit PD. The source follower transistor DX can be controlled according to the amount of photocharges accumulated in the floating diffusion region FD.

[0029] The reset transistor RX can periodically reset the charge accumulated in the floating diffusion region FD. The drain electrode of the reset transistor RX can be connected to the floating diffusion region FD, and the source electrode can be connected to a power supply voltage. When the reset transistor RX is turned on, the power supply voltage connected to the source electrode of the reset transistor RX can be applied to the floating diffusion region FD. Therefore, when the reset transistor RX is turned on, the charge accumulated in the floating diffusion region FD can be discharged, resetting the floating diffusion region FD.

[0030] The source follower transistor DX including the source follower gate electrode SF can act as a source follower buffer amplifier, amplifying the potential change at the floating diffusion region FD and outputting it to the output line of the logic circuit.

[0031] The selection transistor SX including the selection gate electrode SEL can select a unit pixel PXL to be read out row by row. When the selection transistor SX is turned on, a power supply voltage can be applied to the drain electrode of the source follower transistor DX.

[0032] FIG. 4 is a cross-sectional view of the image sensor of FIG. 3 taken along line AA' according to an embodiment of the present invention.

[0033] Referring to FIG. 4, the image sensor 1000 includes first, second, and third semiconductor chips CH1, CH2, and CH3 stacked in sequence. The first semiconductor chip CH1 may be a logic circuit chip. The first semiconductor chip CH1 may include a first substrate SB1, a first isolation portion ST1, a first peripheral transistor PTR1, a first contact plug CT1, a first wiring IT1, a first interlayer insulating film IL1, and a first bonding pad CP1. The first isolation portion ST1 may be disposed on a front surface of the first substrate SB1 to define an active region for the first peripheral transistor PTR1. The first peripheral transistor PTR1, the first contact plug CT1, and the first wiring IT1 may be disposed on a front surface of the first substrate SB1, and the front surface of the first substrate SB1 may be covered by a first interlayer insulating film IL1. The first substrate SB1 may be, for example, a silicon single crystal wafer, a silicon epitaxial layer, or a silicon-on-insulator (SOI) substrate. The first interlayer insulating film IL1 may have a single layer or multi-layer structure made of at least one of silicon oxide, silicon nitride, silicon oxynitride, and porous insulating material.

[0034] The first peripheral transistor PTR1, the first contact plug CT1, and the first wiring IT1 may constitute a logic circuit, which may include a row driver (1002), a row decoder (1003), a column decoder (1007), a timing generator (1005), a correlated double sampler (CDS) (1004), an analog-to-digital converter (ADC) (1006), and an input / output buffer (I / O buffer) (1008) as shown in FIG.

[0035] The second semiconductor chip CH2 can transmit charges or electrical signals generated by light in the light-receiving region PX of the third semiconductor chip CH3 to the first semiconductor chip CH1. The second semiconductor chip CH2 includes first and second lower insulating layers BL1 and BL2, a second substrate SB2, a second element isolation portion ST2, a source follower transistor DX, a select transistor SX, a second peripheral transistor PTR2, a second contact plug CT2, a second wiring IT2, a first landing wiring LT1, a second interlayer insulating layer IL2, a second bonding pad CP2, a third bonding pad CP3, a first through via TV1, and a first via insulating layer 11.

[0036] The second substrate SB2 may be, for example, a silicon single crystal wafer, a silicon epitaxial layer, or an SOI (silicon on insulator) substrate. Each of the first and second lower insulating layers BL1 and BL2, the second interlayer insulating layer IL2, and the first via insulating layer 11 may have a single layer or multi-layer structure made of at least one of silicon oxide, silicon nitride, silicon oxynitride, SiCN, and a porous insulating material.

[0037] The back surface SB2_B of the second substrate SB2 may be covered in order with first and second lower insulating layers BL1 and BL2. A second bonding pad CP2 may be disposed in the second lower insulating layer BL2. The lower surface of the second bonding pad CP2 contacts the upper surface of the first bonding pad CP1. The lower surface of the second lower insulating layer BL2 contacts the upper surface of the first interlayer insulating layer IL1.

[0038] A second isolation portion ST2 is disposed on the front surface SB2_F of the second substrate SB2 to define active regions for the source follower transistor DX, the select transistor SX, and the second peripheral transistor PTR2. The source follower transistor DX, the select transistor SX, the second peripheral transistor PTR2, the second contact plug CT2, and the second wiring IT2 are disposed on the front surface SB2_F of the second substrate SB2, and a second interlayer insulating film IL2 covers the front surface SB2_F of the second substrate SB2. A third bonding pad CP3 is disposed on the upper end of the second interlayer insulating film IL2.

[0039] The third semiconductor chip CH3 may be a light-sensing chip. The third semiconductor chip CH3 includes a third substrate SB3 and a third interlayer insulating film IL3. A front surface SB3_F of the third substrate SB3 faces the second semiconductor chip CH2. The third substrate SB3 may be doped with impurities of a first conductivity type. For example, the first conductivity type may be P-type.

[0040] The third substrate SB3 includes a second main region MR2 and a second edge region ER2. The second main region MR2 includes a plurality of light-receiving regions PX. Deep isolation portions DTI are disposed on the third substrate SB3 to separate the light-receiving regions PX from one another. The deep isolation portions DTI may have a mesh shape in a plan view. The deep isolation portions DTI may include an insulating material.

[0041] Photoelectric conversion units PD may be disposed within the third substrate SB3 in the light receiving regions PX. The photoelectric conversion units PD may be doped with impurities of a second conductivity type opposite to the first conductivity type. The second conductivity type may be, for example, N-type. The N-type impurities doped in the photoelectric conversion units PD may form a PN junction with P-type impurities doped in the surrounding third substrate SB3 to provide a photodiode.

[0042] A third isolation portion ST3 may be disposed on a front surface SB3_F of the third substrate SB3. The third isolation portion ST3 may be penetrated by a deep isolation portion DTI. The third isolation portion ST3 may define an active region for a transfer transistor TX in each unit light receiving region PX. An interface may not be observed between the third isolation portion ST3 and the deep isolation portion DTI.

[0043] 4, a transfer gate TG may be disposed on the front surface SB3_F of the third substrate SB3 in each unit light receiving region PX. The transfer gate TG may be a vertical type, or may be a planar type that does not extend into the third substrate SB3 and is flat. A floating diffusion region FD may be disposed in the third substrate SB3 beside the transfer gate TG in each unit light receiving region PX. The floating diffusion region FD may be doped with, for example, impurities of the second conductivity type.

[0044] A third contact plug CT3 and a third wiring IT3 are disposed on a front surface SB3_F of the third substrate SB3. The front surface SB3_F of the third substrate SB3 may be covered with a third interlayer insulating film IL3. A fourth bonding pad CP4 is disposed on a lower end of the third interlayer insulating film IL3 and contacts the third bonding pad CP3.

[0045] The first through third contact plugs CT1 through CT3, the first through third wirings IT1 through IT3, the first landing wiring LT1, and the first through fourth bonding pads CP1 through CP4 may each include a metal such as aluminum, copper, tungsten, titanium, or tantalum. The third interlayer insulating film IL3 may have a single layer or multi-layer structure made of at least one of silicon oxide, silicon nitride, silicon oxynitride, SiCN, and a porous insulating material.

[0046] The back surface SB3_B of the third substrate SB3 may be covered with a fixed charge layer FL. The fixed charge layer FL may have negative fixed charges. The fixed charge layer FL may be made of a metal oxide or metal fluoride containing at least one metal selected from the group consisting of hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (Ti), yttrium, and lanthanides. For example, the fixed charge layer FL may be a hafnium oxide layer or an aluminum oxide layer. In this case, hole accumulation may occur around the fixed charge layer FL. Therefore, dark current and white spots may be effectively reduced.

[0047] A light-shielding grid pattern WG and a first optical black pattern BT are disposed on the fixed charge layer FL. The light-shielding grid pattern WG is disposed in the second main region MR2 and may overlap the deep isolation portion DTI. The first optical black pattern BT is disposed in the second edge region ER2. The light-shielding grid pattern WG and the first optical black pattern BT may be made of the same material and have the same thickness. The light-shielding grid pattern WG and the first optical black pattern BT may include at least one of titanium, titanium nitride, and tungsten, for example.

[0048] A color filter array including color filters CF1 and CF2 may be disposed between the light-blocking grid patterns WG. Each of the color filters CF1 and CF2 may have one of blue, green, and red. As another example, the color filters CF1 and CF2 may include other colors such as cyan, magenta, or yellow. The color filters CF1 and CF2 may be arranged in a Bayer pattern, a 2x2 Tetra pattern, a 3x3 Nona pattern, or a 4x4 Hexadeca pattern. A second optical black pattern CFB may be disposed on the first optical black pattern BT. The second optical black pattern CFB may be made of the same material as the blue color filter.

[0049] A microlens ML may be disposed on the color filters CF1 and CF2. A lens residual layer MLR may be disposed on the second optical black pattern CFB. The lens residual layer MLR may include the same transparent material as the microlens ML.

[0050] The image sensor 1000 may be a rear surface photodetection image sensor. Light may be incident into the third substrate SB3 through the rear surface SB3_B of the third substrate SB3. The incident light may generate electron-hole pairs at the PN junction. The generated electrons may be transferred to the photoelectric conversion unit PD. When a voltage is applied to the transfer gate TG, the electrons may be transferred to the floating diffusion region FD. The floating diffusion region FD may be connected to the source follower gate SF via a third contact plug CT3, a third wiring IT3, a fourth bonding pad CP4, a third bonding pad CP3, a second wiring IT2, and a second contact plug CT2.

[0051] Figure 5A is an enlarged view of a portion 'P1' in Figure 4 according to an embodiment of the present invention, and Figure 5B is a plan view showing a portion of Figure 5A.

[0052] 4, 5A, and 5B, a source / drain region IM of the second peripheral transistor PTR2 may be formed in the second substrate SB2. A portion of the second contact plug CT2 may be in contact with the source / drain region IM. A first through via TV1 may penetrate the first lower insulating layer BL1, the second substrate SB2, the second device isolation portion ST2, and a portion of the second interlayer insulating layer IL2 to connect the second bonding pad CP2 to the first landing wire LT1. A first via insulating layer 11 may be interposed between the first through via TV1 and the second substrate SB2. The first through via TV1 may include a metal such as copper or tungsten. The first through via TV1 may have a width that narrows as it rises. The first through via TV1 and the first via insulating layer 11 may be disposed within a through via hole TH1.

[0053] A plurality of via plugs VA2 may be disposed between the first landing wire LT1 and the second wire IT2 disposed thereon. The first landing wire LT1 may be in contact with the first through via TV1. A mark pattern IP may be disposed within the first landing wire LT1. The mark pattern IP may penetrate the first landing wire LT1. The mark pattern IP may have the same thickness as the first landing wire LT1.

[0054] The mark pattern IP may be formed of a different material from the first landing wire LT1. For example, the mark pattern IP may include at least one of silicon oxide, silicon nitride, silicon oxynitride, polysilicon, and silicon germanium. Alternatively, the mark pattern IP may include a different metal from the first landing wire LT1. In a plan view, the mark pattern IP may be located within the through via hole TH1. The mark pattern IP may be vertically overlapped with the first through via TV1. The mark pattern IP may be in contact with the first through via TV1. The planar shape of the mark pattern IP may be various, such as a circle, an ellipse, a square, a polygon, a cross, or a closed curve.

[0055] When forming the through via hole TH1, the mark pattern IP can be used to check whether the through via hole TH1 is open, thereby solving the problem of the through via hole TH1 not being open, and thus providing an image sensor with improved reliability.

[0056] 6A to 6C are enlarged views of a portion 'P1' in FIG. 4 according to an embodiment of the present invention.

[0057] 6A, a portion TV1_P of the first through via TV1 is inserted into the first landing line LT1 and covers the inner wall of the first landing line LT1. The thickness of the mark pattern IP may be thinner than the first landing line LT1. Because the first through via TV1 is extended to cover the inner wall of the first landing line LT1, the contact area between the first through via TV1 and the first landing line LT1 is increased, reducing electrical resistance therebetween and improving mechanical (physical) bonding strength therebetween. Therefore, an image sensor with improved reliability may be provided.

[0058] 6B, a portion TV1_P of the first through via TV1 is inserted into the first landing line LT1 to cover not only the inner wall of the first landing line LT1 but also at least one sidewall of the via plug VA2. The image sensor according to the structure of FIG. 6B can eliminate the mark pattern IP of FIGS. 5A and 6A.

[0059] Alternatively, referring to FIG. 6C, a portion TV1_P of the first through via TV1 may be further extended in the state of FIG. 6B to contact the lower surface of the second wiring IT2.

[0060] Figure 7A is an enlarged view of a portion 'P1' in Figure 4 according to an embodiment of the present invention, and Figure 7B is a plan view showing a portion of Figure 7A.

[0061] 7A and 7B, two mark patterns IP may be disposed in the first landing wire LT1. The two mark patterns IP may contact the first through via TV1. The two mark patterns IP may be located in the through via hole TH1. In this example, the number of mark patterns IP is two, but the present invention is not limited thereto, and three or more mark patterns IP may be provided. In addition, the arrangement and intervals of the mark patterns IP may also vary.

[0062] 8A is an enlarged view of a portion 'P1' of FIG. 4 according to an embodiment of the present invention. FIG. 8B is a plan view showing a portion of FIG. 8A. FIG. 8A may correspond to a cross section of FIG. 8B taken along line B-B'.

[0063] 8A and 8B, the first landing wire LT1 may include a wiring portion WP and a pad portion PP. The pad portion PP contacts the first through via TV1. The pad portion PP may have a cross shape in a plan view. Alternatively, the pad portion PP may have a line shape or a polygonal shape in a plan view. One edge of the pad portion PP may be exposed by a through via hole TH1. A portion TV1_P of the first through via TV1 may cover a side surface of the pad portion PP. The first through via TV1 may cover the entire side surface of a corner of the pad portion PP. Because the first through via TV1 covers the inner wall of the first landing wire LT1, the contact area between the first through via TV1 and the first landing wire LT1 is increased, reducing electrical resistance therebetween and improving mechanical (physical) bonding strength therebetween. Therefore, an image sensor with improved reliability may be provided. Other configurations are the same or similar to those described above.

[0064] 8A and 8B, when forming the through via hole TH1, whether the through via hole TH1 is open can be confirmed by whether one edge of the pad portion PP is exposed. Therefore, the problem of the through via hole TH1 not being open can be solved. In addition, because a portion TV1_P of the first through via TV1 covers the side surface of the pad portion PP, the contact area between the first through via TV1 and the first landing line LT1 is increased, thereby reducing the electrical resistance therebetween. Therefore, an image sensor with improved reliability can be provided.

[0065] Figure 9A is an enlarged view of a portion 'P1' in Figure 4 according to an embodiment of the present invention, and Figure 9B is a plan view showing a portion of Figure 9A.

[0066] 9A and 9B, the first landing wire LT1 may include a wiring portion WP and a pad portion PP. The pad portion PP may have a cross shape in a plan view. A mark pattern IP may be located at the center of the pad portion PP. Other configurations are the same or similar to those described above.

[0067] 4 illustrates one first through via TV passing through the second substrate SB2 of the second semiconductor chip CH2, the number of first through vias TV is not limited thereto and may be multiple. Also, an additional through via may be provided and pass through at least one of the first substrate SB1 of the first semiconductor chip CH1 and the third substrate SB3 of the third semiconductor chip CH3.

[0068] The concept of individual semiconductor chips in this specification can be defined as a stacked structure formed from different semiconductor wafers. Although the boundaries of individual semiconductor chips may not be clearly visible depending on the bonding form and bonding materials between chips, even in the case of such a stacked structure, it is not excluded from the concept of individual semiconductor chips formed from different semiconductor wafers.

[0069] 10A to 10J are cross-sectional views showing the manufacturing process of the image sensor having the cross section of FIG.

[0070] 10A, a first semiconductor chip wafer CH1_W is manufactured through a conventional process. The first semiconductor chip wafer CH1_W may include device regions and scribe lane regions therebetween. Each device region in the first semiconductor chip wafer CH1_W includes a first substrate SB1, a first device isolation portion ST1, a first peripheral transistor PTR1, a first contact plug CT1, a first wiring IT1, a first interlayer insulating film IL1, and a first bonding pad CP1, as shown in FIG. 10A.

[0071] Referring to FIG. 10B, a second semiconductor chip wafer CH2_W is manufactured through a conventional process. The second semiconductor chip wafer CH2_W may include device regions and scribe lane regions therebetween. As shown in FIG. 10B, each device region in the second semiconductor chip wafer CH2_W includes a second substrate SB2, a second device isolation portion ST2, a source follower transistor DX, a select transistor SX, a second peripheral transistor PTR2, a second contact plug CT2, a second wiring IT2, a first landing wiring LT1, a second interlayer insulating film IL2, and a third bonding pad CP3. The second substrate SB2 may have a first thickness T1. As shown in FIG. 5A, a mark pattern IP may be present in the first landing wiring LT1.

[0072] Referring to FIG. 10C, a third semiconductor chip wafer CH3_W is manufactured through a conventional process. The third semiconductor chip wafer CH3_W may include device regions and scribe lane regions therebetween. As shown in FIG. 10C, each device region in the third semiconductor chip wafer CH3_W includes a third substrate SB3, a third device isolation portion ST3, a deep isolation portion DTI, a transfer gate TG, a floating diffusion region FD, a third contact plug CT3, a third wiring IT3, and a fourth bonding pad CP4. The third substrate SB3 may have a third thickness T3. The deep isolation portion DTI may have a depth that is lower than the back surface SB3_B of the third substrate SB3.

[0073] 10D, a thermocompression bonding process is performed to flip the second semiconductor chip wafer CH2_W of FIG. 10B over and bond it onto the third semiconductor chip wafer CH3_W of FIG. 10C. Therefore, the third interlayer insulating film IL3 contacts the second interlayer insulating film IL2, and the fourth bonding pads CP4 contact the third bonding pads CP3. A backgrinding process is performed on the back surface SB2_B of the second substrate SB2 of the second semiconductor chip wafer CH2_W to thin the second substrate SB2 to a second thickness T2.

[0074] 5A, 5B, and 10E, a first lower insulating film BL1 is formed on the back surface SB2_B of the second substrate SB2. The first lower insulating film BL1, the second substrate SB2, the second isolation portion ST2, and the second interlayer insulating film IL2 are etched to form a through via hole TH1 exposing the first landing line LT1. At this time, the mark pattern IP of the first landing line LT1 may be exposed. After forming the through via hole TH1, it may be checked using a scanning electron microscope, etc., whether the mark pattern IP is exposed. Therefore, when forming the through via hole TH1, the open state of the through via hole TH1 may be confirmed by the mark pattern IP. Therefore, the problem of the through via hole TH1 not being open may be solved. Therefore, an image sensor with improved reliability may be provided.

[0075] 5A, 5B, and 10F, in the state of FIG. 10E, an insulating film is conformally formed on the first lower insulating film BL1 to cover the inner wall of the through via hole TH1, and then an anisotropic etching process is performed on the insulating film to open the bottom of the through via hole TH1 and simultaneously form the via insulating film 11. The opening of the through via hole TH1 can also be confirmed by the mark pattern IP when forming the via insulating film 11. A conductive film is deposited to fill the through via hole TH1, and a planarization process is performed to form the first through via TV1.

[0076] 10G, a second lower insulating film BL2 is formed on the first lower insulating film BL1, and a second bonding pad CP2 is formed in the second lower insulating film BL2 to contact the first through via TV1.

[0077] 10H and 10I, a thermocompression bonding process is performed to flip the first semiconductor chip wafer CH1_W of FIG. 10A over and bond it onto the second semiconductor chip wafer CH2_W. Therefore, the second lower insulating film BL2 contacts the first interlayer insulating film IL1, and the second bonding pads CP2 contact the first bonding pads CP1. The bonded structure is then flipped over, so that the back surface SB3_B of the third substrate SB3 of the third semiconductor chip wafer CH3_W faces upward.

[0078] 10J, a backgrinding process is performed on the back surface SB3_B of the third substrate SB3. Therefore, the third substrate SB3 having the third thickness T3 as shown in FIG. 10C may be thinned to a fourth thickness T4. The backgrinding process may also partially remove and expose the deep isolation portion DTI.

[0079] 4, a fixed charge layer FL, a light-shielding grid pattern WG, color filters CF1 and CF2, a first optical black pattern BT, a second optical black pattern CFB, a microlens ML, a lens residual layer MLR, etc. may be formed on the back surface SB3_B of the third substrate SB3 by performing a conventional process. Then, a sawing process for cutting a scribe lane area may be performed to manufacture the image sensor 1000 of FIG. 4.

[0080] As described above, the method for manufacturing an image sensor according to the present invention can solve the problem of the through via hole TH1 not being open, thereby reducing process defects and improving yield.

[0081] FIG. 11 is a cross-sectional view of the image sensor of FIG. 3 taken along line AA' according to an embodiment of the present invention.

[0082] 11, in the image sensor 1000a according to this embodiment, the second semiconductor chip CH2 may include a first landing wire LT1 and a second landing wire LT2 that are spaced apart from each other. A first mark pattern IP1 is disposed in the first landing wire LT1, and a second mark pattern IP2 is disposed in the second landing wire LT2. A first through via TV1 may penetrate the second substrate SB2 and contact the first landing wire LT1 and the first mark pattern IP1.

[0083] The deep isolation portion DTI included in the third semiconductor chip CH3 may include an isolation conductive pattern 14 and an isolation insulating pattern 16. The isolation insulating pattern 16 may be interposed between the isolation conductive pattern 14 and the third substrate SB3. In the second edge region ER2, a back contact pattern BCA may penetrate the fixed charge layer FL, a portion of the third substrate SB3, and a portion of the deep isolation portion DTI to connect the isolation conductive pattern 14 to the first optical black pattern BT. In this case, the first optical black pattern BT may also be referred to as a 'back wiring'.

[0084] In the second edge region ER2, a second through via TV2 may penetrate the fixed charge layer FL, the third substrate SB3, the third interlayer insulating film IL3, and a portion of the second interlayer insulating film IL2 to connect the first optical black pattern BT to the second landing line LT2. The second through via TV2 may include a metal such as copper or tungsten. The second through via TV2 may be in contact with a second mark pattern IP2. The second through via TV2 and the second mark pattern IP2 may have the same or similar structure as the first through via TV1 and the first mark pattern IP1 described with reference to FIGS. 5A to 9B. A second via insulating film 21 may be interposed between the second through via TV2 and the third substrate SB3. The second via insulating film 21 may be formed of silicon oxide. The remaining structure may be the same or similar to that described with reference to FIG. 4.

[0085] FIG. 12 is a cross-sectional view of the image sensor of FIG. 3 taken along line AA' according to an embodiment of the present invention.

[0086] 12, in the image sensor 1000b according to this embodiment, the second semiconductor chip CH2 may have a structure similar to the inverted second semiconductor chip CH2 of FIG. 3. Specifically, in the second semiconductor chip CH2 according to this embodiment, the front surface SB2_F of the second substrate SB faces the first semiconductor chip CH1, and the back surface SB2_B of the second substrate SB faces the third semiconductor chip CH3. First and second lower insulating films BL1 and BL2 are sequentially stacked on the back surface SB2_B of the second substrate SB. A plurality of first landing wires LT1 are disposed, and some of the first landing wires LT1 may overlap the second main region MR2. A portion of the first landing wire LT1 may be extended to vertically overlap the source follower gate SF.

[0087] The first through vias TV1 may penetrate the first lower insulating film BL1, the second substrate SB2, the second isolation portion ST2, and a portion of the second interlayer insulating film IL2 to contact the first landing wires LT1. The first through vias TV1 may have a width that narrows as they go downward. Mark patterns IP may be disposed in the first landing wires LT1. A fourth wire IT4 and a third bonding pad CP3 may be disposed in the second lower insulating film BL2. The fourth wire IT4 may connect the first through vias TV1 to the third bonding pad CP3. The first landing wires LT1 and the mark patterns IP may have the same or similar structures as those described with reference to FIGS. 5A to 9B. Other structures may be the same or similar to those shown in FIG. 4.

[0088] 13A to 13H are cross-sectional views sequentially illustrating a process for manufacturing the image sensor of FIG.

[0089] Referring to FIG. 13A, a first semiconductor chip wafer CH1_W is manufactured through a conventional process. The first semiconductor chip wafer CH1_W may include device regions and scribe lane regions therebetween. As shown in FIG. 13A, each device region in the first semiconductor chip wafer CH1_W includes a first substrate SB1, a first device isolation portion ST1, a first peripheral transistor PTR1, a first contact plug CT1, a first wiring IT1, a first interlayer insulating film IL1, and a first bonding pad CP1. The first bonding pad CP1 may be disposed not only at the edge of the first substrate SB1 but also at the center.

[0090] Referring to FIG. 13B, a second semiconductor chip wafer CH2_W is manufactured through a conventional process. The second semiconductor chip wafer CH2_W may include device regions and scribe lane regions therebetween. As shown in FIG. 13B, each device region in the second semiconductor chip wafer CH2_W includes a second substrate SB2, a second device isolation portion ST2, a source follower transistor DX, a select transistor SX, a second peripheral transistor PTR2, a second contact plug CT2, a second wiring IT2, a first landing wiring LT1, a second interlayer insulating film IL2, and a second bonding pad CP2. The second substrate SB2 may have a first thickness T1. Mark patterns IP may be present in the first landing wiring LT1.

[0091] 13C, a thermocompression bonding process is performed to flip the second semiconductor chip wafer CH2_W of FIG. 13B over and bond it onto the first semiconductor chip wafer CH1_W of FIG. 13A, so that the first interlayer insulating film IL1 contacts the second interlayer insulating film IL2, and the first bonding pads CP1 contact the second bonding pads CP2.

[0092] 13D, a backgrinding process is performed on the back surface SB2_B of the second substrate SB2 of the second semiconductor chip wafer CH2_W to thin the second substrate SB2 to a second thickness T2. A first lower insulating film BL1 is formed on the back surface SB2_B of the second substrate SB2.

[0093] 5A, 5B, and 13E, the first lower insulating film BL1, the second substrate SB2, the second isolation portion ST2, and the second interlayer insulating film IL2 are etched to form through via holes TH1 exposing the first landing wires LT1. At this time, the mark patterns IP of the first landing wires LT1 may be exposed. After forming the through via holes TH1, it may be checked using a scanning electron microscope or the like whether the mark patterns IP are exposed. Therefore, when forming the through via holes TH1, it may be possible to check whether the through via holes TH1 are open or not using the mark patterns IP. This may solve the problem of the through via holes TH1 not being open. This may provide an image sensor with improved reliability.

[0094] 13F, an insulating film is conformally formed on the first lower insulating film BL1 to cover the inner wall of the through via hole TH1, and then an anisotropic etching process is performed on the insulating film to open the bottom of the through via hole TH1 and simultaneously form a via insulating film 11. The mark pattern IP can be used to confirm whether the through via hole TH1 is open while the via insulating film 11 is being formed. A conductive film is deposited to fill the through via hole TH1, and a planarization process is performed to form a first through via TV1.

[0095] 13G, a second lower insulating film BL2, a fourth interconnection IT4, and a third bonding pad CP3 are formed on a first lower insulating film BL1. Then, a third semiconductor chip CH3 is manufactured through a typical process as shown in FIG. 10C. The third semiconductor chip CH3 includes a third substrate SB3, a third device isolation portion ST3, a deep isolation portion DTI, a transfer gate TG, a floating diffusion region FD, a third contact plug CT3, a third interconnection IT3, and a fourth bonding pad CP4. The deep isolation portion DTI may have a depth less than the back surface SB3_B of the third substrate SB3.

[0096] 13G and 13H, the third semiconductor chip wafer CH3_W of FIG. 10C is flipped over and bonded onto the second semiconductor chip wafer CH2_W, so that the second lower insulating film BL2 contacts the third interlayer insulating film IL3 and the fourth bonding pads CP4 contact the third bonding pads CP3.

[0097] Next, referring to Figure 10J, a backgrinding process is performed on the back surface SB3_B of the third substrate SB3. Therefore, the third substrate SB3 having the third thickness T3 as shown in Figure 10C may be thinned to a fourth thickness T4. The backgrinding process may also partially remove and expose the deep isolation portion DTI.

[0098] 12, a fixed charge layer FL, a light-shielding grid pattern WG, color filters CF1 and CF2, a first optical black pattern BT, a second optical black pattern CFB, a microlens ML, a lens residual layer MLR, etc. may be formed on the back surface SB3_B of the third substrate SB3 by performing a conventional process. Then, a sawing process for cutting the scribe lane area may be performed to manufacture the image sensor 1000b of FIG.

[0099] FIG. 14 is a cross-sectional view of a semiconductor memory device according to an embodiment of the present invention.

[0100] 14 and 15, a peripheral circuit structure PS and a cell array structure CS are sequentially stacked on a substrate 103. The substrate 103 may be a silicon single crystal substrate or an SOI (Silicon on Insulator) substrate. The lower surface of the substrate 103 may be covered with a first lower insulating layer 1 and a second lower insulating layer 3. The first lower insulating layer 1 may have a single layer or multi-layer structure of at least one of silicon oxide or silicon nitride, for example. The second lower insulating layer 3 may be made of silicon carbonitride (SiCN).

[0101] An isolation layer 105 may be disposed on the substrate 103 to define an active region. The peripheral circuit structure PS includes a peripheral circuit. A peripheral transistor PTR may be disposed on the active region. Each peripheral transistor PTR may include a peripheral gate electrode, a peripheral gate insulating layer, and peripheral source / drain regions disposed in the substrate 103 adjacent to both sides thereof. The peripheral transistor PTR may be covered with a peripheral interlayer insulating layer 107. The peripheral interlayer insulating layer 107 may have a single layer or multi-layer structure of at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a porous insulating layer. Peripheral wirings 109a and 109b, a first landing wiring LT1, and a peripheral contact 33 may be disposed in the peripheral interlayer insulating layer 107. The peripheral wirings 109a and 109b, the first landing wiring LT1, and the peripheral contact 33 may include conductive layers.

[0102] The peripheral wirings 109a and 109b, the first landing wiring LT1, and a portion of the peripheral contact 33 may be electrically connected to the peripheral transistor PTR. The peripheral transistor PTR, the peripheral wirings 109a and 109b, the first landing wiring LT1, and the peripheral contact 33 may form a page buffer circuit and a decoder circuit.

[0103] An interface film 111 is disposed on the peripheral circuit structure PS. The interface film 111 may include a material having etching selectivity with the semiconductor film 201 and the peripheral interlayer insulating film 107. For example, the interface film 111 may include silicon nitride or silicon oxide. The interface film 111 may also be referred to as an adhesion film.

[0104] A cell array structure CS is disposed on the interface film 111. The cell array structure CS includes a semiconductor film 201, a source structure SCL, a first stack structure STC1, a second stack structure STC2, and first to fourth upper insulating films 205, 207, 209, and 211, which are stacked in sequence. The first stack structure STC1 may include a first electrode layer EL1 and a first inter-electrode insulating film 12, which are alternately stacked. The second stack structure STC2 may include a second electrode layer EL2 and a second inter-electrode insulating film 22, which are alternately stacked, and a second uppermost inter-electrode insulating film 24, which is located on the top layer. The semiconductor film 201 may be, for example, a silicon single crystal layer, a silicon epitaxial layer, or an SOI substrate. The semiconductor film 201 may be doped with, for example, a first conductive type impurity. The first conductive type impurity may be, for example, boron for p-type, or arsenic or phosphorus for n-type.

[0105] The electrode layers EL1 and EL2 may include at least one selected from a doped semiconductor (ex, doped silicon, etc.), a metal (ex, tungsten, copper, aluminum, etc.), a conductive metal nitride (ex, titanium nitride, tantalum nitride, etc.), or a transition metal (ex, titanium, tantalum, etc.). The inter-electrode insulating films 12, 22, and 24 may include at least one single layer or multiple layers selected from a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and a porous insulating film.

[0106] The source structure SCL may include a first source pattern SC1 interposed between the lowermost inter-electrode insulating film 12 and the semiconductor layer 201, and a second source pattern SC2 interposed between the first source pattern SC1 and the semiconductor layer 201. Although not shown, a portion of the first source pattern SC1 may contact the semiconductor layer 201 through the second source pattern SC2. The first source pattern SC1 may include a semiconductor pattern doped with impurities, for example, polysilicon doped with impurities of a first conductivity type. The second source pattern SC2 may include a semiconductor pattern doped with impurities, for example, polysilicon doped with impurities. The second source pattern SC2 may further include the first source pattern SC1 and another semiconductor material. The conductivity type of the impurities doped in the second source pattern SC2 may be the same as the conductivity type of the impurities doped in the first source pattern SC1. The concentration of the impurities doped in the second source pattern SC2 may be the same as or different from the concentration of the impurities doped in the first source pattern SC1.

[0107] The inter-electrode insulating films 12, 22, and 24 and the electrode layers EL1 and EL2 may be penetrated by a cell vertical pattern VS. The cell vertical pattern VS may be disposed on the cell region CAR. A gate insulating film GO may be interposed between the electrode layers EL1 and EL2 and the cell vertical pattern VS. Each of the cell vertical patterns VS may have a hollow cup shape. The cell vertical pattern VS may include, for example, a silicon single crystal layer or polysilicon that is not doped with impurities. A sidewall of the cell vertical pattern VS may have an inflection point adjacent to the first stack structure STC1 and the second stack structure STC2.

[0108] The interior of the cell vertical patterns VS may be filled with a buried insulating pattern 29. The buried insulating pattern 29 may have a single-layer or multi-layer structure made of at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. A bit line pad BPD may be disposed on each of the cell vertical patterns VS. The bit line pad BPD may include impurity-doped polysilicon or a metal such as tungsten, aluminum, or copper. The second source pattern SC2 may penetrate the gate insulating layer GO and contact the lower sidewalls of the cell vertical patterns VS.

[0109] FIG. 15 is an enlarged view of the 'P4' portion of FIG.

[0110] 14 and 15, the gate insulating film GO may include a tunnel insulating film TL, a charge storage film SN, and a blocking insulating film BCL. The charge storage film SN may be a trap insulating film, a floating gate electrode, or an insulating film including conductive nanodots. More specifically, the charge storage film SN may include at least one of a silicon nitride film, a silicon oxynitride film, a silicon-rich nitride film, nanocrystalline silicon, and a laminated trap layer. The tunnel insulating film TL may be one of materials having a larger bandgap than the charge storage film SN, and the blocking insulating film BCL may be a high-k film such as an aluminum oxide film or a hafnium oxide film.

[0111] The gate insulating film GO may further include a high-dielectric layer HL. The high-dielectric layer HL may be interposed between the blocking insulating film BCL and the electrode layers EL1 and EL2. The high-dielectric layer HL may be interposed between the electrode layers EL1 and EL2 and the inter-electrode insulating films 12, 22, and 24. The high-dielectric layer HL may include a metal oxide layer, such as a hafnium oxide layer or an aluminum oxide layer, having a higher dielectric constant than a silicon oxide layer. The second source pattern SC2 may penetrate the gate insulating film GO and contact the cell vertical pattern VS. A lower portion of the gate insulating film GO may be separated from an upper portion of the gate insulating film GO by the second source pattern SC2.

[0112] On the connection region CNR, the lower insulating pattern 5 may penetrate the source structure SCL and the semiconductor layer 201 to contact the interface layer 111. The lower insulating pattern 5 may be formed of, for example, silicon oxide.

[0113] A second upper insulating layer 207 may be disposed on the first upper insulating layer 205. First conductive lines BLL extending in a second direction D2 and parallel to each other may be disposed on the second upper insulating layer 207. In the cell region CAR, a first contact CT1 may penetrate the first and second upper insulating layers 205 and 207 to connect one of the first conductive lines BLL to a bit line pad BPD disposed on the cell vertical pattern VS.

[0114] Third contacts CT3 penetrate the second upper insulating film 207. One of the third contacts CT3 may be in contact with the first through via TV1. The stack structures STC1 and STC2 may have a stepped shape in the connection region CNR. That is, the electrode layers EL1 and EL2 and the inter-electrode insulating films 12, 22, and 24 may have a stepped shape in the connection region CNR. The electrode layers EL1 and EL2 and the inter-electrode insulating films 12, 22, and 24 may be elongated and protruded in the first direction D1 toward the peripheral circuit structure PS. An end of the first stack structure STC1 in the connection region CNR may be covered with a first planar insulating film 210. An end of the second stack structure ST2 in the connection region CNR may be covered with a second planar insulating film 220. The planar insulating films 210 and 220 may include a silicon oxide film or a porous insulating film.

[0115] Ends of the electrode layers EL1 and EL2 may be connected to cell contact plugs CC, respectively. The cell contact plugs CC may be connected to corresponding ones of the electrode layers EL1 and EL2 through the first upper insulating film 205 and the inter-electrode insulating films 12, 22, and 24. One of the cell contact plugs CC may be in contact with one of the electrode layers EL1 and EL2, and a side of the one cell contact plug CC may protrude laterally at the level of the one electrode layer EL1 and EL2. A contact insulating film 4 may be interposed between the one cell contact plug CC and the other electrode layer EL1 or EL2 not connected to the one cell contact plug CC. A second contact CT2 may be connected to the cell contact plug CC. An interconnection line CL may be disposed on the second upper insulating film 207.

[0116] In the connection region CNR, a first through via TV1 may penetrate the first upper insulating film 205, the planar insulating films 210 and 220, the semiconductor film 201, and the interface film 111 to contact a first landing line LT1. A mark pattern IP is disposed in the first landing line LT1. The first through via TV1 may be separated from the stack structures STC1 and STC2. The first through via TV1 may be connected to the connection line CL by second contacts CT2 and third contacts CT3 disposed in the second upper insulating film 207. Therefore, the electrode layers EL1 and EL2 may be connected to, for example, a decoder circuit of the peripheral circuit structure PS. A sidewall of the first through via TV1 may be surrounded by a first via insulating film 11.

[0117] The first through via TV1 may include at least one metal selected from tungsten, aluminum, copper, titanium, and tantalum. The first via insulating film 11 may include an insulating material such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. The cell contact plug CC and the first through via TV1 may have the same height.

[0118] A ground region WR may be disposed in the semiconductor layer 201 at a location spaced apart from the first through via TV1. The ground region WR may be doped with impurities of the first conductivity type doped in the semiconductor layer 201 at a concentration higher than the concentration of the impurities doped in the semiconductor layer 201. A ground contact plug WC may penetrate the first upper insulating layer 205 and the planar insulating layers 210 and 220 in the connection region CNR to contact the ground region WR.

[0119] The connection line CL may be covered with a third upper insulating layer 209. A fourth contact CT4 may penetrate the third upper insulating layer 209. A fourth upper insulating layer 211 is disposed on the third upper insulating layer 209.

[0120] FIG. 16 is a cross-sectional view of a semiconductor memory device according to an embodiment of the present invention.

[0121] 16, the memory device 1400 may have a C2C (chip to chip) structure. The C2C structure may refer to fabricating an upper chip including a cell array structure CELL on a first wafer, fabricating a lower chip including a peripheral circuit structure PERI on a second wafer different from the first wafer, and then connecting the upper and lower chips to each other by a bonding method. For example, the bonding method may refer to a method of electrically connecting a bonding metal formed on the top metal layer of the upper chip to a bonding metal formed on the top metal layer of the lower chip. For example, if the bonding metal is formed of copper (Cu), the bonding method is Cu-to-Cu bonding, and the bonding metal may also be formed of aluminum (Al) or tungsten (W).

[0122] Each of the peripheral circuit structure PERI and the cell array structure CELL of the memory device 1400 may include an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA.

[0123] The peripheral circuit structure PERI may include a first substrate 1210, an interlayer insulating layer 1215, a plurality of circuit elements 1220a, 1220b, and 1220c formed on the first substrate 1210, first metal layers 1230a, 1230b, and 1230c connected to each of the plurality of circuit elements 1220a, 1220b, and 1220c, and second metal layers LT1, 1240b, and 1240c formed on the first metal layers 1230a, 1230b, and 1230c. In one embodiment, the first metal layers 1230a, 1230b, and 1230c may be formed of tungsten, which has a relatively high electrical resistivity, and the second metal layers LT1, 1240b, and 1240c may be formed of copper, which has a relatively low electrical resistivity.

[0124] Although only the first metal layers 1230a, 1230b, and 1230c and the second metal layers LT1, 1240b, and 1240c are illustrated and described herein, this is not limiting, and at least one more metal layer may be formed on the second metal layers LT1, 1240b, and 1240c. At least a portion of the one or more metal layers formed on the second metal layers LT1, 1240b, and 1240c may be formed of aluminum or the like, which has a lower electrical resistivity than copper, which forms the second metal layers LT1, 1240b, and 1240c. The second metal layers LT1, 1240b, and 1240c include a first landing wire LT1. A mark pattern IP is disposed in the first landing wire LT1.

[0125] The interlayer insulating layer 1215 is disposed on the first substrate 1210 to cover the plurality of circuit elements 1220a, 1220b, 1220c, the first metal layers 1230a, 1230b, 1230c, and the second metal layers LT1, 1240b, 1240c, and may include an insulating material such as silicon oxide, silicon nitride, etc.

[0126] Lower bonding metals 1271b and 1272b may be formed on the second metal layer 1240b in the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 1271b and 1272b of the peripheral circuit structure PERI may be electrically connected to the upper bonding metals 1371b and 1372b of the cell array structure CELL by bonding, and the lower bonding metals 1271b and 1272b and the upper bonding metals 1371b and 1372b may be formed of aluminum, copper, tungsten, or the like. The upper bonding metals 1371b and 1372b may also be referred to as upper bonding pads. The lower bonding metals 1271b and 1272b may also be referred to as lower bonding pads.

[0127] The cell array structure CELL may correspond to the cell array structure CS described with reference to FIG. 14. The cell array structure CELL may provide at least one memory block. The cell array structure CELL may include a second substrate 1310 and a common source line 1320. A plurality of word lines 1331-1338; 1330 may be stacked on the second substrate 1310 along a direction (Z-axis direction) perpendicular to the top surface of the second substrate 1310. A string selection line and a ground selection line may be disposed above and below the word line 1330, respectively, and a plurality of word lines 1330 may be disposed between the string selection line and the ground selection line.

[0128] In the bit line bonding region BLBA, a channel structure CH may extend in a direction perpendicular to the top surface of the second substrate 1310 (Z-axis direction) and penetrate the word lines 1330, the string select lines, and the ground select lines. The channel structure CH may include a data storage layer, a channel layer, a buried insulating layer, etc., and the channel layer may be electrically connected to the first metal layer 1350c and the second metal layer 1360c. For example, the first metal layer 1350c may be a bit line contact, and the second metal layer 1360c may be a bit line. In one embodiment, the bit line 1360c may extend along a first direction (Y-axis direction) parallel to the top surface of the second substrate 1310.

[0129] 16, a region where the channel structure CH and the bit line 1360c are arranged may be defined as a bit line bonding region BLBA. The bit line 1360c may be electrically connected to circuit elements 1220c that provide a page buffer 1393 in the peripheral circuit structure PERI in the bit line bonding region BLBA. For example, the bit line 1360c may be connected to upper bonding metals 1371c and 1372c in the peripheral circuit structure PERI, and the upper bonding metals 1371c and 1372c may be connected to lower bonding metals 1271c and 1272c that are connected to circuit elements 1220c of the page buffer 1393.

[0130] In the word line bonding region WLBA, the word lines 1330 may extend along a second direction (X-axis direction) that is perpendicular to the first direction and parallel to the top surface of the second substrate 1310, and may be connected to a plurality of cell contact plugs (1341-1347; 1340). The shape of the cell contact plugs 1341-1347; 1340 may be the same as the cell contacts CC of FIG.

[0131] The word lines 1330 and the cell contact plugs 1340 may be connected to each other through pads, at least some of which extend to different lengths in the word lines 1330 in the second direction. A first metal layer 1350b and a second metal layer 1360b may be sequentially connected to the upper part of the cell contact plug 1340 connected to the word line 1330. The cell contact plug 1340 may be connected to the peripheral circuit structure PERI in the word line bonding region WLBA through upper bonding metals 1371b and 1372b of the cell region CELL and lower bonding metals 1271b and 1272b of the peripheral circuit structure PERI.

[0132] The cell contact plug 1340 may be electrically connected to a circuit element 1220b forming a row decoder 1394 in the peripheral circuit structure PERI. In one embodiment, the operating voltage of the circuit element 1220b forming the row decoder 1394 may be different from the operating voltage of the circuit element 1220c forming the page buffer 1393. For example, the operating voltage of the circuit element 1220c forming the page buffer 1393 may be higher than the operating voltage of the circuit element 1220b forming the row decoder 1394.

[0133] A common source line contact plug 1380 may be disposed in the external pad bonding region PA. The common source line contact plug 1380 may be formed of a conductive material such as metal, metal compound, or polysilicon and may be electrically connected to the common source line 1320. A first metal layer 1350a and a second metal layer 1360a may be sequentially stacked on the common source line contact plug 1380. For example, the region where the common source line contact plug 1380, the first metal layer 1350a, and the second metal layer 1360a are disposed may be defined as the external pad bonding region PA.

[0134] 16, a lower insulating film 1201 covering the lower surface of the first substrate 1210 may be formed under the first substrate 1210, and a first I / O pad 1205 may be formed on the lower insulating film 1201. The first I / O pad 1205 may be connected to at least one of a plurality of circuit elements 1220a, 1220b, and 1220c disposed in the peripheral circuit structure PERI through a first through via TV1 and may be separated from the first substrate 1210 by the lower insulating film 1201. In addition, a side insulating film may be disposed between the first through via TV1 and the first substrate 1210, thereby electrically separating the first through via TV1 and the first substrate 1210.

[0135] 16, an upper insulating film 1301 covering the upper surface of the second substrate 1310 may be formed on the upper surface of the second substrate 1310, and a second I / O pad 1305 may be disposed on the upper insulating film 1301. The second I / O pad 1305 may be connected to at least one of a plurality of circuit elements 1220a, 1220b, and 1220c disposed in the peripheral circuit structure PERI through a second I / O contact plug 1303. In one embodiment, the second I / O pad 1305 may be electrically connected to the circuit element 1220a.

[0136] According to an embodiment, the second substrate 1310 and the common source line 1320 may not be arranged in the region where the second I / O contact plug 1303 is arranged. Also, the second I / O pad 1305 may not overlap with the word line 1380 in the third direction (Z-axis direction). Referring to FIG. 16, the second I / O contact plug 1303 may be separated from the second substrate 1310 in a direction parallel to the top surface of the second substrate 1310 and connected to the second I / O pad 1305 through an interlayer insulating layer 1315 of the cell array structure CELL.

[0137] Depending on the embodiment, the first I / O pads 1205 and the second I / O pads 1305 may be selectively formed. For example, the memory device 1400 may include only the first I / O pads 1205 disposed on the top of the first substrate 1210, or only the second I / O pads 1305 disposed on the top of the second substrate 1310. Alternatively, the memory device 1400 may include both the first I / O pads 1205 and the second I / O pads 1305.

[0138] In each of the external pad bonding area PA and the bit line bonding area BLBA included in each of the cell array structure CELL and the peripheral circuit area PERI, the metal pattern of the top metal layer may exist as a dummy pattern, or the top metal layer may be empty.

[0139] In the memory device 1400, a lower metal pattern 1273a having the same shape as the upper metal pattern 1372a of the cell array structure CELL may be formed in the uppermost metal layer of the peripheral circuit structure PERI in the external pad bonding region PA, corresponding to the upper metal pattern 1372a formed in the uppermost metal layer of the cell array structure CELL. The lower metal pattern 1273a formed in the uppermost metal layer of the peripheral circuit structure PERI may not be connected to another contact in the peripheral circuit structure PERI. Similarly, an upper metal pattern 1372a having the same shape as the lower metal pattern 1273a of the peripheral circuit structure PERI may be formed in the upper metal layer of the cell array structure CELL in the external pad bonding region PA, corresponding to the lower metal pattern 1273a formed in the uppermost metal layer of the peripheral circuit structure PERI.

[0140] Lower bonding metals 1271b and 1272b may be formed on the second metal layer 1240b in the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 1271b and 1272b of the peripheral circuit structure PERI may be electrically connected to the upper bonding metals 1371b and 1372b of the cell array structure CELL by bonding.

[0141] In addition, in the bit line bonding region BLBA, an upper metal pattern 1392 having the same shape as the lower metal pattern 1252 of the peripheral circuit structure PER1 may be formed in the uppermost metal layer of the cell array structure CELL in correspondence with the lower metal pattern 1252 formed in the uppermost metal layer of the peripheral circuit structure PER1. A contact may not be formed on the upper metal pattern 1392 formed in the uppermost metal layer of the cell array structure CELL.

[0142] Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art will understand that the present invention may be embodied in other specific forms without changing the technical spirit or essential characteristics thereof. Therefore, it should be understood that the above-described embodiments are illustrative in all respects and are not limiting. The embodiments of Figures 3 to 16 may be combined with each other. [Explanation of symbols]

[0143] 1000 image sensors 11, 21 Via insulating film BL1, BL2 lower insulating film BT 1st Optical Black Pattern CF1, CF2 color filters CFB 2nd optical black pattern CH1, CH2, CH3 semiconductor chips CP1, CP2, CP3, CP4 bonding pads CT1, CT2 contact plugs DTI deep isolation FD Floating diffusion region FL fixed charge membrane IL1, IL2, IL3 interlayer insulating films IP, IP1, IP2 mark patterns IT1, IT2, IT3, IT4 wiring LT1, LT2 landing wiring ML Micro Lens MLR lens residual layer PRT1, PRT2 peripheral transistors PX pixels RT1, RT2, RT3 Through via areas SB1, SB2, SB3 boards ST1, ST2 isolation section TG Transfer Gate TH1 through via hole TV1, TV2 through via WG Light-blocking grid pattern

Claims

1. a first semiconductor chip including a first substrate, a first interlayer insulating film covering the first substrate, and a first wiring and a first landing wiring disposed within the first interlayer insulating film; a second semiconductor chip including a second substrate including a plurality of light receiving regions, a second interlayer insulating film covering the second substrate, and second wiring disposed in the second interlayer insulating film, the second semiconductor chip being disposed on the first semiconductor chip; a first through via that penetrates the first substrate and contacts the first landing wiring; and at least one first mark pattern disposed in the first landing wiring and overlapping the first through via.

2. The image sensor of claim 1 , wherein the first mark pattern contacts the first through via.

3. The image sensor of claim 1 , wherein a portion of the first through via is inserted into the first landing wire and contacts an inner sidewall of the first landing wire.

4. the first semiconductor chip further includes a first lower insulating film covering a lower surface of the first substrate, and a first bonding pad disposed in the first lower insulating film and in contact with the first through via; the image sensor further includes a third semiconductor chip disposed below the first semiconductor chip; 2. The image sensor of claim 1, wherein the third semiconductor chip includes a third substrate, a third interlayer insulating film covering the third substrate and contacting the first lower insulating film, a third wiring disposed within the third interlayer insulating film, and a second bonding pad disposed on an upper end of the third interlayer insulating film and contacting the first bonding pad.

5. the second interlayer insulating film is disposed under the second substrate and in contact with an upper surface of the first interlayer insulating film; the second semiconductor chip further includes a transfer gate disposed on the lower surface of the second substrate in each of the light receiving regions, and a floating diffusion region disposed in the second substrate beside the transfer gate; the first semiconductor chip further includes a source follower gate disposed on the first substrate; 2. The image sensor of claim 1, wherein a portion of the first wiring and a portion of the second wiring connect the floating diffusion region to the source follower gate.

6. the first semiconductor chip further includes a second landing wire disposed in the first interlayer insulating film and spaced apart from the first landing wire; the second interlayer insulating film is disposed under the second substrate and in contact with an upper surface of the first interlayer insulating film; the second substrate includes a main region and an edge region; The second semiconductor chip a deep isolation region disposed in the second substrate and isolating the light receiving regions; a color filter array disposed on the second substrate; a microlens array disposed over the color filter array; The image sensor a second through via that penetrates the second substrate, the second interlayer insulating film, and a portion of the first interlayer insulating film in the edge region and contacts the second landing wiring; The image sensor of claim 1 , further comprising: at least one second mark pattern disposed within the second landing wire.

7. The deep separation portion is a separated conductive pattern; an isolation insulating film interposed between the isolation conductive pattern and the second substrate, The second semiconductor chip is a back contact pattern penetrating a portion of the second substrate and a portion of the deep isolation portion at the edge region and contacting the isolation conductive pattern; The image sensor of claim 6 , further comprising a backside wiring disposed on the second substrate and connecting the backside contact pattern to the second through via.

8. the second interlayer insulating film is disposed under the second substrate; The first semiconductor chip an upper insulating film disposed on the first substrate and in contact with a lower surface of the second interlayer insulating film; a source follower gate disposed below the first substrate; a first bonding pad disposed on an upper end of the upper insulating film and connected to the first through via; The image sensor of claim 1 , wherein the second semiconductor chip further comprises a second bonding pad disposed on a lower end of the second interlayer insulating film and in contact with the first bonding pad.

9. The image sensor of claim 1 , wherein the first mark pattern includes a material different from that of the first landing line.

10. a first semiconductor chip including a first substrate, a first interlayer insulating film covering the first substrate, and a first wiring and a first landing wiring disposed in the first interlayer insulating film; a second semiconductor chip including a second substrate including a plurality of light receiving regions, a second interlayer insulating film covering the second substrate, and second wiring disposed in the second interlayer insulating film, the second semiconductor chip being disposed on the first semiconductor chip; a first through via that penetrates the first substrate and contacts the first landing wiring; the first landing wiring includes a pad portion in contact with the first through via; The pad portion has a cross shape or a line shape in a plan view, The first through via covers both the top and side surfaces of the pad portion of the image sensor.

11. further including at least one first mark pattern disposed in the first landing wiring and overlapping the first through via; the first mark pattern is in contact with the first through via; The image sensor of claim 10 , wherein a portion of the first through via is inserted into the first landing wire and contacts an inner sidewall of the first landing wire.

12. the first semiconductor chip further includes a first lower insulating film covering a lower surface of the first substrate, and a first bonding pad disposed in the first lower insulating film and in contact with the first through via; the image sensor further includes a third semiconductor chip disposed below the first semiconductor chip; 11. The image sensor of claim 10, wherein the third semiconductor chip includes a third substrate, a third interlayer insulating film covering the third substrate and contacting the first lower insulating film, a third wiring disposed within the third interlayer insulating film, and a second bonding pad disposed on an upper end of the third interlayer insulating film and contacting the first bonding pad.

13. the second interlayer insulating film is disposed under the second substrate and in contact with an upper surface of the first interlayer insulating film; the second semiconductor chip further includes a transfer gate disposed on the lower surface of the second substrate in each of the light receiving regions, and a floating diffusion region disposed in the second substrate beside the transfer gate; the first semiconductor chip includes a source follower gate disposed on the first substrate; 11. The image sensor of claim 10, wherein a portion of the first wiring and a portion of the second wiring connect the floating diffusion region to the source follower gate.

14. the first semiconductor chip further includes a second landing wire spaced apart from the first landing wire; the second interlayer insulating film is disposed under the second substrate and in contact with an upper surface of the first interlayer insulating film; the second substrate includes a main region and an edge region; The second semiconductor chip is a deep isolation region disposed in the second substrate and isolating the light receiving regions; a color filter array disposed on the second substrate; a microlens array disposed over the color filter array; The image sensor a second through via that penetrates the second substrate, the second interlayer insulating film, and a portion of the first interlayer insulating film in the edge region and contacts the second landing wiring; The image sensor of claim 10 , further comprising: at least one second mark pattern disposed within the second landing wire.

15. The deep separation portion is a separated conductive pattern; an isolation insulating film interposed between the isolation conductive pattern and the second substrate, The second semiconductor chip is a back contact pattern penetrating a portion of the second substrate and a portion of the deep isolation portion at the edge region and contacting the isolation conductive pattern; The image sensor of claim 14 , further comprising a backside wiring disposed on the second substrate and connecting the backside contact pattern to the second through via.

16. the second interlayer insulating film is disposed under the second substrate; The first semiconductor chip an upper insulating film disposed on the first substrate and in contact with a lower surface of the second interlayer insulating film; a source follower gate disposed below the first substrate; a first bonding pad disposed on an upper end of the upper insulating film and connected to the first through via; 11. The image sensor of claim 10, wherein the second semiconductor chip further comprises a second bonding pad disposed on a lower end of the second interlayer insulating film and in contact with the first bonding pad.

17. a first semiconductor chip including a first substrate, a first interlayer insulating film covering the first substrate, and a first wiring and a first landing wiring disposed within the first interlayer insulating film; a second semiconductor chip including a second substrate, a second interlayer insulating film covering the second substrate, and second wiring disposed within the second interlayer insulating film, the second semiconductor chip being disposed on the first semiconductor chip; a first through via that penetrates the first substrate and contacts the first landing wiring; and at least one first mark pattern disposed in the first landing wiring and overlapping the first through via.

18. The semiconductor device of claim 17 , wherein a portion of the first through via is inserted into the first landing wire and contacts an inner sidewall of the first landing wire.

19. the first interlayer insulating film covers an upper surface of the first substrate; the second interlayer insulating film covers a lower surface of the second substrate; the first semiconductor chip further includes a first bonding pad disposed on an upper end of the first interlayer insulating film; 18. The semiconductor device of claim 17, wherein the second semiconductor chip further comprises a second bonding pad disposed on a lower end of the second interlayer insulating film and in contact with the first bonding pad.

20. the second semiconductor chip further includes an electrode layer disposed under the second substrate and a vertical pattern penetrating the electrode layer; The semiconductor device of claim 17 , wherein the first semiconductor chip further comprises a plurality of transistors electrically connected to the electrode layer.

Images