Integrated circuit and power supply circuit

Abstract

To provide an integrated circuit that can further reduce power consumption.SOLUTION: An integrated circuit includes a first terminal to which an external circuit that sets the operating mode is connected, and a mode selection circuit that selects whether the integrated circuit is to operate in a shutdown mode in which no switching operation is performed, a normal mode in which continuous switching operation is performed, or a low standby power mode in which switching operation periods and shutdown operation periods are alternately repeated on the basis of the voltage level of the first terminal, and the mode selection circuit operates the integrated circuit in the shutdown mode when the voltage level of the first terminal is in a first voltage range, operates the integrated circuit in the normal mode when the voltage level is in a second voltage range different from the first voltage range, and operates the integrated circuit in the low standby power mode when the voltage level is in a third voltage range different from the first and second voltage ranges.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to an integrated circuit and a power supply circuit. [Background technology]

[0002] There are integrated circuits that control power supply circuits (for example, Patent Documents 1 to 7). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-110173 [Patent Document 2] Japanese Patent Application Laid-Open No. 2013-038857 [Patent Document 3] Japanese Patent Application Laid-Open No. 2014-230377 [Patent Document 4] Japanese Patent Application Laid-Open No. 2016-111758 [Patent Document 5] Japanese Patent Application Publication No. 2017-017767 [Patent Document 6] Japanese Patent Application Laid-Open No. 2017-060329 [Patent Document 7] Japanese Patent Application Laid-Open No. 2017-127109 Summary of the Invention [Problem to be solved by the invention]

[0004] Incidentally, some integrated circuits change their operating mode depending on the load state of the power supply circuit.

[0005] In such integrated circuits, a load detection circuit that detects the load state is generally always active, so even if the load becomes unloaded, the integrated circuit continues to consume a certain amount of power, making it difficult to reduce the power consumption of the integrated circuit.

[0006] The present invention has been made in view of the above-mentioned problems in the prior art, and has an object to provide an integrated circuit that can further reduce power consumption. [Means for solving the problem]

[0007] A first aspect of the integrated circuit of the present invention, which is a main aspect of solving the above-mentioned problems, is an integrated circuit that drives a transistor of a power supply circuit to cause the power supply circuit to generate an output voltage of a target level, and includes: a first terminal to which a first switch that turns on and off based on an instruction signal that indicates an operating mode of the integrated circuit is connected; a first determination circuit that determines, based on the voltage level of the first terminal, whether the integrated circuit should operate in a first mode or a second mode that consumes more power than the first mode; a first power supply voltage generation circuit that stops generating a first power supply voltage when the integrated circuit is to operate in the first mode, and generates the first power supply voltage when the integrated circuit is to operate in the second mode; and a drive circuit that is supplied with the first power supply voltage and drives the transistor.

[0008] The main power supply circuit of the present invention that solves the above-mentioned problems is a power supply circuit that generates an output voltage at a target level, and includes a transistor, an integrated circuit that drives the transistor, and a first switch that turns on and off based on an instruction signal that indicates an operating mode of the integrated circuit, wherein the integrated circuit includes a first terminal to which the first switch is connected, a first determination circuit that determines, based on the voltage level of the first terminal, whether the integrated circuit should operate in a first mode or a second mode that consumes more power than the first mode, a first power supply voltage generation circuit that stops generating a first power supply voltage when the integrated circuit is to operate in the first mode, and generates the first power supply voltage when the integrated circuit is to operate in the second mode, and a drive circuit that is supplied with the first power supply voltage and drives the transistor.

[0009] A second aspect of the integrated circuit of the present invention, which is primarily intended to solve the above-mentioned problems, is an integrated circuit that switches on and drives a power transistor of a power supply circuit in order to cause the power supply circuit to generate an output voltage of a target level, and includes: a first terminal to which an external circuit that sets an operation mode of the integrated circuit is connected; and a mode selection circuit that selects, based on the voltage level of the first terminal, whether to operate the integrated circuit in a shut-off mode in which no switching operation is performed, a normal mode in which continuous switching operation is performed, or a low standby power mode in which periods of switching operation and periods of switching stop are alternately repeated. [Effects of the Invention]

[0010] According to the present invention, it is possible to provide an integrated circuit that can further reduce power consumption. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a diagram illustrating an example of a power supply device 10. FIG. [Figure 2] FIG. 2 is a diagram illustrating an overview of an AC-DC converter 12. [Figure 3] FIG. 2 is a diagram illustrating an example of a DC-DC converter 13. [Figure 4] FIG. 2 is a diagram illustrating an example of a control IC 50. [Figure 5] FIG. 2 is a diagram illustrating an example of a setting circuit 76. [Figure 6] 10 is a diagram showing the relationship between the resistance value of a resistor Rstb and a method for switching the drive pattern of a control IC 50. FIG. [Figure 7] FIG. 10 is a diagram showing an example of drive signals Vdr1 and Vdr2 in the "normal mode." [Figure 8] FIG. 10 is a diagram showing an example of drive signals Vdr1 and Vdr2 in a "low standby power mode." [Figure 9] FIG. 2 is a diagram illustrating an example of an interface (IF) circuit 18a. [Figure 10] 10 is a diagram showing the relationship between the logic levels of the signals Wakeup and ExtSTB and the voltage Vstb. FIG. [Figure 11] 10 is a diagram showing the relationship between the logic levels of the signals Wakeup and ExtSTB and the operation modes of the control IC 50. FIG. [Figure 12] FIG. 2 is a diagram illustrating an example of a power factor correction circuit 22. [Figure 13] FIG. 1 is a diagram illustrating an example of a power factor correction IC 175. [Figure 14] FIG. 4 is a diagram illustrating an example of the operation of the control IC 50. [Figure 15] FIG. 10 is a diagram illustrating an example of an interface (IF) circuit 18b. [Figure 16] FIG. 10 is a diagram showing the relationship between the logic level of a signal Wakeup and a voltage Vstb. [Figure 17] 10 is a diagram showing the relationship between the logic level of the signal Wakeup and the operation modes of the control IC 50 and the power factor correction IC 155. FIG. [Figure 18] FIG. 10 is a diagram illustrating an example of the operation of the control IC 50 and the power factor correction IC 175. DETAILED DESCRIPTION OF THE INVENTION

[0012] At least the following matters will become clear from the description of this specification and the accompanying drawings.

[0013] =====This embodiment===== <<<Outline of Power Supply Unit 10>>> 1 is a diagram showing an example of a power supply device 10. The power supply device 10 is a device incorporated into, for example, a television, generates an output voltage Vout2 from a commercial AC voltage Vac, and supplies power to a predetermined load 14. The power supply device 10 is composed of a switch 11, an AC-DC converter 12, a DC-DC converter 13, a microcontroller (MCU) 15a, a capacitor 16, a photodiode 17, and an interface (IF) circuit 18a. The switch 11 is provided between a node N2 and a node N3, and is turned on and off by a signal SW_sig from the microcontroller 15a.

[0014] When the switch 11 is turned on, the AC-DC converter 12 generates the output voltage Vout1 from the AC voltage Vac applied to the nodes N1 and N2. On the other hand, when the switch 11 is turned off, the AC-DC converter 12 does not generate the output voltage Vout1 because the AC voltage Vac is not applied.

[0015] The DC-DC converter 13 generates an output voltage Vout2 from the output voltage Vout1 applied to nodes N4 and N5. The load 14 is connected to nodes N6 and N7, and operates by receiving the output voltage Vout2 and a load current Iout. The load 14 is, for example, an electronic device included in a television that operates on a DC voltage. Here, "connected" refers to an electrically connected state unless otherwise specified, and includes a case where the load is connected via a resistor.

[0016] The microcontroller 15a controls the power supply device 10 based on instructions from a user. The microcontroller 15a operates by receiving a voltage Vdd from a power supply circuit (not shown) that operates based on a commercial AC voltage Vac, and a capacitor 16 is provided between the terminal VDD and ground to stabilize the voltage Vdd.

[0017] Photodiode 17 is provided between terminal RCV and ground and receives, for example, an infrared signal from a television remote control (not shown). Microcontroller 15a controls the operations of power supply device 10 and various devices (not shown) of the television based on the signal received by photodiode 17.

[0018] Furthermore, when the photodiode 17 receives a signal transmitted from the remote control to turn on the load 14, the microcontroller 15a sends a signal SW_sig to turn on the switch 11, which functions as a relay. As a result, the switch 11 is turned on, and the AC voltage Vac is applied to the AC-DC converter 12. Thereafter, the AC-DC converter 12 generates the output voltage Vout1.

[0019] Also, at this time, the microcontroller 15a outputs a signal Wakeup for starting the DC-DC converter 13 to the interface circuit 18a.

[0020] Then, the DC-DC converter 13 starts based on the voltage Vstb from the interface circuit 18a and supplies power to the load 14. Note that the microcontroller 15a also outputs a signal ExtSTB for changing the operation mode of the DC-DC converter 13 in a predetermined case, and the details will be described later.

[0021] On the other hand, when the microcontroller 15a receives a signal transmitted from the remote control for the photodiode 17 to turn off the load 14, it sends a signal SW_sig for turning off the switch 11. As a result, since the switch 11 is turned off, the supply of the AC voltage Vac to the AC-DC converter 12 is stopped.

[0022] Also, at this time, the microcontroller 15a outputs a signal Wakeup for stopping the DC-DC converter 13 to the interface circuit 18a. As a result, the interface circuit 18a generates a voltage Vstb at a level higher than a predetermined level, although the details will be described later. Also, the DC-DC converter 13 stops generating the output voltage Vout2 upon receiving the voltage Vstb, stops supplying power to the load 14, the load current Iout flowing through the load 14 becomes zero, and the load 14 is in a so-called no-load state.

[0023] Also, the interface circuit 18a realizes a change in the operation of the control IC50 and a cooperation function between the control IC50 and the power factor correction IC175 according to the signal Wakeup and the signal ExtSTB from the microcontroller 15a. Note that the details of the interface circuit 18a will be described later. Also, the interface circuit 18a corresponds to an "external circuit".

[0024] <<<Overview of the AC-DC Converter>>> FIG. 2 is a diagram showing the configuration of the AC-DC converter 12 included in the power supply device 10 of the present invention. The AC-DC converter 12 is a power supply circuit that generates an output voltage Vout1 at a target level from the AC voltage Vac of a commercial power supply.

[0025] The AC-DC converter 12 is configured to include diodes 20, 21 and a power factor correction circuit 22. The diodes 20, 21 full-wave rectify the AC voltage Vac from the nodes N1, N3 and apply it as a rectified voltage Vrec1 to a control IC 50 described later.

[0026] The power factor correction circuit 22 generates an output voltage Vout1 at a target level from the AC voltage Vac of the commercial power supply based on the voltage Sig from the interface circuit 18a and applies it to the nodes N4, N5. Details of the power factor correction circuit 22 will be described later.

[0027] <<<Overview of the DC-DC converter 13>>> FIG. 3 is a diagram showing the configuration of the DC-DC converter 13 included in the power supply device 10 of the present invention. The DC-DC converter 13 is an LLC current resonant type power supply circuit that generates an output voltage Vout2 at a target level (for example, 15V) for a load 14 from a predetermined input voltage Vout1 (for example, 400V).

[0028] The DC-DC converter 13 is configured to include capacitors 30, 31, 42, NMOS transistors 32, 33, a transformer 34, a control block 35, diodes 40, 41, a constant voltage circuit 43, and a light emitting diode 44.

[0029] The capacitor 30 stabilizes the voltage between the power supply line to which the input voltage Vout1 is applied and the ground line on the ground side and removes noise and the like. The input voltage Vout1 is a DC voltage at a predetermined level.

[0030] The NMOS transistor 32 is a high-side power transistor, and the NMOS transistor 33 is a low-side power transistor. In this embodiment, the NMOS transistors 32 and 33 are used as switching elements, but they may also be PMOS transistors or bipolar transistors, for example.

[0031] The transformer 34 includes a primary coil L1, secondary coils L2 and L3, and an auxiliary coil L4, and the primary coil L1, secondary coils L2 and L3, and auxiliary coil L3 are insulated from each other. In the transformer 34, a voltage is generated in the secondary coils L2 and L3 on the secondary side in response to a change in the voltage across the primary coil L1 on the primary side, and a voltage is generated in the auxiliary coil L4 on the primary side in response to a change in the voltage across the secondary coils L2 and L3.

[0032] The primary coil L1 has one end connected to the source of the NMOS transistor 32 and the drain of the NMOS transistor 33, and the other end connected to the source of the NMOS transistor 33 via the capacitor 31.

[0033] Therefore, when switching of the NMOS transistors 32 and 33 starts, the voltages of the secondary coils L2 and L3 and the auxiliary coil L4 change. The primary coil L1 and the secondary coils L2 and L3 are electromagnetically coupled with the same polarity, and the secondary coils L2 and L3 and the auxiliary coil L4 are also electromagnetically coupled with the same polarity.

[0034] The control block 35 is a circuit block for controlling the switching of the NMOS transistors 32 and 33, and will be described in detail later.

[0035] The diodes 40 and 41 rectify the voltages of the secondary coils L2 and L3, and the capacitor 42 smoothes the rectified voltage. As a result, a smoothed output voltage Vout2 is generated in the capacitor 42. The output voltage Vout2 is a DC voltage at a target level.

[0036] The constant voltage circuit 43 is a circuit that generates a constant DC voltage, and is configured using, for example, a shunt regulator.

[0037] The light-emitting diode 44 is an element that emits light with an intensity corresponding to the difference between the output voltage Vout2 and the output of the constant voltage circuit 43, and together with a phototransistor 62 (described later), forms a photocoupler. In this embodiment, as the level of the output voltage Vout2 increases, the intensity of the light emitted from the light-emitting diode 44 increases.

[0038] ===Control Block 35=== The control block 35 includes a control IC 50, a diode 60, capacitors 61, 63, 64, 67, 68, and 154, a phototransistor 62, and resistors 65 and 66.

[0039] The control IC 50 is an integrated circuit that controls the switching of the NMOS transistors 32 and 33 in accordance with the state of a terminal STB, which will be described later, and has terminals VCC, GND, STB, REG, FB, IS, CA, HO, LO, and VH.

[0040] The terminal VCC is a terminal to which a voltage Vcc is applied to operate the control IC 50. The terminal VCC is connected to the cathode of a diode 60 and a capacitor 61, one end of which is grounded. Therefore, the capacitor 61 is charged by a current from a start-up circuit 70 (described later) of the control IC 50 or a current from the diode 60, and the charging voltage of the capacitor 61 becomes the voltage Vcc that operates the control IC 50.

[0041] The terminal GND is a terminal to which a ground voltage is applied, and is connected to, for example, the housing of the device in which the power supply device 10 is installed.

[0042] The terminal STB is a terminal for receiving a voltage generated by the interface circuit 18a or for the control IC 50 to output a signal to a power factor correction IC 175, which will be described later in detail.

[0043] The terminal REG is a terminal that outputs the output voltage of an internal power supply (REG1) 92 (described later) built into the control IC 50. Note that, as will be described in detail later, a capacitor 154 is provided between the terminal REG and ground to stabilize the output voltage of the internal power supply 92, as shown in FIG.

[0044] The terminal FB is a terminal at which a feedback voltage Vfb_a corresponding to the output voltage Vout2 is generated, and is connected to a phototransistor 62 and a capacitor 63. The phototransistor 62 passes a bias current I1, the magnitude of which corresponds to the intensity of light from the light-emitting diode 44, from the terminal FB to ground, and the capacitor 63 is provided to remove noise between the terminal FB and ground. Therefore, the phototransistor 62 operates as a transistor that generates a sink current.

[0045] Terminal IS is a terminal to which a voltage corresponding to the resonant current of DC-DC converter 13 is applied. Here, a voltage corresponding to the current value of the resonant current of primary coil L1 is generated at the node to which capacitor 64 and resistor 65 are connected. Resistor 66 and capacitor 67 form a low-pass filter. Therefore, a voltage from which noise components have been removed is applied to terminal IS according to the current value of the resonant current of primary coil L1.

[0046] The current value of the resonant current increases in accordance with the input power of DC-DC converter 13, and the input power of DC-DC converter 13 increases in accordance with the power consumed by load 14. Therefore, the voltage applied to terminal IS indicates a voltage that corresponds to the power consumption of load 14.

[0047] Terminal CA applies to capacitor 68 a voltage that changes according to the voltage applied to terminal IS. Specifically, when the power consumption of load 14 increases, that is, when load 14 is in a heavy load state, the voltage applied to capacitor 68 increases. On the other hand, when the power consumption of load 14 decreases, that is, when load 14 is in a light load state, the voltage applied to capacitor 68 decreases.

[0048] Note that "load 14 is in a heavy load state" refers to, for example, a case where the current value of the load current Iout flowing through load 14 is greater than a predetermined value (for example, 1 A). Also, "load 14 is in a light load state" refers to, for example, a case where the current value of the load current Iout flowing through load 14 is smaller than a predetermined value (for example, 1 A).

[0049] The terminal VH is a terminal to which the rectified voltage Vrec1 is applied. The control IC 50 includes a startup circuit 70 (described later) that charges the voltage Vcc and starts the control IC 50 when the rectified voltage Vrec1 is applied via the terminal VH, and after being started, operates based on the voltage Vcc.

[0050] The terminal HO is a terminal from which a drive signal Vdr1 for driving the NMOS transistor 32 is output, and the gate of the NMOS transistor 32 is connected.

[0051] The terminal LO is a terminal from which a drive signal Vdr2 for driving the NMOS transistor 33 is output, and the gate of the NMOS transistor 33 is connected.

[0052] The terminal STB corresponds to the "first terminal", the terminal VH corresponds to the "second terminal", the terminal VCC corresponds to the "third terminal", and the terminal REG corresponds to the "fourth terminal".

[0053] <<<Details of Control IC50>>> 4 is a diagram showing the configuration of the control IC 50. The control IC 50 is an integrated circuit that controls an LLC current resonance type power supply circuit. The control IC 50 includes a start-up circuit 70, a current source 71, a Zener diode 72, a determination circuit 73, resistors 74 and 75, a setting circuit 76, a reset circuit (RESET) 90, an undervoltage protection circuit (UVLO) 91, an internal power supply (REG1) 92, an internal power supply (REG2) 93, a load detection circuit 100, an oscillation circuit 101, and a drive circuit 102. The determination circuit 73 corresponds to the "first determination circuit" or the "first mode determination circuit."

[0054] ===Start Circuit 70=== When the control IC 50 starts up, the start-up circuit 70 generates, based on the rectified voltage Vrec1, a power supply voltage Vcc for operating the control IC 50. Specifically, when the control IC 50 starts up, the start-up circuit 70 charges the capacitor 61 in Fig. 3 with a voltage generated from the rectified voltage Vrec1 applied via the terminal VH based on the voltage Vcc at the terminal VCC, thereby generating the voltage Vcc.

[0055] Furthermore, when the start-up of the control IC 50 is completed, the voltage Vcc becomes sufficiently high and the capacitor 61 begins to be charged by the current from the auxiliary coil L4, and the start-up circuit 70 stops charging the capacitor 61.

[0056] Here, "start-up" refers to the operation from when the AC voltage Vac is applied to the power supply device 10, when a signal rst1 (described later) that operates the digital circuit of the control IC 50 is output, until when a signal rst2 (described later) that starts switching is output.

[0057] The "start-up" of the control IC 50 includes the operations shown in steps (1) and (2) below. In step (1), after the AC voltage Vac is applied to the power supply device 10, a "state setting period" elapses during which various circuits of the control IC 50 are initialized. In step (2), after step (1) elapses, the start-up circuit 70 charges the capacitor 61, and sets the voltage Vcc to a level at which the control IC 50 starts switching the NMOS transistors 32 and 33 (for example, a predetermined level Vccon, which will be described later). Details of steps (1) and (2) will be described later. The start-up circuit 70 of this embodiment includes a constant voltage source 80, a control circuit 81, and a charging circuit 82.

[0058] <<Constant voltage source 80>> The constant voltage source 80 generates a constant voltage Vstartup (e.g., 30 V) based on the rectified voltage Vrec1. Specifically, the constant voltage source 80 generates the constant voltage Vstartup based on the rectified voltage Vrec1 applied via the terminal VH, regardless of the operation mode of the control IC 50.

[0059] Furthermore, while the rectified voltage Vrec1 is being applied to the terminal VH, the constant voltage source 80 applies the constant voltage Vstartup to the control circuit 81, the charging circuit 82, the current source 71, and the determination circuit 73. The constant voltage Vstartup corresponds to a "predetermined voltage."

[0060] <<Control circuit 81>> The control circuit 81 controls the charging circuit 82 to generate the voltage Vcc. The control circuit 81 also controls the charging circuit 82 during steps (1) to (2) when the control IC 50 is started up.

[0061] 3, when the determination circuit 73 outputs a signal Sb indicating that the switching of the NMOS transistors 32 and 33 should be started, the control circuit 81 outputs a signal Pon that controls the charging circuit 82 in accordance with the voltage value of the voltage Vcc. Hereinafter, the signal Sb indicating that the switching of the NMOS transistors 32 and 33 should be started will be referred to as the "signal Sb to be switched."

[0062] On the other hand, when the determination circuit 73 outputs a signal Sb indicating that the switching of the NMOS transistors 32 and 33 should be stopped, the control circuit 81 outputs a signal Pon to cause the charging circuit 82 to stop generating the voltage Vcc. The signal Sb indicating that the switching of the NMOS transistors 32 and 33 should be stopped is referred to as the "signal Sb indicating that switching should be stopped." Details of the signal Pon will be described later.

[0063] Here, during the state setting period, if the level of the voltage Vcc is lower than a predetermined level Vston (e.g., 9 V), the control circuit 81 outputs a signal Pon to the charging circuit 82 to charge the capacitor 61. On the other hand, if the level of the voltage Vcc reaches a predetermined level Vstoff (e.g., 10 V), the control circuit 81 outputs a signal Pon to the charging circuit 82 to stop charging the capacitor 61.

[0064] Furthermore, when the level of the voltage Vcc drops from the predetermined level Vstoff to the predetermined level Vston, the control circuit 81 again outputs the signal Pon to the charging circuit 82 to charge the capacitor 61. After that, when the state setting period is completed, the control circuit 81 outputs the signal Pon to the charging circuit 82 to charge the capacitor 61 until the level of the voltage Vcc reaches the predetermined level Vccon.

[0065] Then, when the startup of the control IC 50 is completed and the voltage Vcc level becomes sufficiently high and the capacitor 61 begins to be charged by the current from the auxiliary coil L4, the control circuit 81 outputs a signal Pon to the charging circuit 82 to stop charging the capacitor 61. After the signal Pon to stop charging the capacitor 61 is output to the charging circuit 82, the constant voltage source 80 no longer needs to supply the constant voltage Vstartup, and the current generated by generating this constant voltage Vstartup becomes almost zero. Therefore, the power consumption of the constant voltage source 80 is almost zero. Note that the capacitor 61 corresponds to the "first capacitor."

[0066] <<Charging circuit 82>> The charging circuit 82 operates based on the voltage Vstartup and charges the capacitor 61 via the terminal VCC to generate the voltage Vcc. Specifically, when the control circuit 81 outputs a signal Pon indicating that the capacitor 61 should be charged, the charging circuit 82 charges the capacitor 61 via the terminal VCC based on the voltage Vstartup. On the other hand, when the control circuit 81 outputs a signal Pon indicating that the charging of the capacitor 61 should be stopped, the charging circuit 82 stops charging the capacitor 61.

[0067] ===Current source 71=== The current source 71 is a circuit that generates a voltage at the terminal STB that corresponds to the state of the interface circuit 18a connected to the terminal STB. As will be described in detail later, the level of the voltage Vstb at the terminal STB allows the control IC 50 to operate in an operation mode that corresponds to a signal from the microcontroller 15a. The current source 71 of this embodiment supplies a current Ia to the terminal STB when the control IC 50 is in a predetermined state based on a signal Sa (described later) from the setting circuit 76. Specifically, when a signal Sa instructing the supply of the current Ia is input during a period other than the state setting period, the current source 71 supplies the current Ia to the terminal STB.

[0068] The current Ia is a current that charges a capacitor 150 in an interface circuit 18a shown in Fig. 9, which will be described later. When the microcontroller 15a outputs a signal Wakeup that stops the DC-DC converter 13, the level of the voltage Vstb generated in the capacitor 150 rises and becomes higher than a predetermined level Vstop (for example, 5.0 V).

[0069] On the other hand, when the microcontroller 15a outputs a signal Wakeup to operate the DC-DC converter 13, the capacitor 150 is discharged via a resistor 151 (described later) in FIG. 9, and the level of the voltage Vstb drops below the predetermined level Vstop. In this way, the level of the voltage Vstb at the terminal STB changes in accordance with the current Ia, allowing the control IC 50 to operate in accordance with instructions from the microcontroller 15a. The interface circuit 18a will be described in detail later.

[0070] ===Zener Diode 72=== The Zener diode 72 is provided between the terminal STB and ground, and functions to prevent (i.e., clamp) the level of the voltage Vstb of the terminal STB from exceeding a predetermined level (e.g., 5.9 V). The Zener diode 72 corresponds to a "clamp element."

[0071] ===Judgment circuit 73=== The determination circuit 73 determines whether the level of the voltage Vstb at the terminal STB exceeds a predetermined level Vstop for determining the operation mode of the control IC 50. Specifically, if the level of the voltage Vstb is lower than the predetermined level Vstop, the determination circuit 73 outputs a signal Sb to be switched. The operation mode of the control IC 50 in this case is referred to as the "conduction mode." When the control IC 50 operates in the "conduction mode," the control IC 50 switches the NMOS transistors 32 and 33 after step (2) described above.

[0072] On the other hand, when the level of the voltage Vstb becomes higher than the predetermined level Vstop, the determination circuit 73 outputs a signal Sb indicating that switching should be stopped. The operating mode of the control IC 50 in this case is referred to as the "shutdown mode." When the control IC 50 is in the "shutdown mode," the control IC 50 does not switch the NMOS transistors 32 and 33. The "conduction mode" corresponds to the "first mode," and the "shutdown mode" corresponds to the "second mode." The predetermined level Vstop corresponds to the "first voltage level."

[0073] ===Resistance 74,75=== Resistors 74 and 75 generate a voltage Vh from the rectified voltage Vrec1 to detect the effective value of the AC voltage Vac. Specifically, the resistors 74 and 75 are connected in series between the node to which the rectified voltage Vrec1 is applied and ground, and generate a voltage Vh at the connection point of the resistors 74 and 75.

[0074] ===Setting Circuit 76=== 5 is a diagram showing an example of the setting circuit 76. The setting circuit 76 outputs various signals for setting the operation of the control IC 50. Specifically, the setting circuit 76 outputs a signal Sa for causing the current source 71 to supply or stop supplying the current Ia.

[0075] Furthermore, when changing the drive pattern in "external mode" (described later), the setting circuit 76 detects a change in the level of the voltage Vstb and outputs a signal Sc to an oscillator circuit 101 (described later) to instruct the drive pattern of the NMOS transistors 32 and 33. The setting circuit 76 also outputs a signal Sd indicating the completion of the state setting period and a signal Se indicating a method for changing the drive pattern of the NMOS transistors 32 and 33. The setting circuit 76 is configured to include a digital section 110 configured with digital circuits (logic circuits) and an analog section 111 configured with analog circuits.

[0076] ====Digital Section 110==== The digital section 110 includes a control circuit 120 and a determination circuit 121 .

[0077] =====Control circuit 120===== The control circuit 120 controls the current source 71, the control circuit 81, the internal power supply 92 in Fig. 4, and various circuits in the analog unit 111 in Fig. 5. The control circuit 120 corresponds to the "control circuit."

[0078] =====Judgment circuit 121===== The determination circuit 121 determines the method for changing the drive pattern of the NMOS transistors 32 and 33 based on the signal from the control circuit 120 and the conversion result (digital value Dvstb) of an analog-to-digital converter (ADC) 132 (described later).

[0079] Furthermore, when the control circuit 120 outputs a signal S3 indicating the timing for acquiring the conversion result, the determination circuit 121 acquires a digital value Dvstb obtained by converting the voltage value of the voltage Vstb corresponding to the resistance value Rstb of the resistor 151 (described later) into a digital value. Then, the determination circuit 121 outputs a signal Se indicating whether the drive pattern should be changed in the "external mode" or the "internal mode" according to the digital value Dvstb.

[0080] Here, the "external mode" is a mode in which the comparator 134 described below judges the level of the voltage Vstb output by the interface circuit 18a in accordance with the logical level of the signal ExtSTB, and changes the drive pattern depending on whether it is higher than a predetermined level Vthstb described below.

[0081] On the other hand, the "internal mode" is a mode in which the drive pattern is changed based on the voltage Vca output by the load detection circuit 100 (described later), i.e., the state of the load 14. The determination circuit 121 corresponds to the "second determination circuit."

[0082] ====Analog Section 111==== The analog unit 111 is composed of analog circuits, and includes a discharge circuit 130, a current source 131, an analog-to-digital converter (ADC) 132, a clamp circuit 133, a comparator 134, and a communication circuit 135. During a state setting period, the discharge circuit 130, the current source 131, and the analog-to-digital converter 132 of the analog unit 111 operate to determine a method for changing the drive pattern of the NMOS transistors 32 and 33 in FIG. 3 based on a resistance value Rstb of a resistor 151 shown in FIG. 9, which will be described later.

[0083] =====Discharge circuit 130===== During the state setting period, the discharge circuit 130 discharges a capacitor 150 (described later) in FIG. 9 to accurately determine a voltage corresponding to the resistance value Rstb of the resistor 151. Specifically, when the control circuit 120 outputs a signal S1 for discharging the capacitor 150, the discharge circuit 130 discharges a terminal STB to which the capacitor 150 is connected. On the other hand, when the control circuit 120 outputs a signal S1 for stopping the discharge of the capacitor 150, the discharge circuit 130 stops the discharge of the terminal STB to which the capacitor 150 is connected.

[0084] =====Current source 131===== The current source 131 supplies a current Ib to the terminal STB in order to measure a resistance value Rstb of a resistor 151 shown in FIG. 9 (described later) for setting a method for changing a drive pattern. Specifically, when a signal S2 instructing the supply of the current Ib is output by the control circuit 120, the current source 131 supplies the current Ib to the resistor 151 via the terminal STB. This allows the control IC 50 to determine the resistance value Rstb of the resistor 151.

[0085] Furthermore, as will be described in more detail later, when the user sets the method of changing the drive pattern to "external mode," as shown in FIG. 6, the resistance value Rstb is set to the resistance value Ra, and when the user sets it to "internal mode," the resistance value Rstb is set to the resistance value Rb.

[0086] When the resistance value Rstb is equal to the resistance value Ra, the determination circuit 121 outputs a signal Se indicating that the drive pattern is to be changed in the "external mode." Furthermore, the signal Se indicating that the drive pattern is to be changed in the "external mode" is referred to as the "signal Se indicating the 'external mode'."

[0087] On the other hand, when the resistance value Rstb is the resistance value Rb, the determination circuit 121 outputs a signal Se indicating that the drive pattern is to be changed in the "internal mode." Furthermore, the signal Se indicating that the drive pattern is to be changed in the "internal mode" is referred to as the "signal Se indicating the 'internal mode'."

[0088] =====Analog-to-Digital Converter (ADC) 132===== The analog-to-digital converter (ADC) 132 converts the voltage value of the voltage Vstb into a digital value Dvstb. In this embodiment, the control circuit 120 outputs a signal S2 that instructs the supply of a current Ib, and outputs a signal S3 that indicates the timing at which the digital value Dvstb should be acquired. Thereafter, the determination circuit 121 outputs a signal Se based on the digital value Dvstb. At this time, the analog-to-digital converter 132 converts the voltage value of the voltage generated across the resistor 151 into a digital value Dvstb and outputs it to the determination circuit 121.

[0089] =====Clamp Circuit 133===== The clamp circuit 133 generates a voltage to maintain the level of the voltage Vstb at the terminal STB at a predetermined level Vnorm.

[0090] The clamp circuit 133 includes an operational amplifier 140, a PMOS transistor 141, and a resistor 142. When the level of a voltage Vstb input to the non-inverting input terminal is lower than a predetermined level Vnorm input to the inverting input terminal, the operational amplifier 140 drives the PMOS transistor 141 to reduce the on-resistance of the PMOS transistor 141.

[0091] On the other hand, when the level of voltage Vstb is higher than the predetermined level Vnorm, operational amplifier 140 drives PMOS transistor 141 to increase the on-resistance of PMOS transistor 141. Resistor 142 generates a voltage to set the level of voltage Vstb to the predetermined level Vnorm while limiting the current according to voltage Vreg2 and the on-resistance of PMOS transistor 141.

[0092] The drive capability of the clamp circuit 133 that drives the terminal STB is smaller than the drive capabilities of the discharge circuit 130 and the communication circuit 135 (described later). When these circuits are not operating and when no ground voltage is applied to the terminal STB from the outside, the clamp circuit 133 generates a voltage to set the level of the voltage Vstb to a predetermined level Vnorm.

[0093] =====Comparator 134===== The comparator 134 determines whether the control IC 50 should operate in the "normal mode" or the "low standby power mode" based on the signal ExtSTB from the microcontroller 15a.

[0094] Here, the "normal mode" is an operation mode in which the control IC 50 continuously switches on and off the NMOS transistors 32 and 33 as shown in FIG. 7 when the load state is not light.

[0095] On the other hand, the "low standby power mode" is an operation mode in which, when the load state is light, the control IC 50 performs switching in a so-called burst mode, in which a switching operation period in which the NMOS transistors 32 and 33 are continuously switched on and off and a stop operation period in which the switching is intermittently stopped, as shown in FIG. 8, are alternately repeated.

[0096] The "normal mode" and "low standby power mode" are modes that indicate the driving patterns of the NMOS transistors 32 and 33 when the control IC 50 operates in the "conducting mode."

[0097] Specifically, when a signal Se indicating the "external mode" is output, if the comparator 134 detects a voltage Vstb at a level higher than a predetermined level Vthstb, it outputs a signal Sc indicating the "normal mode" and causes the oscillator circuit 101, which will be described later, to output an oscillation signal Vosc that switches the NMOS transistors 32 and 33 in the "normal mode."

[0098] On the other hand, when the comparator 134 detects a voltage Vstb lower than the predetermined level Vthstb, it outputs a signal Sc indicating a "low standby power mode" and causes the oscillator circuit 101 to output an oscillation signal Vosc that switches the NMOS transistors 32 and 33 in the "low standby power mode." The comparator 134 corresponds to a "first signal output circuit" or a "second mode determination circuit," and the signal Sc corresponds to a "second signal." The predetermined level Vthstb corresponds to a "second voltage level," and the determination circuit 73 and the comparator 134 correspond to a "mode selection circuit."

[0099] =====Communication Circuit 135===== The communication circuit 135 outputs a pulse signal to the terminal STB to realize a linking function with the power factor correction IC 175. Specifically, in order to transmit the effective value of the AC voltage Vac to the power factor correction IC 175, the communication circuit 135 receives a voltage Vh for determining the effective value of the AC voltage Vac based on the rectified voltage Vrec1 applied to the terminal VH, and generates and outputs a pulse signal to the terminal STB based on this voltage Vh. The pulse signal has an amplitude level lower than a predetermined level Vstop and higher than a predetermined level Vthstb.

[0100] This operation is performed by the communication circuit 135 receiving the voltage Vh, generating a pulse signal indicating whether the effective value of the AC voltage Vac is high (e.g., 200 V) or low (e.g., 100 V), and outputting it to the power factor correction IC 175 via the interface circuit 18a (18b).

[0101] Furthermore, when a signal Se indicating the "internal mode" is output, the communication circuit 135 outputs a pulse signal having a pulse width according to the state of the load 14. The communication circuit 135 corresponds to the "second signal output circuit" or the "signal output circuit", and the pulse signal corresponds to the "third signal".

[0102] ===Reset Circuit (RESET) 90=== 4, when the voltage Vcc is low, the reset circuit (RESET) 90 resets the circuitry of the digital section of the control IC 50 and stops the operation of the digital circuitry of the control IC 50. Specifically, when the level of the voltage Vcc is lower than a predetermined level Vccrst, the reset circuit 90 outputs a signal rst1 that resets the digital circuitry of the control IC 50.

[0103] On the other hand, when the level of the voltage Vcc exceeds a predetermined level Vccrst, the reset circuit 90 outputs a signal rst1 that starts operation of the digital circuit of the control IC 50. In this embodiment, when the voltage Vcc rises and the reset circuit 90 releases the reset of the digital circuit, the above-mentioned state setting is executed.

[0104] ===Undervoltage protection circuit (UVLO) 91=== When the voltage Vcc is low, the undervoltage protection circuit (UVLO) 91 resets the load detection circuit 100, the oscillator circuit 101, and the drive circuit 102 (described later), and stops the operation of the load detection circuit 100, the oscillator circuit 101, and the drive circuit 102. Specifically, when the level of the power supply voltage Vcc is lower than a predetermined level Vccon, the undervoltage protection circuit 91 outputs a signal rst2 that resets the load detection circuit 100, the oscillator circuit 101, and the drive circuit 102.

[0105] On the other hand, when the level of the voltage Vcc exceeds a predetermined level Vccon, the low-voltage protection circuit 91 outputs a signal rst2 that causes the load detection circuit 100, the oscillation circuit 101, and the drive circuit 102 to start operating. In this embodiment, when the voltage Vcc rises and the low-voltage protection circuit 91 releases the reset of the various circuits, the control IC 50 starts switching operation.

[0106] ===Internal power supply (REG1)92=== When the level of voltage Vcc rises during startup of control IC 50, internal power supply (REG1) 92 generates voltage Vreg1 for drive signals Vdr1, Vdr2 output by drive circuit 102 (described later). Specifically, when signal Sb to be switched is output by determination circuit 73 and the level of voltage Vcc rises from the ground level, internal power supply 92 gradually generates voltage Vreg1 internally.

[0107] Thereafter, when the setting circuit 76 outputs a signal Sd indicating the completion of the state setting period, the internal power supply 92 outputs the voltage Vreg1 to the terminal REG. Also, when the control IC 50 operates in the "conducting mode," when the low-voltage protection circuit 91 outputs the above-mentioned signal rst2, the drive circuit 102 starts switching the NMOS transistors 32 and 33.

[0108] Furthermore, when the determination circuit 73 outputs a signal Sb indicating that switching should be stopped, the internal power supply 92 stops generating the voltage Vreg1. As a result, when the control IC 50 is in the "shutdown mode," the drive circuit 102 stops the switching of the NMOS transistors 32 and 33. The internal power supply 92 corresponds to the "first power supply voltage generation circuit," and the voltage Vreg1 corresponds to the "first power supply voltage."

[0109] ===Internal power supply (REG2)93=== When the voltage Vcc rises during startup of the control IC 50, the internal power supply (REG2) 93 generates a voltage Vreg2 used as a power supply for various circuits for executing state setting. Specifically, when the signal Sb to be switched is output by the determination circuit 73 and the level of the voltage Vcc rises from the ground level, the internal power supply 93 generates the voltage Vreg2. As a result, when the control IC 50 operates in the "conducting mode," various circuits of the control IC 50 (e.g., the control circuit 120, the discharge circuit 130, and the current source 131) operate by receiving the supply of the voltage Vreg2.

[0110] Furthermore, when the determination circuit 73 outputs a signal Sb indicating that switching should be stopped, the internal power supply 93 stops generating the voltage Vreg2. As a result, the various circuits of the control IC 50 do not operate when the control IC 50 is in the "shutdown mode." The internal power supply 93 corresponds to the "second power supply voltage generation circuit," and the voltage Vreg2 corresponds to the "second power supply voltage."

[0111] ===Load detection circuit 100=== The load detection circuit 100 detects whether the load 14 is in a light load state or a heavy load state based on a voltage applied to the terminal IS and corresponding to the power consumption of the load 14. The load detection circuit 100 outputs a voltage Vca indicating the state of the load 14 to the oscillation circuit 101 and the communication circuit 135.

[0112] Here, the power consumption of the load 14 is greater when the load 14 is in a heavy load state than when the load 14 is in a light load state. Therefore, the voltage Vis applied to the terminal IS indicates a voltage corresponding to the power consumption of the load 14, and the load detection circuit 100 outputs a voltage Vca indicating that the load 14 is in a light load state when the voltage Vis is lower than a predetermined value.

[0113] On the other hand, when the voltage Vis is higher than a predetermined value, the load detection circuit 100 outputs a voltage Vca indicating that the load 14 is in a heavy load state. The heavier the load state of the load 14, the higher the voltage Vca becomes. The voltage Vca corresponds to a "first signal."

[0114] ===Oscillator Circuit 101=== The oscillator circuit 101 is a voltage-controlled oscillator circuit that outputs an oscillation signal Vosc for switching the NMOS transistors 32 and 33 shown in FIG. 3 based on an input feedback voltage Vfb_a.

[0115] Furthermore, when the level of voltage Vfb_a decreases, oscillator circuit 101 outputs a high-frequency oscillation signal Vosc. When load 14 is lightly loaded, output voltage Vout2 rises above the target level. This increases the internal input to constant-voltage circuit 43, which is comprised of a shunt regulator (see FIG. 3), causing a large current to flow through a transistor (not shown) inside the shunt regulator in order to maintain a constant output.

[0116] As a result, a large current also flows through the light-emitting diode 44. Then, the phototransistor 62 causes a bias current I1, the magnitude of which corresponds to the amplification degree of the light from the light-emitting diode 44, to flow from the terminal FB to the ground, thereby reducing the feedback voltage Vfb_a.

[0117] In addition, when the low voltage protection circuit 91 outputs a signal rst2 that causes the oscillator circuit 101 to start operating, the oscillator circuit 101 outputs an oscillation signal Vosc to the control IC 50 based on the signal Sc or the voltage Vca, causing the NMOS transistors 32 and 33 to switch in the "normal mode" or the "low standby power mode."

[0118] When the signal Se indicating the “external mode” is output, the oscillation circuit 101 operates based on the logic level of the signal Sc from the setting circuit 76.

[0119] On the other hand, when the signal Se indicating the “internal mode” is output, the oscillation circuit 101 operates based on the voltage level of the voltage Vca from the load detection circuit 100.

[0120] <<Changing the drive pattern in "internal mode">> When the signal Se indicating the "internal mode" is output, if the load detection circuit 100 outputs a voltage Vca higher than the predetermined level Vcastb, the oscillation circuit 101 switches the NMOS transistors 32 and 33 in the "normal mode."

[0121] On the other hand, when the load detection circuit 100 outputs a voltage Vca that is lower than the predetermined level Vcastb, the oscillation circuit 101 switches the NMOS transistors 32 and 33 in the "low standby power mode."

[0122] The oscillator circuit 101 corresponds to the "oscillating circuit", the "normal mode" corresponds to the "third mode", the "low standby power mode" corresponds to the "fourth mode", and the oscillator signal Vosc corresponds to the "drive signal".

[0123] ===Driver circuit 102=== The drive circuit 102 is supplied with a voltage Vreg1 and switches the NMOS transistors 32 and 33 at the frequency of the oscillation signal Vosc. Specifically, the drive circuit 102 outputs pulse-shaped drive signals Vdr1 and Vdr2 having the frequency of the oscillation signal Vosc and a constant duty ratio (e.g., 50%) to the NMOS transistors 32 and 33, respectively, as shown in Figures 7 and 8. The drive circuit 102 changes the drive signals Vdr1 and Vdr2 complementarily while providing a dead time so that the NMOS transistors 32 and 33 are not turned on simultaneously.

[0124] Here, when the level of the output voltage Vout2 rises above the target level during operation in "normal mode," the feedback voltage Vfb_a decreases, and the frequency of the oscillation signal Vosc increases. As a result, the output voltage Vout2 of the DC-DC converter 13, which is an LLC current resonance type power supply circuit, decreases.

[0125] On the other hand, when the level of the output voltage Vout2 drops below the target level, the feedback voltage Vfb_a increases, and the frequency of the oscillation signal Vosc decreases. As a result, the output voltage Vout2 of the DC-DC converter 13 increases. Therefore, during operation in the "normal mode," the DC-DC converter 13 can generate the output voltage Vout2 at the target level.

[0126] <<<Configuration and Operation of Interface Circuit 18a>>> 9 is a diagram illustrating an example of the interface circuit 18a. As described above, the interface circuit 18a changes the operation of the control IC 50 and realizes a linking function between the control IC 50 and the power factor correction IC 175 in response to the signal Wakeup and the signal ExtSTB from the microcontroller 15a in FIG.

[0127] The interface circuit 18a includes capacitors 150, 154, 159, and 162, resistors 151, 155, 156, 158, and 161, and NMOS transistors 152, 153, 157, and 160.

[0128] As will be described in detail below, capacitors 150 and 154, resistors 151, 155 and 156, and NMOS transistors 152, 153 and 157 set the level of voltage Vstb at terminal STB of control IC 50. Meanwhile, resistors 158 and 161, capacitors 159 and 162, and NMOS transistor 160 realize a linking function between control IC 50 and power factor correction IC 175.

[0129] === Circuit that sets the voltage Vstb level of terminal STB === <Circuit configuration related to the Wakeup signal> Capacitor 150 is provided between ground and signal line L1 connected to terminal STB of control IC 50, and is charged with current Ia from current source 71 of control IC 50. Capacitor 150 corresponds to the "second capacitor," and signal line L1 corresponds to the "first signal line."

[0130] The resistor 151 has a resistance value Rstb, one end connected to the signal line L1, and the other end connected to ground via the NMOS transistor 152. As described above, the resistance value RStb is a resistance value that is set to allow the control IC 50 to determine whether the control IC 50 is in the "external mode" or the "internal mode."

[0131] The NMOS transistor 152 is a switch that is turned on and off at its gate electrode based on a signal Wakeup from the microcontroller 15a in Fig. 1. The NMOS transistor 152 is connected in series to the resistor 151.

[0132] ==Operation when the Wakeup signal is at low level (hereinafter referred to as "L" level)== When the NMOS transistor 152 receives the "L" level signal Wakeup that stops the DC-DC converter 13, it turns off and disconnects the resistor 151 from ground. In this case, the capacitor 150 is not discharged through the resistor 151, so it is charged by the current Ia from the current source 71, and the level of the voltage Vstb becomes higher than the predetermined level Vstop, as shown in Figure 10. As a result, the determination circuit 73 determines that the control IC 50 should be placed in the "shutdown mode."

[0133] That is, the interface circuit 18a puts the control IC 50 into the "shutdown mode" as shown in the "L" stage of the signal Wakeup in Fig. 11. When the signal Wakeup is at the "L" level, the NMOS transistor 153 (described later) is disconnected from the ground, and therefore the level of the voltage Vstb is not affected by the signal ExtSTB.

[0134] ==Operation when the Wakeup signal is at high level (hereinafter referred to as "H" level)== On the other hand, when the NMOS transistor 152 receives a signal Wakeup that operates the DC-DC converter 13 (i.e., a signal at "H" level), it turns on and connects the resistor 151 connected in series with the NMOS transistor 152 to ground. As a result, the capacitor 150 is discharged via the resistor 151, and the level of the voltage Vstb falls below the predetermined level Vstop as shown in FIG. 10. As a result, the determination circuit 73 determines that the control IC 50 should be placed in the "conducting mode."

[0135] As a result, the control IC 50 operates in the "conduction mode" as shown in the "H" stage of the signal Wakeup in Figure 11. The resistor 151 corresponds to a "resistor," the NMOS transistor 152 corresponds to a "first switch," and the signal Wakeup corresponds to an "instruction signal." The current source 71 corresponds to a "current source."

[0136] When the control IC 50 is in the state setting period upon startup, the current Ib from the current source 131, which has received a signal S2 instructing the supply of the current Ib, flows through the resistor 151, and a predetermined voltage appears as the voltage Vstb at the terminal STB. As a result, the analog-to-digital converter 132 converts this predetermined voltage into a digital value Dvstb.

[0137] Thereafter, the determination circuit 121 outputs a signal Se indicating whether the drive pattern should be changed in the "external mode" or the "internal mode" according to the digital value Dvstb. Specifically, when the resistance value Rstb of the resistor 151 is the resistance value Ra, the determination circuit 121 outputs a signal Se indicating the "external mode" as shown in FIG.

[0138] On the other hand, when the resistance value Rstb of the resistor 151 is the resistance value Rb, the decision circuit 121 outputs a signal Se indicating the "internal mode" as shown in FIG.

[0139] <Configuration of circuits related to the signal ExtSTB> The NMOS transistor 153 is a switch that changes the level of the voltage Vstb based on the signal ExtSTB, and is provided between the NMOS transistor 157 (described later) and the NMOS transistor 152. The NMOS transistor 153 receives the signal ExtSTB from the microcontroller 15a at its gate electrode.

[0140] Before describing what level of voltage Vstb the interface circuit 18a outputs depending on the logic level of the signal EXtSTB, the relationship between the terminal REG and an NMOS transistor 157 (described later) will be described.

[0141] <Circuit configuration related to terminal REG> The capacitor 154 is provided between the terminal REG and the ground, and stabilizes the output voltage Vreg1 of the internal power supply 92.

[0142] Resistors 155 and 156 divide the voltage Vreg1, generating a voltage Vreg1_div at their connection point.

[0143] The NMOS transistor 157 receives a gate electrode voltage Vreg1_div, is provided between the signal line L1 and the NMOS transistor 153, and is connected to ground via the NMOS transistors 152 and 153. The NMOS transistors 153 and 157 are connected in parallel to the resistor 151.

[0144] Then, the internal power supply 92 stops outputting the voltage Vreg1 until the state setting period of the control IC 50 is completed, and the NMOS transistor 157 is turned off. Therefore, the NMOS transistor 157 eliminates the influence of the NMOS transistor 153, which receives the signal ExtSTB, on the level of the voltage Vstb. The NMOS transistor 157 corresponds to the "second switch," and the NMOS transistor 153 corresponds to the "third switch."

[0145] Specifically, the internal power supply 92 outputs the voltage Vreg1, which is the ground voltage, until the state setting period of the control IC 50 is completed, so that the NMOS transistor 157 is turned off, eliminating the influence of the NMOS transistor 153 during the state setting period.

[0146] Thereafter, when the state setting period of the control IC 50 is completed, the internal power supply 92 outputs the voltage Vreg1, and the NMOS transistor 157 turns on. When the NMOS transistor 157 turns on, the NMOS transistor 152 is also on, so the level of the voltage Vstb changes depending on whether the NMOS transistor 153 is turned on or off, and the control IC 50 changes the operating mode in response to the signal ExtSTB.

[0147] When the signal ExtSTB instructing the drive pattern of the NMOS transistors 32 and 33 in FIG. 3 is output, the NMOS transistor 153 turns on and off, setting the voltage Vstb lower or higher than the voltage Vthstb as shown in FIG.

[0148] Furthermore, when the signal Wakeup is at the "L" level and the control IC 50 is in the "shutdown mode," the NMOS transistor 153 is disconnected from ground, and the level of the voltage Vstb is not affected by the signal ExtSTB. Therefore, the following will describe what level of the voltage Vstb the interface circuit 18a outputs in response to the signal ExtSTB when the signal Wakeup is at the high level "H" and the control IC 50 is in the "conductive mode."

[0149] ==Operation when signal ExtSTB is at "H" level== Specifically, when a signal ExtSTB (i.e., a signal at "H" level) that switches the NMOS transistors 32 and 33 in the "low standby power mode" is output, the NMOS transistor 153 turns on. At this time, regardless of the operation of the clamp circuit 133 in FIG. 5, the level of the voltage Vstb becomes lower than the predetermined level Vthstb as shown in FIG.

[0150] At this time, the comparator 134 outputs a signal Sc instructing the "low standby power mode", and causes the oscillator circuit 101 to output an oscillation signal Vosc that switches the NMOS transistors 32 and 33 in the "low standby power mode".

[0151] As a result, the interface circuit 18a causes the control IC 50 to perform intermittent switching of the NMOS transistors 32 and 33 as shown in the stage where the signal ExTSTB is at "H" level in FIG.

[0152] ==Operation when signal ExtSTB is at "L" level== On the other hand, when a signal ExtSTB (i.e., a signal at an "L" level) that switches the NMOS transistors 32 and 33 in the "normal mode" is output, the NMOS transistor 153 is turned off. At this time, the level of the voltage Vstb becomes higher than the predetermined level Vthstb, as shown in FIG.

[0153] At this time, the comparator 134 outputs a signal Sc instructing the "normal mode" and causes the oscillation circuit 101 to output an oscillation signal Vosc that switches the NMOS transistors 32 and 33 in the "normal mode."

[0154] As a result, the interface circuit 18a causes the control IC 50 to continuously switch on and off the NMOS transistors 32 and 33, as shown in the stage where the signal ExTSTB is at the "L" level in Fig. 11. The cooperation function of the interface circuit 18a will be described later.

[0155] ==Power factor correction IC175 side circuit== As described above, the resistors 158 and 161, the capacitors 159 and 162, and the NMOS transistor 160 realize the cooperation function between the control IC 50 and the power factor correction IC 175.

[0156] Resistor 158 and capacitor 159 form a low-pass filter that removes noise from the pulse signal output by communication circuit 135 in Fig. 5. The pulse signal is configured to output two pulses with a period T1 when the effective value of AC voltage Vac is 100V, and to output one pulse with a period T1 when the effective value of AC voltage Vac is 200V.

[0157] The NMOS transistor 160 is turned on and off in response to the output of the low-pass filter, and outputs a voltage Sig to the power factor correction IC 175 in response to the pulse signal output by the communication circuit 135 .

[0158] The resistor 161 is provided between the terminal RT and the ground, and reduces the voltage of the terminal RT when the NMOS transistor 160 is turned off.

[0159] The capacitor 162 is provided between the terminal RT and the ground, and stabilizes the voltage of the terminal RT.

[0160] <<<Outline of the power factor correction circuit 22>>> 12 is a diagram showing the configuration of the power factor correction circuit 22. The power factor correction circuit 22 is a boost chopper type power supply circuit that generates an output voltage Vout1 at a target level from an AC voltage Vac of a commercial power supply.

[0161] The power factor correction circuit 22 includes a full-wave rectifier circuit 170, capacitors 171, 174, 183, and 184, a transformer 172, a diode 173, a power factor correction IC 175, an NMOS transistor 176, and resistors 180 to 182.

[0162] The full-wave rectifier circuit 170 full-wave rectifies the applied predetermined AC voltage Vac to obtain a rectified voltage Vrec2, which is applied to a capacitor 171 and a main coil L5 of a transformer 172. Here, the AC voltage Vac is, for example, a voltage of 100 to 240 V and a frequency of 50 to 60 Hz.

[0163] The capacitor 171 is an element that smoothes the rectified voltage Vrec2, and the transformer 172 has a main coil L5 and an auxiliary coil L6 magnetically coupled to the main coil L5. In this embodiment, the auxiliary coil L6 is wound so that the voltage generated in the auxiliary coil L6 has the opposite polarity to the voltage generated in the main coil L5. The voltage Vzcd generated in the auxiliary coil L6 is applied to the terminal ZCD.

[0164] The rectified voltage Vrec2 is applied directly to the main coil L5, but may also be applied to the main coil L5 via an element such as a resistor (not shown).

[0165] Furthermore, the main coil L5, together with the diode 173, the capacitor 174, and the NMOS transistor 176, constitutes a boost chopper circuit. Therefore, the charging voltage of the capacitor 174 becomes the DC output voltage Vout1. The output voltage Vout1 is, for example, 400 V.

[0166] The power factor correction IC 175 is an integrated circuit that controls the switching of the NMOS transistor 176 so that the level of the output voltage Vout1 becomes a target level (for example, 400 V) while correcting the power factor of the AC-DC converter 12. Specifically, the power factor correction IC 175 drives the NMOS transistor 176 based on the inductor current IL flowing through the main coil L5 and the output voltage Vout1.

[0167] The power factor correction IC 175 is provided with terminals VH, VCC, RT, FB, ZCD, COMP, and OUT, which will be described in detail later. The power factor correction IC 175 is also provided with terminals other than the seven terminals VH, VCC, RT, FB, ZCD, COMP, and OUT described above, but these are omitted here for convenience.

[0168] The NMOS transistor 176 is a transistor for controlling the power supplied to the DC-DC converter 13 from the AC-DC converter 12. In this embodiment, the NMOS transistor 176 is a MOS (Metal Oxide Semiconductor) transistor, but is not limited to this. The NMOS transistor 176 may be, for example, a bipolar transistor, as long as it is a transistor that can control power. The gate electrode of the NMOS transistor 176 is connected so as to be driven by a signal from the terminal OUT.

[0169] The resistors 180 and 181 form a voltage divider circuit that divides the output voltage Vout1 and generates a feedback voltage Vfb_b that is used when switching the NMOS transistor 176. The feedback voltage Vfb_b generated at the node to which the resistors 180 and 181 are connected is applied to the terminal FB.

[0170] The resistor 182 and capacitors 183 and 184, which will be described in detail later, are elements for phase compensation of the feedback-controlled power factor correction IC 175. The resistor 182 and capacitor 183 are connected in series between the terminal COMP and the ground, and the capacitor 184 is connected in parallel with them.

[0171] A pulse signal is input to the terminal RT from the interface circuit 18a.

[0172] <<<Details of the Power Factor Correction IC175>>> Fig. 13 is a diagram showing an example of the configuration of a power factor correction IC 175. The power factor correction IC 175 includes a drive circuit 190, a signal detection circuit 191, and a resistor 192. For convenience, terminals are drawn in different positions in Fig. 13 than in Fig. 12, but the wiring, elements, etc. connected to each terminal are the same in Figs. 12 and 13.

[0173] ===Drive circuit 190=== The drive circuit 190 is a circuit that generates a drive signal Vdr that turns on and off the NMOS transistor 176 based on a feedback voltage Vfb_b that corresponds to the output voltage Vout1. The drive circuit 190 includes a zero current detection circuit 200, a delay circuit 201, a pulse circuit 202, a turn-on timer circuit 203, OR circuits 204 and 213, an error amplifier circuit 210, an oscillation circuit 211, a comparator 212, an SR flip-flop 220, and a buffer circuit 221.

[0174] ====Zero Current Detection Circuit 200==== The zero current detection circuit 200 is a circuit that detects whether the current value of the inductor current IL is a "current value Ia" indicating almost zero (hereinafter, for convenience, "almost zero" will be simply referred to as "zero") based on the voltage Vzcd of the terminal ZCD. Note that the zero current detection circuit 200 of this embodiment outputs an "H" level signal Vz when it detects that the current value of the inductor current IL is the "current value Ia" which is "zero." The zero current detection circuit 200 also includes a comparator (not shown) that compares the voltage Vzcd with a predetermined voltage of the auxiliary coil L6 when the inductor current IL becomes the "current value Ia."

[0175] ====Delay circuit 201==== When the zero current detection circuit 200 outputs the signal Vz at "H" level, the delay circuit 201 delays it by a predetermined time and then outputs it.

[0176] ====Pulse circuit 202==== When the delay circuit 201 outputs the "H" level signal Vz, the pulse circuit 202 outputs the H level pulse signal Vp1.

[0177] ====Turn-on timer circuit 203==== The turn-on timer circuit 203 outputs a pulse signal Vp2 for turning on the NMOS transistor 176 when the power factor correction IC 175 is started up or when the AC voltage Vac is cut off and the pulse signal Vp1 is not output. Specifically, if the pulse signal Vp1 is not output for a predetermined period, the turn-on timer circuit 203 outputs an “H” level pulse signal Vp2 at predetermined intervals.

[0178] ====OR circuit 204==== The OR circuit 204 calculates and outputs the logical sum of the pulse signals Vp1 and Vp2. Therefore, in this embodiment, the OR circuit 204 outputs either the pulse signal Vp1 or the pulse signal Vp2 as the signal Vp3.

[0179] ====Error amplifier circuit 210==== The error amplifier circuit 210 amplifies the error between the feedback voltage Vfb_b applied to the terminal FB and a predetermined reference voltage VREF0 or VREF1. Based on the reference voltage VREF0, the ratio between the resistors 180 and 181 is adjusted so that the output voltage Vout1 becomes a desired voltage.

[0180] The reference voltages VREF0 and VREF1 are selected based on a signal enb from a signal detection circuit 191, which will be described later. The reference voltage VREF1 is a reference voltage for generating an output voltage Vout1 at a predetermined level lower than a target level when the AC input is high (for example, 200 V).

[0181] Furthermore, a resistor 182 and capacitors 183 and 184 for phase compensation are connected between the output of the error amplifier circuit 210 and the ground via a terminal COMP. Here, the voltage of the node where the output of the error amplifier circuit 210 and the terminal COMP are connected is defined as a voltage Ve.

[0182] ====Oscillator Circuit 211==== Every time the oscillator circuit 211 receives the "H" level signal Vp1 from the SR flip-flop 220, it outputs a ramp wave Vr whose amplitude gradually increases.

[0183] ====Comparator 212==== The comparator 212 compares the magnitudes of the voltage Ve and the ramp wave Vr, and outputs a signal Vc1 as the comparison result. Here, the voltage Ve is applied to the inverting input terminal of the comparator 212, and the ramp wave Vr is applied to the non-inverting input terminal of the comparator 212. Therefore, when the level of the ramp wave Vr is lower than the level of the voltage Ve, the signal Vc1 becomes "L" level, and when the level of the ramp wave Vr is higher than the level of the voltage Ve, the signal Vc1 becomes "H" level.

[0184] ====OR circuit 213==== The OR circuit 213 calculates and outputs the logical sum of the signal Vc1 and the signal Vsb from the signal detection circuit 191. Therefore, when the signal Vc1 or the signal Vsb goes high, the OR circuit 213 outputs a signal Vp4 at high level.

[0185] ====SR Flip-Flop 220==== The signal Vp3 is input to the S input of the SR flip-flop 220, and the signal Vp4 is input to the R input. Therefore, when the signal Vp3 goes to the "H" level, the drive signal Vq1, which is the Q output of the SR flip-flop 220, goes to the "H" level. On the other hand, when the signal Vp4 goes to the "H" level, the drive signal Vq1 goes to the "L" level. Note that the SR flip-flop 220 operates with reset priority, and when the signal Vp4 is at the "H" level, it always outputs the signal Vq1 at the "L" level regardless of the signal Vp3.

[0186] ====Buffer circuit 221==== The buffer circuit 221 drives the NMOS transistor 176 based on the drive signal Vq1. Specifically, the buffer circuit 221 drives the NMOS transistor 176, which has a large gate capacitance, with a signal Vdr having the same logical level as the input signal. The buffer circuit 221 also turns on the NMOS transistor 176 based on the drive signal Vq1 at an "H" level, and turns off the NMOS transistor 176 based on the drive signal Vq1 at an "L" level.

[0187] ===Signal detection circuit 191=== The signal detection circuit 191 realizes a main function when the control IC 50 operates in the "internal mode" and controls the power factor correction IC 175. This embodiment also describes the case where the control IC 50 operates in the "external mode."

[0188] Therefore, in this embodiment, when the determination circuit 121 outputs a signal Se indicating the "external mode," the communication circuit 135 in FIG. 5 outputs a pulse signal indicating whether the effective value of the AC voltage Vac is high (e.g., 200 V) or low (e.g., 100 V) to the power factor correction IC 175 via the interface circuit 18 a.

[0189] The signal detection circuit 191 detects whether the AC input is 100 V or 200 V based on the pulse signal input via the terminal RT, and outputs a signal enb indicating whether the AC input is 100 V or 200 V. A resistor 192 is connected to the terminal RT for pulling up to the power supply voltage Vdd from an internal power supply (not shown). Other functions of the signal detection circuit 191 will be described later.

[0190] <<<Control IC 50 Operation>>> FIG. 14 is a diagram illustrating an example of the operation of the control IC 50. Note that FIG. 14 illustrates an example of the operation of the control IC 50 when the control IC 50 changes the drive pattern in "external mode" after the control IC 50 is started. Also, before time t0, the microcontroller 15a outputs a Wakeup signal (i.e., an "L" level) that stops the DC-DC converter 13. Also, at this time, the control IC 50 is in "shutdown mode." Also, the effective value of the AC voltage Vac (i.e., AC input) is assumed to be 100 V.

[0191] At time t0, when the microcontroller 15a in Fig. 1 outputs a signal Wakeup (i.e., a signal of "H" level) to operate the DC-DC converter 13, the NMOS transistor 152 in Fig. 9 turns on. The capacitor 150 is discharged via the resistor 151, and the voltage Vstb at the terminal STB starts to decrease.

[0192] At time t1, when voltage Vstb drops to a predetermined level Vstop, the determination circuit 73 outputs a switching signal Sb. This causes the control circuit 81 to output a signal Pon to the charging circuit 82, causing it to start charging the capacitor 61 shown in FIG. 3. Then, voltage Vcc begins to rise. At this time, the control IC 50 transitions to the "conduction mode." However, because the control IC 50 has not yet completed its initial setup, the NMOS transistors 32 and 33 are not switched on.

[0193] At time t2, when the voltage Vcc reaches a predetermined level Vccrst, the reset circuit 90 outputs a signal rst1 that causes the various circuits in the control IC 50 to start operating. Then, the state setting period begins, and the control circuit 120 in FIG. 5 outputs a signal S1 that discharges the capacitor 150, causing the discharge circuit 130 to discharge the capacitor 150. As a result, the voltage Vstb becomes the ground voltage.

[0194] At time t3, when the voltage Vcc reaches a predetermined level Vstoff, the control circuit 81 outputs a signal Pon to the charging circuit 82 to stop charging the capacitor 61. Thereafter, until time t6 (described later) is reached, when the voltage Vcc reaches a predetermined level Vston, the control circuit 81 causes the charging circuit 82 to start charging the capacitor 61 in Fig. 3, and when the voltage Vcc reaches the predetermined level Vstoff, it outputs a signal Pon to stop charging.

[0195] At time t4, the control circuit 120 outputs a signal S1 to stop discharging the capacitor 150 and a signal S2 to instruct the supply of a current Ib, and the current source 131 in FIG. 5 supplies the current Ib to the resistor 151 via the terminal STB. As a result, the voltage Vstb becomes a voltage corresponding to the resistance value Rstb of the resistor 151. In this embodiment, the resistance value Rstb of the resistor 151 is assumed to be the resistance value Ra shown in FIG. 6.

[0196] At time t5, the control circuit 120 outputs a signal S3 indicating the timing to acquire the digital value Dvstb, and the determination circuit 121 acquires the digital value Dvstb of the voltage Vstb. As a result, the determination circuit 121 determines that the mode is "external mode," and outputs a signal Se indicating "external mode."

[0197] Thereafter, the control circuit 120 outputs a signal S1 to discharge the capacitor 150, and the discharge circuit 130 discharges the capacitor 150. As a result, the voltage Vstb becomes the ground voltage.

[0198] At time t6 when the state setting period is completed, the control circuit 120 outputs a signal Sd indicating the completion of the state setting period for initializing various circuits of the control IC 50. The control circuit 81 then causes the charging circuit 82 to charge the capacitor 61 until the voltage Vcc reaches a predetermined level Vccon. The internal power supply 92 also outputs a voltage Vreg1 to the terminal REG.

[0199] Then, when the control circuit 120 outputs the signal S1 to stop discharging the capacitor 150, the discharge circuit 130 stops discharging the capacitor 150. As a result, the clamp circuit 133 starts to maintain the voltage Vstb at the voltage Vnorm.

[0200] At time t7, when the voltage Vcc exceeds the predetermined level Vccon, the low voltage protection circuit 91 outputs a signal rst2 that causes the load detection circuit 100, the oscillation circuit 101, and the drive circuit 102 in Fig. 4 to start operating. Also, because the voltage Vcc has reached the predetermined level Vccon, the control circuit 81 outputs a signal Pon to the charging circuit 82 to stop charging the capacitor 61.

[0201] Furthermore, when the oscillation circuit 101 receives the signal Sc indicating the “normal mode” and the signal Se indicating the “external mode”, it outputs to the drive circuit 102 an oscillation signal Vosc for causing the NMOS transistors 32 and 33 to perform continuous switching.

[0202] 3, the capacitor 61 is then charged by the current from the auxiliary coil L4. Also, since the AC input is 100 V, the communication circuit 135 outputs a pulse signal indicating that the effective value of the AC voltage Vac is low to the power factor correction IC 175 via the terminal STB.

[0203] At time t8, the microcontroller 15a outputs a signal ExtSTB (i.e., a high-level signal) to the control IC 50 to switch the NMOS transistors 32 and 33 in the low standby power mode. As a result, the comparator 134 outputs a signal Sc indicating the low standby power mode.

[0204] When the oscillator circuit 101 receives the signal Sc indicating the "low standby power mode" and the signal Se indicating the "external mode", it outputs an oscillation signal Vosc to the drive circuit 102 to cause the NMOS transistors 32 and 33 to perform intermittent switching.

[0205] At time t9, the microcontroller 15a outputs a signal ExtSTB (i.e., a signal of "L" level) to the control IC 50 to switch the NMOS transistors 32 and 33 in the "normal mode," causing the level of the voltage Vstb to become higher than the predetermined level Vthstb. As a result, the comparator 134 outputs a signal Sc indicating the "normal mode."

[0206] When the oscillation circuit 101 receives the signal Sc indicating the "normal mode" and the signal Se indicating the "external mode", it outputs to the drive circuit 102 an oscillation signal Vosc for causing the NMOS transistors 32 and 33 to perform continuous switching.

[0207] At time t10, similarly to time t7, the communication circuit 135 outputs a pulse signal indicating that the effective value of the AC voltage Vac is low to the power factor correction IC 175 via the terminal STB because the AC input is 100V.

[0208] The above describes an embodiment in which the control IC 50 changes the drive pattern in the "external mode." Furthermore, the control IC 50 can change its operating mode between a "shutdown mode," in which circuits other than the start-up circuit 70 are stopped, and a "conduction mode," in which circuits including the start-up circuit 70 are operated, depending on the logic level of the signal Wakeup.

[0209] In this embodiment, the configuration of the interface circuit 18a allows the control IC 50 to appropriately switch the NMOS transistors 32 and 33 between the "normal mode" and the "low standby power mode" after startup depending on the logic level of the signal ExtSTB.

[0210] This allows the control IC 50 to reduce its own power consumption when it is in the "shutdown mode". Furthermore, even when the control IC 50 operates in the "conductive mode", the control IC 50 can change the drive pattern to the "normal mode" or the "low standby power mode" according to the logic level of the signal ExtSTB, thereby reducing the power consumption of the DC-DC converter 13. Furthermore, the power consumption when the control IC 50 is in the "shutdown mode" is less than the power consumption when the control IC 50 operates in the "normal mode" or the "low standby power mode".

[0211] <<<Configuration and Operation of Interface Circuit 18b>>> 15 is a diagram showing an example of an interface (IF) circuit 18b. The interface circuit 18b is used when changing the drive pattern in the "internal mode," and is a circuit in which NMOS transistors 153 and 157 and resistors 155 and 156 are removed from the interface circuit 18a in FIG. 9. Therefore, the configuration of the interface circuit 18b will not be described in detail.

[0212] <<Operation when the Wakeup signal is at "L" level>> 9, when the microcontroller 15b outputs a signal Wakeup that stops the DC-DC converter 13 (i.e., a signal at "L" level), the level of the voltage Vstb at the terminal STB becomes higher than the predetermined level Vstop, as shown in Fig. 16. As a result, the interface circuit 18b puts the control IC 50 into the "shutdown mode," as shown in the stage in Fig. 17 where the signal Wakeup is at "L" level.

[0213] <<Operation when the Wakeup signal is at "H" level>> On the other hand, when the microcontroller 15b outputs a signal Wakeup that operates the DC-DC converter 13 (i.e., at "H" level), the level of the voltage Vstb becomes lower than the predetermined level Vstop, as shown in Fig. 16. As a result, the interface circuit 18b operates the control IC 50 in the "conducting mode," as shown in the "H" stage of Fig. 17 where the signal Wakeup is at "H."

[0214] <Explanation of the cooperation between the control IC 50 and the power factor correction IC 175> When the drive pattern is changed in the "internal mode," the communication circuit 135 of FIG. 5 outputs a pulse signal to the power factor correction IC 175 according to the AC input and the operating mode of the control IC 50, in order to realize a cooperative function between the control IC 50 and the power factor correction IC 175, as shown in FIG. 17.

[0215] Specifically, as shown in FIG. 17, the communication circuit 135 changes the number of pulses included in the pulse signal in accordance with the AC input (for example, see pulses (a) and (c)), and changes the pulse width of the pulse in accordance with the operating mode of the control IC 50 (for example, see pulses (a) and (b)).

[0216] When the power factor correction IC 175 receives (a) a pulse signal with a pulse width of T1 and two pulses, it detects that the AC input is 100V and that the operating mode should be changed to continuous switching. When the power factor correction IC 175 receives (b) a pulse signal with a pulse width of T2 and two pulses, it detects that the AC input is 100V and that the operating mode should be changed to intermittent switching.

[0217] Furthermore, when the power factor correction IC 175 receives a pulse signal (c) with a pulse width of T1 and a single pulse, it detects that the AC input is 200V and that the operating mode should be changed to continuous switching. Furthermore, when the power factor correction IC 175 receives a pulse signal (d) with a pulse width of T2 and a single pulse, it detects that the AC input is 200V and that the operating mode should be changed to intermittent switching.

[0218] Furthermore, when the power factor correction IC 175 receives a pulse signal (e) that is a continuous pulse with a pulse width of T3, it stops switching while receiving the pulse signal. The power factor correction IC 175 also stops when the control IC 50 is in "shutdown mode." The magnitude relationship among the pulse widths T1 to T3 is T2>T1>T3.

[0219] <Details of the signal detection circuit 191> 13 detects the voltage Sig at the terminal RT to which the pulse signal from the control IC 50 is input, and detects the AC input and a switching instruction based on the number of pulses and pulse width of the pulse signal. Specifically, as described above, the signal detection circuit 191 detects that the AC input is 100 V when the pulse signal contains two pulses.

[0220] If the pulse signal contains one pulse, the signal detection circuit 191 detects that the AC input is 200 V. This allows the power factor correction IC 175 to change its operation according to the type of AC input indicated by the pulse signal, without having to detect the AC input itself.

[0221] Furthermore, when the pulse width of the pulse signal is pulse width T1, the signal detection circuit 191 detects that the control IC 50 is instructing the power factor correction IC 175 to perform "continuous switching." In this case, the signal detection circuit 191 outputs an "L" level signal Vsb to the OR circuit 213. Then, the power factor correction IC 175 sets the signal Vdr to the "L" level based on the signal Vc1 output by the comparator 212.

[0222] Furthermore, when the pulse width of the pulse signal is pulse width T2, the signal detection circuit 191 detects that the control IC 50 is instructing the power factor correction IC 175 to perform "intermittent switching." In this case, the signal detection circuit 191 outputs an "H" level signal Vsb when the voltage Vfb_b reaches a predetermined level V1, and outputs an "L" level signal Vsb when the voltage Vfb_b drops to a predetermined level V2.

[0223] Therefore, when the voltage Vfb_b reaches the predetermined level V1, the signal detection circuit 191 sets the signal Vdr to the "L" level, causing the power factor correction IC 175 to turn off the NMOS transistor 176. On the other hand, when the voltage Vfb_b drops to the predetermined level V2, the signal detection circuit 191 causes the power factor correction IC 175 to drive the NMOS transistor 176 based on the signal Vc1.

[0224] Furthermore, when the pulse width of the pulse signal is pulse width T3, the signal detection circuit 191 detects that the control IC 50 is instructing the power factor correction IC 175 to stop switching while outputting the pulse signal. In this case, the signal detection circuit 191 outputs the signal Vsb at an “H” level while the pulse signal is being input, sets the signal Vdr to an “L” level, and causes the power factor correction IC 175 to turn off the NMOS transistor 176.

[0225] <<<Coordination between control IC50 and power factor correction IC175>>> Fig. 18 is a diagram showing an example of the operation of the control IC 50 and the power factor correction IC 155. Fig. 18 shows an example of the operation of the control IC 50 when the control IC 50 changes the drive pattern in the "internal mode" after the control IC 50 is started.

[0226] Also, before time t20, the microcontroller 15b outputs a signal Wakeup (i.e., at "L" level) that stops the DC-DC converter 13. At this time, the control IC 50 is in "shutdown mode." Also, the effective value of the AC voltage Vac (i.e., AC input) is assumed to be 100 V.

[0227] Furthermore, in the interface circuit 18b, the signal ExtSTB and the voltage Vreg1_div are not used as inputs, and therefore are not shown in Fig. 18. Furthermore, the operation of the control IC 50 from time t20 to time t27 in Fig. 18 corresponds to the operation of the control IC 50 from time t0 to time t7 in Fig. 14, except for the following points.

[0228] Also, at time t25, the decision circuit 121 decides that the mode is the "internal mode" and outputs a signal Se indicating the "internal mode."

[0229] Furthermore, the power factor correction IC 175 stops switching before time t21 when the control IC 50 is in the "shutdown mode." Furthermore, the power factor correction IC 175 stops switching from time t21 when the control IC 50 transitions to the "conduction mode" until time t27 when the state setting period ends and continuous switching begins. Therefore, the operation of the control IC 50 and the power factor correction IC 175 after time t27 will be described below.

[0230] At time t27, when the level of voltage Vcc exceeds predetermined level Vccon, low voltage protection circuit 91 outputs signal rst2, which causes load detection circuit 100, oscillator circuit 101, and drive circuit 102 in Fig. 4 to start operating. Also, because the level of voltage Vcc reaches predetermined level Vccon, control circuit 81 outputs signal Pon to charging circuit 82 to stop charging capacitor 61.

[0231] Furthermore, the oscillation circuit 101 operates in the same manner as at time t7 in Fig. 14. Then, similar to the case of time t7 in Fig. 14, the capacitor 61 is subsequently charged with current from the auxiliary coil L4. Furthermore, the communication circuit 135 operates in the same manner as at time t7 in Fig. 14.

[0232] Furthermore, the power factor correction IC 175 starts continuous switching in response to the level of the voltage Vcc exceeding a predetermined level Vccon.

[0233] At time t28, the load detection circuit 100 in Fig. 4 indicates that the load 14 in Fig. 1 is in a light load state and outputs a voltage Vca that is lower than the predetermined level Vcastb. As a result, upon receiving the voltage Vca indicating that the load 14 is in a light load state and the signal Se indicating the "internal mode," the oscillation circuit 101 outputs an oscillation signal Vosc to the drive circuit 102 to cause the NMOS transistors 32 and 33 in Fig. 3 to perform intermittent switching. Then, the communication circuit 135 in Fig. 5 outputs a pulse signal including two pulses with a pulse width of T2.

[0234] At time t29, the power factor correction IC 175 detects, based on the pulse signal, that the AC input is 100 V and that intermittent switching should be performed, so the power factor correction IC 175 starts intermittent switching.

[0235] 4 indicates that the load 14 in FIG. 1 is in a heavy load state, and outputs a voltage Vca that is higher than the predetermined level Vcastb. As a result, upon receiving the voltage Vca indicating that the load 14 is in a heavy load state and the signal Se indicating the "internal mode," the oscillator circuit 101 outputs an oscillation signal Vosc to the drive circuit 102 to cause the NMOS transistors 32 and 33 to perform continuous switching.

[0236] At time t31, the communication circuit 135 in FIG. 5 outputs a pulse signal including two pulses with a pulse width of T1.

[0237] At time t32, the power factor correction IC 175 detects from the pulse signal that the AC input is 100 V and that continuous switching should be performed, so the power factor correction IC 175 starts continuous switching.

[0238] The above describes an embodiment in which the control IC 50 changes the drive pattern in the "internal mode." Furthermore, the control IC 50 can change its operating mode between a "shutdown mode," in which circuits other than the start-up circuit 70 are stopped, and a "conduction mode," in which circuits including the start-up circuit 70 are operated, depending on the logic level of the signal Wakeup.

[0239] In this embodiment, the configuration of the interface circuit 18b allows the control IC 50 to appropriately switch the NMOS transistors 32 and 33 between the "normal mode" and the "low standby power mode" depending on the state of the load 14 after startup.

[0240] As a result, when the control IC 50 is in the "shutdown mode," the control IC 50 can reduce its own power consumption. Furthermore, even when the control IC 50 operates in the "conductive mode," the control IC 50 can change the drive pattern to the "normal mode" or the "low standby power mode" depending on the state of the load 14, thereby reducing the power consumption of the DC-DC converter 13. Furthermore, the power consumption when the control IC 50 is in the "shutdown mode" is less than the power consumption when the control IC 50 operates in the "normal mode" or the "low standby power mode." Furthermore, the control IC 50, in cooperation with the power factor correction IC 175, can reduce the power consumption of the entire power supply device 10.

[0241] ===Summary=== The power supply device 10 of this embodiment has been described above. The control IC 50 includes a terminal STB, a determination circuit 73, an internal power supply 92, and a drive circuit 102. The control IC 50 controls the internal power supply 92 based on the voltage level (voltage Vstb) of the terminal STB, and when operating in "shutdown mode," the control IC 50 can cause the internal power supply 92 to stop generating voltage Vreg1. When the internal power supply 92 stops generating voltage Vreg1, the control IC 50 can stop the operation of circuits that operate by receiving the supply of voltage Vreg1. This makes it possible to provide an integrated circuit that can further reduce power consumption.

[0242] The control IC 50 also includes a terminal VH, a constant voltage source 80, and a current source 71. This allows the control IC 50 to supply the voltage Vstartup to the current source 71 and the determination circuit 73 while the rectified voltage Vrec1 is applied to the terminal VH, even when the control IC 50 is in the "shutdown mode."

[0243] Control IC 50 also includes a terminal VCC, which, because internal power supply 92 operates based on voltage Vcc, causes voltage Vcc to drop when control IC 50 is in "shutdown mode," prompting internal power supply 92 to stop generating voltage Vreg1.

[0244] Control IC 50 also includes a charging circuit 82. This causes charging circuit 82 to stop charging capacitor 61, so that control IC 50, when in "shutdown mode," causes voltage Vcc to drop, thereby causing internal power supply 92 to stop generating voltage Vreg1.

[0245] The control IC 50 also includes a load detection circuit 100, an oscillation circuit 101, a determination circuit 121, and a comparator 134. This allows the control IC 50 to change the drive pattern of the NMOS transistors 32 and 33 in either the "external mode" or the "internal mode."

[0246] The control IC 50 also includes a communication circuit 135. This allows the control IC 50 to output a pulse signal to the power factor correction IC 175 and operate in cooperation with the power factor correction IC 175 when changing the drive pattern in the "internal mode."

[0247] The control IC 50 also includes a terminal REG, which prevents the control IC 50 from malfunctioning even if the signal ExtSTB is erroneously input from the microcontroller 15a during the state setting period.

[0248] The control IC 50 also includes a discharge circuit 130 and a control circuit 120. This allows the control IC 50 to accurately determine the voltage according to the resistance value Rstb of the resistor 151 during the state setting period.

[0249] The control IC 50 also includes an internal power supply 93. This allows the control IC 50 to stop circuits that operate when supplied with the voltage Vreg2 when the control IC 50 is in the "shutdown mode."

[0250] The control IC 50 also includes a Zener diode 72. This prevents the voltage Vstb from exceeding a predetermined level even if the capacitor 150 is charged by the current source 71.

[0251] The control IC 50 also includes a terminal STB and a mode selection circuit (a determination circuit 73 and a comparator 134). The control IC 50 can operate in any of a "shutdown mode," a "normal mode," or a "low standby power mode" based on the voltage level (voltage Vstb) of the terminal STB. This allows the control IC 50 to further reduce power consumption.

[0252] Furthermore, the mode selection circuit can change the operation mode of the control IC 50 based on the voltage level of the terminal STB, so that the operation mode of the control IC 50 can be changed simply by detecting the voltage level of the terminal STB.

[0253] The mode selection circuit also includes a determination circuit 73 that operates even in the "shutdown mode," and a comparator 134 that does not operate in the "shutdown mode." This allows the control IC 50 to operate in either the "normal mode" or the "low standby power mode" in the "conductive mode," while suppressing power consumption in the "shutdown mode."

[0254] The control IC 50 also includes a load detection circuit 100, an oscillation circuit 101, and a setting circuit 76. This allows the control IC 50 to change the drive pattern of the NMOS transistors 32 and 33 in either the "external mode" or the "internal mode."

[0255] The control IC 50 also includes a communication circuit 135. The communication circuit 135 outputs a pulse signal that is lower than a predetermined level Vstop and higher than a predetermined level Vthstb. This prevents the change in the operating mode of the control IC 50 from being affected even if the voltage level of the terminal STB is changed by the pulse signal.

[0256] The control IC 50 also includes an internal power supply 92 and a drive circuit 102. The control IC 50 controls the internal power supply 92 based on the voltage level (voltage Vstb) of the terminal STB, and when operating in the "shutdown mode," can cause the internal power supply 92 to stop generating the voltage Vreg1. When the internal power supply 92 stops generating the voltage Vreg1, the control IC 50 can stop the operation of circuits that operate by receiving the supply of the voltage Vreg1.

[0257] The DC-DC converter 13 also includes an interface circuit 18a. The interface circuit 18a includes a resistor 151 and NMOS transistors 152, 153, and 157. This allows the interface circuit 18a to apply a voltage that sets the operation mode of the control IC 50 to the terminal STB by turning on and off the NMOS transistors 152, 153, and 157.

[0258] Furthermore, by turning on and off the NMOS transistor 152, the interface circuit 18a can operate the control IC 50 in a "shutdown mode" or a "conduction mode."

[0259] Furthermore, by turning on and off the NMOS transistors 153 and 157, the interface circuit 18a can operate the control IC 50 in a "normal mode" or a "low standby power mode."

[0260] The above-described embodiments are intended to facilitate understanding of the present invention and are not intended to limit the present invention. Furthermore, the present invention may be modified or improved without departing from the spirit thereof, and the present invention includes equivalents thereof. [Explanation of symbols]

[0261] 10 Power supply 11 Switch 12 AC-DC converter 13 DC-DC converter 14 Load 15a, 15b Microcontroller 16,30,31,42,61,63,64,67,68,150,154,159,162,171,174,183,184 Capacitors 17 Photodiode 18a, 18b Interface circuit 20, 21, 40, 41, 60, 173 diodes 22 Power factor correction circuit 32, 33, 152, 153, 157, 160, 176 NMOS transistors 34,172 Trans 35 control blocks 43 Constant voltage circuit 44 Light-emitting diode 62 Phototransistor 65,66,74,75,142,151,155,156,158,161,180,181,182 Resistance 70 Starter circuit 71,131 current source 72 Zener diode 73 Judgment circuit 76 Setting circuit 80 Constant voltage source 81,120 Control circuit 82 Charging circuit 90 Reset Circuit 91 Low voltage protection circuit 92,93 Internal power supply 100 Load detection circuit 101,211 Oscillator circuit 102,190 Drive circuit 110 Digital Department 111 Analog section 121 Judgment circuit 130 Discharge circuit 132 Analog-to-Digital Converter 133 Clamp Circuit 134,212 Comparators 135 Communication Circuit 140 operational amplifiers 141 PMOS transistor 170 Full wave rectifier circuit 191 Signal detection circuit 200 Zero current detection circuit 201 Delay Circuit 202 Pulse Circuit 203 Turn-on timer circuit 204,213 OR circuit 210 Error amplifier circuit 220 SR Flip-Flop 221 Buffer Circuit

Claims

1. An integrated circuit that switches and drives a power transistor of a power supply circuit to generate an output voltage of a target level from the power supply circuit, a first terminal to which an external circuit for setting an operation mode of the integrated circuit is connected; a mode selection circuit that selects, based on a voltage level of the first terminal, whether the integrated circuit is to operate in a shutdown mode in which no switching operation is performed, a normal mode in which continuous switching operation is performed, or a low standby power mode in which switching operation periods and stop operation periods are alternately repeated; Equipped with The mode selection circuit an integrated circuit that operates the integrated circuit in the shutdown mode when the voltage level of the first terminal is in a first voltage range, operates the integrated circuit in the normal mode when the voltage level is in a second voltage range different from the first voltage range, and operates the integrated circuit in the low standby power mode when the voltage level is in a third voltage range different from the first and second voltage ranges.

2. 10. The integrated circuit of claim 1, a voltage level of the first voltage range being higher than a voltage level of the second voltage range; the voltage level of the second voltage range is higher than the voltage level of the third voltage range; Integrated circuit.

3. 3. An integrated circuit according to claim 2, The mode selection circuit a first mode determination circuit that determines to operate the integrated circuit in the shutdown mode when the voltage level is within the first voltage range; a second mode determination circuit that determines to operate the integrated circuit in the normal mode when the voltage level is in the second voltage range, and determines to operate the integrated circuit in the low standby power mode when the voltage level is in the third voltage range; 1. An integrated circuit comprising:

4. 4. An integrated circuit according to claim 2 or claim 3, an oscillation circuit that outputs an oscillation signal according to an operation mode of the integrated circuit; a load detection circuit for detecting a load state of the power supply circuit; a setting circuit that sets the state of the oscillation circuit based on the voltage level during a state setting period in which the integrated circuit sets the state of the oscillation circuit while starting up, so that the oscillation circuit operates in either an external mode in which the oscillation circuit operates based on the voltage level or an internal mode in which the oscillation circuit operates based on an output from the load detection circuit; Equipped with the oscillation circuit outputs the oscillation signal corresponding to the voltage level when the oscillation circuit operates in the external mode, and outputs the oscillation signal corresponding to the output from the load detection circuit when the oscillation circuit operates in the internal mode. Integrated circuit.

5. 5. An integrated circuit according to claim 4, a signal output circuit that outputs a signal with an amplitude level in the second voltage range to the first terminal; 1. An integrated circuit comprising:

6. The integrated circuit according to any one of claims 1 to 5, a first power supply voltage generation circuit that stops generating a first power supply voltage when the integrated circuit is operated in the shut-down mode, and generates the first power supply voltage when the integrated circuit is operated in the normal mode or the low standby power mode; a drive circuit to which the first power supply voltage is supplied and which drives the power transistor in the switching manner; 1. An integrated circuit comprising:

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