Nitride semiconductor device

Abstract

To realize a low on-resistance.SOLUTION: A nitride semiconductor device 10A includes a chip 20A including: a nitride semiconductor layer 34 disposed on a first substrate surface 32A of a semiconductor substrate 32 and including an element region A1 in which a transistor is formed and a peripheral region A2 surrounding the element region A1; a first insulating layer 36 disposed on the nitride semiconductor layer 34; and a second insulating layer 38 disposed on a second substrate surface 32B of the semiconductor substrate 32. The chip 20A includes: a first pad 60 disposed on a front surface 36A of the first insulating layer 36 at a position overlapping the peripheral region A2 in plan view; a second pad 70 disposed on a front surface 38A of the second insulating layer 38 at a position overlapping the first pad 60; and a through wiring 50 disposed in a through hole 40 disposed at a position overlapping the first pad 60 and the second pad 70 and electrically connecting the first pad 60 and the second pad 70.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to nitride semiconductor devices. [Background technology]

[0002] Currently, high electron mobility transistors (HEMTs) using group III nitride semiconductors (hereinafter sometimes simply referred to as "nitride semiconductors") such as gallium nitride (GaN) are being commercialized. Patent Document 1 discloses an example of a nitride semiconductor device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-73506

[0004] [overview] In some nitride semiconductor devices, it is desirable to reduce the on-resistance.

[0005] a nitride semiconductor device according to one embodiment of the present disclosure, comprising: a semiconductor substrate including a first substrate surface and a second substrate surface opposite the first substrate surface; a nitride semiconductor layer disposed on the first substrate surface, the nitride semiconductor layer including an element region in which a transistor is formed, and a peripheral region surrounding the element region; a first insulating layer disposed on the nitride semiconductor layer; and a second insulating layer disposed on the second substrate surface, wherein the chip includes: a first pad disposed on a surface of the first insulating layer at a position overlapping with the peripheral region in a planar view; a second pad disposed on a surface of the second insulating layer at a position overlapping with the first pad in a planar view; a through hole disposed at a position overlapping with the first pad and the second pad in a planar view, the through hole penetrating the first insulating layer, the nitride semiconductor layer, the semiconductor substrate, and the second insulating layer; and a through wiring disposed in the through hole, electrically connecting the first pad and the second pad. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a schematic plan view of an exemplary nitride semiconductor device according to the first embodiment. [Figure 2] FIG. 2 is a schematic plan view of the nitride semiconductor device of FIG. 1 as viewed from above the device. [Figure 3] FIG. 3 is a schematic cross-sectional view taken along line F3-F3 in FIG. [Figure 4] FIG. 4 is a schematic cross-sectional view taken along line F4-F4 in FIG. [Figure 5] FIG. 5 is a schematic cross-sectional view taken along line F5-F5 in FIG. [Figure 6] FIG. 6 is a schematic cross-sectional view taken along line F6-F6 in FIG. [Figure 7] FIG. 7 is an enlarged view of the nitride semiconductor device in region F7 of FIG. [Figure 8] FIG. 8 is an enlarged view of the nitride semiconductor device in region F8 of FIG. [Figure 9] FIG. 9 is a schematic cross-sectional view taken along line F9-F9 in FIG. [Figure 10] FIG. 10 is a schematic cross-sectional view taken along line F10-F10 in FIG. [Figure 11] FIG. 11 is a schematic side view showing a nitride semiconductor device including a plurality of chips of FIG. [Figure 12] FIG. 12 is an explanatory diagram for explaining the configuration of the nitride semiconductor device of FIG. [Figure 13] FIG. 13 is a schematic plan view of an exemplary nitride semiconductor device according to the second embodiment. [Figure 14] FIG. 14 is a schematic plan view of the nitride semiconductor device of FIG. 13 as viewed from the mounting surface. [Figure 15] FIG. 15 is a schematic cross-sectional view taken along line F15-F15 in FIG. [Figure 16] FIG. 16 is a schematic cross-sectional view taken along line F16-F16 in FIG. [Figure 17] FIG. 17 is a schematic cross-sectional view of a nitride semiconductor device according to a modified example. [Figure 18] FIG. 18 is a schematic plan view of a nitride semiconductor device according to a modified example. [Figure 19] FIG. 19 is a schematic side view showing a laminated body of a nitride semiconductor device according to a modified example.

[0007] [Detailed explanation] Hereinafter, several embodiments of nitride semiconductor devices according to the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of description, components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered to limit the present disclosure. Terms such as "first," "second," and "third" in the present disclosure are used merely to distinguish between objects and are not used to rank the objects.

[0008] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0009] The phrase "at least one" as used herein means "one or more" of the desired options. As an example, the phrase "at least one" as used herein means "only one option" or "both of two options" when the number of options is two. As another example, the phrase "at least one" as used herein means "only one option" or "any combination of two or more options" when the number of options is three or more.

[0010] (First embodiment) An illustrative nitride semiconductor device 10A according to the first embodiment will be described below with reference to FIGS.

[0011] [1. Structure of nitride semiconductor device] FIG. 1 shows a schematic planar structure of a nitride semiconductor device 10A. FIG. 2 shows a schematic planar structure of the nitride semiconductor device 10A of FIG. 1 viewed from the opposite side to that of FIG. 1. FIG. 2 shows the nitride semiconductor device 10A of FIG. 1 inverted about the Y-axis. FIG. 3 is a schematic cross-sectional view taken along line F3-F3 of FIG. 1. FIG. 4 is a schematic cross-sectional view taken along line F4-F4 of FIG. 1. FIG. 5 is a schematic cross-sectional view taken along line F5-F5 of FIG. 1.

[0012] The term "plan view" used in the present disclosure refers to viewing the nitride semiconductor device 10A and its related configuration in the Z-axis direction of the mutually orthogonal X, Y, and Z axes shown in Fig. 1. In the present disclosure, the X-axis direction corresponds to the "first direction," and the Y-axis direction corresponds to the "second direction" orthogonal to the first direction in the plan view. For ease of explanation, the +Z direction is defined as up, the -Z direction as down, the +X direction as right, and the -X direction as left in the nitride semiconductor device 10A shown in Fig. 1 .

[0013] As shown in FIGS. 1 to 5, a nitride semiconductor device 10A includes a chip 20A. Chip 20A includes first chip surface 21 and second chip surface 22 opposite first chip surface 21. In one example, chip 20A has a rectangular flat plate shape. In one example, chip 20A has a rectangular shape in which the dimension in the Y-axis direction is larger than the dimension in the X-axis direction in a plan view. Chip 20A includes multiple chip side surfaces 23, 24, 25, and 26. The multiple chip side surfaces 23 to 26 are surfaces connecting first chip surface 21 and second chip surface 22. In one example, the multiple chip side surfaces 23 to 26 are orthogonal to first chip surface 21 and second chip surface 22. First chip side surface 23 and second chip side surface 24 face in opposite directions from each other in the X-axis direction. Third chip side surface 25 and fourth chip side surface 26 face in opposite directions from each other in the Y-axis direction.

[0014] (semiconductor substrate) As shown in FIGS. 3 to 5, the chip 20A includes a semiconductor substrate 32. The chip 20A may be referred to as a semiconductor chip. The semiconductor substrate 32 includes a first substrate surface 32A and a second substrate surface 32B opposite to the first substrate surface 32A. In one example, the semiconductor substrate 32 is a silicon (Si) substrate. The semiconductor substrate 32 may be a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, or a sapphire substrate. The thickness of the semiconductor substrate 32 may be, for example, not less than 100 μm and not more than 1500 μm.

[0015] (nitride semiconductor layer) The chip 20A includes a nitride semiconductor layer 34. The nitride semiconductor layer 34 is disposed on a first substrate surface 32A of a semiconductor substrate 32. The nitride semiconductor layer 34 includes a first semiconductor surface 34A and a second semiconductor surface 34B opposite to the first semiconductor surface 34A. The first semiconductor surface 34A of the nitride semiconductor layer 34 faces the same direction as the first substrate surface 32A of the semiconductor substrate 32. The second semiconductor surface 34B of the nitride semiconductor layer 34 is in contact with the first substrate surface 32A of the semiconductor substrate 32. It can be said that the nitride semiconductor layer 34 is disposed on the semiconductor substrate 32. The nitride semiconductor layer 34 may include a nitride semiconductor, a metal material, an insulating material, etc.

[0016] (First insulating layer, second insulating layer) The chip 20A includes a first insulating layer 36 and a second insulating layer 38. The first insulating layer 36 is disposed on the nitride semiconductor layer 34. The first insulating layer 36 covers the first semiconductor surface 34A of the nitride semiconductor layer 34. The first insulating layer 36 is in contact with the first semiconductor surface 34A of the nitride semiconductor layer 34. The surface 36A of the first insulating layer 36 forms the first chip surface 21 of the chip 20A. The first insulating layer 36 may be made of a material including, for example, any one of silicon dioxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), alumina (AlO), aluminum nitride (AlN), and aluminum oxynitride (AlON). In one example, the first insulating layer 36 is made of a material including SiO.

[0017] The second insulating layer 38 is disposed on the second substrate surface 32B of the semiconductor substrate 32. The second insulating layer 38 covers the second substrate surface 32B of the semiconductor substrate 32. The second insulating layer 38 is in contact with the second substrate surface 32B of the semiconductor substrate 32. A surface 38A of the second insulating layer 38 constitutes the second chip surface 22 of the chip 20A. The second insulating layer 38 may be made of a material including, for example, any one of SiO2, SiN, SiON, Al2O3, AlN, and AlON. In one example, the second insulating layer 38 is made of a material including SiO2.

[0018] 1 and 2, the chip 20A includes an element region A1 and a peripheral region A2 that surrounds the element region A1 in a planar view. In the example of Fig. 1 and Fig. 2, the element region A1 is located in the central part of the chip 20A in a planar view, and the peripheral region A2 is located in a frame shape on the outer periphery of the chip 20A.

[0019] The chip 20A includes a transistor 100 formed in the nitride semiconductor layer 34. The transistor 100 is formed in the element region A1. The transistor 100 is not formed in the peripheral region A2. In other words, the element region A1 is a region where the transistor 100 is formed, and the peripheral region A2 is a region where the transistor 100 is not formed. It can be said that the nitride semiconductor layer 34 includes the element region A1 where the transistor 100 is formed, and the peripheral region A2 that surrounds the element region A1.

[0020] (First pad) 1 and 3 to 5, chip 20A includes first pads 60 disposed on surface 36A of first insulating layer 36. As shown in Fig. 1, first pads 60 are disposed so as to overlap peripheral region A2 in plan view.

[0021] 1, the first pad 60 includes a first source pad 62, a first drain pad 64, and a first gate pad 66. The first source pad 62, the first drain pad 64, and the first gate pad 66 can be made of any conductive material including, for example, at least one of copper (Cu), aluminum (Al), an AlCu alloy, tungsten (W), titanium (Ti), and titanium nitride (TiN). In one example, the first source pad 62, the first drain pad 64, and the first gate pad 66 are made of a material including Cu.

[0022] The first source pad 62 is an electrode pad electrically connected to the source electrode 128 of the transistor 100. In the example of FIG. 1, the first source pad 62 is arranged in the peripheral region A2 alongside the element region A1 on the right side (+X direction side) of the element region A1. The first source pad 62 is arranged between the element region A1 and the second chip side surface 24 in a plan view. The first source pad 62 has a rectangular shape extending in the Y-axis direction in a plan view. The first source pad 62 can be formed with dimensions along the Y-axis direction that are approximately the same as the dimensions of the element region A1.

[0023] The first drain pad 64 is an electrode pad electrically connected to the drain electrode 130 of the transistor 100. In the example of FIG. 1, the first drain pad 64 is arranged in the peripheral region A2 alongside the element region A1 on the left side (negative X-direction side) of the element region A1. The first drain pad 64 is arranged between the element region A1 and the first chip side surface 23 in a plan view. The first drain pad 64 has a rectangular shape extending in the Y-axis direction in a plan view. The first drain pad 64 can be formed with approximately the same dimensions as the element region A1 along the Y-axis direction. The first source pad 62 and the first drain pad 64 are arranged on either side of the element region A1.

[0024] The first gate pad 66 is an electrode pad electrically connected to the gate electrode 124 of the transistor 100. In the example of FIG. 1, the first gate pad 66 includes two first gate pads 66A and 66B. The first gate pad 66A is located above (on the +Y direction side of) the first source pad 62, i.e., above the element region A1, and is arranged alongside the first source pad 62 in the peripheral region A2. The first gate pad 66B is located below (on the -Y direction side of) the first source pad 62, i.e., below the element region A1, and is arranged alongside the first source pad 62 in the peripheral region A2. In one example, the first gate pads 66A and 66B are arranged with the first source pad 62 sandwiched between them. The first gate pads 66A and 66B may have a rectangular shape extending in the X direction in a plan view. The first gate pads 66A and 66B may protrude in the -X direction beyond the first source pad 62.

[0025] (Second pad) 2 to 5, chip 20A includes second pads 70 disposed on surface 38A of second insulating layer 38. As shown in Fig. 2, second pads 70 are disposed so as to overlap peripheral region A2 in plan view. Second pads 70 are disposed at positions so as to overlap first pads 60 in plan view.

[0026] 2, the second pad 70 includes a second source pad 72, a second drain pad 74, and a second gate pad 76. The second source pad 72, the second drain pad 74, and the second gate pad 76 can be made of any conductive material including, for example, at least one of Cu, Al, an AlCu alloy, W, Ti, and TiN. In one example, the second source pad 72, the second drain pad 74, and the second gate pad 76 are made of a material including Cu.

[0027] The second source pad 72 is disposed at a position overlapping with the first source pad 62 in plan view. In the example of FIG. 2, the second source pad 72 is disposed in the peripheral region A2 alongside the element region A1 on the right side (+X direction side) of the element region A1. The second source pad 72 is disposed between the element region A1 and the second chip side surface 24 in plan view. The second source pad 72 has a rectangular shape extending in the Y-axis direction in plan view. The second source pad 72 can be formed with dimensions along the Y-axis direction that are approximately the same as the dimensions of the element region A1.

[0028] The second drain pad 74 is arranged at a position overlapping with the first drain pad 64 in plan view. In the example of FIG. 2, the second drain pad 74 is arranged in the peripheral region A2 alongside the element region A1 on the left side (negative X-direction side) of the element region A1. The second drain pad 74 is arranged between the element region A1 and the first chip side surface 23 in plan view. The second drain pad 74 has a rectangular shape extending in the Y-axis direction in plan view. The second drain pad 74 can be formed with approximately the same dimensions as the element region A1 along the Y-axis direction. The second source pad 72 and the second drain pad 74 are arranged with the element region A1 sandwiched therebetween.

[0029] The second gate pad 76 is disposed at a position overlapping the first gate pad 66 in a plan view. In the example of Fig. 2, the second gate pad 76 includes two second gate pads 76A and 76B. The second gate pad 76A is disposed at a position overlapping the first gate pad 66A in a plan view, and the second gate pad 76B is disposed at a position overlapping the first gate pad 66B in a plan view.

[0030] The second gate pad 76A is arranged above (on the +Y direction side of) the second source pad 72, i.e., above the element region A1, alongside the second source pad 72 in the peripheral region A2. The second gate pad 76B is arranged below (on the -Y direction side of) the second source pad 72, i.e., below the element region A1, alongside the second source pad 72 in the peripheral region A2. In one example, the second gate pad 76A and the second gate pad 76B are arranged with the second source pad 72 sandwiched between them. The second gate pads 76A and 76B may have a rectangular shape in plan view that has the same length in the X direction as the second source pad 72.

[0031] (1st protective film, 2nd protective film) The nitride semiconductor device 10A may include a first protective film 81 that covers the first chip surface 21 of the chip 20A. In FIG. 1, the first protective film 81 is indicated by a two-dot chain line. The first protective film 81 covers the first chip surface 21 of the chip 20A and the first pad 60. The nitride semiconductor device 10A may include the first protective film 81. The first protective film 81 includes openings 81A to 81C that partially expose the first pad 60. The first protective film 81 may include an opening 81A that exposes a portion of the first source pad 62, an opening 81B that exposes a portion of the first drain pad 64, and an opening 81C that exposes a portion of the first gate pad 66.

[0032] The nitride semiconductor device 10A may include a second protective film 82 that covers the second chip surface 22 of the chip 20A. In FIG. 2, the second protective film 82 is indicated by a two-dot chain line. The second protective film 82 covers the second chip surface 22 of the chip 20A and the second pad 70. The nitride semiconductor device 10A may include the second protective film 82. The second protective film 82 includes openings 82A to 82C that partially expose the second pad 70. The second protective film 82 may include an opening 82A that exposes a portion of the second source pad 72, an opening 82B that exposes a portion of the second drain pad 74, and an opening 82C that exposes a portion of the second gate pad 76.

[0033] (Through hole) 1 to 5, the chip 20A includes a through hole 40. The through hole 40 penetrates the first insulating layer 36, the nitride semiconductor layer 34, the semiconductor substrate 32, and the second insulating layer 38. It can be said that the through hole 40 penetrates the chip 20A from the surface 36A of the first insulating layer 36 to the surface 38A of the second insulating layer 38. The through hole 40 is disposed at a position overlapping the first pad 60 and the second pad 70 in a plan view.

[0034] As shown in FIGS. 1 and 2, the through-holes 40 include a source through-hole 42, a drain through-hole 44, and a gate through-hole 46. 1, the source through-holes 42 are arranged at positions overlapping with the first source pads 62 in a plan view. In one example, the chip 20A includes three source through-holes 42 that overlap with the first source pads 62 in a plan view. In one example, each source through-hole 42 has a rectangular shape in a plan view. As shown in FIG. 2, the source through-holes 42 are arranged at positions overlapping with the second source pads 72 in a plan view.

[0035] 3 and 4, the chip 20A includes an inner surface 42C that constitutes the source through-hole 42. The inner surface 42C of the source through-hole 42 includes the inner surface 32C of the semiconductor substrate 32, the inner surface 34C of the nitride semiconductor layer 34, the inner surface 36C of the first insulating layer 36, and the inner surface 38C of the second insulating layer 38.

[0036] 1, the drain through-holes 44 are arranged at positions overlapping with the first drain pads 64 in a plan view. In one example, the chip 20A includes three drain through-holes 44 overlapping with the first drain pads 64 in a plan view. In one example, each drain through-hole 44 has a rectangular shape in a plan view. As shown in FIG. 2, the drain through-holes 44 are arranged at positions overlapping with the second drain pads 74 in a plan view.

[0037] As shown in FIG. 1 , the source through hole 42 and the drain through hole 44 are arranged on either side of the element region A1. In one example, the source through hole 42 and the drain through hole 44 are arranged in positions that are line-symmetric with respect to the element region A1. In one example, the source through hole 42 and the drain through hole 44 have shapes that are line-symmetric with respect to a central axis L1 that passes through a center point O1 between the source through hole 42 and the drain through hole 44 and extends in the Y-axis direction, which is perpendicular to the X-axis direction in a plan view. The center point O1 may be located at the same position as the center of the element region A1. The central axis L1 that passes through the center point O1 between the source through hole 42 and the drain through hole 44 may be a central axis that passes through the center point of the element region A1 and extends in the Y-axis direction. It can be said that the source through hole 42 and the drain through hole 44 are arranged in positions that are line-symmetric with respect to the central axis L1 that passes through the center point O1 of the element region A1 and extends in the Y-axis direction.

[0038] 3 and 5 , the chip 20A includes an inner surface 44C that configures the drain through-hole 44. The inner surface 44C of the drain through-hole 44 includes the inner surface 32C of the semiconductor substrate 32, the inner surface 34C of the nitride semiconductor layer 34, the inner surface 36C of the first insulating layer 36, and the inner surface 38C of the second insulating layer 38.

[0039] 1, the gate through-hole 46 includes gate through-holes 46A and 46B that are arranged at positions overlapping with the first gate pads 66A and 66B in a plan view. In one example, the gate through-holes 46A and 46B have a rectangular shape in a plan view. As shown in FIG. 2, the gate through-holes 46A and 46B are arranged at positions overlapping with the second gate pads 76A and 76B in a plan view.

[0040] As shown in FIGS. 1 and 4, in one example, the gate through-holes 46A and 46B are arranged with the source through-hole 42 therebetween. 4, the chip 20A includes an inner surface 46C that configures the gate through-hole 46. The inner surface 46C of the gate through-hole 46 includes the inner surface 32C of the semiconductor substrate 32, the inner surface 34C of the nitride semiconductor layer 34, the inner surface 36C of the first insulating layer 36, and the inner surface 38C of the second insulating layer 38.

[0041] (through wiring) As shown in FIGS. 1 to 5, the chip 20A includes a through wire 50 disposed in the through hole 40.

[0042] The through wiring 50 includes a source through wiring 52 , a drain through wiring 54 , and a gate through wiring 56 . The source through wiring 52 is disposed in the source through hole 42. In one example, the source through wiring 52 is made of a conductive material filled in the source through hole 42. The source through wiring 52 can be made of any conductive material including at least one of Cu, Al, an AlCu alloy, W, Ti, and TiN, for example. In one example, the source through wiring 52 is made of a material including Cu.

[0043] The source through wiring 52 is connected to a first source pad 62 on the surface 36A of the first insulating layer 36, and is also connected to a second source pad 72 on the surface 38A of the second insulating layer 38. The source through wiring 52 electrically connects the first source pad 62 and the second source pad 72. The second source pad 72 is electrically connected to the first source pad 62 by the source through wiring 52. The first source pad 62 and the second source pad 72 can be said to be electrode pads electrically connected to the source electrode 128 of the transistor 100.

[0044] The source through-wire 52 contacts the inner surface 42C of the source through-hole 42. The inner surface 42C of the source through-hole 42 includes the inner surface 32C of the semiconductor substrate 32. The source through-wire 52 contacts the inner surface 32C of the semiconductor substrate 32. The source through-wire 52 is electrically connected to the semiconductor substrate 32. Therefore, the first source pad 62 and the second source pad 72 are electrically connected to the semiconductor substrate 32 by the source through-wire 52.

[0045] The drain through wiring 54 is disposed within the drain through hole 44. The source through wiring 52 and the drain through wiring 54 can be said to be disposed on either side of the element region A1. In one example, the source through wiring 52 and the drain through wiring 54 are disposed in positions that are line-symmetric with respect to the element region A1. In one example, the source through hole 42 and the drain through hole 44 have shapes that are line-symmetric with respect to a central axis L1 that passes through a center point O1 between the source through hole 42 and the drain through hole 44 and extends in the Y-axis direction, which is perpendicular to the X-axis direction in a plan view. The center point O1 may be located at the same position as the center of the element region A1. The central axis L1 that passes through the center point O1 between the source through hole 42 and the drain through hole 44 may be a central axis that passes through the center point of the element region A1 and extends in the Y-axis direction. The source through hole 42 and the drain through hole 44 can be disposed in positions that are line-symmetric with respect to the central axis L1 that passes through the center point O1 of the element region A1 and extends in the Y-axis direction.

[0046] In one example, the drain through wiring 54 is made of a conductive material. The drain through wiring 54 can be made of any conductive material including, for example, at least one of Cu, Al, an AlCu alloy, W, Ti, and TiN. In one example, the drain through wiring 54 is made of a material including Cu.

[0047] As shown in FIGS. 3 and 5 , an insulating film 45 is provided on the inner surface 44C of the drain through hole 44. The insulating film 45 covers the entire inner surface 44C of the drain through hole 44. The drain through wiring 54 is surrounded by the insulating film 45 of the drain through hole 44. Therefore, the drain through wiring 54 is not in contact with the inner surface 44C of the drain through hole 44. The drain through wiring 54 is insulated from the semiconductor substrate 32 by the insulating film 45 of the drain through hole 44. The insulating film 45 may be made of a material containing any one of SiO 2 , SiN, SiON, Al 2 O 3 , AlN, and AlON, for example. In one example, the insulating film 45 is made of a material containing SiO 2 .

[0048] The drain through wiring 54 is connected to a first drain pad 64 on the surface 36A of the first insulating layer 36, and is also connected to a second drain pad 74 on the surface 38A of the second insulating layer 38. The drain through wiring 54 electrically connects the first drain pad 64 and the second drain pad 74. The second drain pad 74 is electrically connected to the first drain pad 64 by the drain through wiring 54. The first drain pad 64 and the second drain pad 74 can be said to be electrode pads electrically connected to the drain electrode 130 of the transistor 100.

[0049] The nitride semiconductor device 10A of the first embodiment includes three source through-wires 52 and three drain through-wires 54. In plan view, the total area of the three source through-wires 52 may be equal to the total area of the three drain through-wires 54.

[0050] The three source through wirings 52 are arranged side by side in the Y-axis direction. The three source through wirings 52 may be arranged at equal intervals in the Y-axis direction. The three source through wirings 52 may have the same shape as one another in a planar view. The three drain through wirings 54 are arranged side by side in the Y-axis direction. The three drain through wirings 54 may be arranged at equal intervals in the Y-axis direction. The three drain through wirings 54 may have the same shape as one another in a planar view. The interval between two source through wirings 52 adjacent to one another in the Y-axis direction may be equal to the interval between two drain through wirings 54 adjacent to one another in the Y-axis direction.

[0051] The gate through wiring 56 is disposed in the gate through hole 46. In one example, the gate through wiring 56 is made of a conductive material. The gate through wiring 56 can be made of any conductive material including, for example, at least one of Cu, Al, an AlCu alloy, W, Ti, and TiN. In one example, the gate through wiring 56 is made of a material including Cu.

[0052] 3 and 5, an insulating film 47 is provided on the inner surfaces 46C of the gate through-holes 46A and 46B. The insulating film 47 covers the entire inner surfaces 46C of the gate through-holes 46A and 46B. The insulating film 47 may be made of a material containing, for example, any one of SiO2, SiN, SiON, Al2O3, AlN, and AlON. In one example, the insulating film 47 is made of a material containing SiO2.

[0053] The gate through wiring 56 includes a gate through wiring 56A arranged in the gate through hole 46A and a gate through wiring 56B arranged in the gate through hole 46B. The gate through wirings 56A and 56B are arranged with the source through wiring 52 sandwiched between them.

[0054] The gate through-wires 56A, 56B are surrounded by the insulating film 47 of the gate through-holes 46A, 46B. Therefore, the gate through-wires 56A, 56B do not contact the inner surfaces 46C of the gate through-holes 46A, 46B. The gate through-wires 56A, 56B are insulated from the semiconductor substrate 32 by the insulating film 47 of the gate through-holes 46A, 46B.

[0055] The gate through-wires 56A, 56B are connected to the first gate pads 66A, 66B on the surface 36A of the first insulating layer 36, and are also connected to the second gate pads 76A, 76B on the surface 38A of the second insulating layer 38. The gate through-wires 56A, 56B electrically connect the first gate pads 66A, 66B and the second gate pads 76A, 76B. The second gate pads 76A, 76B are electrically connected to the first gate pads 66A, 66B by the gate through-wires 56A, 56B. The first gate pads 66A, 66B and the second gate pads 76A, 76B can be considered electrode pads electrically connected to the gate electrode 124 of the transistor 100.

[0056] In plan view, the area of the gate through wirings 56A and 56B may be smaller than the area of the source through wiring 52. The area of the gate through wirings 56A and 56B may be smaller than the area of the drain through wiring 54.

[0057] [2. Transistor structure] Fig. 6 is a schematic cross-sectional view of a portion of the nitride semiconductor device 10A taken along line F6-F6 in Fig. 1, illustrating an example of a schematic cross-sectional structure of the transistor 100. Note that Fig. 6 illustrates components related to the configuration of the transistor 100.

[0058] 6, the transistor 100 is a high electron mobility transistor (HEMT) using a nitride semiconductor. The transistor 100 is formed in a nitride semiconductor layer 34 disposed on a semiconductor substrate 32.

[0059] The nitride semiconductor layer 34 includes a buffer layer 114 disposed on the semiconductor substrate 32, an electron transit layer 116 disposed on the buffer layer 114, and an electron supply layer 118 disposed on the electron transit layer 116.

[0060] The buffer layer 114 may be made of any material capable of suppressing wafer warpage and cracks due to mismatch in thermal expansion coefficients between the semiconductor substrate 32 and the electron transit layer 116. The buffer layer 114 includes one or more nitride semiconductor layers made of nitride semiconductors. The buffer layer 114 may include, for example, at least one of an AlN layer, an aluminum gallium nitride (AlGaN) layer, and a graded AlGaN layer having different Al compositions. For example, the buffer layer 114 may be made of a single AlN film, a single AlGaN film, a film having an AlGaN / GaN superlattice structure, a film having an AlN / AlGaN superlattice structure, or a film having an AlN / GaN superlattice structure.

[0061] In one example, the buffer layer 114 includes a first buffer layer that is an AlN layer formed on the semiconductor substrate 32, and a second buffer layer that is an AlGaN layer formed on the AlN layer (first buffer layer). The first buffer layer may be an AlN layer having a thickness of, for example, 200 nm, and the second buffer layer may be a graded AlGaN layer having a thickness of, for example, 300 nm. Note that, in order to suppress leakage current in the buffer layer 114, impurities may be introduced into a portion of the buffer layer 114 to make the buffer layer 114 semi-insulating except for the surface region. In this case, the impurity is, for example, carbon (C) or iron (Fe). The impurity concentration is, for example, 4×10 16 cm -3 It can be more than that.

[0062] The electron transit layer 116 is made of a nitride semiconductor. The electron transit layer 116 may be, for example, a GaN layer. The thickness of the electron transit layer 116 may be, for example, 0.5 μm or more and 2 μm or less. In order to suppress leakage current in the electron transit layer 116, impurities may be introduced into a portion of the electron transit layer 116 to make the electron transit layer 116 semi-insulating except for the surface region. In this case, the impurity may be, for example, C. The impurity concentration may be, for example, 4×10 16 cm -3 It can be more than that.

[0063] The electron transit layer 116 may include multiple GaN layers with different impurity concentrations, such as a C-doped GaN layer and a non-doped GaN layer. In this case, the C-doped GaN layer is formed on the buffer layer 114. The thickness of the C-doped GaN layer may be, for example, 0.3 μm or more and 2 μm or less. The C concentration in the C-doped GaN layer may be, for example, 5×10 17 cm -3 Over 9x10 19 cm -3The following can be achieved. The non-doped GaN layer is formed on the C-doped GaN layer. The thickness of the non-doped GaN layer can be, for example, 0.05 μm or more and 0.4 μm or less. The non-doped GaN layer is in contact with the electron supply layer 118. In one example, the electron traveling layer 116 includes a C-doped GaN layer with a thickness of 0.4 μm and a non-doped GaN layer with a thickness of 0.4 μm. The C concentration in the C-doped GaN layer is about 2×10 19 cm -3 −3

[0064] The electron supply layer 118 is composed of a nitride semiconductor having a larger bandgap than the electron traveling layer 116. The electron supply layer 118 may be, for example, an AlGaN layer. In a nitride semiconductor, the larger the Al composition, the larger the bandgap. Therefore, the electron supply layer 118, which is an AlGaN layer, has a larger bandgap than the electron traveling layer 116, which is a GaN layer. In one example, the electron supply layer 118 is composed of Al X Ga 1-X X

[0065] N, where X is, for example, 0 < X < 0.4, and more preferably 0.1 < X < 0.3. The thickness of the electron supply layer 118 can be, for example, 5 nm or more and 20 nm or less.

[0066] The transistor 100 includes a gate layer 122 formed on the electron supply layer 118, a gate electrode 124 formed on the gate layer 122, and an insulating layer 126 covering the electron supply layer 118, the gate layer 122, and the gate electrode 124. The gate electrode 124 is formed on a portion of the gate layer 122. The insulating layer 126 includes a source opening 126A and a drain opening 126B provided on both sides of the gate layer 122 in the X-axis direction and spaced apart from the gate layer 122. That is, the source opening 126A and the drain opening 126B are spaced apart from each other in the X-axis direction.

[0067] The gate layer 122 is located between the source opening 126A and the drain opening 126B. The gate layer 122 is disposed closer to the source opening 126A in the X-axis direction than the drain opening 126B. That is, the distance between the gate layer 122 and the drain opening 126B in the X-axis direction is longer than the distance between the gate layer 122 and the source opening 126A in the X-axis direction.

[0068] The gate layer 122 is made of a nitride semiconductor. For example, the gate layer 122 can be made of any material having a band gap smaller than that of the electron supply layer 118, which is an AlGaN layer. In the first embodiment, the gate layer 122 is made of a nitride semiconductor containing acceptor-type impurities. In one example, the gate layer 122 is a GaN layer (p-type GaN layer) doped with acceptor-type impurities. The acceptor-type impurities can include at least one of zinc (Zn), magnesium (Mg), and C. The maximum concentration of the acceptor-type impurities in the gate layer 122 is, for example, 1×10 18 cm -3 More than 1×10 20 cm -3 The following is the result.

[0069] In the present disclosure, the nitride semiconductor constituting the electron transit layer 116 corresponds to a first nitride semiconductor, the nitride semiconductor constituting the electron supply layer 118 corresponds to a second nitride semiconductor, and the nitride semiconductor constituting the gate layer 122 corresponds to a third nitride semiconductor.

[0070] The inclusion of acceptor-type impurities in the gate layer 122 raises the energy levels of the electron transit layer 116 and the electron supply layer 118. As a result, the energy level of the conduction band of the electron transit layer 116 near the heterojunction interface between the electron transit layer 116 and the electron supply layer 118 in the region immediately below the gate layer 122 is approximately the same as or higher than the Fermi level. Therefore, at zero bias, when no voltage is applied to the gate electrode 124, the 2DEG 120 is not formed in the region of the electron transit layer 116 immediately below the gate layer 122. On the other hand, the 2DEG 120 is formed in the region of the electron transit layer 116 other than the region immediately below the gate layer 122.

[0071] In this way, the presence of the gate layer 122 doped with acceptor-type impurities causes the channel formed by the 2DEG 120 to disappear in the region directly below the gate layer 122, thereby achieving normally-off operation of the transistor 100. When an appropriate on-voltage is applied to the gate electrode 124, a channel formed by the 2DEG 120 is formed in the electron transit layer 116 in the region directly below the gate electrode 124, thereby establishing electrical conduction between the source and drain.

[0072] The shape of the gate layer 122 is not particularly limited. In the example of FIG. 6, the gate layer 122 has a step structure. For example, the gate layer 122 includes a gate layer main body portion 122A, a first extension portion 122B extending from a first side surface (left side surface in FIG. 6) of the gate layer main body portion 122A toward the source opening 126A, and a second extension portion 122C extending from a second side surface (right side surface in FIG. 6) of the gate layer main body portion 122A toward the drain opening 126B. The gate electrode 124 is located on the gate layer main body portion 122A. The gate layer main body portion 122A may have any cross-sectional shape, such as a rectangular shape, a trapezoidal shape, or a ridge shape, in the XZ plane. The thickness of the gate layer main body 122A, that is, the distance from the upper surface of the gate layer main body 122A to the lower surface of the gate layer main body 122A (the lower surface of the gate layer 122 in contact with the electron supply layer 118) can be 80 nm or more and 160 nm or less.

[0073] The first extension portion 122B extends from the gate layer main body portion 122A toward the source opening 126A while being spaced apart from the source opening 126A. The second extension portion 122C extends from the gate layer main body portion 122A toward the drain opening 126B while being spaced apart from the drain opening 126B. In the example of FIG. 6, the second extension portion 122C is formed longer in the X-axis direction than the first extension portion 122B. However, the first extension portion 122B and the second extension portion 122C may have the same length. The length of the first extension portion 122B in the X-axis direction may be, for example, 0.2 μm or more and 0.3 μm or less. The length of the second extension portion 122C in the X-axis direction may be, for example, 0.2 μm or more and 1.5 μm or less.

[0074] The gate electrode 124 is composed of one or more metal layers. For example, the gate electrode 124 is a TiN layer. Alternatively, the gate electrode 124 may include a first metal layer made of a material containing Ti and a second metal layer made of a material containing TiN, stacked on the first metal layer. When the gate electrode 124 is made of TiN, for example, the gate electrode 124 forms a Schottky junction with the gate layer 122. The gate electrode 124 is formed in an area smaller than the gate layer main body 122A in a planar view. However, the gate electrode 124 may be formed in the same area as the gate layer main body 122A in a planar view. The thickness of the gate electrode 124 may be, for example, 60 nm to 200 nm.

[0075] The insulating layer 126 is formed on the electron supply layer 118. The insulating layer 126 is part of the first insulating layer 36 that covers the transistor 100. The insulating layer 126 is also called a passivation layer. The insulating layer 126 covers the gate layer 122 and the gate electrode 124. The thickness of the insulating layer 126 can be, for example, 80 nm or more and 160 nm or less.

[0076] The transistor 100 further includes a source electrode 128 in contact with the electron supply layer 118 through the source opening 126A, and a drain electrode 130 in contact with the electron supply layer 118 through the drain opening 126B.

[0077] The source electrode 128 and the drain electrode 130 are composed of one or more metal layers (e.g., Ti, Al, AlCu, TiN, etc.). The source electrode 128 includes a source contact portion 128A that contacts the electron supply layer 118 through a source opening 126A and makes ohmic contact with the 2DEG 120 directly below the source contact portion 128A through the source opening 126A. The drain electrode 130 includes a drain contact portion 130A that contacts the electron supply layer 118 through a drain opening 126B and makes ohmic contact with the 2DEG 120 directly below the drain contact portion 130A through the drain opening 126B.

[0078] Transistor 100 may further include a field plate electrode 131 formed on insulating layer 126. Field plate electrode 131 extends into a region between gate layer 122 and drain electrode 130, and is spaced apart from drain electrode 130. Thus, field plate electrode 131 includes end 131A located between drain electrode 130 (drain opening 126B) and gate layer 122 in a plan view.

[0079] The field plate electrode 131 is electrically connected to the source electrode 128. In the example of FIG. 6, the field plate electrode 131 is formed integrally and continuously with the source electrode 128. In the case of such an integrated electrode, the electrode portion embedded in the source opening 126A and / or the electrode portion located in the vicinity of the source opening 126A may correspond to the source electrode 128. The field plate electrode 131 may correspond to the remaining portion of the integrated electrode other than the source electrode 128. The field plate electrode 131 serves to reduce electric field concentration near the end of the gate electrode 124 when a drain voltage is applied to the drain electrode 130 in an off state that causes the channel of the 2DEG 120 in the electron transit layer 116 directly below the gate layer 122 to disappear.

[0080] Fig. 7 is an enlarged view of a portion of the nitride semiconductor device 10A in region F7 of Fig. 1, and Fig. 8 is an enlarged view of a portion of the nitride semiconductor device 10A in region F8 of Fig. 7. Note that Fig. 8 shows the portion of the source electrode 128 buried in the source opening 126A, the portion of the drain electrode 130 buried in the drain opening 126B, and the gate electrode 124 so that they can be seen through.

[0081] As shown in FIG. 8, the source electrode 128, the drain electrode 130, and the gate electrode 124 extend elongatedly in the Y-axis direction. Although not shown, the gate layer 122 and the field plate electrode 131 also extend elongatedly in the Y-axis direction. That is, the transistor 100 (HEMT) shown in FIG. 6 is formed continuously in the Y-axis direction. Note that a plurality of transistors 100 (unit transistors) are arranged in an array in the element region A1, one of which is shown in FIG. 6. For example, a plurality of transistors 100 are arranged side by side in the element region A1 along both the X-axis direction and the Y-axis direction. Note that, although not shown in FIG. 8, the end of the gate electrode 124 protrudes from the element region A1 and is located in the peripheral region A2.

[0082] [3. Various wiring structures and peripheral structures] 8, the nitride semiconductor device 10A includes a plurality of source wirings 142 extending from the first source pad 62, a plurality of drain wirings 144 extending from the first drain pad 64, and a gate wiring 146 extending from the first gate pad 66. The source wirings 142, the drain wirings 144, and the gate wiring 146 are formed on the surface 36A of the first insulating layer 36. Note that the source wirings 142 and the drain wirings 144 are not shown in FIG.

[0083] The source wiring 142 extends in a comb shape in the X-axis direction from the first source pad 62 toward the first drain pad 64. The source wiring 142 is provided across both the peripheral region A2 and the element region A1, and the tip of the source wiring 142 is located in the element region A1. The source wiring 142 is arranged at equal intervals in the Y-axis direction. The source wiring 142 may be formed integrally with the first source pad 62.

[0084] The drain wiring 144 extends in a comb shape in the X-axis direction from the first drain pad 64 toward the first source pad 62. The drain wiring 144 is provided across both the peripheral region A2 and the element region A1, and the tip of the drain wiring 144 is located in the element region A1. The drain wiring 144 is arranged at equal intervals in the Y-axis direction. The source wiring 142 and the drain wiring 144 are arranged alternately one by one in the Y-axis direction, spaced apart from each other. The drain wiring 144 may be formed integrally with the first drain pad 64.

[0085] 1, the gate wiring 146 includes a first gate wiring 146A and a second gate wiring 146B. The first gate wiring 146A and the second gate wiring 146B electrically connect the first gate pad 66A and the first gate pad 66B. The first gate wiring 146A and the second gate wiring 146B are arranged as a whole in the shape of a frame surrounding the element region A1, the first source pad 62, and the first drain pad 64. The first gate wiring 146A and the second gate wiring 146B may be formed integrally with the first gate pads 66A and 66B.

[0086] 9 is a schematic cross-sectional view of a portion of the nitride semiconductor device 10A taken along line F9-F9 in FIG. 8, and FIG. 10 is a schematic cross-sectional view of a portion of the nitride semiconductor device 10A taken along line F10-F10 in FIG. 8. Note that, for ease of understanding, the cross-sectional structure of the transistor 100 is shown in FIGS. 9 and 10 in a simplified manner compared to the cross-sectional structure in FIG. 6. For example, only the portion of the gate layer 122 directly below the gate electrode 124 is shown in a simplified manner. The shape of the integrated electrode of the source electrode 128 and the field plate electrode 131 is also simplified. The semiconductor substrate 32 and the buffer layer 114 are not shown.

[0087] 9 and 10, the electron supply layer 118 is not formed in the peripheral region A2. The electron transit layer 116 located in the peripheral region A2 is provided as a peripheral portion made of a first nitride semiconductor (e.g., GaN) with the upper portion of the electron transit layer 116 removed, and the first insulating layer 36 is formed in contact with this peripheral portion. Because the electron supply layer 118 is not present on the electron transit layer 116 provided as the peripheral portion, the 2DEG 120 is not generated in the peripheral portion.

[0088] 8 and 9, source wiring 142 includes an overlapping portion 142A that overlaps with source electrode 128 (and field plate electrode 131 formed integrally therewith) in a plan view. A via conductor Vs that penetrates first insulating layer 36 and electrically connects source wiring 142 and source electrode 128 is formed in first insulating layer 36 between source wiring 142 and source electrode 128 at a position corresponding to this overlapping portion 142A.

[0089] 8 and 10 , the drain wiring 144 has an overlapping portion 144A that overlaps with the drain electrode 130 in a plan view. A via conductor Vd that penetrates the first insulating layer 36 and electrically connects the drain wiring 144 and the drain electrode 130 is provided in the first insulating layer 36 between the drain wiring 144 and the drain electrode 130 at a position corresponding to the overlapping portion 144A.

[0090] Although not shown in the figure, the gate wiring 146 includes an overlapping portion that overlaps in a planar view with the end of the gate electrode 124 that protrudes into the peripheral region A2, and is electrically connected to the gate electrode 124 by a via that penetrates the first insulating layer 36 at a position corresponding to this overlapping portion.

[0091] As shown in FIGS. 8 to 10, a first outer peripheral guard ring 151 and a second outer peripheral guard ring 152 each having a rectangular frame shape are provided on the outer periphery of the element region A1 to surround the center of the element region A1.

[0092] An example of the first outer peripheral guard ring 151 includes a semiconductor layer 151A provided on and in contact with the electron supply layer 118, a first conductive layer 151B provided on and in contact with the semiconductor layer 151A, and a second conductive layer 151C embedded in the first insulating layer 36 above the first conductive layer 151B. The semiconductor layer 151A is made of, for example, the same material as the gate layer 122. The first conductive layer 151B is made of, for example, the same material as the gate electrode 124. The second conductive layer 151C is made of, for example, the same material as the source electrode 128 and the drain electrode 130.

[0093] The second outer peripheral guard ring 152 is provided to surround the first outer peripheral guard ring 151 on the outer periphery side of the element region A1 relative to the first outer peripheral guard ring 151. An example of the second outer peripheral guard ring 152 is a conductive layer provided on and in contact with the electron supply layer 118. The second outer peripheral guard ring 152 is made of, for example, the same material as the source electrode 128 and the drain electrode 130.

[0094] [4. Nitride Semiconductor Device Including Multiple Chips] Fig. 11 is a schematic side view showing a nitride semiconductor device 200 including a plurality of chips 20A of Fig. 1. Fig. 12 is an explanatory diagram for explaining the configuration of the nitride semiconductor device 200 of Fig. 11. In Figs. 11 and 12, the first protective film 81 and the second protective film 82 are omitted in order to clarify the first pad 60 and the second pad 70. In Figs. 11 and 12, the first gate pad 66 and the second gate pad 76 are omitted for convenience.

[0095] The nitride semiconductor device 200 shown in FIG. 11 includes two chips 20A, a first chip 210 and a second chip 220. Both the first chip 210 and the second chip 220 have the same configuration as the chip 20A described above. That is, the first chip 210 and the second chip 220 include a first pad 60 arranged on a first chip surface 21 and a second pad 70 arranged on a second chip surface 22. The first pad 60 includes a first source pad 62, a first drain pad 64, and a first gate pad 66. The second pad 70 includes a second source pad 72, a second drain pad 74, and a second gate pad 76.

[0096] In the first chip 210 and the second chip 220, the first source pad 62 is electrically connected to the second source pad 72 by the source through wiring 52, and the first drain pad 64 is electrically connected to the second drain pad 74 by the drain through wiring 54. Although not shown, in the first chip 210 and the second chip 220, the first gate pad 66 is electrically connected to the second gate pad 76 by the gate through wiring 56.

[0097] The first chip 210 and the second chip 220 are arranged so that the second chip surface 22 of the first chip 210 faces the first chip surface 21 of the second chip 220. Therefore, the second pad 70 of the first chip 210 faces the first pad 60 of the second chip 220. More specifically, the second source pad 72 of the first chip 210 faces the first source pad 62 of the second chip 220. The second drain pad 74 of the first chip 210 faces the first drain pad 64 of the second chip 220. The second gate pad 76 of the first chip 210 faces the first gate pad 66 of the second chip 220.

[0098] The second pad 70 of the first chip 210 is electrically connected to the first chip 210 of the second chip 220 via a conductive connecting member 232. The connecting member 232 may be made of a material containing tin (Sn), for example. The connecting member 232 may be solder containing Sn, for example. The second source pad 72 of the first chip 210 is electrically connected to the first source pad 62 of the second chip 220 via the connecting member 232. The second drain pad 74 of the first chip 210 is electrically connected to the first drain pad 64 of the second chip 220 via the connecting member 232. The second gate pad 76 of the first chip 210 is electrically connected to the first gate pad 66 of the second chip 220 via the connecting member 232. Therefore, the transistor 100 included in the first chip 210 and the transistor 100 included in the second chip 220 are connected in parallel.

[0099] A connection member 231 is provided on the first pad 60 of the first chip 210. The connection member 231 is electrically conductive. For example, the connection member 231 may be made of a material containing Sn. For example, the connection member 231 may be a solder bump containing Sn.

[0100] 11, a first chip 210 and a second chip 220 are prepared. Connection members 231 are provided on the first pads 60 of the first chip 210. Connection members 232 are provided as solder bumps on the first pads 60 of the second chip 220. The second chip 220 and the first chip 210 are connected by the connection members 232 provided on the first pads 60 of the second chip 220.

[0101] The connecting member 231 provided on the first chip 210 and the connecting member 232 provided on the second chip 220 may have different melting points. The melting points of the connecting members 231 and 232 are adjusted, for example, by the Sn content. The content means mass or volume. For example, the melting point of the connecting member 231 provided on the first chip 210 is higher than the melting point of the connecting member 232 provided on the second chip 220. Therefore, when the first chip 210 and the second chip 220 are connected by the connecting member 232, melting of the connecting member 231 provided on the first chip 210 can be suppressed.

[0102] 10 , a connecting member 231 provided on the first chip 210 may be used to mount a nitride semiconductor device 200 including the first chip 210 and the second chip 220. The nitride semiconductor device 200 is arranged such that the first chip 210 faces a mounting surface 301 of a mounting substrate 300 indicated by a dashed dotted line. The nitride semiconductor device 200 is mounted to a source pad 302 and a drain pad 303 provided on the mounting surface 301 of the mounting substrate 300 by the connecting member 231.

[0103] The nitride semiconductor device 200 includes a first chip 210 and a second chip 220. The second chip 220 is connected to a second pad 70 of the first chip 210. In other words, the first chip 210 and the second chip 220 are stacked in the thickness direction of the first chip 210 and the second chip 220. Therefore, the mounting area of the nitride semiconductor device 200 is smaller than when the first chip 210 and the second chip 220 are separately mounted on the mounting substrate 300. In other words, it is possible to suppress an increase in the mounting area when mounting multiple chips.

[0104] The transistor 100 included in the first chip 210 and the transistor 100 included in the second chip 220 are connected in parallel. Therefore, the transistor 100 of the first chip 210 and the transistor 100 of the second chip 220 are connected in parallel to the source pad 302 and the drain pad 303 of the mounting substrate 300. Therefore, when the nitride semiconductor device 200 is turned on, the resistance between the source pad 302 and the drain pad 303 of the mounting substrate 300, i.e., the on-resistance of the nitride semiconductor device 200, is lower than the on-resistance of the transistor 100 included in the first chip 210 and the on-resistance of the transistor 100 included in the second chip 220. In other words, the first chip 210 and the second chip 220 contribute to lowering the on-resistance of the nitride semiconductor device 200.

[0105] (Operation of the first embodiment) Next, the operation of the nitride semiconductor device 10A of the first embodiment will be described. The nitride semiconductor device 10A includes a chip 20A having a semiconductor substrate 32 including a first substrate surface 32A and a second substrate surface 32B opposite the first substrate surface 32A, a nitride semiconductor layer 34 arranged on the first substrate surface 32A and including an element region A1 in which a transistor 100 is formed and a peripheral region A2 surrounding the element region A1, a first insulating layer 36 arranged on the nitride semiconductor layer 34, and a second insulating layer 38 arranged on the second substrate surface 32B. Chip 20A includes a first pad 60 arranged on surface 36A of first insulating layer 36 at a position overlapping peripheral region A2 in a planar view, a second pad 70 arranged on surface 38A of second insulating layer 38 at a position overlapping first pad 60 in a planar view, a through hole 40 arranged at a position overlapping first pad 60 and second pad 70 in a planar view and penetrating first insulating layer 36, nitride semiconductor layer 34, semiconductor substrate 32, and second insulating layer 38, and a through wiring 50 arranged within through hole 40 and electrically connecting first pad 60 and second pad 70.

[0106] The chips 20A of the nitride semiconductor device 10A can be stacked and connected in the thickness direction by the first pads 60 and the second pads 70. The transistors 100 included in the multiple chips 20A are connected in parallel with each other by stacking and connecting the multiple chips 20A. Therefore, the nitride semiconductor device 10A including the first pads 60 and the second pads 70 can achieve low on-resistance.

[0107] The first gate pad 66 and the second gate pad 76 are electrically connected to each other by the gate through wiring 56. The first gate pad 66 and the second gate pad 76 are electrically connected to the gate electrode 124 of the transistor 100. Therefore, when multiple chips 20A are stacked and electrically connected to each other, the transistors 100 included in each chip 20A can be switched on and off simultaneously.

[0108] The first pad 60 includes a first source pad 62, a first drain pad 64, and a first gate pad 66. The second pad 70 includes a second source pad 72, a second drain pad 74, and a second gate pad 76. The through wiring 50 includes a source through wiring 52, a drain through wiring 54, and a gate through wiring 56. The first source pad 62 and the second source pad 72 are electrically connected to each other by the source through wiring 52. The first source pad 62 and the second source pad 72 are electrically connected to the source electrode 128 of the transistor 100. The first drain pad 64 and the second drain pad 74 are electrically connected to each other by the drain through wiring 54. The first drain pad 64 and the second drain pad 74 are electrically connected to the drain electrode 130 of the transistor 100. For example, when two chips 20A are stacked and electrically connected to each other, the current flowing through each chip 20A is reduced to half of the total. Therefore, the amount of source-drain current in the chip 20A can be reduced. This also reduces the amount of heat generated in each chip 20A.

[0109] The source through-hole 42 is in contact with the inner surface 32C of the semiconductor substrate 32 that forms the inner surface 42C of the source through-hole 42. The source through-hole 52 is electrically connected to the semiconductor substrate 32. The semiconductor substrate 32 is then electrically connected to the source electrode 128 of the transistor 100. Therefore, the potential of the semiconductor substrate 32 can be set to the potential of the source electrode 128 for the transistor 100 configured as a HEMT.

[0110] Here, a nitride semiconductor device that includes only the first pad 60 but not the second pad 70 can be cited as a comparative example of the nitride semiconductor device 10A of the first embodiment. For example, a method can be considered in which multiple nitride semiconductor devices of the comparative example are arranged side by side on a mounting substrate and the same electrode pads are connected to each other by wires. However, this method requires a large mounting area. Furthermore, this method increases the inductance of the nitride semiconductor device of the comparative example as seen from the mounting substrate due to the wires connecting the electrode pads, making it difficult to achieve high-speed switching operation.

[0111] The chip 20A of the nitride semiconductor device 10A of the first embodiment can be stacked and connected in the thickness direction by the first pads 60 and the second pads 70. Therefore, when mounting a plurality of nitride semiconductor devices 10A, i.e., a plurality of chips 20A, only a mounting area sufficient for mounting one nitride semiconductor device 10A is required, and an increase in the mounting area can be suppressed.

[0112] The chips 20A of the nitride semiconductor device 10A of the first embodiment can be stacked and connected in the thickness direction by the first pads 60 and the second pads 70. Therefore, compared to connecting multiple nitride semiconductor devices 10A, i.e., multiple chips 20A in parallel to a mounting substrate by wires or the like, an increase in parasitic inductance due to the connection can be suppressed, thereby enabling high-speed switching operation.

[0113] (Effects of the first embodiment) As described above, the nitride semiconductor device 10A of the first embodiment provides the following advantages.

[0114] (1-1) The nitride semiconductor device 10A includes a chip 20A having a semiconductor substrate 32 including a first substrate surface 32A and a second substrate surface 32B opposite the first substrate surface 32A, a nitride semiconductor layer 34 disposed on the first substrate surface 32A and including an element region A1 in which a transistor 100 is formed and a peripheral region A2 surrounding the element region A1, a first insulating layer 36 disposed on the nitride semiconductor layer 34, and a second insulating layer 38 disposed on the second substrate surface 32B. Chip 20A includes a first pad 60 arranged on surface 36A of first insulating layer 36 at a position overlapping peripheral region A2 in a planar view, a second pad 70 arranged on surface 38A of second insulating layer 38 at a position overlapping first pad 60 in a planar view, a through hole 40 arranged at a position overlapping first pad 60 and second pad 70 in a planar view and penetrating first insulating layer 36, nitride semiconductor layer 34, semiconductor substrate 32, and second insulating layer 38, and a through wiring 50 arranged within through hole 40 and electrically connecting first pad 60 and second pad 70.

[0115] The chips 20A of the nitride semiconductor device 10A can be stacked and connected in the thickness direction by the first pads 60 and the second pads 70. The transistors 100 included in the multiple chips 20A are connected in parallel with each other by stacking and connecting the multiple chips 20A. Therefore, the nitride semiconductor device 10A including the first pads 60 and the second pads 70 can achieve low on-resistance.

[0116] (1-2) The first gate pad 66 and the second gate pad 76 are electrically connected to each other by the gate through wiring 56. The first gate pad 66 and the second gate pad 76 are electrically connected to the gate electrode 124 of the transistor 100. Therefore, when multiple chips 20A are stacked and electrically connected to each other, the transistors 100 included in each chip 20A can be switched on and off simultaneously.

[0117] (1-3) The first pad 60 includes a first source pad 62, a first drain pad 64, and a first gate pad 66. The second pad 70 includes a second source pad 72, a second drain pad 74, and a second gate pad 76. The through wiring 50 includes a source through wiring 52, a drain through wiring 54, and a gate through wiring 56. The first source pad 62 and the second source pad 72 are electrically connected to each other by the source through wiring 52. The first source pad 62 and the second source pad 72 are electrically connected to the source electrode 128 of the transistor 100. The first drain pad 64 and the second drain pad 74 are electrically connected to each other by the drain through wiring 54. The first drain pad 64 and the second drain pad 74 are electrically connected to the drain electrode 130 of the transistor 100. For example, when two chips 20A are stacked and electrically connected to each other, the current flowing through each chip 20A is half of the total. Therefore, the amount of source-drain current in the chip 20A can be reduced. This also reduces the amount of heat generated in each chip 20A.

[0118] (1-4) The source through-wire 52 contacts the inner surface 32C of the semiconductor substrate 32 that forms the inner surface 42C of the source through-hole 42. The source through-wire 52 is electrically connected to the semiconductor substrate 32. The semiconductor substrate 32 is then electrically connected to the source electrode 128 of the transistor 100. Therefore, the potential of the semiconductor substrate 32 can be set to the potential of the source electrode 128 for the transistor 100 configured as a HEMT.

[0119] (1-5) The chip 20A of the nitride semiconductor device 10A of the first embodiment can be stacked and connected in the thickness direction by the first pads 60 and the second pads 70. Therefore, when mounting a plurality of nitride semiconductor devices 10A, i.e., a plurality of chips 20A, only a mounting area sufficient for mounting one nitride semiconductor device 10A is required, and an increase in the mounting area can be suppressed.

[0120] (1-6) The chips 20A of the nitride semiconductor device 10A of the first embodiment can be stacked and connected in the thickness direction by the first pads 60 and the second pads 70. Therefore, compared to connecting multiple nitride semiconductor devices 10A, i.e., multiple chips 20A in parallel to a mounting substrate by wires or the like, an increase in parasitic inductance due to the connection can be suppressed. This enables high-speed switching operation.

[0121] (1-7) The 2DEG 120 is not formed in the peripheral region A2. Therefore, even if the source through wiring 52 is in contact with the inner surface 42C of the source through hole 42, the occurrence of a short circuit with the drain electrode 130 of the transistor 100 can be suppressed.

[0122] (Second embodiment) An illustrative nitride semiconductor device 10B according to the second embodiment will now be described with reference to FIGS.

[0123] In the nitride semiconductor device 10B according to the second embodiment, the same components as those in the nitride semiconductor device 10A according to the first embodiment are denoted by the same reference numerals. In the following, the description of the same components as those in the first embodiment will be omitted, and only the components different from those in the first embodiment will be described.

[0124] Fig. 13 shows a schematic planar structure of an exemplary nitride semiconductor device 10B according to the second embodiment. Fig. 14 shows a schematic planar structure of the nitride semiconductor device 10B of Fig. 13 viewed from the opposite side to that of Fig. 13. Fig. 14 shows the nitride semiconductor device 10B of Fig. 13 inverted about the Y-axis. Fig. 15 is a schematic cross-sectional view taken along line F15-F15 of Fig. 13. Fig. 16 is a schematic cross-sectional view taken along line F16-F16 of Fig. 13.

[0125] 13 to 16, a nitride semiconductor device 10B according to the second embodiment includes a chip 20B. The chip 20B includes two source through holes 42 and two drain through holes 44. The two source through holes 42 are arranged at positions overlapping with both the first source pad 62 and the second source pad 72. The two source through holes 42 are arranged spaced apart in the Y-axis direction. The two drain through holes 44 are arranged at positions overlapping with both the first drain pad 64 and the second drain pad 74. The two source through holes 42 are arranged spaced apart in the Y-axis direction.

[0126] As shown in FIG. 13 , the source through hole 42 and the drain through hole 44 are arranged on either side of the element region A1. In one example, the source through hole 42 and the drain through hole 44 are arranged in positions that are line-symmetric with respect to the element region A1. In one example, the source through hole 42 and the drain through hole 44 have shapes that are line-symmetric with respect to a central axis L1 that passes through a center point O1 between the source through hole 42 and the drain through hole 44 and extends in the Y-axis direction, which is perpendicular to the X-axis direction in a plan view. The center point O1 may be located at the same position as the center of the element region A1. The central axis L1 that passes through the center point O1 between the source through hole 42 and the drain through hole 44 may be a central axis that passes through the center point of the element region A1 and extends in the Y-axis direction. It can be said that the source through hole 42 and the drain through hole 44 are arranged in positions that are line-symmetric with respect to the central axis L1 that passes through the center point O1 of the element region A1 and extends in the Y-axis direction.

[0127] As shown in FIG. 15, in the chip 20B, the inner surface 42C of the source through-hole 42 is covered with an insulating film 43. The insulating film 43 covers the entire inner surface 42C of the source through-hole 42. The source through-wiring 52 is surrounded by the insulating film 43 of the source through-hole 42. The source through-wiring 52 of the second embodiment does not contact the inner surface 42C of the source through-hole 42. The source through-wiring 52 is insulated from the semiconductor substrate 32 by the insulating film 43 of the source through-hole 42. The insulating film 43 may be made of a material containing, for example, any one of SiO2, SiN, SiON, Al2O3, AlN, and AlON. In one example, the insulating film 43 is made of a material containing SiO2.

[0128] 13 and 15, the chip 20B includes via holes 48. In one example, the chip 20B includes three via holes 48. The number of via holes 48 may be one, two, or any number greater than or equal to four.

[0129] The three via holes 48 are arranged in the peripheral region A2 in a planar view. In one example, the three via holes 48 are arranged at positions overlapping with the first source pad 62 in a planar view. In one example, the three via holes 48 are arranged between two source through-holes 42. In one example, the three via holes 48 overlap with the first source pad 62 in a planar view and are arranged closer to the second chip side surface 24 than the element region A1.

[0130] 15, the via hole 48 extends from the first chip surface 21 of the chip 20B toward the semiconductor substrate 32. The via hole 48 penetrates the first insulating layer 36 and the nitride semiconductor layer 34 and reaches partway into the semiconductor substrate 32. In one example, the via hole 48 extends toward the second substrate surface 32B of the semiconductor substrate 32 beyond the first substrate surface 32A that forms the interface between the semiconductor substrate 32 and the nitride semiconductor layer 34. The via hole 48 includes a bottom surface 48A and an inner surface 48B between the bottom surface 48A and the first chip surface 21 of the chip 20B. The semiconductor substrate 32 is exposed at the bottom surface 48A of the via hole 48.

[0131] As shown in FIG. 15, the chip 20B includes a substrate connection wiring 58. The substrate connection wiring 58 is disposed in the via hole 48. The substrate connection wiring 58 is disposed at a position overlapping the first source pad 62 in a plan view. In one example, the substrate connection wiring 58 is made of a conductive material filled in the via hole 48. The substrate connection wiring 58 can be made of any conductive material including at least one of Cu, Al, an AlCu alloy, W, Ti, and TiN, for example. In one example, the substrate connection wiring 58 is made of a material including Cu.

[0132] The substrate connecting wire 58 is in contact with the bottom surface 48A of the via hole 48. The substrate connecting wire 58 is electrically connected to the first source pad 62. The substrate connecting wire 58 electrically connects the first source pad 62 and the semiconductor substrate 32.

[0133] (Effects of the second embodiment) As described above, the nitride semiconductor device 10B of the second embodiment has the following advantages in addition to the advantages of the nitride semiconductor device 10A of the first embodiment.

[0134] (2-1) The nitride semiconductor device 10B of the second embodiment includes a substrate connecting wiring 58 electrically connected to the semiconductor substrate 32. This nitride semiconductor device 10B includes the substrate connecting wiring 58 in addition to the source through wiring 52. No drain-source current due to the switching operation of the nitride semiconductor device 10B flows through the substrate connecting wiring 58. Therefore, the potential of the semiconductor substrate 32 can be further stabilized.

[0135] (Example of change) The above embodiment can be modified, for example, as follows: The above embodiment and each of the following modified examples can be combined with each other as long as no technical contradiction occurs. In the following modified examples, parts common to the above embodiment will be assigned the same reference numerals as in the above embodiment, and their description will be omitted.

[0136] The configuration of the nitride semiconductor devices 10A, 10B, and 200 may be changed as appropriate. 17, in a nitride semiconductor device 10C of the modified example, the gate through wiring 56 (56A, 56B) may be made of a conductive film provided on the inner surface 46C of the gate through hole 46 (46A, 46B). The gate through wiring 56 made of a conductive film may be hollow and may be filled with resin.

[0137] 18, in a nitride semiconductor device 10D of the modified example, the through-hole 40 has a circular shape in a plan view. The shape of the through-hole 40 may be any shape in a plan view, such as a circular shape, a rectangular shape, an elliptical shape, an oval shape, a trapezoidal shape, or the like, in addition to a circular shape or a rectangular shape.

[0138] One of the source through-hole 42, the drain through-hole 44, and the gate through-hole 46 may have a different shape from the others. In one example, the source through-hole 42 and the drain through-hole 44 may have a rectangular shape in a plan view, and the gate through-hole 46 may have a circular shape in a plan view. Furthermore, the source through-hole 42, the drain through-hole 44, and the gate through-hole 46 may have different shapes from each other.

[0139] In the nitride semiconductor device 10D of the modified example, the through wiring 50 has a circular shape in a plan view. The shape of the through wiring 50 can be any shape in a plan view, such as a circular shape, a rectangular shape, an elliptical shape, an oval shape, a trapezoidal shape, etc.

[0140] One of the source through wiring 52, the drain through wiring 54, and the gate through wiring 56 may have a different shape from the other through wirings. In one example, the source through wiring 52 and the drain through wiring 54 may have a rectangular shape in a plan view, and the gate through wiring 56 may have a circular shape in a plan view. Furthermore, the source through wiring 52, the drain through wiring 54, and the gate through wiring 56 may have different shapes from each other.

[0141] The gate through-holes 46A and 46B may have smaller opening diameters than the source through-hole 42 and the drain through-hole 44 in plan view. In plan view, the area of the gate through wirings 56A and 56B may be smaller than the area (total area) of the source through wiring 52 and the drain through wiring 54.

[0142] In the nitride semiconductor device 200A shown in FIG. 19, a chip 230 including only first pads 60 is connected on top of the chip 210. The first pads 60 of the chip 230 have the same shape as the first pads 60 of the chip 210. This nitride semiconductor device 200A can also achieve low on-resistance, as with the nitride semiconductor device 200 described in the first embodiment. The chip 230 may be connected on top of the first chip 210 and the second chip 220 shown in FIG. 11. In other words, a nitride semiconductor device is configured by stacking multiple chips, and the topmost chip may or may not include the second pads 70.

[0143] The first gate pads 66A and 66B may be arranged on either side of the first drain pad 64. The second gate pads 76A and 76B may be arranged on either side of the second drain pad 74.

[0144] The substrate connecting wire 58 shown in FIG. 15 may be surrounded by the insulating film on the inner surface 48B of the via hole 48 as long as it is electrically connected to the semiconductor substrate 32.

[0145] 11 may be mounted with the second pads 70 of the second chip 220 facing the mounting substrate 300. In this case, connecting members 231 are provided on the second pads 70 of the second chip 220. The nitride semiconductor device 200 is mounted face-up so that the first chip surface 21 faces upward, that is, so that the nitride semiconductor layer 34 (see FIG. 3) including the transistor 100 faces upward.

[0146] The term "on" as used in this disclosure includes both "on" and "above" unless the context clearly indicates otherwise. Thus, the phrase "a first layer is formed on a second layer" is intended to mean that in some embodiments, the first layer may be disposed directly on the second layer in contact with the second layer, while in other embodiments, the first layer may be disposed above the second layer without contacting the second layer. In other words, the term "on" does not exclude a structure in which another layer is formed between the first and second layers.

[0147] The Z-axis direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure (for example, the structure shown in FIG. 1 ) are not limited to the "up" and "down" in the Z-axis direction described in this disclosure being "up" and "down" in the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

[0148] (Addendum) The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the appendices are given the reference numerals of the corresponding components in the embodiments. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0149] (Appendix 1) a semiconductor substrate (32) including a first substrate surface (32A) and a second substrate surface (32B) opposite the first substrate surface (32A); a nitride semiconductor layer (34) disposed on the first substrate surface (32A) and including an element region (A1) in which a transistor (100) is formed, and a peripheral region (A2) surrounding the element region (A1); a first insulating layer (36) disposed on the nitride semiconductor layer (34); a second insulating layer (38) disposed on the second substrate surface (32B); A chip (20A) having The chip (20A) a first pad (60) arranged on the surface of the first insulating layer (36) at a position overlapping the peripheral region (A2) in a plan view; a second pad (70) disposed on the surface of the second insulating layer (38) at a position overlapping the first pad (60) in a plan view; a through hole (40) that is arranged at a position overlapping the first pad (60) and the second pad (70) in a plan view and that penetrates the first insulating layer (36), the nitride semiconductor layer (34), the semiconductor substrate (32), and the second insulating layer (38); a through wiring (50) disposed in the through hole (40) and electrically connecting the first pad (60) and the second pad (70); A nitride semiconductor device comprising:

[0150] (Appendix 2) The first pad (60) is electrically connected to the transistor (100) and includes a first gate pad (66), a first source pad (62), and a first drain pad (64) that are spaced apart from each other on the surface of the first insulating layer (36); The second pad (70) includes a second gate pad (76), a second source pad (72), and a second drain pad (74) that are spaced apart from each other on the surface of the second insulating layer (38), The second gate pad (76) is disposed at a position overlapping the first gate pad (66), The second source pad (72) is disposed at a position overlapping the first source pad (62), The second drain pad (74) is disposed at a position overlapping the first drain pad (64), The through hole (40) is a gate through-hole (46) arranged at a position overlapping the first gate pad (66) and the second gate pad (76); a source through-hole (42) arranged at a position overlapping the first source pad (62) and the second source pad (72); a drain through-hole (44) arranged at a position overlapping the first drain pad (64) and the second drain pad (74), The through wiring (50) is a gate through-hole (46) disposed within the gate through-hole (46) and electrically connecting the first gate pad (66) and the second gate pad (76); a source through-hole (42) disposed within the source through-hole (42) and electrically connecting the first source pad (62) and the second source pad (72); a drain through wiring (54) disposed in the drain through hole (44) and electrically connecting the first drain pad (64) and the second drain pad (74), 2. The nitride semiconductor device according to claim 1.

[0151] (Appendix 3) Insulating films (45, 47) are provided on the inner surfaces of the gate through-hole (46) and the drain through-hole (44), the gate through-wiring (56) is surrounded by the insulating film (47) of the gate through-hole (46); The drain through wiring (54) is surrounded by the insulating film (45) of the drain through hole (44). 3. The nitride semiconductor device according to claim 2.

[0152] (Appendix 4) The source through-wire (52) is in contact with the inner surface (42C) of the source through-hole (42). 4. The nitride semiconductor device according to claim 2 or 3.

[0153] (Appendix 5) An insulating film (43) is provided on the inner surface of the source through-hole (42), The source through-wiring (52) is surrounded by the insulating film (43) of the source through-hole (42). 4. The nitride semiconductor device according to claim 2 or 3.

[0154] (Appendix 6) a via hole (48) that is disposed in the peripheral region (A2) in a plan view and penetrates the nitride semiconductor layer (34) to reach the semiconductor substrate (32); a substrate connection wiring (58) embedded in the via hole (48) and electrically connecting the first source pad (62) and the semiconductor substrate (32); Including, 6. The nitride semiconductor device according to claim 5.

[0155] (Appendix 7) An insulating film is provided on the inner surface of the via hole (48), The substrate connection wiring (58) is surrounded by the insulating film of the via hole (48). 7. The nitride semiconductor device according to claim 6.

[0156] (Appendix 8) The via hole (48) is arranged at a position overlapping the first source pad (62) in a plan view. 8. The nitride semiconductor device according to claim 6 or 7.

[0157] (Appendix 9) In a plan view, the first source pad (62) and the first drain pad (64) are arranged to sandwich the element region (A1) in a first direction, the source through wiring (52) and the drain through wiring (54) are arranged to sandwich the element region (A1) in the first direction; 9. The nitride semiconductor device according to any one of Supplementary Note 2 to Supplementary Note 8.

[0158] (Appendix 10) In a plan view, the first gate pad (66) is disposed adjacent to at least one of the first source pad (62) and the first drain pad (64). 10. The nitride semiconductor device according to any one of Supplementary Note 2 to Supplementary Note 9.

[0159] (Appendix 11) The first gate pad (66) is provided in two pieces, In a plan view, the two first gate pads (66A, 66B) are arranged to sandwich the first source pad (62). 10. The nitride semiconductor device according to any one of Supplementary Note 2 to Supplementary Note 9.

[0160] (Appendix 12) In a plan view, the first source pad (62) and the first drain pad (64) are arranged to sandwich the element region (A1) in a first direction, The source through wiring (52) and the drain through wiring (54) have shapes that are symmetrical with respect to a central axis (L1) that passes through a center point between the source through wiring (52) and the drain through wiring (54) and extends in a second direction that is perpendicular to the first direction in a plan view. 12. The nitride semiconductor device according to claim 2, wherein the nitride semiconductor device is a nitride semiconductor material.

[0161] (Appendix 13) In a plan view, the first gate pad (66) has an area smaller than that of the first source pad (62) and the first drain pad (64), and the area of the gate through wiring (56) is smaller than that of the source through wiring (52) and the drain through wiring (54). 13. The nitride semiconductor device according to any one of Supplementary Note 2 to Supplementary Note 12.

[0162] (Appendix 14) In plan view, the area of the source through wiring (52) and the area of the drain through wiring (54) are equal. 14. The nitride semiconductor device according to claim 2, wherein the nitride semiconductor device is a nitride semiconductor.

[0163] (Appendix 15) The source through wiring (52) and the drain through wiring (54) are provided in plurality. 15. The nitride semiconductor device according to any one of claims 2 to 14.

[0164] (Appendix 16) In a plan view, the first source pad (62) and the first drain pad (64) are arranged to sandwich the element region (A1) in a first direction, The plurality of source through-wirings (52) are arranged side by side in a second direction perpendicular to the first direction in a plan view, The plurality of drain through wirings (54) are arranged side by side in the second direction. 16. The nitride semiconductor device according to claim 15.

[0165] (Appendix 17) The plurality of source through-wirings (52) are arranged at equal intervals in the second direction, The plurality of drain through wirings (54) are arranged at equal intervals in the second direction. 17. The nitride semiconductor device according to claim 16.

[0166] (Appendix 18) The spacing between the source through-wirings (52) adjacent to each other in the second direction is equal to the spacing between the drain through-wirings (54) adjacent to each other in the second direction. 18. The nitride semiconductor device according to claim 16 or 17.

[0167] (Appendix 19) The length of the source through wiring (52) in the second direction is equal to the length of the drain through wiring (54) in the second direction. 19. The nitride semiconductor device according to any one of Supplementary Note 16 to Supplementary Note 18.

[0168] (Appendix 20) The number of the source through-wirings (52) is equal to the number of the drain through-wirings (54). 20. The nitride semiconductor device according to any one of Supplementary Note 15 to Supplementary Note 19.

[0169] (Appendix 21) The nitride semiconductor layer (34) is an electron transit layer disposed on the semiconductor substrate (32) and made of a nitride semiconductor; an electron supply layer (118) disposed on the electron transit layer in the element region (A1) and made of a nitride semiconductor having a band gap larger than that of the electron transit layer; a gate layer (122) disposed on a portion of the electron supply layer (118) and made of a nitride semiconductor containing acceptor-type impurities; Including, The transistor (100) the electron transit layer (116); the electron supply layer (118); the gate layer (122); a gate electrode (124) disposed on the gate layer (122); a source electrode (128) and a drain electrode (130) disposed on the electron supply layer (118) with the gate layer (122) interposed therebetween; 21. The nitride semiconductor device according to claim 20,

[0170] (Appendix 22) a gate wiring electrically connecting the gate electrode (124) and the first gate pad (66); a source wiring electrically connecting the source electrode (128) and the first source pad (62); a drain wiring electrically connecting the drain electrode (130) and the first drain pad (64); Including, 22. The nitride semiconductor device according to claim 21.

[0171] (Appendix 23) The semiconductor substrate (32) is a Si substrate. 23. The nitride semiconductor device according to claim 1, wherein the nitride semiconductor device is a nitride semiconductor.

[0172] (Appendix 24) The nitride semiconductor layer is a GaN layer. 24. The nitride semiconductor device according to claim 1, wherein the nitride semiconductor device is a nitride semiconductor.

[0173] (Appendix 25) The chip (20A) includes a first chip (20A) and a second chip (20A) stacked on each other, The second pads (70) of the first chip (20A) and the first pads (60) of the second chip (20A) are electrically connected. 25. The nitride semiconductor device according to claim 1, wherein the nitride semiconductor device is a nitride semiconductor.

[0174] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims. [Explanation of symbols]

[0175] 10A-10D Nitride semiconductor devices 20A, 20B chip 21 First chip surface 22 Second chip surface 23~26 Chip side 32 Semiconductor substrate 32A 1st board surface 32B 2nd board surface 32C inner surface 34 Nitride semiconductor layer 34A 1st semiconductor surface 34B 2nd semiconductor surface 34C Inner Surface 36 First insulating layer 36A surface 38 Second insulating layer 38A surface 40 through holes 42 Source through-hole 42C inner surface 43 Insulating film 44 Drain through hole 44C inner surface 45 insulating film 46 Gate through hole 46A Gate Through Hole 46B Gate through hole 46C inner surface 47 Insulating Film 48 Beer Hall 48A Bottom 48B inner surface 50 through wiring 52 Source through wiring 54 Drain through wiring 56 Gate through wiring 56A gate through wiring 56B Gate through wiring 58 PCB connection wiring 60 First Pad 62 1st Source Pad 64 First Drain Pad 66 First gate pad 66A 1st gate pad 66B 1st gate pad 70 Second Pad 72 Second Source Pad 74 Second drain pad 76 Second gate pad 76A Second gate pad 76B Second gate pad 81 1st protective film 81A~81C opening 82 Second protective film 82A~82C opening 100 transistors 114 Buffer Layer 116 Electron transport layer 118 Electron supply layer 120 Two-dimensional electron gas 122 Gate Layer 122A Gate layer main body 122B 1st extension part 122C 2nd extension 124 gate electrode 126 Insulating Layer 126A Source Opening 126B Drain opening 128 Source Electrode 128A Source Contact 130 drain electrode 130A drain contact 131 Field plate electrode 131A End 142 Source wiring 144 Drain wiring 146 Gate wiring 146A 1st gate wiring 146B Second gate wiring 200 Nitride semiconductor device 200A nitride semiconductor device 210 First Chip 220 Second Chip 231 Connecting member 232 Connecting member A1 element area A2 Peripheral area L1 center axis O1 center point

Claims

1. a semiconductor substrate including a first substrate surface and a second substrate surface opposite the first substrate surface; a nitride semiconductor layer disposed on the first substrate surface, the nitride semiconductor layer including an element region in which a transistor is formed and a peripheral region surrounding the element region; a first insulating layer disposed on the nitride semiconductor layer; a second insulating layer disposed on the second substrate surface; a chip comprising: The chip is a first pad disposed on a surface of the first insulating layer at a position overlapping the peripheral region in a plan view; a second pad disposed on a surface of the second insulating layer at a position overlapping the first pad in a plan view; a through hole that is arranged at a position overlapping the first pad and the second pad in a plan view and that penetrates the first insulating layer, the nitride semiconductor layer, the semiconductor substrate, and the second insulating layer; a through wiring disposed in the through hole and electrically connecting the first pad and the second pad; A nitride semiconductor device comprising:

2. the first pad is electrically connected to the transistor and includes a first gate pad, a first source pad, and a first drain pad that are spaced apart from each other on the surface of the first insulating layer; the second pads include a second gate pad, a second source pad, and a second drain pad spaced apart from each other on the surface of the second insulating layer; the second gate pad is disposed at a position overlapping the first gate pad, the second source pad is disposed at a position overlapping the first source pad, the second drain pad is disposed at a position overlapping the first drain pad, The through hole is a gate through-hole arranged at a position overlapping the first gate pad and the second gate pad; a source through-hole arranged at a position overlapping the first source pad and the second source pad; a drain through-hole arranged at a position overlapping the first drain pad and the second drain pad, The through wiring is a gate through-hole that is disposed within the gate through-hole and electrically connects the first gate pad and the second gate pad; a source through-hole that is disposed in the source through-hole and electrically connects the first source pad and the second source pad; a drain through-wiring disposed in the drain through-hole and electrically connecting the first drain pad and the second drain pad; The nitride semiconductor device according to claim 1 .

3. an insulating film is provided on the inner surface of the gate through-hole and the drain through-hole; the gate through-wiring is surrounded by the insulating film of the gate through-hole, the drain through-wiring is surrounded by the insulating film of the drain through-hole; The nitride semiconductor device according to claim 2 .

4. the source through-wiring is in contact with the inner surface of the source through-hole; The nitride semiconductor device according to claim 2 .

5. an insulating film is provided on the inner surface of the source through-hole; the source through-wiring is surrounded by the insulating film of the source through-hole; The nitride semiconductor device according to claim 2 .

6. a via hole that is disposed in the peripheral region in a plan view and penetrates the nitride semiconductor layer to reach the semiconductor substrate; a substrate connection wiring buried in the via hole and electrically connecting the first source pad and the semiconductor substrate; Including, The nitride semiconductor device according to claim 5 .

7. an insulating film is provided on the inner surface of the via hole; the substrate connection wiring is surrounded by the insulating film of the via hole; The nitride semiconductor device according to claim 6 .

8. the via hole is disposed at a position overlapping the first source pad in a plan view; The nitride semiconductor device according to claim 6 .

9. In a plan view, the first source pad and the first drain pad are arranged to sandwich the element region in a first direction, the source through-wiring and the drain through-wiring are arranged to sandwich the element region in the first direction; The nitride semiconductor device according to claim 2 .

10. the first gate pad is disposed adjacent to at least one of the first source pad and the first drain pad in a plan view; The nitride semiconductor device according to claim 2 .

11. two first gate pads are provided, In a plan view, the two first gate pads are arranged to sandwich the first source pad. The nitride semiconductor device according to claim 2 .

12. In a plan view, the first source pad and the first drain pad are arranged to sandwich the element region in a first direction, the source through wiring and the drain through wiring have shapes that are line-symmetric with respect to a central axis that passes through a center point between the source through wiring and the drain through wiring and extends in a second direction that is perpendicular to the first direction in a plan view, The nitride semiconductor device according to claim 2 .

13. In a plan view, the first gate pad has an area smaller than that of the first source pad and that of the first drain pad, and the area of the gate through wiring is smaller than that of the source through wiring and that of the drain through wiring. The nitride semiconductor device according to claim 2 .

14. In a plan view, the area of the source through-hole wiring and the area of the drain through-hole wiring are equal. The nitride semiconductor device according to claim 2 .

15. a plurality of the source through wirings and a plurality of the drain through wirings are provided; The nitride semiconductor device according to claim 2 .

16. In a plan view, the first source pad and the first drain pad are arranged to sandwich the element region in a first direction, the plurality of source through-wirings are arranged side by side in a second direction perpendicular to the first direction in a plan view, The plurality of drain through-wirings are arranged side by side in the second direction. The nitride semiconductor device according to claim 15.

17. the plurality of source through-wirings are arranged at equal intervals in the second direction, The plurality of drain through-wirings are arranged at equal intervals in the second direction. The nitride semiconductor device according to claim 16.

18. The nitride semiconductor layer is an electron transit layer made of a nitride semiconductor and disposed on the semiconductor substrate; an electron supply layer disposed on the electron transit layer in the element region and made of a nitride semiconductor having a band gap larger than that of the electron transit layer; a gate layer disposed on a portion of the electron supply layer and made of a nitride semiconductor containing acceptor-type impurities; Including, The transistor is the electron transit layer; the electron supply layer; the gate layer; a gate electrode disposed on the gate layer; a source electrode and a drain electrode disposed on the electron supply layer with the gate layer interposed therebetween; The nitride semiconductor device according to claim 2 .

19. a gate wiring electrically connecting the gate electrode and the first gate pad; a source wiring electrically connecting the source electrode and the first source pad; a drain wiring electrically connecting the drain electrode and the first drain pad; Including, The nitride semiconductor device according to claim 18.

20. The chip includes a first chip and a second chip stacked on top of each other, the second pads of the first chip and the first pads of the second chip are electrically connected to each other; The nitride semiconductor device according to claim 1 .

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