Semiconductor package and manufacturing method for the same

Abstract

To provide a semiconductor package that can implement a small form factor by maximizing the heat release characteristic, and a manufacturing method for the semiconductor package.SOLUTION: A semiconductor package includes: a first rewiring substrate; a first semiconductor chip disposed on a right side in a first direction on the first rewiring substrate and including a penetration electrode; a first penetration post disposed on a left side in the first direction on the first rewiring substrate while being adjacent to the first semiconductor chip; a second rewiring substrate disposed on the first semiconductor chip and the first penetration post; a semiconductor element disposed on the left side in the first direction on the second rewiring substrate; and a second semiconductor chip disposed on the right side in the first direction on the second rewiring substrate while being adjacent to the semiconductor element.SELECTED DRAWING: Figure 1B

Description

[Technical Field]

[0001] The present invention relates to a semiconductor package, and more particularly to a semiconductor package including rewiring substrates above and below a semiconductor chip, and a method for manufacturing the same. [Background technology]

[0002] Rapid developments in the electronics industry and user demands have led to further miniaturization and weight reduction of electronic devices. As electronic devices become smaller and lighter, the semiconductor packages used therein are also becoming smaller and lighter, and semiconductor packages are required to have high performance, large capacity, and high reliability. As the performance and capacity of such semiconductor packages increase, their power consumption is also increasing. Therefore, miniaturization, performance improvement, and heat dissipation characteristics of semiconductor packages are becoming increasingly important. Summary of the Invention [Problem to be solved by the invention]

[0003] SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor package capable of maximizing heat dissipation characteristics and realizing a small form factor, and a method for manufacturing the same.

[0004] Furthermore, the problems to be solved by the technical idea of the present invention are not limited to the above-mentioned problems, and other problems will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0005] In order to solve the above problem, the technical idea of the present invention provides a semiconductor package including: a first rewiring substrate; a first semiconductor chip having a through electrode, the first semiconductor chip being disposed on the right side in a first direction on the first rewiring substrate; a first through post disposed on the left side in the first direction on the first rewiring substrate adjacent to the first semiconductor chip; a second rewiring substrate disposed on the first semiconductor chip and the first through post; a semiconductor element disposed on the left side in the first direction on the second rewiring substrate; and a second semiconductor chip disposed on the right side in the first direction on the second rewiring substrate adjacent to the semiconductor element.

[0006] In order to solve the above problem, the technical idea of the present invention provides a semiconductor package including: a first redistribution substrate; a first semiconductor chip having a through electrode disposed on the right side in a first direction on the first redistribution substrate; a first encapsulant disposed on the first redistribution substrate and encapsulating the first semiconductor chip; a first through post disposed on the left side in the first direction on the first redistribution substrate adjacent to the first semiconductor chip and extending through the first encapsulant; a second redistribution substrate disposed on the first semiconductor chip and the first through post; a semiconductor element disposed on the left side in the first direction on the second redistribution substrate; a second semiconductor chip disposed on the right side in the first direction on the second redistribution substrate adjacent to the semiconductor element; and a second encapsulant disposed on the second redistribution substrate and encapsulating the semiconductor element and the second semiconductor chip; wherein top surfaces of the semiconductor element and the second semiconductor chip are exposed from the second encapsulant.

[0007] Furthermore, in order to solve the above problem, the technical idea of the present invention provides a semiconductor package including: a first rewiring substrate; a first semiconductor chip disposed on the first rewiring substrate and having a through electrode; a second rewiring substrate disposed on the first semiconductor chip; a semiconductor element disposed on the second rewiring substrate on the left side in a first direction; and a second semiconductor chip disposed on the second rewiring substrate on the right side in the first direction adjacent to the semiconductor element.

[0008] Meanwhile, in order to solve the above problem, the technical idea of the present invention provides a method for manufacturing a semiconductor package, including the steps of forming an upper redistribution substrate on a first carrier substrate; attaching a semiconductor element and a top semiconductor chip on a first surface of the upper redistribution substrate; attaching a bottom semiconductor chip on a second surface of the upper redistribution substrate opposite to the first surface; forming a lower redistribution substrate on the bottom semiconductor chip; and attaching a passive element and an external connection terminal on the lower redistribution substrate, wherein the bottom semiconductor chip has a through electrode. [Brief explanation of the drawings]

[0009] [Figure 1A] 1 is a plan view of a semiconductor package according to an embodiment of the present invention; [Figure 1B] 1 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention; [Figure 2A] 1C is a cross-sectional view showing the structure of a memory element in the semiconductor package of FIG. 1B in further detail. [Figure 2B] 1C is a cross-sectional view showing the structure of a memory element in the semiconductor package of FIG. 1B in further detail. [Figure 2C] 1C is a cross-sectional view showing the structure of a memory element in the semiconductor package of FIG. 1B in further detail. [Figure 3A] 1 is a plan view of a semiconductor package according to an embodiment of the invention; [Figure 3B] 1 is a plan view of a semiconductor package according to an embodiment of the invention; [Figure 4] 1 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention; [Figure 5A] 1A to 1C are cross-sectional views schematically illustrating a process of a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 5B] 1A to 1C are cross-sectional views schematically illustrating a process of a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 5C] 1A to 1C are cross-sectional views schematically illustrating a process of a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 5D]1A to 1C are cross-sectional views schematically illustrating a process of a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 5E] 1A to 1C are cross-sectional views schematically illustrating a process of a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 5F] 1A to 1C are cross-sectional views schematically illustrating a process of a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 5G] 1A to 1C are cross-sectional views schematically illustrating a process of a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 5H] 1A to 1C are cross-sectional views schematically illustrating a process of a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 5I] 1A to 1C are cross-sectional views schematically illustrating a process of a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 5J] 1A to 1C are cross-sectional views schematically illustrating a process of a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 6A] FIG. 5F is a cross-sectional view specifically illustrating the step of FIG. 5E in more detail. [Figure 6B] FIG. 5F is a cross-sectional view specifically illustrating the step of FIG. 5E in more detail. [Figure 6C] FIG. 5F is a cross-sectional view specifically illustrating the step of FIG. 5E in more detail. [Figure 6D] FIG. 5F is a cross-sectional view specifically illustrating the step of FIG. 5E in more detail. [Figure 6E] FIG. 5F is a cross-sectional view specifically illustrating the step of FIG. 5E in more detail. [Figure 6F] FIG. 5F is a cross-sectional view specifically illustrating the step of FIG. 5E in more detail. [Figure 7A] 1A to 1C are cross-sectional views schematically illustrating a process of a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 7B] 1A to 1C are cross-sectional views schematically illustrating a process of a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 7C] 1A to 1C are cross-sectional views schematically illustrating a process of a method for manufacturing a semiconductor package according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0010] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings. The same components in the drawings are designated by the same reference numerals, and redundant description thereof will be omitted.

[0011] 1A and 1B are a plan view and a cross-sectional view of a semiconductor package according to an embodiment of the present invention.

[0012] 1A and 1B, the semiconductor package 1000 of this embodiment may include a first redistribution substrate 100, a first semiconductor chip 200, through posts 300, a second redistribution substrate 400, a semiconductor element 500, a second semiconductor chip 600, an external connection terminal 700, a passive element 800, and an encapsulant 900.

[0013] The first redistribution substrate 100 may be disposed under the first semiconductor chip 200, the through posts 300, and the first encapsulant 910. The first redistribution substrate 100 may serve to redistribute chip pads of the first semiconductor chip 200 to an external region of the first semiconductor chip 200. The first redistribution substrate 100 may include a first body insulating layer 101 and first redistribution lines 110.

[0014] The first body insulating layer 101 may be made of an insulating material, such as a photo imageable dielectric (PID) or photo imageable polyimide (PIP) resin, and may further include an inorganic filler. However, the material of the first body insulating layer 101 is not limited to the above-mentioned materials. For example, the first body insulating layer 101 may include polyimide isoindro quirazorindione (PIQ), polyimide (PI), polybenzoxazole (PBO), etc.

[0015] The first body insulating layer 101 has a multi-layer structure due to the multi-layer structure of the first redistribution lines 110. However, for convenience, the first body insulating layer 101 is illustrated as a single-layer structure in FIG. 1B. However, when the first body insulating layer 101 has a multi-layer structure, all layers of the first body insulating layer 101 may contain the same material, or at least one layer may contain a different material.

[0016] The first redistribution lines 110 may be arranged in multiple layers within the first body insulating layer 101. The first redistribution lines 110 arranged in different layers may be connected to each other by vertical vias. For reference, the vertical vias are not shown in FIG. 1B. The first redistribution lines 110 and the vertical vias may include, for example, copper (Cu). However, the material of the first redistribution lines 110 and the vertical vias is not limited to Cu.

[0017] An external connection terminal 700 may be disposed on the lower surface of the first body insulating layer 101. The external connection terminal 700 may be disposed on an external connection pad disposed on the lower surface of the first body insulating layer 101. The external connection pad may be included as a part of the first redistribution line 110. However, in some embodiments, the external connection pad is treated as a separate component from the first redistribution line 110.

[0018] The first semiconductor chip 200 may be mounted on the first redistribution substrate 100 via the first connecting terminal 250. The first connecting terminal 250 may include a metal pillar or solder. In some embodiments, the first connecting terminal 250 may include a metal pillar and solder. Here, the metal pillar may include, for example, Cu. However, the material of the metal pillar is not limited to Cu.

[0019] The first semiconductor chip 200 may be arranged offset to one side in the x-direction on the first redistribution substrate 100. For example, as shown in FIG. 1B, the first semiconductor chip 120 may be arranged offset to the right side in the x-direction on the first redistribution substrate 100. In addition, since the first semiconductor chip 200 is arranged offset to the right side in the x-direction, the second semiconductor chip 600 above the first semiconductor chip 200 may also be arranged offset to the right side. This arrangement structure is also intended to effectively dissipate heat generated by the first semiconductor chip 200 and the second semiconductor chip 600.

[0020] The first semiconductor chip 200 may be an analog chip. For example, the first semiconductor chip 200 may be a modem chip that supports communication with the second semiconductor chip 600. However, the type of the first semiconductor chip 200 is not limited to a modem chip. For example, the first semiconductor chip 200 may include various types of integrated devices that support the operation of the second semiconductor chip 600. The first semiconductor chip 200 may include a multi-channel I / O interface for exchanging memory signals with the memory device 500. The first semiconductor chip 200 may also include an SRAM for temporarily storing data.

[0021] As shown in FIG. 1B , the first semiconductor chip 200 may include a substrate 201, an active layer 210, and a through-electrode 220. The substrate 201 constitutes the body of the first semiconductor chip 200 and may be based on a silicon wafer. The active layer 210 may be disposed below the substrate 201. Strictly speaking, the active layer 210 may include an integrated circuit layer in which active elements such as transistors are disposed, and a multilayer wiring layer disposed on the integrated circuit layer. Generally, the multilayer wiring layer occupies most of the active layer 210, and the integrated circuit layer occupies only a portion of the active layer 210. Meanwhile, the multilayer wiring layer may include multiple wiring lines, and wiring lines in different layers may be connected to each other through vias. Chip pads connected to the wiring lines of the multilayer wiring layer may be disposed on the lower surface of the active layer 210, and the first connecting terminals 250 may be disposed on the chip pads.

[0022] The through electrodes 220 may extend vertically, i.e., in the z-direction, and penetrate the substrate 201. A lower surface of the through electrodes 220 may be connected to a wiring line of a multilayer wiring layer of the active layer 210, and an upper surface of the through electrodes 220 may be connected to a second connecting terminal 270. For example, an upper pad may be disposed on the upper surface of the through electrodes 220, and the second connecting terminal 270 may be connected to the through electrodes 220 via the upper pad. Therefore, the first semiconductor chip 200 may be connected to the second redistribution substrate 400 via the through electrodes 220 and the second connecting terminal 270. In addition, the first semiconductor chip 200 may be connected to the second semiconductor chip 600 via the second redistribution line 410 of the second redistribution substrate 400 and the fourth connecting terminal 650.

[0023] The through electrode 220 has a structure that penetrates the silicon that constitutes the substrate 201, and is therefore also referred to as a TSV (Through Silicon Via). For reference, the through electrode 220 may be classified into a via-first structure formed before the formation of the integrated circuit layer of the active layer 210, a via-middle structure formed after the formation of the integrated circuit layer but before the formation of the multilayer wiring layer of the active layer 210, and a via-last structure formed after the formation of the multilayer wiring layer. In FIG. 1B , the through electrode 220 may correspond to, for example, a via-middle structure. However, without being limited thereto, in the semiconductor package 1000 of this embodiment, the through electrode 220 may have a via-first or via-last structure.

[0024] The lower surface of the first semiconductor chip 200 may be referred to as a front side, which is an active surface, and the upper surface may be referred to as a back side, which is an inactive surface. That is, the lower surface of the active layer 210 may correspond to the front side of the first semiconductor chip 200, and the upper surface of the substrate 201 may correspond to the back side of the first semiconductor chip 200. Chip pads may be formed on the front side, which is the active side, and the first semiconductor chip 200 may be mounted on the first redistribution substrate 100 via first connecting terminals 250 arranged on the chip pads.

[0025] The through post 300 may be disposed between the first redistribution substrate 100 and the second redistribution substrate 400. By disposing a first encapsulant 910 between the first redistribution substrate 100 and the second redistribution substrate 400, the through post 300 has a structure extending in the z-direction through the first encapsulant 910. The through post 300 may electrically connect the first redistribution substrate 100 and the second redistribution substrate 400. For example, the through post 300 may be connected to the first redistribution line 110 of the first redistribution substrate 100 and to the second redistribution line 410 of the second redistribution substrate 400.

[0026] In the semiconductor package 1000 of this embodiment, the through posts 300 may include first through posts 310 and second through posts 320. As can be seen in FIGS. 1A and 1B , the first through posts 310 may be arranged on the first redistribution substrate 100 on the left side of the first semiconductor chip 200 in the x direction. The first through posts 310 may be arranged, for example, in a two-dimensional array on the first redistribution substrate 100 on the left side of the first semiconductor chip 200 in the x direction. The first through posts 310 may be connected to the semiconductor device 500 through the second redistribution substrate 400.

[0027] The second through posts 320 may be arranged on the first redistribution substrate 100 to the right of the first semiconductor chip 200 in the x direction. The second through posts 320 may be arranged in, for example, a single row on the first redistribution substrate 100 to the right of the first semiconductor chip 200 in the x direction. However, in some embodiments, the second through posts 320 may be arranged in multiple rows. The second through posts 320 may be connected to the second semiconductor chip 600 via the second redistribution substrate 400.

[0028] Meanwhile, the left and right sides in the x direction are relative concepts. Therefore, the positions of the first semiconductor chip 200, the first through post 310, the second through post 320, etc. may be changed. For example, the first semiconductor chip 200 may be disposed offset to the left in the x direction, the first through post 310 may be disposed to the right of the first semiconductor chip 200 in the x direction, and the second through post 320 may be disposed to the left of the first semiconductor chip 200 in the x direction. Furthermore, the second semiconductor chip 600 may be disposed to the left in the x direction corresponding to the first semiconductor chip 200, and the semiconductor element 500 may be disposed to the right in the x direction.

[0029] The through post 300 may include, for example, Cu. However, the material of the through post 300 is not limited to Cu. The through post 300 may be formed by electroplating using a seed metal. As such, the through post 300 may be referred to as a Cu-post. The seed metal may include various metal materials, such as Cu, titanium (Ti), tantalum (Ta), titanium nitride (TiN), and tantalum nitride (TaN). In the semiconductor package 1000 of this embodiment, the seed metal may be included as part of the through post 300. For example, both the seed metal and the through post 300 may be made of Cu. As such, the seed metal is not separately illustrated in FIG. 1B .

[0030] The second redistribution substrate 400 may be disposed on the first semiconductor chip 200, the through posts 300, and the first encapsulant 910. The second redistribution substrate 400 may have a similar structure to the first redistribution substrate 100 but may differ in thickness. For example, the second redistribution substrate 400 may include a second body insulating layer 401 and second redistribution lines 410. However, the number of layers of the second redistribution lines 410 of the second redistribution substrate 400 is smaller than the number of layers of the first redistribution lines 110 of the first redistribution substrate 100. However, in some embodiments, the number of layers of the second redistribution lines 410 of the second redistribution substrate 400 may be substantially the same as the number of layers of the first redistribution lines 110 of the first redistribution substrate 100. Meanwhile, the second redistribution lines 410 of the second redistribution substrate 400 may be electrically connected to the external connection terminals 700 through the through posts 300 and the first redistribution lines 110 of the first redistribution substrate 100 .

[0031] The semiconductor device 500 may be mounted on the second redistribution substrate 400 via the third connecting terminal 550. The semiconductor device 500 may be disposed on the left side of the second redistribution substrate 400 in the x-direction, corresponding to the first through-post 310. The semiconductor device 500 may be a single chip or a package including multiple chips. For example, if the semiconductor device 500 is a single chip, the semiconductor device 500 may include one memory chip. If the semiconductor device 500 is a package, the semiconductor device 500 may include multiple memory chips. The memory chip of the semiconductor device 500 may include, for example, a volatile memory device such as a dynamic random access memory (DRAM) or a static random access memory (SRAM), or a non-volatile memory device such as a flash memory. In the semiconductor package 1000 of this embodiment, the memory chip of the semiconductor device 500 may be, for example, a DRAM chip. The type of memory chip of the semiconductor device 500 is not limited to a DRAM chip. The single-chip structure or package structure of semiconductor device 500 will be described in further detail in the description of Figures 2A-2C.

[0032] Meanwhile, when the semiconductor device 500 is a package, the semiconductor package 1000 of this embodiment may have a POP (Package On Package) structure. For example, in the semiconductor package 1000 of this embodiment, the first redistribution substrate 100, the first semiconductor chip 200, the through posts 300, and the second redistribution substrate 400 may form a lower package, and the semiconductor device 500 of the package structure may form an upper package. As a result, the semiconductor package 1000 of this embodiment has a POP structure in which the upper package is stacked on the lower package.

[0033] The second semiconductor chip 600 may be mounted on the second redistribution substrate 400 via the fourth connecting terminals 650. The second semiconductor chip 600 may be disposed on the right side of the second redistribution substrate 400 in the x direction, corresponding to the first semiconductor chip 200. By disposing the second semiconductor chip 600 on the first semiconductor chip 200 in this manner, the signal path between the first semiconductor chip 200 and the second semiconductor chip 600 may be minimized and heat dissipation characteristics may be maximized.

[0034] In some embodiments, the second semiconductor chip 600 may be mounted on the second redistribution substrate 400 via pad-to-pad bonding, hybrid bonding (HB), or bonding using anisotropic conductive film (ACF). For reference, pad-to-pad bonding is also referred to as Cu-to-Cu bonding because the pads are typically formed of Cu. HB may refer to a combination of pad-to-pad bonding and insulator-to-insulator bonding. ACF is an anisotropic conductive film that conducts electricity in only one direction and may refer to a conductive film formed into a film by mixing fine conductive particles into an adhesive resin.

[0035] The second semiconductor chip 600 may be a logic chip. Accordingly, the second semiconductor chip 600 may include a number of logic elements therein. Here, the logic elements are elements that perform various signal processing, and may include, for example, AND, OR, NOT, flip-flops, etc. In the semiconductor package 1000 of this embodiment, the second semiconductor chip 600 may be, for example, an AP (Application Processor) chip. The second semiconductor chip 600 may also be referred to as a control chip, a process chip, a CPU chip, etc. depending on its function. Meanwhile, in terms of integrated functionality, the second semiconductor chip 600 may be referred to as a SoC (System on Chip) together with the first semiconductor chip 200 or independently.

[0036] The second semiconductor chip 600 may include a substrate and an active layer. However, unlike the first semiconductor chip 200, the second semiconductor chip 600 does not include through-electrodes. The active layer may include an integrated circuit layer and a multilayer wiring layer. The integrated circuit layer may include a number of integrated elements. The multilayer wiring layer may be disposed below the integrated circuit layer and may include multiple wiring lines. In the second semiconductor chip 600, the lower surface may be the front surface, which is the active surface, and the upper surface may be the back surface, which is the non-active surface. In other words, the lower surface of the active layer may correspond to the front surface of the second semiconductor chip 600, and the upper surface of the substrate may correspond to the back surface of the second semiconductor chip 600.

[0037] The external connection terminals 700 may be electrically connected to the first redistribution lines 110 via external connection pads disposed on the lower surface of the first redistribution substrate 100. Thus, the external connection terminals 700 may be electrically connected to the first semiconductor chip 200 via the first redistribution lines 110 and the first connection terminals 250 of the first redistribution substrate 100. The external connection terminals 700 may also connect the semiconductor package 1000 to a package substrate of an external system or a main board of an electronic device such as a mobile phone. The external connection terminals 700 may include at least one of a conductive material, for example, solder, tin (Sn), silver (Ag), copper (Cu), and aluminum (Al). However, the material of the external connection terminals 700 is not limited to the above-mentioned materials.

[0038] The external connection terminals 700 may be arranged on a first lower surface portion of the first redistribution substrate 100 corresponding to the lower surface of the first semiconductor chip 200, and on a second lower surface portion of the first redistribution substrate 100 extending outward in the x and y directions from the first lower surface portion. A package structure in which the external connection terminals 700 are arranged in an area wider than the lower surface of the first semiconductor chip 200 is referred to as a fan-out (FO) package structure. On the other hand, a package structure in which the external connection terminals 700 are arranged only in the first lower surface portion corresponding to the lower surface of the first semiconductor chip 200 is referred to as a fan-in (FI) package structure.

[0039] The passive element 800 may be disposed on the lower surface of the first redistribution substrate 100. Depending on the embodiment, the passive element 800 may be disposed on the upper surface of or inside the first redistribution substrate 100. The passive element 800 may also be disposed on the lower surface, upper surface, or inside the second redistribution substrate 400. The passive element 800 may include a two-terminal element such as a resistor, inductor, or capacitor. In the semiconductor package 1000 of this embodiment, the passive element 800 may include an MLCC 810 (Multi-Layer Ceramic Capacitor) and a Si-capacitor 820.

[0040] The encapsulant 900 may include a first encapsulant 910 and a second encapsulant 920. The first encapsulant 910 may be disposed between the first redistribution substrate 100 and the second redistribution substrate 400. The first encapsulant 910 may cover and seal the side surfaces of the through posts 300 and the side and top surfaces of the first semiconductor chip 200. In some embodiments, the first semiconductor chip 200 is connected to the second redistribution substrate 400 by pad-to-pad bonding, HB bonding, ACF bonding, or the like, and the first encapsulant 910 is not disposed between the first semiconductor chip 200 and the second redistribution substrate 400.

[0041] The second encapsulant 920 may be disposed on the second redistribution substrate 400 and may cover and seal side surfaces of the semiconductor device 500 and the second semiconductor chip 600. The second encapsulant 920 may fill a gap between the second redistribution substrate 400 and the semiconductor device 500 and between the third connecting terminals 550. The second encapsulant 920 may also fill a gap between the second redistribution substrate 400 and the second semiconductor chip 600 and between the fourth connecting terminals 650.

[0042] However, in some embodiments, an underfill may be filled between the semiconductor device 500 and the second redistribution substrate 400 and between the third connecting terminal 550, and the sides of the underfill may be covered with the second encapsulant 920. In some embodiments, an underfill may be filled between the second semiconductor chip 600 and the second redistribution substrate 400 and between the fourth connecting terminal 650, and the sides of the underfill may be covered with the second encapsulant 920.

[0043] Meanwhile, the second encapsulant 920 may encapsulate the semiconductor device 500 and the second semiconductor chip 600 by exposing the top surfaces of the semiconductor device 500 and the second semiconductor chip 600. For example, as shown in FIG. 1B , the top surfaces of the semiconductor device 500, the second semiconductor chip 600, and the second encapsulant 920 may be substantially flush with each other. Because the second semiconductor chip 600 is exposed from the second encapsulant 920, the heat dissipation characteristics of the second semiconductor chip 600 may be maximized. In addition, because the second encapsulant 920 has a structure that exposes the top surfaces of the semiconductor device 500 and the second semiconductor chip 600, the thickness of the second encapsulant 920 may be minimized, thereby reducing the overall thickness of the semiconductor package 1000.

[0044] In the semiconductor package 1000 of this embodiment, for example, the first semiconductor chip 200 has a thickness of 0.2 mm or less, the second semiconductor chip 600 has a thickness of 0.5 mm or less, and the total thickness of the package can be 1.0 mm or less. In addition, in terms of the area of the semiconductor package 1000 of this embodiment, for example, the first semiconductor chip 200 has a thickness of 13.0*11.0 mm. 2 The second semiconductor chip 600 has the following dimensions: 12*10 mm 2 The semiconductor element 500 has the following dimensions: 7.0*12.5mm 2 The overall package area is 17.0*14.0mm. 2 However, the thickness and area of the components of the semiconductor package 1000 of this embodiment are not limited to the above values.

[0045] The encapsulant 900 may include an insulating material, for example, a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a resin containing a reinforcing material such as an inorganic filler. For example, the encapsulant 900 may include ABF, FR-4, BT resin, etc. The encapsulant 900 may also include a molding material such as EMC, or a photosensitive material such as PIE (Photo Imageable Encapsulant). However, the material of the encapsulant 900 is not limited to the above-mentioned materials.

[0046] 1A , the planar sizes and positional relationships of the first and second redistribution substrates 100 and 400, the first and second semiconductor chips 200 and 600, and the semiconductor device 500 will be briefly described. The first and second redistribution substrates 100 and 400 have substantially the same planar size as the encapsulant 900. Therefore, the first semiconductor chip 200 and the through-posts 300 may be located within the first redistribution substrate 100. In addition, the semiconductor device 500 and the second semiconductor chip 600 disposed on the through-posts 300 and the first semiconductor chip 200 may also be located within the second redistribution substrate 400.

[0047] Alternatively, most of the first semiconductor chip 200 may overlap the second semiconductor chip 600, and only a portion of the first semiconductor chip 200 may overlap the semiconductor device 500. Specifically, the semiconductor device 500 may overlap the first through-posts 310 and the left portion of the first semiconductor chip 200 in the x-direction. The second semiconductor chip 600 may overlap the second through-posts 320 and the center and right portions of the first semiconductor chip 200 in the x-direction.

[0048] The semiconductor package 1000 of this embodiment has a fan-out wafer-level package (FOWLP) structure, which can maximize heat dissipation characteristics and achieve a small form factor. Specifically, the first semiconductor chip 200 is connected to the second redistribution substrate 400 via the through electrodes 220 and the second connecting terminals 270. The first semiconductor chip 200 has a large thickness corresponding to the first encapsulant 910. Therefore, heat generated in the first semiconductor chip 200 can be effectively transferred to the second redistribution substrate 400. The second semiconductor chip 600 is disposed on the second redistribution substrate 400 with its top surface exposed. The second semiconductor chip 600 has a large thickness corresponding to the second encapsulant 920. Therefore, heat generated in the second semiconductor chip 600 can be effectively dissipated, and heat generated in the first semiconductor chip 200 can also be dissipated upward from the semiconductor package 1000 along with the second redistribution substrate 400. As a result, the heat dissipation characteristics of the semiconductor package 1000 can be significantly improved.

[0049] 1A and 1B, the semiconductor package 1000 of this embodiment may achieve a small form factor by vertically stacking the first semiconductor chip 200 and the second semiconductor chip 600 via the second redistribution substrate 400. Furthermore, by disposing the second through-posts 320 below the second semiconductor chip 600, power may be effectively transmitted to the second semiconductor chip 600 via the second through-posts 320. For example, the power path to the second semiconductor chip 600 may be configured to be the shortest distance using the second through-posts 320 and the second redistribution substrate 400. Meanwhile, the semiconductor package 1000 of this embodiment does not require separate fabrication of the first semiconductor chip 200 and the second semiconductor chip 600 in a 3D-IC structure. Therefore, the semiconductor package 1000 of this embodiment may achieve a gain in turn-around time (TAT) and is significantly advantageous in terms of throughput and investment efficiency.

[0050] For reference, consider a structure in which a first semiconductor chip 200 and a second semiconductor chip 600 have a 3D-IC structure and are applied to a semiconductor package. Here, the 3D-IC structure may refer to a structure in which the second semiconductor chip 600 is directly stacked on the first semiconductor chip 200 via connecting terminals for integration. A semiconductor package structure in which the 3D-IC structure is disposed between a lower redistribution substrate and an upper redistribution substrate may achieve a small form factor but has limitations in heat dissipation characteristics. To improve heat dissipation characteristics, a heat path block (HPB) such as a heat sink may be added to the upper redistribution substrate, but this increases the overall thickness of the semiconductor package. On the other hand, a semiconductor package structure in which the upper redistribution substrate is omitted and a semiconductor device including a memory chip and the 3D-IC are disposed together on a single redistribution substrate may maximize heat dissipation characteristics, but may have limitations in achieving a small form factor because the 3D-IC is disposed side-by-side with the semiconductor device.

[0051] Meanwhile, the semiconductor package 1000 of this embodiment can simultaneously realize maximized heat dissipation characteristics and a small form factor by using the FOWLP structure as described above. Also, the semiconductor package 1000 of this embodiment is advantageous over package structures including 3D-IC structures in terms of power supply to the second semiconductor chip 600, TAT gain, throughput, and investment costs.

[0052] 2A to 2C are cross-sectional views showing in more detail the structure of the memory element in the semiconductor package of FIG. 1B.

[0053] 2A , the semiconductor device 500 may include one memory chip. The memory chip may include, for example, a volatile memory device such as a DRAM or an SRAM, or a non-volatile memory device such as a flash memory. In the semiconductor package 1000 of this embodiment, the memory chip of the semiconductor device 500 may include, for example, a DRAM chip. The semiconductor device 500 may be mounted on the second redistribution substrate 400 using a flip-chip bonding structure using the third connecting terminals 550. The third connecting terminals 550 may include a pillar and a solder, or may include only a solder.

[0054] Referring to FIG. 2B, the semiconductor device 500a may include a semiconductor package having a wire bonding structure. Specifically, the semiconductor device 500a may include a package substrate 510 and a plurality of memory chips 520 stacked on the package substrate 510. The memory chips 520 may be mounted on the package substrate 510 using a wire bonding structure using an adhesive layer 525 and wires 530. The memory chips 520 of the semiconductor device 500a may include, for example, volatile memory devices such as DRAM or SRAM, or non-volatile memory devices such as flash memory. In the semiconductor package 1000 of this embodiment, the memory chips 520 of the semiconductor device 500a may include, for example, DRAM chips. Meanwhile, the semiconductor device 500a may include an inner encapsulant that encapsulates the memory chips 520 and wires 530 on the package substrate 510. However, the inner encapsulant is omitted from FIG. 2B for convenience.

[0055] 2B, four memory chips 520 are stacked on the package substrate 510, but the number of memory chips 520 is not limited to four. For example, three or fewer or five or more memory chips 520 may be stacked on the package substrate 510. Furthermore, the memory chips 520 are not limited to being stacked in a staircase structure, but may be stacked on the package substrate 510 in a zigzag structure or a combined structure of a staircase structure and a zigzag structure. The semiconductor device 500a having a package structure may also be mounted on the second redistribution substrate 400 via the third connecting terminals 550.

[0056] 2C, the semiconductor device 500b may include a High Bandwidth Memory (HBM) package. Specifically, the semiconductor device 500b may include a base chip 510a, a plurality of core chips 520a stacked on the base chip 510a, and an inner encapsulant 540. The base chip 510a and the core chips 520a may include through electrodes 530a therein. Meanwhile, the uppermost core chip 520a does not include through electrodes 530a.

[0057] The base chip 510a may include logic elements. Therefore, the base chip 510a may be a logic chip. The base chip 510a may be disposed below the core chip 520a. The base chip 510a may integrate signals from the core chip 520a and transmit them to the outside, and may transmit external signals and power to the core chip 520a. Therefore, the base chip 510a may also be referred to as a buffer chip or a control chip. Each of the core chips 520a may be a memory chip. For example, each of the core chips 520a may be a DRAM chip. Each of the core chips 520a may be stacked on the base chip 510a or a lower core chip 520a via pad-to-pad bonding, HB bonding, bonding using a connection terminal, or bonding using ACF. Although four core chips 520a are stacked on the base chip 510a in FIG. 2C , the number of core chips 520a is not limited to four. For example, three or fewer or five or more core chips 520a can be stacked on the base chip 510a.

[0058] A third connecting terminal 550 may be disposed on the lower surface of the base chip 510a. Therefore, the semiconductor device 500b in the HBM package may also be mounted on the second redistribution substrate 400 via the third connecting terminal 550. The core chips 520a on the base chip 510a may be sealed by an inner sealant 540. However, the uppermost core chip 520a among the core chips 520a is not covered by the inner sealant 540. However, in other embodiments, the uppermost core chip 520a may be covered by the inner sealant 540.

[0059] 3A and 3B are plan views of a semiconductor package according to an embodiment of the present invention, each corresponding to the plan view of FIG. 1A. Contents already described in the description of FIGS. 1A to 2C will be briefly described or omitted.

[0060] 3A, the semiconductor package 1000a of this embodiment may differ from the semiconductor package 1000 of FIG. 1A in the arrangement of the through posts 300a. Specifically, the semiconductor package 1000a of this embodiment may include a first redistribution substrate 100, a first semiconductor chip 200, through posts 300a, a second redistribution substrate 400, a semiconductor device 500, a second semiconductor chip 600, external connecting terminals 700, a passive device 800, and an encapsulant 900. The first redistribution substrate 100, the first semiconductor chip 200, the second redistribution substrate 400, the semiconductor device 500, the second semiconductor chip 600, the external connecting terminals 700, the passive device 800, and the encapsulant 900 are the same as those described above for the semiconductor package 1000 of FIG. 1A.

[0061] In the semiconductor package 1000a of this embodiment, the through-posts 300a may be arranged only on the first redistribution substrate 100 on the left side of the first semiconductor chip 200 in the x direction. That is, the through-posts 300a are not arranged on the first redistribution substrate 100 on the right side of the first semiconductor chip 200 in the x direction. As a result, the first semiconductor chip 200 may be arranged more to the right in the x direction on the first redistribution substrate 100. As a result, the area of the first semiconductor chip 200 overlapping with the second semiconductor chip 600 increases, and the heat dissipation efficiency of the first semiconductor chip 200 may be improved.

[0062] 3B, the semiconductor package 1000b of this embodiment may differ from the semiconductor package 1000 of FIG. 1A in the arrangement of the through posts 300b. Specifically, the semiconductor package 1000b of this embodiment may include a first redistribution substrate 100, a first semiconductor chip 200, through posts 300b, a second redistribution substrate 400, a semiconductor device 500, a second semiconductor chip 600, external connecting terminals 700, a passive device 800, and an encapsulant 900. The first redistribution substrate 100, the first semiconductor chip 200, the second redistribution substrate 400, the semiconductor device 500, the second semiconductor chip 600, the external connecting terminals 700, the passive device 800, and the encapsulant 900 are the same as those described for the semiconductor package 1000 of FIG. 1A.

[0063] In the semiconductor package 1000b of this embodiment, the through posts 300b may include a first through post 310 and a second through post 320a. The first through post 310 may be arranged on the first redistribution substrate 100 to the left of the first semiconductor chip 200 in the x direction. The second through posts 320a may be arranged on the first redistribution substrate 100 to the right of the first semiconductor chip 200 in the x direction and on both sides of the first semiconductor chip 200 in the y direction. That is, the second through posts 320a may be arranged to surround the first semiconductor chip 200 to the right of the first semiconductor chip 200 in the x direction and on both sides of the first semiconductor chip 200 in the y direction. For example, the second through posts 320a may be arranged in a single row surrounding three sides of the first semiconductor chip 200. However, in some embodiments, the second through posts 320a may be arranged in multiple rows surrounding three sides of the first semiconductor chip 200.

[0064] In the semiconductor package 1000b of this embodiment, more second through posts 320a may be arranged under the second redistribution substrate 400 corresponding to the second semiconductor chip 600. Therefore, the number of power supply paths in the second semiconductor chip 600 may be increased, and the effectiveness of power transmission to the second semiconductor chip 600 may be further improved.

[0065] 4 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention, which may correspond to the cross-sectional view of FIG. 1B. Contents already described in the description of FIGS. 1A to 3B will be briefly described or omitted.

[0066] 4, the semiconductor package 1000c of this embodiment may differ from the semiconductor package 1000 of FIG. 1B in the structures of the second semiconductor chip 600a and the encapsulant 900a. Specifically, the semiconductor package 1000c of this embodiment may include a first redistribution substrate 100, a first semiconductor chip 200, through posts 300, a second redistribution substrate 400, a semiconductor device 500, a second semiconductor chip 600a, external connecting terminals 700, a passive device 800, and an encapsulant 900a. The first redistribution substrate 100, the first semiconductor chip 200, the second redistribution substrate 400, the semiconductor device 500, the external connecting terminals 700, and the passive device 800 are the same as those described for the semiconductor package 1000 of FIG. 1A.

[0067] In the semiconductor package 1000c of this embodiment, the thickness of the second semiconductor chip 600a is thinner than the thickness of the second semiconductor chip 600 in the semiconductor package 1000 of FIG. 1B. Therefore, a second height H2, which is the height of the top surface of the second semiconductor chip 600a mounted on the second redistribution substrate 400, is lower than a first height H1, which is the height of the top surface of the semiconductor element 500 mounted on the second redistribution substrate 400. Furthermore, since the top surface of the second semiconductor chip 600a is lower than the top surface of the semiconductor element 500, the encapsulant 900a may cover the top surface of the second semiconductor chip 600a. Specifically, the second encapsulant 920a may expose the top surface of the semiconductor element 500 and the top surface of the second semiconductor chip 600a. For reference, having the top surface of the second semiconductor chip 600a exposed from the encapsulant 900a is advantageous in terms of heat dissipation characteristics. However, when the semiconductor device 500 has a package structure, the second semiconductor chip 600a, which corresponds to the chip, is relatively thinner than the semiconductor device 500. Therefore, the semiconductor package 1000c of this embodiment can be realized in the manufacturing process. The method of manufacturing the semiconductor package 1000c of this embodiment will be described in more detail in the description of Figures 7A to 7C.

[0068] Although the structures of several semiconductor packages 1000, 1000a to 1000c have been described above, the technical concept of the present invention is not limited to the above-described semiconductor package structures. For example, the technical concept of the present invention can be applied to all semiconductor package structures having a FOWLP 3D stacked structure and all semiconductor package structures requiring a redistribution layer (RDL) process.

[0069] 5A to 5J are cross-sectional views schematically illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. The description will be made with reference to both FIGS. 1A and 1B, and the contents already described in the description of FIGS. 1A to 4 will be briefly described or omitted.

[0070] 5A , the method for manufacturing a semiconductor package according to this embodiment first forms an upper redistribution substrate 400s. The upper redistribution substrate 400s may include a second body insulating layer 401 and second redistribution lines 410. The upper redistribution substrate 400s may be formed on a first carrier substrate 2000a. The first carrier substrate 2000a may be a large-sized substrate such as a wafer. The upper redistribution substrate 400s formed on the first carrier substrate 2000a may be a large-sized redistribution substrate including a plurality of second redistribution substrates 400. Meanwhile, although not shown, an adhesive layer may be disposed between the upper redistribution substrate 400s and the first carrier substrate 2000a. The adhesive layer may adhere and fix the upper redistribution substrate 400s to the first carrier substrate 2000a.

[0071] For reference, a semiconductor package that is formed by forming subsequent components on a large-sized rewiring substrate and then separating the components through a sawing process or a singulation process is also referred to as a wafer level package (WLP). However, for convenience of explanation, only components corresponding to one second rewiring substrate 400 are shown in FIG. 5A and subsequent drawings.

[0072] 5B, after the upper redistribution substrate 400s is formed, the semiconductor device 500 and the second semiconductor chip 600 are mounted on a first surface of the upper redistribution substrate 400s. Here, the first surface may correspond to the top surface of the second redistribution substrate 400 in the semiconductor package 1000 of FIG. 1B. Specifically, the semiconductor device 500 may be mounted on the first surface of the upper redistribution substrate 400s via the third connecting terminals 550, and the second semiconductor chip 600 may be mounted on the first surface of the upper redistribution substrate 400s adjacent to the semiconductor device 500 in the x-direction via the fourth connecting terminals 650. Various bonding processes, such as reflow, thermal compression bonding (TCB), and laser assisted bonding (LAB), may be used to mount the semiconductor device 500 using the third connecting terminals 550 and the second semiconductor chip 600 using the fourth connecting terminals 650. The semiconductor device 500 and the second semiconductor chip 600 are as described in the description of FIGS. 1A to 2C.

[0073] 5B, the heights of the top surfaces of the semiconductor device 500 and the second semiconductor chip 600 mounted on the first surface of the upper redistribution substrate 400s may be substantially the same, i.e., each may have a first height H1. However, the thicknesses of the semiconductor device 500 and the second semiconductor chip 600 may be the same or different. Accordingly, the heights of the third connecting terminal 550 and the fourth connecting terminal 650 may be adjusted to make the heights of the top surfaces of the semiconductor device 500 and the second semiconductor chip 600 substantially the same. Furthermore, in a subsequent grinding process of the upper encapsulant 920s1, an upper portion of either the semiconductor device 500 or the second semiconductor chip 600 may be removed.

[0074] 5C , after the semiconductor device 500 and the second semiconductor chip 600 are mounted on the first surface of the upper redistribution substrate 400s, the semiconductor device 500 and the second semiconductor chip 600 are sealed with an upper encapsulant 920s1. The upper encapsulant 920s1 may cover the side and top surfaces of the semiconductor device 500 and the second semiconductor chip 600. The upper encapsulant 920s1 may also fill the spaces between the upper redistribution substrate 400s and the semiconductor device 500, between the upper redistribution substrate 400s and the second semiconductor chip 600, between the third connecting terminals 550, and between the fourth connecting terminals 650. However, in some embodiments, an underfill may be filled between the upper redistribution substrate 400s and the second semiconductor chip 600 and the third connecting terminal 550, and / or between the upper redistribution substrate 400s and the second semiconductor chip 600 and the fourth connecting terminal 650, and the upper encapsulant 920s1 may cover a side surface of the underfill. The material of the upper encapsulant 920s1 is the same as that described in the description of the semiconductor package 1000 in FIG. 1B.

[0075] 5D, the upper portion of the upper encapsulant 920s1 is then removed through a mold grinding (MG) process. After the MG process, the upper surfaces of the semiconductor device 500 and the second semiconductor chip 600 may be exposed from the upper encapsulant 920s. In addition, because the upper surfaces of the semiconductor device 500 and the second semiconductor chip 600 are exposed through the MG process, the upper surfaces of the semiconductor device 500, the second semiconductor chip 600, and the upper encapsulant 920s may be substantially flush with each other.

[0076] 5E, after the MG process, the upper redistribution substrate 400s and the structure thereon are separated from the first carrier substrate 2000a and attached upside down to the second carrier substrate 2000b. That is, as shown in FIG. 5E, the semiconductor device 500, the second semiconductor chip 600, and the upper encapsulant 920s may be positioned at the bottom of the second carrier substrate 2000b, and the upper redistribution substrate 400s may be positioned at the top. Also, the exposed top surfaces of the semiconductor device 500, the second semiconductor chip 600, and the upper encapsulant 920s may be attached to the top surface of the second carrier substrate 2000b with their exposed top surfaces facing downward. Meanwhile, although not shown, an adhesive layer may be disposed between the exposed top surfaces of the semiconductor device 500, the second semiconductor chip 600, and the upper encapsulant 920s and the second carrier substrate 2000b.

[0077] Next, through posts 300 are formed on the second surface of the upper redistribution substrate 400s. Here, the second surface refers to the surface opposite to the first surface and may correspond to the bottom surface of the second redistribution substrate 400 in the semiconductor package 1000 of FIG. 1B. The through posts 300 may include a first through post 310 and a second through post 320. The first through post 310 corresponds to the semiconductor device 500 and may be disposed on the left side of the second surface of the upper redistribution substrate 400s in the x direction. The second through post 320 corresponds to the second semiconductor chip 600 and may be disposed on the right side of the second surface of the upper redistribution substrate 400s in the x direction. A method for forming the through posts 300 will be described in further detail with reference to FIGS. 6A to 6F.

[0078] 5F, after the through posts 300 are formed, the first semiconductor chip 200 is mounted on the second surface of the upper redistribution substrate 400s in a portion where the through posts 300 are not disposed. Specifically, the first semiconductor chip 200 may be mounted on the second surface of the upper redistribution substrate 400s via the second connecting terminals 270. The first connecting terminals 250 may be disposed on the upper surface of the first semiconductor chip 200. The first semiconductor chip 200 is as described in the description of the semiconductor package 1000 in FIG. 1B.

[0079] 5G, after the first semiconductor chip 200 is mounted, a lower encapsulant 910s is formed on the second surface of the upper redistribution substrate 400s to cover the through posts 300 and the first semiconductor chip 200. The lower encapsulant 910s may cover the side and top surfaces of the through posts 300 and the first semiconductor chip 200. The lower encapsulant 910s may also fill spaces between the first semiconductor chip 200 and the upper redistribution substrate 400s, between the second connecting terminals 270, and between the first connecting terminals 250.

[0080] Thereafter, the upper portion of the lower encapsulant 910s is removed through an MG process. Through the MG process on the lower encapsulant 910s, the upper surfaces of the through posts 300 and the first connecting terminals 250 of the first semiconductor chip 200 may be exposed from the lower encapsulant 910s. The material of the lower encapsulant 910s is the same as that described in the description of the semiconductor package 1000 in FIG. 1B.

[0081] 5H, a lower redistribution substrate 100s is then formed on the first semiconductor chip 200, the through posts 300, and the lower encapsulant 910s. The lower redistribution substrate 100s may include a first body insulating layer 101 and a first redistribution line 110. The lower redistribution substrate 100s may include a plurality of first redistribution substrates 100.

[0082] 5I, after the lower wiring substrate 100s is formed, external connection terminals 700 and passive elements 800 are attached to a first surface of the lower wiring substrate 100s. The first surface of the lower wiring substrate 100s corresponds to the lower surface of the first redistribution substrate 100 in the semiconductor package 1000 of FIG. 1B. Meanwhile, the external connection terminals 700 and the passive elements 800 are as described in the description of the semiconductor package 1000 of FIG. 1B.

[0083] 5J, after the external connection terminals 700 and the passive elements 800 are attached, the semiconductor packages included in the entire structure can be separated into individual pieces through a sawing process. The semiconductor package 1000 of FIG. 1B can be manufactured through separation using this sawing process. After the sawing process, a sorting process can be performed to separate non-defective products from defective products through electrical testing.

[0084] 6A-6F are cross-sectional views illustrating the step of FIG. 5E in greater detail.

[0085] 6A, in the method for manufacturing a semiconductor package according to this embodiment, the through posts 300 may be formed on the second surface of the upper redistribution substrate 400s through the following process. First, a seed metal 301 is formed on the second surface of the upper redistribution substrate 400s. The seed metal 301 is subsequently used in an electroplating process for forming the through posts 300. The seed metal 301 may be made of various metal materials, for example, Cu, Ti, Ta, TiN, TaN, etc. In the method for manufacturing a semiconductor package according to this embodiment, the seed metal 301 is made of Cu, for example.

[0086] 6B, a photoresist 1500 (PR) is then applied on the seed metal 301 of the upper redistribution substrate 400s. The PR 1500 may be applied by, for example, a spin coating method using a spin coater. The PR 1500 may be formed to a thickness corresponding to the length of the through post 300.

[0087] Referring to FIG. 6C, after the application of the PR 1500, an exposure process is performed. The exposure process may be performed using a mask having a specific pattern. For example, a transparent mask may be used to transmit light and irradiate specific portions of the PR 1500. The chemical properties of the irradiated portions of the PR 1500 may be changed. For example, after the exposure process, the PR 1500a may be divided into an unexposed portion 1510 and an exposed portion 1520. As can be seen in FIG. 6C, the exposed portions 1520 may be located on the left and right sides of the upper redistribution substrate 400s in the x direction. The exposed portion 1520 on the left side may correspond to the first through post 310, and the exposed portion 1520 on the right side may correspond to the second through post 320. Meanwhile, when manufacturing the semiconductor packages 1000a and 1000b of FIG. 3A or 3B, the positions of the exposed portions 1520 may vary depending on the arrangement of the through posts 300a and 300b.

[0088] 6D, after the exposure process, a development process is performed on PR 1500a. In the development process, for example, the exposed portion 1520 may be removed. For example, PR 1500a is a positive PR. Meanwhile, in some embodiments, negative PR may be used, and when negative PR is used, the unexposed portion may be removed in the development process.

[0089] The exposed portion 1520 may be removed through a development process to form a PR pattern 1500b. The PR pattern 1500b may include a number of through holes H. The seed metal 301 may be exposed at the bottom of the through holes H. Meanwhile, after the development process, by-products such as PR scum may remain inside the through holes H. Therefore, the by-products are removed through a cleaning process. For reference, the process of removing the PR scum is referred to as a PR descum process. Such a PR descum process may be included in the cleaning process.

[0090] 6E, after the cleaning process, through-posts 300 are formed inside the through-holes H by plating. The through-posts 300 may include a first through-post 310 on the left side of the upper redistribution substrate 400s in the x-direction and a second through-post 320 on the right side. The through-posts 300 may be made of, for example, Cu. Although not shown, the through-posts 300 may also be formed outside the through-holes H and on a portion of the top surface of the PR pattern 1500b adjacent to the through-holes H.

[0091] Referring to FIG. 6F, after the through posts 300 are formed, the PR pattern 1500b is removed. The PR pattern 1500b may be removed through an ashing / strip process. After removing the PR pattern 1500b, the seed metal 301 may be exposed between the through posts 300. Then, the seed metal 301 exposed between the through posts 300 is removed through an etching process. By removing the seed metal 301, the second surface of the upper redistribution substrate 400s may be exposed between the through posts 300. Meanwhile, the seed metal 301a on the lower surface of the through post 300 may be left intact. Because both the seed metal 301a and the through post 300 are made of Cu, the seed metal 301a and the through post 300 are illustrated as being integrated with the through post 300 in FIGS. 5E to 5J.

[0092] 7A to 7C are cross-sectional views schematically illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. The description will be made with reference to FIG. 4, and the parts already described in the description of FIGS. 5A to 6F will be briefly described or omitted.

[0093] 7A, in the method for manufacturing a semiconductor package according to this embodiment, first, an upper redistribution substrate 400s is formed on a first carrier substrate 2000a through the process of FIG. 5A. Then, a semiconductor device 500 and a second semiconductor chip 600a are mounted on a first surface of the upper redistribution substrate 400s. Specifically, the semiconductor device 500 may be mounted on the first surface of the upper redistribution substrate 400s via a third connecting terminal 550, and the second semiconductor chip 600a may be mounted on the first surface of the upper redistribution substrate 400s adjacent to the semiconductor device 500 via a fourth connecting terminal 650.

[0094] Meanwhile, the top surface of the semiconductor device 500 mounted on the first surface of the upper redistribution substrate 400s may have a first height H1, and the top surface of the second semiconductor chip 600a mounted on the first surface of the upper redistribution substrate 400s may have a second height H2. As shown in FIG. 7A , the second height H2 is lower than the first height H1. Specifically, the semiconductor device 500, the third connecting terminal 550, and the fourth connecting terminal 650 may be substantially identical to the semiconductor device 500, the third connecting terminal 550, and the fourth connecting terminal 650 of the first semiconductor package 1000, and thus may have the same thickness or height. Meanwhile, the second semiconductor chip 600a may have a thinner thickness than the second semiconductor chip 600 of the first semiconductor package 1000. Therefore, the second height H2 of the top surface of the second semiconductor chip 600a is lower than the first height H1 of the top surface of the semiconductor device 500.

[0095] 7B, after the semiconductor device 500 and the second semiconductor chip 600a are mounted on the first surface of the upper redistribution substrate 400s, the semiconductor device 500 and the second semiconductor chip 600a are sealed with an upper encapsulant 920s2. The upper encapsulant 920s2 may cover the side and top surfaces of the semiconductor device 500 and the second semiconductor chip 600a. The upper encapsulant 920s2 may also fill the spaces between the upper redistribution substrate 400s and the semiconductor device 500, between the upper redistribution substrate 400s and the second semiconductor chip 600a, between the third connecting terminals 550, and between the fourth connecting terminals 650. However, in some embodiments, an underfill may be filled between the upper redistribution substrate 400s and the semiconductor element 500, and between the third connecting terminal 550, and / or between the upper redistribution substrate 400s and the second semiconductor chip 600a, and between the fourth connecting terminal 650, and the upper sealing material 920s2 may cover the sides of the underfill.

[0096] Referring to Figure 7C, the upper portion of the upper encapsulant 920s2 is then removed through an MG process. After the MG process, the upper surface of the semiconductor device 500 may be exposed from the upper encapsulant 920sa. However, the upper surface of the second semiconductor chip 600a may not be exposed and may be covered by the upper encapsulant 920sa. Then, the semiconductor package 1000c of Figure 4 may be manufactured through the processes of Figures 5E to 5J.

[0097] Although the present invention has been described above with reference to the embodiments shown in the drawings, these are merely illustrative, and those skilled in the art will recognize that various modifications and equivalent embodiments are possible. Therefore, the true technical scope of the present invention should be determined by the technical spirit of the claims. [Explanation of symbols]

[0098] 100, 400 1st, 2nd rewiring board 100s Lower Rewiring Board 400s upper rewiring board 101, 401 First and second body insulating layers 110, 410 1st and 2nd wiring lines 200 First Semiconductor Chip 201 Substrate 210 active users 220, 530a Through electrode 250, 270, 550, 650 1st, 2nd, 3rd, 4th connection terminal 301, 301a seed metal 300, 300a, 300b through post 310 First Pier Post 320, 320a Second penetration post 500, 500a, 500b Semiconductor elements 510 package substrate 510a base chip 520 memory chips 520a core chip 525 Adhesive layer 530 Wire 600 Second Semiconductor Chip 700 External connection terminal 800 Passive Elements 900, 900a sealant 910 1st sealant 920, 920a 2nd sealant 910s lower sealant 920s1, 920s2, 920s, 920sa upper sealant 1000, 1000a~1000c semiconductor package 1500, 1500a PR 1500b PR pattern 2000a, 2000b First and second carrier substrates

Claims

1. a first rewiring substrate; a first semiconductor chip disposed on the first rewiring substrate on the right side in the first direction and having a through electrode; a first through post disposed on the first rewiring substrate on the left side in the first direction, adjacent to the first semiconductor chip; a second rewiring substrate disposed on the first semiconductor chip and the first through-post; a semiconductor element disposed on the second rewiring substrate on the left side in the first direction; a second semiconductor chip disposed on the second rewiring substrate adjacent to the semiconductor element and on the right side in the first direction;

2. 2. The semiconductor package of claim 1, wherein the first semiconductor chip is connected to the first redistribution substrate via a first connecting terminal disposed on a lower surface thereof, and is connected to the second redistribution substrate via a second connecting terminal disposed on an upper surface thereof and the through electrode.

3. The semiconductor package of claim 2 , wherein the first semiconductor chip is connected to the second semiconductor chip via the second redistribution substrate and the second connecting terminals.

4. the semiconductor element overlaps the first through post and a left portion of the first semiconductor chip in the first direction; The semiconductor package of claim 1 , wherein the second semiconductor chip overlaps a central portion and a right portion of the first semiconductor chip in the first direction.

5. Further included are second through posts disposed on the first redistribution substrate in at least a portion of a portion adjacent to a right side of the first semiconductor chip in the first direction and portions adjacent to both sides of the first semiconductor chip in a second direction perpendicular to the first direction, The semiconductor package of claim 4 , wherein the first and second through posts connect the first and second redistribution substrates.

6. a first sealing material disposed between the first redistribution substrate and the second redistribution substrate and sealing the first semiconductor chip; The semiconductor package of claim 1 , further comprising a second encapsulant disposed on the second redistribution substrate to encapsulate the semiconductor device and a second semiconductor chip.

7. The semiconductor package of claim 6 , wherein a top surface of the second semiconductor chip is exposed from the second encapsulant.

8. the semiconductor device is a memory chip or a memory package; 2. The semiconductor package according to claim 1, wherein the first semiconductor chip and the second semiconductor chip are logic chips.

9. a first rewiring substrate; a first semiconductor chip disposed on the first rewiring substrate on the right side in the first direction and having a through electrode; a first sealing material disposed on the first rewiring substrate and sealing the first semiconductor chip; a first through post disposed on the first redistribution substrate adjacent to the first semiconductor chip on the left side in the first direction, the first through post extending through the first sealing material; a second rewiring substrate disposed on the first semiconductor chip and the first through-post; a semiconductor element disposed on the second rewiring substrate on the left side in the first direction; a second semiconductor chip disposed on the second rewiring substrate adjacent to the semiconductor element on the right side in the first direction; a second sealing material disposed on the second redistribution substrate and sealing the semiconductor element and the second semiconductor chip; The semiconductor package, wherein the top surfaces of the semiconductor element and the second semiconductor chip are exposed from the second encapsulant.

10. the first semiconductor chip is connected to the first redistribution substrate through a first connecting terminal disposed on a lower surface thereof, and is connected to the second redistribution substrate through a second connecting terminal disposed on an upper surface thereof and the through electrode; The semiconductor package of claim 9 , wherein the first semiconductor chip is connected to the second semiconductor chip via the second redistribution substrate and the second connecting terminals.

11. the first redistribution substrate further includes second through posts disposed in at least a portion of a portion adjacent to a right side of the first semiconductor chip in the first direction and a portion adjacent to both sides of the first semiconductor chip in a second direction perpendicular to the first direction, the second through posts extending through the first sealing material, The semiconductor package of claim 9 , wherein the first and second through posts connect the first and second redistribution substrates.

12. a first rewiring substrate; a first semiconductor chip disposed on the first rewiring substrate and having a through electrode; a second rewiring substrate disposed on the first semiconductor chip; a semiconductor element disposed on the second rewiring substrate on the left side in the first direction; a second semiconductor chip disposed on the second rewiring substrate adjacent to the semiconductor element and on the right side in the first direction;

13. the first semiconductor chip is disposed on the first rewiring substrate on the right side in the first direction; The semiconductor package is a first through post disposed on the first rewiring substrate adjacent to the first semiconductor chip and on the left side in the first direction; 13. The semiconductor package of claim 12, further comprising: second through posts arranged on the first redistribution substrate in at least a portion of a portion adjacent to the right side of the first semiconductor chip in the first direction and a portion adjacent to both sides of the first semiconductor chip in a second direction perpendicular to the first direction.

14. the first semiconductor chip is connected to the first redistribution substrate through a first connecting terminal disposed on a lower surface thereof, and is connected to the second redistribution substrate through a second connecting terminal disposed on an upper surface thereof and the through electrode; The semiconductor package of claim 13 , wherein the first semiconductor chip is connected to the second semiconductor chip via the second redistribution substrate and the second connecting terminals.

15. a first sealing material disposed between the first redistribution substrate and the second redistribution substrate and sealing the first semiconductor chip; a second sealing material disposed on the second redistribution substrate and sealing the semiconductor device and the second semiconductor chip; 14. The semiconductor package of claim 13, wherein top surfaces of the semiconductor device and the second semiconductor chip are exposed from the second encapsulant.

16. the semiconductor device is an HBM package; 14. The semiconductor package of claim 13, wherein the first semiconductor chip and the second semiconductor chip are logic chips.

17. forming an upper redistribution substrate on a first carrier substrate; attaching a semiconductor device and a top semiconductor chip to a first surface of the upper rewiring substrate; attaching a bottom semiconductor chip to a second surface of the upper redistribution substrate opposite the first surface; forming a lower redistribution substrate on the bottom semiconductor chip; attaching a passive element and an external connection terminal to the lower redistribution substrate; The method for manufacturing a semiconductor package, wherein the bottom semiconductor chip has a through electrode.

18. Before attaching the bottom semiconductor chip, sealing the semiconductor device and the top semiconductor chip with an upper encapsulant; grinding the upper encapsulant to expose the semiconductor device and an upper surface of the top semiconductor chip; 18. The method of claim 17, further comprising: inverting the upper rewiring substrate, the semiconductor device, and the top semiconductor chip; attaching the upper surfaces of the semiconductor device and the top semiconductor chip to a second carrier substrate; and arranging the second surface of the upper rewiring substrate facing upward.

19. In the step of attaching the bottom semiconductor chip, 18. The method of claim 17, further comprising forming through posts on the second surface of the upper redistribution substrate except for a first portion where the bottom semiconductor chip is to be disposed, and then attaching the bottom semiconductor chip to the first portion.

20. the bottom semiconductor chip is attached to the second surface of the upper redistribution substrate via second connecting terminals; the bottom semiconductor chip is connected to the upper redistribution substrate via the second connecting terminals and the through electrodes; 18. The method of claim 17, wherein the bottom semiconductor chip is connected to the top semiconductor chip via the upper redistribution substrate and the second connecting terminals.

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