capacitor

Abstract

To provide a capacitor capable of suppressing breakdown of the capacitor.SOLUTION: An MIM capacitor includes a lower electrode, a dielectric film provided on the lower electrode, and an upper electrode provided on the dielectric film, an insulating film provided on the upper electrode so as to cover the MIM capacitor, an additional electrode provided within the insulating film above and spaced apart from the outer periphery of the upper electrode, the outer periphery of which is located outside the outer periphery of the upper electrode, the additional electrode being connected to the upper electrode, and an external electrode connected to the additional electrode, and the additional electrode has a connection region that is connected to the external electrode, and the connection region of the additional electrode is not connected to the upper electrode by the insulating film.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to capacitors, for example capacitors having MIM capacitors. [Background technology]

[0002] Metal-insulator-metal (MIM) capacitors are known, in which a lower electrode, a dielectric film, and an upper electrode are stacked on a substrate. MIM capacitors are integrated with active elements such as transistors on a semiconductor layer and used in MMICs (Monolithic Microwave Integrated Circuits). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2001-15693 Summary of the Invention [Problem to be solved by the invention]

[0004] However, when an MIM capacitor is subjected to a current test, the capacitor may be destroyed near the periphery of the upper electrode.

[0005] The present disclosure has been made in consideration of the above-mentioned problems, and aims to suppress breakdown of a capacitor. [Means for solving the problem]

[0006] One embodiment of the present disclosure is a capacitor comprising: a lower electrode, a dielectric film provided on the lower electrode, and an upper electrode provided on the dielectric film; an insulating film provided on the upper electrode so as to cover the MIM capacitor; an additional electrode provided within the insulating film above and spaced apart from the outer periphery of the upper electrode, the outer periphery of which is located outside the outer periphery of the upper electrode, the additional electrode connected to the upper electrode; and an external electrode connected to the additional electrode, wherein the additional electrode has a connection region that connects to the external electrode, and the connection region of the additional electrode is not connected to the upper electrode by the insulating film. [Effects of the Invention]

[0007] According to the present disclosure, it is possible to suppress breakdown of the capacitor. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view and a cross-sectional view of a capacitor in accordance with a first embodiment. [Figure 2A] FIG. 2A is a cross-sectional view showing the structure of the capacitor C1. [Figure 2B] FIG. 2B is a cross-sectional view showing the structure of the capacitor C2. [Figure 3A] FIG. 3A is a cross-sectional view showing the structure of the case B1. [Figure 3B] FIG. 3B is a cross-sectional view showing the structure of case B2. [Figure 4] FIG. 4 is a plan view and a cross-sectional view of a capacitor in accordance with a second embodiment. [Figure 5A] FIG. 5A is a cross-sectional view (part 1) illustrating a method for manufacturing a capacitor according to the second embodiment. [Figure 5B] FIG. 5B is a cross-sectional view (part 2) illustrating a method for manufacturing a capacitor according to the second embodiment. [Figure 5C] FIG. 5C is a cross-sectional view (part 3) illustrating a method for manufacturing a capacitor in accordance with the second embodiment. [Figure 6A] FIG. 6A is a cross-sectional view (part 4) illustrating a method for manufacturing a capacitor in accordance with the second embodiment. [Figure 6B] FIG. 6B is a cross-sectional view (part 5) illustrating the method for manufacturing the capacitor in accordance with the second embodiment. [Figure 7] FIG. 7 is a plan view and a cross-sectional view of a capacitor in accordance with a third embodiment. [Figure 8A] FIG. 8A is a cross-sectional view (part 1) illustrating a method for manufacturing a capacitor according to the third embodiment. [Figure 8B] FIG. 8B is a cross-sectional view (part 2) illustrating a method for manufacturing a capacitor according to the third embodiment. [Figure 8C] FIG. 8C is a cross-sectional view (part 3) illustrating a method for manufacturing a capacitor in accordance with the third embodiment. [Figure 9] FIG. 9 is a cross-sectional view of a capacitor according to a first modification of the third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] [Description of the embodiments of the present disclosure] First, the contents of the embodiments of the present disclosure will be listed and described. (1) One embodiment of the present disclosure is a capacitor including: a lower electrode, a dielectric film provided on the lower electrode, and an upper electrode provided on the dielectric film; an insulating film provided on the upper electrode so as to cover the MIM capacitor; an additional electrode provided within the insulating film above and spaced apart from an outer periphery of the upper electrode, the outer periphery of which is located outside the outer periphery of the upper electrode, the additional electrode connected to the upper electrode; and an external electrode connected to the additional electrode, wherein the additional electrode has a connection region that connects to the external electrode, and the connection region of the additional electrode is not connected to the upper electrode by the insulating film. As a result, the additional electrode shields an electric field, thereby preventing breakdown of the capacitor during an electrical test or the like. (2) It is preferable that the outer periphery of the additional electrode is located outside the outer periphery of the upper electrode over the entire outer periphery of the upper electrode. (3) It is preferable that the outer periphery of the additional electrode is positioned outward from the outer periphery of the upper electrode by at least the distance between the lower surface of the additional electrode and the lower surface of the upper electrode. (4) It is preferable that the outer periphery of the lower electrode is located outside the outer periphery of the upper electrode. (5) It is preferable that the lower surface of the additional electrode is located at a position at least twice the thickness of the dielectric film above the upper surface of the lower electrode. (6) It is preferable that the dielectric film is an inorganic insulator film, and the insulating film is an organic insulator film. (7) It is preferable that the additional electrode is joined to the upper electrode at the center. (8) The additional electrode preferably has an opening in a region where the insulating film is provided between the additional electrode and the upper surface of the upper electrode. (9) It is preferable that the external electrode is connected to a central region of the additional electrode.

[0010] [Details of the embodiments of the present disclosure] Specific examples of capacitors according to embodiments of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, but is defined by the claims, and is intended to include all modifications within the meaning and scope of the claims.

[0011] [Example 1] FIG. 1 shows a plan view and a cross-sectional view of a capacitor according to a first embodiment. The upper view of FIG. 1 is a plan view, and the lower view is an AA cross-sectional view of the upper view. The direction normal to the upper surface of a substrate 10 is the Z direction, and directions parallel to the upper surface of the substrate 10 are the X direction and the Y direction. As shown in FIG. 1, a semiconductor layer 11 is provided on the substrate 10. The semiconductor layer 11 is, for example, a GaN-based semiconductor layer or a GaAs-based semiconductor layer. When the semiconductor layer 11 is a GaN-based semiconductor layer, the substrate 10 is, for example, a SiC substrate, a sapphire substrate, a silicon substrate, or a GaN substrate, and the semiconductor layer 11 includes a layer made of GaN, AlN, InN, or a mixed crystal thereof. When the semiconductor layer 11 is a GaAs-based semiconductor layer, the substrate 10 is, for example, a GaAs substrate, and the semiconductor layer 11 includes a layer made of GaAs, AlAs, InAs, or a mixed crystal thereof. A transistor using the semiconductor layer 11 may be provided on the substrate 10, and the MIM capacitor 20 and the transistor may be integrated on the same substrate 10 to form an MMIC.

[0012] An insulating film 12 is provided on the semiconductor layer 11. The insulating film 12 is an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon nitride oxide film. The insulating film 12 has a thickness of, for example, 100 nm to 1200 nm. An MIM capacitor 20 is provided on the insulating film 12. The MIM capacitor 20 includes a lower electrode 14 provided on the insulating film 12, a dielectric film 16 provided on the lower electrode 14, and an upper electrode 18 provided on the dielectric film 16. In a parallel-plate MIM capacitor, the distance between the lower electrode 14 and the upper electrode 18 via the dielectric film 16 is approximately uniform within the manufacturing tolerance. The outer periphery 54 of the lower electrode 14 is located outside the outer periphery 50 of the upper electrode 18. The lower electrode 14 and the upper electrode 18 are, for example, metal films including an adhesive film and a low-resistance film provided on the adhesive film. The adhesive film is, for example, a Ti film, a WSi film, a TiW film, a TiWN film, or a TiN film. The low-resistance film is made of a material with a lower resistivity than the adhesive film, for example, an Au film. The thickness of the adhesive film is, for example, 3 nm to 300 nm. The adhesive film does not necessarily have to be provided. The thickness of the low resistance film is, for example, 50 nm to 400 nm. The dielectric film 16 is an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon nitride oxide film. The thickness of the dielectric film 16 is, for example, 50 nm to 400 nm.

[0013] An insulating film 24 is provided on the semiconductor layer 11 to cover the MIM capacitor 20. The insulating film 24 is, for example, an organic insulator film such as a polyimide film. The insulating film 24 has a thickness of, for example, 1 μm to 5 μm. An additional electrode 22 is provided within the insulating film 24. The additional electrode 22 is provided above the outer periphery 50 of the upper electrode 18 via the insulating film 24, and the outer periphery of the upper electrode 18 overlaps with the additional electrode 22. In other words, the outer periphery 52 of the additional electrode 22 is located outside the outer periphery 50 of the upper electrode 18. The additional electrode 22 is electrically connected to the upper electrode 18 via a connection portion 29. This causes the additional electrode 22 and the upper electrode 18 to have approximately the same potential. The additional electrode 22 includes an adhesive film such as a Ti film, a WSi film, a TiW film, a TiWN film, or a TiN film, and a low-resistance film such as an Au film provided on the adhesive film. The adhesive film has a thickness of, for example, 3 nm to 300 nm. The adhesive film may not be provided. The thickness of the low resistance film is, for example, 100 nm to 1.5 μm.

[0014] Let D1 be the distance between the outer periphery 52 of the additional electrode 22 and the outer periphery 50 of the upper electrode 18, D2 be the distance between the outer periphery 54 of the lower electrode 14 and the outer periphery 50 of the upper electrode 18, D3 be the distance between the top surface of the lower electrode 14 and the bottom surface of the additional electrode 22, D4 be the distance between the top surface of the upper electrode 18 and the bottom surface of the additional electrode 22, D5 be the width of the additional electrode 22, and D6 be the distance between the bottom surface of the additional electrode 22 and the bottom surface of the upper electrode 18. If the end faces of the upper electrode 18, the additional electrode 22, and the lower electrode 14 are inclined or curved, the outer peripheries 50, 52, and 54 are located at the outermost positions of the end faces.

[0015] When a voltage test is performed on an MIM capacitor that does not include the additional electrode 22, breakdown of the capacitor occurs primarily near the outer periphery of the upper electrode 18. Some capacitors have a short lifespan. A possible cause of breakdown in capacitors with a short lifespan is fine peeling between the upper electrode 18 and the insulating film 24 at the outer periphery 50 of the upper electrode 18. For example, if the top surface of the upper electrode 18 is made of Au and the insulating film 24 is an organic insulating film such as polyimide, the adhesion between the upper electrode 18 and the insulating film 24 is poor. This makes peeling more likely to occur at the interface between the upper electrode 18 and the insulating film 24. If the dielectric film 16 is a hard insulating film such as an inorganic insulating film and the insulating film 24 is a soft insulating film such as an organic insulating film, stress concentration at the outer periphery 50 of the upper electrode 18 makes peeling more likely to occur at the interface between the soft insulating film 24 and the upper electrode 18. Because the additional electrode 22 is located within the soft insulating film 24, stress is less likely to occur between the additional electrode 22 and the insulating film 24, making peeling less likely to occur.

[0016] When the peeled portion between the upper electrode 18 and the insulating film 24 becomes a gap, the dielectric constant of the gap is smaller than the dielectric constant of the insulating film 24, and therefore the capacitance of the gap becomes smaller than the capacitance of the insulating film 24. As a result, an electric field concentrates in the gap. If the electric field concentration becomes too great, partial discharge occurs between the upper electrode 18 and the lower electrode 14, which is thought to drastically shorten the life of the capacitor. Therefore, in Example 1, the additional electrode 22 is provided to prevent the electric field from concentrating on the periphery of the upper electrode 18.

[0017] [simulation] For capacitor C1 without additional electrode 22 and capacitor C2 with additional electrode 22, we simulated the magnitude of the electric field for Case B1, where no gap was formed between the insulating film 24 and the upper electrode 18, and Case B2, where a gap was formed. FIGS. 2A and 2B are cross-sectional views showing the structures of capacitors C1 and C2, respectively. As shown in FIGS. 2A and 2B, capacitors C1 and C2 have a dielectric film 16, an upper electrode 18, and an insulating film 24 on the lower electrode 14. The lower electrode 14, the dielectric film 16, and the insulating film 24 are sufficiently large in the X direction so as not to affect the electric field around the upper electrode 18 and additional electrode 22. For capacitor C2, an additional electrode 22 is provided within the insulating film 24. The lower electrode 14 is connected to ground, and a voltage V is applied to the upper electrode 18 and additional electrode 22. The boundary condition used was 0 V at infinity in the Z direction. Capacitor C1 corresponds to the comparative example, and capacitor C2 corresponds to Example 1.

[0018] The thicknesses of the dielectric film 16, the upper electrode 18, the additional electrode 22 and the insulating film 24 are T1, T2, T3 and T4, respectively. The simulation conditions are as follows: Lower electrode 14: perfect conductor Dielectric film 16: silicon nitride film, T1=400 nm Upper electrode 18: perfect conductor, T2=80 nm Additional electrode 22: perfect conductor, T3=400 nm, D1=1000 nm, D5=2000 nm, D6=800 nm Insulating film 24: Polyimide, T4=2000 nm, D3=1200 nm

[0019] 3A and 3B are cross-sectional views showing the structures of Cases B1 and B2, respectively. FIGS. 3A and 3B are enlarged views of the outer periphery 50 of the upper electrode 18. The additional electrode 22 is located outside the figure. As shown in FIG. 3A, in Case B1, the dielectric film 16, the upper electrode 18, and the insulating film 24 are in contact with each other. As shown in FIG. 3B, in Case B2, a gap 30 is provided between the dielectric film 16 and the insulating film 24 and between the upper electrode 18 and the insulating film 24. The thickness T5 of the gap 30 is 20 nm, and the thickness T5 is uniform. The electric field was simulated at points A to D. Point A is located within the dielectric film 16 below the upper electrode 18. Point B is located within the dielectric film 16 below the outer periphery 50 of the upper electrode 18. Point C is located on the -X side of the lower end of the upper electrode 18. Point D is located on the -X side of the upper end of the upper electrode 18. In Case B1, points C and D are located within the insulating film 24, while in Case B2, points C and D are located within the gap 30. The electric field strengths at points B to D were normalized by the electric field strength at point A.

[0020] Table 1 shows the normalized electric field strength at each location. [Table 1]

[0021] As shown in Table 1, in capacitor C1 without additional electrode 22, the electric field strength at points C and D in case B2 with film peeling is three times and seven times, respectively, the electric field strength at points C and D in case B1 without film peeling. Thus, without additional electrode 22, the electric field strength in gap 30 increases. In particular, the electric field strength near the top end of upper electrode 18 increases.

[0022] In capacitor C2 provided with additional electrode 22, the electric field intensity in case B1 is the same as that of capacitor C1 at all points A to D. The electric field intensity at points C and D in case B2 is lower than that of capacitor C1 in case B2. In particular, the electric field intensity at point D is approximately the same as that at point C. Thus, in capacitor C2 provided with additional electrode 22, electric field concentration is suppressed even when gap 30 is formed between insulating film 24 and upper electrode 18. This suppresses breakdown during electrical testing. The reason electric field concentration at point D is thought to be that, because outer periphery 52 of additional electrode 22 is located outside outer periphery 50 of upper electrode 18, additional electrode 22, which has the same potential as upper electrode 18, shields the electric field applied to upper electrode 18 from 0 V at infinity.

[0023] According to the first embodiment, the additional electrode 22 is provided above and spaced apart from the outer periphery 50 of the upper electrode 18 within the insulating film 24, and is electrically connected to the upper electrode 18. The outer periphery 52 of the additional electrode 22 is located outside the outer periphery 50 of the upper electrode 18. As a result, the additional electrode 22 shields the electric field, thereby suppressing breakdown of the capacitor during an electrical test or the like.

[0024] It is sufficient that the outer periphery 52 of the additional electrode 22 is located outside the outer periphery 50 of the upper electrode 18 in part of the outer periphery of the upper electrode 18, but it is preferable that the outer periphery 52 of the additional electrode 22 is located outside the outer periphery 50 of the upper electrode 18 in the entire outer periphery of the upper electrode 18. This can prevent the capacitor from being destroyed.

[0025] When shielding an electric field, a sufficient electric field shielding effect can be achieved if the angle between the line connecting the outer periphery 50 of the upper electrode 18 and the outer periphery 52 of the additional electrode 22 and the lower surface of the upper electrode 18 is 45° or less. From this perspective, the distance D1 between the outer periphery 52 of the additional electrode 22 and the outer periphery 50 of the upper electrode 18 is preferably equal to or greater than the distance D6 between the lower surface of the additional electrode 22 and the lower surface of the upper electrode 18. In other words, the outer periphery 52 of the additional electrode 22 is preferably positioned at least the distance D6 outward from the outer periphery 50 of the upper electrode 18. The distance D1 is more preferably equal to or greater than 1.5 times the distance D6, and even more preferably equal to or greater than 2 times the distance D6. If the distance D1 is too large, the capacitance between the additional electrode 22 and the lower electrode 14 becomes significant compared to the capacitance of the MIM capacitor 20 itself. Therefore, the distance D1 is preferably equal to or less than 10 times the distance D6.

[0026] If the distance D4 between the additional electrode 22 and the upper electrode 18 is too large, the effect of shielding the electric field will be reduced. Therefore, the distance D4 is preferably 10 times or less the thickness T1 of the dielectric film 16, and more preferably 5 times or less the thickness T1.

[0027] The outer periphery 54 of the lower electrode 14 is located outside the outer periphery 50 of the upper electrode 18. This makes it possible to shield the electric field from the substrate 10 side, thereby suppressing breakdown of the capacitor. It is sufficient that the outer periphery 54 of the lower electrode 14 is located outside the outer periphery 50 of the upper electrode 18 in part of the outer periphery of the upper electrode 18, but it is preferable that the outer periphery 54 of the lower electrode 14 is located outside the outer periphery 50 of the upper electrode 18 in the entirety of the outer periphery 50 of the upper electrode 18. This makes it possible to suppress breakdown of the capacitor.

[0028] The distance D2 between the outer periphery 54 of the lower electrode 14 and the outer periphery 50 of the upper electrode 18 is preferably at least half the thickness T1 of the dielectric film 16, more preferably at least the thickness T1, and even more preferably at least twice the thickness T1. This allows for better shielding of the electric field. If the distance D2 is too large, the capacitance between the additional electrode 22 and the lower electrode 14 becomes significant compared to the capacitance of the MIM capacitor 20 itself. Therefore, the distance D2 is preferably no more than 10 times the thickness T1.

[0029] If the distance D3 between the additional electrode 22 and the lower electrode 14 is too small, the capacitance between the additional electrode 22 and the lower electrode 14 becomes significant relative to the capacitance of the MIM capacitor 20 itself. Therefore, the distance D3 is preferably at least twice the thickness T1. That is, the lower surface of the additional electrode 22 is preferably positioned at a height above the upper surface of the lower electrode 14 that is at least twice the thickness T1 of the dielectric film 16. The distance D3 is more preferably at least three times the thickness T1, and even more preferably at least four times the thickness T1. To shield the electric field, the distance D3 is preferably no more than 10 times the thickness T1.

[0030] When the dielectric film 16 is an inorganic insulator film and the insulating film 24 is an organic insulator film, the insulating film 24 is softer than the dielectric film 16, and therefore the insulating film 24 is likely to peel off from the upper electrode 18 above the outer periphery 50 of the upper electrode 18. Therefore, it is preferable to provide the additional electrode 22.

[0031] The MIM capacitor 20 is provided on the semiconductor layer 11. This allows the MIM capacitor 20 and active elements such as transistors formed on the semiconductor layer 11 to be integrated on the same substrate 10.

[0032] [Example 2] FIG. 4 shows a plan view and a cross-sectional view of a capacitor according to Example 2. The upper view of FIG. 4 is a plan view, and the lower view is a cross-sectional view taken along the line AA of the upper view. As shown in FIG. 4, an insulating film 13 is provided on a semiconductor layer 11, and an insulating film 12 is provided on the insulating film 13. The additional electrode 22 has an outer periphery 22a and a connecting portion 22b. The outer periphery 22a is provided so as to overlap with the outer periphery 50 of the upper electrode 18. The connecting portion 22b connects the outer periphery 22a to the upper electrode 18. A central portion 22c of the connecting portion 22b contacts the upper electrode 18. As a result, the outer periphery 22a is electrically connected to the upper electrode 18, and the outer periphery 22a and the upper electrode 18 are at approximately the same potential. A through-hole 25a is provided through the insulating film 24, and a wiring 26a is electrically connected to the upper electrode 18 via the through-hole 25a. A through-hole 25b is provided through the insulating film 24 and the dielectric film 16, and the wiring 26b is electrically connected to the lower electrode 14 via the through-hole 25b. The wirings 26a and 26b electrically connect the MIM capacitor 20 to other elements or pads, etc. The other configurations are the same as those in the first embodiment, and therefore the description thereof will be omitted.

[0033] The substrate 10 is, for example, a SiC substrate. The semiconductor layer 11 includes, for example, a GaN channel layer and an AlGaN barrier layer. The insulating films 13 and 12 are, for example, a silicon nitride film and a silicon oxide film, respectively. The lower electrode 14 is, for example, a Ti film and an Au film on the Ti film. The dielectric film 16 is, for example, a silicon nitride film. The upper electrode 18 is, for example, a Ti film and an Au film on the Ti film. The additional electrode 22 is, for example, a Ti film and an Au film on the Ti film. The insulating film 24 is, for example, a polyimide film. The wirings 26a and 26b are, for example, a TiW film and an Au film on the TiW film.

[0034] 5A to 6B are cross-sectional views showing a method for manufacturing a capacitor according to a second embodiment. As shown in FIG. 5A, insulating films 13 and 12 are formed on a substrate 10 having a semiconductor layer 11 formed on its upper surface. The insulating films 13 and 12 are formed, for example, by chemical vapor deposition (CVD). When the insulating film 13 is a silicon nitride film, the insulating film 13 is formed by plasma CVD. When the insulating film 12 is a silicon oxide film, the insulating film 12 is formed by atmospheric pressure CVD. A lower electrode 14 is formed on the insulating film 12. The lower electrode 14 is formed by sputtering and etching, for example. The lower electrode 14 may also be formed by vacuum deposition and lift-off. A dielectric film 16 is formed on the insulating film 12 and the lower electrode 14 by CVD, for example. When the dielectric film 16 is a silicon nitride film, the dielectric film 16 is formed by plasma CVD. An upper electrode 18 is formed on the dielectric film 16. The upper electrode 18 is formed by vacuum deposition and lift-off, for example. The upper electrode 18 may also be formed by sputtering and etching. The dielectric film 16 and the insulating film 12 are patterned into a desired shape using an etching method.

[0035] As shown in FIG. 5B, an insulating film 24a is formed on the substrate 10 so as to cover the MIM capacitor 20. When the insulating film 24a is an organic insulator such as polyimide, the insulating film 24a is formed by, for example, a coating method. Through-holes 25c and 25d are formed through the insulating film 24a by, for example, an etching method. The through-hole 25c is formed on the upper electrode 18, and the through-hole 25d is formed on the lower electrode 14 outside the MIM capacitor 20.

[0036] As shown in FIG. 5C, additional electrode 22 and wiring layer 23 are formed on insulating film 24a and in through holes 25c and 25d, respectively. Additional electrode 22 and wiring layer 23 are formed using, for example, sputtering and etching, vacuum deposition and lift-off, or plating. When additional electrode 22 is formed using plating, a seed layer is formed using, for example, sputtering or vacuum deposition, and a mask layer is formed on the seed layer. A plating layer is formed on the seed layer using the mask layer as a mask. The seed layer is etched using the plating layer as a mask.

[0037] 6A, an insulating film 24b is formed on the insulating film 24a so as to cover the additional electrode 22 and the wiring layer 23. When the insulating film 24b is an organic insulator such as polyimide, the insulating film 24b is formed by, for example, a coating method. Through holes 25a and 25e are formed through the insulating film 24b by, for example, an etching method. The through hole 25a is formed on the additional electrode 22, and the through hole 25e is formed on the wiring layer 23.

[0038] As shown in FIG. 6B, wirings 26a and 26b are formed on insulating film 24b and in through holes 25a and 25e. Wirings 26a and 26b are formed by, for example, sputtering, vacuum deposition, or plating. For example, a seed layer may be formed by sputtering or vacuum deposition, and wirings 26a and 26b may be formed on the seed layer by plating. As shown in FIG. 4, wiring 26b may be in direct contact with lower electrode 14, or as shown in FIG. 6B, wiring 26b may be connected to lower electrode 14 via wiring layer 23. In this manner, the capacitor according to Example 2 is manufactured.

[0039] In the second embodiment, the additional electrode 22 is joined to the upper electrode 18 at the central portion 22c. This allows the outer peripheral portion 22a to be spaced upward from the upper electrode 18, shielding the electric field, and the outer peripheral portion 22a and the upper electrode 18 to be electrically connected by the connecting portion 22b.

[0040] [Example 3] FIG. 7 shows a plan view and a cross-sectional view of a capacitor according to Example 3. The upper view of FIG. 7 is a plan view, and the lower view is a cross-sectional view taken along line AA of the upper view. As shown in FIG. 7, an opening 27 is provided in the connection portion 22b of the additional electrode 22. The other configurations are the same as those of Example 2, and therefore a description thereof will be omitted.

[0041] 8A to 8C are cross-sectional views showing a method for manufacturing a capacitor according to the third embodiment. As shown in FIG. 8A, after FIG. 5A of the second embodiment, a mask layer 34 having an opening 35 is formed to cover the MIM capacitor 20. The opening 35 is formed on the upper electrode 18. The mask layer 34 is, for example, a photoresist, and is formed by coating, exposing, and developing. An additional electrode 22 having an opening 27 is formed on the mask layer 34. The method for forming the additional electrode 22 is the same as that shown in FIG. 5C of the second embodiment.

[0042] 8B, the mask layer 34 is removed. If the mask layer 34 is a photoresist, the mask layer 34 is removed using, for example, an organic solvent. At this time, the organic solvent is supplied to the mask layer 34 between the additional electrode 22 and the upper electrode 18 through the opening 27. This allows the mask layer 34 to be removed without any mask layer 34 remaining between the additional electrode 22 and the upper electrode 18.

[0043] As shown in FIG. 8C, an insulating film 24 is formed to cover the MIM capacitor 20 and the additional electrode 22. When a solution containing an organic insulator is applied as the insulating film 24, the solution containing the organic insulator is supplied between the additional electrode 22 and the upper electrode 18 through the opening 27. This allows the insulating film 24 to be formed between the additional electrode 22 and the upper electrode 18. The opening 27 is filled with the insulating film 24. Through holes 25a and 25b are then formed in the insulating film 24. Thereafter, wirings 26a and 26b are formed in the same manner as in FIG. 6B of Example 2. In this manner, the capacitor according to Example 3 is manufactured.

[0044] According to the third embodiment, the additional electrode 22 has an opening 27 in a region where the insulating film 24 is provided between the additional electrode 22 and the upper electrode 18. This makes it possible to remove the mask layer 34 between the additional electrode 22 and the upper electrode 18 and form the insulating film 24. It is preferable that the opening 27 does not overlap with the outer periphery 50 of the upper electrode 18, and it is preferable that the distance between the outer periphery 50 of the upper electrode 18 and the opening 27 is equal to or greater than the distance between the lower surface of the additional electrode 22 and the lower surface of the upper electrode 18. This makes it possible to prevent the electric field from extending to the outer periphery 50 of the upper electrode 18 via the opening 27.

[0045] [Modification 1 of Example 3] FIG. 9 is a cross-sectional view of a capacitor according to a first modification of the third embodiment. As shown in FIG. 9, the additional electrode 22 is curved so that the distance between the lower surface of the additional electrode 22 and the upper surface of the upper electrode 18 becomes shorter toward the central portion 22c. The other configurations are the same as those of the third embodiment, and therefore a description thereof will be omitted. In the third embodiment, as shown in FIG. 8A, the side surface of the opening 35 in the mask layer 34 is vertical, which results in poor coverage of the additional electrode 22, and the additional electrode 22 may become thin near the side surface of the opening 35. In the first modification of the third embodiment, the side surface of the opening 35 is smoothly curved, which allows the thickness of the additional electrode 22 to be more uniform.

[0046] The embodiments disclosed herein should be considered to be illustrative and not restrictive in all respects. The scope of the present disclosure is defined by the claims, not by the meaning described above, and is intended to include all modifications within the meaning and scope equivalent to the claims. [Explanation of symbols]

[0047] 10 Substrate 11 Semiconductor layer 12, 13, 24, 24a, 24b insulating film 14 Lower electrode 16 Dielectric film 18 Upper electrode 20 MIM capacitors 22 Additional electrode 22a Outer periphery 22b, 29 Connection 22c central part 23 Wiring layer 25a~25e Through hole 26a, 26b wiring 27, 35 aperture 30 void 34 Mask Layer 50, 52, 54 perimeter

Claims

1. an MIM capacitor including a lower electrode, a dielectric film provided on the lower electrode, and an upper electrode provided on the dielectric film; an insulating film provided on the upper electrode so as to cover the MIM capacitor; an additional electrode provided in the insulating film above and spaced from the outer periphery of the upper electrode, the outer periphery of which is located outside the outer periphery of the upper electrode, and the additional electrode connected to the upper electrode; an external electrode connected to the additional electrode, the additional electrode has a connection region that connects to the external electrode; A capacitor, wherein the connection region of the additional electrode does not interpose the insulating film between the additional electrode and the upper electrode.

2. 2. The capacitor according to claim 1, wherein the outer periphery of the additional electrode is located outside the outer periphery of the upper electrode at all of the outer peripheries of the upper electrode.

3. 3. The capacitor according to claim 1, wherein the outer periphery of the additional electrode is positioned outward from the outer periphery of the upper electrode by at least the distance between the lower surface of the additional electrode and the lower surface of the upper electrode.

4. 4. The capacitor according to claim 1, wherein the outer periphery of the lower electrode is positioned outside the outer periphery of the upper electrode.

5. 5. The capacitor according to claim 4, wherein the lower surface of the additional electrode is located above the upper surface of the lower electrode by at least twice the thickness of the dielectric film.

6. 6. The capacitor according to claim 1, wherein the dielectric film is an inorganic insulator film, and the insulating film is an organic insulator film.

7. 7. The capacitor according to claim 1, wherein the additional electrode is joined to the upper electrode at a central portion thereof.

8. 8. The capacitor according to claim 1, wherein the additional electrode has an opening in a region where the insulating film is provided between the additional electrode and an upper surface of the upper electrode.

9. 9. The capacitor according to claim 1, wherein the external electrode is connected to a central region of the additional electrode.

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