Semiconductor device

Abstract

To provide a semiconductor device comprising a transistor having stable electrical characteristics.SOLUTION: An electrode has a metal containing nitrogen, a first conductor, a second conductor and an insulator, the insulator has an opening that penetrates the insulator and reaches the second conductor, the side surface of the opening and the bottom surface of the opening have areas in contact with the metal, the first conductor has areas in contact with the sides of the opening and the bottom of the aperture through the metal, and the electrical resistivity of the metal in contact with the bottom of the aperture is lower than the electrical resistivity of the metal in contact with the sides of the opening.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to, for example, a transistor and a semiconductor device. The present invention also relates to a method for manufacturing a semiconductor device, a display device, a semiconductor device, and a semiconductor device. The present invention relates to a device, a light-emitting device, a lighting device, a power storage device, a storage device, a processor, and an electronic device. The present invention relates to a method for manufacturing a display device, a liquid crystal display device, a light emitting device, a storage device, and an electronic device. The present invention relates to a display device, a liquid crystal display device, a light-emitting device, a storage device, and a method for driving electronic equipment.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect relates to an article, a method, or a manufacturing method. One aspect of the present invention is a process, machine, manufacture, or composition. It is about the (object of matter).

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to a general category of devices, including display devices, light-emitting devices, lighting devices, electro-optical devices, semiconductor circuits, and electronic devices. may have semiconductor devices. [Background technology]

[0004] In recent years, the development of transistors using oxide semiconductors (typically In-Ga-Zn oxide) has Oxide semiconductors have a long history, dating back to 1990. In 1988, the use of crystalline In-Ga-Zn oxide in semiconductor devices was disclosed. (See Patent Document 1.) In 1995, a transistor using an oxide semiconductor was developed. It has been revealed that the material is a silicon dioxide, and its electrical properties are disclosed (see Patent Document 2).

[0005] Furthermore, we have developed a transistor that uses silicon (Si) as the semiconductor layer and a transistor that uses oxide semiconductor as the semiconductor layer. A semiconductor device that combines a transistor used in the above with a semiconductor device has been attracting attention (see Patent Document 3). ). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Patent Publication No. 63-239117 [Patent Document 2] Special table 11-505377 [Patent Document 3] Patent Publication No. 2011-119674 Summary of the Invention [Problem to be solved by the invention]

[0007] One object of the present invention is to provide a semiconductor device having a transistor with stable electrical characteristics. Alternatively, a semiconductor device having a transistor with a small leakage current when off is provided. Another object of the present invention is to provide a transistor having normally-off electrical characteristics. Another object of the present invention is to provide a semiconductor device that can provide a highly reliable transistor. It is an object of the present invention to provide a semiconductor device having a

[0008] Another object is to provide a module including the semiconductor device. It is an object of the present invention to provide a semiconductor device or an electronic device having the module. Another object is to provide a novel semiconductor device. One of the objectives is to provide a novel electronic device. do.

[0009] The description of these problems does not preclude the existence of other problems. It is not necessary for the present invention to solve all of these problems. The above will be made clear from the description, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0010] (1) One embodiment of the present invention provides a semiconductor device including a nitrogen-containing metal, a first conductor, a second conductor, an insulator, and an insulator having an opening extending through the insulator to the second conductor; The side surface and the bottom surface of the opening have an area in contact with the metal, and the first The conductor has an area contacting the side surface and the bottom surface of the opening via the metal. the electrical resistivity of the metal in contact with the bottom surface of the opening is greater than that of the metal before contacting the side surface of the opening. The electrode is characterized by having an electrical resistivity lower than that of the metal.

[0011] (2) One aspect of the present invention is the method according to (1), characterized in that the metal contains tantalum and oxygen. It is an electrode.

[0012] (3) In one aspect of the present invention, the first conductor contains copper or tungsten. ) or (2).

[0013] (4) One aspect of the present invention is characterized in that the insulator contains aluminum and oxygen. The electrode according to any one of (1) to (3).

[0014] (5) One embodiment of the present invention is a semiconductor device including an electrode, a first transistor, and a second transistor. The transistor has a gate electrode, and the second transistor has a drain electrode and a gate The source electrode is electrically connected to the drain electrode via an electrode, and the electrode is one of (1) to (4). The semiconductor device is characterized by the electrode according to any one of the above.

[0015] (6) One aspect of the present invention is the electrode according to any one of (1) to (4) and the semiconductor according to (5). The module includes a device and a printed circuit board.

[0016] (7) One aspect of the present invention is the electrode according to any one of (1) to (4) and the semiconductor according to (5). (6) A device characterized by having the module described in (6) and a speaker or an operation key. It is an electronic device.

[0017] (8) One embodiment of the present invention is a method for manufacturing a semiconductor device using a plurality of electrodes according to any one of (1) to (4) or (5). ) A semiconductor wafer having a plurality of semiconductor devices according to the present invention and having a dicing region. .

[0018] (9) In one embodiment of the present invention, a first insulator is formed on a first conductor, and a second insulator is formed on the first insulator. A dielectric is deposited, a third insulator is deposited on the second insulator, and a hard mask is deposited on the third insulator. The hard mask is used as an etching mask to form the first insulator, the second insulator, and By etching a part of the third insulator, the first insulator, the second insulator and the third insulator are removed. An opening is formed through the insulator to reach the top surface of the first conductor, and the side and bottom surfaces of the opening are covered. A metal film containing nitrogen is formed so as to fill the opening, and a plasma treatment is performed. A second conductive material is deposited on the metal containing nitrogen, and a hard mask, a metal containing nitrogen, and a second conductive material are deposited on the metal containing nitrogen. The body is subjected to a polishing process to remove the hard mask and expose the nitrogen-containing metal, the second conductor, and The height of the top surface of the third insulator is made to be approximately the same, and the electrical resistance of the nitrogen-containing metal in contact with the bottom surface of the opening is The resistivity is lower than the electrical resistivity of the nitrogen-containing metal adjacent to the side of the opening. A method for producing an electrode.

[0019] (10) One aspect of the present invention is characterized in that the gas used in the plasma treatment contains argon (9 ) is a method for producing an electrode described in

[0020] (11) One embodiment of the present invention is a method for manufacturing a semiconductor device, the semiconductor device including: an electrode; a first transistor; a first transistor having a gate electrode and a second transistor; The second transistor has a drain electrode, and a gate electrode is connected to the drain electrode via an electrode. The method for producing an electrode according to any one of (9) and (10) above, wherein the electrodes are electrically connected. The semiconductor device is characterized by being manufactured using the above.

[0021] (12) One aspect of the present invention is a method for manufacturing a module, the module being (9) or (10) (11) An electrode produced by the method for producing an electrode according to any one of (1) to (10). The present invention is characterized by having a semiconductor device and a printed circuit board manufactured using the semiconductor device manufacturing method. This is a method for manufacturing a module that features

[0022] (13) One embodiment of the present invention is a method for manufacturing an electronic device, the electronic device comprising: A capacitor element manufactured by using the method for manufacturing an electrode according to any one of (1) and (11). A semiconductor device manufactured using the method for manufacturing a semiconductor device, and a method for manufacturing a module according to (12). The module is characterized by having a speaker or an operation key. This is a method for manufacturing an electronic device. [Effects of the Invention]

[0023] A semiconductor device including a transistor with stable electrical characteristics can be provided. Alternatively, it is possible to provide a semiconductor device having a transistor with a small leakage current when it is not conducting. Alternatively, a semiconductor device including a transistor having normally-off electrical characteristics can be provided. Alternatively, a semiconductor device having a highly reliable transistor can be provided. It is possible.

[0024] Alternatively, a module having the semiconductor device can be provided. Alternatively, a novel semiconductor device or an electronic device having the module can be provided. A new module can be provided. Alternatively, a novel electronic device can be provided.

[0025] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these may be included in the description, This becomes clear from the description, drawings, claims, etc. From any description, it is possible to extract effects other than these. [Brief explanation of the drawings]

[0026] [Figure 1] 1A and 1B are a cross-sectional view and a top view illustrating a structure of a semiconductor device according to one embodiment of the present invention. [Figure 2] 1A and 1B are a cross-sectional view and a top view illustrating a structure of a semiconductor device according to one embodiment of the present invention. [Figure 3] FIG. 1 is a cross-sectional view illustrating a structure of a semiconductor device according to one embodiment of the present invention. [Figure 4] FIG. 1 is a cross-sectional view illustrating a structure of a semiconductor device according to one embodiment of the present invention. [Figure 5] 1A and 1B are cross-sectional views and a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 6] 1A and 1B are cross-sectional views and a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 7] 1A and 1B are cross-sectional views and a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 8] 1A and 1B are cross-sectional views and a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 9] 1A and 1B are cross-sectional views and a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 10] 1A and 1B are cross-sectional views and a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 11] 1A and 1B are cross-sectional views and a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 12] 1A and 1B are a cross-sectional view and a top view illustrating a structure of a transistor according to one embodiment of the present invention. [Figure 13] 1A and 1B are a cross-sectional view and a top view illustrating a structure of a transistor according to one embodiment of the present invention. [Figure 14] FIG. 1 is a diagram illustrating the range of atomic ratios of oxide semiconductors according to the present invention. [Figure 15] A diagram explaining the InMZnO4 crystal. [Figure 16] FIG. 1 is a band diagram of a stacked structure of oxide semiconductors. [Figure 17] FIG. 1 is a cross-sectional view illustrating a structure of a capacitor according to one embodiment of the present invention. [Figure 18] FIG. 1 is a cross-sectional view illustrating a structure of a transistor according to one embodiment of the present invention. [Figure 19] FIG. 1 is a cross-sectional view illustrating a structure of a semiconductor device according to one embodiment of the present invention. [Figure 20] FIG. 1 is a cross-sectional view illustrating a structure of a semiconductor device according to one embodiment of the present invention. [Figure 21] 1A to 1C are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 22] 1A to 1C are cross-sectional views illustrating a method for manufacturing a transistor according to one embodiment of the present invention. [Figure 23] FIG. 1 is a cross-sectional view illustrating a structure of a semiconductor device according to one embodiment of the present invention. [Figure 24] 1A and 1B are diagrams illustrating structural analysis of a CAAC-OS and a single-crystal oxide semiconductor by XRD, and a selected-area electron diffraction pattern of a CAAC-OS. [Figure 25] Cross-sectional TEM image of CAAC-OS, as well as planar TEM image and its image analysis. [Figure 26] Electron diffraction pattern of nc-OS and cross-sectional TEM image of nc-OS. [Figure 27] Cross-sectional TEM image of a-like OS. [Figure 28] FIG. 1 shows the change in the crystalline part of an In-Ga-Zn oxide due to electron irradiation. [Figure 29] FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 30] FIG. 1 is a circuit diagram illustrating a memory device according to one embodiment of the present invention. [Figure 31] FIG. 1 is a circuit diagram illustrating a memory device according to one embodiment of the present invention. [Figure 32] 1A and 1B are a circuit diagram and a timing chart illustrating one embodiment of the present invention. [Figure 33]1A and 1B are graphs and circuit diagrams illustrating one embodiment of the present invention. [Figure 34] 1A and 1B are a circuit diagram and a timing chart illustrating one embodiment of the present invention. [Figure 35] 1A and 1B are a circuit diagram and a timing chart illustrating one embodiment of the present invention. [Figure 36] 1A to 1C are a block diagram, a circuit diagram, and waveform diagrams illustrating one embodiment of the present invention. [Figure 37] 1A and 1B are a circuit diagram and a timing chart illustrating one embodiment of the present invention. [Figure 38] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 39] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 40] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 41] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 42] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 43] FIG. 1 is a block diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 44] FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 45] FIG. 1 is a top view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 46] FIG. 1 is a block diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 47] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 48] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 49] FIG. 10 is a perspective view illustrating an electronic device according to one embodiment of the present invention. [Figure 50] FIG. 10 is a diagram showing the amount of film loss of tantalum nitride according to an example. [Figure 51] FIG. 10 is a diagram showing the measurement results of sheet resistance according to an example. [Figure 52] FIG. 10 is a diagram showing the results of XPS analysis according to an example. [Figure 53] FIG. 1 shows the results of XPS analysis according to an example. [Figure 54] FIG. 1 is a top view of a semiconductor wafer according to one embodiment of the present invention. [Figure 55] 1A and 1B are a flowchart and a schematic perspective view illustrating an example of a manufacturing process for an electronic component. DETAILED DESCRIPTION OF THE INVENTION

[0027] The embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the above, and various modifications in form and details can be easily made by those skilled in the art. It is understood that the present invention should not be construed as being limited to the description of the following embodiments. In explaining the configuration of the invention using the drawings, the same symbols are used in different The hatch pattern is used in common between drawings. However, there are cases where no particular symbol is attached.

[0028] The configurations shown in the following embodiments may be applied or combined as appropriate with other configurations shown in the embodiments. The above-mentioned embodiments can be combined or substituted to form one embodiment of the present invention.

[0029] In the drawings, the size, thickness of the film (layer), or area is exaggerated for clarity. There may be cases where this is the case.

[0030] In this specification, the terms "film" and "layer" are interchangeable. It is possible to do this.

[0031] Also, voltage is a voltage between a certain potential and a reference potential (for example, ground potential (GND) or source potential). Therefore, voltage can be replaced with potential. Generally, potential (voltage) is relative and is expressed in terms of its magnitude relative to a reference potential. Therefore, even if it is described as "ground potential," For example, the lowest potential in a circuit may be the "ground potential." Or, the intermediate potential in the circuit may be the "ground potential." With respect to the potential, a positive potential and a negative potential are defined.

[0032] The ordinal numbers such as 1st and 2nd are used for convenience and do not represent the order of processes or stacking. Therefore, for example, "the first" should not be replaced with "the second" or "the third" In addition, ordinal numbers described in this specification and the like can be replaced with other numbers as appropriate. and the ordinal numbers used to identify an aspect of the present invention may not match.

[0033] Even when written as "semiconductor," if the conductivity is sufficiently low, it may be written as "insulator." In addition, the boundary between "semiconductor" and "insulator" is vague, and Therefore, the term "semiconductor" as used herein may be used interchangeably with "insulator." Similarly, the term "insulator" used herein can be interpreted as "semiconductor." " can sometimes be rephrased as ".

[0034] Also, even if a material is written as a "semiconductor," if the material has a sufficiently high conductivity, it may be written as a "conductor." In addition, the boundary between "semiconductor" and "conductor" is vague, and Therefore, the term "semiconductor" as used herein may be used interchangeably with "conductor." Similarly, the term "conductor" used in this specification can be used to refer to a "semiconductor." " can sometimes be rephrased as ".

[0035] The impurities in a semiconductor refer to, for example, substances other than the main components that make up the semiconductor. For example, the concentration Elements with a concentration of less than 0.1 atomic percent are considered impurities. The formation of DOS (Density of States) in the body and carrier migration The semiconductor may be an oxide semiconductor, and the crystallinity may decrease. In the case of a conductor, impurities that change the properties of the semiconductor include, for example, elements of Group 1, Group elements, 13th group elements, 14th group elements, 15th group elements, and transition metals other than the main component. In particular, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, In the case of oxide semiconductors, impurities such as hydrogen can cause In addition, when the semiconductor is a silicon layer, the characteristics of the semiconductor Impurities that change the properties include, for example, oxygen, elements of Group 1 except for hydrogen, elements of Group 2, and elements of Group 3. These include the Group 13 elements and Group 15 elements.

[0036] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. When the transistor is in the on state, the gate electrode overlaps with the semiconductor (the part where current flows). The source (source region or source voltage) in the region where the The distance between the source and drain (drain region or drain electrode) is In a transistor, the channel length does not necessarily have the same value in all regions. The channel length of each transistor may not be determined to a single value. In the document, the channel length is any one value, maximum value, The minimum or average value.

[0037] The channel width is, for example, the width of the semiconductor (or transistor) in a top view of the transistor. The area where the gate electrode overlaps with the semiconductor (the part of the semiconductor where current flows when the semiconductor is on). Or, in the region where the channel is formed, the channel length direction is the reference. The channel width is the length of the entire region in one transistor. In other words, the channel width of a transistor does not necessarily have the same value in the Therefore, in this specification, the channel width is the width of the channel formed. It can be any one value, maximum value, minimum value or average value in the area.

[0038] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may be The effective channel width (hereinafter referred to as the effective channel width) and the The channel width (hereinafter referred to as apparent channel width) may differ from the actual channel width. For example, In a transistor having a three-dimensional structure, the effective channel width is The apparent channel width becomes larger than that shown in For example, in transistors with a fine, three-dimensional structure, In some cases, the proportion of the channel region formed may be large. The effective channel width of the channel that is actually formed is larger than the apparent channel width that is The larger the

[0039] In the case of a transistor having a three-dimensional structure, the effective channel width is measured. For example, it may be difficult to estimate the effective channel width from the design value. In order to obtain this, it is necessary to assume that the shape of the semiconductor is known. If is not known accurately, it is difficult to accurately measure the effective channel width.

[0040] Therefore, in this specification, the apparent channel width is referred to as the "surrounding channel width (SCW)". In addition, in this specification, So, when we simply write "channel width," it means the enclosed channel width or the apparent channel width. In this specification, when simply referred to as a channel width, it may refer to the actual It may refer to the effective channel width. The width, apparent channel width, and enclosed channel width were determined by taking cross-sectional TEM images. The value can be determined, such as by analyzing the image.

[0041] The field effect mobility of the transistor and the current value per channel width are calculated. In this case, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0042] In this specification and the like, silicon oxynitride refers to a material having a composition containing more oxygen than nitrogen. The content is high, and preferably the oxygen content is 55 atomic % or more and 65 atomic % or less, and the nitrogen content is 1 % or more and 20 atomic % or less, silicon is 25 atomic % or more and 35 atomic % or less, hydrogen is 0.1 atomic % or more Silicon oxide nitride is a material containing silicon dioxide at a concentration of 10 atomic percent or more. The composition of the material is such that the nitrogen content is higher than the oxygen content, and preferably the nitrogen content is 55%. atomic % or more and 65 atomic % or less, oxygen is 1 atomic % or more and 20 atomic % or less, silicon is 25 atomic % and hydrogen in the concentration range of 0.1 atomic % to 10 atomic %. This refers to

[0043] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case of -5° or more and 5° or less. "Line" refers to the state in which two straight lines are arranged at an angle between -30° and 30°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case where the angle is between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0044] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is expressed as a hexagonal crystal system. .

[0045] (Embodiment 1) In this embodiment, a manufacturing method of a semiconductor device according to one embodiment of the present invention will be described with reference to drawings. Reveal.

[0046] <Plug making method 1> The following describes the configuration of a plug and its creation as part of the configuration of a semiconductor device according to one aspect of the present invention. The manufacturing method will be explained using the cross-sectional views and top views shown in Figs. 1, 5 and 6. A), Fig. 5(A), Fig. 5(C), Fig. 6(A) and Fig. 6(C) are Fig. 1(B), Fig. 5(B ), which corresponds to the dashed line X1-X2 in the top view shown in Figures 5(D), 6(B) and 6(D). 1 shows a cross-sectional view of the same.

[0047] 1(A) and (B) are drawings of the completed plug, and in FIGS. 5 and 6, the conductor 12 (hereinafter referred to as , may be called a conductive film or wiring, etc.), and the insulator 13a, the insulator 14a and the insulating The nitrogen-containing metal 20a and the conductor 2 are embedded in the opening 17 formed in the insulator 15a. The process of connecting 1a and 1b is described. Here, the opening 17 is a via hole or the like. The metal 20a and the conductor 21a having nitrogen are embedded in the opening 17. At the bottom of the opening 17, the nitrogen-containing metal 20a and the conductor 12 The metal 20a containing nitrogen in the region where the metal 20a contacts the metal 20a has a region with low resistance. The region where the metal 20a having nitrogen therein has a low resistance is indicated by a dotted line.

[0048] First, a conductor 12 is formed on a substrate. The conductor 12 may have a single layer structure or a multilayer structure. It should be noted that the substrate is not shown in Fig. 1(A), Fig. 6 and Fig. 6. Alternatively, another conductor, insulator, or semiconductor may be provided between the substrate and the conductor 12. good.

[0049] The conductor 12 is formed by the same method as that for the nitrogen-containing metal 20 and the conductor 21, which will be described later. Just use

[0050] Next, an insulator 13 is formed on the conductor 12. The insulator 13 may have a single layer structure. The insulator 13 may be formed by a sputtering method, a chemical vapor deposition (CVD) method, or the like. D: Chemical Vapor Deposition) method, molecular beam epitaxy ( MBE: Molecular Beam Epitaxy, Pulsed Laser Deposition (PL D: Pulsed Laser Deposition (PLD) or Atomic Layer Deposition (ALD) This can be done using the atomic layer deposition (ALD) method. .

[0051] The CVD method is a plasma CVD (PECVD) method that uses plasma. enhanced CVD method, thermal CVD (TCVD) D) method, and photo-CVD (Photo CVD) method, which uses light. Depending on the source gas, metal CVD (MCVD) and metal organic CVD ( MOCVD (Metal Organic CVD) method.

[0052] Next, the insulator 14 is formed on the insulator 13. The insulator 14 may have a single layer structure. The insulator 14 may be formed by a sputtering method, a CVD method, an MBE method, or the like. , PLD method, ALD method, or the like can be used.

[0053] The insulator 14 is preferably made of a material that is less permeable to hydrogen and water than the insulator 13. The insulator 14 may be, for example, aluminum oxide, aluminum oxynitride, or gallium oxide. gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, Hafnium oxynitride or the like can be used. By using these as the insulator 14, This allows it to function as an insulating film that has the effect of blocking the diffusion of hydrogen and water.

[0054] Next, the insulator 15 is formed on the insulator 14. The insulator 15 may have a single layer structure. Alternatively, the insulator 15 may be omitted. The film is formed using the sputtering method, CVD method, MBE method, PLD method, or ALD method. This can be done.

[0055] Next, a material for the hard mask 16 is deposited on the insulator 15. The material may be a conductor such as a metal material, or an insulator. The material for the mask 16 may be a single layer or a laminate of an insulator and a conductor. In this specification, the term "hard mask" refers to a material other than resist (such as a metal material). The hard mask 16 is made of an insulating material. The deposition can be performed by using a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. do.

[0056] Next, a hard mask 1 is formed using a resist mask formed by lithography or the like. The material of 6 is etched to form a hard mask 16 having an opening 17a (FIG. 5(A)). (See (B)). Here, FIG. 5(A) corresponds to the dashed line X1-X2 shown in FIG. 5(B). Similarly, below, cross-sectional views and top views are shown corresponding to the dashed dotted line X1-X2.

[0057] In the lithography method, first, the resist is exposed to light through a mask. The resist mask is formed by removing or leaving the exposed area using a developer. By etching through the resist mask, a conductor, a semiconductor, an insulator, etc. It can be processed into the desired shape. For example, KrF excimer laser light, ArF excimer Laser light, EUV (Extreme Ultraviolet) light, etc. are used to A resist mask can be formed by exposing the substrate to light. An immersion technique may be used in which the substrate is exposed to a liquid (for example, water). In addition, an electron beam or an ion beam may be used. In this case, the mask is not required. The resist mask can be removed by ashing or other methods. dry etching treatment, or wet etching treatment, or dry etching treatment In addition to the etching process, wet etching is performed, or in addition to the wet etching process, Additionally, a dry etching process can be performed.

[0058] The opening 17a has a circular top surface, but is not limited to this. The surface may be elliptical, triangular, rectangular or other polygonal. In the case of a rounded shape, the corners may be rounded.

[0059] Next, the insulators 15, 14 and 16 are etched using the hard mask 16 as an etching mask. The insulator 13 is etched until the top surface of the conductor 12 is exposed, forming an opening 17. 5a, insulator 14a and insulator 13a are formed. Here, hard mask 16 is etched. The thickness of the mask film is thinned to form a hard mask 16a. It is preferable that

[0060] The dry etching equipment is a capacitively coupled plasma (CCP) with parallel plate electrodes. Capacitively Coupled Plasma etching equipment is used. The capacitively coupled plasma etching apparatus having parallel plate electrodes can Alternatively, a high frequency power supply may be applied to one of the electrodes. A configuration in which a plurality of different high frequency power supplies are applied to the electrodes may also be used. Alternatively, a high frequency power supply of the same frequency may be applied to each of the parallel plate electrodes. Alternatively, a high-frequency power supply having a high-density plasma source may be used. Dry etching equipment with a high density plasma source can be used. The device may be, for example, an inductively coupled plasma (ICP) d Plasma etching equipment or the like can be used.

[0061] By-products may be formed on the side of the opening 17. The by-products may include the insulator 13, the insulator 1 4, a component contained in the insulator 15 or the hard mask 16, or the insulator 13, the insulator 1 The by-products are formed by containing components contained in the etching gas for the insulating layer 4 or the insulating layer 15. It can be removed by performing plasma treatment using a gas containing O2 gas.

[0062] In addition, an oxide of the conductor 12 is generated in the exposed portion of the bottom of the opening 17. These oxides can be removed by cleaning with pure water or chemicals. (See Figures 5(C) and (D)).

[0063] Next, a nitrogen-containing metal 20 is deposited in the opening 17. The nitrogen-containing metal 20 is a conductive metal. It is preferable to use a conductor that is less permeable to hydrogen than the conductor 21. As the oxide, it is preferable to use tantalum nitride or titanium nitride, especially tantalum nitride. By providing such a metal 20 containing nitrogen, impurities such as hydrogen and water can be prevented from being condensed into the conductor. Furthermore, the metal components contained in the conductor 21 can be prevented from diffusing into the conductor 21. Prevents the diffusion of the conductive material 21, prevents oxidation of the conductive material 21, and improves the adhesion of the conductive material 21 to the opening 17. In addition, when the metal 20 containing nitrogen is formed in a laminated structure, For example, titanium, tantalum, titanium nitride, tantalum nitride, etc. may be used. When depositing tantalum nitride as a nitrogen-containing metal, RTA (Rapid Thermal Atomic Energy Analysis) is used after deposition. Heat treatment may be performed using a thermal annealing device.

[0064] The nitrogen-containing metal 20 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, or the like. The nitrogen-containing metal 20 is formed in the opening 17. It is preferable that the film be formed with good coverage so as to cover the inner wall and bottom surface of the collimator. It is preferable to use a toner sputtering method, an MCVD method, an ALD method, or the like.

[0065] Collimated sputtering is achieved by placing a collimator between the target and the substrate. In other words, the sputtering particles have a perpendicular component to the substrate. The electrons pass through the collimator and reach the substrate. This allows the aperture 17 with a high aspect ratio to be formed. Since the sputtered particles can easily reach the bottom surface, a film can be sufficiently formed on the bottom surface of the opening 17. can.

[0066] In addition, the nitrogen-containing metal 20 is formed into a film by using the ALD method. The metal 20 is formed into a film with good coating properties, and pinholes or the like are not formed in the metal 20 containing nitrogen. By forming the metal 20 containing nitrogen in this way, The impurities such as hydrogen and water diffuse through the nitrogen-containing metal 20 into the conductor 21. For example, nitrogen can be further suppressed by using the ALD method to form a nitrogen-containing metal 20. When depositing tantalum chloride, pentakis(dimethylamino)tantalum (structural formula: Ta[N (CH3)2]5) can be used as a precursor.

[0067] When the ALD method or the like is used to form a film of the metal 20 containing nitrogen, the metal 20 contains nitrogen with high electrical resistivity. The metal 20 containing nitrogen may have a high electrical resistivity. A failure in the electrical connection with the conductor 12 may occur.

[0068] Here, a method for reducing the resistance of a nitrogen-containing metal, which is one embodiment of the present invention, will be described. The nitrogen-containing metal 20 is irradiated with a plasma containing a rare gas to form a nitrogen-containing metal. Specifically, for example, a process using argon gas can be performed. By irradiating the plasma, the surface of the metal 20 containing nitrogen is positively charged with argon in the plasma. The positive ions of argon are accelerated by the electric field in the plasma. Therefore, for example, if the electric field direction is perpendicular to the plane parallel to the back surface of the substrate, Therefore, the surface of the metal 20 having nitrogen formed on the side of the opening 17 is Since the surface faces almost parallel to the electric field direction, the amount of argon positive ions irradiated is small. The metal 20 containing nitrogen formed on the side of the substrate 17 is difficult to reduce the resistance. The area facing almost parallel to the electric field is perpendicular to the electric field direction, so it is irradiated with a lot of positive argon ions. Therefore, the resistance of the area facing approximately parallel to the rear surface of the substrate is reduced. This is preferable because it provides a good electrical connection with the exposed portion of the conductor 12 on the surface. The direction of ion irradiation is indicated by an arrow. The metal 20 containing nitrogen becomes low resistance by ion irradiation. The degraded area is indicated by a dotted line (see Figures 6(A) and (B)).

[0069] Plasma processing equipment includes dry etching equipment, PECVD equipment, and high density plasma processing equipment. A Zuma device and a sputtering device can be used. In particular, when a sputtering device is used, Preferably, the sputtering device has a function of reverse sputtering.

[0070] In sputtering, positive ions in the plasma usually move toward the target. The electric field is set so that the positive ions in the plasma The electric field is switched so that it moves toward the substrate rather than the target. Say what you want.

[0071] Next, we will look at the mechanism by which metals containing nitrogen become less resistive when irradiated with ions. An example using tantalum nitride will be explained. In tantalum nitride, the bond between Ta and N is Other bonds include Ta and O. Tantalum nitride, which has a high ratio of Ta and N bonds, is a resistive material. The resistivity is low, but the resistivity increases as the ratio of Ta and O bonds increases. Physical damage by Ta breaks the bond between Ta and O, reducing the bond between Ta and O. This increases the ratio of Ta and N bonds in tantalum nitride. As a result, it is believed that the resistance of tantalum nitride can be reduced.

[0072] Alternatively, when tantalum nitride is deposited using the ALD method, the surface of the tantalum nitride is The ratio of Ta and O bonds is sometimes greater than that of Ta and N bonds. By removing the high-resistance parts that account for a large proportion of the total volume through physical damage caused by ion irradiation, It is thought that this can lower the resistance of tantalum nitride. The ratio of Ta and O bonds is high. The high resistance portion is set to 3 nm or less, or 5 nm or less from the surface.

[0073] Next, a conductor 21 is formed on the nitrogen-containing metal 20 so as to fill the opening 17 (see FIG. See 6(C) and (D).

[0074] The conductor 21 may be, for example, boron, nitrogen, oxygen, fluorine, silicon, phosphorus, or aluminum. Smoke, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium Sm, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum and Conductors containing one or more types of tungsten may be used in a single layer or a multilayer. The film is formed by sputtering, CVD, MBE, PLD, ALD or plating methods. Here, the conductor 21 is formed so as to fill the opening 17. Therefore, it is preferable to use the CVD method (particularly the MCVD method) or the plating method.

[0075] Next, the conductor 21, the nitrogen-containing metal 20, the hard mask 16a, and the insulator 15a are polished. A polishing process is performed to remove the nitrogen-containing metal 20a and the conductor 21a embedded in the opening 17. (See Figure 1(A) and (B)). The polishing process can be mechanical polishing, chemical polishing, or the like. Chemical Mechanical Polishing: CMP) can be performed.

[0076] Here, the opening 17 functions as a via hole, a contact hole, or the like. The metal 20a and the conductor 21a are embedded in the opening 17 and function as plugs.

[0077] Here, the semiconductor device described in this embodiment has an oxide semiconductor provided over a semiconductor substrate. The above-described laminated insulator and a layer formed on the insulator are provided between the semiconductor substrate and the oxide semiconductor. A conductor is provided which functions as a plug and is embedded in the opening. In the semiconductor device shown in this embodiment, a transistor is formed using an oxide semiconductor. An element layer including a transistor is formed on the element layer including a semiconductor substrate. A transistor may be formed in an element layer including a capacitor element. For example, an element layer including a capacitor or the like may be formed on an element layer including an oxide semiconductor. Alternatively, the insulating film may be formed between an element layer including a semiconductor substrate and an element layer including an oxide semiconductor. good. Here, the insulator 14a has a function of blocking the diffusion of hydrogen and water. Impurities such as hydrogen and water are introduced from the insulator 13a through the insulator 14a into the element layer including the oxide semiconductor. Furthermore, the nitrogen-containing metal 20 can prevent the diffusion of hydrogen and water. The metal 20 having nitrogen has a function of blocking diffusion and is inserted into the opening 17 of the insulator 14a. As a result, the conductor 2 is prevented from passing through the opening 17 of the insulator 14a. 1 to prevent impurities such as hydrogen and water from diffusing into the element layer including the oxide semiconductor. This can be done.

[0078] In this way, the insulator 14a and the nitrogen-containing metal 20a are formed between the semiconductor substrate and the oxide semiconductor. By dividing the semiconductor substrate, impurities such as hydrogen or water contained in the device layer, etc. The object is inserted through a plug (conductor 21) or a via hole (opening 17) formed in the insulator 14a. This prevents diffusion to the upper layer. In this case, hydrogen is used to terminate the dangling bonds of the silicon substrate, The amount of hydrogen contained in the element layer including the conductive substrate is large, and hydrogen reaches the element layer including the oxide semiconductor. Although there is a risk of diffusion, the structure described in this embodiment can be used to It is possible to prevent hydrogen from diffusing into the element layer containing the element.

[0079] Oxide semiconductors are made by reducing impurities such as hydrogen and water, lowering carrier density, and providing high-purity pure oxide semiconductors. It is preferable that the oxide semiconductor be a pure or substantially highly pure intrinsic oxide semiconductor. By forming a transistor using a compound semiconductor, the electrical characteristics of the transistor can be stabilized. In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor can be used. This reduces the leakage current when the transistor is not conducting. By using a highly intrinsic or substantially highly purified intrinsic oxide semiconductor, The reliability can be improved.

[0080] <Plug making method 2> In the following, we will discuss plugs with different configurations from those shown in Figures 1(A) and (B), as shown in Figures 1(C) and (D). 1C and 1D are cross-sectional views and top views of the device. 2 shows a cross-sectional view and a top view corresponding to FIG.

[0081] 1(C) and (D) are drawings of the completed plug, and show the insulator 13a, the insulator 14a and the insulator The nitrogen-containing metal 20a and the conductor 22a are embedded in the opening 17 formed in the edge 15a. and the conductor 21a. Here, the opening 17 is a via hole or the like. The nitrogen-containing metal 20a, the conductor 21a, and the conductor 22a function as openings. The plug shown in Figures 1(A) and 1(B) functions as a plug embedded in the The conductor 22a is disposed between the nitrogen-containing metal 20a and the conductor 21a. In addition, at the bottom of the opening 17, the metal 20a containing nitrogen and the conductor 12 come into contact with each other. The metal 20a having nitrogen in the region has a region where the resistance is reduced. The region where the metal 20a having the element has a low resistance is indicated by a dotted line.

[0082] The method for producing the plug shown in FIGS. 1(C) and 1(D) is to form a metal 20 containing nitrogen. The process is the same as in plug fabrication method 1 (FIG. 6(A) and (B). Plasma treatment method and nitrogen-containing metal 20a by plasma treatment The effect of reducing the resistance is explained in the plug manufacturing method 1 described above.

[0083] In addition, after performing reverse sputtering as a plasma treatment, for example, the conductor that becomes the conductor 22a is This method can be performed continuously in the same sputtering device. This is expected to improve productivity.

[0084] The conductor 22a may be, for example, tantalum nitride or titanium nitride, particularly nitride. It is preferable to use tantalum. In addition, the conductor that becomes the conductor 22a may be a laminated film. For example, a laminated film of tantalum nitride and tantalum can be used. When copper is used as the conductor 21a, the laminated film of copper and tantalum is used. This is preferable because it improves adhesion to the film.

[0085] For the subsequent manufacturing steps and effects, please refer to the plug manufacturing method 1 described above. , plugs can be fabricated as shown in Figures 1(C) and (D).

[0086] <How to make wiring and plugs 1> Hereinafter, as a part of the configuration of a semiconductor device according to one aspect of the present invention, the configuration of wiring and plugs will be described. The manufacturing method thereof will be described with reference to the cross-sectional views and top views shown in FIGS. 2(A) and 2(B) and FIGS. 7 to 11. 2(A) and 2(B) and FIGS. 7 to 11 correspond to the dashed dotted line X1-X2. 1 shows a cross-sectional view and a top view of the same.

[0087] 2(A) and 2(B) are diagrams showing the completed wiring and plug, and FIGS. 7 to 11 show the conductor 12 (hereinafter referred to as , may be called a conductive film or wiring, etc.), and the insulator 13a, the insulator 14b and the insulating The nitrogen-containing metal 20a and the conductor are embedded in the opening 17f formed in the edge 15c. The process of connecting the opening 17f to the upper and lower portions is described. The lower part of the opening 17f (hereinafter referred to as opening 17fa) is a via hole or a capacitor. The upper part of the opening 17f (hereinafter referred to as opening 17fb) functions as a contact hole. The metal 20a having nitrogen functions as a groove for embedding a wiring pattern, etc. The portion of the conductor 21a that is embedded in the opening 17fa functions as a plug, and contains nitrogen. The metal 20a and the conductor 21a embedded in the opening 17fb function as wiring or the like. Furthermore, the nitrogen-containing metal 20a and the conductor 12 are in contact with each other at the bottom of the opening 17fa. The metal 20a having nitrogen in the corresponding region has a region where the resistance is reduced. The region where the resistance of the nitrogen-containing metal 20a is reduced is indicated by a dotted line.

[0088] First, a conductor 12 is formed on a substrate. The conductor 12 may have a single layer structure or a multilayer structure. It should be noted that the substrate is not shown in FIGS. 2(A) and 2(B) and 7 to 11. In addition, a structure in which another conductor, an insulator, a semiconductor, or the like is provided between the substrate and the conductor 12 is also possible. It may also be composed.

[0089] The conductor 12 can be formed by the same method as that for the nitrogen-containing metal 20 and the conductor 21. That's fine.

[0090] Next, an insulator 13 is formed on the conductor 12. The insulator 13 may have a single layer structure. The insulator 13 may be formed by a sputtering method, a CVD method, an MBE method, or the like. The deposition can be carried out by using a PLD method, an ALD method, or the like.

[0091] Next, the insulator 14 is formed on the insulator 13. The insulator 14 may have a single layer structure. The insulator 14 may be formed by a sputtering method, a CVD method, an MBE method, or the like. , PLD method, ALD method, or the like can be used.

[0092] The insulator 14 is preferably made of a material that is less permeable to hydrogen and water than the insulator 13. The insulator 14 may be, for example, aluminum oxide, aluminum oxynitride, or gallium oxide. gallium oxide nitride, yttrium oxide, yttrium oxide nitride, hafnium oxide, Hafnium oxynitride or the like can be used. By using these as the insulator 14, This allows it to function as an insulating film that has the effect of blocking the diffusion of hydrogen and water.

[0093] Next, the insulator 15 is formed on the insulator 14. The insulator 15 may have a single layer structure. The insulator 15 may be formed by a sputtering method, a CVD method, an MBE method, or the like. , PLD method, ALD method, or the like can be used.

[0094] Next, a material for the hard mask 16 is deposited on the insulator 15. The material may be a conductor such as a metal material, or an insulator. The material for the mask 16 may be a single layer or a laminate of an insulator and a conductor. In this specification, the term "hard mask" refers to a material other than resist (such as a metal material). The hard mask 16 is made of an insulating material. The deposition can be performed by using a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. do.

[0095] Next, a hard mask 1 is formed using a resist mask formed by lithography or the like. The material of 6 is etched to form a hard mask 16 having an opening 17a (FIG. 7(A)). (See (B)). Here, FIG. 7(A) corresponds to the dashed line X1-X2 shown in FIG. 7(B). Similarly, below, cross-sectional views and top views are shown corresponding to the dashed dotted line X1-X2.

[0096] Here, the opening 17a is an opening 17fb to be formed in a later step, that is, an opening into which a wiring pattern is to be embedded. Therefore, the upper surface shape of the opening 17a corresponds to the wiring pattern. become.

[0097] Next, a resist mask 1 having an opening 17b is formed on the insulator 15 and the hard mask 16. 7(C)(D) 。 Here, the resist mask 18a is a hard mask. It is preferable that the resist is formed so as to cover the mask 16. This also includes the case where an organic coating film or the like is formed under the resist.

[0098] Here, the opening 17b is an opening 17fa, that is, a via hole or a contact hole, to be formed in a later step. Therefore, the upper surface of the opening 17b corresponds to a via hole or a contact hole. It corresponds to a contact hole. It also corresponds to a via hole or a contact hole. The opening 17b is formed in the opening 17a corresponding to the groove in which the wiring pattern is to be embedded. In this case, it is preferable that the maximum width of the opening 17b is equal to or smaller than the minimum width of the opening 17a. For example, if the width of the opening 17b in the X1-X2 direction shown in FIG. 7(C)(D) is The width of the opening 17a in the X1-X2 direction shown in A) and (B) is less than the width of the opening 17a. This allows via holes or contact holes to be placed with a margin relative to the grooves of the wiring pattern. It can be formed by adding

[0099] The opening 17b has a circular top surface, but is not limited to this. The surface may be elliptical, triangular, rectangular or other polygonal. In the case of a rounded shape, the corners may be rounded.

[0100] Next, the insulator 15 is etched using the resist mask 18a to form an opening 17c. The insulator 15a is formed (see FIGS. 8(A) and 8(B)). Etching is performed until the upper surface of the edge 14 is exposed. The etching is performed by dry etching. It is preferable to use a

[0101] Next, the insulator 14 is etched using the resist mask 18a to form an opening 17d. The insulator 14a is formed (see FIGS. 8(C) and (D)). Etching is performed until the upper surface of the edge 13 is exposed. It is preferable to use the same dry etching equipment as above. can be done.

[0102] Furthermore, when forming the opening 17d, it is not necessary to stop the etching on the top surface of the insulator 13. For example, the opening 17d is formed, and then a part of the insulator 13 is etched to form the opening 17d. An insulator having a recess formed at a position overlapping with 17d may be formed.

[0103] Next, the resist mask 18a is removed (see FIGS. 9(A) and 9(B)). If an organic coating film is formed under 8a, it is removed together with the resist mask 18a. The resist mask 18a is preferably removed by dry etching such as ashing. Or, wet etching process is performed, or wafer is subjected to dry etching process in addition to the wet etching process or dry etching process in addition to wet etching process This can be done by practicing the principles.

[0104] After removing the resist mask 18a, a by-product is formed around the upper edge of the opening 17c. The by-products may be insulator 14, insulator 15 or resist mask. 18a or the etching gas for the insulator 14 or the insulator 15. The by-products are removed when the opening 17e is formed in the next step. It is possible.

[0105] Next, the insulators 13, 14a and 15a are etched using the hard mask 16. The insulators 13a, 14b, and 15b are formed by etching, and the openings 17e are formed in the insulators 13a, 14b, and 15b. (See FIGS. 9(C) and (D)). Here, the upper surface of the conductor 12 is At this time, the edge of the opening 17a of the hard mask 16 is also etched. The hard mask 16a may be etched to form a hard mask 16a. The edge of the opening 17a has a tapered shape, and the upper part of the edge of the opening 17a is rounded. It is preferable to use dry etching for the etching. The same devices as those described above can be used.

[0106] Here, the opening 17e is located at the bottom and is formed using the insulator 14a as a mask. ea and an opening 17eb located on the top and formed using the hard mask 16 as a mask. The opening 17ea will be a via hole or a contact hole in a later process. The opening 17eb will function as a groove into which a wiring pattern will be embedded in a later process. It functions as such.

[0107] The insulator 15b has a tapered edge (which can also be called the inner wall of the opening 17eb) of the opening 17eb. As shown in FIG. 9(D), the tape of the insulator 15b is preferably The bar-shaped portion may be formed so as to be visible from the top surface.

[0108] The insulators 13a and 14b are formed on the edge of the opening 17ea (also called the inner wall of the opening 17ea). It is preferable that the opening 17ea of the insulator 14b has a tapered shape. It is preferable that the upper part of the edge of the opening 17ea is rounded. As a result, in the subsequent process, the metal 20 having nitrogen, which has high blocking ability against hydrogen, can be coated with the metal 20 with good coating properties. As shown in FIG. 9(D), the tapered portion of the insulator 13a Sometimes the molars are formed so that they are visible from the top.

[0109] In order to etch the opening 17ea into such a shape, in the above dry etching The etching rate of the insulator 13 is excessively large relative to the etching rate of the insulator 14a. For example, it is preferable that the etching rate of the insulator 13 is not higher than that of the insulator 14a. The thickness should be 8 times or less, preferably 6 times or less, more preferably 4 times or less of the thickness of the chining rate. .

[0110] By carrying out the dry etching under these conditions, a tapered edge of the opening 17ea is formed. Furthermore, even if a by-product is formed, the by-product can be removed. By removing the opening 17ea of the insulator 14b, the upper edge of the opening 17ea can be rounded. do.

[0111] However, the shape of the opening 17e is not necessarily limited to the above shape. The inner walls of 17ea and opening 17eb may be formed substantially vertically. Alternatively, the opening 17eb may be formed in the insulator 15b and the insulator 14b. , so that openings 17eb are formed in the insulators 15b, 14b and 13a. That's fine.

[0112] Next, a nitrogen-containing metal 20 is deposited in the opening 17e. It is preferable that the film of O be formed with good coverage so as to cover the inner wall and bottom surface of the opening 17e. Preferably, the metal 20 having nitrogen therein contacts the insulator 14b at the edge of the opening 17e. Preferably, the opening formed in the insulator 14b is closed with the nitrogen-containing metal 20. As described above, the edge of the opening 17ea of the insulator 14b is tapered, and the insulating The upper edge of the opening 17ea of the edge body 14b is rounded, so that the nitrogen-containing gas This can further improve the coverage of the metal 20 .

[0113] The nitrogen-containing metal 20 is preferably made of a conductor that is less permeable to hydrogen than the conductor 21. The nitrogen-containing metal 20 is preferably tantalum nitride or titanium nitride, particularly titanium nitride. It is preferable to use metal 20 having nitrogen. It is possible to prevent impurities such as hydrogen and water from diffusing into the conductor 21. Preventing diffusion of metal components contained in the conductor 21, preventing oxidation of the conductor 21, and forming openings in the conductor 21 It is possible to obtain the effect of improving adhesion to 17e. When the metal 20 is formed as a laminate, for example, titanium, tantalum, titanium nitride, or tantalum nitride may be used. In addition, when forming a film of tantalum nitride as a metal containing nitrogen, After the film formation, a heat treatment may be performed using an RTA apparatus.

[0114] The nitrogen-containing metal 20 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, or the like. The nitrogen-containing metal film can be formed by a coating method or an ALD method. It is preferable that the deposition be carried out by a method with good performance, such as a collimated sputtering method or an MCVD method. Alternatively, it is preferable to use an ALD method or the like.

[0115] Here, the collimated sputtering method involves placing a collimator between the target and the substrate. This allows for directional deposition. The sputter particles pass through the collimator and reach the substrate. This allows for high aspect ratio apertures. Since sputter particles can easily reach the bottom of the opening 17ea, As described above, the inner walls of the openings 17ea and 17eb can be formed separately. By forming the opening 17ea and the opening 17eb in a tapered shape, a film can be sufficiently formed on the inner walls of the opening 17ea and the opening 17eb. It is possible.

[0116] In addition, the nitrogen-containing metal 20 is formed into a film by using the ALD method. The metal 20 is formed into a film with good coating properties, and pinholes or the like are not formed in the metal 20 containing nitrogen. By forming the metal 20 containing nitrogen in this way, The impurities such as hydrogen and water diffuse through the nitrogen-containing metal 20 into the conductor 21. For example, nitrogen can be further suppressed by using the ALD method to form a nitrogen-containing metal 20. When depositing tantalum chloride, pentakis(dimethylamino)tantalum (structural formula: Ta[N (CH3)2]5) can be used as a precursor.

[0117] When the ALD method or the like is used to form a film of the metal 20 containing nitrogen, the metal 20 contains nitrogen with high electrical resistivity. The metal 20 containing nitrogen may have a high electrical resistivity. A failure in the electrical connection with the conductor 12 may occur.

[0118] Here, a method for reducing the resistance of a nitrogen-containing metal, which is one embodiment of the present invention, will be described. The nitrogen-containing metal 20 is irradiated with a plasma containing a rare gas to form a nitrogen-containing metal. Specifically, for example, a process using argon gas can be performed. By irradiating the plasma, the surface of the metal 20 containing nitrogen is positively charged with argon in the plasma. The positive ions of argon are accelerated by the electric field in the plasma. Therefore, for example, if the electric field direction is perpendicular to the plane approximately parallel to the rear surface of the substrate, this electric field Therefore, the surface of the metal 20 having nitrogen formed on the side of the opening 17e is Since the surface faces almost parallel to the electric field direction, the amount of argon positive ions irradiated is small. The resistance of the nitrogen-containing metal 20 formed on the side surface of the opening 17e is difficult to lower. The area facing approximately parallel to the back surface faces perpendicular to the electric field direction, so it is irradiated by positive ions of argon. The area facing the rear surface of the substrate in parallel with the surface of the substrate has a low resistance because of the increased reflection. This is preferable because it provides a good electrical connection with the exposed portion of the conductor 12 on the bottom surface of the insulating layer 7e. The nitrogen in the region approximately parallel to the rear surface of the substrate is in contact with the insulator 14b and the nitrogen-containing metal 20. The metal 20 having the element is also reduced in resistance. The direction of ion irradiation is indicated by an arrow in FIG. 10(A). The region where the resistance of the metal 20 containing nitrogen is reduced by ion irradiation is indicated by a dotted line. (See Figures 10(A) and (B)).

[0119] Plasma processing equipment includes dry etching equipment, PECVD equipment, and high density plasma processing equipment. A Zuma device and a sputtering device can be used. In particular, when a sputtering device is used, Preferably, the sputtering device has a function of reverse sputtering.

[0120] In sputtering, positive ions in the plasma usually move toward the target. The electric field is set so that the positive ions in the plasma The electric field is switched so that it moves toward the substrate rather than the target. Say what you want.

[0121] Next, we will look at the mechanism by which metals containing nitrogen become less resistive when irradiated with ions. An example using tantalum nitride will be explained. In tantalum nitride, the bond between Ta and N is Other bonds include Ta and O. Tantalum nitride, which has a high ratio of Ta and N bonds, is a resistive material. The resistivity is low, but the resistivity increases as the ratio of Ta and O bonds increases. Physical damage by Ta breaks the bond between Ta and O, reducing the bond between Ta and O. This increases the ratio of Ta and N bonds in tantalum nitride. As a result, it is believed that the resistance of tantalum nitride can be reduced.

[0122] Alternatively, when tantalum nitride is deposited using the ALD method, the surface of the tantalum nitride is The ratio of Ta and O bonds is sometimes greater than that of Ta and N bonds. By removing the high-resistance parts that account for a large proportion of the total volume through physical damage caused by ion irradiation, It is thought that this can lower the resistance of tantalum nitride. The ratio of Ta and O bonds is high. The high resistance portion is set to 3 nm or less, or 5 nm or less from the surface.

[0123] Next, a conductor 21 is formed on the nitrogen-containing metal 20 so as to fill the opening 17e. See Figure 11(A)(B).

[0124] The conductor 21 may be, for example, boron, nitrogen, oxygen, fluorine, silicon, phosphorus, or aluminum. Smoke, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium Sm, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum and Conductors containing one or more types of tungsten may be used in a single layer or a multilayer. The deposition of the conductor 21 can be performed by a sputtering method, a CVD method, an MBE method, a PLD method, an A method, The conductor 21 can be formed by the LD method, plating method, or the like. Since the hole 17e is buried, the CVD method (particularly the MCVD method) or the plating method is used. It is preferable that

[0125] Next, the conductor 21, the nitrogen-containing metal 20, the hard mask 16a, and the insulator 15b are polished. A polishing process is performed to remove the nitrogen-containing metal 20a and the conductor 21a from the opening 17f. (See Figure 11(C)(D)). The polishing process can be mechanical polishing, chemical polishing, or the like. For example, by performing the CMP process, the insulator 15b and the conductor 2 The upper part of the metal 20 containing 1 and nitrogen, as well as the hard mask 16a, are removed, and the upper surface is flat. Insulator 15c, conductor 21a, and metal 20a containing nitrogen can be formed.

[0126] Here, the opening 17f is located at the bottom and functions as a via hole, a contact hole, or the like. and an opening 17fa located at the top that functions as a groove for embedding wiring patterns, etc. The opening 17fa can be seen as being composed of the insulator 13a and the opening 17fb. The opening 17fb is formed in the insulator 14b, and the opening 17fb is formed in the insulator 15c. The portion of the conductor 20a and the conductor 21a embedded in the opening 17fa functions as a plug. The metal 20a having the element and the conductor 21a are embedded in the opening 17fb. It functions as:

[0127] The nitrogen-containing metal 20a is preferably in contact with the insulator 14b at the edge of the opening 17fa. The nitrogen-containing metal 20a has a rounded shape at the top of the opening 17fa of the insulator 14b. It is more preferable that this portion contacts the tapered portion of the edge of the opening 17fa. It is more preferable that the metal 2 containing nitrogen is in contact with the upper surface of the insulator 14b. 0a contacts the inner wall of the opening 17fa of the insulator 13a and the inner wall of the opening 17fb of the insulator 15c. It is preferable that the

[0128] As shown in this embodiment, the insulating film 100 functions as a via hole or a contact hole. and an opening 17eb which functions as a groove for embedding a wiring pattern or the like. After the opening 17e is formed, the nitrogen-containing metal 20 is deposited. The portion of the metal 20a that functions as the wiring and the portion that functions as the plug are integrally formed. As a result, for example, in the vicinity of the boundary between the opening 17ea and the opening 17eb, a nitrogen-containing Since the metal 20a is continuously formed, it has better blocking properties against hydrogen and water. In addition, the wiring and plugs can be fabricated using the single damascene method. When using this method to form a film, the formation of the plug and the formation of the wiring require the deposition of a conductor and the CMP process, respectively. However, in the method shown in this embodiment, the wiring and plug type This allows for the deposition of conductive material and polishing processes such as CMP to be completed in one step. This allows the process to be shortened.

[0129] Here, the semiconductor device described in this embodiment has an oxide semiconductor provided over a semiconductor substrate. The above-described laminated insulator and a layer formed on the insulator are provided between the semiconductor substrate and the oxide semiconductor. and a conductor that functions as a wiring and a plug and is embedded in the opening. The semiconductor device described in this embodiment has a transistor formed using an oxide semiconductor. An element layer including the transistor is formed over an element layer including a semiconductor substrate. A transistor may be formed in an element layer including a semiconductor substrate. For example, an element layer including a capacitor element may be formed on an element layer including an oxide semiconductor. The semiconductor layer may be formed on an element layer including a semiconductor substrate and an element layer including an oxide semiconductor. It may be formed between.

[0130] In the semiconductor device having such a configuration, as shown in FIGS. 11(C) and 11(D), the insulator 14b It is preferable that the nitrogen-containing metal 20a contacts the edge of the opening 17fa formed in the In other words, the opening 17fa formed in the insulator 14b is filled with the nitrogen-containing metal 20a. It is preferable that the shape is closed with

[0131] Here, the insulator 14b has a function of blocking the diffusion of hydrogen and water. Impurities such as hydrogen and water pass from the body 13a through the insulator 14b and reach the element layer including the oxide semiconductor. Furthermore, the nitrogen-containing metal 20 can prevent the diffusion of hydrogen and water. The nitrogen-containing metal 20 has a function of blocking diffusion, and the nitrogen-containing metal 20 is disposed in the opening 17f of the insulator 14b. As a result, the conductor is prevented from leaking into the opening 17f of the insulator 14b. 21 to prevent impurities such as hydrogen and water from diffusing into the element layer including the oxide semiconductor. It is possible.

[0132] In this way, the insulator 14b and the nitrogen-containing metal 20a are formed between the semiconductor substrate and the oxide semiconductor. By dividing the semiconductor substrate, impurities such as hydrogen or water contained in the device layer, etc. The object penetrates the plug (conductor 21) or the via hole (opening 17fa) formed in the insulator 14b. In particular, when a silicon substrate is used as a semiconductor substrate, the diffusion of the metal to the upper layer can be prevented. When using hydrogen, hydrogen is used to terminate the dangling bonds of the silicon substrate. The amount of hydrogen contained in the element layer including the semiconductor substrate is large, and the amount of hydrogen reaches the element layer including the oxide semiconductor. However, by adopting the structure shown in this embodiment, the oxide semiconductor This can prevent hydrogen from diffusing into the element layer including the conductor.

[0133] As will be described in detail later, oxide semiconductors reduce impurities such as hydrogen and water and increase carrier density. It is preferable to reduce the concentration of the oxide semiconductor to a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. By forming a transistor using such an oxide semiconductor, The electrical characteristics of the capacitor can be stabilized. By using a certain oxide semiconductor, leakage current when a transistor is off can be reduced. In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor can be used. This can improve the reliability of the transistor.

[0134] <How to make wiring and plugs 2> In the following, we will discuss plugs with different configurations from those shown in Figures 2(A) and (B), as shown in Figures 2(C) and (D). 2(C) and (D) are cross-sectional views and top views of the X1-X 2 shows a cross-sectional view and a top view corresponding to FIG.

[0135] FIG. 2(C) shows the completed wiring and plug, and the insulators 13a, 14b and 1 The nitrogen-containing metal 20a, the conductor 22a, and the conductor 23a are embedded in the opening 17f formed in the semiconductor substrate 5c. The opening 17f is formed at the top and bottom. The lower part of the opening 17f (hereinafter referred to as opening 17fa) is a via hole or a capacitor. The upper part of the opening 17f (hereinafter referred to as opening 17fb) functions as a contact hole. The metal 20a containing nitrogen functions as a groove for embedding a wiring pattern, etc. The conductor 22a and the portion of the conductor 21a embedded in the opening 17fa function as a plug. The nitrogen-containing metal 20a, the conductor 22a, and the conductor 21a are embedded in the opening 17fb. The plugged portion functions as wiring, etc. The wiring and plug shown in Figures 2(A) and 2(B) are The conductor 22a is disposed between the nitrogen-containing metal 20a and the conductor 21a. Also, at the bottom of the opening 17fa, the metal 20a containing nitrogen and the conductor 12 are The metal 20a having nitrogen in the contact region has a region where the resistance is reduced. The region where the resistance of the metal 20a containing nitrogen is reduced is indicated by a dotted line.

[0136] The method for fabricating the wiring and plug shown in Figures 2(C) and 2(D) uses a nitrogen-containing metal 2 The process from forming the SiO2 film to plasma treatment is the same as in Method 1 for fabricating wiring and plugs (Fig. 1 See (A) and (B). The plasma treatment method and the nitrogen-containing Regarding the effect of reducing the resistance of the metal 20a, please refer to the above-mentioned method 1 for manufacturing the wiring and plug. do.

[0137] In addition, after performing reverse sputtering as a plasma treatment, for example, the conductor that becomes the conductor 22a is This method can be performed continuously in the same sputtering device. This is expected to improve productivity.

[0138] The conductor 22a may be, for example, tantalum nitride or titanium nitride, particularly nitride. It is preferable to use tantalum. In addition, the conductor that becomes the conductor 22a may be a laminated film. For example, a laminated film of tantalum nitride and tantalum can be used. When copper is used as the conductor 21a, the laminated film of copper and tantalum is used. This is preferable because it improves adhesion to the film.

[0139] For the subsequent manufacturing steps and effects, please refer to the above-mentioned wiring and plug manufacturing method 1. This allows the wiring and plugs shown in Figures 2(C) and (D) to be fabricated.

[0140] The shapes of the wiring and plugs shown in this embodiment are not limited to those shown in FIG. The following shows the wiring and plugs that differ from those shown in Figure 2.

[0141] The shapes of the wiring and plug shown in FIG. 3(A) are different in that the shape of the opening 17g is different from that of the opening 17f. The opening 17g is located at the bottom and is a via hole or a capacitor. The opening 17ga functions as a contact hole, and the upper part is used for wiring patterns. It can be seen as consisting of 17GB openings that function as recesses for embedding. The opening 17gb is formed in the lower part of the insulator 13a and the insulator 14b. c and the insulator 14b. The metal 20a having the element and the conductor 21a are formed by an insulator 14b. The insulating body 14b is provided so as to be embedded in the upper part of the opening. The inner walls of the openings 17ga and 17gb are formed in a stepped shape.

[0142] The shapes of the wiring and plug shown in FIG. 3(B) are different in that the shape of the opening 17h is different from that of the opening 17f. The opening 17h is located at the bottom and is a via hole or a capacitor. The opening at the top is 17ha, which functions as a contact hole, and the wiring pattern is It can be seen as consisting of opening 17hb, which functions as a recess for filling. The opening 7ha is formed in the lower part of the insulator 13a, and the opening 17hb is formed in the insulators 15c, 14b, and Therefore, in the structure shown in FIG. 3(B), nitrogen is The metal 20a and the conductor 21a are arranged on the insulator 13a. The insulator 13a is provided so as to be embedded in the opening. Here, the inner wall of the opening provided in the insulator 13a is The inner walls of opening 17ha and opening 17hb are formed in a stepped shape.

[0143] The shapes of the wiring and plug shown in FIG. 3(C) are different in that the shape of the opening 17i is different from that of the opening 17f. The opening 17i is located at the bottom and is a via hole or a capacitor. The opening 17a functions as a contact hole, and the upper part is used for wiring patterns. It can be seen as consisting of an opening 17ib that functions as a recess for filling. An opening 7ia is formed in the insulator 13a, and an opening 17ib is formed in the insulators 15c and 14b. Therefore, in the structure shown in FIG. 3(C), the metal 20a containing nitrogen and the conductive The portion of the body 21a that functions as wiring or the like is provided so as to be embedded in the insulator 14b. Here, the inner wall of the opening of the insulator 14b is formed in a gentle tapered shape.

[0144] The shapes of the wiring and plug shown in FIG. 4(A) are different from those of the opening 17f in that the opening 17j has a different shape. The opening 17j is located at the bottom and is a via hole or a capacitor. The opening 17ja functions as a contact hole, and the upper part is used for wiring patterns, etc. It can be seen as being composed of an opening 17jb that functions as a recess for embedding. The opening 7ja is formed in the insulator 13a and the insulator 14b, and the opening 17jb is formed in the insulator 15c. Therefore, in the structure shown in FIG. 4(A), the metal 20a containing nitrogen and the conductive The portion of the body 21a that functions as wiring or the like is provided so as to be embedded in the insulator 15c. Here, the inner walls of the opening 17ja formed in the insulator 13a and the insulator 14b are made of the conductor 1. The inner wall of the opening 17jb in the insulator 15c is The inner wall of the opening is provided substantially perpendicular to the insulator 14b. In this case, in order to form a nitrogen-containing metal film 20a with a sufficient thickness on the inner wall of the opening, ALD is used. It is preferable to form a film of the metal 20a containing nitrogen by using a method such as a method for forming a nitrogen-containing metal film.

[0145] The shapes of the wiring and plug shown in Figure 4(B)(C) are different from those of the opening 17k. The opening 17k is located at the bottom and is not connected to the via hole. 17ka of openings that function as contact holes, etc., and a wiring pattern located on top. It can be seen as consisting of a 17kb opening that functions as a groove for embedding the above. The shape of the wiring and plug shown in Fig. 4(B)(C) is such that the maximum width of the opening 17ka is For example, the X1- of the aperture 17 ka shown in Fig. 4(B)(C) is The width in the X2 direction is approximately equal to the width of the opening 17 kb in the X1-X2 direction. In this way, the area occupied by the wiring can be reduced. For example, the width of the opening 17a in the hard mask 16 in the X1-X2 direction shown in FIG. 7(A)(B) and the The widths of the openings 17b in the resist mask 18a shown in FIGS. 7(C) and 7(D) in the X1-X2 direction are approximately the same. You can set it to do so.

[0146] <Structure of Transistor Having Oxide Semiconductor Film> 12(A), (B), and (C) show transistors formed in an element layer containing an oxide semiconductor. 12A is a top view of the transistor 60a, and FIG. 1B is a cross-sectional view of the transistor 60a along the channel length direction A1-A2. 2(C) is a cross-sectional view of the transistor 60a taken along the channel width direction A3-A4. The channel length direction of the transistor is the direction parallel to the substrate and parallel to the source (source region). Between the source electrode and the drain electrode, The channel width direction is the direction in which carriers move, and the channel width direction is the direction in which the carriers move within a plane parallel to the substrate. This refers to the direction perpendicular to the longitudinal direction of the panel.

[0147] In the cross-sectional views of FIG. 12(B) and FIG. 12(C), the patterned conductive Although the edges of electric conductors, semiconductors, insulators, etc. are shown at right angles in the drawings, The semiconductor device shown in FIG. 1 is not limited to this, and the end portions may be rounded.

[0148] The transistor 60a includes a conductor 62a, a conductor 62b, an insulator 65, and an insulator 63. , an insulator 64, an insulator 66a, a semiconductor 66b, a conductor 68a, a conductor 68b, The insulator 66c, the insulator 72, and the conductor 74 are included. The conductor 62b acts as the back gate of the transistor 60a, and the insulator 65, the insulating The body 63 and the insulator 64 serve as gate insulating films for the back gate of the transistor 60a. Conductor 68a and conductor 68b function as the source or drain of transistor 60a. The insulator 72 functions as a gate insulating film of the transistor 60a. and conductor 74 serves as the gate of transistor 60a.

[0149] As will be described in detail later, when the insulators 66a and 66c are used alone, they are conductors, In some cases, materials that can function as semiconductors or insulators are used. Therefore, when a transistor is formed by stacking the semiconductor 66b, electrons pass through the semiconductor 66b. The flow passes through the vicinity of the interface between the semiconductor 66b and the insulator 66a, and the vicinity of the interface between the semiconductor 66b and the insulator 66c. The insulators 66a and 66c are regions that do not function as the channel of the transistor. Therefore, in this specification and the like, the insulators 66a and 66c are introduced. Instead of describing them as conductors and semiconductors, they will be described as insulators or oxide insulators.

[0150] In this embodiment and the like, the term "insulator" can be replaced with "insulating film" or "insulating layer." The term "conductor" can also be replaced with "conductive film" or "conductive layer." The term "semiconductor" can also be rephrased as "semiconductor film" or "semiconductor layer."

[0151] Below the transistor 60a, an insulator 67 having an opening is provided on the insulator 61. A conductor 62a is provided in the opening, and a conductor 62b is provided on the conductor 62a. At least a portion of the conductor 62a and the conductor 62b is covered with an insulator 66 a, semiconductor 66b, and insulator 66c overlap. The conductors 62a and 62b functioning as gates are connected to the above-mentioned wiring and plug. The conductors 21a and 21b, which function as a pair, can be fabricated in parallel. The insulator 61 is connected to the insulator 14b, the insulator 67 is connected to the insulator 15c, and the conductor 62a is connected to the insulator 14b. The metal 20a corresponds to the conductor 62b, and the conductor 21a corresponds to the conductor 21a.

[0152] The upper surfaces of the conductors 62a and 62b are in contact with the conductors 62a and 62b. An insulator 65 is provided to cover the insulating material 63. An insulator 64 is provided on the edge 63 .

[0153] Here, one end of the conductor 62a and the conductor 62b in the channel length direction is a part of the conductor 68a. The other ends of the conductors 62a and 62b in the channel length direction overlap with one of the conductors 68b. It is preferable that the conductors 62a and 62b overlap with each other. Therefore, the region between the conductors 68a and 68b of the semiconductor 66b, that is, the region between the conductors 68a and 68b of the semiconductor 66b, The channel forming region can be sufficiently covered with the conductors 62a and 62b. Therefore, conductor 62a and conductor 62b are used to further control the threshold voltage of transistor 60a. This can be done more effectively.

[0154] An insulator 66a is provided on the insulator 64, and the insulator 66a is in contact with at least a part of the upper surface of the insulator 66a. In addition, in FIGS. 12(B) and 12(C), the insulator 66a The insulator 66a and the semiconductor 66b are formed so that the ends of the insulator 66a and the semiconductor 66b are approximately aligned. However, the structure of the semiconductor device described in this embodiment is not limited to this.

[0155] A conductor 68a and a conductor 68b are formed in contact with at least a part of the upper surface of the semiconductor 66b. The conductor 68a and the conductor 68b are formed apart from each other, as shown in FIG. It is preferable that the electrodes are formed facing each other with the conductor 74 interposed therebetween.

[0156] An insulator 66c is provided in contact with at least a portion of the upper surface of the semiconductor 66b. is formed to cover the upper surface of the conductor 68a and the upper surface of the conductor 68b, etc. It is preferable that the conductive material 8a contacts a part of the upper surface of the semiconductor 66b between the conductive material 8a and the conductive material 68b.

[0157] An insulator 72 is provided on the insulator 66c. The insulator 72 is provided between the conductor 68a and the conductor 68b. It is preferable that the insulator 66c contacts a part of the upper surface of the insulator 66c between the points b.

[0158] A conductor 74 is provided on the insulator 72. The conductor 74 is a conductor between the conductors 68a and 68b. It is preferable that the insulating member 72 contacts a part of the upper surface of the insulating member 72 between the insulating member 72 and the upper surface of the insulating member 72 .

[0159] An insulator 79 is provided to cover the conductor 74. However, the insulator 79 is not necessarily provided. There is no need to.

[0160] The insulator 66c covers the insulator 66a, the semiconductor 66b, the conductor 68a, and the conductor 68b. The insulating member 64 is provided so as to be in contact with the upper surface of the insulating member 64 .

[0161] However, the transistor 60a is not limited to the configuration shown in FIGS. 12(A), (B), and (C). For example, the A1-A2 direction of the insulator 66c, the insulator 72, and the conductor 74 For example, the insulator 72 may be provided so that the sides of the insulator 66 are aligned. a, the semiconductor 66b, the conductor 68a, and the conductor 68b are covered, and the insulating material 64 is in contact with the upper surface of the insulating material 64. The configuration may be such that the sensor is provided so as to

[0162] The conductor 74 is made up of the insulators 72, 66c, 64, 63, and 65. Alternatively, the conductive material 62 may be connected to the conductive material 62b through an opening formed in the conductive material 62b.

[0163] An insulator 77 is provided on the insulator 66c and the insulator 79. An insulator 78 is provided on top of the 7.

[0164] Next, a modified example of the transistor 60a will be described with reference to FIGS. 13(A), (B), and (C). 13A is a top view of the transistor 60b, and FIGS. 12B and 12C, the channel length direction of the transistor 60b is 10A and 10B are cross-sectional views of the transistor 60b in the channel width direction.

[0165] The transistor 60b shown in FIGS. 13A, 13B, and 13C has an insulator 64, a conductor 6 An insulator 77 is provided on the conductor 68a and the conductor 68b. and an insulator 66c, an insulator 12(A), (B) and (C) at the point where 72 and conductor 74 are provided. 13(A), (B), and (C). Other configurations of the transistor 60b are shown in FIGS. 12(A), (B) and (C). The configuration of the transistor 60a can be taken into consideration.

[0166] In addition, the transistor 60b has an insulator 76 provided on an insulator 77. In this case, the insulator 76 may be used as the insulator 77. In addition, the transistor 60b does not need to be provided with the insulator 79. However, the present invention is not limited to this configuration, and an insulator 79 may be provided.

[0167] However, the transistor 60b is not limited to the configuration shown in FIGS. 13(A), (B), and (C). For example, the side surfaces of the insulator 66c, the insulator 72, and the conductor 74 are not necessarily the same as the semiconductor 66c. It may have a tapered shape inclined at an angle of 30° or more and less than 90° with respect to the upper surface of 6b. stomach.

[0168] <Oxide semiconductor> The oxide semiconductor used for the semiconductor 66b will be described below.

[0169] The oxide preferably contains at least indium or zinc. In addition to these, aluminum, gallium, yttrium, and zinc are preferably contained. It is preferable that the material contains boron, silicon, titanium, or the like. , iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium One selected from zinc, hafnium, tantalum, tungsten, or magnesium Or, multiple types may be included.

[0170] Here, consider a case where the oxide contains indium, element M, and zinc. is aluminum, gallium, yttrium, or tin. Other elements M Applicable elements include boron, silicon, titanium, iron, nickel, germanium, and di Zr, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tantalum However, the element M can be a combination of multiple of the above elements. There are cases where it is acceptable to do so.

[0171] First, with reference to FIGS. 14(A), 14(B), and 14(C), the oxide according to the present invention will be described. The preferred range of the atomic ratio of indium, element M, and zinc contained in the alloy will be described below. In addition, the atomic ratio of oxygen is not shown in FIG. The atomic ratios of elements In, M, and zinc are expressed as [In], [M], and [Zn], respectively. Let's say.

[0172] In Figures 14(A), 14(B), and 14(C), the dashed lines represent the [In]:[M] :[Zn]=(1+α):(1-α):1 atomic ratio (-1≦α≦1), The line where the atomic ratio of In]:[M]:[Zn]=(1+α):(1-α):2 is n]:[M]:[Zn]=(1+α):(1-α):3, ]:[M]:[Zn]=(1+α):(1-α):4 atomic ratio line, and [ The line where the atomic ratio of In]:[M]:[Zn]=(1+α):(1-α):5 is shown. .

[0173] The dashed line indicates the atomic ratio of [In]:[M]:[Zn]=1:1:β (β≧0). The line where the atomic ratio of [In]:[M]:[Zn]=1:2:β is :[M]:[Zn]=1:3:β atomic ratio line, [In]:[M]:[Zn] = 1:4:β atomic ratio line, [In]:[M]:[Zn]=2:1:β atoms The line where the atomic ratio is [In]:[M]:[Zn]=5:1:β Represents in.

[0174] The dashed double-dashed line indicates the atomic number of [In]:[M]:[Zn]=(1+γ):2:(1-γ). The ratio (-1≦γ≦1) is shown. Oxides with an atomic ratio of [n] = 0:2:1 or a value close to that have a spinel-type crystal structure. Cheap.

[0175] 14(A) and 14(B) show the indium and An example of a preferred range of the atomic ratio of element M and zinc is shown.

[0176] As an example, FIG. 15 shows InMZnO, where [In]:[M]:[Zn]=1:1:1. 4. Also, Fig. 15 shows the crystal structure of InMZn when observed from a direction parallel to the b axis. The crystal structure of the layer containing M, Zn, and oxygen shown in FIG. The metal element in layer n) represents element M or zinc. In this case, element M and zinc The ratio of elements M and zinc is equal. The element M and zinc can be substituted, and the arrangement is irregular. .

[0177] InMZnO4 has a layered crystal structure (also called a layered structure), as shown in Figure 15. The layer containing indium and oxygen (hereinafter referred to as the In layer) is 1, while the element M, zinc, and The (M,Zn) layer containing oxygen is layer 2.

[0178] Indium and the element M can be substituted for each other. Therefore, the element M in the (M, Zn) layer M can be replaced with indium and expressed as an (In,M,Zn) layer. In that case, the In layer It has a layered structure with one layer and two (In,M,Zn) layers.

[0179] In the oxide with the atomic ratio of [In]:[M]:[Zn]=1:1:2, the In layer is 1 , (M, Zn) layer has 3 layers. That is, [Z When the oxide crystallizes, the ratio of the (M, Zn) layer to the In layer increases. Increase.

[0180] However, in the oxide, when the In layer is 1 and the (M, Zn) layer is a non-integer, I There may be multiple types of layered structures where the n layer is 1 and the (M, Zn) layer is an integer. For example, when [In]:[M]:[Zn]=1:1:1.5, the In layer is 1, and the (M A layered structure in which the number of (M,Zn) layers is two and a layered structure in which the number of (M,Zn) layers is three are mixed. It may be a structure.

[0181] For example, when forming an oxide film using a sputtering device, deviation from the atomic ratio of the target occurs. In particular, depending on the substrate temperature during film formation, the [Zn ], the [Zn] of the film may be smaller than that of the film.

[0182] In addition, multiple phases may coexist in an oxide (two-phase coexistence, three-phase coexistence, etc.). For example, At atomic ratios close to [In]:[M]:[Zn]=0:2:1, the spin Two phases, a flanking crystal structure and a layered crystal structure, tend to coexist. At atomic ratios close to the atomic ratio of [Zn]=1:0:0, bixbyite-type Two phases, a crystalline structure and a layered crystalline structure, tend to coexist. When multiple phases coexist in an oxide, In the case where grain boundaries are formed between different crystal structures, There is a match.

[0183] In addition, by increasing the indium content, the carrier mobility (electron mobility) of the oxide can be increased. This is mainly due to the fact that in oxides containing indium, element M and zinc, The s orbital of the heavy metal contributes to carrier conduction, and increasing the indium content As a result, the overlapping area of the s orbitals becomes larger, and oxides with a high indium content This is because the carrier mobility is higher compared to oxides with a lower indium content.

[0184] On the other hand, when the content of indium and zinc in the oxide is low, the carrier mobility is low. Therefore, the atomic ratio [In]:[M]:[Zn]=0:1:0 and its vicinity In the atomic ratio where the value is large (for example, region C shown in FIG. 14(C)), the insulating property becomes high.

[0185] Therefore, the oxide according to one embodiment of the present invention has a layer structure with high carrier mobility and few grain boundaries. It is preferable that the atomic ratio be that shown in region A in FIG. 14(A), which is likely to result in a structure.

[0186] Also, in region B shown in Figure 14(B), [In]:[M]:[Zn] = 4:2:3 to 4. 1 and its neighboring values. For example, the atomic ratio [In]:[M] :[Zn]=5:3:4. The oxides having the atomic ratio shown in region B are particularly It is an excellent oxide with high crystallinity and high carrier mobility.

[0187] The condition for an oxide to form a layered structure is not uniquely determined by the atomic ratio. The difficulty of forming a layered structure varies depending on the atomic ratio. However, depending on the formation conditions, a layered structure may or may not be formed. The regions shown are regions showing the atomic ratios in which the oxide has a layered structure, and are regions A to C. The boundary is not strict.

[0188] Next, the case where the oxide is used in a transistor will be described.

[0189] By using the above oxide in a transistor, carrier scattering at grain boundaries can be reduced. This allows realization of a transistor with high field effect mobility. Furthermore, a highly reliable transistor can be realized.

[0190] In addition, it is preferable to use an oxide with a low carrier density for the transistor. For example, The oxide has a carrier density of 8×10 11 / cm 3 Less than 1 x 10 11 / cm 3 less than 1×10 10 / cm 3Less than 1 x 10 -9 / cm 3 That's all Just do that.

[0191] In addition, high-purity intrinsic or substantially high-purity intrinsic oxides have fewer carrier generation sources. Therefore, the carrier density can be reduced. Since the oxide having the above structure has a low defect state density, the trap state density may also be low.

[0192] In addition, the charges trapped in the oxide trap levels take a long time to disappear. Therefore, oxides with high trap level density are A transistor having a channel region formed therein may have unstable electrical characteristics.

[0193] Therefore, in order to stabilize the electrical characteristics of the transistor, it is necessary to reduce the impurity concentration in the oxide. In order to reduce the impurity concentration in the oxide, it is effective to It is also preferable to reduce the concentration of impurities. Impurities include hydrogen, nitrogen, alkali metals, and alkali metals. These include alkaline earth metals, iron, nickel, and silicon.

[0194] Here, the influence of each impurity in the oxide will be explained.

[0195] When oxides contain silicon or carbon, which are elements of Group 14, Therefore, the concentration of silicon and carbon in the oxide and the The concentration of silicon and carbon near the interface was measured by secondary ion mass spectroscopy (SIMS). The concentration obtained by ion mass spectrometry) is calculated by 2 x 1 0 18 atoms / cm 3Less than or equal to 2 x 10 17 atoms / cm 3 The following .

[0196] In addition, if an oxide contains an alkali metal or alkaline earth metal, defect levels are formed, Therefore, alkali metals or alkaline earth metals may be included. Transistors using oxides containing SiO2 tend to be normally-on. It is preferable to reduce the concentration of alkali metals or alkaline earth metals in the product. is the concentration of alkali metals or alkaline earth metals in the oxide obtained by SIMS, 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 below To do so.

[0197] In addition, when nitrogen is contained in an oxide, electrons that act as carriers are generated, and the carrier density As a result, transistors using oxides containing nitrogen as semiconductors are Therefore, nitrogen should be contained as little as possible in the oxide. For example, the nitrogen concentration in the oxide is preferably reduced by SIMS. 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 below , more preferably 1 × 10 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 The following applies.

[0198] In addition, the hydrogen contained in the oxide reacts with the oxygen that bonds with the metal atoms to form water, so oxygen When hydrogen enters the oxygen vacancy, electrons, which act as carriers, are generated. In addition, some of the hydrogen atoms may bond with oxygen atoms that bond with metal atoms, forming carriers. Therefore, transistors using oxides containing hydrogen Therefore, hydrogen in the oxide is reduced as much as possible. Specifically, it is preferable that the hydrogen concentration of the oxide is measured by SIMS. , 1 x 10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Less than.

[0199] By using an oxide with sufficiently reduced impurities for the channel formation region of a transistor, It is possible to impart specific electrical properties.

[0200] Next, the case where the oxide has a two-layer structure or a three-layer structure will be described. The band diagram of the stacked structure of oxide S2 and oxide S3, and the insulator adjacent to the stacked structure. , the stacked structure of oxide S2 and oxide S3, and the band diagram of the insulator in contact with the stacked structure. , will be explained using FIG.

[0201] FIG. 16(A) shows the structure of an insulator I1, an oxide S1, an oxide S2, an oxide S3, and an insulator I2 FIG. 16(B) is an example of a band diagram in the film thickness direction of a laminated structure having an insulator I 1. Band diagram in the thickness direction of a stacked structure consisting of oxide S2, oxide S3, and insulator I2 In order to make it easier to understand, the band diagram is divided into insulator I1, oxide S1, and oxide The energy levels (Ec) of the conduction band minimum of the material S2, oxide S3, and insulator I2 are shown.

[0202] The oxides S1 and S3 have a lower energy level at the conduction band near the vacuum level than the oxide S2. The energy level of the conduction band minimum of oxide S2 is close to that of oxide S1 and oxide S2. The difference between the energy level of the conduction band minimum of 3 is 0.15 eV or more, or 0.5 eV or more, and preferably 2 eV or less, or 1 eV or less. The difference between the electron affinity of the substance S3 and the electron affinity of the oxide S2 is 0.15 eV or more, or 0 It is preferably 0.5 eV or more and 2 eV or less, or 1 eV or less.

[0203] As shown in FIGS. 16(A) and 16(B), oxide S1, oxide S2, oxide S3 In other words, the energy level at the bottom of the conduction band changes smoothly. In order to have such a band diagram, the oxide The oxide S1 is formed at the interface between the oxide S2 and the oxide S3, or at the interface between the oxide S2 and the oxide S3. It is preferable to lower the defect level density of the mixed layer to be formed.

[0204] Specifically, oxides S1 and S2, and oxides S2 and S3 have common elements other than oxygen. By having the element (as the main component), it is possible to form a mixed layer with a low defect level density. For example, if oxide S2 is In-Ga-Zn oxide, oxide S1 and oxide S3 are , In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide, etc. may be used.

[0205] At this time, the main carrier path is oxide S2. The interface between oxide S1 and oxide S2 , and the defect state density at the interface between the oxide S2 and the oxide S3 can be reduced. Therefore, the effect of interface scattering on carrier conduction is small, resulting in a high on-current.

[0206] When electrons are captured in the trap level, the captured electrons behave like fixed charges. Therefore, the threshold voltage of the transistor is shifted in the positive direction. By providing S3, the trap level can be kept away from the oxide S2. By forming the transistor in this manner, the threshold voltage of the transistor is prevented from shifting in the positive direction. It is possible.

[0207] The oxide S1 and the oxide S3 are made of materials having sufficiently low electrical conductivity compared to the oxide S2. At this time, the oxide S2, the interface between the oxide S2 and the oxide S1, and the oxide S2 and the oxide S The interface with oxide S1 and oxide S3 mainly functions as a channel region. In FIG. 14(C), it is preferable to use an oxide having an atomic ratio shown in region C where the insulating property is high. In addition, the region C shown in FIG. 14(C) is [In]:[M]:[Zn]=0:1:0, or The atomic ratio is shown as a value close to the atomic ratio.

[0208] In particular, when oxide S2 is an oxide having an atomic ratio shown in region A, oxide S1 and The oxide S3 is an oxide having an [M] / [In] ratio of 1 or more, preferably 2 or more. In addition, it is preferable that the oxide S3 has a sufficiently high insulating property. It is preferable to use an oxide in which ([Zn]+[In]) is 1 or more.

[0209] The insulator 66a, the semiconductor 66b, and the insulator 66c are formed by sputtering, CVD, or MB. The film can be formed by the E method, PLD method, ALD method, or the like.

[0210] The insulator 66a, the semiconductor 66b, and the insulator 66c are subjected to a substrate heating process during film formation. It is preferable to perform heat treatment after the film formation. 66a, semiconductor 66b, insulator 66c, etc. In addition, excess oxygen can be supplied to the insulator 106a and the semiconductor 106b. The heat treatment is carried out at a temperature of 250°C to 650°C, preferably 300°C to 400°C. The heat treatment may be carried out at a temperature of 50°C or less, more preferably 350°C to 400°C. Active gas atmosphere or oxidizing gas containing 10 ppm or more, 1% or more, or 10% or more The heat treatment may be carried out under reduced pressure or in an inert gas atmosphere. After heat treatment in the atmosphere, oxidizing gas is added at 10 ppm or more, 1% to compensate for the oxygen that has been removed. The heat treatment may be carried out in an atmosphere containing 10% or more of fluorine. The heat treatment using an RTA device is shorter than that using a furnace. This is effective in increasing productivity because it requires only a small amount of time.

[0211] The conductor 62a serving as the back gate of the transistor, the plug and wiring shown in FIG. When tantalum nitride is used as the metal 20a containing nitrogen, the heat treatment temperature is The temperature may be set to 350°C or higher and 410°C or lower, preferably 370°C or higher and 400°C or lower. By performing heat treatment in this temperature range, the release of hydrogen from the tantalum nitride film is suppressed. can.

[0212] Also, the semiconductor 66b or the insulator 66c or the like is in contact with the conductor 68a or the conductor 68b. A low resistance region may be formed in the region where the semiconductor 66b is in contact. Oxygen is extracted by the conductor 68a or the conductor 68b, or the conductor 68a or the conductor The conductive material contained in the body 68b is formed by bonding with elements in the semiconductor 66b. By forming such a low resistance region, the conductor 68a or the conductor 68b and the semiconductor Since the contact resistance with the substrate 66b can be reduced, the on-current of the transistor 60a can be reduced. It can be increased.

[0213] The semiconductor 66b has a conductor 68a and a conductor 68b between the conductors 68a and 68b. The conductors 68a and 8b may have a region that is thinner than the region that overlaps them. When forming the conductor 68b, a part of the upper surface of the semiconductor 66b is removed. On the upper surface of the semiconductor 66b, a conductor film is formed to become the conductor 68a and the conductor 68b. When the resistance of the low-resistance region is increased, a region with a low resistance similar to the low-resistance region may be formed. By removing the region located between the conductors 68a and 68b on the top surface of the semiconductor 66b, This makes it possible to prevent a channel from being formed in a low resistance region on the top surface of the semiconductor 66b. Cut.

[0214] The above-described three-layer structure of the insulator 66a, the semiconductor 66b, and the insulator 66c is an example. For example, a two-layer structure may be used in which either the insulator 66a or the insulator 66c is not provided. Alternatively, a single layer structure may be used in which neither the insulator 66a nor the insulator 66c is provided. Alternatively, the insulator, semiconductor or the like exemplified as the insulator 66a, the semiconductor 66b or the insulator 66c may be used. Alternatively, the layer may have an n-layer structure (n is an integer of 4 or more) having either a metal or a conductor.

[0215] <Insulators, conductors> The components of the transistor 60a other than the semiconductor will be described in detail below.

[0216] The insulators 59 and 61 are made of an insulator having a function of blocking hydrogen or water. The hydrogen and water in the insulators provided near the insulator 66a, the semiconductor 66b, and the insulator 66c Insulator 66a, semiconductor 66b, and insulator 66c function as oxide semiconductors. This may result in a decrease in the reliability of the transistor 60a. In particular, when silicon or the like is used for the semiconductor substrate 91, the dummy Since hydrogen is used to terminate the ring bonds, the hydrogen has an oxide semiconductor. There is a risk that hydrogen or water may diffuse into the transistors. By providing the insulators 59 and 61 having the function, the transistor having the oxide semiconductor can be The present invention suppresses the diffusion of hydrogen or water from the lower layer of a transistor having an oxide semiconductor. The insulators 59 and 61 can be replaced by the insulators 65 and 66. Preferably, the insulating layer 62 is less permeable to hydrogen or water than the insulating layer 64 .

[0217] In addition, it is preferable that the insulators 59 and 61 also have a function of blocking oxygen. The insulators 59 and 61 block oxygen diffusing from the insulator 64, By effectively supplying oxygen from the insulator 64 to the insulator 66a, the semiconductor 66b, and the insulator 66c, This can be done.

[0218] The insulators 59 and 61 may be made of, for example, aluminum oxide or aluminum oxynitride. gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, oxide Hafnium, hafnium oxynitride, etc. can be used. Preferably, the insulator 59 is A The insulating layer 59 is formed by the LD method, and the insulating layer 61 is formed by the sputtering method. and by using it as an insulator 61, it has the effect of blocking the diffusion of oxygen, hydrogen or water. In addition, the insulators 59 and 61 can function as insulating films that exhibit the effect. For example, silicon nitride, silicon nitride oxide, etc. can be used for the insulating layer. By using it as a material 59 and an insulator 61, it is possible to block the diffusion of hydrogen and water. The insulators 59 and 61 can function as insulating films. It can be performed using the sputtering method, CVD method, MBE method, PLD method, ALD method, etc. can.

[0219] The insulator 67 may be, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, or aluminum. aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, A single layer of insulator containing zirconium, lanthanum, neodymium, hafnium or tantalum The insulator 67 may be formed by a sputtering method, a CVD method, or the like. The deposition can be carried out by using an MBE method, a PLD method, an ALD method, or the like.

[0220] At least a portion of the conductor 62a and the conductor 62b is sandwiched between the conductor 68a and the conductor 68b. It is preferable that the conductor 62a and the semiconductor 66b overlap in the area where the conductor 62a and the semiconductor 66b are included. 2b functions as the back gate of the transistor 60a. and the conductor 62b are provided to control the threshold voltage of the transistor 60a. By controlling the threshold voltage, the gate ( When the voltage applied to the conductor 74 is low, for example, when the applied voltage is below 0 V, This prevents the transistor 60a from being turned on. This makes it easier to shift the electrical characteristics of the transistor in the direction of normally-off.

[0221] Furthermore, the conductors 62a and 62b functioning as back gates are supplied with a predetermined potential. For example, the conductor 62a and the conductor 6 2b may be connected to a wiring to which a constant potential is supplied. The constant potential may be a high power supply potential. or a low power supply potential such as ground potential.

[0222] The conductor 62a may be any conductor that can be used for the nitrogen-containing metal. The conductor 62b may be any conductor that can be used for the conductor 21.

[0223] The insulator 65 is provided to cover the conductors 62a and 62b. An insulator similar to the insulator 64 or the insulator 72 described below can be used.

[0224] The insulator 63 is provided so as to cover the insulator 65. The insulator 63 has a function of blocking oxygen. By providing such an insulator 63, it is preferable that the insulator 64 has a conductive property. This prevents the current collector 62a and the current collector 62b from extracting oxygen. By effectively supplying oxygen from the insulator 64 to the insulator 66a, the semiconductor 66b, and the insulator 66c, In addition, by increasing the covering property of the insulator 63, it is possible to draw more from the insulator 64. The amount of oxygen removed is further reduced, and the insulator 64 is divided into the insulator 66a, the semiconductor 66b, and the insulator 66c. This allows oxygen to be supplied more effectively to the

[0225] The insulator 63 may be boron, aluminum, silicon, scandium, titanium, gallium, or the like. Aluminum, yttrium, zirconium, indium, lanthanum, cerium, neodymium, hafnium The oxide or nitride containing hafnium or thallium is preferably used. Alternatively, aluminum oxide is used. The insulator 63 is formed by a method such as sputtering or CV. This can be done using the D method, MBE method, PLD method, ALD method, or the like.

[0226] In the insulators 65, 63, and 64, the insulator 63 forms an electron capture region. It is preferable that the insulators 65 and 64 have a function of suppressing electron emission. When the electrons are trapped in the insulator 63, they behave like fixed negative charges. 63 functions as a floating gate.

[0227] The insulator 64 preferably has a small amount of water or hydrogen contained in the film. The body 64 may be, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, or the like. Umium, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zinc Insulators containing lanthanum, neodymium, hafnium or tantalum are used in single or double layers. For example, the insulator 64 may be aluminum oxide, magnesium oxide, or the like. Sium, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide ammonium, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, nickel oxide Oxygen, hafnium oxide, or tantalum oxide may be used. Preferably, silicon oxide is used. Alternatively, silicon oxynitride is used. The insulator 64 is formed by a sputtering method, a CV method, or the like. This can be done using the D method, MBE method, PLD method, ALD method, or the like.

[0228] In addition, the insulator 64 is preferably an insulator having excess oxygen. 4, the oxide is transferred from the insulator 64 to the insulator 66a, the semiconductor 66b, and the insulator 66c. The oxygen can be supplied to the insulator 66a, which is an oxide semiconductor, and the semiconductor This reduces oxygen deficiencies that can cause defects in the insulating layer 66b and the insulating layer 66c. The body 66a, the semiconductor 66b, and the insulator 66c are oxidized to have stable properties with low defect level density. The material may be a semiconductor.

[0229] In this specification and the like, excess oxygen refers to, for example, oxygen contained in excess of the stoichiometric composition. Alternatively, the excess oxygen refers to a film containing the excess oxygen, for example, by heating. Excess oxygen is oxygen released from the membrane or layer. The movement of excess oxygen can occur between atoms in the film or layer, or between oxygen atoms that make up the film or layer. In some cases, the two move in a domino effect, replacing each other.

[0230] The insulator 64 having excess oxygen was analyzed by thermal desorption spectroscopy (TDS analysis) at 100°C. Desorption of oxygen molecules in the surface temperature range of 700°C or 100°C to 500°C The amount is 1.0 x 10 14 molecules / cm 2 Over 1.0 x 10 16 molecul es / cm 2 or less, more preferably 1.0 × 10 15 molecules / cm 2 End 5.0×10 15 molecules / cm 2 The following is the result.

[0231] The method for measuring the amount of released molecules using TDS analysis is explained below, taking the amount of released oxygen as an example. explain.

[0232] The total amount of gas released when the measurement sample is subjected to TDS analysis is calculated based on the integral value of the ion intensity of the released gas. Then, by comparison with a standard sample, the total amount of gas released can be calculated.

[0233] For example, the TDS analysis results of a silicon substrate containing a predetermined density of hydrogen as a standard sample, and From the TDS analysis results of the measurement sample, the amount of released oxygen molecules (N O2 ) is expressed as Here, the gas detected with a mass-to-charge ratio of 32 obtained by TDS analysis is We assume that all of the carbon atoms are derived from oxygen molecules. The mass-to-charge ratio of CH3OH is 32, but The possibility is low and is not considered here. The abundance ratio of oxygen atoms and oxygen molecules containing oxygen atoms with mass number 18 in nature is The rate is so small that it is not taken into consideration.

[0234] where N O2 =N H2 / S H2 ×S O2 Let it be ×α.

[0235] N H2 is the density converted value of hydrogen molecules desorbed from the standard sample. H2 is a standard test The integral value of the ion intensity when the sample is subjected to TDS analysis. H2 / S H2 Let's say S O2 is the integral value of the ion intensity when the measurement sample is subjected to TDS analysis. α is a coefficient that affects the ion intensity in TDS analysis. For details, see Japanese Patent Laid-Open Publication No. 6-275697. A thermal desorption analyzer EMD-WA1000S / W manufactured by NIMS Corporation was used. Measurements are performed using a silicon substrate containing a fixed amount of hydrogen atoms.

[0236] In addition, some of the oxygen is detected as oxygen atoms in TDS analysis. The ratio of the oxygen molecules can be calculated from the ionization rate of the oxygen molecules. Since the ionization rate of oxygen atoms is included in the calculation, the amount of oxygen atoms released can be estimated by evaluating the amount of oxygen molecules released. It can also be estimated.

[0237] In addition, N O2 is the amount of released oxygen molecules. The amount of released oxygen atoms is This is twice the amount released.

[0238] Alternatively, an insulator that releases oxygen upon heat treatment may contain peroxide radicals. Specifically, the spin density due to peroxide radicals is 5×10 17 spins / cm 3 Insulators containing peroxide radicals can be analyzed by electron spin resonance (ES) R: Electron Spin Resonance (G) shows a g value near 2.01. It may also have symmetrical signals.

[0239] The insulator 64 or the insulator 63 has a function of preventing the diffusion of impurities from the lower layer. Good too.

[0240] As mentioned above, it is preferable that the upper or lower surface of the semiconductor 66b is highly flat. Therefore, the top surface of the insulator 64 is subjected to a planarization process such as CMP to improve the flatness. That's fine.

[0241] Conductor 68a and conductor 68b are the source or drain electrodes of transistor 60a, respectively. It functions as one of the rain electrodes.

[0242] The conductors 68a and 68b may include, for example, boron, nitrogen, oxygen, fluorine, silicon, etc. Copper, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc , Gallium, Yttrium, Zirconium, Molybdenum, Ruthenium, Silver, Indium, Conductors containing one or more of tin, tantalum, and tungsten are used in a single layer or multilayer. For example, when the conductor 68a and the conductor 68b have a laminated structure, tantalum nitride Alternatively, tungsten may be laminated on the conductor 68a. 8b may be, for example, an alloy or compound, and may be a conductor including aluminum, copper, and titanium. Conductors containing tin, conductors containing copper and manganese, conductors containing indium, tin and oxygen Conductor 68a and conductor containing titanium and nitrogen may be used. The dielectric 68b is formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. This can be done using, for example.

[0243] The insulator 72 functions as a gate insulating film for the transistor 60a. The insulator 72 may be an insulator having excess oxygen, similar to the insulator 64. As a result, oxygen is supplied from the insulator 72 to the insulator 66a, the semiconductor 66b, and the insulator 106. It is possible.

[0244] The insulators 72 and 77 may be, for example, boron, carbon, nitrogen, oxygen, fluorine, or magnesium. Sium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, Insulation containing tritium, zirconium, lanthanum, neodymium, hafnium or tantalum For example, the insulators 72 and 77 may be made of: Aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide Silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide tungsten oxide, lanthanum oxide, neodymium oxide, hafnium oxide or tantalum oxide may be used. The insulators 72 and 77 may be formed by sputtering, CVD, MBE, or the like. Alternatively, the PLD method, the ALD method, or the like can be used.

[0245] In addition, the insulator 77 is preferably an insulator having excess oxygen. By providing the insulator 77, the oxide is transferred from the insulator 77 to the insulator 66a, the semiconductor 66b, and the insulator 66c. The oxygen can be supplied to the insulator 66a, which is an oxide semiconductor, and the semiconductor This reduces oxygen deficiencies that can cause defects in the insulating layer 66b and the insulating layer 66c. The body 66a, the semiconductor 66b, and the insulator 66c are oxidized to have stable properties with low defect level density. The material may be a semiconductor.

[0246] The insulator 77 with excess oxygen was analyzed by thermal desorption spectroscopy (TDS) at 100°C. Desorption of oxygen molecules in the surface temperature range of 700°C or 100°C to 500°C The amount is 1.0 x 10 14 molecules / cm 2 Over 1.0 x 10 16 molecul es / cm 2 or less, more preferably 1.0 × 10 15 molecules / cm 2 End 5.0×10 15 molecules / cm 2 The following is the result.

[0247] Insulator 77 also contains hydrogen, water, and nitrogen oxides (NO x , such as nitric oxide, nitrogen dioxide, etc. It is preferable that the amount of impurities such as ) is small. By using such an insulator 77, Impurities such as hydrogen, water, and nitrogen oxides are released from the insulator 77 to the insulator 66a, the semiconductor 66b, and the insulator The diffusion of the semiconductor 66b into the semiconductor 66c is suppressed, and the semiconductor 66b has a low defect level density and stable characteristics. The oxide semiconductor can be an oxide semiconductor.

[0248] Here, the insulator 77 is subjected to TDS analysis in the surface temperature range of 200°C to 560°C. The number of H2O molecules released is 3.80 × 10 15 molecules / cm 2 The following is more preferred: 2.40 x 10 15 molecules / cm 2 The insulator 77 is as follows: TDS analysis showed that the amount of H2O molecules desorbed was 7. 00×10 14molecules / cm 2 It is more preferable that the following is true: TDS analysis of the compound 77 showed that the amount of NO2 molecules desorbed was 1.80 x 10 13 molecule s / cm 2 It is preferable that the following be true:

[0249] Conductor 74 functions as the gate electrode of transistor 60a or 60b. Examples of the elements include boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, and titanium. chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zinc Copper, molybdenum, ruthenium, silver, indium, tin, tantalum and tungsten A conductor containing one or more kinds of fluorine may be used in a single layer or a multilayer structure. In the case of a laminated structure, tungsten may be laminated on tantalum nitride. The conductor 74 may be, for example, an alloy or a compound, and may be a conductor containing aluminum, copper, or the like. and titanium-containing conductors, copper and manganese-containing conductors, indium, tin and oxide Conductors containing titanium and nitrogen may also be used. The film is formed using the sputtering method, CVD method, MBE method, PLD method, ALD method, etc. This can be done.

[0250] Preferably, a conductor is formed by sputtering on a tantalum nitride film formed by, for example, the ALD method. A two-layer structure may be used. Tantalum nitride is deposited by the ALD method in the area in contact with the gate insulating film. Therefore, the insulator 72 that functions as a gate insulating film is not damaged. Furthermore, the high resistivity near the surface of tantalum nitride film formed by ALD method The area is then removed by reverse sputtering, and tantalum nitride or Alternatively, a multilayer structure can be formed by depositing a film of tungsten or the like. This is preferable because it reduces damage to the insulator 72 caused by the sputtering method. The removal of high resistance regions by sputtering and the deposition of films by sputtering can be performed using the same equipment. can.

[0251] Here, as shown in FIG. 12(C), the conductors 62a, 62b, and 74 The electric field of the semiconductor 66b can electrically surround the semiconductor 66b (the electric field generated by the conductor The structure of the transistor that electrically surrounds the semiconductor is called the surrounded c This is called the s-channel structure.) Therefore, the entire semiconductor 66b ( In the s-channel structure, the transistor is A large current can be passed between the source and drain of the transistor, and the current (on-state current) when the transistor is turned on is increased. It can be made easier.

[0252] When the transistor has an s-channel structure, the transistor is also formed on the side surface of the semiconductor 66b. Therefore, the thicker the semiconductor 66b, the larger the channel region. That is, the thicker the semiconductor 66b, the higher the on-current of the transistor. The thicker the semiconductor 66b, the greater the proportion of the region with high carrier controllability. For example, the threshold swing value can be reduced to 10 nm or more, preferably 2 If the semiconductor 66b has a region with a thickness of 0 nm or more, more preferably 30 nm or more, However, productivity of semiconductor devices may decrease, so for example, The semiconductor 66b may have a thickness of 1000 .mu.m.

[0253] Because it can achieve high on-state current, the s-channel structure is suitable for miniaturized transistors. Since the transistor can be miniaturized, a semiconductor having the transistor can be The device can be a highly integrated, high density semiconductor device. The transistor preferably has a channel length of 40 nm or less, more preferably 30 nm or less. More preferably, the transistor has a region of 20 nm or less, and the channel width is preferably Preferably, the thickness is 40 nm or less, more preferably 30 nm or less, and even more preferably 20 nm or less. It has.

[0254] It is preferable to provide an insulator 79 that can be used for the insulator 63. For example, , gallium oxide or aluminum oxide formed by ALD as the insulator 79 By providing such an insulator 79 to cover the conductor 74, the insulator The conductor 74 takes away excess oxygen supplied to 77, preventing the conductor 74 from being oxidized. can be done.

[0255] The thickness of the insulator 78 can be, for example, 5 nm or more, or 20 nm or more. In addition, it is preferable that at least a portion of the insulator 78 be formed in contact with the upper surface of the insulator 77. It's nice.

[0256] The insulator 78 may be, for example, carbon, nitrogen, oxygen, fluorine, magnesium, or aluminum. , silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconia Insulators containing sulphur, lanthanum, neodymium, hafnium or tantalum, either in a single layer or The insulator 78 may be oxygen, hydrogen, water, an alkali metal, an alkaline earth metal, or the like. It is preferable that the insulating material has the effect of blocking the above-mentioned. The nitride insulating film can be made of silicon nitride, silicon oxynitride, or the like. Aluminum nitride, aluminum oxide nitride, etc. are used instead of nitride insulating films. An oxide insulating film having a blocking effect against oxygen, hydrogen, water, and the like may be provided on the insulating film. The insulating film may be aluminum oxide, aluminum oxynitride, gallium oxide, or gallium oxynitride. Sodium, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride The insulator 78 may be used as the insulator 66a or the insulator 66c. The insulator 78 can be formed by sputtering. The deposition can be carried out by using a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0257] Here, the insulator 78 is preferably formed by sputtering. It is more preferable to perform the sputtering under an insulating atmosphere. By forming the insulator 78, the surface of the insulator 77 (after the insulator 78 is formed) is simultaneously formed. Oxygen is added to the vicinity of the interface between the insulator 77 and the insulator 78. For example, by sputtering, Then, an aluminum oxide film can be formed on the aluminum oxide film by the ALD method. By using the ALD method, it is possible to prevent the formation of pinholes. Therefore, oxygen, hydrogen, water, alkali metals, alkaline earth metals, etc. of the insulator 78 can be suppressed. This can further improve the blocking effect.

[0258] It is preferable to perform heat treatment during or after the formation of the insulator 78. By performing heat treatment, oxygen added to the insulator 77 is diffused, and the insulator 66a and the semiconductor The oxygen can be supplied to the insulator 66b and the insulator 66c. 72 or the insulator 64 to the insulator 66a, the semiconductor 66b, and the insulator 66c. The heat treatment is carried out at a temperature of 250°C to 650°C, preferably 350°C to 450°C. The heat treatment should be carried out in an inert gas atmosphere or in an atmosphere containing oxidizing gas at a concentration of 10 ppm or less. The heat treatment is carried out in an atmosphere containing 1% or more or 10% or more of the above. The heat treatment may be carried out under reduced pressure. Heat treatment can also be performed using an RTA device that uses lamp heating.

[0259] The conductor 62a serving as the back gate of the transistor, the plug and the When tantalum nitride is used for the metal 20a containing nitrogen that constitutes the wiring, the above heat treatment The temperature may be set to 350°C or higher and 410°C or lower, preferably 370°C or higher and 400°C or lower. By performing heat treatment in this temperature range, hydrogen is released from tantalum nitride. It can be suppressed.

[0260] The insulator 78 is an insulator that is less permeable to oxygen than the insulator 77, and blocks oxygen. By providing such an insulator 78, the insulator 77 When oxygen is supplied from the insulating layer 66a to the semiconductor layer 66b and the insulating layer 66c, the oxygen This can prevent the heat from being released to the outside above the edge 78.

[0261] Aluminum oxide is permeable to both impurities such as hydrogen and moisture, and oxygen. It is preferable to apply it to the insulator 78 because it has a high blocking effect of preventing the passage of the gas.

[0262] <Capacitor element configuration> 17A shows an example of the configuration of a capacitor 80a. The capacitor 80a includes a conductor 82 and The insulating material 81 has an insulator 83 and a conductor 84. As shown in FIG. A conductor 82 is provided on the surface, and an insulator 83 is provided to cover the conductor 82. A conductor 84 is provided to cover the conductor 84, and an insulator 85 is provided on the conductor 84.

[0263] Here, the insulator 83 is provided so as to contact the side surface of the conductor 82, and the conductor 84 is provided so as to contact the side surface of the insulator 82. It is preferable that the conductive material 82 is provided so as to contact the side surface of the protrusion 3. Since not only the surface but also the side surface of the conductor 82 can function as a capacitance element, the capacitance value can be made larger.

[0264] The conductors 82 and 84 may be, for example, boron, nitrogen, oxygen, fluorine, or silicon. , phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium Sodium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin When a conductor containing one or more of tantalum and tungsten is used in a single layer or a multilayer, For example, the material may be an alloy or compound, and may be a conductor containing aluminum, copper, and titanium. Conductors containing tin, conductors containing copper and manganese, conductors containing indium, tin and oxygen Conductor 82 and conductor containing titanium and nitrogen may be used. The film 84 is formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. This can be done using

[0265] The insulator 83 may be, for example, aluminum oxide, aluminum oxynitride, or magnesium oxide. silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide , germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide Use an insulator containing one or more selected from zinc oxide, hafnium oxide, tantalum oxide, etc. For example, silicon oxynitride may be laminated on aluminum oxide. Hafnium Silicate (HfSi x O y (x>0, y>0)), nitrogen-doped hafnium HfSi x O y N z (x>0, y>0, z>0)), nitrogen added Hafnium aluminate (HfAl x O y N z (x>0, y>0, z>0)), oxide haf It is preferable to use a high-k material such as tungsten or yttrium oxide. When a high-k material is used as the insulator 83, the capacitance value can be increased by heat treatment. By using such high-k materials, it is possible to Even if the insulator 83 is made thick, the capacitance value of the capacitive element 80a can be sufficiently secured. This makes it possible to suppress leakage current occurring between the conductor 82 and the conductor 84. The insulator 83 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or the like. This can be done using an ALD method or the like.

[0266] The insulators 81 and 85 are made of an insulator that can be used as the insulator 77. The insulator 85 may be an organic silane gas (for example, TEOS (Tetra-Ethylene Oxide)). Alternatively, a film may be formed using tetraethyl-ortho-silicate, etc.

[0267] Next, modified examples of the capacitive element 80a will be described with reference to FIGS. 17(B) and 17(C).

[0268] The capacitance element 80b shown in FIG. 17(B) is formed so that the conductor 84 overlaps the upper surface of the conductor 82. 17(A) in that it is configured as follows. In B), the side edge of the conductor 84 and the side edge of the conductor 82 are arranged to overlap. However, the capacitive element 80b is not limited to this.

[0269] The capacitance element 80c shown in FIG. 17(C) is provided with an insulator 86 having an opening on an insulator 81. The conductor 82 is provided in the opening, which is the same as that shown in FIG. Here, the opening of the insulator 86 and the upper surface of the insulator 81 are regarded as a groove. It is preferable that the conductor 82 is provided along the groove. As shown in (C), the upper surface of the insulator 86 is formed so as to be roughly aligned with the upper surface of the conductor 82. This may be done.

[0270] An insulator 83 is provided on the conductor 82, and a conductor 84 is provided on the insulator 83. In this case, the conductor 84 has a region facing the conductor 82 via the insulator 83 in the groove. In addition, the insulator 83 is preferably provided so as to cover the upper surface of the conductor 82. By providing the insulator 83 in this way, a leakage current flows between the conductor 82 and the conductor 84. In addition, the side edge of the insulator 83 and the side edge of the conductor 84 are approximately In this way, the capacitive element 80c may be of a concave or It is preferable that the capacitor element 80c has a conductive shape such as a rectangular shape or a cylindrical shape. The top surfaces of the insulator 82, the insulator 83, and the conductor 84 may have a polygonal shape other than a square. Alternatively, it may be a circular shape including an ellipse.

[0271] <Configuration of transistors formed on a semiconductor substrate> 18(A) and 18(B) show transistors included in an element layer having a semiconductor substrate. 18A shows an example of the configuration of the transistor 90a. 18B is a cross-sectional view corresponding to the channel width direction B3 of the transistor 90a. FIG. 10 is a cross-sectional view corresponding to line B4.

[0272] A plurality of protrusions are formed on the semiconductor substrate 91, and grooves (called trenches) are formed between the protrusions. An element isolation region 97 is formed in the semiconductor substrate 91. An insulator 94 is formed on the region 97, and a conductor 96 is formed on the insulator 94. An insulator 95 is formed in contact with the side surfaces of the insulator 94 and the conductor 96. An insulator 99 is provided on the substrate 91, the element isolation region 97, the insulator 95, and the conductor 96. An insulator 98 is provided on top of the insulating material.

[0273] As shown in FIG. 18A, at least the insulator 9 is formed on the protruding portion of the semiconductor substrate 91. The low resistance region 93a and the low resistance region 93b are formed so as to overlap with a part of the low resistance region 5. The low resistance region 92a and the low resistance region 92b are formed outside the low resistance region 93a and the low resistance region 93b. The low resistance region 92a and the low resistance region 92b are formed by the low resistance region 93a and the low resistance region 93b. It is preferable that the resistance is lower than that of the resistive region 93b.

[0274] Here, conductor 96 serves as the gate of transistor 90a, and insulator 94 serves as the gate of transistor 90b. The low-resistance region 92a functions as the source insulating film of the transistor 90a. low-resistance region 92b serves as either the source or drain of transistor 90a; The insulator 95 functions as the other of the drains of the transistor 90a. The low resistance region 93a and the low resistance region 93b function as a wall insulating film. The LDD (Lightly Doped Drain) region of the transistor 90a is In addition, in the convex portion of the semiconductor substrate 91, the conductor 96 overlaps and the low resistance region 93a and the region located between the low-resistance region 93b is a channel forming region of the transistor 90a. It functions as:

[0275] In the transistor 90a, as shown in FIG. 18B, the protrusions in the channel forming region The side and top portions of the conductor 96 overlap with the insulator 94 sandwiched therebetween, forming a channel. Carriers flow over a wide area, including the sides and top of the region. The area occupied by the transistor 90a on the substrate is kept small while the moving As a result, the amount of carriers in the transistor 90a increases. In particular, the convex portion in the channel forming region is The length of the channel width direction (channel width) of the part is W, and the height of the convex part in the channel formation region is If T is the aspect ratio, which corresponds to the ratio of the height T of the convex part to the channel width W (T / W), When θ is high, the range over which carriers can flow is wider, so the on-current of transistor 90a For example, the field effect mobility can be increased by In the case of the transistor 90a using the solid substrate 91, the aspect ratio is required to be 0.5 or more. It is preferable that the number be 1 or more, and more preferable that the number be 1 or more.

[0276] The transistor 90a shown in FIGS. 18A and 18B is formed by trench isolation (STI). This shows an example of element isolation using low trench isolation. The semiconductor device described in this embodiment mode is not limited to this.

[0277] The semiconductor substrate 91 may be, for example, a single semiconductor substrate such as silicon or germanium, or are silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, A semiconductor substrate such as gallium oxide may be used. Preferably, the semiconductor substrate 91 is A single crystal silicon substrate is used. The semiconductor substrate 91 has an insulating region inside. A semiconductor substrate having a region, such as an SOI (Silicon On Insulator) substrate A plate or the like may also be used.

[0278] The semiconductor substrate 91 is, for example, a semiconductor substrate containing impurities that impart p-type conductivity. However, the semiconductor substrate 91 is a semiconductor substrate containing impurities that impart n-type conductivity. Alternatively, the semiconductor substrate 91 may be an i-type.

[0279] The low resistance region 92a and the low resistance region 92b provided in the semiconductor substrate 91 are formed of phosphorus or Elements that provide n-type conductivity, such as arsenic, or p-type conductivity, such as boron or aluminum Similarly, the low resistance region 93a and the low resistance region 94b preferably contain an element that imparts electrical conductivity. Region 93b is also formed by an element that provides n-type conductivity, such as phosphorus or arsenic, or by an element such as boron or aluminum. It is preferable that the low resistance region 93a contains an element that provides p-type conductivity, such as ruthenium. Since it is preferable that the low resistance region 93b functions as an LDD, the low resistance region 93a The concentration of the element that provides conductivity contained in the low resistance region 93b is and is preferably lower than the concentration of the element that provides conductivity contained in the low-resistance region 92b. The low resistance region 92a and the low resistance region 92b may be formed using silicide or the like. stomach.

[0280] The insulators 94 and 95 are made of, for example, aluminum oxide, aluminum oxynitride, or aluminum oxide. magnesium, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, oxide Gallium, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, acid The insulator contains one or more selected from neodymium oxide, hafnium oxide, tantalum oxide, etc. In addition, hafnium silicate (HfSi x O y (x>0, y>0) Nitrogen-doped hafnium silicate (HfSi x O y N z (x>0, y>0, z>0 )), nitrogen-doped hafnium aluminate (HfAl x O y N z (x>0, y>0 , z>0), hafnium oxide, or yttrium oxide. The insulators 94 and 95 may be formed by a sputtering method, a CVD method, an MB method, or the like. This can be carried out using the E method, PLD method, ALD method, or the like.

[0281] The conductor 96 may be tantalum, tungsten, titanium, molybdenum, chromium, niobium, or the like. or an alloy material or compound material containing these metals as the main component. It is also preferable to use polycrystalline silicon doped with impurities such as phosphorus. In addition, the conductor 96 may be formed by laminating a metal film containing nitrogen and the above metal film. As metals containing nitrogen, tungsten nitride, molybdenum nitride, and titanium nitride are used. By providing a metal film containing nitrogen, the adhesion of the metal film can be improved. The conductor 96 can be formed by sputtering. The deposition can be carried out by using a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0282] The insulators 98 and 99 may be, for example, boron, carbon, nitrogen, oxygen, fluorine, ma, or the like. Magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium , including yttrium, zirconium, lanthanum, neodymium, hafnium or tantalum The insulator may be a single layer or a stacked layer. The deposition can be carried out by using a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0283] As the insulator 98, silicon carbonitride e), silicon oxycarbide, etc. can be used. Also, USG (Undoped Silicate Glass), BPSG ( Boron Phosphorus Silicate Glass), BSG(Bor USG, BPSG, etc. are usually It can be formed by using a high pressure CVD method. For example, HSQ (hydrogen silsesquioxane) Alternatively, the above may be formed by using a coating method.

[0284] However, it may be preferable for the insulator 99 to contain hydrogen. The insulator 99 contains hydrogen, and thus the semiconductor The substrate 91 may reduce defects and improve the characteristics of the transistor 90a. When a material containing silicon is used as the semiconductor substrate 91, hydrogen damages the silicon. Defects such as ring bonds can be terminated.

[0285] Next, a modification of the transistor 90a will be described with reference to FIGS. 18(C) and (D) show the channel of the transistor 90a in the same manner as in FIGS. 18(A) and (B). 10A and 10B are a longitudinal cross-sectional view and a channel width direction cross-sectional view of the transistor 90a.

[0286] The transistor 90b shown in FIGS. 18(C) and 18(D) has a protrusion formed on a semiconductor substrate 91. 18A and 18B in that the transistor 90a does not have a gate electrode. Other configurations of the transistor 90b shown in (C) and (D) are shown in FIGS. The configuration of the transistor 90a can be taken into consideration.

[0287] In the transistors 90a and 90b, the area in contact with the bottom surface of the conductor 96 However, the semiconductor device shown in this embodiment is not limited to this. For example, the insulator 94 may be provided so as to contact the bottom and side surfaces of the conductor 96. It may also be composed.

[0288] <Configuration example of semiconductor device> An element layer including an oxide semiconductor is formed on an element layer including a semiconductor substrate (hereinafter referred to as element layer 50). (hereinafter referred to as element layer 30) is provided, and an element layer including a capacitive element (hereinafter referred to as An example of the configuration of a semiconductor device provided with a transistor layer 40 is shown in FIG. 1 is a cross-sectional view of a transistor 60a and a transistor 90a taken along the channel length direction C1-C2. In FIG. 19, the channel length direction of the transistor 60a and the transistor 90a is are parallel to each other, but are not limited to this and can be set appropriately.

[0289] The element layer 50 is provided with a transistor 90a shown in FIG. A substrate 91, an element isolation region 97, an insulator 98, an insulator 99, an insulator 94, an insulator 95, a conductor The conductive body 96, the low resistance region 93a and the low resistance region 93b, the low resistance region 92a and the low resistance region For the area 92b, the above description can be taken into consideration.

[0290] The element layer 50 includes a conductor 51a and a conductor 52a, a conductor 51b and a conductor 52b, The conductors 51c and 52c are provided with portions that function as plugs. The lower surfaces of the body 51a and the conductor 52a are in contact with the low resistance region 92a, and the insulator 98 and the insulating layer 99 are in contact with the low resistance region 92a. The conductors 51b and 52b are formed in the openings of the edge 99. The lower surfaces of the conductors 51b and 52b are conductive. The conductor 51c and the conductor 51d are formed in the opening of the insulator 98 and in contact with the conductor 96. The lower surface of the insulating layer 2c is in contact with the low resistance region 92b and is formed in the openings of the insulating layer 98 and the insulating layer 99. It has been completed.

[0291] Here, the conductors 51a to 51c have nitrogen as shown in FIGS. 2(A) and 2(B). The conductors 52a to 52c may have the same structure as the metal 20a. The conductor 21a may have a structure similar to that shown in (A) and (B). Alternatively, the plug and the wiring may be formed separately using, for example, a single damascene method. .

[0292] As shown in FIG. 19, the conductors 51a to 51c and the conductors 52a to 52c The conductors 51a to 51c preferably have a laminated structure. Titanium, tantalum, titanium nitride, tantalum nitride, etc. may be used in a single layer or a laminated layer. Metals containing nitrogen, such as tantalum nitride or titanium nitride, especially tantalum nitride, are used as conductors. By using the conductive materials 51a to 51c, impurities such as hydrogen and water contained in the element layer 50 and the like can be prevented. Prevents substances from diffusing into the conductors 51a to 51c and moving to higher layers. This can be done not only for the conductors 51a to 51c but also for other plugs and wiring. The same applies to the conductors that function as lines. Similarly, the conductors 111a to 111c and the conductors 121a to 121c also have a stacked structure. and a metal having nitrogen such as tantalum nitride or titanium nitride, particularly tantalum nitride, as the underlayer. By using the above, impurities such as hydrogen and water can be diffused into the element layer 30 located above. With this configuration, the oxide semiconductor contained in the element layer 30 can be prevented. The conductor can be a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor.

[0293] An insulator 102a and an insulator 102b are provided on the insulator 98. The conductors 51a, 52a, and 51b are inserted into the openings formed in the insulator 102b. b and the conductor 52b, the conductor 51c and the conductor 52c, which function as wiring or the like. For example, the conductors 52a to 52c are provided with a diffusion layer such as copper. When using metals that are easily permeated, insulating materials such as silicon nitride and silicon carbide nitride that are difficult for copper to penetrate are used. The use of an insulating material prevents impurities such as copper from diffusing into the transistor 90a. In addition, the insulator 102a is made of an insulator having a lower hydrogen concentration than the insulator 98. It is also preferable that the insulator 102b has a lower dielectric constant than the insulator 102a. In FIG. 19, the insulator 102a and the insulator 102b are stacked. However, the present invention is not limited to this and may be a single layer insulator.

[0294] An insulator 104 is provided on the insulator 102b, and an insulator 106 is provided on the insulator 104. The insulator 102a is provided on the insulator 102b, and the insulator 108 is provided on the insulator 106. , insulator 104, insulator 106 and insulator 108 can be used for insulator 98. Insulators may be used. Either the insulating layer 106 or the insulating layer 108 has a function of blocking impurities such as hydrogen and oxygen. It is preferable to use an insulator that has the function of blocking impurities such as hydrogen and oxygen. Examples of insulators having this property include boron, carbon, nitrogen, oxygen, fluorine, and magnesium. , aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium an insulator containing sulphur, zirconium, lanthanum, neodymium, hafnium or tantalum, It may be used as a single layer or a laminated layer, for example, silicon nitride.

[0295] Furthermore, when a metal that easily diffuses, such as copper, is used for the conductors 52a to 52c, the insulator 1 04 by using an insulator that copper cannot easily penetrate, such as silicon nitride or silicon carbide nitride. This can prevent impurities such as copper from diffusing into the oxide semiconductor film included in the element layer 30. can.

[0296] The insulators 104 and 106 are provided with the conductors 111a and 112a, and the conductor 111b. 11b and conductor 112b, and conductor 111c and conductor 112c. The insulator 108 is provided with a portion that functions as a conductor 111a and a conductor 111b. 12a, conductor 111b and conductor 112b, conductor 111c and conductor 112c, The conductor 111a and the conductor 112a are provided with a portion that functions as a wiring. The lower surface of the insulator 104, the insulator 106, and the insulator 108 are in contact with the conductor 52a. The bottom surfaces of the conductors 111b and 112b are connected to the conductor 52b. The conductive layer 104 is formed in the openings of the insulator 104, the insulator 106, and the insulator 108. The bottom surfaces of the conductor 111c and the conductor 112c are in contact with the conductor 52c, and the insulator 104 and the insulator It is formed within an opening in the edge 106 and the insulator 108 .

[0297] Here, the conductors 111a to 111c are the nitrogen-containing conductors shown in FIGS. The conductors 112a to 112c may have a structure similar to that of the metal 20a. The conductor 21a may have the same structure as that of the conductor 21a shown in FIGS. For example, the plug and the wiring may be formed separately using a single damascene method. That's fine.

[0298] An insulator 110 is provided on the insulator 108. The insulator 110 is the same as the insulator 106. Any suitable insulator may be used.

[0299] The element layer 30 on the insulator 110 is provided with a transistor 60a shown in FIG. The insulator 61, the insulator 67, the conductor 62a, the conductor 62b, the insulator 65, the insulator semiconductor 63, insulator 64, insulator 66a, semiconductor 66b, insulator 66c, conductor 68a, conductive Regarding the conductor 68b, the insulator 72, the conductor 74, the insulator 79, the insulator 77, and the insulator 78, The above description can be taken into consideration.

[0300] The insulators 61, 59, 58 and 110 are provided with the conductors 121a and 121b. Conductor 122a, conductor 121b and conductor 122b, conductor 121c and conductor 12 2c, and the insulator 67 has a portion that functions as a plug for the conductor 1. 21a and conductor 122a, conductor 121b and conductor 122b, conductor 121c and The conductors 121a and 122c are provided with portions that function as wiring. The lower surfaces of the conductor 122a are in contact with the conductor 112a, and the insulators 67, 61, and 59, insulator 58 and insulator 110 are formed in the openings. The bottom surfaces of the conductors 122b and 122b are in contact with the conductor 112b, and the insulators 67, 61, and 59, insulator 58 and insulator 110 are formed in the openings. The lower surface of the conductor 122c is in contact with the conductor 112c, and the insulators 67, 61, and 59, formed within openings in insulator 58 and insulator 110.

[0301] Here, the conductors 121a to 121c are nitrogen-containing conductors shown in FIGS. The conductors 122a to 122c may have a structure similar to that of the metal 20a. The conductor 21 may have a structure similar to that of the conductor 21a shown in FIGS. 2(A) and 2(B).

[0302] In addition, the conductors 62a and 62b are connected to the conductors 121a and 122a, The conductor 121b and the conductor 122b, the conductor 121c and the conductor 122c are formed in the same layer. It has been completed.

[0303] As shown in FIG. 19, the insulators 61, 59, and 66b are provided between the semiconductor substrate 91 and the semiconductor 66b. The conductors 121a to 121c are separated from the insulator 58 and the conductors 121a to 121c. The conductor 121c has a function of blocking the diffusion of hydrogen and water, and therefore, the element layer 5 Impurities such as hydrogen or water contained in the insulator 61, the insulator 59, and the insulator 5 Conductors 122a to 122c functioning as via holes and plugs formed in the substrate 8 are This can prevent the impurities from diffusing into the semiconductor 66b via the impurities.

[0304] FIG. 20 shows a cross-sectional view corresponding to the C3-C4 cross section near the scribe line 138. As shown in Figure 20, the insulator 6 7, openings are formed in the insulators 65, 63, 64 and 77, and the insulators 6 7, the insulator 78 covers the sides of the insulators 65, 63, 64 and 77. It is preferable that the insulator 78 and the insulator 61 are formed in contact with each other in the opening.

[0305] By adopting such a shape, the insulator 78 and the insulator 61 are , the insulators 63, 64 and 77 can be covered up to the side surfaces. The insulator 61 has a function of blocking hydrogen and water, and therefore, Even if the conductor device is scribed, the insulators 67, 65, 63, 64 and The insulator 77 is formed to prevent hydrogen or water from penetrating from the side and diffusing into the transistor 60a. You can do this.

[0306] As described above, excess oxygen can be supplied to the insulator 77 during the formation of the insulator 78. At this time, since the side surface of the insulator 77 is covered with the insulator 78, oxygen can be prevented from penetrating the insulator. 78, filling the insulator 77 with oxygen and allowing oxygen to diffuse from the insulator 77 to the insulator 66 a, the semiconductor 66b, and the insulator 66c can be supplied with oxygen. This can reduce oxygen vacancies that cause defects in the body 66a, the semiconductor 66b, and the insulator 66c. This allows the semiconductor 66b to be an oxide semiconductor with a low defect state density and stable characteristics. It is possible.

[0307] An insulator 88 is provided on the insulator 78. The insulator 88 is made of an insulator similar to the insulator 78. However, it is preferable to form the film by the ALD method. The insulator 89 may be any insulator that can be used for the insulator 59. An insulator 81 is provided on the insulator 89. The insulator 81 can be used for the insulator 77. Any suitable insulator can be used.

[0308] Insulator 81, insulator 89, insulator 88, insulator 78, insulator 77, insulator 66c, insulator 64, insulator 63, and insulator 65 are provided with conductor 31a and conductor 31b acting as plugs. Conductor 32a, conductor 31b and conductor 32b, conductor 31c and conductor 32c, conductor The conductive body 31d and the conductive body 32d, the conductive body 31e and the conductive body 32e are provided. The lower surfaces of the body 31a and the conductor 32a are in contact with the conductor 122a, and the insulators 81 and 8 9, insulator 88, insulator 78, insulator 77, insulator 66c, insulator 64, insulator 63, and The conductors 31b and 32b are formed in the openings of the insulator 65. is in contact with the conductor 68a, and the insulators 81, 89, 88, 78, and 7 7 and insulator 66c. Conductor 31c and conductor 32c are formed in the openings of , the lower surface of which is in contact with the conductor 68b, and the insulators 81, 89, 88, 78, and The conductor 31d and the conductor 31c are formed in the openings of the edge 77 and the insulator 66c. 2d has its bottom surface in contact with the conductor 122b, and is made up of the insulators 81, 89, 88, and 78, insulator 77, insulator 66c, insulator 64, insulator 63, and the openings of insulator 65 The lower surfaces of the conductors 31e and 32e are in contact with the conductor 122c. Insulator 81, insulator 89, insulator 88, insulator 78, insulator 77, insulator 66c, insulator It is formed in the openings of the edge 64, the insulator 63 and the insulator 65.

[0309] Here, the conductors 31a to 31e have nitrogen atoms as shown in FIGS. 2(A) and 2(B). Any conductor that can be used for the metal 20a may be used. By configuring the openings as described above, the conductors 31a to 31e are formed in the openings. The conductors 31a to 31e can be shaped to block the diffusion of hydrogen and water. Since the transistor has a locking function, the transistor is turned on via the conductors 32a to 32e. This can prevent impurities such as hydrogen or water from diffusing into the capacitor 60a. The conductors 32a to 32e can be used for the conductor 21a shown in FIGS. 2(A) and 2(B). Any suitable conductor may be used.

[0310] The conductors 33a, 33b, 82, and 33e are formed on the insulator 81. Here, the conductor 82 is one of the electrodes of the capacitance element 80a of the element layer 40. The conductor 33a contacts the exposed upper surfaces of the conductors 31a and 32a, and the conductor 33b The conductor 82 contacts the exposed upper surfaces of the conductors 31b and 32b, and the conductor 82 contacts the exposed upper surfaces of the conductors 31c and The conductor 33 is in contact with the exposed upper surfaces of the conductors 32c, 31d, and 32d. e contacts the exposed upper surfaces of the conductors 31e and 32e.

[0311] Here, the conductors 33a, 33b, and 33e can be used as the conductor 82. Any suitable conductor may be used.

[0312] In the cross-sectional view shown in FIG. 19, the conductor 74, the wiring and the plug connected to the conductor 62b are Although not shown, a separate device may be provided.

[0313] The element layer 40 is provided with the capacitance element 80a shown in FIG. 17(A), and the insulator 81 For the conductor 82, the insulator 83, the conductor 84, and the insulator 85, please refer to the above description. It is possible.

[0314] The element layer 40 includes a conductor 41a, a conductor 42a, and a conductor 41b, which function as plugs. and conductor 42b, conductor 41c and conductor 42c, conductor 41d and conductor 42 The lower surfaces of the conductors 41a and 42a are in contact with the conductor 33a. , are formed in the openings of the insulators 83 and 85. The conductors 41b and The lower surface of the conductor 42b is in contact with the conductor 33b and is formed in the opening of the insulator 83 and the insulator 85. The bottom surfaces of the conductors 41c and 42c are in contact with the conductor 84, and the bottom surfaces of the conductors 41c and 42c are in contact with the insulator 8. The conductors 41d and 42d are formed in the openings of the conductor 33. e and formed in the openings of the insulators 83 and 85.

[0315] Here, the conductors 41a to 41d have nitrogen as shown in FIGS. 2(A) and 2(B). Any conductor that can be used for the metal 20a may be used. 42d uses a conductor that can be used for the conductor 21a shown in FIGS. 2(A) and (B). That's good enough.

[0316] The conductors 43a to 43d functioning as wirings are formed on an insulator 85. The conductor 43a contacts the exposed upper surfaces of the conductors 41a and 42a, and the conductor 43b contacts the exposed upper surfaces of the conductors 41b and 42b, and the conductor 43c contacts the exposed upper surfaces of the conductors 41c and 42b. and conductor 42c, and conductor 43d is in contact with conductor 41d and conductor 44c. It is in contact with the exposed top surface of 2d.

[0317] Here, the conductors 43a to 43d are the conductors 33a, 33b, and 33c. Conductors that can be used for the conductors 43a to 43d may be used. Since the conductors 43a to 43d are formed on the element layer 30, they are heated at high temperatures after the conductors 43a to 43d are formed. Therefore, the conductors 43a to 43d may not need to be subjected to the heat treatment. For example, by using metal materials such as aluminum and copper, which have low heat resistance but low resistance, This allows the wiring resistance to be reduced.

[0318] An insulator 134 is formed on the insulator 85 to cover the conductors 43a to 43d. The edge 134 may be made of an insulator that can be used for the insulator 85 .

[0319] The insulator 134 is provided with a conductor 131 and a conductor 132 that function as plugs. The bottom surfaces of the conductors 131 and 132 are in contact with the conductor 42a, and the bottom surfaces of the conductors 131 and 132 are in contact with the insulator 134. The opening is formed in the

[0320] Here, the conductor 131 is used for the nitrogen-containing metal 20a shown in FIGS. 2(A) and 2(B). The conductor 132 may be any conductor that can be used. Any conductor that can be used for the conductor 21a shown in FIG.

[0321] The conductor 133, which functions as a wiring, is formed on the insulator 134. is in contact with the exposed top surfaces of conductor 131 and conductor 132. The conductors 33a, 33b, and 33e are made of conductors that can be used for the conductors 33a, 33b, and 33e. That's fine.

[0322] An insulator 136 is formed on the insulator 134 so as to have an opening above the conductor 133. The insulator 136 may be made of the same insulator that can be used for the insulator 134. The insulator 136 may be an organic insulating film such as polyimide.

[0323] 23 shows a semiconductor device having a different configuration from that shown in FIG. 1 and 2. The cross-sectional view corresponds to the channel length direction C1-C2 of the transistor 90a. In the example shown in FIG. 23, the channel lengths of the transistors 60a and 90a are parallel to each other. However, the present invention is not limited to this and can be set appropriately.

[0324] The insulator 77 is disposed to cover the transistor 60a in the semiconductor device shown in FIG. The following describes the configuration that differs from the semiconductor device shown in FIG.

[0325] The insulators 77, 66c, 64, 63, and 65 are provided with plugs and The conductors 31a and 32a, the conductors 31b and 32b, and the conductors Conductor 31c and conductor 32c, conductor 31d and conductor 32d, conductor 31e and conductor The conductor 31a and the conductor 32a are provided with a conductor 122 on the bottom surface. a, and the insulators 77, 66c, 64, 63, and 65 The conductors 31b and 32b are formed in the openings. The lower surfaces of the conductors 31b and 32b are connected to the conductor 68a. The conductors 31c and 66c are formed in the openings of the insulators 77 and 66c. The lower surfaces of the conductor 32c are in contact with the conductor 68b, and the openings of the insulator 77 and the insulator 66c are The bottom surfaces of the conductors 31d and 32d are connected to the conductor 122b. The openings of the insulators 77, 66c, 64, 63, and 65 are The lower surfaces of the conductors 31e and 32e are in contact with the conductor 122c. In the openings of the insulators 77, 66c, 64, 63, and 65, is formed.

[0326] The conductors 31a and 32a, 31b and 32b function as plugs. b, conductors 31c and 32c, conductors 31d and 32d, and conductor 31e and the conductor 32e, the insulators 55a, 55b, and the insulator 55c are provided so as to cover the upper surfaces of the conductor 32e. The insulating body 55c is covered with an insulator 55d and an insulator 55e. b, the insulators 55c, 55d, and 55e are made of the same insulator as the insulator 78. However, it is preferable to form the film by the ALD method.

[0327] The insulators 55a, 55b, 55c, 55d, and 55e include , for example, metal oxides such as aluminum oxide, hafnium oxide, tantalum oxide, or It is preferable to use metal nitrides such as tantalum nitride. In particular, aluminum oxide is , oxygen, and impurities such as hydrogen and moisture, which are factors that cause fluctuations in the electrical characteristics of transistors. Therefore, aluminum oxide has a high blocking effect that prevents the penetration of During and after the manufacturing process of the transistor, impurities such as hydrogen and moisture It is possible to prevent contamination with 0a.

[0328] On the insulator 55a, on the insulator 55b, on the insulator 55c, on the insulator 55d, on the insulator 55e, and On the insulator 77, an insulator 78, an insulator 88, an insulator 89, and an insulator 81 are arranged in this order. The insulator 78 is formed to supply oxygen to the insulator 77. This oxygen becomes excess oxygen and passes through the insulators 77 and 66c, etc., and becomes the semiconductor. It can diffuse into the body 66b and repair defects in the semiconductor 66b.

[0329] The insulators 78, 88, 89, and 81 are provided with conductors 31a to 31c. The conductor 31e and the conductors 32a to 32e are embedded. The conductors 1a to 31e and the conductors 32a to 32e are the capacitance element 80a, the transformer As a plug or wiring electrically connecting to the transistor 60a or the transistor 90a The conductors 31a to 31e have the nitrogen-containing function shown in FIGS. Any conductor that can be used for the metal 20a may be used. The conductor 32e is a conductor that can be used for the conductor 21a shown in FIGS. Just use your body.

[0330] The insulators 81, 89, 88, 78, and 55c are provided with plugs and Conductors 41c and 42c, and conductors 41d and 42d that function as a pair are provided. The bottom surfaces of the conductors 41c and 42c are in contact with the conductor 32c, and the bottom surfaces of the conductors 41c and 42c are in contact with the conductor 32c. 81, insulator 89, insulator 88, insulator 78, and insulator 55c. The bottom surfaces of the conductors 41d and 42d are in contact with the conductor 32d and are connected to the insulator 81. , insulator 89, insulator 88, insulator 78, and insulator 55d. The conductor 87 is made up of the conductors 41c, 41d, 42c and 42d. conductors 82a and 82b, which are in contact with the upper surface of conductor 87, are also arranged. The conductor 87, the conductor 82a, and the conductor 82b form a capacitance element. It functions as one of the electrodes 80a.

[0331] An insulator 83 is disposed on the insulator 81, the conductor 87, the conductor 82a, and the conductor 82b. The insulator 83 functions as a dielectric of the capacitor element 80a. 83 can have a three-layer structure of insulator 83a, insulator 83b, and insulator 83c. For example, the insulators 83a, 83b, and 83c are formed by the ALD method. 3a is silicon oxide, insulator 83b is aluminum oxide, and insulator 83c is silicon oxide. You may do so.

[0332] The insulators 83, 81, 89, 88, 78, and 55a The conductors 41a and 42a, 41b and 42b function as plugs. 42b, conductor 41e, and conductor 42e are provided. The lower surface of the insulating member 42a is in contact with the conductor 32a, and the insulating member 83, the insulating member 81, the insulating member 89, the insulating member 88, insulator 78, and insulator 55a. The lower surfaces of the conductors 42b and 42b are in contact with the conductor 32b, and the insulators 83, 81, and 89 are , insulator 88, insulator 78, and insulator 55b. The lower surfaces of the insulators 1e and 42e are in contact with the conductor 32e, and the insulators 83, 81, and 42e are in contact with the conductor 32e. It is formed within the openings of edge 89, insulator 88, insulator 78, and insulator 55e.

[0333] A conductor 43a having a region in contact with the upper surface of the conductor 42a is provided on the insulator 83. Furthermore, on the insulator 83, there is a conductor 43b having a region in contact with the upper surface of the conductor 42b. Further, on the insulator 83, a region in contact with the upper surface of the conductor 42e is provided. A conductor 43c having a conductor 84 is provided on the insulator 83. The conductor 84 functions as the other electrode of the capacitor 80a.

[0334] On the insulator 83, the conductor 43a, the conductor 43b, the conductor 43c, and the conductor 84 An insulator 134 is provided. The insulator 134 includes a conductor 131 that functions as a plug. The conductors 131 and 132 are connected at their bottom surfaces to the conductor 43a. and formed in the opening of the insulator 134.

[0335] Here, the conductor 131 is used for the nitrogen-containing metal 20a shown in FIGS. 2(A) and 2(B). The conductor 132 may be any conductor that can be used. Any conductor that can be used for the conductor 21a shown in FIG.

[0336] The conductor 133, which functions as a wiring, is formed on the insulator 134. is in contact with the exposed top surfaces of conductor 131 and conductor 132. The conductors 33a, 33b, and 33e are made of conductors that can be used for the conductors 33a, 33b, and 33e. That's fine.

[0337] An insulator 136 is formed on the insulator 134 so as to have an opening above the conductor 133. The insulator 136 may be made of the same insulator that can be used for the insulator 134. The insulator 136 may be an organic insulating film such as polyimide.

[0338] <Method for manufacturing transistor having oxide semiconductor film>

[0339] Next, the conductor 62a and the conductor 62b functioning as the back gate of the transistor 60a shown in FIG. and a method for manufacturing a transistor 60a having an oxide semiconductor film over a conductor 62b. This will be explained using the cross-sectional views shown in Figures 21 and 22. 21(E), 22(A), 22(C) and 22(E) show the transistor 60a. 21(B), 21(D), and 21(C) are cross-sectional views corresponding to the channel length direction A1-A2. 1(F), FIG. 22(B), FIG. 22(D) and FIG. 22(F) show the channel of transistor 60a. 1 is a cross-sectional view taken along line A3-A4 in the width direction of the panel.

[0340] First, the insulator 65 is formed on the insulator 67, the conductor 62a, and the conductor 62b. The insulator 65 may be formed by a sputtering method. This can be done using a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 65 is formed of silicon oxide or silicon oxynitride by the PECVD method. Just film it.

[0341] Next, the insulator 63 is formed on the insulator 65. The insulator 63 is the above-mentioned insulator. The insulator 63 may be formed by sputtering, CVD, MBE, or PLD. For example, the insulator 63 can be formed by the ALD method. A film of hafnium oxide or aluminum oxide may be formed.

[0342] Next, the insulator 64 is formed on the insulator 63 (see FIGS. 21(A) and 21(B)). The insulator 64 may be formed by a method such as sputtering or CVD. This can be done by using a method such as MBE, PLD, or ALD. 64, silicon oxide or silicon oxynitride can be formed using the PECVD method. In addition, the insulators 65, 63, and 64 are formed without being exposed to the atmosphere. It may also be carried out continuously using the LD method.

[0343] Next, it is preferable to perform a heat treatment. By performing the heat treatment, the insulators 65 and 63 The water or hydrogen in the insulator 64 can be further reduced. 4. It may be possible to have excess oxygen in the material. Heat treatment is carried out at temperatures between 250°C and 650°C. The temperature is preferably 350° C. or higher and 450° C. or lower. When tantalum nitride is used for the gate conductor 62a, the heat treatment temperature is set to 350°C. The temperature may be set to 370°C or higher and 410°C or lower, preferably 370°C or higher and 400°C or lower. By performing the heat treatment within this range, it is possible to suppress the release of hydrogen from tantalum nitride. Heat treatment is carried out in an inert gas atmosphere or in an atmosphere containing oxidizing gases at 10 ppm or more, 1% or more, or 1 The heat treatment is carried out in an atmosphere containing 0% or more of HCl. The heat treatment may be carried out under reduced pressure. After heat treatment in an inert gas atmosphere, oxidizing gas was added at 10ppm to compensate for the desorbed oxygen. The heat treatment may be carried out in an atmosphere containing at least 1% or at least 10% of Zn. This allows impurities such as hydrogen and water to be removed. Heat treatment with an RTA device can be performed in a shorter time than with a furnace. This is effective in increasing productivity because it requires less time.

[0344] Next, the insulator 69a that will become the insulator 66a is formed. Any insulator or semiconductor may be used as the insulator 66a. The film is formed using the sputtering method, CVD method, MBE method, PLD method, ALD method, etc. The insulator 69a is preferably formed while the substrate is heated. The temperature for heating the substrate may be the same as that for the heat treatment described below.

[0345] Next, a semiconductor film that will become the semiconductor 66b is formed. Any semiconductor that can be used as the semiconductor 66b may be used. Sputtering, CVD, MBE, PLD, ALD, etc. It is also preferable to form the semiconductor 66b while heating the substrate. The heating temperature may be the same as that of the heat treatment described later. The film and the semiconductor film that will become the semiconductor 66b are formed successively without being exposed to the atmosphere. This can reduce the amount of impurities entering the film and at the interface.

[0346] Next, it is preferable to perform a heat treatment on the insulator 69a and the semiconductor 69b. By doing so, it may be possible to reduce the hydrogen concentration in the insulator 66a and the semiconductor 66b. In addition, oxygen vacancies in the insulator 66a and the semiconductor 66b may be reduced. The heat treatment is carried out at a temperature of 250°C or higher and 650°C or lower, preferably 350°C or higher and 450°C or lower. Furthermore, tantalum nitride may be used for the conductor 62a that serves as the back gate of the transistor. When using, the heat treatment temperature is 350°C or higher and 410°C or lower, preferably 370°C or higher and 40 By performing heat treatment in this temperature range, tantalum nitride The heat treatment can be carried out in an inert gas atmosphere or an oxidizing gas atmosphere. The heat treatment is carried out in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more. Alternatively, the heat treatment may be performed in an inert gas atmosphere, followed by desorption of the desorbed fluorine. In an atmosphere containing oxidizing gases of 10 ppm or more, 1% or more, or 10% or more to supplement oxygen Heat treatment may be performed. The heat treatment may change the crystallinity of the insulator 66a and the semiconductor 66b. The heat treatment can increase the temperature and remove impurities such as hydrogen and water. An RTA device with a tap heating system can also be used. Heat treatment with an RTA device is more efficient than with a furnace. This is effective in increasing productivity because it requires a short time. When CAAC-OS (described later) is used as b, the peak intensity increases by heat treatment. In other words, the crystallinity of CAAC-OS is improved by heat treatment. become.

[0347] By this heat treatment, oxygen is supplied from the insulator 64 to the insulator 69a and the semiconductor 69b. By subjecting the insulator 64 to a heat treatment, it is possible to insulate oxygen very easily. The insulator can be provided as body 66a, and the semiconductor can be provided as semiconductor 66b.

[0348] Here, the insulator 63 functions as a barrier film that blocks oxygen. By providing the insulating material 64 under the insulating material 64, oxygen diffused into the insulating material 64 is absorbed by the insulating material 64. This can prevent diffusion to the lower layer.

[0349] In this way, oxygen is supplied to the insulator that becomes the insulator 66a and the semiconductor that becomes the semiconductor 66b. By reducing oxygen vacancies, high purity intrinsic or substantially high purity silicon with low defect level density can be obtained. A pure intrinsic oxide semiconductor can be obtained.

[0350] Next, a conductor 68 that will become the conductor 68a and the conductor 68b is formed (FIG. 21(C)(D) ) The conductor 68 can be used as the conductor 68a and the conductor 68b described above. The conductor 68 can be formed by a sputtering method, a CVD method, an MBE method, or the like. For example, the conductor 68 may be A tantalum nitride film is formed using the sputtering method, and then a tungsten film is formed on top of that. That's fine.

[0351] Next, a resist or the like is formed on the conductor 68, and the resist or the like is used to form an insulator 69a, The semiconductor 69b and the conductor 68 are processed into an island shape, and the island-shaped conductor 68, the semiconductor 66b, and An insulator 66a is formed.

[0352] Next, heat treatment may be performed. By the heat treatment, the insulators 64, 63, and Further reducing the amount of water or hydrogen in the insulator 65, the insulator 66a, and the semiconductor 66b. The heat treatment can be carried out at a temperature of 250°C or higher and 650°C or lower, preferably 350°C or higher and 450°C or lower. Further, nitride film is formed on the conductor 62a which is the back gate of the transistor. When tantalum is used, the heat treatment temperature is set to 350°C or higher and 410°C or lower, preferably 370°C or lower. By performing heat treatment in this temperature range, the nitride film can be The heat treatment can be performed in an inert gas atmosphere. The heat treatment may be carried out in an atmosphere containing an oxidizing gas. Alternatively, the heat treatment may be carried out in an inert gas atmosphere, followed by heating to replenish the desorbed oxygen. Therefore, heat treatment is carried out in an atmosphere containing oxidizing gases at 10 ppm or more, 1% or more, or 10% or more. Heat treatment can also be performed using an RTA device that uses lamp heating. Heat treatment by a station takes less time than by using a furnace, and is therefore effective in increasing productivity.

[0353] The heat treatment carried out up to this point removes impurities such as water and hydrogen that affect oxide semiconductors. As described above, the insulator 61 can be reduced before the deposition of the oxide semiconductor. By closing the via holes formed in the insulator 61 with the conductor 121a or the like, Impurities such as hydrogen contained in the lower layer can be prevented from diffusing from the insulator 61 to the upper layer. Furthermore, the temperature of the process performed after the oxide semiconductor film formation can be adjusted by changing the temperature of the conductor 121a and the like to water. By keeping the temperature below the temperature at which the atoms are released, the influence of impurity diffusion is reduced. can be done.

[0354] The insulator 66a and the semiconductor 66b are formed, and the surface of the insulator 64 is exposed. By carrying out the treatment, the supply of water and hydrogen to the insulator 66a and the semiconductor 66b is suppressed. While suppressing the above, the water or hydrogen in the insulators 64, 63 and 65 is further reduced. It can be done.

[0355] In addition, when forming the insulator 66a and the semiconductor 66b, impurities such as hydrogen and carbon are When using an etching gas containing pure substances, the insulator 66a and the semiconductor 66b are etched with water. In this way, impurities such as silicon and carbon may be introduced into the insulator 66a and the semiconductor After the formation of the conductor 66b, a further heat treatment is performed to remove the water trapped during etching. Impurities such as hydrogen and carbon can be desorbed.

[0356] Next, a resist or the like is formed on the island-shaped conductor 68, and processing is performed using the resist or the like. Conductors 68a and 68b are formed (see FIGS. 21(E) and 21(F)).

[0357] In addition, in the region of the semiconductor 66b that contacts the conductor 68a or the conductor 68b, a low resistance region In addition, the semiconductor 66b may form a region between the conductor 68a and the conductor 68b. conductor 68a or conductor 68b. This is because when the conductors 68a and 68b are formed, one of the upper surfaces of the semiconductor 66b is It is formed by removing a portion.

[0358] Next, on the insulator 64, the insulator 66a, the semiconductor 66b, the conductor 68a and the conductor 68b The insulator 69c is formed on the insulating film 66c. The insulator or semiconductor that can be used as the insulator 66 may be used. The film c is formed using the sputtering method, CVD method, MBE method, PLD method, ALD method, etc. Before forming the insulator film that will become the insulator 66c, the surface of the semiconductor 66b or the like is The surface may be etched, for example, by using a plasma containing a rare gas. Thereafter, an insulator that will become the insulator 66c is continuously formed without being exposed to the atmosphere. This reduces the amount of impurities entering the interface between the semiconductor 66b and the insulator 66c. Impurities present at the interface between films may be more easily diffused than impurities within the film. Therefore, by reducing the amount of impurities mixed in, a stable current can be obtained in the transistor. It can be given a special characteristic.

[0359] Next, an insulator 72a that will become the insulator 72 is formed on the insulator 69c. Any insulator that can be used as the insulator 72 described above may be used. The film is formed using the sputtering method, CVD method, MBE method, PLD method, ALD method, etc. For example, silicon oxynitride can be formed as the insulator 69c by using the PECVD method. The insulator 69c and the insulator 72a may be formed in a large amount. By performing this process continuously without exposing the film to air, it is possible to reduce the inclusion of impurities in the film and at the interface. This can be done.

[0360] Next, a conductor that will become the conductor 74 is formed on the insulator 72. Any conductor that can be used as the conductor 74 described above may be used. The deposition of the conductive material is performed by sputtering, CVD, MBE, PLD, or ALD. This can be done using methods such as the For example, a titanium nitride film is formed as the conductor 74 by the ALD method, and then By using the sputtering method, a tantalum nitride film is formed on the surface after reverse sputtering. That's fine.

[0361] Next, a resist or the like is formed on the conductor that will become the conductor 74, and the resist or the like is used to process the conductor. This forms the conductor 74 (see FIGS. 22(A) and 22(B)).

[0362] Next, an insulator that will become the insulator 79 is formed on the insulator 72a. The insulator may be any insulator that can be used as the insulator 79 described above. The insulator film to be formed is made by sputtering, CVD, MBE or PLD, AL For example, the insulator 79 can be formed by the ALD method. A film of gallium oxide or aluminum oxide may be formed using the above.

[0363] Next, a resist or the like is formed on the insulator that will become the insulator 79, and the resist or the like is used to form a mold. This forms an insulator 79 (see FIGS. 22(C) and 22(D)).

[0364] Next, the insulator 7 is applied on the insulator 64, the insulator 79, the conductor 68a, the conductor 68b, etc. The insulator 77 may be any of the insulators described above. It is preferable that the insulator 77 contains few impurities such as hydrogen, water, and nitrogen oxides. The method can be performed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, silicon oxynitride or the like can be formed as the insulator 77 by using the PECVD method. A film may be formed.

[0365] Next, it is preferable to improve the flatness of the upper surface of the insulator 77 by using a CMP method or the like.

[0366] Here, as shown in FIG. 20, a scribe line 138 is formed by using a lithography method or the like. In the vicinity of the overlapping region, the insulator 67, the insulator 65, the insulator 63, the insulator 64 and the insulator Preferably, the rim 77 has an opening formed therein.

[0367] Next, an insulator 78 is formed on the insulator 77. The insulator 78 is made of the above-mentioned material. The insulator 78 may be formed by a sputtering method, a CVD method, or the like. This can be done by using a method such as MBE, PLD, or ALD. In the vicinity of the scribe line 138 shown in FIG. 1, the insulator 67, the insulator 65, and the insulator An insulator 78 is formed to cover the side surfaces of the insulator 63, the insulator 64, and the insulator 77, and the opening Insulator 78 and insulator 61 come into contact with each other at this point.

[0368] The insulator 78 is preferably formed by plasma deposition, for example, by sputtering. It is more preferable to carry out the sputtering in an oxygen-containing atmosphere. More preferable.

[0369] The sputtering method uses a direct current (DC) power supply for the sputtering power supply. current sputtering method, and pulsed DC sputtering method, which applies a bias in a pulsed manner. RF (Radio Frequency) sputtering, which uses a high frequency power supply for sputtering. A sputtering method may also be used. Alternatively, a magnetron having a magnet mechanism inside the chamber may be used. Sputtering method, bias sputtering method in which voltage is applied to the substrate during film formation, reactive gas Alternatively, the reactive sputtering method performed in a gas atmosphere may be used. The oxygen gas flow rate and film formation power for sputtering may be adjusted depending on the amount of oxygen. The amount may be determined appropriately depending on the amount added, etc.

[0370] Here, the insulator 78 is made of aluminum oxide or the like which has a blocking effect against oxygen, hydrogen, water, etc. For example, a sputtered oxide insulating film is preferably used as the insulator 78. Then, an aluminum oxide film can be formed on top of it using the ALD method. It is preferable to form a film of aluminum oxide using the ALD method. By using this, it is possible to prevent the formation of pinholes, and therefore the hydrogen and This can further improve the blocking performance against heat and water.

[0371] By forming the insulator 78 by sputtering, the surface of the insulator 77 Oxygen is added to the vicinity of the interface between the insulator 77 and the insulator 78 after the insulator 78 is formed. , oxygen is added to the insulator 77 as, for example, oxygen radicals. The state of oxygen is not limited to this. Oxygen can be insulated in the form of oxygen atoms or oxygen ions. The oxygen may be added to the insulator 77. When oxygen is added, oxygen is stoichiometrically added to the insulator 77. Oxygen may be contained in excess of the composition, and in this case, it can be called excess oxygen.

[0372] It is preferable to heat the substrate when forming the insulator 78. The temperature may be from 350°C to 450°C, preferably from 350°C to 450°C. When tantalum nitride is used for the conductor 62a that serves as the back gate of the transistor, the above heat treatment The temperature may be set to 350°C or higher and 410°C or lower, preferably 370°C or higher and 400°C or lower. By performing heat treatment in this temperature range, hydrogen is released from tantalum nitride. It can be suppressed.

[0373] Next, it is preferable to perform a heat treatment. By performing the heat treatment, the insulator 64 or the insulating film The oxygen added to the insulator 77 is diffused to form the insulator 66a, the semiconductor 66b, the insulator 66ca, and the insulating layer 66b. The heat treatment can be carried out at a temperature of 250° C. or higher and 650° C. or lower, preferably The heat treatment may be carried out at a temperature of 350°C or higher and 450°C or lower. The heat treatment is carried out in an atmosphere containing chemical gases at 10 ppm or more, 1% or more, or 10% or more. Heat treatment may be carried out under reduced pressure. Heat treatment may also be carried out using an RTA device with lamp heating. do.

[0374] The heat treatment is preferably performed at a temperature lower than that of the heat treatment performed after the semiconductor 66b is formed. The temperature difference between the heat treatment after the formation of the conductor 66b is 20°C or more and 150°C or less, preferably 40°C or less. This prevents excess oxygen from being released from the insulator 64 and the like. The heat treatment after the formation of the insulator 78 can be performed by the same heat treatment. When the heating process can be performed simultaneously by heating each layer during film formation (for example, when the insulating layer 78 is formed, the heating process can be performed simultaneously), In some cases, it may not be necessary to perform this step (e.g., when heating is performed).

[0375] By this heat treatment, the oxygen added to the insulators 64 and 77 is converted into the insulators 64 and 77. The insulator 78 is an insulator that is less permeable to oxygen than the insulator 77. The insulator 78 is an insulator that functions as a barrier film to block oxygen. Since the insulating layer 77 is formed on the insulating layer 77, oxygen diffusing in the insulating layer 77 does not diffuse upward. First, the insulator 77 is diffused mainly in the lateral or downward direction. When the insulator 78 is heated, oxygen is diffused into the insulators 64 and 77 at the same time as the addition. It can be done.

[0376] The oxygen diffusing through the insulator 64 or the insulator 77 is transferred to the insulators 66a, 66ca, and At this time, the oxygen blocking function is provided to the semiconductor 66b. The insulator 63 is provided under the insulator 64, so that the oxygen diffused in the insulator 64 is prevented from It is possible to prevent the element from diffusing into the layer below the insulator 64. In the vicinity of the drain line 138, the insulator 78 and the insulator 61 are By covering the surface, oxygen is prevented from diffusing out of the insulator 78, and the insulator 77 Fill with oxygen, and supply oxygen from insulator 77 to insulator 66a, semiconductor 66b, and insulator 66c. It is possible.

[0377] Furthermore, during the heat treatment, impurities such as hydrogen and water diffused from the lower layer are absorbed by the insulator 61 and the The via hole of the insulator 61 is blocked by a conductor 121a or the like provided therein, and the upper surface of the insulator 77 is blocked by a conductor 121b or the like provided therein. The insulator 78 blocks impurities such as hydrogen and water that diffuse from the surface and sides. As a result, the insulator 7 wrapped in the insulators 61 and 78 can be 7. Impurities such as hydrogen and water in the insulators 66a, 66c and semiconductors 66b. Furthermore, impurities such as hydrogen can be reduced in the insulator 77. It may combine with oxygen to form water, which may hinder the diffusion of oxygen. By reducing the amount of impurities such as hydrogen and water, the supply of oxygen can be promoted. Cut.

[0378] In this way, the insulator 66a, the insulator 66c and the semiconductor 66b, especially the semiconductor 66b The diffusion of impurities such as water and hydrogen is suppressed in the region where the channel is formed, and oxygen is effectively introduced. In this way, the insulators 66a, 66ca, 66cb, and By supplying oxygen to the semiconductor 66b and reducing oxygen vacancies, a low density of defect states is formed. The oxide semiconductor may be a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0379] The heat treatment after the formation of the insulator 78 may be performed at any time after the formation of the insulator 78. For example, it may be performed after the insulator 119 is formed.

[0380] In this manner, the transistor 60a can be formed.

[0381] In this manner, by using the manufacturing method of a semiconductor device described in this embodiment mode, a stable electric current can be obtained. It is possible to provide a semiconductor device having a transistor with thermal characteristics. By using the manufacturing method of the semiconductor device shown in the above embodiment, a transistor with a small leakage current when non-conducting can be obtained. In addition, the semiconductor device shown in this embodiment can be provided. By using the manufacturing method of the device, a transistor having normally-off electrical characteristics can be obtained. In addition, a method for manufacturing a semiconductor device described in this embodiment can be provided. By using the above, a semiconductor device having a highly reliable transistor can be provided. .

[0382] This embodiment may be implemented in any manner other than as described, at least in part, herein. The present invention can be implemented in combination with the examples as appropriate.

[0383] (Embodiment 2) In this embodiment, the oxide semiconductor included in the semiconductor device of one embodiment of the present invention will be described in detail. , as explained below.

[0384] <Oxide semiconductor structure> The structure of an oxide semiconductor will be described below.

[0385] Oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, c-axis-aligned oxide semiconductor (CAAC-OS) crystalline oxide semiconductor), polycrystalline oxide Semiconductor, nc-OS (nanocrystalline oxide semiconducting uctor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous-l amorphous oxide semiconductors and amorphous oxide semiconductors. do.

[0386] From another point of view, oxide semiconductors are classified into amorphous oxide semiconductors and other crystalline oxide semiconductors. Crystalline oxide semiconductors are divided into single-crystal oxide semiconductors, CAAC- Examples include OS, polycrystalline oxide semiconductor, and nc-OS.

[0387] Amorphous structures are generally isotropic and have no heterogeneous structure, and are metastable arrangements of atoms. The bond angles are flexible, and there is short-range order but no long-range order. It is said that...

[0388] That is, the stable oxide semiconductor is completely amorphous. ) and cannot be called an oxide semiconductor. On the other hand, a-li oxide semiconductors cannot be called completely amorphous oxide semiconductors. The ke OS is not isotropic but has an unstable structure with voids. In terms of instability, a-like OS is similar in physical properties to amorphous oxide semiconductors. .

[0389] <caac-os> First, let me explain about CAAC-OS.

[0390] CAAC-OS is an oxide semiconductor having multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of conductor.

[0391] CAAC-OS was analyzed by X-ray diffraction (XRD). For example, the analysis of InGaZnO4, which is classified into the space group R-3m, Structural analysis of crystalline CAAC-OS is performed using the out-of-plane method. As shown in FIG. 24(A), a peak appears at a diffraction angle (2θ) of approximately 31°. The crystal structure is attributed to the (009) plane of the InGaZnO4 crystal. The crystal has a c-axis orientation, and the c-axis is the surface on which the CAAC-OS film is to be formed (also called the surface on which the film is to be formed). It can be seen that the crystal is oriented in a direction perpendicular to the surface, or in a direction approximately perpendicular to the surface. In addition to the peaks around 2θ around 36°, a peak may also appear. The peaks around the nucleus are due to the crystal structure classified into the space group Fd-3m. It is preferable that -OS does not exhibit such a peak.

[0392] On the other hand, in-pla, X-rays are incident on the CAAC-OS from a direction parallel to the surface to be formed. When structural analysis is performed using the NE method, a peak appears at 2θ around 56°. This peak is due to I The lattice constant is fixed at 2θ around 56°. The analysis (φ scan) is performed by rotating the sample around the normal vector of the sample surface (φ axis). Even if the peak is increased, no clear peak appears, as shown in Figure 24(B). When φ is scanned with 2θ fixed at around 56° for nO4, the results are as shown in Figure 24(C). As shown in Fig. 1, six peaks are observed that are attributed to the crystal plane equivalent to the (110) plane. From the structural analysis using RD, it was found that the orientation of the a-axis and b-axis of CAAC-OS is irregular. It can be confirmed that:

[0393] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with nO4 crystals, a probe was applied parallel to the surface on which the CAAC-OS was formed. When an electron beam with a diameter of 300 nm is incident, a diffraction pattern (control pattern) as shown in FIG. 24(D) is generated. This diffraction pattern may contain In. This includes spots due to the (009) plane of the GaZnO4 crystal. Even in such cases, the pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis is aligned with the surface on which the film is formed. On the other hand, for the same sample, the direction of the sample surface is The diffraction pattern when an electron beam with a probe diameter of 300 nm is incident perpendicularly is shown in Figure 24(E). As shown in Figure 24(E), a ring-shaped diffraction pattern is observed. Electron diffraction using an electron beam with a diameter of 300 nm also revealed the presence of pellets in CAAC-OS. It can be seen that the a-axis and b-axis of the dots do not have any orientation. The ring is due to the (010) and (100) planes of the InGaZnO4 crystal. It is thought that the second ring in Figure 24(E) is due to the (110) plane, etc. It is possible.

[0394] In addition, a transmission electron microscope (TEM) A combined analysis image of the bright-field image and diffraction pattern of CAAC-OS was obtained using a microscope. (also called high-resolution TEM image) reveals multiple pellets. On the other hand, even in high-resolution TEM images, the boundaries between pellets, i.e., grain boundaries (grain bows), are not clearly visible. It may not be possible to clearly identify the CAAC It can be said that the -OS is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0395] Figure 25(A) shows a high-resolution T image of a cross section of CAAC-OS observed from a direction approximately parallel to the sample surface. The TEM image shown here is a spherical aberration correction (SAC) image. The spherical aberration correction function was used. A high-resolution TEM image is specifically called a Cs-corrected high-resolution TEM image. For example, an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd. It can be observed that

[0396] From Figure 25(A), it is possible to confirm the pellet, which is the region where metal atoms are arranged in layers. It has been found that the size of a single pellet can be 1 nm or more, or 3 nm or more. Therefore, the pellets are called nanocrystals (nc). Also, CAAC-OS can be used with CANC (C-Axis Aligned Nano The pellets can also be called oxide semiconductors with CAAC -OS surface or upper surface unevenness is reflected, and CAAC-OS surface or upper surface unevenness is reflected. is parallel to the surface.

[0397] 25(B) and 25(C) show the CAAC images observed from a direction approximately perpendicular to the sample surface. Figures 25(D) and 25(E) show Cs-corrected high-resolution TEM images of the -OS surface. These are the images obtained by image processing of Figure 25(B) and Figure 25(C), respectively. First, the fast Fourier transform (FFT) of FIG. Then, the FFT image is obtained by Fourier Transform (FFT). In the FFT image, the origin is used as the reference point, and the -1 to 5.0 nm -1 Remaining range between Next, the masked FFT image is subjected to an inverse fast Fourier transform (IFFT). Inverse Fast Fourier Transform (FFT) processing The image thus obtained is called an FFT filtered image. The filtered image is an image in which the periodic components are extracted from a Cs-corrected high-resolution TEM image. The sequence is shown.

[0398] In Figure 25(D), the area where the lattice arrangement is disturbed is indicated by a dashed line. The area surrounded by the dashed line is The area indicated by the broken line is the connection between the pellets. The broken line indicates a hexagonal shape, which indicates that the pellets are hexagonal. The shape of the dot is not limited to a regular hexagon, and is often a non-regular hexagon.

[0399] In FIG. 25(E), a lattice pattern is formed between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement. The dotted lines indicate the change in the orientation of the array, and the dashed lines indicate the change in the orientation of the lattice array. Even near the dotted line, no clear grain boundaries can be seen. When connecting the surrounding lattice points to the center, distorted hexagons, pentagons, and / or heptagons are formed. In other words, it was found that the formation of grain boundaries was suppressed by distorting the lattice arrangement. This is because the atomic arrangement of CAAC-OS is not dense in the ab-plane direction and The substitution of metal elements changes the bond distance between atoms, allowing for distortion. This is thought to be because

[0400] As described above, the CAAC-OS has a c-axis orientation and multiple crystals in the ab-plane direction. A number of pellets (nanocrystals) are connected to form a distorted crystal structure. AC-OS, CAA crystal(c-axis-aligned ab-pl It can also be called an oxide semiconductor with an anchored crystal. do.

[0401] CAAC-OS is an oxide semiconductor with high crystallinity. CAAC-OS is designed to be free from impurities and defects ( It can also be said to be an oxide semiconductor with few oxygen vacancies.

[0402] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, oxygen is more likely to be present than metal elements such as silicon that make up oxide semiconductors. Elements with strong bonding strength with the oxide semiconductor remove oxygen from the oxide semiconductor, thereby changing the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, and niobium Carbon dioxide and other compounds have a large atomic radius (or molecular radius), so they can easily arrange the atoms of oxide semiconductors. This causes disorder and reduces crystallinity.

[0403] <nc-os> Next, we will explain nc-OS.

[0404] We will explain the case where nc-OS is analyzed by XRD. For example, When structural analysis is performed using the out-of-plane method, no peaks indicating orientation appear. That is, the crystals of nc-OS do not have any orientation.

[0405] For example, an nc-OS having InGaZnO4 crystals was thinned to a thickness of 34 nm. When an electron beam with a probe diameter of 50 nm is incident on the region in parallel to the surface to be formed, the A ring-shaped diffraction pattern (nanobeam electron diffraction pattern) as shown in (A) was observed. In addition, the diffraction pattern (nano) when an electron beam with a probe diameter of 1 nm is incident on the same sample. The electron diffraction pattern (B) is shown in Figure 26(B). Therefore, nc-OS has a probe diameter of 50 nm. Although the order is not confirmed by irradiating an electron beam, the order is confirmed by irradiating an electron beam with a probe diameter of 1 nm. By projecting the images, order is confirmed.

[0406] In addition, when an electron beam with a probe diameter of 1 nm is incident on an area with a thickness of less than 10 nm, As shown in Figure 26(C), an electron diffraction pattern was observed in which the spots were arranged in a roughly regular hexagonal shape. Therefore, in the range of thickness less than 10 nm, the nc-OS is ordered. It can be seen that the crystals are oriented in various directions. Therefore, there are some areas where no regular electron diffraction pattern is observed.

[0407] FIG. 26(D) shows the Cs-corrected high-resolution image of the cross section of nc-OS observed from a direction approximately parallel to the surface on which the film was formed. The nc-OS is shown in the high-resolution TEM image, with the areas indicated by the auxiliary lines. There are two areas where crystals can be seen, as shown in Fig. 1, and areas where no clear crystals can be seen. The crystal part contained in the nc-OS has a size of 1 nm to 10 nm. In particular, the size is often between 1 nm and 3 nm. An oxide semiconductor having a size of more than 0 nm and not more than 100 nm is called a microcrystalline oxide semiconductor (microcrystalline oxide semiconductor). It is sometimes called a crystalline oxide semiconductor. For example, in the case of nc-OS, the grain boundaries cannot be clearly identified in high-resolution TEM images. It is possible that the nanocrystals originate from the same source as the pellets in CAAC-OS. Therefore, the crystalline part of nc-OS may be referred to as pellets below.

[0408] In this way, the nc-OS can be used in microscopic regions (e.g., regions of 1 nm to 10 nm, especially The atomic arrangement has periodicity in the region of 1 nm to 3 nm. Therefore, no regularity in the crystal orientation is observed between different pellets. Therefore, depending on the analytical method, nc-OS may be classified as a-like OS or amorphous OS. It may be difficult to distinguish it from an oxide semiconductor.

[0409] Since the crystal orientation between the pellets (nanocrystals) is not regular, nc-OS is Oxide with RANC (Random Aligned nanocrystals) Semiconductor or NANC (Non-Aligned nanocrystals) The oxide semiconductor may also be called an oxide semiconductor.

[0410] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. nc-OS has a lower defect state density than a-like OS and amorphous oxide semiconductors. However, there is no regularity in the crystal orientation between different pellets in nc-OS. , the nc-OS has a higher density of defect states than the CAAC-OS.

[0411] <a-like OS> The a-like OS is an oxide semiconductor with a structure between the nc-OS and amorphous oxide semiconductor. It is a conductor.

[0412] Figure 27 shows a high-resolution cross-sectional TEM image of the a-like OS. This is a high-resolution cross-sectional TEM image of the a-like OS at the start of electron irradiation. ) is 4.3 × 10 8 e - / nm 2 electrons (e - ) High a-like OS after irradiation 27(A) and 27(B) show that the a-like OS It can be seen that bright striped regions extending in the vertical direction are observed from the start of electron irradiation. It can be seen that the bright areas change shape after electron irradiation. It is estimated to be in the degree range.

[0413] Because of the porosity, the a-like OS has an unstable structure. To demonstrate that the OS has an unstable structure compared with CAAC-OS and nc-OS. , showing the structural changes caused by electron irradiation.

[0414] The samples prepared were a-like OS, nc-OS, and CAAC-OS. The sample is also an In-Ga-Zn oxide.

[0415] First, high-resolution cross-sectional TEM images of each sample are acquired. Each of these has a crystalline portion.

[0416] The unit cell of the InGaZnO4 crystal has three In-O layers and a Ga-Zn- It is known that it has a structure in which a total of nine layers, including six O layers, are stacked in layers along the c-axis. The spacing between these adjacent layers is the same as the lattice spacing (also called the d value) of the (009) plane. The value is estimated to be 0.29 nm from crystal structure analysis. Below, the area where the lattice spacing is between 0.28 nm and 0.30 nm is InGaZn The lattice fringes correspond to the ab plane of the InGaZnO4 crystal. do.

[0417] Figure 28 shows an example of investigating the average size of the crystal parts (22 to 30 locations) of each sample. The length of the lattice fringes mentioned above is the size of the crystal part. The crystal part of the OS grows in size according to the cumulative amount of electron irradiation used to obtain the TEM image. From Figure 28, it can be seen that in the early stages of TEM observation, the size of the particles was about 1.2 nm. The crystal part (also called the initial nucleus) that was - ) cumulative exposure is 4.2 × 10 8 e - / nm 2 On the other hand, in the case of nc, the size of the crystals grows to about 1.9 nm. The cumulative electron dose from the start of electron irradiation was 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystals within the range of The size of the crystalline parts of nc-OS and CAAC-OS was It can be seen that the thicknesses are approximately 1.3 nm and 1.8 nm, respectively. A Hitachi transmission electron microscope H-9000NAR was used for the TEM observations. The acceleration voltage was 300 kV and the current density was 6.7 × 10 5 e - / (nm 2 ·s), irradiation area The diameter was set to 230 nm.

[0418] In this way, the growth of crystalline parts can be observed in a-like OS due to electron irradiation. On the other hand, in the case of nc-OS and CAAC-OS, the growth of the crystals due to electron irradiation is almost nonexistent. That is, compared with nc-OS and CAAC-OS, It is clear that this is an unstable structure.

[0419] In addition, due to its porosity, a-like OS is more flexible than nc-OS and CAAC-OS. Specifically, the density of a-like OS is lower than that of a single crystal with the same composition. The density of nc-OS is 78.6% or more and less than 92.3% of that of CAAC. The density of the -OS is 92.3% or more but less than 100% of the density of a single crystal of the same composition. It is difficult to form a film of an oxide semiconductor having a density of less than 78% of that of the oxide semiconductor.

[0420] For example, in an oxide semiconductor with an atomic ratio of In:Ga:Zn=1:1:1, The density of single-crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g / cm 3 That is it. For example, in an oxide semiconductor that satisfies the atomic ratio of In:Ga:Zn=1:1:1, , the density of a-like OS is 5.0 g / cm 3 More than 5.9g / cm 3 is less than For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of nc-OS and that of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 is less than.

[0421] If single crystals of the same composition do not exist, single crystals of different compositions can be combined in any ratio. By doing so, it is possible to estimate the density equivalent to that of a single crystal with a desired composition. The density corresponding to a single crystal of a desired composition is calculated by the ratio of the single crystals of different compositions combined. The density can be estimated using a weighted average. However, the density should be calculated by combining as few types of single crystals as possible. It is preferable to estimate them together.

[0422] As described above, oxide semiconductors have a variety of structures, each of which has a variety of properties. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, an nc-OS, A laminated film containing two or more CAAC-OS materials may also be used.

[0423] <Carrier density of oxide semiconductors> Next, the carrier density of an oxide semiconductor will be described below.

[0424] Factors that affect the carrier density in oxide semiconductors include oxygen vacancies in the oxide semiconductor ( Vo), or impurities in the oxide semiconductor.

[0425] When the number of oxygen vacancies in an oxide semiconductor increases, hydrogen bonds to the oxygen vacancies (this state is called VoH). When the oxide semiconductor is doped with a SiO 2 film, the density of defect states increases. When the impurities are added, the density of defect states increases. By controlling the potential density, the carrier density of the oxide semiconductor can be controlled.

[0426] Here, a transistor using an oxide semiconductor for a channel region will be considered.

[0427] Suppression of a negative shift in the threshold voltage of a transistor or suppression of the off-state current of a transistor In order to reduce the carrier density, it is preferable to lower the carrier density of the oxide semiconductor. In order to reduce the carrier density of an oxide semiconductor, the impurity concentration in the oxide semiconductor is In this specification and the like, the impurity concentration is low and the defect level density is low. A low density of recessed levels is called high purity intrinsic or substantially high purity intrinsic. The carrier density of semiconductors is 8×10 15 cm -3 Less than 1 x 10 11 cm -3 less than 1×10 10 cm -3 Less than 1 x 10 -9 cm - 3 That's all there is to it.

[0428] On the other hand, the improvement of the on-state current of the transistor or the field-effect mobility of the transistor In this case, it is preferable to increase the carrier density of the oxide semiconductor. When increasing the carrier density of an oxide semiconductor, the impurity concentration of the oxide semiconductor is slightly increased. Alternatively, the defect state density of the oxide semiconductor may be increased slightly. It is better to make the band gap of the semiconductor smaller. For example, the Id-Vg of a transistor In the range where the on / off ratio of the characteristics can be obtained, the impurity concentration is slightly high or the defect level Oxide semiconductors with slightly higher densities can be considered essentially intrinsic. As a result, the band gap becomes smaller, and as a result, the thermally excited electrons (capacitors) The oxide semiconductor with increased electron affinity can be considered essentially intrinsic. When an oxide semiconductor with high conductivity is used, the threshold voltage of the transistor is lowered. .

[0429] The oxide semiconductor with the increased carrier density is slightly n-type. An oxide semiconductor with an increased carrier density may be called a "slightly-n" oxide semiconductor. stomach.

[0430] The carrier density of a substantially intrinsic oxide semiconductor is 1×10 5 cm -3 More than 1×10 18 c m -3 Less than 1 x 10 is preferable. 7 cm -3 More than 1×10 17 cm -3 The following is preferred: 1×10 9 cm -3 5x10 or more 16 cm -3 Even better: 1 x 10 10 cm -3 More than 1×10 16 cm -3 Even better: 1 x 10 11 cm -3 1 more x10 15 cm -3 The following is even more preferred:

[0431] As described above, this embodiment is similar to other embodiments and the like, at least a part of which is described in this specification. The present invention can be implemented in combination with the above-described embodiments.

[0432] (Embodiment 3) In this embodiment, a semiconductor device including a transistor according to one embodiment of the present invention will be described. An example of the circuit will be described.

[0433] <Circuit> An example of a circuit of a semiconductor device using a transistor or the like according to one embodiment of the present invention will be described below. We will explain about this.

[0434] <CMOSインバータ> The circuit diagram shown in FIG. 29(A) includes a p-channel transistor 2200 and an n-channel transistor 2201. Transistor 2100 is connected in series and each gate is connected, so-called CMO The circuit shown in FIG. 29(A) is a circuit diagram of an S inverter. 200 using the transistor 60a shown in FIG. 12 or the transistor 60b shown in FIG. 18. The transistor 2100 can be formed by using the transistor 90a shown in FIG. It can be formed using transistor 90b.

[0435] The semiconductor device shown in FIG. 29(A) is a semiconductor device in which a p-channel transistor is formed using a semiconductor substrate. By fabricating a thin film transistor and fabricating an n-channel transistor above it, the area occupied by the element can be reduced. In other words, the degree of integration of the semiconductor device can be increased. A p-channel transistor and a p-channel transistor are fabricated using the same semiconductor substrate. Since the process can be simplified compared to the conventional method, the productivity of semiconductor devices can be increased. Furthermore, the yield of the semiconductor device can be increased. The transistor has an LDD (Lightly Doped Drain) region, a shallow It may be possible to omit complex processes such as wrench structure and distortion design. Compared to fabricating a silicon-doped transistor using a semiconductor substrate, productivity and yield are improved. It may be possible to make it higher.

[0436] <CMOSアナログスイッチ> The circuit diagram shown in FIG. 29(B) is that of the transistor 2100 and the transistor 2200. The figure shows a configuration in which the source and drain of each transistor are connected. It can function as a so-called CMOS analog switch. The circuit shown in FIG. 13 is similar to that shown in FIG. 12, except that transistor 2200 is replaced by transistor 60a shown in FIG. 12 or transistor 60b shown in FIG. 15. The transistor 2100 can be formed using the transistor 60b shown in FIG. This can be formed using transistor 90a or transistor 90b shown.

[0437] <Storage device 1> A transistor according to one embodiment of the present invention is used to retain stored contents even when power is not supplied. An example of a semiconductor device (memory device) that can be stored and has no limit on the number of times it can be written is shown in FIG. Shown below.

[0438] The semiconductor device shown in FIG. 30A includes a transistor 3200 using a first semiconductor and a second The semiconductor device includes a transistor 3300 and a capacitor 3400. The transistor 3300 is the same as the transistor 2100 described above. Here, the transistor 3200 is configured with the above-mentioned element layer 50, and the transistor The capacitor 3300 is formed by the element layer 30, and the capacitor 3400 is formed by the element layer 40. Therefore, the circuit shown in FIG. 30A can be formed using the semiconductor device shown in FIG. 19 or the like. .

[0439] The transistor 3300 preferably has a low off-state current. For example, a transistor including an oxide semiconductor can be used as the transistor 00. The small off-state current of the capacitor 3300 allows for long-term recording at a specific node of the semiconductor device. It is possible to retain the memory contents, i.e., no refresh operation is required, or This allows the frequency of refresh operations to be reduced significantly, resulting in low power consumption semiconductors. It becomes a body device.

[0440] In FIG. 30A, a first wiring 3001 is electrically connected to the source of a transistor 3200. The second wiring 3002 is electrically connected to the drain of the transistor 3200. The third wiring 3003 is electrically connected to one of the source and drain of the transistor 3300. The fourth wiring 3004 is electrically connected to the gate of the transistor 3300. The gate of the transistor 3200 and the source of the transistor 3300 are connected to each other. The other of the drains is electrically connected to one of the electrodes of the capacitor 3400 and is connected to the fifth wiring 30 05 is electrically connected to the other electrode of the capacitor 3400 .

[0441] The semiconductor device shown in FIG. 30A can hold the potential of the gate of the transistor 3200. This property makes it possible to write, store, and read information, as shown below. do.

[0442] Writing and holding of information will be described. First, the potential of the fourth wiring 3004 is changed by a transistor. The transistor 3300 is set to a potential at which it becomes conductive, thereby making the transistor 3300 conductive. As a result, the potential of the third wiring 3003 is applied to the gate of the transistor 3200 and the capacitor The voltage is applied to a node FG electrically connected to one of the electrodes of the capacitor 3400. A predetermined charge is applied to the gate of the register 3200 (write). Charges that give two potential levels (hereinafter referred to as low-level charge and high-level charge) Then, the potential of the fourth wiring 3004 is applied to the transistor. The transistor 3300 is set to a potential at which it is in a non-conductive state, thereby making the transistor 3300 in a non-conductive state. As a result, charge is held at the node FG (retention).

[0443] Since the off-state current of the transistor 3300 is small, the charge of the node FG is retained for a long time. It will be held.

[0444] Next, reading of information will be described. A predetermined potential (constant potential) is applied to the first wiring 3001. When an appropriate potential (read potential) is applied to the fifth wiring 3005 in this state, the second wiring 3002 takes a potential according to the amount of charge held in the node FG. If 3200 is an n-channel type, a high level charge is applied to the gate of transistor 3200. The apparent threshold voltage V th_H is the transistor 3200 Apparent threshold voltage V when a low-level charge is applied to the gate th_L Yo Here, the apparent threshold voltage is the voltage at which the transistor 3200 is This refers to the potential of the fifth wiring 3005 required to make it "conductive." The potential of the fifth wiring 3005 is V th_H and V th_L By setting the potential V0 between For example, in a write operation, the charge applied to node FG can be determined. When a high level charge is applied to the fifth wiring 3005, the potential of the fifth wiring 3005 becomes V0 (> V th_H ), the transistor 3200 is in a "conducting state." Meanwhile, the node FG When a low level charge is applied to the fifth wiring 3005, the potential of the fifth wiring 3005 becomes V0 ( <V th_L ), transistor 3200 remains in a "non-conducting state." By determining the potential of the second wiring 3002, the data stored in the node FG is read. You can put it out.

[0445] When memory cells are arranged in an array, the information of the desired memory cell is read. For example, in a memory cell that does not read information, The voltage at which transistor 3200 is in a "non-conducting state" regardless of the charge applied to the FG. Place, that is, V th_H By applying a lower potential to the fifth wiring 3005, a desired memory Alternatively, the charge applied to the node FG can be read out. The potential at which transistor 3200 is in a "conducting state" regardless of the th_L twist By applying a high potential to the fifth wiring 3005, only the information in the desired memory cell can be read out. This can be configured as follows.

[0446] In the above, an example in which two types of charges are held in the node FG is shown. The semiconductor device according to the present invention is not limited to this. For example, It is also possible to configure the node so that three or more types of charges can be held in the node. This allows the semiconductor device to be multi-valued, thereby increasing the storage capacity.

[0447] <Storage device 2> The semiconductor device shown in FIG. 30B differs from the semiconductor device shown in FIG. 30A in that it does not include the transistor 3200. In this case, the operation is the same as that of the semiconductor device shown in FIG. This allows for writing and holding of information. Transistor 3300 may be replaced by transistor 60a shown in FIG. 12 or transistor 60b shown in FIG. 17. The capacitor 3400 can be formed using the capacitor 60b. Furthermore, a semiconductor device shown in FIG. In this case, a transistor 90a shown in FIG. Alternatively, it can be formed using transistor 90b.

[0448] The reading of data from the semiconductor device shown in FIG. When the capacitor 3300 is brought into a conductive state, the third wiring 3003 and the capacitor element 3400, which are in a floating state, The third wiring 3003 and the capacitor 3400 are electrically connected to each other, and charge is redistributed between the third wiring 3003 and the capacitor 3400. As a result, the potential of the third wiring 3003 changes. The amount of change in the potential of the third wiring 3003 is determined by the capacitance The potential of one of the electrodes of the element 3400 (or the charge stored in the capacitor element 3400) , take different values.

[0449] For example, the potential of one electrode of the capacitor 3400 is V, the capacitance of the capacitor 3400 is C, and the third The capacitance component of the third wiring 3003 before the charge is redistributed is CB. If the potential is VB0, the potential of the third wiring 3003 after the charge is redistributed is (CB× Therefore, the state of the memory cell is If the potential of one of the 3400 electrodes takes two states, V1 and V0 (V1>V0), then: The potential of the third wiring 3003 when the potential V1 is maintained (=(CB×VB0+CV1) / (CB+C)) is the potential (=(C It can be seen that this is higher than B×VB0+CV0) / (CB+C)).

[0450] Then, the potential of the third wiring 3003 is compared with a predetermined potential, thereby reading out information. can be done.

[0451] In this case, the transistor to which the first semiconductor is applied is used in a drive circuit for driving the memory cell. A transistor to which a second semiconductor is applied is used as the transistor 3300. The structure may be such that the electrodes are stacked on the drive circuit.

[0452] The semiconductor device described above uses a transistor including an oxide semiconductor and having low off-state current. By doing so, it is possible to retain the memory contents for a long period of time. This eliminates the need for refresh operations or makes it possible to reduce the frequency of refresh operations significantly. Therefore, a semiconductor device with low power consumption can be realized. Even if the potential is fixed, it is possible to store the data for a long period of time. It is possible to maintain the volume.

[0453] Furthermore, since the semiconductor device does not require a high voltage to write information, deterioration of the elements does not occur. For example, unlike conventional nonvolatile memory, injection of electrons into the floating gate Since electrons are not introduced or extracted from the floating gate, there is no risk of insulator degradation. That is, the semiconductor device according to one embodiment of the present invention does not have the same problem as a conventional nonvolatile memory. There is no limit to the number of times that data can be rewritten, which is a problem, and the reliability of this semiconductor device has been dramatically improved. Furthermore, information is written depending on whether the transistor is conductive or non-conductive. This allows for high-speed operation.

[0454] <Storage device 3> Regarding a modification of the semiconductor device (memory device) shown in FIG. 30(A), a circuit diagram shown in FIG. 31 is used. and explain.

[0455] The semiconductor device illustrated in FIG. 31 includes transistors 4100 to 4400 and a capacitor. The transistor 4100 has a capacitor 4500 and a capacitor 4600. A transistor similar to the transistor 3200 can be used, and the transistor 420 0 to 4400 can be transistors similar to the transistor 3300 described above. Although not shown in FIG. 31, the semiconductor device shown in FIG. 31 can be implemented in a matrix. The semiconductor device shown in FIG. 31 includes a wiring 4001, a wiring 4003, and a wiring 400 5 to 4009, the writing and reading of the data voltage is controlled according to the signal or potential applied to Here, the circuit shown in FIG. 31 can be controlled by replacing transistor 4100 with the transistor shown in FIG. The transistor 90a or 90b may be used to form the transistor The transistors 4200, 4300 and 4400 are the transistors shown in FIG. 13. The capacitor 60a can be formed using the transistor 60b shown in FIG. The element 4500 and the capacitance element 4600 are formed using the capacitance element 80a shown in FIG. This can be done.

[0456] One of the source and the drain of the transistor 4100 is connected to a wiring 4003. The other of the source and the drain of the transistor 4100 is connected to a wiring 4001. In FIG. 33, the conductivity type of the transistor 4100 is shown as a p-channel type. That's fine too.

[0457] The semiconductor device shown in FIG. 31 has two data holding units. For example, the first data holding unit is , one of the source and drain of the transistor 4400 connected to the node FG1, One electrode of the element 4600 and one of the source and drain of the transistor 4200 The second data storage unit stores a charge between the transistor connected to node FG1 and the transistor connected to node FG2. the gate of the transistor 4100, the other of the source or drain of the transistor 4200, One of the source or drain of the transistor 4300 and one of the electrodes of the capacitor element 4500 The charge is held between

[0458] The other of the source and the drain of the transistor 4300 is connected to a wiring 4003. The other of the source and drain of the transistor 4400 is connected to a wiring 4001. The gate of the transistor 4400 is connected to the wiring 4005. The gate of the transistor 4300 is connected to a wiring 4006. The gate of the transistor 4300 is connected to a wiring 4007. The other electrode of the capacitor 4600 is connected to the wiring 4008. The other electrode of 00 is connected to a wiring 4009 .

[0459] The transistors 4200 to 4400 are transistors that control writing of data voltages and retention of charges. Note that the transistors 4200 to 4400 are in a non-conducting state. In this case, a transistor with a low current (off-state current) that flows between the source and drain is used. As a transistor with a low off-state current, a transistor having an oxidized layer in a channel formation region is preferably used. Preferably, the transistor is an OS transistor. The transistor has advantages such as low off-state current and the ability to be stacked with a silicon-containing transistor. In FIG. 33, the conductivity types of the transistors 4200 to 4204 are n-channel. However, it may be a p-channel type.

[0460] The transistors 4200, 4300, and 4400 are oxidized. Even if the transistor uses a compound semiconductor, it is preferable to provide it in a separate layer. The semiconductor device shown in FIG. 1 includes a first layer 4 having a transistor 4100 as shown in FIG. 021 and a second layer 4022 having transistors 4200 and 4300. and a third layer 4023 having a transistor 4400. By stacking layers having transistors, the circuit area can be reduced, and This allows for the body device to be made smaller.

[0461] Next, the operation of writing information into the semiconductor device shown in FIG. 31 will be described.

[0462] First, a data voltage write operation (hereinafter, ) will be described below. The data voltage written to the data storage unit is V D1 and the threshold voltage of the transistor 4100 is The voltage is Vth.

[0463] In write operation 1, the wiring 4003 is connected to V D1 Then, after setting the wiring 4001 to the ground potential, The wirings 4005 and 4006 are set to a high level. 007 to 4009 are set to low level. Then, the node FG2 in an electrically floating state The potential of the wiring 40 increases, and a current flows through the transistor 4100. The potential of the transistor 4400 and the transistor 4200 are turned on. Therefore, as the potential of the wiring 4001 increases, the potentials of the nodes FG1 and FG2 also increase. The potential of the node FG2 rises, and a potential difference between the gate and source of the transistor 4100 is When the voltage (Vgs) reaches the threshold voltage Vth of the transistor 4100, the transistor 410 Therefore, the potential of the wiring 4001 and the nodes FG1 and FG2 is The rise stopped, and V D1 Vth has dropped from D1 -Vth" and becomes constant.

[0464] In other words, the V given to wire 4003 D1 When a current flows through the transistor 4100, The potential is applied to the wiring 4001, and the potentials of the nodes FG1 and FG2 increase. , the potential of node FG2 is "V D1 -Vth", the Vgs of transistor 4100 is Vth is reached, and the current stops.

[0465] Next, the data voltage is written to the data storage unit connected to the node FG2 (hereinafter, the write This is called write operation 2. The data voltage written to the part is V D2 It will be explained as follows.

[0466] In write operation 2, wire 4001 is connected to V D2 Then, after setting the wiring 4003 to the ground potential, The wiring 4007 is set to a high level. 4006, 4008, and 4009 are set to low level. Transistor 4300 is set to the conductive state. Therefore, the potential of the node FG2 is also set to low. The voltage of the wiring 4003 decreases as the voltage of the wiring 4003 decreases. The potential of the wiring 4003 increases. As the potential at node FG2 rises, the potential at node FG2 also rises. When Vgs of transistor 4100 becomes Vth of transistor 4100, transistor 4 The current flowing through 100 becomes smaller. Therefore, the potential of wiring 4003 and FG2 does not stop rising. Ri, V D2 Vth has dropped from D2 -Vth" and becomes constant.

[0467] In other words, the V given to wire 4001 D2 When a current flows through the transistor 4100, The potential of the node FG2 is increased by the increase in the potential. The potential of FG2 is "V D2 -Vth", Vgs of transistor 4100 is Vth. At this time, the potential of the node FG1 is 400 are in a non-conductive state, and the "V D1 -Vth" is maintained can be.

[0468] In the semiconductor device shown in FIG. 33, after writing data voltages to a plurality of data holding units, 4009 is set to high level, and the potentials of the nodes FG1 and FG2 are raised. The transistor is made non-conductive, preventing the movement of charge and maintaining the written data voltage. .

[0469] By the above-described operation of writing data voltages to the nodes FG1 and FG2, multiple data The data voltage can be held in the data holding section. D 1-Vth" and "V D2 -Vth" was used as an example, but these are multi-value data. Therefore, each data storage unit stores 4 bits of data. When holding 16 values of "V D1 -Vth" and "V D2 -Vth" can be used.

[0470] Next, the operation of reading information from the semiconductor device shown in FIG. 31 will be described.

[0471] First, the data voltage is read from the data storage unit connected to the node FG2 (hereinafter, This will be referred to as read operation 1.

[0472] In the read operation 1, the wiring 4003 is precharged and then brought into an electrically floating state. The wirings 4005 to 4008 are set to a low level. The potential of the electrically floating node FG2 is set to "V D2 -Vth" When the potential of the node FG2 decreases, a current flows through the transistor 4100. The flow of current reduces the potential of the electrically floating wiring 4003. As the voltage Vgs of transistor 4100 decreases, the voltage Vgs of transistor 4100 decreases. When Vgs becomes Vth of the transistor 4100, the current flowing through the transistor 4100 becomes That is, the potential of the wiring 4003 becomes smaller than the potential of the node FG2 “V D2 -Vth" Vth is larger than Vth. D2 The potential of the wiring 4003 is The data voltage of the data storage section connected to G2 corresponds to the data of the analog value that is read out. The voltage of the capacitor undergoes A / D conversion and acquires data from the data storage section connected to node FG2. .

[0473] That is, the wiring 4003 after precharging is in a floating state, and the potential of the wiring 4009 is set to a high level. Switching the voltage from high to low allows current to flow through transistor 4100. As a result, the potential of the wiring 4003, which was in a floating state, drops to "V D2 ". Tran In register 4100, the "V D2 Vgs between "-Vth" is Vth The current stops. Then, the wiring 4003 is connected to the "V D2 " is read out.

[0474] After acquiring the data of the data storage section connected to node FG2, transistor 4300 is turned on. In the conductive state, the "V D2 -Vth" is discharged.

[0475] Next, the charge held at node FG1 is distributed to node FG2, and the The data voltage of the data storage unit connected to node FG1 is transferred to the data storage unit connected to node FG2. The wiring 4001 and 4003 are set to low level, and the wiring 4006 is set to high level. , the wiring 4005 and the wirings 4007 to 4009 are set to low level. is turned on, the charge of the node FG1 is shared with the node FG2.

[0476] Here, the potential after the charge distribution is the written potential "V D1 -Vth" and Therefore, the capacitance value of the capacitor 4600 is set to be larger than the capacitance value of the capacitor 4500. Alternatively, the potential "V D1 -Vth" is the same data The potential "V D2 It is preferable to set the capacitance value to be larger than "-Vth". By changing the ratio of the potential and increasing the potential to be written in advance, the potential after the charge distribution can be reduced. The fluctuation of the potential due to the distribution of the charge will be described later.

[0477] Next, a data voltage is read from the data storage unit connected to the node FG1 (hereinafter referred to as a read This is called "read-out operation 2.") will be explained below.

[0478] In the read operation 2, the wiring 4003 is precharged and then placed in an electrically floating state. The wirings 4005 to 4008 are set to a low level. It is set to high level during precharge and then to low level. By using this as a pin, the electrically floating node FG2 is set to the potential "V D1 -Vth" When the potential of the node FG2 decreases, a current flows through the transistor 4100. As a result, the potential of the wiring 4003 in an electrically floating state is reduced. As the voltage drops, the Vgs of transistor 4100 decreases. When gs becomes Vth of the transistor 4100, the current flowing through the transistor 4100 becomes small. That is, the potential of the wiring 4003 becomes lower than the potential of the node FG2 “V D1 -Vth" or Vth is larger than Vth. D1 The potential of the wiring 4003 is The analog value data read out corresponds to the data voltage of the data storage section connected to 1. The voltage undergoes A / D conversion, and data is acquired from the data storage unit connected to node FG1. The above is the operation of reading out the data voltage to the data holding unit connected to node FG1.

[0479] That is, the wiring 4003 after precharging is in a floating state, and the potential of the wiring 4009 is set to a high level. Switching the voltage from high to low allows current to flow through transistor 4100. As a result, the potential of the wiring 4003, which was in a floating state, drops to "V D1 ". Tran In register 4100, the "V D1 Vgs between "-Vth" is Vth The current stops. Then, the wiring 4003 is connected to the "V D1 " is read out.

[0480] By the above-described operation of reading the data voltages from the nodes FG1 and FG2, a plurality of data For example, the data voltage can be read from the data storage unit. FG2 stores 4 bits (16 values) of data, for a total of 8 bits (256 values) In FIG. 31, the first layer 4021 to the third layer 4022 can store data. However, by forming further layers, the surface of the semiconductor device can be It is possible to increase the storage capacity without increasing the product.

[0481] The potential that is read out is a voltage that is Vth higher than the written data voltage. Therefore, the "V D1 -Vth" and "V D2 - As a result, the Vth of the memory cell can be offset and read. This improves the storage capacity per memory and also brings the read data closer to the correct data. This allows for excellent data reliability.

[0482] <Storage device 4> The semiconductor device shown in FIG. 30C includes a transistor 3500 and a sixth wiring 3006. This is different from the semiconductor device shown in FIG. It is possible to write and store information by the same operation as the device. The transistor 3500 may be the same as the transistor 3200 described above. Here, the transistor 3200 and the transistor 3500 are configured in the element layer 50, The transistor 3300 is formed by the element layer 30, and the capacitance element 3400 is formed by the element layer 40. By configuring it, the circuit shown in FIG. 30A can be formed using the semiconductor device shown in FIG. Here, the circuit shown in FIG. 30C includes a transistor 3200 and a transistor 3500 is formed using transistor 90a or transistor 90b shown in FIG. 12 or transistor 60a shown in FIG. 13. The capacitor element 3400 can be formed using the transistor 60b shown in FIG. The capacitor 80a can be used to form the capacitor.

[0483] The sixth wiring 3006 is electrically connected to the gate of the transistor 3500. One of the source and drain of the transistor 3500 is electrically connected to the drain of the transistor 3200. The other of the source and drain of the transistor 3500 is electrically connected to a third wiring 3003. Connected.

[0484] This embodiment may be implemented in any manner other than as described, at least in part, herein. The present invention can be implemented in combination with the examples as appropriate.

[0485] (Fourth embodiment) In this embodiment, a circuit configuration to which the OS transistor described in the above embodiment can be applied is described. An example of this will be described with reference to FIGS.

[0486] 32A shows a circuit diagram of the inverter. The inverter 800 receives the voltage at the input terminal IN. The inverter 800 outputs a signal whose logic is inverted from the output terminal OUT. The OS transistor is included. BG The electrical characteristics of the OS transistor can be switched. This is a signal that can be used.

[0487] FIG. 32B shows an example of an inverter 800. The inverter 800 is an OS transistor. The inverter 800 includes an n-channel Since it can be made with transistors, it is called CMOS (Complementary Metal Oxide Semiconductor) Inverter (CMOS inverter) by Etal Oxide Semiconductor It can be produced at a lower cost than when producing a silicon wafer (a silicon wafer).

[0488] The inverter 800 having OS transistors is a CM inverter made of Si transistors. The inverter 800 can be placed on the OS. Therefore, it is possible to suppress an increase in the circuit area due to the addition of the inverter 800.

[0489] The OS transistors 810 and 820 have a first gate that functions as a front gate and a back gate. The second gate acts as a gate and the first gate acts as either a source or a drain. a terminal and a second terminal that functions as the other of the source or drain.

[0490] The first gate of OS transistor 810 is connected to the second terminal. The second gate of 0 is the signal S BG The OS transistor 810 is connected to a wiring that supplies The first terminal of the OS transistor 810 is connected to a wiring that supplies a voltage VDD. is connected to the output terminal OUT.

[0491] A first gate of the OS transistor 820 is connected to the input terminal IN. The second gate of the OS transistor 820 is connected to the input terminal IN. The second terminal of the OS transistor 820 is connected to the output terminal OUT. Connected to the wiring.

[0492] FIG. 32C is a timing chart for explaining the operation of the inverter 800. In FIG. In the timing chart of Figure 32(C), the signal waveform of the input terminal IN and the signal waveform of the output terminal OUT are signal waveform, signal S BG and the threshold value of the OS transistor 810 (FET 810). The voltage change is shown.

[0493] signal S BG is applied to the second gate of the OS transistor 810, The threshold voltage of 10 can be controlled.

[0494] signal S BG is the voltage V for shifting the threshold voltage negatively BG_A , threshold voltage Voltage V BG_B The second gate has a voltage V BG_A To give As a result, the OS transistor 810 has a threshold voltage V TH_A can be negatively shifted to Also, the second gate is supplied with a voltage V BG_B By providing Voltage V TH_B can be shifted positively to

[0495] To visualize the above explanation, FIG. 33(A) shows one of the electrical characteristics of a transistor. The Vg-Id curve is shown.

[0496] The electrical characteristics of the OS transistor 810 described above are as follows: BG_A Noyo By increasing the value as shown in FIG. 33(A), the curve is shifted to the dashed line 840. The electrical characteristics of the OS transistor 810 can be determined by applying a voltage to the second gate. Pressure V BG_B By making it smaller, the curve shown by the solid line 841 in Figure 33(A) As shown in FIG. 33A, the OS transistor 810 can shift the signal No.S BG voltage V BG_A Or voltage V BG_B By switching like this, the threshold The voltage can be shifted either positively or negatively.

[0497] The threshold voltage is V TH_B By shifting the voltage to the positive side, the OS transistor 810 This makes it difficult for current to flow. Figure 33(B) shows this state in a visualized manner. As shown in FIG. 33B, the current I B To the utmost Therefore, when the signal applied to the input terminal IN is high level, the OS transistor When the transistor 820 is in the ON state (ON), it causes the voltage at the output terminal OUT to drop sharply. This can be done.

[0498] As shown in FIG. 33B, a state in which a current is difficult to flow through the OS transistor 810 Therefore, the signal at the output terminal in the timing chart shown in FIG. 32(C) can be The signal waveform 831 can be changed sharply. This reduces the through current that flows between the wiring that supplies the signal, allowing for low power consumption. You can perform the work.

[0499] Also, the threshold voltage is V TH_A By shifting the voltage to the negative side, the OS transistor 810 can be made to be in a state where current can easily flow. This state is shown in FIG. As shown in Figure 33(C), the current I A At least the current I B Therefore, when the signal applied to the input terminal IN is low level, When the OS transistor 820 is in the OFF state, the voltage of the output terminal OUT is rapidly increased. It can be increased.

[0500] As shown in FIG. 33C, a current easily flows through the OS transistor 810. Therefore, the signal at the output terminal in the timing chart shown in FIG. 32(C) can be The signal waveform 832 can be changed sharply.

[0501] In addition, signal S BG The control of the threshold voltage of the OS transistor 810 by It is preferable to perform this before the state of 820 changes, that is, before time T1 or T2. For example, as shown in FIG. 32(C), when the signal applied to the input terminal IN is switched to a high level, Before the time T1 at which the voltage is switched, the threshold voltage V TH_A to threshold voltage V TH_B OS Trans It is preferable to switch the threshold voltage of the resistor 810. Also, as shown in FIG. As shown in the figure, the threshold voltage Vth falls before time T2 when the signal applied to the input terminal IN switches to low level. Pressure V TH_B to threshold voltage V TH_A Switching the threshold voltage of the OS transistor 810 It is preferable.

[0502] In the timing chart of FIG. 32(C), the signal S BG However, other configurations may be used. For example, a configuration for controlling the threshold voltage The voltage for this is held at the second gate of the OS transistor 810 in a floating state. An example of a circuit configuration that can realize this configuration is shown in FIG. show.

[0503] 34A, in addition to the circuit configuration shown in FIG. 32B, an OS transistor 850 is The first terminal of OS transistor 850 is connected to the second gate of OS transistor 810. The second terminal of the OS transistor 850 is connected to the voltage V BG_B (or voltage V BG_A The first gate of the OS transistor 850 is connected to a wiring that supplies a signal S F The second gate of the OS transistor 850 is connected to a line that supplies a voltage V BG_ B (or voltage V BG_A ) is connected to the wiring that provides

[0504] The operation of FIG. 34(A) will be described using the timing chart of FIG. 34(B).

[0505] The voltage for controlling the threshold voltage of the OS transistor 810 is a signal applied to the input terminal IN. is switched to a high level at time T3, the second gate of the OS transistor 810 The signal S F is set to a high level to turn on the OS transistor 850. , node N BG Voltage V for controlling the threshold voltage BG_B Give.

[0506] Node N BG is the voltage V BG_B After this, the OS transistor 850 is turned off. The OS transistor 850 has an extremely small off-state current. , node N BG is set to a state close to floating, and then the node N BG held in The applied voltage V BG_B Therefore, the first voltage of the OS transistor 850 can be maintained. 2. Gate voltage V BG_B The number of operations to give the voltage V BG_B To rewrite This can reduce the power consumption required.

[0507] In the circuit configurations of FIGS. 32B and 34A, the second gate of OS transistor 810 Although the configuration in which the voltage applied to the port is controlled externally has been shown, a different configuration can be used. For example, the voltage for controlling the threshold voltage may be set based on the signal applied to the input terminal IN. The second gate of the OS transistor 810 may be provided with the second gate of the OS transistor 810. An example of a possible circuit configuration is shown in FIG.

[0508] In Fig. 35(A), the input terminal IN and the OS transformer are connected in the circuit configuration shown in Fig. 32(B). A CMOS inverter 860 is provided between the second gate of the transistor 810 and the second gate of the transistor 810. The input terminal of the CMOS inverter 860 is connected to the input terminal IN. The terminal is connected to the second gate of OS transistor 810.

[0509] The operation of FIG. 35(A) will be explained using the timing chart of FIG. 35(B). In the timing chart of 35(B), the signal waveform of the input terminal IN and the signal of the output terminal OUT are waveform, the output waveform IN_B of the CMOS inverter 860, and the OS transistor 810 ( FET 810).

[0510] The output waveform IN_B, which is the inverted signal of the signal applied to the input terminal IN, is The signal can be used to control the threshold voltage of the resistor 810. As described in (C) to (D), the threshold voltage of the OS transistor 810 can be controlled. At time T4 in FIG. 35(B), the signal applied to the input terminal IN is at a high level. The OS transistor 820 is turned on. At this time, the output waveform IN_B is at a low level. Therefore, the OS transistor 810 can be made to be in a state where it is difficult for current to flow, and the output This allows the voltage at the output terminal OUT to drop sharply.

[0511] At time T5 in FIG. 35(B), the signal applied to the input terminal IN is at a low level. At this time, the OS transistor 820 is turned off. At this time, the output waveform IN_B is at a high level. Therefore, the OS transistor 810 can be made to be in a state where current easily flows. The voltage at the output terminal OUT can be increased sharply.

[0512] As described above, in the configuration of this embodiment, in the inverter having the OS transistor, The back gate voltage is switched according to the logic of the signal at the input terminal IN. By configuring the OS transistor as a gate, the threshold voltage of the OS transistor can be controlled. The threshold voltage of the OS transistor is controlled by the signal supplied to the output terminal OUT. It is also possible to reduce the through current between the wiring that supplies the power supply voltage. Therefore, it is possible to reduce power consumption.

[0513] This embodiment may be implemented in any manner other than as described, at least in part, herein. The present invention can be implemented in combination with the examples as appropriate.

[0514] (Embodiment 5) In this embodiment, a plurality of circuits each having the OS transistor described in the above embodiment are An example of a semiconductor device having such a structure will be described with reference to FIGS.

[0515] 36A is a block diagram of a semiconductor device 900. The semiconductor device 900 includes a power supply circuit 901, a circuit 902, a voltage generating circuit 903, a circuit 904, a voltage generating circuit 905, and a circuit It has 906.

[0516] The power supply circuit 901 supplies a reference voltage V ORG This is a circuit that generates a voltage V ORG is simply It is possible to use multiple voltages instead of a single voltage. ORG is input from the outside of the semiconductor device 900. The semiconductor device 900 can generate the voltage V based on the externally applied voltage V0. The voltage V ORG Therefore, the semiconductor device 900 can generate It can operate without receiving multiple power supply voltages from the unit.

[0517] The circuits 902, 904, and 906 are circuits that operate on different power supply voltages. The power supply voltage of the 902 is V ORG and voltage V SS (V ORG >V SS ) and applied based on For example, the power supply voltage of the circuit 904 is a voltage V POG and voltage V SS (V P OG >V ORG ) is a voltage applied based on the above. For example, the power supply voltage of the circuit 906 is , voltage V ORG and voltage V NEG (V ORG >V SS >V NEG ) and the applied voltage based on The voltage V SS If the potential is the same as the ground potential (GND), the power supply circuit 90 1 can reduce the number of voltage types generated.

[0518] The voltage generating circuit 903 generates a voltage V POG The voltage generating circuit 903 is a circuit that generates a voltage. The voltage V given by the power supply circuit 901 ORG Based on the voltage V POG Therefore, The semiconductor device 900 having the circuit 904 operates based on a single power supply voltage applied from the outside. It is possible.

[0519] The voltage generating circuit 905 generates a voltage V NEG The voltage generating circuit 905 is a circuit that generates a voltage. The voltage V given by the power supply circuit 901 ORG Based on the voltage V NEG Therefore, The semiconductor device 900 having the circuit 906 operates based on a single power supply voltage provided from the outside. It is possible.

[0520] Figure 36(B) shows the voltage V POG FIG. 36C shows an example of the circuit 904 operating in 10 is an example of a waveform of a signal for operation.

[0521] FIG. 36B shows a transistor 911. The signal that can be output is, for example, a voltage V POG and voltage V SS The signal is generated based on the When resistor 911 is in the conducting state, the voltage V POG , and when operating in a non-conducting state, the voltage V SS Voltage V POG As shown in Figure 36(C), the voltage V ORG Greater than Therefore, the transistor 911 can more reliably connect the source (S) and the drain (D). As a result, the circuit 904 can be a circuit with reduced malfunction. do.

[0522] Figure 36(D) shows the voltage V NEG FIG. 36(E) shows an example of a circuit 906 that operates in the 10 is an example of a waveform of a signal for operation.

[0523] FIG. 36D shows a transistor 912 having a back gate. The signal applied to the gate of the capacitor 912 is, for example, a voltage V ORG and voltage V SS Generated based on This signal is applied to the transistor 911 at a voltage V ORG , non-conducting When operating in this state, the voltage V SS Also, the back gate of the transistor 912 is generated based on The signal applied to the port is voltage V NEG It is generated based on the voltage V NEG is shown in Figure 36(E). As shown, the voltage V SS (GND). Therefore, the threshold voltage of transistor 912 The value voltage can be controlled to be shifted to the positive side. 2 can be more reliably put into a non-conducting state, and the current between the source (S) and the drain (D) can be As a result, the circuit 906 has reduced malfunctions and low power consumption. This allows for a highly simplified circuit.

[0524] Furthermore, the voltage V NEG may be directly applied to the back gate of the transistor 912. Or, voltage V ORG and voltage V NEG is applied to the gate of transistor 912 based on A signal may be generated and applied to the back gate of the transistor 912. .

[0525] Also, FIGS. 37(A) and (B) show modified examples of FIGS. 36(D) and (E).

[0526] In the circuit diagram shown in FIG. 37A, a control circuit is provided between the voltage generating circuit 905 and the circuit 906. The transistor 922 whose conduction state can be controlled by the transistor 921 is shown. , an n-channel OS transistor. BG teeth , which is a signal for controlling the conduction state of the transistor 922. Transistors 912A and 912B are OS transistors like transistor 922.

[0527] In the timing chart of FIG. 37(B), the control signal S BG The change in the potential of the transistor The potential state of the back gates of the transistors 912A and 912B is determined by the node N BG Shown by the change in potential Control signal S BG When the voltage at the node N BG is the voltage V NEG Then, the control signal S BG When is low, node N BG is electrically floating. , the off-current is small. Therefore, the node N BG Even if the The applied voltage V NEG can be maintained.

[0528] FIG. 38A shows an example of a circuit configuration applicable to the voltage generating circuit 903. The voltage generating circuit 903 shown in FIG. 38A includes diodes D1 to D5 and a capacitor C1. The charge pump is a five-stage charge pump having C1 to C5 and an inverter INV. CLK is applied to capacitors C1 through C5 either directly or through an inverter INV. The power supply voltage of the inverter INV is set to voltage V ORG and voltage V SS and the applied voltage based on Then, by applying the clock signal CLK, the voltage V ORG rises to a positive voltage five times higher The applied voltage V POG The forward voltages of the diodes D1 to D5 can be obtained. is set to 0V. Also, by changing the number of stages of the charge pump, the desired voltage V POG can be obtained.

[0529] FIG. 38B shows an example of a circuit configuration applicable to the voltage generating circuit 905. The voltage generating circuit 905 shown in FIG. 38B includes diodes D1 to D5 and a capacitor C1 The charge pump is a four-stage charge pump having C1, C2, C3, C4, C5, and an inverter INV. CLK is applied to capacitors C1 through C5 either directly or through an inverter INV. The power supply voltage of the inverter INV is set to voltage V ORG and voltage V SS and the applied voltage based on Then, by applying a clock signal CLK, the ground, that is, the voltage V SS to voltage V ORG The voltage V is stepped down to a negative voltage four times that of NEG It can be obtained. The forward voltage of the diodes D1 to D5 is set to 0 V. The number of stages of the charge pump is By changing the NEG can be obtained.

[0530] The circuit configuration of the voltage generating circuit 903 is not limited to the configuration shown in the circuit diagram of FIG. Modifications of the voltage generating circuit 903 are shown in FIGS. 39(A) to 39(C) and 40(A) and 40(B). show.

[0531] The voltage generating circuit 903A shown in FIG. 39A includes transistors M1 to M10, a capacitor The clock signal CLK is supplied to the transistors C11 to C14 and the inverter INV1. The voltages are applied to the gates of the transistors M1 to M10 either directly or via an inverter INV1. By applying a clock signal CLK, the voltage V ORG boosted to four times the positive voltage Voltage V POG By changing the number of stages, the desired voltage V POG of The voltage generating circuit 903A shown in FIG. By using an OS transistor as M10, the off-state current can be reduced, and the capacitors C11 to C Therefore, the leakage of the charge held in 14 can be suppressed. ORG to voltage V P OG It is possible to boost the voltage to

[0532] The voltage generating circuit 903B shown in FIG. 39B includes transistors M11 to M14, a capacitor The clock signal CLK is supplied to the It is applied to the gates of the transistors M11 to M14 directly or via the inverter INV2. By applying a clock signal CLK, the voltage V ORG Boost to twice the positive voltage The applied voltage V POG The voltage generating circuit 903B shown in FIG. By using OS transistors as the transistors M11 to M14, the off-state current can be reduced. This can prevent the charge stored in the capacitors C15 and C16 from leaking. V ORG to voltage V POG It is possible to boost the voltage to

[0533] The voltage generating circuit 903C shown in FIG. 39(C) includes an inductor I11 and a transistor M1 5, diode D6, and capacitor C17. Transistor M15 is connected to the control signal The conduction state is controlled by the control signal EN. ORG is boosted The applied voltage V POG The voltage generating circuit 903C shown in FIG. Since the voltage is boosted using the inductor I11, it is possible to boost the voltage with high conversion efficiency. can.

[0534] 40A is the same as the voltage generating circuit 903D shown in FIG. The three diodes D1 to D5 are placed in diode-connected transistors M16 to M20. The voltage generating circuit 903D shown in FIG. By using OS transistors for M6 to M20, the off-state current can be reduced. Therefore, the leakage of the charge held in C5 can be suppressed. ORG to voltage V POG It is possible to boost the voltage to

[0535] 40(B) is the same as the voltage generating circuit 90 shown in FIG. The 3D transistors M16 to M20 are replaced by back-gate transistors M21 to M22. The voltage generating circuit 903E shown in FIG. The gate can be supplied with the same voltage as the gate, so the amount of current flowing through the transistor can be Therefore, the voltage V ORG to voltage V POG to boost It is possible.

[0536] The modified example of the voltage generating circuit 903 is also applicable to the voltage generating circuit 905 shown in FIG. 38(B). The circuit configuration in this case is shown in Figures 41(A) to (C), 42(A) and (B). The voltage generating circuit 905A shown in FIG. By this, the voltage V SS to voltage V ORG The voltage V is stepped down to a negative voltage three times that of NEG get The voltage generating circuit 905A shown in FIG. By applying the voltage V SS to voltage V ORG The voltage V is stepped down to a negative voltage twice that of N EG can be obtained.

[0537] The voltage generating circuits 905A to 905B shown in FIGS. 41(A) to 41(C) and 42(A) and 42(B) In E, the voltage generating circuit 903A shown in FIGS. 39(A) to 39(C) and 40(A) and 40(B) is In the above 903E, the voltage applied to each wiring is changed or the arrangement of the elements is changed. The voltage generating circuits shown in FIGS. 41(A) to 41(C) and 42(A) and 42(B) correspond to the configurations shown in FIGS. 905A to 905E, similar to the voltage generating circuits 903A to 903E, efficiently generate the voltage V SS from voltage V NEG It is possible to step down the voltage to

[0538] As described above, in the configuration of the present embodiment, the voltage required for the circuit included in the semiconductor device can be generated internally. Therefore, the semiconductor device can reduce the types of power supply voltages supplied from the outside.

[0539] The present embodiment can be implemented in appropriate combination with at least a part thereof and other embodiments and examples described in this specification.

[0540] (Embodiment 6) In the present embodiment, an example of a CPU including a semiconductor device such as a transistor according to an aspect of the present invention and the above-described memory device will be described.

[0541] <Configuration of CPU>

[0542] The semiconductor device 400 shown in FIG. 43 has a CPU core 401, a power management unit 421, and a peripheral circuit 422. The power management unit 421 has a power controller 402 and a power switch 403. The peripheral circuit 422 has a cache 404 having a cache memory, a bus interface (BUS I / F) 405 , and a debug interface (Debug I / F) 406. The CPU core 4 01 has a data bus 423, a control device 407, a PC (program counter) 408, a pipe pline register 409, a pipeline register 410, an ALU (Arithmetic logic unit) 411, and a register file 412. The data exchange between the CPU core 4 01 and the peripheral circuit 422 such as the cache 404 is performed via the data bus 42 This is done via 3.

[0543] The semiconductor device (cell) includes many components, including a power controller 402 and a control device 407. It can be applied to logic circuits. In particular, it can be constructed using standard cells. As a result, a small-sized semiconductor device 400 can be provided. Furthermore, it is possible to provide a semiconductor device 400 that can reduce power consumption. It is possible to provide a semiconductor device 400 that can improve the speed. Therefore, it is possible to provide a semiconductor device 400 that can reduce the

[0544] The semiconductor device (cell) includes a p-channel Si transistor and the oxide semiconductor device described in the above embodiment. The channel forming region contains an oxide semiconductor (preferably an oxide containing In, Ga, and Zn). By using a transistor and applying the semiconductor device (cell) to the semiconductor device 400, In addition, the semiconductor device 400 can reduce power consumption. 00 can be provided. Also, a semiconductor device 400 that can improve the operating speed can be provided. In particular, by using only p-channel Si transistors, manufacturing costs can be kept low. It is possible.

[0545] The control unit 407 includes a PC 408, a pipeline register 409, and a pipeline register 410, ALU 411, register file 412, cache 404, bus interface The operation of the interface 405, the debug interface 406, and the power controller 402 is controlled by the By controlling the entire system, the commands contained in the input application programs can be It has the function of decoding and executing the above.

[0546] The ALU 411 has the function of performing various arithmetic operations such as arithmetic operations and logical operations.

[0547] The cache 404 has a function of temporarily storing frequently used data. C408 is a register that has the function of storing the address of the next instruction to be executed. Although not shown in FIG. 43, the cache 404 has a memory for controlling the operation of the cache memory. A cache controller is provided.

[0548] The pipeline register 409 is a register that temporarily stores instruction data. is.

[0549] The register file 412 has a plurality of registers including general-purpose registers. Data read from memory or data obtained as a result of ALU411 arithmetic processing, etc. can be stored.

[0550] The pipeline register 410 stores data used in the arithmetic processing of the ALU 411, or A A register that temporarily stores data obtained as a result of LU411's calculations. It is Ta.

[0551] The bus interface 405 connects the semiconductor device 400 and each external device. Debug Interface 4 functions as a data path between the device and the 06 is a signal path for inputting a command for controlling debugging to the semiconductor device 400. It functions as a road.

[0552] The power switch 403 is a power supply that is connected to the power controller 402 of the semiconductor device 400. The above circuits have the function of controlling the supply of power supply voltage to various circuits. Each circuit belongs to a power domain, and various circuits that belong to the same power domain are The switch 403 controls whether or not the power supply voltage is supplied. 402 has the function of controlling the operation of a power switch 403 .

[0553] The semiconductor device 400 having the above configuration is capable of performing power gating. The flow of the power gating operation will be described using an example.

[0554] First, the CPU core 401 determines the timing to stop the supply of the power supply voltage by the power controller. Then, the CPU core 401 sends the data to the register of the power controller 402. 02 to start power gating. The various registers and caches 404 included in the memory device begin to evacuate data. The power supply voltage is supplied to various circuits other than the power controller 402 of the device 400. The power switch 403 then stops the power supply. An interrupt signal is then sent to the power controller 402. , the supply of power supply voltage to the various circuits of the semiconductor device 400 begins. A counter is provided in the power controller 402 to count the number of times the power supply voltage is supplied. The timing at which the interrupt is generated is determined by using the counter, regardless of the input of an interrupt signal. The various registers and caches 404 then begin returning the data. Then, execution of instructions in the control unit 407 resumes.

[0555] Such power gating is performed on the entire processor or on a part of the processor. It can be done in one or more logic circuits. This allows for fine-grained control of power consumption in space and time. Reductions can be made.

[0556] When power gating is performed, the information held by the CPU core 401 and the peripheral circuit 422 is It is preferable to be able to evacuate in a short time. This allows the power to be turned on and off in a short time. This increases the effect of power saving.

[0557] In order to save the information held by the CPU core 401 and the peripheral circuit 422 in a short time, It is preferable that the flip-flop circuit can save data within the circuit (backup possible) (This is called a flip-flop circuit.) Also, the SRAM cell can save data within the cell. It is preferable to use a backup-capable SRAM cell. The chip circuit and SRAM cell are made of oxide semiconductor (preferably oxide containing In, Ga, and Zn). It is preferable to have a transistor including a semiconductor material in a channel formation region. The low off-state current of the resistor allows it to be used in backup flip-flop circuits and SR circuits. AM cells can retain information for a long period without power supply. The fast switching speed allows for backup flip-flop circuits and SR circuits. The AM cell may be capable of saving and restoring data for a short period of time.

[0558] An example of a flip-flop circuit capable of backing up will be described with reference to FIG.

[0559] The semiconductor device 500 shown in FIG. 44 is an example of a flip-flop circuit capable of backing up. The semiconductor device 500 includes a first memory circuit 501, a second memory circuit 502, and a third memory circuit 503. The semiconductor device 500 includes a memory circuit 503 and a read circuit 504. The potential difference between potential V1 and potential V2 is supplied as the power supply voltage. The potential V1 is at the low level, and the other is at the high level. An example of the configuration of the semiconductor device 500 will be described using the case of a bell as an example.

[0560] The first memory circuit 501 stores the following data during a period in which the power supply voltage is supplied to the semiconductor device 500: When a signal D containing data is input, the semiconductor memory device has a function of holding the data. During the period when the power supply voltage is supplied to the semiconductor device 500, the first memory circuit 501 On the other hand, the first memory circuit 501 outputs a signal Q containing the stored data. During the period when the power supply voltage is not supplied to the semiconductor device 500, data can be retained. That is, the first memory circuit 501 can be called a volatile memory circuit.

[0561] The second memory circuit 502 reads the data stored in the first memory circuit 501 and stores the data. The third memory circuit 503 has a function of storing (or saving) data. It has the function of reading and storing (or saving) the data held in 502. The read circuit 504 reads the data stored in the second memory circuit 502 or the third memory circuit 503. The first memory circuit 501 has a function of reading out data and storing (or restoring) the data.

[0562] In particular, the third memory circuit 503 stores the data during a period when the power supply voltage is not supplied to the semiconductor device 500. In this case, the data held in the second memory circuit 502 is read and stored (or retrieved). It has the function of avoiding

[0563] As shown in FIG. 44, the second memory circuit 502 includes a transistor 512 and a capacitor 519. The third memory circuit 503 includes a transistor 513, a transistor 515, a capacitor The read circuit 504 includes a transistor 510 and an element 520. 8, a transistor 509, and a transistor 517.

[0564] The transistor 512 stores a charge according to the data stored in the first memory circuit 501. The transistor 512 has a function of charging and discharging the capacitor 519. The charge corresponding to the data held in the capacitor 519 can be quickly charged and discharged. Specifically, the transistor 512 is preferably made of crystalline silicon (preferably Preferably, the channel forming region contains silicon (preferably polycrystalline silicon, more preferably single crystal silicon). desirable.

[0565] The transistor 513 is turned on or off depending on the charge held in the capacitor 519. The non-conducting state is selected. The transistor 515 is in the non-conducting state when the transistor 513 is in the conducting state. At this time, the capacitor 520 has a function of charging and discharging electric charge according to the potential of the wiring 544. It is desirable that the transistor 515 has a significantly small off-state current. The capacitor 515 is made of an oxide semiconductor (preferably an oxide containing In, Ga, and Zn) as a channel. It is desirable to include it in the forming region.

[0566] To explain the connection relationship of each element in detail, the source and drain of the transistor 512 One end is connected to the first memory circuit 501. The source and drain of the transistor 512 The other input is connected to one electrode of the capacitor 519, the gate of the transistor 513, and the The other electrode of the capacitor 519 is connected to the gate of the transistor 518. One of the source and drain of the transistor 513 is connected to the wiring 544. The other of the source and drain of the transistor 513 is connected to the The source and drain of the transistor 515 are connected to one of the source and drain. The other terminal is connected to one electrode of the capacitor 520 and the gate of the transistor 510. The other electrode of the capacitor 520 is connected to a wiring 543. One of the source and drain of the transistor 510 is connected to the wiring 541. The other of the source and drain is connected to one of the source and drain of a transistor 518. The other of the source and drain of the transistor 518 is connected to the source of the transistor 509. The source and drain of the transistor 509 are connected to one of the The other is connected to one of the source and drain of the transistor 517 and the first memory circuit 501. The other of the source and the drain of the transistor 517 is connected to a wiring 540. In FIG. 44, the gate of the transistor 509 is connected to the Although the gate of transistor 509 is connected to the gate of transistor 17, the gate of transistor 509 is not necessarily connected to the gate of transistor 17. It is not necessary to connect it to the gate of the inverter 517.

[0567] The transistor 515 can be any of the transistors described in the above embodiments. Since the off-state current of the transistor 515 is small, the semiconductor device 500 can be supplied with power for a long period of time. The transistor 515 has good switching characteristics, so that information can be retained without any problem. Therefore, the semiconductor device 500 can perform high-speed backup and recovery.

[0568] This embodiment may be implemented in any manner other than as described, at least in part, herein. The present invention can be implemented in combination with the examples as appropriate. (Embodiment 7) In this embodiment, an imaging device including a transistor according to one embodiment of the present invention will be described. An example will be described.

[0569] <Imaging device> An imaging device according to one aspect of the present invention will be described below.

[0570] FIG. 45A is a plan view showing an example of an imaging device 200 according to one aspect of the present invention. The device 200 includes a pixel section 210, a peripheral circuit 260 for driving the pixel section 210, and a peripheral circuit The pixel section 210 has p rows and q columns. (p and q are integers of 2 or more) are arranged in a matrix. The peripheral circuits 260, 270, 280, and 290 are each The pixel 211 is connected to the plurality of pixels 211 and has a function of supplying signals for driving the plurality of pixels 211. In this specification, the peripheral circuits 260, 270, 280, and and peripheral circuit 290 may be referred to as a "peripheral circuit" or a "drive circuit." For example, peripheral circuit 260 can be considered a part of the peripheral circuit.

[0571] The imaging device 200 preferably includes a light source 291. The light source 291 emits detection light P It can emit 1.

[0572] The peripheral circuits include at least a logic circuit, a switch, a buffer, an amplifier, or a converter. The peripheral circuits may be formed on the substrate on which the pixel portion 210 is formed. Also, semiconductor devices such as IC chips may be used for part or all of the peripheral circuits. , the peripheral circuits are peripheral circuit 260, peripheral circuit 270, peripheral circuit 280, and peripheral circuit 290 One or more of these may be omitted.

[0573] As shown in FIG. 45B, in the pixel section 210 of the imaging device 200, By arranging the pixels 211 at an angle, the pixel The pixel interval (pitch) in the column direction can be shortened. This can further improve the quality of the images captured.

[0574] <Pixel configuration example 1> One pixel 211 included in the imaging device 200 is composed of a plurality of sub-pixels 212, and each sub-pixel By combining a filter (color filter) that transmits light in a specific wavelength range with the pixel 212, This allows the acquisition of information for realizing color image display.

[0575] FIG. 46(A) is a plan view showing an example of a pixel 211 for acquiring a color image. The pixel 211 shown in 46(A) is provided with a color filter that transmits light in the red (R) wavelength range. The sub-pixel 212 (hereinafter also referred to as "sub-pixel 212R") transmits light in the green (G) wavelength range. A sub-pixel 212 (hereinafter also referred to as "sub-pixel 212G") is provided with a color filter that transmits light. and a sub-pixel 212 (hereinafter referred to as a sub-pixel 213) provided with a color filter that transmits light in the blue (B) wavelength range. The subpixel 212 functions as a photosensor. It can be done.

[0576] The subpixels 212 (subpixels 212R, 212G, and 212B) are connected to the wiring 23 1, electrically connected to wiring 247, wiring 248, wiring 249, and wiring 250. The pixel 212R, the sub-pixel 212G, and the sub-pixel 212B are each connected to an independent wiring 25 3. In this specification, for example, the pixel 211 in the nth row is connected to The wiring 248, the wiring 249, and the wiring 250 are respectively referred to as wiring 248[n] and wiring 249[n]. [n] and wiring 250[n]. The wiring 253 is described as wiring 253[m]. The wiring 253 connected to the sub-pixel 212R of the pixel 211 is referred to as wiring 253[m]R, The wiring 253 connected to the sub-pixel 212G is connected to the wiring 253[m]G and the sub-pixel 212B. The wiring 253 is described as wiring 253[m]B. It is electrically connected to the peripheral circuits.

[0577] In addition, the imaging device 200 has color filters that transmit light in the same wavelength range of adjacent pixels 211. The sub-pixels 212 provided with the filters are electrically connected to each other via the switches. In Figure 46(B), the matrix is arranged in n rows (n is an integer between 1 and p) and m columns (m is an integer between 1 and q). The sub-pixel 212 of the pixel 211 arranged in the n+1th row and the mth column adjacent to the pixel 211 is 46B shows an example of connection of sub-pixels 212 of a pixel 211 placed in the nth row. The sub-pixel 212R arranged in the mth column and the sub-pixel 212R arranged in the n+1th row and the mth column are switched. The sub-pixels 212G arranged in the nth row and the mth column are connected via the n+ The sub-pixels 212G arranged in the first row and the mth column are connected via the switches 202. The sub-pixels 212B arranged in the nth row and the mth column and the sub-pixels 212B arranged in the n+1th row and the mth column are switched. 203.

[0578] The color filters used for the subpixels 212 are not limited to red (R), green (G), and blue (B). color filters that transmit cyan (C), yellow (Y) and magenta (M) light respectively. A single pixel 211 may have sub-pixels 212 for detecting light in three different wavelength ranges. By providing the sensor 12, a fu...

Claims

1. a first transistor; a second transistor disposed in an upper layer of the first transistor; a first connection member that electrically connects the layer having the first transistor and the layer having the second transistor; a capacitive element; a second connection member that electrically connects the second transistor and the capacitance element, the first connection member does not have a conductive layer in the same layer as a conductive layer that functions as a gate electrode of the second transistor, an upper portion of the first connection member functions as a wiring having an extending region in a plan view; The semiconductor device, wherein the second connection member has a circular shape in a plan view.

2. a first transistor; a second transistor disposed in an upper layer of the first transistor; a first connection member that electrically connects the layer having the first transistor and the layer having the second transistor; a capacitive element; a second connection member that electrically connects the second transistor and the capacitance element, the first connection member is provided to penetrate an insulating layer containing hafnium oxide; the first connection member does not have a conductive layer in the same layer as a conductive layer that functions as a gate electrode of the second transistor, an upper portion of the first connection member functions as a wiring having an extending region in a plan view; The semiconductor device, wherein the second connection member has a circular shape in a plan view.

3. a first transistor; a second transistor disposed in an upper layer of the first transistor; a first connection member that electrically connects the layer having the first transistor and the layer having the second transistor; a capacitive element; a second connection member that electrically connects the second transistor and the capacitance element, the first connecting member comprises tungsten; the first connection member does not have a conductive layer in the same layer as a conductive layer that functions as a gate electrode of the second transistor, an upper portion of the first connection member functions as a wiring having an extending region in a plan view; The semiconductor device, wherein the second connection member has a circular shape in a plan view.

4. a first transistor; a second transistor disposed in an upper layer of the first transistor; a first connection member that electrically connects the layer having the first transistor and the layer having the second transistor; a capacitive element; a second connection member that electrically connects the second transistor and the capacitance element, the first connection member is provided to penetrate an insulating layer containing hafnium oxide; the first connecting member comprises tungsten; the first connection member does not have a conductive layer in the same layer as a conductive layer that functions as a gate electrode of the second transistor, an upper portion of the first connection member functions as a wiring having an extending region in a plan view; The semiconductor device, wherein the second connection member has a circular shape in a plan view.

5. In any one of claims 1 to 4, A semiconductor device, wherein, in a plan view, an area of the second connection member is smaller than an area of the first connection member.

Images