Method for manufacturing semiconductor device and semiconductor device

Abstract

To provide a method for manufacturing a semiconductor device capable of reducing wiring resistance, and the semiconductor device.SOLUTION: A method for manufacturing a semiconductor device according to the present embodiment comprises forming a recess in a first insulating film. Furthermore, the manufacturing method comprises forming a first conductive film containing a first metal on an inner surface and a bottom surface of the recess. Furthermore, the manufacturing method comprises forming an amorphous layer on the first conductive film. Furthermore, the manufacturing method comprises forming a second conductive film containing the first metal on the amorphous layer so as to embed the recess.SELECTED DRAWING: Figure 1C

Description

[Technical Field]

[0001] The present embodiment relates to a method for manufacturing a semiconductor device and a semiconductor device. [Background technology]

[0002] As the width of wiring decreases with miniaturization, the resistance of the wiring increases, so it is desirable for the resistance of the wiring to be low. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-23380 Summary of the Invention [Problem to be solved by the invention]

[0004] A method for manufacturing a semiconductor device that can reduce wiring resistance and a semiconductor device are provided. [Means for solving the problem]

[0005] A method for manufacturing a semiconductor device according to the present embodiment includes forming a recess in a first insulating film. The method also includes forming a first conductive film containing a first metal on an inner side surface and a bottom surface of the recess. The method also includes forming an amorphous layer on the first conductive film. The method also includes forming a second conductive film containing the first metal on the amorphous layer so as to fill the recess. [Brief explanation of the drawings]

[0006] [Figure 1A] 2A to 2C are cross-sectional views showing an example of a method for manufacturing the semiconductor device according to the first embodiment. [Figure 1B] 1B is a cross-sectional view showing an example of a method for manufacturing a semiconductor device, following FIG. 1A. [Figure 1C]1C is a cross-sectional view showing an example of a method for manufacturing a semiconductor device, following FIG. 1B. [Figure 1D] 1D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device, subsequent to FIG. 1C. [Figure 2] 4 is a graph showing an example of measurement results of the resistivity of the conductive film according to the first embodiment. [Figure 3] FIG. 1 is a cross-sectional view showing an example of a wiring configuration according to a first comparative example. [Figure 4] 4 is a graph showing an example of measurement results of the resistivity of a conductive film, for further explaining the characteristics of an amorphous layer in the first embodiment. [Figure 5] FIG. 10 is a cross-sectional view showing an example of the structure of a semiconductor device according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The present invention is not limited to the embodiment. The drawings are schematic or conceptual, and the proportions of the various parts are not necessarily the same as those in reality. In the specification and drawings, elements similar to those described above with reference to the previous drawings are designated by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

[0008] (First embodiment) 1A to 1D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device according to Embodiment 1. More specifically, FIGS. 1A to 1D are views illustrating the formation of wiring 70 included in the semiconductor device.

[0009] The wiring 70 shown in Fig. 1D is electrically connected to a semiconductor circuit (not shown). For example, the wiring 70 extends in the X direction and a plurality of wirings 70 are arranged side by side in the Y direction. Note that Figs. 1B to 1D schematically show the particle diameters of the conductive films 61 and 63 (conductors 71 and 72).

[0010] First, as shown in FIG. 1A, a recess 54 is formed in an insulating film 50. In the example shown in FIG. 1A, the insulating film 50 has stacked insulating films 51, 52, and 53. The insulating film 51 contains, for example, silicon oxide (SiO2). The insulating film 52 contains, for example, silicon nitride (SiN). The insulating film 53 contains, for example, silicon oxide (SiO2).

[0011] Next, as shown in FIG. 1B, a conductive film 61 containing a first metal as a main component is formed on the inner side and bottom surfaces of the recess 54. The first metal is, for example, tungsten (W). The conductive film 61 is, for example, a tungsten film formed by PVD (Physical Vapor Deposition). The thickness of the conductive film 61 in the Z direction is, for example, 3 nm to 7 nm. As shown in FIG. 1B, the conductive film 61 has a relatively small grain size. The grain size of the conductive film 61 will be described later.

[0012] Next, as shown in FIG. 1C, an amorphous layer 62 is formed on the conductive film 61. The amorphous layer 62 contains a first metal and oxygen, and is, for example, a tungsten oxide (WO x ) The amorphous layer 62 is formed, for example, by oxidizing the surface of the conductive film 61. The amorphous layer 62 is thinner than the conductive film 61. To ensure barrier properties, the conductive film 61 preferably has a thickness in the Z direction of, for example, about 3 nm or more. For example, when the conductive film 61 is formed to a thickness of about 4 nm, the thickness in the Z direction of the amorphous layer 62 is about 1 nm.

[0013] In the following description, it is assumed that the amorphous layer 62 is formed by natural oxidation. In this case, the conductive film 61 and the conductive film 63, which will be described later, are formed in separate apparatuses.

[0014] Next, as shown in FIG. 1D , a conductive film 63 containing tungsten is formed on the amorphous layer 62 so as to fill the recesses 54. The conductive film 63 is formed, for example, by CVD (Chemical Vapor Deposition). Alternatively, the conductive film 63 may be formed by ALD (Atomic Layer Deposition). The thickness of the conductive film 63 in the Z direction is, for example, 20 nm to 100 nm. In the CVD film formation technique, the grain size of the formed film may be affected by the grain size of the underlying layer. Because the conductive film 63 is formed on the amorphous layer 62, it is not affected by the relatively small grain size (crystallinity) of the conductive film 61, and the grain size of the conductive film 63 can be large.

[0015] 1D, the amorphous layer 62 has disappeared. This is thought to be because the amorphous layer 62 is reduced when the conductive film 63 is formed. A part of the amorphous layer 62 may remain between the conductive film 61 and the conductive film 63. The conductive film 61 and the amorphous layer 62 function as an underlayer containing tungsten for the conductive film 63.

[0016] In addition, in FIG. 1D, excess conductive films 61 and 63 are removed down to the upper surface of the insulating film 50 by CMP (Chemical Mechanical Polishing) or the like.

[0017] 1A to 1D, wiring 70 is formed on insulating film 50. Wiring 70 has conductors 71 and 72.

[0018] The conductor 71 includes tungsten.

[0019] The conductor 72 is provided between the side surface and bottom surface of the conductor 71 and the insulating film 50. The conductor 72 contains tungsten.

[0020] The grain size of the conductor 71 is larger than the grain size of the conductor 72. The grain size indicates the size of the crystal grain and can be measured, for example, by electron backscatter diffraction (EBSD). The grain size of the conductor 71 is, for example, 80 nm or more. The grain size of the conductor 72 is, for example, 15 nm or less.

[0021] 2 is a graph showing an example of the measurement results of the resistivity of the conductive film 63 according to the first embodiment. The vertical axis represents the resistivity (μΩ·cm) of the conductive film 63. The horizontal axis represents the number of days (days) remaining after the formation of the conductive film 61 and before the formation of the conductive film 63. Generally, as the number of days (days) remaining increases, the amount of natural oxide film on the conductive film 61 increases.

[0022] 2, the longer the residence time, the smaller the resistivity of the conductive film 63. Furthermore, the resistivity of the conductive film 63 when the residence time is 10 days is approximately 10% lower than the resistivity of the conductive film 63 when the residence time is 0 days. In other words, the more the amorphous layer 62 is formed by natural oxidation, the smaller the resistivity of the conductive film 63.

[0023] As described above, according to the first embodiment, a conductive film 61 containing tungsten is formed on the inner side and bottom surfaces of the recess 54. An amorphous layer 62 is formed on the conductive film 61. A conductive film 63 containing tungsten is formed on the amorphous layer 62 so as to fill the recess 54. This increases the grain size of the conductive film 63, thereby reducing the resistivity of the conductive film 63. As a result, the resistance of the wiring 70 can be reduced.

[0024] The first metal is not limited to tungsten, but may be molybdenum (Mo). In this case, the amorphous layer 62 may be formed of, for example, an oxide of molybdenum (MoO x ) is an oxide layer containing

[0025] Furthermore, the formation of the amorphous layer 62 is not limited to natural oxidation, and may be performed by, for example, oxygen heat treatment, oxygen plasma treatment, etc. In this case, the steps from the formation of the conductive film 61 to the formation of the conductive film 63 are performed in the same apparatus.

[0026] Furthermore, the formation of the amorphous layer 62 is not limited to oxidation. For example, the amorphous layer 62 can be formed on the surface of the conductive film 61 by ion implantation.

[0027] Fig. 3 is a cross-sectional view showing an example of the configuration of a wiring 70a according to a first comparative example. Fig. 3 is an enlarged cross-sectional view showing the vicinity of the boundary between the wiring 70a and the insulating film 50, with the insulating film 50 positioned on the lower side of Fig. 3. The first comparative example differs from the first embodiment in that a barrier metal film 81 and a nucleation layer 82 (initial layer) are formed.

[0028] In the first comparative example, a barrier metal film 81 is formed inside the recess 54 in contact with the insulating film 50, for example, to improve adhesion with the insulating layer 50. Then, a nucleation layer 82 containing tungsten is formed on the barrier metal film 81. Then, a conductive film 63 is formed on the nucleation layer 82 so as to fill the recess 54. The barrier metal film 81 contains, for example, TiN. The resistances of the barrier metal film 81 and the nucleation layer 82 are higher than the resistance of the conductive film 63. Furthermore, due to the influence of the crystallinity of the barrier metal film 81 and the nucleation layer 82, the grain size of the conductive film 63 becomes smaller. The smaller grain size of the conductive film 63 leads to an increase in the resistance of the conductive film 63.

[0029] In contrast, in the first embodiment, the conductive film 61 is formed using PVD, which has higher adhesion than CVD, thereby eliminating the need for the barrier metal film 81, and the conductive film 63 is formed on the amorphous layer 62. By omitting the high-resistance barrier metal film 81 and suppressing the reduction in the grain size of the conductive film 63, the resistance of the wiring 70 can be reduced. The conductive film 61 has the same level of barrier properties as the barrier metal film 81.

[0030] FIG. 4 is a graph showing an example of the measurement results of the resistivity of the conductive film 63 to further explain the characteristics of the amorphous layer 62 in the first embodiment. The vertical axis represents resistivity (μΩ·cm). The horizontal axis represents film thickness (nm). The film thickness is the result of cross-sectional SEM (Scanning Electron Microscope). Note that the resistivity values ​​shown in FIG. 4 do not necessarily have to match the resistivity values ​​shown in FIG. 2. This is because FIGS. 2 and 4 are verification data showing a decrease in resistivity, and the film formation conditions, etc., may differ between FIGS. 2 and 4.

[0031] 4, in the first embodiment in which the amorphous layer 62 is formed, the resistivity of the conductive film 63 is lower than when the amorphous layer 62 is not formed. This is thought to be because the amorphous layer 62 increases the grain size of the conductive film 63, thereby reducing the resistivity of the conductive film 63. That is, in the first embodiment, the resistance of the conductive film 63 can be reduced by suppressing the grain size reduction of the conductive film 63 due to the grain size (crystallinity) of the conductive film 61.

[0032] (Second embodiment) Fig. 5 is a cross-sectional view showing an example of the structure of a semiconductor device according to Embodiment 2. The semiconductor device shown in Fig. 5 is a three-dimensional memory in which an array chip C1 and a circuit chip C2 are bonded together.

[0033] The array chip C1 includes a memory cell array 11 including a plurality of memory cells arranged three-dimensionally, an insulating film 12 on the memory cell array 11, and an interlayer insulating film 13 below the memory cell array 11. The insulating film 12 is, for example, a silicon oxide film or a silicon nitride film. The interlayer insulating film 13 is, for example, a silicon oxide film or a laminated film including a silicon oxide film and another insulating film.

[0034] The circuit chip C2 is provided below the array chip C1. The symbol S indicates the bonding surface between the array chip C1 and the circuit chip C2. The circuit chip C2 includes an interlayer insulating film 14 and a substrate 15 below the interlayer insulating film 14. The interlayer insulating film 14 is, for example, a silicon oxide film or a laminated film including a silicon oxide film and another insulating film. The substrate 15 is an example of a first substrate, such as a semiconductor substrate such as a silicon substrate. FIG. 5 shows the X and Y directions, which are parallel to and perpendicular to the surface, i.e., the top surface, of the substrate 15, and the Z direction, which is perpendicular to the surface of the substrate 15. The Y direction is an example of a first direction, the X direction is an example of a second direction intersecting the first direction, and the Z direction is an example of a third direction intersecting the first and second directions.

[0035] The array chip C1 includes a plurality of word lines WL and source lines SL as a plurality of electrode layers in the memory cell array 11. FIG. 5 shows a staircase structure 21 of the memory cell array 11. Each word line WL is electrically connected to a word wiring layer 23 via a contact plug 22. Each columnar portion CL penetrating the plurality of word lines WL is electrically connected to a bit line BL via a via plug 24 and is also electrically connected to a source line SL. The source line SL includes a first layer SL1, which is a semiconductor layer, and a second layer SL2, which is a metal layer. The symbol V denotes a via plug provided below the bit line BL.

[0036] The circuit chip C2 includes a plurality of transistors 31. Each transistor 31 includes a gate electrode 32 provided on the substrate 15 via a gate insulating film, and a source diffusion layer and a drain diffusion layer (not shown) provided in the substrate 15. The circuit chip C2 also includes a plurality of contact plugs 33 provided on the source diffusion layer or the drain diffusion layer of each of the transistors 31, a wiring layer 34 provided on the contact plugs 33 and including a plurality of wires, and a wiring layer 35 provided on the wiring layer 34 and including a plurality of wires.

[0037] The circuit chip C2 further includes a wiring layer 36 provided on the wiring layer 35 and including a plurality of wires, a plurality of via plugs 37 provided on the wiring layer 36, and a plurality of metal pads 38 provided on these via plugs 37. The metal pads 38 are, for example, a Cu (copper) layer or an Al (aluminum) layer. The circuit chip C2 functions as a control circuit (logic circuit) that controls the operation of the array chip C1. This control circuit is composed of transistors 31 and the like, and is electrically connected to the metal pads 38.

[0038] The array chip C1 includes a plurality of metal pads 41 provided on the metal pads 38 and a plurality of via plugs 42 provided on the metal pads 41. The array chip C1 also includes a wiring layer 43 provided on the via plugs 42 and including a plurality of wires, and a wiring layer 44 provided on the wiring layer 43 and including a plurality of wires including bit lines BL. The metal pads 41 are, for example, a Cu layer or an Al layer. The above-mentioned via plugs V are connected to the wiring layer 43 and the bit lines BL.

[0039] The array chip C1 further includes a plurality of via plugs 45 provided on the wiring layer 44, metal pads 46 provided on the via plugs 45 and on the insulating film 12, and a passivation film 47 provided on the metal pads 46 and on the insulating film 12. The metal pads 46 are, for example, a Cu layer or an Al layer, and function as external connection pads (bonding pads) of the semiconductor device shown in FIG. 5. The passivation film 47 is, for example, an insulating film such as a silicon oxide film, and has openings P that expose the top surfaces of the metal pads 46. The metal pads 46 can be connected to a mounting board or other devices via bonding wires, solder balls, metal bumps, or the like through the openings P.

[0040] Here, the wiring 70 described in the first embodiment corresponds to, for example, the wiring in the wiring layer 43. The insulating film 50 described in the first embodiment corresponds to, for example, a part of the interlayer insulating film 13. Note that the vertical direction in FIG. 5 is reversed with respect to FIG. 1D.

[0041] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents. [Explanation of symbols]

[0042] 50 insulating film, 54 recess, 61 conductive film, 62 amorphous layer, 63 conductive film, 70 wiring, 71 conductor, 72 conductor

Claims

1. forming a recess in the first insulating film; forming a first conductive film containing a first metal on an inner side surface and a bottom surface of the recess; forming an amorphous layer on the first conductive film; forming a second conductive film containing the first metal on the amorphous layer so as to fill the recess; A method for manufacturing a semiconductor device, comprising:

2. forming the amorphous layer includes oxidizing a surface of the first conductive film to form an oxide film, which is the amorphous layer, on the first conductive film; The method for manufacturing a semiconductor device according to claim 1 , wherein the oxide film includes an oxide of the first metal.

3. The method for manufacturing a semiconductor device according to claim 2 , wherein oxidizing the surface of said first conductive film includes natural oxidation.

4. 3. The method for manufacturing a semiconductor device according to claim 2, wherein oxidizing the surface of said first conductive film includes oxygen heat treatment or oxygen plasma treatment.

5. 3. The method for manufacturing a semiconductor device according to claim 2, wherein said forming said second conductive film includes forming said second conductive film while reducing at least a part of said oxide film.

6. The method for manufacturing a semiconductor device according to claim 1 , wherein the amorphous layer is thinner than the first conductive film.

7. forming the first conductive film includes forming the first conductive film by PVD (Physical Vapor Deposition); 2. The method for manufacturing a semiconductor device according to claim 1, wherein forming the second conductive film includes forming the second conductive film by CVD (Chemical Vapor Deposition) or ALD (Atomic Layer Deposition).

8. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the first metal is tungsten (W) or molybdenum (Mo).

9. a first insulating film; a wiring disposed on the first insulating film; Equipped with The wiring is a first conductor including a first metal; a second conductor provided between the side and bottom surfaces of the first conductor and the first insulating film, the second conductor including the first metal; and The semiconductor device, wherein the grain size of the first conductor is 80 nm or more.

10. The semiconductor device according to claim 9 , wherein a grain size of said first conductor is larger than a grain size of said second conductor.

11. 10. The semiconductor device according to claim 9, wherein the first metal is tungsten (W) or molybdenum (Mo).

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