Pseudo access load generation mechanism and computer

Abstract

To generate a pseudo access load for appropriately performing operation verification of application programs of which the number is smaller than that of a plurality of application programs, in a computer scheduled to execute the plurality of application programs by a processor.SOLUTION: A pseudo access load generation mechanism 30 is provided in a computer 10 and includes a pseudo access load generation unit 33 which generates a pseudo access load on a memory module 51 on the basis of access profile information 80 acquired by a profile acquisition unit 35 or information for self-running mode stored in a self-running mode information storage unit 36. Therefore, it is possible to generate a sufficiently high load state of the memory module 51, which corresponds to a load state of the memory module 51 at the time of execution of a plurality of application programs 23 to 26 by a processor 20.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a pseudo-access load generating mechanism that generates a pseudo-access load on a memory module included in a computer, and a computer that includes the pseudo-access load generating mechanism. [Background technology]

[0002] For example, Patent Document 1 discloses a program testing device that verifies the validity of various response processes in response to access to computer hardware resources by a program under test running on a computer when verifying the operation of the program under test. Specifically, the testing device in Patent Document 1 is equipped with a pseudo-driver that generates various pseudo-responses by replacing a normal return value from an interface that services access to computer hardware resources with an arbitrary response value based on pre-given parameters, and performs operation verification for the arbitrary response processes via the pseudo-driver. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-104490 Summary of the Invention [Problem to be solved by the invention]

[0004] As described above, the test device of Patent Document 1 is intended to verify the operation of response processing by computer hardware resources of a program under test.

[0005] Here, it is conceivable that multiple application programs are implemented on a computer. In this case, the multiple application programs may be developed individually and then ultimately integrated and implemented on a computer. When individual application programs are developed during the development process, the operation of the developed application programs can be verified by implementing and running each of the developed application programs on a computer.

[0006] However, even if a standalone application program performs as expected, a test of multiple integrated applications may fail to produce the expected results for at least one of them. One possible cause of this is believed to be that multiple application programs compete for memory module resources and interfere with each other's operations.

[0007] Therefore, when a smaller number of application programs than a plurality of application programs are implemented on a computer and their operation is verified, it is possible to simulate a high load state on the memory module and verify the operation of the smaller number of application programs under that high load environment. This makes it possible to confirm during the development process of each application program whether each individual application program operates as expected when multiple application programs are integrated.

[0008] When data obtained from an external computer or the like is written to the memory module via an external interface (IF) or data read from the memory module is sent to an external computer or the like in order to create a high load state for the memory module, it is difficult to create a sufficiently high load state because the amount of data per unit time of communication via the external IF (i.e., the data bandwidth of the external IF) is less than the amount of data read and written per unit time in the memory module (i.e., the data bandwidth of the memory module).

[0009] Furthermore, when a high load state of a memory module is created using a processor inside a computer, the operation of the processor is affected, which may affect the operation of the application program being verified. As a result, it may be impossible to perform appropriate operation verification in an environment that simulates the state in which multiple application programs are integrated.

[0010] The present disclosure has been made in consideration of the above points, and has a first object to provide a pseudo-access load generation mechanism capable of generating a pseudo-access load in a computer in which a processor is scheduled to execute multiple application programs, in order to appropriately verify the operation of a number of application programs that is smaller than the number of application programs. Further, a second object is to provide a computer equipped with the pseudo-access load generation mechanism. [Means for solving the problem]

[0011] In order to achieve the first object described above, a pseudo access load generating mechanism (30, 130) according to the present disclosure is a pseudo access load generating mechanism for enabling simulation of an access load on a memory module (51) when a processor (20) executes a number of application programs (23, 24, 25, 26) in a computer (10) that is scheduled to execute a number of application programs (23, 24, 25, 26) by the processor for operation verification, the pseudo access load generating mechanism comprising: an acquisition or storage unit (35, 36, 135, 136) that acquires or stores information for applying a pseudo access load to the memory module; a pseudo-access load generating unit (33, 133) that generates a pseudo-access load on the memory module based on the information acquired or stored by the acquiring or storing unit; The pseudo-access load generating mechanism is characterized by being provided inside the computer separately from the processor.

[0012] In order to achieve the second object described above, a computer (10) according to the present disclosure is a computer that is intended to execute a plurality of application programs (23, 24, 25, 26) by a processor (20), a memory module (51) accessed by the processor for writing and reading data when multiple application programs are executed; a pseudo-access load generating mechanism (30, 130) having an acquisition or storage unit (35, 36, 135, 136) that acquires or stores information for applying a pseudo-access load to a memory module, and a pseudo-access load generating unit (33, 133) that generates a pseudo-access load on the memory module based on the information acquired or stored by the acquisition or storage unit; The pseudo-access load generating mechanism is provided inside the computer separately from the processor, When a processor executes a number of application programs less than a plurality of application programs for operation verification, the pseudo access load generated by the pseudo access load generating mechanism makes it possible to simulate the access load on the memory module when the processor executes a plurality of application programs.

[0013] As described above, the pseudo-access load generating mechanism according to the present disclosure is provided within a computer. The pseudo-access load generating mechanism includes a pseudo-access load generating unit that generates a pseudo-access load on a memory module based on information for applying a pseudo-access load acquired or stored by an acquiring or storing unit. Therefore, unlike when the memory module is accessed via an external IF, the pseudo-access load generating mechanism according to the present disclosure can create a sufficiently high load state of the memory module that corresponds to the load state of the memory module when multiple application programs are executed by a processor.

[0014] Furthermore, the pseudo-access load generating mechanism according to the present disclosure is provided inside the computer separately from the processor of the computer. Therefore, the pseudo-access load generating mechanism applies a pseudo-access load to the memory module, which can prevent the pseudo-access load generating mechanism from affecting the operation of the processor. Therefore, in a computer equipped with the pseudo-access load generating mechanism, it is possible to accurately verify the operation of an application program executed by the processor.

[0015] The reference numbers in parentheses above merely indicate an example of a correspondence with specific configurations in the embodiments described below, in order to facilitate understanding of the present disclosure, and are not intended to limit the scope of the present disclosure in any way.

[0016] Furthermore, the technical features of the present disclosure other than those described above will become apparent from the following description of the embodiments and the accompanying drawings. [Brief explanation of the drawings]

[0017] [Figure 1] 1 is a configuration diagram showing the overall configuration of a computer equipped with a pseudo-access load generating mechanism according to a first embodiment, and peripheral devices of the computer. [Figure 2] FIG. 10 is an explanatory diagram illustrating an example of access profile information. [Figure 3] 10 is a flowchart illustrating an example of a process executed in a pseudo-access load generating mechanism for generating a pseudo-access load in a memory module. [Figure 4] FIG. 10 is a configuration diagram showing the overall configuration of a computer equipped with a pseudo-access load generating mechanism according to a second embodiment, and peripheral devices of the computer. DETAILED DESCRIPTION OF THE INVENTION

[0018] Hereinafter, embodiments of a pseudo access load generating mechanism and a computer according to the present disclosure will be described with reference to the drawings. In the following description of the embodiments, the same or similar components may be assigned the same reference numerals across multiple drawings, and their description may be omitted. When only a portion of a component is described in each embodiment, the other components of the previously described embodiment may be applied. Furthermore, in addition to the combinations of components explicitly stated in the description of each embodiment, components of multiple embodiments may be partially combined together even if not explicitly stated, as long as there is no particular problem with the combination.

[0019] (First embodiment) FIG. 1 is a configuration diagram showing the overall configuration of a computer 10 equipped with a pseudo access load generating mechanism 30 according to this embodiment, and peripheral devices of the computer 10. The computer 10 according to this embodiment can be used, for example, to control various control target devices mounted on a vehicle. However, application examples of the computer 10 according to this disclosure are not limited to the control of control target devices mounted on a vehicle, and the computer 10 may be applied to the control of control target devices for other purposes. For example, the computer 10 according to this disclosure may be applied to the control of control target devices for controlling the operation of a robot or construction machine.

[0020] As shown in Fig. 1, a computer 10 includes a processor 20, a pseudo-access load generating mechanism 30, an internal bus 40, a memory controller 50, a storage interface (IF) 60, and an external IF 70. The processor 20, the pseudo-access load generating mechanism 30, the memory controller 50, the storage interface (IF) 60, and the external IF 70 are each connected to the internal bus 40. Note that the configuration of the computer 10 shown in Fig. 1 is an example. For example, part of the configuration shown in Fig. 1 may be omitted. Alternatively, any configuration may be added to the configuration shown in Fig. 1.

[0021] 1, a plurality of application programs, specifically, first to Nth application programs 23 to 26, are planned to be installed on computer 10. In computer 10, processor 20 executes first to Nth application programs 23 to 26 on operating system 22, thereby controlling devices to be controlled, etc.

[0022] The operating system 22 and the first to Nth application programs 23 to 26 are all software programs stored in the storage 61. When the computer 10 starts operating, the operating system 22 and the first to Nth application programs 23 to 26 are each loaded into the memory module 51. This enables the processor 20 to execute the operating system 22 and software programs 21 such as the first to Nth applications. The operating system 22 controls the basic operations of the computer 10, and, for example, manages hardware resources such as the processor 20, memory module 51, and storage 61, and provides an interface that enables the first to Nth application programs 23 to 26 to use the hardware resources.

[0023] The processor 20 is a processing unit that performs various arithmetic processes to execute the first to Nth application programs 23 to 26. The processor 20 includes at least one arithmetic core module such as a CPU (Central Processing Unit). The processor 20 may further include modules such as a GPU (Graphics Processing Unit) for performing image processing and an NPU (Neural Processing Unit) for processing AI (Artificial Intelligence) tasks. When performing various processes, the processor 20 accesses the memory module 51 via the memory controller 50 to temporarily store data in the memory module 51 or read the stored data.

[0024] The memory controller 50 provides interface functions such as data reading and data writing to the memory module 51 in the computer system. For example, when a desired address is specified and a data read command is issued, the memory controller 50 reads the data stored at the specified address and returns the read data. Furthermore, if the memory module 51 includes a DRAM (Dynamic Random Access Memory), the memory controller 50 also refreshes the DRAM.

[0025] The memory module 51 includes a DRAM, an SRAM (Static RAM), etc. As described above, various software programs 21 are loaded into the memory module 51 to enable execution by the processor 20. As a result, the various software programs 21 are stored in the memory module 51. Furthermore, when the processor 20 executes the first to Nth application programs 23 to 26, various data are written to and read from the memory module 51, such as data used in the arithmetic processing of each program, data obtained by the arithmetic processing, and data for image processing and AI tasks. In FIG. 1, the memory module 51 is depicted as being provided outside the computer 10 and connected to the memory controller 50. However, the memory module 51 may be built into the computer 10.

[0026] The storage IF 60 provides interface functions such as reading and writing data to the storage 61. The storage 61 includes a non-volatile storage medium such as a flash memory. The storage 61 stores a software program 21 executed by the processor 20. The storage 61 may also store access profile information 80 for generating a pseudo access load on the memory module 51 by the pseudo access load generating mechanism 30. In FIG. 1, the storage 61 is depicted as being provided outside the computer 10 and connected to the storage IF 60. However, the storage 61 may also be built into the computer 10.

[0027] The external IF 70 is a circuit that provides an interface for the computer 10 to communicate with an external computer, etc. The external IF 70 can be realized using a chip or the like that is equipped with a communication circuit that complies with a communication standard for communication with the external computer, etc. The above-mentioned access profile information 80 can also be imported into the computer 10 via the external IF 70, as shown in FIG.

[0028] Here, when multiple application programs (first to Nth application programs 23 to 26) are planned to be implemented, as in the computer 10 according to this embodiment, the first to Nth application programs 23 to 26 may be developed individually and ultimately integrated and implemented in the computer 10. When each application program is developed in the development process, the developed application program can be implemented and run on the computer 10, thereby verifying the operation of the developed application program.

[0029] However, even if an operation test of a single application program in computer 10 or an environment equivalent to computer 10 shows that the program operates as expected, an operation test of the integrated state of multiple application programs 23 to 26 may not produce the expected operation result for at least one application program. One reason for this is presumably that the multiple application programs 23 to 26 compete for hardware resources related to memory module 51 and interfere with each other's operation.

[0030] Therefore, when fewer application programs than the plurality of application programs 23-26 are installed in the computer 10 and their operation is verified (for example, when only the first and second application programs 23 and 24 of the first to N-th application programs 23-26 are installed in the computer 10 and their operation is verified), it is possible to simulate a high load state on the memory module 51. This makes it possible to simulate a high load state on the memory module 51 as if the plurality of application programs 23-26 were running when the computer 10 or the like is running fewer application programs than the plurality of application programs 23-26. Therefore, during the development process of each application program, it becomes possible to confirm whether each application program operates as expected when the plurality of application programs 23-26 are integrated. Confirmation of whether the application programs operate as expected, i.e., operation verification, can be determined based on, for example, the operation time of the application program to be verified and the access time to the memory module 51.

[0031] When data acquired from an external computer or the like is written to memory module 51 or data read from memory module 51 is transmitted to an external computer or the like via external IF 70 in order to create a high-load state of memory module 51, it is difficult to create a sufficiently high-load state because the data bandwidth of communication via external IF 70 is smaller than the data bandwidth of memory module 51. Furthermore, when a high-load state of memory module 51 is created using processor 20 within computer 10, the operation of processor 20 is affected, which may affect the operation of the application program to be verified. Therefore, there is a possibility that appropriate operation verification cannot be performed in an environment that simulates a state in which multiple application programs 23 to 26 are integrated.

[0032] Therefore, in this embodiment, a pseudo access load generating mechanism 30 capable of issuing a pseudo access load to the memory module 51 is provided inside the computer 10, separate from the processor 20. The pseudo access load generating mechanism 30 includes a CPU core 31, firmware 32, a pseudo access load generating unit 33, a profile acquiring unit 35, a self-running mode information storage unit 36, and an access mode management unit 37. In the configuration shown in FIG. 1, the profile acquiring unit 35 and the access mode management unit 37 are embodied by a software program 34 executed by the CPU core 31.

[0033] The CPU core 31 is a processing unit that performs various arithmetic processes to execute software programs 34, such as the profile acquisition unit 35 and the access mode management unit 37. The CPU core 31 uses a simpler arithmetic core than the processor 20. This prevents increases in costs due to the pseudo access load generation mechanism 30 being installed inside the computer 10. The firmware 32 is software incorporated to perform basic control of hardware, such as the pseudo access load generation unit 33, when the CPU core 31 executes software programs 34, such as the profile acquisition unit 35 and the access mode management unit 37. The firmware 32 and the software programs 34 may be loaded into the memory module 51 and executed. Alternatively, the pseudo access load generation mechanism 30 may include a dedicated memory therein, and the firmware 32 and the software programs 34 may be loaded into the dedicated memory and executed.

[0034] The pseudo access load generating unit 33 is a hardware circuit for inputting and outputting data, connected to the internal bus 40 and configured to be able to access the memory module 51 via the internal bus 40. Specifically, the pseudo access load generating unit 33 writes data to a storage area at a specified address in the memory module 51, and reads data from a storage area at a specified address, based on the access profile information 80 or the information for the free-running mode. By reading and writing data in this way, a high load state of the memory module 51 is realized.

[0035] The profile acquisition unit 35 acquires the access profile information 80 and provides the access profile information 80 to the simulated access load generation unit 33 via the access mode management unit 37. The access profile information 80 is loaded into the memory module 51 via the storage IF 60 or the external IF 70. This loading of the access profile information 80 into the memory module 51 can be executed, for example, by an instruction from the CPU core 31 or the processor 20 of the simulated access load generation mechanism 30. The profile acquisition unit 35 can acquire the access profile information by reading it from the memory module 51. Note that a dedicated memory for storing the access profile information 80 may be provided within the simulated access load generation mechanism 30, and the profile acquisition unit 35 may acquire the access profile information 80 by reading it from the dedicated memory.

[0036] 2, the access profile information 80 is information that sequentially defines multiple access data, including the address of the memory module 51 to be accessed, the type of access (write or read), the data size, module information indicating which module of the processor 20 handles the data, and a wait time. The access profile information 80 is created, for example, based on the actual access load to the memory module of another product that is expected to generate an access load similar to the access load of the memory module 51 caused by the multiple application programs 23 to 26 to be implemented, so as to generate an access load that is reduced by the number of application modules to be verified. Multiple types of access profile information 80 may be created, each with a different load level of the simulated access load. The access profile information 80 to be loaded into the memory module 51 may be switched, for example, in response to an instruction from the processor 20.

[0037] 2, the first access data #1 instructs writing image processing data for the GPU module with a data size of 256 KB to address 0x800_000 of the memory module 51. The second access data #2 instructs waiting for 100 μs. The third access data #3 instructs reading data for the NPU module with a data size of 256 KB from address 0x800_000 of the memory module 51.

[0038] The self-running mode information storage unit 36 ​​has multiple internal registers that store self-running mode information. The multiple internal registers store setting values ​​such as the read / write ratio when accessing the memory module 51 and the data size per unit time (i.e., data bandwidth). The pseudo-access load generator 33 generates a pseudo-access load according to the read / write ratio and data bandwidth specified by the self-running mode information. The address of the memory module 51 to be accessed may be determined randomly based on a random number, for example, or may be determined according to a predetermined rule (such as the initial address value and the countable value of the address for each access).

[0039] The self-propelled mode information storage unit 36 ​​can store the self-propelled mode information by storing the self-propelled mode information in advance. In this case, the self-propelled mode information storage unit 36 ​​may store multiple types of self-propelled mode information that differ in the access load state of the memory module 51. In this case, for example, the load level of the generated pseudo access load can be adjusted by switching the self-propelled mode information to be adopted in response to an instruction from the processor 20. Alternatively, the processor 20 may process the self-propelled mode information so that optimal self-propelled mode information is written to the self-propelled mode information storage unit 36 ​​each time before generating a pseudo access load in the self-propelled mode.

[0040] The access mode management unit 37 manages which mode to execute: a profile playback mode that applies a pseudo access load to the memory module 51 based on the access profile information 80 provided by the profile acquisition unit 35, or a self-running mode that applies a pseudo access load to the memory module 51 based on the self-running mode information provided by the self-running mode information storage unit 36. Furthermore, when the processor 20 instructs the access mode management unit 37 to adjust the load level of the pseudo access load, the access mode management unit 37 also manages switching of the access profile information 80 and switching or rewriting of the self-running mode information.

[0041] Next, an example of a process executed by the pseudo-access load generating mechanism 30 to generate a pseudo-access load in the memory module 51 will be described with reference to the flowchart of Fig. 3. The process shown in the flowchart of Fig. 3 is executed, for example, when the computer 10 is powered on.

[0042] In step S100, the pseudo-access load generating mechanism 30 determines whether or not it has received a pseudo-access generation instruction signal from the processor 20. For example, as shown in Fig. 1, when only the first and second application programs 23, 24 of the first to Nth application programs 23-26 are implemented in the computer 10 and their operation is verified, the processor 20 can instruct the pseudo-access load generating mechanism 30 to generate a pseudo-access load in accordance with the start of the operation verification. The pseudo-access load generation instruction signal can also be given to the pseudo-access load generating mechanism 30 from an external computer connected to the external IF 70.

[0043] In step S110, the pseudo-access load generating mechanism 30 receives a mode selection command signal, for example, from the processor 20. The mode selection command signal instructs the pseudo-access load generating mechanism 30 which mode to execute, the profile playback mode or the free-running mode. The mode selection command signal can also be given to the pseudo-access load generating mechanism 30 from an external computer connected to the external IF 70.

[0044] In step S120, the pseudo-access load generating mechanism 30 determines whether the profile playback mode or the free-running mode has been instructed as the mode to be executed. If the profile playback mode has been instructed, the pseudo-access load generating mechanism 30 proceeds to the processing of step S130. On the other hand, if the free-running mode has been instructed, the pseudo-access load generating mechanism 30 proceeds to the processing of step S170.

[0045] In step S130, the pseudo access load generating mechanism 30 or the processor 20 loads the access profile information 80 into the memory module 51 via the storage IF 60 or the external IF 70. This enables the profile acquiring unit 35 of the pseudo access load generating mechanism 30 to acquire the access profile information 80 by reading it out at high speed from the memory module 51 and provide it to the pseudo access load generating unit 33.

[0046] In step S140, the pseudo access load generating mechanism 30 (pseudo access load generating unit 33) generates a pseudo access load by accessing the memory module 51 in accordance with each piece of access data included in the access profile information 80, based on the access profile information 80. In this way, executing access in accordance with each piece of access data included in the access profile information 80 corresponds to reproducing the access profile defined by the access profile information 80. For this reason, in this embodiment, the mode in which an access load is generated based on the access profile information 80 is called a profile reproduction mode.

[0047] In step S140, when access to the memory module 51 according to all the access data included in the access profile information 80 has ended, or when an end command is issued by, for example, the processor 20, the pseudo-access load generating unit 33 ends the generation of the pseudo-access load in the profile playback mode. Thereafter, the pseudo-access load generating mechanism 30 proceeds to the processing of step S150.

[0048] In step S150, the simulated access load generating mechanism 30 determines whether or not it has received an instruction to change the simulated access load, i.e., an instruction to adjust the load level of the simulated access load, from, for example, the processor 20. As described above, the load level of the simulated access load can be adjusted by switching the access profile information 80 for generating the simulated access load. If it is determined that it has received an instruction to change the simulated access load, the simulated access load generating mechanism 30 proceeds to processing in step S160. On the other hand, if it is determined that it has not received an instruction to change the simulated access load, the simulated access load generating mechanism 30 ends the processing shown in the flowchart of FIG. 3.

[0049] In step S160, the pseudo access load generating mechanism 30 or the processor 20 loads new access profile information 80 into the memory module 51 via the storage IF 60 or the external IF 70. This changes the access profile information 80 for generating a pseudo access load. Then, the pseudo access load generating unit 33 generates a pseudo access load by accessing the memory module 51 in accordance with each access data included in the changed access profile information 80 based on the changed access profile information 80. Note that the change of the access profile information 80 may be repeated multiple times as necessary.

[0050] In step S170, the pseudo access load generating mechanism 30 generates a pseudo access load in accordance with the setting values ​​stored in the multiple internal registers, such as the read / write ratio and data bandwidth when accessing the memory module 51. In this way, the pseudo access load generating mechanism 30 can autonomously generate a pseudo access load in accordance with the setting values ​​stored in the multiple internal registers. In this embodiment, the mode in which an access load is generated based on the setting values ​​stored in the multiple internal registers is called a self-running mode.

[0051] In step S170, when the time for generating the pseudo access load in the self-running mode reaches a certain time or when an end command is issued by, for example, the processor 20, the pseudo access load generating unit 33 ends the generation of the pseudo access load in the self-running mode. After that, the pseudo access load generating mechanism 30 proceeds to the processing of step S180.

[0052] In step S180, the pseudo-access load generating mechanism 30 determines whether it has received an instruction to change the pseudo-access load from, for example, the processor 20. As described above, the pseudo-access load generating mechanism 30 can adjust the load level of the generated pseudo-access load by, for example, switching the self-running mode information to be adopted from multiple stored automatic mode information in response to an instruction from the processor 20. Alternatively, the pseudo-access load generating mechanism 30 can adjust the load level of the pseudo-access load by having the processor 20 write optimal self-running mode information to the self-running mode information storage unit 36 ​​each time before generating a pseudo-access load in the self-running mode. If it is determined that it has received an instruction to change the pseudo-access load, the pseudo-access load generating mechanism 30 proceeds to step S190. On the other hand, if it is determined that it has not received an instruction to change the pseudo-access load, the pseudo-access load generating mechanism 30 ends the process shown in the flowchart of FIG. 3.

[0053] In step S190, the pseudo-access load generating mechanism 30 changes the setting values ​​stored in the internal register by switching the information for the self-running mode or writing new information for the self-running mode. Then, the pseudo-access load generating unit 33 generates a pseudo-access load by accessing the memory module 51 according to the changed setting values. Note that the change of the information for the self-running mode (setting values) may be repeated multiple times as necessary.

[0054] As described above, the pseudo access load generating mechanism 30 according to the first embodiment is provided inside the computer 10. The pseudo access load generating mechanism 30 includes a pseudo access load generating unit 33 that generates a pseudo access load on the memory module 51 based on the access profile information 80 acquired by the profile acquiring unit 35 or the information for the self-running mode stored by the information storage unit for the self-running mode 36. Therefore, unlike when the memory module 51 is accessed via the external IF 70, the pseudo access load generating mechanism 30 according to this embodiment can create a sufficiently high load state of the memory module 51 that corresponds to the load state of the memory module 51 when the processor 20 executes the plurality of application programs 23 to 26, for example.

[0055] Furthermore, the pseudo access load generating mechanism 30 according to this embodiment is provided inside the computer 10 separately from the processor 20 of the computer 10. Therefore, it is possible to suppress the pseudo access load generated by the pseudo access load generating mechanism 30 from affecting the operation of the processor 20 due to the pseudo access load it applies to the memory module 51. Therefore, in the computer 10 equipped with the pseudo access load generating mechanism 30, it is possible to accurately verify the operation of the application program executed by the processor 20.

[0056] (Second embodiment) Next, a pseudo-access load generating mechanism according to a second embodiment of the present disclosure and a computer including the pseudo-access load generating mechanism will be described.

[0057] The pseudo access load generating mechanism 30 according to the first embodiment described above includes a CPU core 31, firmware 32, etc., and the profile acquiring unit 35 and the access mode managing unit 37 are realized by a software program 34. However, it is also possible for the pseudo access load generating mechanism to realize all of its functions by a hardware circuit, without relying on the software program 34.

[0058] 4 is a configuration diagram showing the configuration of the pseudo access load generating mechanism 130 when the functions of the pseudo access load generating mechanism 130 are realized by a hardware circuit, the computer 10 equipped with the pseudo access load generating mechanism 130, and the overall configuration of peripheral devices of the computer 10. The configuration other than the pseudo access load generating mechanism 130 is the same as in the first embodiment, so a description thereof will be omitted.

[0059] In this embodiment, similar to the pseudo access load generating unit 33 in the first embodiment, the pseudo access load generating unit 133 is a hardware circuit for inputting and outputting data that is connected to the internal bus 40 and configured to be able to access the memory module 51 via the internal bus 40. The access mode managing unit 137 can be configured as a switching circuit that selects either the access profile information 80 from the profile acquiring unit 135 or the information for the self-running mode from the information storage unit for self-running mode 136 in response to a mode selection command signal from the processor 20, and provides the selected information to the pseudo access load generating unit 133.

[0060] The profile acquisition unit 135 can be configured, for example, from an input interface circuit that reads out each access data item of the access profile information 80 loaded into the memory module 51, and a buffer circuit that temporarily stores the read access data. The self-running mode information storage unit 136 has multiple internal registers that store self-running mode information, similar to the self-running mode information storage unit 36 ​​of the first embodiment.

[0061] In this way, the pseudo access load generating mechanism 130 can realize all of its functions not by using the software program 34 but by using hardware circuits.

[0062] The above describes preferred embodiments of the present disclosure, but the present disclosure is not limited to the above-described embodiments and can be implemented in various modified forms within the scope of the gist of the present disclosure.

[0063] For example, in the first and second embodiments described above, the pseudo-access load generating mechanisms 30 and 130 are configured to be able to select and execute either a profile replay mode in which a pseudo-access load is applied to the memory module 51 based on the access profile information 80, or a self-running mode in which a pseudo-access load is applied to the memory module 51 based on the information for the self-running mode. However, the pseudo-access load generating mechanisms 30 and 130 may be configured to be able to execute only one of the profile replay mode and the self-running mode. In this case, the access mode management unit 137, the profile acquisition unit 135 for the other mode, or the self-running mode information storage unit 136 can be omitted from the pseudo-access load generating mechanisms 30 and 130.

[0064] Finally, this specification discloses the following technical concepts and combinations thereof. The combinations of the following technical concepts apply not only to the pseudo-access load generating mechanisms 30 and 130 but also to the computer 10 equipped with the pseudo-access load generating mechanisms 30 and 130.

[0065] (Technical thought 1) In a computer (10) in which a processor (20) is scheduled to execute a plurality of application programs (23, 24, 25, 26), when a number of application programs less than the number of application programs is executed by the processor for operation verification, a pseudo-access load generating mechanism (30, 130) is provided for simulating an access load on a memory module (51) in the case where the processor executes the plurality of application programs, the pseudo-access load generating mechanism comprising: an acquisition or storage unit (35, 36, 135, 136) that acquires or stores information for applying a pseudo access load to the memory module; a pseudo-access load generating unit (33, 133) that generates a pseudo-access load on the memory module based on the information acquired or stored by the acquiring or storing unit, The pseudo-access load generating mechanism is provided inside the computer separately from the processor.

[0066] (Technical thought 2) The processor and the memory module are connected via an internal bus (40), The pseudo-access load generating mechanism according to Technical Idea 1, wherein the pseudo-access load generating unit is connected to the internal bus and is configured to be able to access the memory module via the internal bus.

[0067] (Technical Thought 3) The pseudo-access load generating mechanism described in Technical Idea 1 or 2, wherein the information for applying a pseudo-access load to the memory module acquired by the acquisition or storage unit is access profile information (80) that specifies multiple access data in order, including at least the address of the memory module to be accessed, the type of access, and the data size.

[0068] (Technical Thought 4) The access profile information is loaded into the memory module via a storage interface (60) or an external interface (70) provided in the computer; The pseudo access load generating mechanism according to Technical Idea 3, wherein the acquisition or storage unit acquires the access profile information by reading it from the memory module.

[0069] (Technical Thought 5) the information for applying a pseudo access load to the memory module, which is stored by the acquisition or storage unit, is information for a free-running mode, which includes at least a read / write ratio and a data size per unit time when accessing the memory module; A pseudo-access load generating mechanism described in any one of technical ideas 1 to 4, wherein the pseudo-access load generating unit generates a pseudo-access load according to the read / write ratio and data size per unit time indicated by the information for the self-running mode.

[0070] (Technical Thought 6) The pseudo-access load generating mechanism described in Technical Idea 5, wherein the acquisition or storage unit has an internal register for storing the information for the self-running mode.

[0071] (Technical Thought 7) The acquisition or storage unit is capable of storing information for the self-running mode, the information including at least a read / write ratio and a data size per unit time when accessing the memory module, and the acquiring or storing unit is capable of acquiring access profile information (80) that specifies a plurality of access data in order, the access profile information including at least the address of the memory module to be accessed, the type of access, and the data size; The pseudo-access load generating mechanism described in Technical Idea 1 or 2 has a mode management unit (37, 137) in the pseudo-access load generating unit that manages which mode to execute: a self-running mode that applies a pseudo-access load to the memory module based on the information for the self-running mode, or a profile playback mode that applies a pseudo-access load to the memory module based on the access profile information.

[0072] (Technical Thought 8) A pseudo-access load generating mechanism described in any one of technical ideas 1 to 7, wherein when the processor executes fewer application programs than the plurality of application programs for operation verification, the pseudo-access load generating mechanism instructs the pseudo-access load generating mechanism to generate a pseudo-access load on the memory module. [Explanation of symbols]

[0073] 10: Computer, 20: Processor, 21: Software program, 22: Operating system, 23: First application program, 24: Second application program, 25: Third application program, 26: Nth application program, 30: Pseudo access load generating mechanism, 31: CPU core, 32: Firmware, 33: Pseudo access load generating unit, 34: Software program, 35: Profile acquisition unit, 36: Information storage unit for self-running mode, 37: Access mode management unit, 40: Internal bus, 50: Memory controller, 51: Memory module, 60: Storage IF, 61: Storage, 70: External IF, 80: Access profile information, 130: Pseudo access load generating mechanism, 133: Pseudo access load generating unit, 135: Profile acquisition unit, 136: Information storage unit for self-running mode, 137: Access mode management unit

Claims

1. In a computer (10) in which a processor (20) is scheduled to execute a plurality of application programs (23, 24, 25, 26), when a number of application programs less than the number of the application programs is executed by the processor for operation verification, a pseudo-access load generating mechanism (30, 130) is provided for simulating an access load on a memory module (51) in the case where the processor executes the plurality of application programs, the pseudo-access load generating mechanism comprising: an acquisition or storage unit (35, 36, 135, 136) that acquires or stores information for applying a pseudo access load to the memory module; a pseudo-access load generating unit (33, 133) that generates a pseudo-access load on the memory module based on the information acquired or stored by the acquiring or storing unit, The pseudo-access load generating mechanism is provided inside the computer separately from the processor.

2. The processor and the memory module are connected via an internal bus (40); 2. The pseudo-access load generating mechanism according to claim 1, wherein said pseudo-access load generating unit is connected to said internal bus and is configured to be able to access said memory module via said internal bus.

3. The pseudo-access load generating mechanism of claim 1 or 2, wherein the information for applying a pseudo-access load to the memory module acquired by the acquisition or storage unit is access profile information (80) that specifies multiple access data in order, including at least the address of the memory module to be accessed, the type of access, and the data size.

4. The access profile information is loaded into the memory module via a storage interface (60) or an external interface (70) provided in the computer; The pseudo access load generating mechanism according to claim 3 , wherein the acquisition or storage unit acquires the access profile information by reading it from the memory module.

5. the information for applying a pseudo access load to the memory module, which is stored by the acquisition or storage unit, is information for a free-running mode, which includes at least a read / write ratio and a data size per unit time when accessing the memory module; 3. The pseudo-access load generating mechanism according to claim 1, wherein the pseudo-access load generating unit generates a pseudo-access load according to the read / write ratio and the data size per unit time indicated by the information for the free-running mode.

6. The pseudo-access load generating mechanism according to claim 5 , wherein the acquisition or storage unit has an internal register for storing the information for the free-running mode.

7. The acquisition or storage unit is capable of storing information for the free-running mode, the information including at least a read / write ratio and a data size per unit time when accessing the memory module, and The acquisition or storage unit is capable of acquiring access profile information (80) that specifies a plurality of access data in order, the access profile information including at least the address of the memory module to be accessed, the type of access, and the data size; The pseudo-access load generating mechanism of claim 1 or 2, further comprising a mode management unit (37, 137) for managing which mode to execute between a self-running mode that applies a pseudo-access load to the memory module based on the information for the self-running mode and a profile playback mode that applies a pseudo-access load to the memory module based on the access profile information.

8. The pseudo-access load generating mechanism of claim 1 or 2, wherein when the processor executes fewer application programs than the plurality of application programs for operation verification, the processor instructs the pseudo-access load generating mechanism to generate a pseudo-access load on the memory module.

9. A computer (10) configured to execute a plurality of application programs (23, 24, 25, 26) by a processor (20), comprising: a memory module (51) accessed by the processor for writing and reading data when the plurality of application programs are executed; a pseudo-access load generating mechanism (30, 130) having an acquisition or storage unit (35, 36, 135, 136) that acquires or stores information for applying a pseudo-access load to the memory module, and a pseudo-access load generating unit (33, 133) that generates a pseudo-access load on the memory module based on the information acquired or stored by the acquisition or storage unit; the pseudo-access load generating mechanism is provided inside the computer separately from the processor; A computer that, for operation verification, when a number of application programs less than the plurality of application programs are executed by the processor, is capable of simulating the access load on the memory module when the processor executes the plurality of application programs by using a pseudo access load generated by the pseudo access load generating mechanism.

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