Oxide semiconductor film

Abstract

To provide a novel material.SOLUTION: An oxide semiconductor is a composite oxide semiconductor in which a first region and a plurality of second regions are mixed. The first region contains at least indium, an element M (the element M is one or a plurality of Al, Ga, Y, and Sn), and zinc, and each of the second regions contains indium and zinc. Each of the second region contains indium at a higher concentration than the first region, and each of the second regions has higher conductivity than the first region. An end part of one of the plurality of second regions overlaps with an end part of the other one of the plurality of second regions, and the first region three-dimensionally sandwiches the plurality of second regions.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an article, a method, or a manufacturing method. Alternatively, the present invention relates to a process, a machine, relating to the manufacture or composition of matter, especially One embodiment of the present invention relates to an oxide semiconductor or a method for manufacturing the oxide semiconductor. One embodiment of the present invention is a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a power storage device, a storage device, a storage The present invention relates to a memory device, a driving method thereof, or a manufacturing method thereof.

[0002] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to semiconductor devices in general, including semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and memory devices. The device is one aspect of a semiconductor device. Optical devices, power generation devices (including thin-film solar cells, organic thin-film solar cells, etc.), and electronic devices are all semiconductor devices. The semiconductor device may include a conductor device. [Background technology]

[0003] In Non-Patent Document 1, 1-x Ga 1+x O3(ZnO) m (x is -1≦x≦1. It has been stated that there exist homologous phases expressed by the sum of (m, m is a natural number). In Non-Patent Document 1, the solid solution range of the homologous phase For example, the solid solution region of the homologous phase when m=1 is the region where x is -0. It is stated that the range is from 0.33 to 0.08, and the homologous phase for m = 2 The solid solution region is stated to be in the range of x from -0.68 to 0.32.

[0004] Also disclosed is a technique for manufacturing a transistor using an In-Ga-Zn-based oxide semiconductor. (See, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-96055 [Non-patent literature]

[0006] [Non-Patent Document 1] M. Nakamura, N. Kimizuka, and T. Mohri, "The Phase Relations in the In2O3-Ga2ZnO4-ZnO System at 1350℃", J. Solid State Chem., 1991, Vol.93, pp.298-315 Summary of the Invention [Problem to be solved by the invention]

[0007] In Non-Patent Document 1, x Zn y Ga z O w An example is shown, where x, y and z are ZnG The composition near a2O4, that is, x, y, and z are close to (x, y, z) = (0, 1, 2). It is described that when the crystal structure has a spinel structure, it is likely to form or be mixed. Compounds with a spinel-type crystal structure are represented by AB2O4 (A and B are metals). Compounds that can be used for this purpose are known.

[0008] However, a spinel-type crystal structure is formed in an In-Ga-Zn-based oxide semiconductor. When the In-Ga-Zn oxide semiconductor is mixed with the In-Ga-Zn oxide semiconductor, a semiconductor device (e.g., a transistor) having the In-Ga-Zn oxide semiconductor may be formed. This may adversely affect the electrical characteristics or reliability of the transistor.

[0009] In view of the above problems, an object of one embodiment of the present invention is to provide a novel oxide semiconductor. Another object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics. Another object of the present invention is to provide a highly reliable semiconductor device. It is an object of the present invention to provide a semiconductor device having a novel structure. One of the objectives is to provide a facility for

[0010] The description of these problems does not preclude the existence of other problems. It is not necessary for the present invention to solve all of these problems. The above will be made clear from the description, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0011] One aspect of the present invention is a composite oxide semiconductor in which a first region and a plurality of second regions are mixed. In the present invention, the first region is composed of at least indium and an element M (the element M is Al, Ga, Y, or and zinc, and the second region includes indium and The second region contains zinc, and the second region contains indium at a higher concentration than the first region. The region has a higher conductivity than the first region, and is connected to an end of one of the plurality of second regions and a plurality of The other end of the second region overlaps the first region, and the first region includes the plurality of second regions. It is sandwiched in three dimensions.

[0012] The composite oxide semiconductor having the above-described structure has an atomic ratio of indium, element M, and zinc of In:M The composition is Zn=5:1:6 or a value close to that.

[0013] The atomic ratio of indium, element M, and zinc in the first region of the above configuration is In:M: The composition is Zn=4:2:3 or a value close to that.

[0014] The atomic ratio of indium, element M, and zinc in the second region of the above configuration is In:M: The composition is Zn=2:0:3 or a value close to that.

[0015] The composite oxide semiconductor having the above-described structure has an atomic ratio of indium, element M, and zinc of In:M The composition is Zn=4:2:3 or a value close to that.

[0016] The atomic ratio of indium, element M, and zinc in the first region of the above configuration is In:M: The composition is Zn=1:1:1 or a value close to that.

[0017] The atomic ratio of indium, element M, and zinc in the second region of the above configuration is In:M: The composition is Zn=2:0:1 or a value close to that.

[0018] The thickness of the second region in the c-axis direction in the above configuration is 0.1 nm or more and less than 1 nm.

[0019] The first region of the above structure is non-single crystal.

[0020] The first region of the above structure includes a crystalline portion, and the c-axis of the crystalline portion is aligned with the surface where the complex oxide semiconductor film is to be formed. The normal vector of the vector .lamda.

[0021] The second region of the above structure is non-single crystal.

[0022] Another embodiment of the present invention is a transistor including the complex oxide semiconductor having the above structure. It is a transistor.

[0023] Another embodiment of the present invention is a display device including any of the above oxide semiconductors and a display element. Another embodiment of the present invention is a display device including the display device and a touch sensor. Another embodiment of the present invention is a display module comprising any one of the oxide semiconductors described above. a semiconductor device, a display device, or a display module, and an operation key or and a battery. [Effects of the Invention]

[0024] According to one embodiment of the present invention, a novel oxide semiconductor can be provided. According to one embodiment, a semiconductor device can have good electrical characteristics. Alternatively, a semiconductor device having a novel configuration can be provided. Alternatively, a display device with a novel configuration can be provided.

[0025] The description of these effects does not preclude the existence of other effects. The embodiment does not necessarily have to have all of these effects. , the specification, drawings, claims, etc., and It is possible to extract other effects from the claims and other descriptions. [Brief explanation of the drawings]

[0026] [Figure 1] 1 is a conceptual diagram of the structure of an oxide semiconductor. [Figure 2]1 is a conceptual diagram of the structure of an oxide semiconductor. [Figure 3] 1 is a conceptual diagram of the structure of an oxide semiconductor. [Figure 4] 1 is a conceptual diagram of the structure of an oxide semiconductor. [Figure 5] 1A and 1B are diagrams illustrating atomic ratios of oxide semiconductors. [Figure 6] FIG. 1 is a diagram illustrating a sputtering apparatus. [Figure 7] FIG. 1 is a diagram illustrating a sputtering apparatus. [Figure 8] FIG. 1 is a diagram illustrating a sputtering apparatus. [Figure 9] FIG. 1 is a diagram illustrating a sputtering apparatus. [Figure 10] FIG. 1 is a top view showing an example of a film forming apparatus. [Figure 11] FIG. 1 is a cross-sectional view showing an example of a film forming apparatus. [Figure 12] 1A and 1B illustrate a top view and a cross-sectional structure of a transistor according to an embodiment. [Figure 13] 1A and 1B illustrate a top view and a cross-sectional structure of a transistor according to an embodiment. [Figure 14] 1A and 1B illustrate a top view and a cross-sectional structure of a transistor according to an embodiment. [Figure 15] 1A and 1B illustrate a top view and a cross-sectional structure of a transistor according to an embodiment. [Figure 16] 1A and 1B illustrate a top view and a cross-sectional structure of a transistor according to an embodiment. [Figure 17] 1A and 1B illustrate a top view and a cross-sectional structure of a transistor according to an embodiment. [Figure 18] 1A and 1B illustrate a top view and a cross-sectional structure of a transistor according to an embodiment. [Figure 19] 1A to 1C illustrate an example of a method for manufacturing a transistor according to an embodiment. [Figure 20] 1A to 1C illustrate an example of a method for manufacturing a transistor according to an embodiment. [Figure 21] 1A to 1C illustrate an example of a method for manufacturing a transistor according to an embodiment. [Figure 22]1A to 1C illustrate an example of a method for manufacturing a transistor according to an embodiment. [Figure 23] 1A to 1C illustrate a cross-sectional structure of a semiconductor device according to an embodiment. [Figure 24] 1A to 1C illustrate a cross-sectional structure of a semiconductor device according to an embodiment. [Figure 25] 1A to 1C illustrate a cross-sectional structure of a semiconductor device according to an embodiment. [Figure 26] 1A to 1C illustrate a cross-sectional structure of a semiconductor device according to an embodiment. [Figure 27] 1A to 1C illustrate a cross-sectional structure of a semiconductor device according to an embodiment. [Figure 28] 1A to 1C illustrate a cross-sectional structure of a semiconductor device according to an embodiment. [Figure 29] 1A to 1C illustrate a cross-sectional structure of a semiconductor device according to an embodiment. [Figure 30] 1 is a circuit diagram of a semiconductor device according to an embodiment. [Figure 31] 1A to 1C illustrate a cross-sectional structure of a semiconductor device according to an embodiment. [Figure 32] 1A to 1C are a circuit diagram and a cross-sectional view illustrating a semiconductor device according to an embodiment. [Figure 33] 1A to 1C illustrate a cross-sectional structure of a semiconductor device according to an embodiment. [Figure 34] FIG. 1 is a circuit diagram illustrating a memory device according to one embodiment of the present invention. [Figure 35] FIG. 1 is a circuit diagram illustrating a memory device according to one embodiment of the present invention. [Figure 36] 1A and 1B are a circuit diagram and a timing chart illustrating one embodiment of the present invention. [Figure 37] 1A and 1B are graphs and circuit diagrams illustrating one embodiment of the present invention. [Figure 38] 1A and 1B are a circuit diagram and a timing chart illustrating one embodiment of the present invention. [Figure 39] 1A and 1B are a circuit diagram and a timing chart illustrating one embodiment of the present invention. [Figure 40] 1A to 1C are a block diagram, a circuit diagram, and waveform diagrams illustrating one embodiment of the present invention. [Figure 41]1A and 1B are a circuit diagram and a timing chart illustrating one embodiment of the present invention. [Figure 42] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 43] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 44] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 45] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 46] FIG. 1 is a circuit diagram illustrating one embodiment of the present invention. [Figure 47] FIG. 1 is a block diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 48] FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 49] FIG. 1 is a top view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 50] FIG. 1 is a block diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 51] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 52] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 53] FIG. 1 is a top view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 54] 1A to 1C are a flowchart illustrating one embodiment of the present invention and a perspective view of a semiconductor device. [Figure 55] FIG. 10 is a perspective view illustrating an electronic device according to one embodiment of the present invention. [Figure 56] 1 shows EDX mapping of a cross section of a sample according to this example. [Figure 57] 1 is a BF-STEM image of a cross section of a sample according to this example. [Figure 58] FIG. 2 is a diagram showing the XRD measurement results of the sample according to the present embodiment and the XRD analysis positions. DETAILED DESCRIPTION OF THE INVENTION

[0027] Hereinafter, embodiments will be described with reference to the drawings. It is possible to carry out the invention in various forms and in various ways without departing from the spirit and scope of the invention. It will be readily apparent to those skilled in the art that various modifications may be made to the design and details of the present invention. The present invention should not be construed as being limited to the following description of the embodiments.

[0028] In addition, in the drawings, the size, thickness of layers, or areas may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. The figures are merely schematic representations and are not limited to the shapes or values ​​shown in the drawings.

[0029] In addition, the ordinal numbers "first," "second," and "third" used in this specification are intended to be used to indicate a mixture of elements. It should be noted that the numbers are added to avoid confusion and are not intended to limit the number.

[0030] In addition, in this specification, the terms "above" and "below" that indicate the position of components are used. The relationship is used for convenience in explaining the relationship with reference to the drawings. The values ​​change depending on the direction in which each component is depicted. It is not limited to words and phrases, and can be rephrased appropriately depending on the situation.

[0031] In this specification, a transistor includes a gate, a drain, and a source. It is an element with at least three terminals. And, the drain (drain terminal, drain Between the source (source terminal, source region or drain electrode) and the source (source terminal, source region or source electrode) It has a channel region, and current flows between the source and drain through the channel region. In this specification and the like, the channel region is a region where a current mainly flows. The flow area.

[0032] The source and drain functions may differ depending on the type of transistor used, or the circuit operation. This may be reversed if the direction of the current changes during operation. In the text, the terms source and drain may be used interchangeably. .

[0033] In addition, in this specification, "electrically connected" means "something that has some kind of electrical effect." This includes cases where the device is connected via a " is not subject to any particular restrictions as long as it enables the transmission and reception of electrical signals between connected objects. For example, "things that have some kind of electrical action" include electrodes, wiring, and transistors. These include switching elements, resistor elements, inductors, capacitors, and other various functions. This includes elements such as

[0034] In this specification and the like, a silicon oxynitride film is a film containing more oxygen than nitrogen as a composition. A silicon nitride film is a film that contains more nitrogen than oxygen. This refers to a film with a high content.

[0035] In addition, in this specification and the like, when explaining the configuration of the invention using drawings, the same The same reference numerals may be used in common between different drawings.

[0036] In addition, in this specification, "parallel" means that two straight lines are at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Almost parallel" means that two straight lines are arranged at an angle of between -30° and 30°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes the case where the angle is between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0037] In addition, in this specification and the like, the terms "film" and "layer" may be used interchangeably. For example, the term "conductive layer" can be replaced with "conductive film" Alternatively, for example, the term "insulating film" may be changed to " may be changed to the term "insulating layer."

[0038] Even when written as "semiconductor," if the conductivity is sufficiently low, it may be written as "insulator." In addition, the boundary between "semiconductor" and "insulator" is vague, and Therefore, the term "semiconductor" as used herein may be used interchangeably with "insulator." Similarly, the term "insulator" used herein can be interpreted as "semiconductor." " can sometimes be rephrased as ".

[0039] (Embodiment 1) In this embodiment, an oxide semiconductor which is one embodiment of the present invention will be described.

[0040] The oxide semiconductor preferably contains at least indium. It is preferable that lead is contained. In addition to these, aluminum, gallium, yttrium It is preferable that the alloy contains boron, silicon, titanium, iron, or the like. , nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium , hafnium, tantalum, tungsten, magnesium, or One or more types may be included.

[0041] Here, a case where the oxide semiconductor contains indium, an element M, and zinc is considered. The element M is aluminum, gallium, yttrium, or tin. Other elements Applicable elements for M include boron, silicon, titanium, iron, nickel, and germanium. , zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, Tungsten, magnesium, etc. However, the element M can be a combination of multiple of the above elements. In some cases, indium, the element M, and The terms for the atomic ratio of zinc are [In], [M], and [Zn].

[0042] <Oxide semiconductor structure> 1 to 4 show conceptual diagrams of the oxide semiconductor of the present invention.

[0043] 1 to 4 show conceptual diagrams of the oxide semiconductor of the present invention. 3A and 4A are top views of the oxide semiconductor (here, referred to as the ab-plane direction). 1(B), 2(B), 3(B), and 4(B) are conceptual diagrams of the substrate Sub 1 is a conceptual diagram of a cross section (here, referred to as the c-axis direction) of an oxide semiconductor formed on a substrate.

[0044] 1 to 4 illustrate the case where an oxide semiconductor is formed over a substrate. However, the present invention is not limited to this, and an insulating film such as an underlayer or an interlayer film may be provided between the substrate and the oxide semiconductor. Alternatively, other semiconductor films such as oxide semiconductor films may be formed.

[0045] As shown in FIGS. 1A and 1B, the oxide semiconductor of the present invention has a region A1 and a region B2. Region A1 is a complex oxide semiconductor having a mixed structure with region B1. :[M]:[Zn]=x:y:z (x>0, y≧0, z≧0) is the region with a high In content. On the other hand, in the region B1, [In]:[M]:[Zn]=a:b:c (a>0, b>0, c > 0) is a region where there are few In.

[0046] In this specification, the atomic ratio of In to element M in region A1 is The atomic ratio of In to M in region A1 is larger than that in region B1. Therefore, in this specification, the region A1 is referred to as an in-rich region. The area B1 is also called an in-poor area.

[0047] For example, the concentration of In in the region A1 is 1.1 times or more, preferably 2 times or more, than that in the region B1. The region A1 may be an oxide containing at least In. Furthermore, the elements M and Zn do not necessarily have to be contained.

[0048] <Atomic ratio> Here, the atomic ratio of elements contained in the complex oxide semiconductor of one embodiment of the present invention will be described.

[0049] In the oxide semiconductor of the present invention, for example, the region A1 contains In, an element M, and Zn. In this case, the atomic ratio of each element can be shown using the phase diagram shown in Figure 5. The atomic ratio of Zn and Zn is expressed as x:y:z, where x, y, and z are the atomic ratios. The numerical ratio can be expressed in the diagram as coordinates (x:y:z). No numerical ratios are given.

[0050] In FIG. 5, the dashed line indicates the principle of [In]:[M]:[Zn]=(1+α):(1-α):1. The line where the number of electrons ratio (-1≦α≦1) is [In]:[M]:[Zn]=(1+α):(1 -α):2 atomic ratio line, [In]:[M]:[Zn]=(1+α):(1- The line where the atomic ratio is α):3, [In]:[M]:[Zn]=(1+α):(1-α ):4, and the line where the atomic ratio is [In]:[M]:[Zn]=(1+α):(1 -α):5 represents the line where the atomic ratio is

[0051] The dashed line indicates the atomic ratio of [In]:[M]:[Zn]=1:1:β (β≧0). The line where the atomic ratio of [In]:[M]:[Zn]=1:2:β is :[M]:[Zn]=1:3:β atomic ratio line, [In]:[M]:[Zn] = 1:4:β atomic ratio line, [In]:[M]:[Zn]=1:7:β atoms A line where the atomic ratio is [In]:[M]:[Zn]=2:1:β, and represents the line where the atomic ratio is [In]:[M]:[Zn]=5:1:β.

[0052] In addition, the atomic ratio of [In]:[M]:[Zn]=0:2:1 or its vicinity, as shown in FIG. Oxide semiconductors with high conductivity tend to have a spinel-type crystal structure.

[0053] The region A2 shown in FIG. 5 has a preferable atomic ratio of indium, element M, and zinc contained in the region A1. The region A2 is an example of a preferable range of [In]:[M]:[Zn]. This also includes the line where the atomic ratio is (1+γ):0:(1-γ) (-1≦γ≦1). do.

[0054] The region B2 shown in FIG. 5 has a preferable atomic ratio of indium, element M, and zinc contained in the region B1. The region B2 is an example of a preferable range of [In]:[M]:[Zn]. = 4:2:3 to 4.1 and its neighboring values. Nearby values ​​include, for example, the atomic ratio [ In]:[M]:[Zn]=5:3:4. ]:[Zn]=5:1:6 and its neighboring values.

[0055] The region A2 has a high In concentration, so it has a higher conductivity than the region B2, and carrier movement Therefore, the oxide semiconductor having the region A1 has a function of increasing the field effect mobility. The on-state current and carrier mobility of a transistor using such a material can be increased.

[0056] On the other hand, the region B2 has a lower In concentration and is therefore less conductive than the region A2, resulting in a lower leakage current. Therefore, a transistor using an oxide semiconductor having the region B1 The off-state current of the transistor can be reduced.

[0057] In the oxide semiconductor of the present invention, the region A1 and the region B1 form a complex. That is, carrier movement is likely to occur in region A1, and carrier movement is unlikely to occur in region B1. Therefore, the oxide semiconductor of the present invention has high carrier mobility and switching properties. It can be used as a material with high characteristics and good semiconductor properties.

[0058] As an example, as shown in FIG. 1A, the region A1 is basically As shown in FIG. 1B, the region A1 is formed in a shape close to a circle. Therefore, the region A1 is formed in an island shape. and can exist in a state where it is sandwiched three-dimensionally between areas B1. This structure is contained in region B1.

[0059] As shown in FIG. 1(A) and FIG. 1(B), the region A1 has irregular Therefore, a plurality of regions A1 may be connected to each other. The plurality of regions A1 are in the shape of overlapping circles in the ab-plane direction or in the shape of overlapping circles in the c-axis direction. However, if all the regions A1 are aligned in the ab plane direction, the ellipses may be connected at their ends. When the transistor is connected in the opposite direction, the switching characteristics of the transistor, for example, the off-current of the transistor, As shown in Figures 1(A) and 1(B), the area A1 is scattered within the area B1. It would be preferable to have done so.

[0060] The proportion of the scattered regions A1 can be adjusted depending on the manufacturing conditions or composition of the composite oxide semiconductor. For example, as shown in FIG. 2, the composite oxide semiconductor with a low ratio of the region A1 can be conductor, or as shown in FIG. 3, forming a complex oxide semiconductor with a high ratio of region A1. In addition, in the complex oxide semiconductor of the present invention, the ratio of the region A1 to the region B1 is small. In complex oxide semiconductors where the proportion of region A1 is very large, the observation range is As a result, there are cases where region B1 is formed within region A1.

[0061] In addition, for example, the size of the island formed by the region A1 varies depending on the conditions for producing the complex oxide semiconductor. The conditions or composition can be adjusted as appropriate. As shown in Figure 4, the island-like regions of the same size are formed. There may be scattered areas A1 of the same size.

[0062] In addition, there are cases where a clear boundary between the area A1 and the area B1 cannot be observed. The sizes of area A1 and area B1 can be evaluated by EDX mapping. 1 indicates that the thickness (also called diameter) of area A1 in the EDX mapping of the cross-sectional photograph is 0.1 It may be observed to be between 0.3 nm and 3 nm, or between 0.3 nm and 3 nm. Preferably, the thickness of the region A1 is 0.1 nm or more and 1 nm or less.

[0063] As described above, the oxide semiconductor of one embodiment of the present invention has a complex structure in which the region A1 and the region B1 are mixed. The semiconductor is a composite oxide semiconductor, and the functions of the region A1 and the region B1 are different from each other, The region A1 and the region B1 function complementary to each other. For example, in the In-G In the case of α-Zn oxide (hereinafter referred to as IGZO), the oxide semiconductor of one embodiment of the present invention is It can be called complementary IGZO (abbreviated as C / IGZO).

[0064] On the other hand, for example, in the case where the region A1 and the region B1 are laminated in layers, Since there is no interaction or little interaction between area A1 and area B1, The functions of area B1 and area A2 may function independently. Even if the carrier mobility can be increased, the off-state current of the transistor may become high. Therefore, by using the above-mentioned composite oxide semiconductor or C / IGZO, It has both high carrier mobility and good switching characteristics. This is an excellent effect that can be obtained with the complex oxide semiconductor of the present invention.

[0065] When an oxide semiconductor is deposited using a sputtering device, the atomic ratio of the target is In particular, depending on the substrate temperature during film formation, the atomic ratio of [Zn] As a result, the atomic ratio of the film may become smaller than that of the target.

[0066] Furthermore, the characteristics of the complex oxide semiconductor according to one embodiment of the present invention are uniquely determined by the atomic ratio. Therefore, the illustrated regions are the region A1 and the region B1 of the complex oxide semiconductor. The boundary is not strict.

[0067] Here, the oxide semiconductor includes a single-crystal oxide semiconductor, a non-single-crystal oxide semiconductor, and As non-single-crystal oxide semiconductors, CAAC-OS (c-axis alignable oxide semiconductor) gned crystalline oxide semiconductor), polycrystalline nc-OS (nanocrystalline oxide semiconductor) conductor), pseudo-amorphous oxide semiconductor (a-like OS) amorphous oxide semiconductors) and amorphous oxide semiconductors etc.

[0068] CAAC-OS has a c-axis orientation and multiple nanocrystals are connected in the ab-plane direction. The crystal structure is distorted.

[0069] nc-OS is a material that can be used in microscopic areas (e.g., areas between 1 nm and 10 nm, especially areas between 1 nm and 3 nm). The nc-OS has periodic atomic arrangement in the nanometer range (nm or less). There is no regularity in the crystal orientation between the crystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, nc-OS may be distinguished from a-like OS or amorphous oxide semiconductor. It may be difficult to distinguish between the two.

[0070] The a-like OS is an oxide semiconductor with a structure between the nc-OS and amorphous oxide semiconductor. Conductive. A-like OS has voids or low density regions. The OS has an unstable structure compared to the nc-OS and CAAC-OS.

[0071] Oxide semiconductors have a variety of structures, each of which has a variety of properties. Conductors are amorphous oxide semiconductors, a-like OS, nc-OS, and CAAC-OS. It may also be a composite oxide semiconductor having two or more of these.

[0072] For example, the region A1 is preferably non-single crystal, while the region B1 is preferably CAAC-O. The semiconductor device may have at least one of a silicon-silicon-based semiconductor (S), a polycrystalline oxide semiconductor (PES), and an nc-OS region. It is also preferable that the region A1 and the region B1 have different crystal structures.

[0073] <Transistors containing oxide semiconductors> Next, a case where the oxide semiconductor is used in a transistor will be described.

[0074] By using the above-described complex oxide semiconductor in a transistor, the carrier mobility is high and Furthermore, it is possible to realize a transistor with high switching characteristics. A transistor can be realized.

[0075] In addition, it is preferable to use an oxide semiconductor with low carrier density for the transistor. For example, oxide semiconductors have a carrier density of 8×10 11 / cm 3 Less than 1 x 10 11 / cm 3 less than 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 That's all there is to it.

[0076] Note that a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor has a small carrier generation source. In addition, the carrier density can be reduced because the material is intrinsically or substantially pure. Since the density of defect states in an intrinsic oxide semiconductor is low, the density of trap states may also be low. There is a match.

[0077] In addition, it takes a long time for the charges trapped in the trap levels of the oxide semiconductor to disappear. Therefore, the trap level density is high. A transistor in which a channel region is formed in an oxide semiconductor may have unstable electrical characteristics. There is.

[0078] Therefore, in order to stabilize the electrical characteristics of a transistor, the impurity concentration in the oxide semiconductor is In order to reduce the impurity concentration in the oxide semiconductor, It is also preferable to reduce the impurity concentration in the film in contact with the film. Potassium metal, alkaline earth metal, iron, nickel, silicon, etc.

[0079] Here, the influence of each impurity in an oxide semiconductor will be described.

[0080] When oxide semiconductors contain silicon or carbon, which are elements of Group 14, oxide Defect levels are formed in semiconductors. This causes defects in silicon and carbon in oxide semiconductors. The concentration of silicon and carbon near the interface with the oxide semiconductor (Secondary Ion Mass Spectroscopy ( SIMS (Secondary Ion Mass Spectrometry) The resulting concentration is 2 x 10 18 atoms / cm 3 Less than or equal to 2 x 10 17 at oms / cm 3 The following applies.

[0081] In addition, when an oxide semiconductor contains an alkali metal or alkaline earth metal, defect levels are formed. Therefore, alkali metals or alkaline earth metals A transistor using an oxide semiconductor containing such a compound tends to be normally on. Therefore, the concentration of alkali metal or alkaline earth metal in the oxide semiconductor can be reduced. Specifically, it is preferable to use an alkali metal or alkali metal in an oxide semiconductor obtained by SIMS. The concentration of alkaline earth metals is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 1 6 atoms / cm 3 The following applies.

[0082] In addition, when nitrogen is contained in an oxide semiconductor, electrons that act as carriers are generated, and the carriers The density increases and it becomes easier to make the oxide semiconductor n-type. The transistor using the oxide semiconductor is likely to be normally on. Therefore, it is preferable that the nitrogen content is reduced as much as possible. For example, the nitrogen concentration in the oxide semiconductor is The degree is 5×10 in SIMS. 19 atoms / cm 3 Less than 5 x 10 1 8 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Below, further Preferably 5 x 10 17 atoms / cm 3 The following applies.

[0083] In addition, hydrogen contained in oxide semiconductors reacts with oxygen that bonds with metal atoms to form water. , oxygen deficiency (V o ) may be formed. o ) hydrogen enters the In some cases, electrons, which are carriers, are generated. In addition, some of the hydrogen atoms bond with the metal atoms. It can combine with hydrogen to produce electrons, which are carriers. Transistors using oxide semiconductors tend to be normally-on. It is preferable that the amount of hydrogen in the semiconductor is reduced as much as possible. Specifically, the amount of hydrogen in the oxide semiconductor is reduced as much as possible. The hydrogen concentration obtained by SIMS is 1×10 20 atoms / cm 3 less than, Preferably 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atom s / cm 3 less than 1×10 18 atoms / cm 3 Less than.

[0084] In addition, oxygen vacancies (V o ) is achieved by introducing oxygen into an oxide semiconductor. In other words, oxygen vacancies (V o ) is replenished with oxygen This results in oxygen deficiency (V o ) disappears. Therefore, diffusing oxygen into the oxide semiconductor This reduces the oxygen deficiency (V o ) can be reduced and reliability can be improved.

[0085] As a method for introducing oxygen into an oxide semiconductor, for example, a method for introducing oxygen into an oxide semiconductor by chemical It is possible to provide an oxide containing more oxygen than the stoichiometric composition. In oxides, there is a region where oxygen exists in excess of the stoichiometric composition (hereinafter referred to as the excess oxygen region). In particular, when an oxide semiconductor is used in a transistor, In this case, an oxide having an excess oxygen region is provided in an underlayer film or an interlayer film near a transistor. This reduces oxygen vacancies in the transistor, leading to improved reliability.

[0086] To use an oxide semiconductor in which impurities are sufficiently reduced for a channel formation region of a transistor This allows stable electrical properties to be imparted.

[0087] <Method for forming oxide semiconductor film> An example of a method for forming an oxide semiconductor film by sputtering will be described below.

[0088] The temperature during the formation of the oxide semiconductor film is preferably room temperature or higher and lower than 140°C. Note that room temperature includes not only cases where temperature control is not performed, but also cases where temperature control is performed. Let's say.

[0089] The sputtering gas may be a rare gas (typically argon), oxygen, or a mixture of a rare gas and oxygen. Mixed gases are used appropriately. In the case of mixed gases, the ratio of oxygen to rare gases should be 5% or more and 30% or less. % or less, preferably 7% or more and 20% or less.

[0090] When oxygen is contained in the sputtering gas, the oxide semiconductor film is formed and the underlying film is also formed. In addition, oxygen can be added to form an oxygen-excess region. Purification is also necessary. For example, oxygen gas and argon gas used as sputtering gases The dew point is preferably -40°C or less, more preferably -80°C or less, more preferably -100°C or less, and even more preferably -40°C or less. Preferably, the gas is highly purified to -120°C or less, so that moisture is not absorbed in the oxide semiconductor. This can prevent the incorporation of such information as much as possible.

[0091] In addition, when forming an oxide semiconductor film by sputtering, the temperature of the sputtering device is The chamber is cryo-treated to remove as much water as possible, which is an impurity for oxide semiconductors. A high vacuum (5 x 10) was created using a suction type vacuum exhaust pump such as -7 Pa to 1 x 10 - 4 It is preferable to evacuate the chamber to a pressure of about 100 Pa. Alternatively, a turbomolecular pump and a cold trap may be used. By combining this pump, gases, especially those containing carbon or hydrogen, can flow back into the chamber from the exhaust system. It is preferable to avoid this.

[0092] In addition, an In-Ga-Zn metal oxide target can be used as the target. For example, [In]:[Ga]:[Zn]=4:2:4.1 [atomic ratio], or [In ]:[Ga]:[Zn]=5:1:6 [atomic ratio] or a value close to that. It is preferable to use a metal oxide target.

[0093] In addition, the target may be rotated or moved in the sputtering device. For example, by swinging the magnet unit up and down and / or left and right during film formation, The composite oxide semiconductor of the present invention can be formed. For example, the target is heated at 0.1 Hz. and 1 kHz or less beat (also called rhythm, beat, pulse, frequency, period or cycle) You can also rotate or move the magnet unit by The oscillation frequency should be between 0.1 Hz and 1 kHz. Details will be described in a later embodiment.

[0094] For example, the sputtering gas may be a rare gas with an oxygen gas ratio of about 10% and a Using a mixed gas, the substrate temperature was 130°C, and the ratio of [In]:[Ga]:[Zn] was 4:2:4. Film formation is performed by oscillating an In-Ga-Zn metal oxide target with an atomic ratio of 0.1. In this way, the oxide semiconductor of the present invention can be formed.

[0095] First, rare gas or oxygen gas is ionized in the deposition chamber and split into positive ions and electrons to form plasma. The positive ions in the plasma are converted into the target by the potential applied to the target holder. The positive ions collide with the In-Ga-Zn metal oxide target. By this, sputtered particles are generated and deposited on the substrate.

[0096] First, positive ions collide with an In-Ga-Zn metal oxide target, resulting in a relative atomic mass Ga and Zn, which are lighter in amount than In, are preferentially ejected from the target. The released In, Ga, and Zn combine with oxygen and deposit on the substrate, forming region B1 At this time, In is segregated on the surface of the target.

[0097] Next, the In segregated on the surface of the target forms a multi-particle structure and is then The segregated In, which has a structure like multiple particles, combines with oxygen, The particles collide with the previously deposited area B1 and spread into a shape close to a circle, forming an island-shaped area. Since the segregated In is expelled, the target surface is left with In. , Ga, and Zn exist in a state close to the original atomic ratio.

[0098] Here, furthermore, the positive ions collide with the target, and the relative atomic mass of In is Light Ga and Zn are preferentially ejected from the target. On the surface of the wafer, In is segregated. By depositing on the region A1, the region B1 is formed so as to sandwich the region A1. can be.

[0099] In addition, In segregates in one region of the target surface, and in another region of the target surface, The segregated In is expelled. In other words, the mechanism by which In segregates and the mechanism by which the segregated In is expelled are explained. The mechanism of the release of the particles occurs simultaneously, and area A1 is sandwiched between area B1 and is unevenly distributed. The resulting structure is:

[0100] By going through the above-described film formation model, the regions A1 and A2 shown in FIGS. It is believed that a complex oxide semiconductor is formed in which the region B1 is mixed with the region B2.

[0101] The oxide semiconductor of the present invention has an In-rich region A1, which is configured with an atomic ratio shown in region A2. The In-rich region B1, which is composed of the atomic ratio shown in region B2, and the In-rich region B2 are mixed and complex. In other words, carrier movement is likely to occur in region A1, and Therefore, the oxide semiconductor of the present invention has a low carrier mobility. It can be used as a material with high conductivity, high switching characteristics, and good semiconductor properties. can.

[0102] As described above, the structure shown in this embodiment may be appropriately combined with structures shown in other embodiments or examples. They can be used in combination.

[0103] (Embodiment 2) In this embodiment, a sputtering method capable of depositing an oxide film according to one embodiment of the present invention is used. The coating apparatus and film forming apparatus will be described with reference to FIGS. In the case of a deposition device, for ease of understanding or to explain the operation during deposition, , the substrate and target are shown in place. Since the sputtering apparatus according to one aspect of the present invention is an object that is installed by the user, It may have no call or target.

[0104] <Sputtering equipment> The sputtering device may be, for example, a parallel plate sputtering device or a facing target sputtering device. A parallel plate sputtering device can be used. The film formation method used is called PESP (parallel electrode SP). Also, the film formation method using a facing target sputtering device is called VDSP (v It can also be called apor deposition SP).

[0105] [Parallel Plate Sputtering System (PESP)] First, the parallel plate sputtering apparatus will be explained. 6A is a cross-sectional view of a film-forming chamber 601, which is a sputtering apparatus. The target holder 620, the backing plate 610, the target 600, and the The target 600 includes a magnet unit 630 and a substrate holder 670. , is placed on the backing plate 610. The backing plate 610 is The magnet unit 630 is placed on the backing plate 620. The substrate holder 670 is placed under the target 600 via the plate 610. In this specification, the term "multiple magnets (magnetic The magnet unit is made up of a cathode and a , cathode magnet, magnetic member, magnetic part, etc. The unit 630 includes a magnet 630N, a magnet 630S, and a magnet holder 6 32. In the magnet unit 630, the magnet 630N and The magnet 630S is placed on a magnet holder 632. The magnet 630N is disposed at a distance from the magnet 630S. When loading 60 , the substrate 660 is placed on the substrate holder 670 .

[0106] The target holder 620 and the backing plate 610 are fastened together using screws (bolts, etc.). The target holder 620 is fixed and equipotential. It has the function of supporting the target 600 via 610.

[0107] A target 600 is fixed to the backing plate 610. For example, The backing plate 610 and the target are bonded together by a bonding material containing a low melting point metal such as aluminum. The set 600 can be fixed.

[0108] FIG. 6A shows the magnetic field lines 680a and magnetic field lines 680b formed by the magnet unit 630. Line 680b is shown.

[0109] The magnetic field line 680a is one of the magnetic field lines that form the horizontal magnetic field near the top surface of the target 600. The vicinity of the upper surface of the target 600 is, for example, a portion of the target 600 that is vertically spaced from the target 600 by 0. The range is from 0 mm to 5 mm, particularly from 0 mm to 10 mm.

[0110] The magnetic field lines 680b are horizontal magnetic fields at a vertical distance d from the top surface of the magnet unit 630. The vertical distance d is, for example, 0 mm or more and 20 mm or less, or Between 5mm and 15mm.

[0111] At this time, by using the powerful magnet 630N and the powerful magnet 630S, A strong magnetic field can be generated even near the top surface of the substrate 660. The magnetic flux density of the horizontal magnetic field on the upper surface of 660 is 10 G or more and 100 G or less, preferably 15 G The strength can be set to 60G or less, and more preferably 20G or more and 40G or less.

[0112] The magnetic flux density of the horizontal magnetic field can be measured by measuring the value when the magnetic flux density of the vertical magnetic field is 0G. good.

[0113] By setting the magnetic flux density of the magnetic field in the film formation chamber 601 within the above range, a film having high density and crystalline Furthermore, the oxide obtained contains multiple types of crystal phases. The oxide contains little crystal phase and is almost entirely a single crystal phase.

[0114] 6B shows a top view of the magnet unit 630. The magnet unit 630 , circular or nearly circular magnet 630N, and circular or nearly circular magnet 630S. , is fixed to the magnet holder 632. Then, the magnet unit 630 is The normal vector at the center or approximately the center of the upper surface of the magnet unit 630 is set as the rotation axis. For example, the magnet unit 630 can be rotated at a frequency of 0.1 Hz to 1 kHz. Beats below Hz (also known as rhythm, beat, pulse, frequency, period, or cycle) ) to rotate it.

[0115] Therefore, the strong magnetic field region on the target 600 is generated by the rotation of the magnet unit 630. The region with a strong magnetic field becomes a high-density plasma region, so in its vicinity, Sputtering of the target 600 is likely to occur. For example, the area with a strong magnetic field is In this case, only a specific area of ​​the target 600 will be used. As shown in FIG. 6B, the magnet unit 630 is rotated to rotate the target 60. Since plasma 640 is generated between the target 600 and the substrate 660, the target 600 is uniformly used. Furthermore, by rotating the magnet unit 630, it is possible to obtain a uniform Films with uniform thickness and quality can be deposited.

[0116] In addition, by rotating the magnet unit 630, the magnetic field on the upper surface of the substrate 660 The direction of the lines of force can also be changed.

[0117] Although an example in which the magnet unit 630 is rotated is shown here, one embodiment of the present invention is For example, the magnet unit 630 may be moved up and down and / or For example, the magnet unit 630 may be rotated at a frequency of 0.1 Hz or more. The target 600 may be oscillated at a beat of 1 kHz or less. Alternatively, the target 600 may be rotated or moved. For example, if you set Target 600 to a beat of 0.1Hz or more and 1kHz or less, Alternatively, the substrate 660 may be rotated or moved relative to the substrate 660. The direction of the magnetic field lines on the upper surface of 660 may be changed. It's okay to do that.

[0118] The film-forming chamber 601 may have a water channel inside or below the backing plate 610. Then, by flowing a fluid (air, nitrogen, rare gas, water, oil, etc.) through the waterway, spatter is At times, abnormal discharge occurs due to a rise in the temperature of the target 600, or deformation of the film forming chamber 601 occurs due to deformation of the components. At this time, the backing plate 610 and the target 6 00 via a bonding material is preferable because it improves cooling performance.

[0119] A gasket is provided between the target holder 620 and the backing plate 610. This is preferable because it makes it difficult for impurities to enter the film forming chamber 601 from the outside or water channels.

[0120] In the magnet unit 630, the magnet 630N and the magnet 630S are Each magnet is arranged with a different pole facing the target 600 side. The 30N magnet is placed so that the north pole is on the target 600 side, and the magnet 630S is placed on the target The case where the magnet unit 600 is positioned so that the south pole is the The arrangement of magnets and poles in the magnet 630 is not limited to this arrangement. Moreover, the arrangement is not limited to that shown in FIG. 6(A).

[0121] During film formation, the potential V1 applied to the terminal V1 connected to the target holder 620 is, for example, This potential is lower than the potential V2 applied to the terminal V2 connected to the substrate holder 670. The potential V2 applied to the terminal V2 connected to the substrate holder 670 is, for example, the ground potential. The potential V3 applied to the terminal V3 connected to the magnet holder 632 is, for example, , and the ground potential. The potentials applied to terminals V1, V2, and V3 are The target holder 620, the substrate holder 670, the magnet holder For example, if the substrate holder 670 is electrically In FIG. 6(A), the target holder 620 is connected to the target holder 620. Although an example of a so-called DC sputtering method in which a potential V1 is applied to the terminal V1 has been shown, One embodiment of the present invention is not limited to this. For example, the target holder 620 may be provided with a 13. RF sputtering, which connects to a high frequency power source such as 56MHz or 27.12MHz The ring method may also be used.

[0122] In addition, in FIG. 6(A), a backing plate 610 and a target holder 620 are An example in which the magnet unit 630 and the magnet holder 632 are not electrically connected is shown. For example, but not limited to, the backing plate 610 and the target hole The magnet unit 630 and the magnet holder 632 are electrically connected to each other. It does not matter if they are connected and have the same potential.

[0123] In order to further improve the crystallinity of the resulting oxide, the temperature of the substrate 660 may be increased. By increasing the temperature of the substrate 660, the amount of sputtered particles on the upper surface of the substrate 660 is reduced. This can promote migration, resulting in a denser, more crystalline The temperature of the substrate 660 is, for example, 100° C. or higher. 450°C or less, preferably 150°C or more and 400°C or less, more preferably 170°C or more The temperature should be 350°C or less.

[0124] Moreover, if the oxygen partial pressure in the film-forming gas is too high, an oxide film containing multiple types of crystal phases is likely to be formed. Therefore, the deposition gas is a rare gas such as argon (other gases include helium, neon, krypton, and xenon). It is preferable to use a mixed gas of oxygen and ethanol. For example, the ratio of oxygen to the total is Less than 50% by volume, preferably 33% by volume or less, more preferably 20% by volume or less, Preferably, the content is 15% by volume or less.

[0125] The vertical distance between the target 600 and the substrate 660 is preferably 10 mm or more and 600 mm or less. Preferably, it is 20 mm or more and 400 mm or less, and more preferably, it is 30 mm or more and 200 mm or less. More preferably, the distance between the target 600 and the substrate 660 is 40 mm or more and 100 mm or less. By bringing the vertical distance close to the above range, the sputtered particles reach the substrate 660. In addition, the decrease in energy between the target 600 and the substrate can be suppressed. By increasing the vertical distance between the substrate 660 and the sputtered particles to the above range, the sputtered particles can be prevented from entering the substrate 660. Since the direction of the irradiation can be made closer to perpendicular, damage to the substrate 660 due to the collision of the sputtered particles can be reduced. You might be able to reduce the image.

[0126] FIG. 7(A) shows an example of a film formation chamber different from that shown in FIG. 6(A).

[0127] The film forming chamber 601 shown in FIG. 7(A) includes a target holder 620a and a target holder 62b. 0b, backing plate 610a, backing plate 610b, and target 6 600a, target 600b, magnet unit 630a, and magnet unit 630b, a member 642, and a substrate holder 670. is placed on the backing plate 610a. The magnet unit 630a is placed on the target holder 620a. The target 600a is placed under the mounting plate 610a. The backing plate 600b is disposed on the backing plate 610b. 610b is placed on the target holder 620b. 0b is placed below the target 600b via a backing plate 610b.

[0128] The magnet unit 630a includes a magnet 630N1, a magnet 630N2, and a magnet The magnet unit 630S includes a magnet holder 632. In 630a, magnet 630N1, magnet 630N2 and magnet 63 The magnet 630N1 and the magnet 630N2 are placed on the magnet holder 632. The magnet 630N2 is placed at a distance from the magnet 630S. The magnet unit 630b has the same structure as the magnet unit 630a. When the substrate 660 is loaded into the chamber 601 , the substrate 660 is placed on the substrate holder 670 .

[0129] a target 600a, a backing plate 610a, and a target holder 620a; a target 600b, a backing plate 610b, and a target holder 620b; are separated by a member 642. The member 642 is preferably an insulator. However, the member 642 may be a conductor or a semiconductor. The surface of a conductor or semiconductor may be covered with an insulator.

[0130] The target holder 620a and the backing plate 610a are connected with screws (bolts, etc.). The target holder 620a is fixed to the backing plate 620b, and is at an equipotential. The target 600a is supported by the plate 610a. The holder 620b and the backing plate 610b are fixed together using screws (bolts, etc.). The target holder 620b is attached to the backing plate 61. 0b and has the function of supporting target 600b.

[0131] The backing plate 610a has a function of fixing the target 600a. The mounting plate 610b has a function of fixing the target 600b.

[0132] FIG. 7A shows the magnetic field lines 680a and magnetic Force lines 680b are shown.

[0133] The magnetic field lines 680a are the magnetic field lines that form the horizontal magnetic field near the top surface of the target 600a. The vicinity of the upper surface of the target 600a is, for example, a vertical distance from the target 600a. The distance is in the range of 0 mm to 10 mm, particularly in the range of 0 mm to 5 mm.

[0134] The magnetic field lines 680b extend from the top surface of the magnet unit 630a to the horizontal magnetic field at a vertical distance d. The vertical distance d is one of the magnetic field lines that form the field. is between 5mm and 15mm.

[0135] At this time, the strong magnet 630N1, the strong magnet 630N2 and the strong magnet By using the net 630S, a strong magnetic field is generated even near the top surface of the substrate 660. Specifically, the magnetic flux density of the horizontal magnetic field on the upper surface of the substrate 660 can be set to 10 G or more. 100G or less, preferably 15G or more and 60G or less, more preferably 20G or more and 40G or less It can be below.

[0136] By setting the magnetic flux density of the magnetic field in the film formation chamber 601 within the above range, a film having high density and crystalline Furthermore, the oxide obtained contains multiple types of crystal phases. The oxide contains little crystal phase and is almost entirely a single crystal phase.

[0137] The magnet unit 630b also generates magnetic lines of force similar to those of the magnet unit 630a. will be done.

[0138] FIG. 7B shows a top view of the magnet unit 630a and the magnet unit 630b. The magnet unit 630a includes a rectangular or substantially rectangular magnet 630N1. and rectangular or nearly rectangular magnet 630N2 and rectangular or nearly rectangular magnet It can be seen that the magnet 630S is fixed to the magnet holder 632. The mat unit 630a can be swung left and right as shown in FIG. For example, the magnet unit 630a can be oscillated at a beat of 0.1 Hz to 1 kHz. That's fine.

[0139] Therefore, the region of strong magnetic field on the target 600a is the region of strong magnetic field on the magnet unit 630a. The region with a strong magnetic field becomes a high-density plasma region, so the For example, in an area with a strong magnetic field, the sputtering phenomenon of the target 600a is likely to occur. If the target 600a is a specific location, only that specific area of ​​the target 600a will be used. On the other hand, as shown in FIG. 7(B), by swinging the magnet unit 630a, the Since plasma 640 is generated between the target 600a and the substrate 660, In addition, the magnet unit 630a can be oscillated. This allows deposition of a film with uniform thickness and quality.

[0140] In addition, by swinging the magnet unit 630a, the upper surface of the substrate 660 The state of the magnetic field lines can also be changed. The same is true.

[0141] Here, the magnet unit 630a and the magnet unit 630b are swung. However, one embodiment of the present invention is not limited to this. Alternatively, the light source unit 630a and the magnet unit 630b may be rotated. , the magnet unit 630a and the magnet unit 630b are set to 1 Hz or more. Alternatively, the target 600 can be rotated or moved. For example, you can set Target 600 with a beat of 0.1 Hz or more and 1 kHz or less. Alternatively, the substrate 660 may be rotated or moved relative to the substrate 660. The state of the magnetic field lines on the upper surface of 60 can be changed. It's okay to do that.

[0142] The film forming chamber 601 is provided with a backing plate 610a and a backing plate 610b. Alternatively, a water channel may be provided at the bottom or the like. The water channel may be filled with a fluid (air, nitrogen, rare gas, water, By flowing oil, the target 600a and the target 600b are This prevents abnormal discharge due to a rise in temperature and damage to the film forming chamber 601 due to deformation of the components. At this time, the backing plate 610a and the target 600a are bonded together. It is preferable to use a backing material to make the contact, as this will improve the cooling performance. When the target 610b and the target 600b are bonded together via a bonding material, the cooling performance is improved. This is preferable because it increases

[0143] A gasket is provided between the target holder 620a and the backing plate 610a. This is preferable because it makes it difficult for impurities to enter the film forming chamber 601 from the outside or from the water channel. In addition, a gasket is provided between the target holder 620b and the backing plate 610b. This is preferable because it makes it difficult for impurities to enter the film formation chamber 601 from the outside or from the water channel.

[0144] In the magnet unit 630a, the magnet 630N1 and the magnet 630N 2 and magnet 630S are arranged with different poles facing the target 600a side. Here, the magnet 630N1 and the magnet 630N2 are connected to the target 60 The magnet 630S is positioned so that the target 600a side is the S pole. However, the case where the magnet unit 630a is arranged so that The arrangement of the magnets and poles is not limited to this arrangement. The same applies to the magnet unit 630b. is.

[0145] During film formation, the potential applied to the terminal V1 connected to the target holder 620a and the target The potential applied to the terminal V4 connected to the holder 620b may be alternately high and low. The potential applied to the terminal V2 connected to the substrate holder 670 is, for example, a ground potential. The potential applied to the terminal V3 connected to the magnet holder 632 is, for example, , and the ground potential. Note that the voltages applied to terminals V1, V2, V3, and V4 are The potential is not limited to the above. 20b, the substrate holder 670, and the magnet holder 632 may not all be applied with a potential. For example, the substrate holder 670 may be electrically floating. Then, the potential applied to the terminal V1 connected to the target holder 620a and the potential of the target holder The potential applied to the terminal V4 connected to the lead 620b alternates between high and low. However, one embodiment of the present invention is not limited to this.

[0146] In addition, in FIG. 7(A), a backing plate 610a and a target holder 620a are The magnet unit 630a and the magnet holder 632 are not electrically connected. For example, the backing plate 610a and the turntable 610b are A get holder 620a, a magnet unit 630a and a magnet holder 632 , may be electrically connected and have the same potential. The target 610b and the target holder 620b, and the magnet unit 630b and the magnet Although an example in which the net holder 632 is not electrically connected is shown, the present invention is not limited to this. For example, a backing plate 610b and a target holder 620b, and a magnet unit The magnet holder 632 is electrically connected to the nozzle 630b and the magnet holder 632, and is at the same potential. It's okay if it's there.

[0147] In order to further improve the crystallinity of the resulting oxide, the temperature of the substrate 660 may be increased. By increasing the temperature of the substrate 660, the amount of sputtered particles on the upper surface of the substrate 660 is reduced. This can promote migration, resulting in a denser, more crystalline The temperature of the substrate 660 is, for example, 100° C. or higher. 450°C or less, preferably 150°C or more and 400°C or less, more preferably 170°C or more The temperature should be 350°C or less.

[0148] Moreover, if the oxygen partial pressure in the film-forming gas is too high, an oxide film containing multiple types of crystal phases is likely to be formed. Therefore, the deposition gas is a rare gas such as argon (other gases include helium, neon, krypton, and xenon). It is preferable to use a mixed gas of oxygen and ethanol. For example, the ratio of oxygen to the total is Less than 50% by volume, preferably 33% by volume or less, more preferably 20% by volume or less, Preferably, the content is 15% by volume or less.

[0149] The vertical distance between the target 600a and the substrate 660 is set to 10 mm or more and 600 mm or less. Preferably, it is 20 mm or more and 400 mm or less, and more preferably, it is 30 mm or more and 200 mm or less. More preferably, the distance between the target 600a and the substrate 660 is 40 mm or more and 100 mm or less. By reducing the vertical distance to the above range, sputtered particles can reach the substrate 660. In some cases, the decrease in energy between the target 600a and the target 600a can be suppressed. By increasing the vertical distance between the substrate 660 and the sputtered particles to the above range, the Since the incident direction of the sputtered particles on the substrate 660 can be made closer to perpendicular, the impact of the sputtered particles on the substrate 660 can be prevented. It may be possible to reduce damage to

[0150] The vertical distance between the target 600b and the substrate 660 is set to 10 mm or more and 600 mm or less. Preferably, 20 mm or more and 400 mm or less, and more preferably, 30 mm or more and 200 mm or less , and more preferably, 40 mm or more and 100 mm or less. By reducing the vertical distance to the above range, sputtered particles can reach the substrate 660. In some cases, the decrease in energy between the target 600b and the target 600b can be suppressed. By increasing the vertical distance between the substrate 660 and the sputtered particles to the above range, the Since the incident direction of the sputtered particles on the substrate 660 can be made closer to perpendicular, the impact of the sputtered particles on the substrate 660 can be prevented. It may be possible to reduce damage to

[0151] [Facing Target Sputtering System (VDSP)] Next, a facing target sputtering apparatus will be described. 8(A) is a cross-sectional view of a film formation chamber in a target-type sputtering apparatus. The target 600a and the target 600b are Backing plate 610a and backing plate 610b respectively hold the backing plate 610a and the backing plate 610b. 610b and the backing plate 610a and the backing plate 610b. The magnet units are arranged on the rear surfaces of the target 600a and the target 600b, respectively. The substrate holder 670 also includes a substrate holder 670a and a magnet unit 630b. The substrate holder 670 is disposed between the target 600a and the target 600b. The area between the target 600a and the target 600b (target After the substrate 660 is carried into the film formation chamber, The substrate 660 is fixed to a substrate holder 670 .

[0152] As shown in FIG. 8(A), the substrate holder 670 is disposed above the inter-target region. However, it may be disposed on the lower side, or it may be disposed on both the lower and upper sides. By disposing the substrate holders 670 on the upper and lower sides, two or more substrates can be simultaneously deposited. This allows for increased productivity.

[0153] As shown in FIG. 8(A), the backing plate 610a and the backing plate Power supplies 690 and 691 for applying a potential are connected to 610b. The potential applied to the backing plate 610a and the potential applied to the backing plate 610b are It is preferable to use a so-called AC power supply, which alternates between high and low voltages. The power supply 690 and the power supply 691 shown in FIG. 1 are examples using AC power supplies, but they are not limited to this. For example, an RF power supply, a DC power supply, or the like may be used as the power supply 690 and the power supply 691. Alternatively, different types of power supplies may be used for power supply 690 and power supply 691.

[0154] In addition, the substrate holder 670 is preferably connected to GND. 70 may be in a floating state.

[0155] 8(B) and 8(C) show the plasma 640 between the dashed line AB in FIG. 8(A). The potential distribution shown in FIG. 8(B) is the potential distribution on the backing plate 610a. A high potential is applied to the backing plate 610b, and a low potential is applied to the backing plate 610c. The positive ions are accelerated toward the target 600b. A low potential is applied to the backing plate 610a and a high potential is applied to the backing plate 610b. In other words, the positive ions are accelerated toward the target 600a. 8(C) and 8(D) can be alternately performed to form a film.

[0156] In the configuration shown in FIG. 8(A), a target 600a and a target 600b are parallel and face each other. The magnet unit 630a and the magnet unit 630b are arranged as follows. The magnets are arranged so that their poles face each other. is directed from magnet unit 630b to magnet unit 630a. During film formation, the magnet unit 630a and the magnet unit 630b are formed. The magnetic field confines the plasma 640. Therefore, the substrate holder 670 and the substrate 660 , located outside the plasma 640. The substrate 660 is exposed to the high electric field region of the plasma 640. Therefore, damage caused by the plasma 640 can be reduced.

[0157] The facing target sputtering device can generate plasma stably even in a high vacuum. For example, film formation is possible even at a pressure of 0.005 Pa or more and 0.09 Pa or less. Therefore, the concentration of impurities mixed in during film formation can be reduced.

[0158] By using a facing target sputtering device, film formation in a high vacuum is possible. Therefore, film formation with less damage caused by plasma is possible, and the temperature of the substrate 660 is low. For example, even if the temperature of the substrate 660 is 10 Even at temperatures above 100°C and below 100°C, a film with high crystallinity can be formed.

[0159] In the configuration shown in FIG. 9(A), the target 600a and the target 600b are not parallel to each other. The difference from the configuration shown in Figure 8(A) is that they are arranged facing each other in a tilted state (V-shape). Therefore, for details other than the placement of the targets, please refer to the explanation of FIG. 8(A). The magnet unit 630a and the magnet unit 630b are arranged so that their opposite poles face each other. The substrate holder 670 and the substrate 660 are positioned above the inter-target area. The target 600a and the target 600b are arranged as shown in FIG. By using this position, the proportion of sputtered particles that reach the substrate 660 increases, thereby increasing the deposition rate. It can be made higher.

[0160] FIG. 9(B) shows another example of a facing target sputtering apparatus.

[0161] FIG. 9(B) is a cross-sectional schematic diagram of a film formation chamber in a facing target sputtering apparatus. Unlike the film formation chamber shown in FIG. 8(A), the target shield 622 and the target sheet A backing plate 610a and a backing plate 623 are provided. The substrate holder 670 has a power supply 691 connected to the port 610b. This prevents the substrate 660 from being exposed to the high electric field region of the plasma 640. Therefore, damage caused by the plasma 640 can be reduced.

[0162] As shown in FIG. 9(B), the substrate holder 670 is disposed above the inter-target region. However, it may be disposed on the lower side, or it may be disposed on both the lower and upper sides. By disposing the substrate holders 670 on the upper and lower sides, two or more substrates can be simultaneously deposited. This allows for increased productivity.

[0163] As shown in FIG. 9B, the target shield 622 and the target shield 6 23 is connected to GND. In other words, the backing plate 23 is connected to the backing plate 23 to which the potential of the power supply 691 is applied. The plate 610a and backing plate 610b are connected to the target system with GND. A potential difference applied between the target shield 622 and the target shield 623 causes the pump A plasma 640 is formed.

[0164] In the facing target sputtering device described above, the plasma is generated by the magnetic field between the targets. Because the plasma is confined, it is possible to reduce plasma damage to the substrate. The angle of incidence of sputtered particles on the substrate can be made shallow by tilting the nozzle. This improves the step coverage of the deposited film. Also, film deposition in a high vacuum is possible. Therefore, the concentration of impurities mixed into the film can be reduced.

[0165] In addition, a parallel plate sputtering device and an ion beam sputtering device are installed in the film formation chamber. It is okay to use it.

[0166] <Film forming equipment> The following describes a composition in which a sputtering target according to one aspect of the present invention can be installed. A film forming apparatus having a film chamber will be described.

[0167] First, let us look at the structure of the film formation equipment that minimizes the amount of impurities mixed into the film during film formation. This will be explained using FIG.

[0168] FIG. 10 is a schematic top view of a single-wafer multi-chamber film-forming apparatus 2700. As shown in FIG. The film forming apparatus 2700 includes a cassette port 2761 for accommodating a substrate and a and an atmosphere-side substrate supply chamber 2701 having an alignment port 2762 for performing alignment. The substrate is transported from the supply chamber 2701 to the atmospheric substrate transport chamber 2702, and a load lock chamber 2 for switching the pressure in the chamber from atmospheric pressure to reduced pressure or from reduced pressure to atmospheric pressure. 703a, the substrate is removed, and the pressure in the chamber is reduced to atmospheric pressure or reduced from atmospheric pressure. and an unload lock chamber 2703b for switching to a vacuum state, and a transfer chamber 27 04, a substrate heating chamber 2705 for heating the substrate, and a film forming chamber in which a target is placed and a film is formed. The film forming chamber 2706 includes a film forming chamber 2706a, a film forming chamber 2706b, and a film forming chamber 2706c. The film forming chambers 706a, 2706b, and 2706c are configured in accordance with the configuration of the film forming chambers described above. It is possible.

[0169] The atmospheric substrate transfer chamber 2702 is provided with a load lock chamber 2703a and an unload lock chamber 2703b. The load lock chamber 2703a and the unload lock chamber 2703b are connected to each other. b is connected to a transfer chamber 2704, which is connected to a substrate heating chamber 2705, a film forming chamber 2706, and a 06a, and is connected to the film formation chamber 2706b and the film formation chamber 2706c.

[0170] A gate valve 2764 is provided at the connection between the chambers, and the atmosphere-side substrate supply chamber 27 Except for the atmospheric side substrate transfer chamber 2701 and the atmospheric side substrate transfer chamber 2702, each chamber can be independently maintained in a vacuum state. The atmospheric substrate transfer chamber 2702 and the transfer chamber 2704 are connected by a transfer robot 2763. and capable of transporting a substrate.

[0171] It is also preferable that the substrate heating chamber 2705 also serves as a plasma processing chamber. Since the substrate can be transported between processes without being exposed to the atmosphere, impurities in the substrate can be prevented. It is possible to suppress the adsorption of substances. In addition, the order of film formation and heat treatment can be freely configured. In addition, the transfer chamber, film formation chamber, load lock chamber, unload lock chamber and substrate heating chamber The number is not limited to the above, and the optimum number can be set according to the installation space and process conditions. It can be done.

[0172] Next, the dashed dotted line X1-X2, the dashed dotted line Y1-Y2, and the dashed dotted line Y1-Y2 of the film forming apparatus 2700 shown in FIG. A cross section corresponding to the dashed line Y2-Y3 is shown in FIG.

[0173] FIG. 11(A) shows a cross section of the substrate heating chamber 2705 and the transfer chamber 2704. The chamber 2705 has a number of heated stages 2765 capable of accommodating substrates. The substrate heating chamber 2705 is connected to a vacuum pump 2770 via a valve. The air pump 2770 may be, for example, a dry pump or a mechanical booster pump. etc. can be used.

[0174] In addition, examples of heating mechanisms that can be used in the substrate heating chamber 2705 include a resistance heating element. Alternatively, a heating mechanism using a medium such as a heated gas may be used. The heating mechanism may be one that heats by thermal conduction or thermal radiation. For example, GRTA (Ga s Rapid Thermal Anneal), LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) al) can be used. LRTA is compatible with halogen lamps, metal halide lamps, and Xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure mercury lamps, etc. The object to be treated is heated by the radiation of light (electromagnetic waves) emitted from each lamp. The heat treatment is carried out using a gas at a temperature of 1000°C, and an inert gas is used as the gas.

[0175] The substrate heating chamber 2705 is connected to a refiner 278 via a mass flow controller 2780. 1. The mass flow controller 2780 and the refiner 2781 are connected to the gas Although the number of the heating chambers is equal to the number of types, only one is shown for ease of understanding. The gas to be introduced has a dew point of -80°C or less, preferably -100°C or less. For example, oxygen gas, nitrogen gas, and rare gas (such as argon gas) can be used. .

[0176] The transfer chamber 2704 has a transfer robot 2763. The transfer robot 2763 transfers the The transfer chamber 2704 can transfer the substrate to the vacuum pump 2 770 and a cryopump 2771 are connected. The transfer chamber 2704 is evacuated from atmospheric pressure to low or medium vacuum (approximately 0.1 to several hundred Pa). Pump 2770 is used to evacuate the air, and valves are switched to change the vacuum from medium to high or ultra-high. (0.1 Pa to 1×10 -7 The pumping temperature is up to 100 Pa using the cryopump 2771. .

[0177] In addition, for example, two or more cryopumps 2771 are connected in parallel to the transfer chamber 2704. With this configuration, even if one cryopump is in the regeneration Even if the temperature is low, the remaining cryopump can be used to pump the remaining gas. This refers to the process of releasing molecules (or atoms) stored in the cryopump. If the ion pump accumulates too many molecules (or atoms), its pumping capacity will decrease. Periodic regeneration occurs.

[0178] FIG. 11(B) shows the film-forming chamber 2706b, the transfer chamber 2704, and the load-lock chamber 2703a. A cross section is shown.

[0179] Here, the film formation chamber (sputtering chamber) will be described in detail with reference to FIG. 11(B). The film forming chamber 2706b shown in FIG. 11(B) includes a target 2766a and a target 2766b. b, a target shield 2767a, a target shield 2767b, and a magnet unit 2790a, magnet unit 2790b, substrate holder 2768, and power supply Although not shown, the target 2766a and the target 2766 b are fixed to the target holder via a backing plate. The get 2766a and the target 2766b are electrically connected to a power supply 2791. The magnet unit 2790a and the magnet unit 2790b are respectively The target sheet is placed behind the target 2766a and the target 2766b. Target shield 2767a and target shield 2767b are respectively and the end of the target 2766b. The substrate holder 2768 supports a substrate 2769. The substrate holder 2768 is a variable member 278. The substrate holder 27 is fixed to the film forming chamber 2706b via the variable member 2784. The substrate holder 2768 can move the target 2766a and the target It is located above the area between the target 2766b (also called the inter-target area). For example, a substrate holder 2768 supporting a substrate 2769 may be placed above the inter-target region. This reduces plasma damage. Although not shown, the substrate holding mechanism for holding the substrate 2769 and the mechanism for pressing the substrate 2769 from the rear side are also included. A heater or the like may be provided.

[0180] As shown in FIG. 11(B), the substrate holder 2768 is disposed above the inter-target region. However, it may be placed on the bottom side. It may also be placed on both the bottom and top sides. By arranging the substrate holders 2768 on the lower and upper sides, two or more substrates can be simultaneously Since the film can be formed easily, productivity can be increased.

[0181] In addition, the target shield 2767 prevents sputtering from the target 2766. The target shield 2767 prevents particles from being deposited in unwanted areas. It is desirable to process the surface so that the deposited sputtered particles do not peel off. For example, To increase the effectiveness of blasting, or to create irregularities on the surface of the target shield 2767 good.

[0182] The deposition chamber 2706b is connected to the mass flow controller 27 via a gas heating mechanism 2782. 80, and the gas heating mechanism 2782 is purified via the mass flow controller 2780. The gas is introduced into the deposition chamber 2706b by a gas heating mechanism 2782. The gas can be heated to 40°C or higher and 400°C or lower. The mass flow controllers 2780 and refiners 2781 are provided in the same number as the number of gas species. However, only one of them is shown for ease of understanding. A gas having a temperature of -80°C or lower, preferably -100°C or lower, can be used. For example, The gas used is a rare gas (such as argon gas), nitrogen gas, or a rare gas.

[0183] In addition, when a refiner is provided immediately before the gas inlet, the distribution from the refiner to the deposition chamber 2706b The length of the pipe should be 10 m or less, preferably 5 m or less, and more preferably 1 m or less. By limiting the length to 10m or less, 5m or less, or 1m or less, the effects of gases emitted from the piping can be reduced. The reduction can be achieved depending on the length. In addition, the gas piping is It is recommended to use metal piping with the inside coated with chrome or the like. The piping mentioned above is made of, for example, SUS3 Compared to 16L-EP piping, the amount of gas containing impurities released is smaller, and the amount of impurities that enter the gas is reduced. In addition, high-performance ultra-small metal gasket joints (UPG joints) are used for the piping joints. In addition, by constructing the piping entirely from metal, it is possible to reduce the This is preferable because it can reduce the effects of released gas and external leakage.

[0184] The film-forming chamber 2706b is connected to a turbomolecular pump 2772 and a vacuum pump 2773 via a valve. It is connected to 2770.

[0185] The film formation chamber 2706b is provided with a cryotrap 2751.

[0186] Cryotrap 2751 adsorbs molecules (or atoms) with relatively high melting points, such as water. The turbomolecular pump 2772 is a mechanism that can pump large molecules (or atoms). ) and requires little maintenance, making it highly productive. The pumping capacity for water is low. Therefore, in order to improve the pumping capacity for water, etc., a cryotrap is used. The cryotrap 2751 is connected to the film forming chamber 2706b. The temperature of the refrigerator is set to 100 K or less, preferably 80 K or less. If the 751 has multiple refrigerators, changing the temperature of each refrigerator will allow for efficient exhaust. For example, the temperature of the first stage refrigerator is set to 100 K or less, and the second stage The temperature of the first refrigerator should be set to 20 K or less. A higher vacuum may be achieved by using a sublimation pump. In addition, by using an ion pump instead of a cryopump or turbomolecular pump, In some cases, a high vacuum can be achieved.

[0187] The method of exhausting the film forming chamber 2706b is not limited to this, and may be the same as the exhaust method shown in the transfer chamber 2704. It may be configured in the same way as the evacuation method (the evacuation method using a cryopump and a vacuum pump). The exhaust method of the transfer chamber 2704 is the same as that of the film forming chamber 2706b (turbo molecular pump and It is also possible to use an empty pump as an exhaust method.

[0188] In addition, the back pressure ( The total pressure and the partial pressure of each gas molecule (atom) are preferably as follows. Since there is a possibility that impurities may be mixed into the film to be formed, the back pressure of the film forming chamber 2706b, etc. It is also necessary to pay attention to the partial pressure of each gas molecule (atom).

[0189] The back pressure (total pressure) of each chamber mentioned above is 1 x 10 -4 Pa or less, preferably 3×10 -5 Pa or less, more preferably 1 × 10 -5 The mass-to-charge ratio (m / z The partial pressure of a gas molecule (atom) with a mass of 18 is 3 x 10 -5 Pa or less, preferably 1×10 -5Pa or less, more preferably 3×10 -6 Pa or less. In addition, the m The partial pressure of a gas molecule (atom) with a z of 28 is 3 x 10 -5 Pa or less, preferably 1 x 1 0 -5 Pa or less, more preferably 3×10 -6 Pa or less. The partial pressure of a gas molecule (atom) with m / z 44 is 3 x 10 -5 Pa or less, preferably 1× 10 -5 Pa or less, more preferably 3×10 -6 Pa or less.

[0190] The total pressure and partial pressure in the vacuum chamber can be measured using a mass spectrometer. For example, a quadrupole mass spectrometer (also called Q-mass) manufactured by ULVAC, Inc. ee Just use CGM-051.

[0191] The transfer chamber 2704, the substrate heating chamber 2705, and the film forming chamber 2706b are externally It is desirable to have a configuration with little leakage or internal leakage.

[0192] For example, the above-mentioned transfer chamber 2704, substrate heating chamber 2705, and film forming chamber 2706b The crate is 3 x 10 -6 Pa·m 3 / s or less, preferably 1 × 10 -6 Pa·m 3 / s In addition, the leak rate of gas molecules (atoms) with m / z of 18 is 1 × 10 -7 Pa·m 3 / s or less, preferably 3 × 10 -8 Pa·m 3 / s or less. The leak rate of gas molecules (atoms) with a value of 28 is 1×10 -5 Pa·m 3 / s or less, preferred Or 1 x 10 -6 Pa·m 3 / s or less. Also, gas molecules with m / z of 44 (atomic The leak rate of the child is 3×10 -6 Pa·m 3 / s or less, preferably 1×10 -6 Pa· m 3 / s or less.

[0193] The leak rate was calculated from the total pressure and partial pressure measured using the mass spectrometer mentioned above. It can be derived.

[0194] The leak rate depends on external and internal leaks. External leaks occur due to small holes or seals. An internal leak is when gas flows in from outside the vacuum system due to a valve malfunction or other reasons. This is caused by leaks from valves and other partitions, or by gas released from internal components. In order to keep the above figure or less, it is necessary to take measures against both external and internal leaks. There is.

[0195] For example, the opening and closing portion of the film forming chamber 2706b may be sealed with a metal gasket. Sketches are metals coated with iron fluoride, aluminum oxide, or chromium oxide. It is recommended to use a metal gasket. Metal gaskets have a higher adhesion than O-rings and reduce external leakage. It is also possible to use metals coated with iron fluoride, aluminum oxide, chromium oxide, etc. By using a passivation material, the gas released from the metal gasket containing impurities is suppressed. This reduces internal leakage.

[0196] In addition, the film forming apparatus 2700 is made of aluminum, which emits less gas containing impurities. Cr, Ti, Zr, Ni or V is used. The above members may be coated with an alloy containing iron, chromium, nickel, etc. Alloys containing copper and nickel are rigid, heat resistant, and easy to process. Therefore, if the surface roughness of the component is reduced by polishing or other methods to reduce the surface area, the release Gas can be reduced.

[0197] Alternatively, the components of the film forming apparatus 2700 may be replaced with iron fluoride, aluminum oxide, chromium oxide, etc. It may be coated with

[0198] It is preferable that the members of the film forming apparatus 2700 are made of metal only, for example, quartz. When installing a viewing window, the surface must be coated with iron fluoride or acid to suppress gas emission. It is recommended to thinly coat the surface with aluminum oxide or chromium oxide.

[0199] The adsorbates present in the film deposition chamber are adsorbed to the inner walls, etc., and do not affect the pressure in the film deposition chamber. This causes gas emission when the deposition chamber is evacuated. Therefore, the leak rate is proportional to the evacuation speed. Although there is no problem, it is recommended to use a pump with high exhaust capacity to remove as much of the adsorbed matter as possible from the deposition chamber. It is important to desorb and evacuate the adsorbed material beforehand. The deposition chamber may be baked. Baking increases the desorption rate of adsorbed substances by about 10 times. Baking can be done at a temperature between 100°C and 450°C. When removing adsorbed substances while introducing an inert gas into the film-forming chamber, the adsorbed substances cannot be removed by simply evacuating the chamber. The desorption rate of water and other substances can be further increased. By heating the catalyst to the same temperature as the working temperature, the desorption rate of the adsorbed substances can be further increased. Here, it is preferable to use a rare gas as the inert gas. Oxygen or the like may be used instead of the inert gas. For example, when forming an oxide film, In some cases, it is preferable to use oxygen, which is the main component. It is preferable to do this.

[0200] Alternatively, the pressure in the deposition chamber may be increased by introducing an inert gas such as a heated rare gas or oxygen. It is preferable to increase the pressure and then evacuate the film formation chamber again after a certain period of time has elapsed. By introducing the gas, it is possible to desorb the adsorbed substances in the film formation chamber, and the impurities present in the film formation chamber are reduced. This treatment can be repeated 2 to 30 times, preferably 5 to 15 times. It is effective to repeat the process within the following range: Specifically, the temperature is between 40°C and 400°C. By introducing an inert gas or oxygen, etc., preferably at a temperature of 50°C or higher and 200°C or lower, The pressure in the film formation chamber is set to 0.1 Pa or more and 10 kPa or less, preferably 1 Pa or more and 1 kPa or less. More preferably, the pressure is set to 5 Pa or more and 100 Pa or less, and the pressure is maintained for 1 minute or more and 300 minutes or more. The film formation chamber is then heated for 5 to 300 minutes, preferably for 5 to 120 minutes. Thereafter, evacuation is preferably carried out for a period of 10 minutes or more and 120 minutes or less.

[0201] Furthermore, the desorption rate of the adsorbed substances can be further increased by forming a dummy film. Film formation is performed on a dummy substrate by sputtering or other methods. A film is deposited on the plate and the inner wall of the film-forming chamber, and impurities in the film-forming chamber and substances adsorbed on the inner wall of the film-forming chamber are removed from the film. The dummy substrate is preferably one that emits less gas. By performing this, the impurity concentration in the film to be formed later can be reduced. The film formation may be carried out simultaneously with the baking.

[0202] Next, the transfer chamber 2704 and the load lock chamber 2703a shown in FIG. 11(B) and the The atmospheric substrate transfer chamber 2702 and the atmospheric substrate supply chamber 2701 shown in (C) are shown in detail below. 11(C) shows the atmospheric side substrate transfer chamber 2702 and the atmospheric side substrate A cross section of the plate supply chamber 2701 is shown.

[0203] The transfer chamber 2704 shown in FIG. 11(B) is the same as the transfer chamber 2704 shown in FIG. 11(A). Please refer to the above.

[0204] The load lock chamber 2703a includes a substrate transfer stage 2752. 2703a increases the pressure from a reduced pressure state to the atmosphere, and the pressure in the load lock chamber 2703a When the pressure reaches atmospheric pressure, the transfer robot 276 installed in the atmospheric side substrate transfer chamber 2702 3 to the substrate transfer stage 2752. 3a is evacuated to a reduced pressure state, and then the transfer robot provided in the transfer chamber 2704 2763 receives the substrate from the substrate delivery stage 2752 .

[0205] The load lock chamber 2703a is connected to a vacuum pump 2770 and a cryogenic It is connected to the vacuum pump 2770 and the cryopump 2771. The exhaust system of 1 can be connected by referring to the connection method of the transfer chamber 2704. The unload lock chamber 2703b shown in FIG. It can have the same configuration as the lock chamber 2703a.

[0206] The atmospheric substrate transfer chamber 2702 has a transfer robot 2763. This allows the transfer of substrates between the cassette port 2761 and the load lock chamber 2703a. In addition, the atmosphere-side substrate transfer chamber 2702 and the atmosphere-side substrate supply chamber 2701 are located above the chamber. HEPA filter (High Efficiency Particulate Air Filter) A mechanism for cleaning dust or particles such as a filter may be provided. .

[0207] The atmosphere-side substrate supply chamber 2701 has a plurality of cassette ports 2761. 2761 can accommodate multiple substrates.

[0208] The target surface temperature is 100°C or less, preferably 50°C or less, and more preferably room temperature. In sputtering equipment that can handle large-area substrates, the temperature should be around 25°C. However, targets of a size corresponding to a large area are often used. It is difficult to fabricate the targets without any seams. Although they are arranged in a way that creates a large shape, small gaps inevitably occur. As the surface temperature of the target rises, zinc and other materials volatilize from the small gap, gradually filling the gap. If the gap widens, the backing plate or The metal of the bonding material used to bond the electrode and target is sputtered. This increases the impurity concentration. It is preferable that

[0209] Specifically, a metal having high electrical conductivity and high heat dissipation properties (e.g., In addition, a water channel is formed in the backing plate, and a sufficient amount of By flowing cooling water, the target can be cooled efficiently.

[0210] When the target contains zinc, the plasma damage is reduced by forming the film in an oxygen gas atmosphere. This reduces the image and makes it possible to obtain an oxide in which zinc is less likely to volatilize.

[0211] By using the above-mentioned film forming apparatus, the hydrogen concentration can be measured by secondary ion mass spectrometry (SIMS). 2×10 2 0 atoms / cm 3 Less than or equal to 5 x 10 19 atoms / cm 3 The following is more preferred: Or 1 x 10 19 atoms / cm 3 Less than 5 × 10, more preferably 18 atoms / cm 3 The following oxide semiconductor film can be formed.

[0212] In addition, the nitrogen concentration is 5×10 19 atoms / cm 3 Less than, preferably is 1 x 10 19 atoms / cm 3 Less than or equal to 5 × 10 18 atoms / cm 3 or less, more preferably 1 × 10 18 atoms / cm 3 The oxide semiconductor It can be filmed.

[0213] In addition, the carbon concentration was 5×10 19 atoms / cm 3 Less than, preferably is 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 The oxide semiconductor It can be filmed.

[0214] An oxide with few impurities and oxygen vacancies has a low carrier density. Carrier density is 8×10 11 / cm 3 Less than 1 x 10 11 / cm 3 Less than, more Preferably 1 x 10 10 / cm 3 Less than 1 x 10 -9 / cm 3 The above Such an oxide semiconductor can be used as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. CAAC-OS has a low impurity concentration and a low density of defect states. It can be said that it is an oxide with such properties.

[0215] In addition, gas molecules (atoms) with m / z of 2 (such as hydrogen molecules) by TDS, and gas molecules with m / z of 18 A gas molecule (atom) with m / z 28 and a gas molecule (atom) with m / z 44 The amount of gas molecules (atoms) released is 1×10 19 pieces / cm 3 Below, preferably 1 x 1 0 18 pieces / cm 3 The following oxide semiconductor film can be formed.

[0216] By using the above film forming apparatus, it is possible to suppress the inclusion of impurities in the oxide. By using the film forming device, the film that comes into contact with the oxide is formed, and the oxide is removed from the film that comes into contact with the oxide. This can prevent impurities from being mixed into the product.

[0217] As described above, the structure shown in this embodiment may be appropriately combined with structures shown in other embodiments or examples. They can be used in combination.

[0218] (Embodiment 3) In this embodiment mode, one mode of a semiconductor device will be described with reference to FIGS.

[0219] <Transistor structure 1> An example of a transistor according to one embodiment of the present invention will be described below. 12B and 12C are top views and diagrams of a transistor according to one embodiment of the present invention. 12(A) is a top view, and FIG. 12(B) is a cross-sectional view of the part shown in FIG. 12(A). The dashed dotted line X1-X2 and FIG. 12(C) are cross-sectional views corresponding to the dashed dotted line Y1-Y2. In the top view of FIG. 12(A), some elements are omitted for clarity.

[0220] The transistor 200 includes a conductor 205 (conductor 205a, and and conductor 205b), and conductor 260, and insulator 220 which functions as a gate insulating layer. , insulator 222, insulator 224, and insulator 250, and a region in which a channel is formed. The oxide 230 (oxide 230a, oxide 230b, and oxide 230c) and the source A conductor 240a functions as either a source or a drain, and a conductor 240b functions as either a source or a drain. a conductor 240b that functions as a barrier; an insulator 280 that has excess oxygen; and and an insulator 282.

[0221] The oxide 230 is made up of an oxide 230a, an oxide 230b on the oxide 230a, and an oxide and an oxide 230c on the surface 230b. Current flows mainly through the oxide 230b (a channel is formed). The oxide 230a and the oxide 230c are in the vicinity of the interface with the oxide 230b (when they are in a mixed region). In some cases, current may flow through the area, but other areas may act as insulators. There is.

[0222] Also, as shown in FIG. 12, oxide 230c is formed by combining oxide 230a and oxide 230b. It is preferable that the insulator 280 and the region where the channel is formed are provided so as to cover the side surfaces of the insulator 280 and the region where the channel is formed. The oxide 230c is interposed between the oxide 230b and the insulator 280. Therefore, impurities such as hydrogen, water, and halogens are prevented from diffusing into the oxide 230b. It is possible.

[0223] The conductor 205 may be made of molybdenum, titanium, tantalum, tungsten, aluminum, copper, A metal film containing an element selected from chromium, neodymium, and scandium, or Metal nitride films (tantalum nitride film, titanium nitride film, molybdenum nitride film, tantalum nitride film, In particular, metal nitride films such as tantalum nitride films are highly susceptible to hydrogen and oxygen. It is preferable because it has a barrier property against oxidation and is resistant to oxidation (high oxidation resistance). Indium tin oxide, including tungsten oxide Indium oxide, including tungsten oxide Indium zinc oxide containing titanium oxide, indium oxide containing titanium oxide Indium tin oxide, indium zinc oxide, indium tin oxide with silicon oxide added, etc. Conductive materials may also be applied.

[0224] For example, titanium nitride is used as the conductor 205a as a conductor having a barrier property against hydrogen. It is preferable to use tungsten or the like as the conductor 205b, and to stack tungsten, which has high conductivity. By using this combination, it is possible to prevent water from being transferred to the oxide 230 while maintaining the electrical conductivity of the wiring. In FIG. 12, the conductor 205a and the conductor 205b are Although the two-layer structure of 05b is shown, it is not limited to this configuration and may be a single layer or a laminated structure of three or more layers. For example, a conductive material having a barrier property may be placed between a conductive material having a barrier property and a conductive material having a high conductivity. A conductor having high adhesion to a conductor with high conductivity may be formed.

[0225] The insulator 224 is an insulator containing oxygen, such as a silicon oxide film or a silicon oxynitride film. In particular, the insulator 224 contains excess oxygen (a composition other than the stoichiometric composition). It is preferable to use an insulator containing excess oxygen. By providing the oxide 230 that constitutes the transistor 200 in contact with the oxide 230, It is possible to compensate for the oxygen deficiency in the silicon dioxide.

[0226] Also, if the insulator 224 has an excess oxygen region, the insulator 222 will have oxygen, hydrogen, and It is preferable that the insulator 222 has a barrier property against oxygen and water. By having this, the oxygen in the excess oxygen region does not diffuse to the transistor 300 side, and the efficiency The conductor 205 can be efficiently supplied to the oxide 230. This can suppress the reaction with oxygen in the excess oxygen region.

[0227] The insulator 222 may be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or aluminum oxide. Aluminum, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3) or (Ba,Sr)TiO3( It is preferable to use an insulator such as BST in a single layer or laminated form. Use insulating films with barrier properties against oxygen and hydrogen, such as hafnium oxide and hafnium oxide. When such a material is used, the release of oxygen from the oxide 230 is preferable. It also functions as a layer that prevents impurities such as hydrogen from entering from the outside.

[0228] Alternatively, for example, aluminum oxide, bismuth oxide, or germanium oxide may be added to these insulators. Niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, Alternatively, zirconium oxide may be added to these insulators, or these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the insulator.

[0229] The insulators 220, 222, and 224 each have a laminated structure of two or more layers. In this case, the laminated structure is not limited to the same material, and may be made of different materials. A laminated structure may also be used.

[0230] In addition, an insulator 222 containing a high-k material is provided between the insulator 220 and the insulator 224. By doing so, the insulator 222 can capture electrons under certain conditions, increasing the threshold voltage. That is, the insulator 222 may become negatively charged.

[0231] For example, silicon oxide is used for the insulators 220 and 224, and silicon dioxide is used for the insulator 222. Materials with many electron capture levels, such as hafnium oxide, aluminum oxide, and tantalum oxide, are used. If the temperature is higher than the operating or storage temperature of the semiconductor device (for example, 125°C), The electric potential of the conductor 205 is The potential of the source electrode or drain electrode is kept higher than that of the source electrode or drain electrode for 10 milliseconds or more, typically 1 minute or more. By maintaining the above, the oxide constituting the transistor 200 is directed to the conductor 205. At this time, some of the moving electrons are captured by the electron capture level of the insulator 222. can be.

[0232] The transistor in which the necessary number of electrons are captured in the electron capture level of the insulator 222 has a threshold voltage The voltage of the conductor 205 is shifted to the positive side. This allows the threshold voltage to be controlled accordingly. By having this, the transistor 200 is in a non-conducting state (off state) even when the gate voltage is 0V. The transistor is a normally-off transistor (also called a normally-off transistor).

[0233] The electron capture process may be performed during the manufacturing process of a transistor. after forming a conductor that connects to the source or drain conductor of the transistor, or After the end of the pre-process (wafer processing), after the wafer dicing process, or after packaging It is advisable to carry out this at any stage before shipping from the factory, such as:

[0234] In addition, by appropriately adjusting the film thicknesses of the insulators 220, 222, and 224, The threshold voltage can be controlled. For example, the insulator 220, the insulator 222, and the insulator By reducing the total thickness of the insulator 224, the voltage from the conductor 205 is applied efficiently, and the power consumption is reduced. A transistor with low power consumption can be provided. The total thickness of the insulating layer 224 is preferably 65 nm or less, more preferably 20 nm or less. It's nice.

[0235] Therefore, it is possible to provide a transistor with a small leakage current when it is not conducting. Alternatively, a transistor having stable electrical characteristics can be provided. Alternatively, a transistor with a small subthreshold swing value can be provided. Alternatively, a highly reliable transistor can be provided. It is possible.

[0236] The oxide 230a, the oxide 230b, and the oxide 230c are In-M-Zn oxide (M The oxide 230 is formed of a metal oxide such as Al, Ga, Y, or Sn. Alternatively, In-Ga oxide or In-Zn oxide may be used.

[0237] Note that the oxide 230b may be formed using the oxide semiconductor described in the above embodiment. It can be used.

[0238] In addition, the oxide 230a and the oxide 230b, and the oxide 230b and the oxide 230c are formed of a material other than oxygen. By having a common element (main component) in both layers, a mixed layer with a low defect level density can be formed. For example, when the oxide 230b is an In-Ga-Zn oxide, the oxide 230a As the oxide 230c, In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide, etc. It is best to use something like this.

[0239] At this time, the main carrier path is oxide 230b. The defect density at the interface between oxide 230b and oxide 230c is Therefore, the influence of interface scattering on carrier conduction is small, and a high on-state current is achieved. flow is obtained.

[0240] When electrons are captured in the trap level, the captured electrons behave like fixed charges. Therefore, the threshold voltage of the transistor is shifted in the positive direction. By providing the oxide 230c, the trap level can be moved farther away from the oxide 230b. This structure allows the threshold voltage of the transistor to be shifted in the positive direction. This can prevent the following.

[0241] The oxide 230a and the oxide 230c are materials having sufficiently low electrical conductivity compared to the oxide 230b. At this time, the oxide 230b, the interface between the oxide 230b and the oxide 230a, and The interface between oxide 230b and oxide 230c mainly functions as a channel region.

[0242] For example, the oxide 230b may be formed by forming a complex between the region A2 and the region B2 in FIG. When oxides are used, the oxide 230a and the oxide 230c have an [M] / [In] ratio of 1 or more. Therefore, it is preferable to use an oxide having a ratio of 2 or more. Therefore, the ratio [M] / ([Zn]+[In]) is 1 or more, which allows for sufficiently high insulation. It is preferable to use an oxide having such a structure.

[0243] The insulator 250 may be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or aluminum oxide. Aluminum, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3) or (Ba,Sr)TiO3( Insulators such as BST can be used in a single layer or laminated layer. For example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide Titanium oxide, tungsten oxide, yttrium oxide, and zirconium oxide may be added. Alternatively, these insulators may be nitrided. Alternatively, silicon dioxide or silicon nitride may be laminated.

[0244] Also, like the insulator 224, the insulator 250 contains more oxygen than the stoichiometric composition. It is preferable to use an oxide insulator containing excess oxygen. By providing the oxide 230 in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced. Cut.

[0245] The insulator 250 may be aluminum oxide, aluminum oxynitride, gallium oxide, or oxide. Gallium nitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride Use insulating films such as silicon nitride and silicon nitride that have barrier properties against oxygen and hydrogen. When such a material is used, oxygen is released from the oxide 230 and the outside It functions as a layer that prevents impurities such as hydrogen from entering from the inside.

[0246] The insulator 250 is a laminated material similar to the insulators 220, 222, and 224. The insulator 250 may have a structure in which the insulator 250 captures the necessary number of electrons for the electron capture level. By including an insulator, the threshold voltage of the transistor 200 can be shifted to the positive side. By having this configuration, the transistor 200 can The transistor is a normally-off transistor that is in a non-conducting state (also referred to as an off state) even when the transistor is turned on.

[0247] In addition, in the transistor shown in FIG. 12, an insulator is provided between the oxide 230 and the conductor 260. A barrier film may be provided in addition to 250. Alternatively, the oxide 230c may have barrier properties. may also be used.

[0248] For example, an insulating film containing excess oxygen is provided in contact with the oxide 230, and then the insulating film is further wrapped with a barrier film. By this, the oxide is made to have a state where the composition is almost the same as the stoichiometric composition, or a state where the composition is smaller than the stoichiometric composition. It is possible to create a supersaturated state with a high oxygen content. It can prevent intrusion.

[0249] One of the conductors 240a and 240b functions as a source electrode and the other as a drain electrode. It functions as a rain electrode.

[0250] The conductor 240a and the conductor 240b are made of aluminum, titanium, chromium, nickel, copper, or the like. , yttrium, zirconium, molybdenum, silver, tantalum, or tungsten Metals or alloys containing metals as the main component can be used. In particular, tantalum nitride films, etc. The metal nitride film has barrier properties against hydrogen and oxygen, and is highly resistant to oxidation. ,preferable.

[0251] Although the figure shows a single layer structure, it may be a laminated structure of two or more layers. It is preferable to stack a titanium film and a tungsten film. It is also preferable to stack a titanium film and an aluminum film. In addition, a two-layer structure in which an aluminum film is laminated on a tungsten film, a copper-magnesium film, and Two-layer structure with copper film laminated on aluminum alloy film, two-layer structure with copper film laminated on titanium film Alternatively, a two-layer structure may be used in which a copper film is laminated on a tungsten film.

[0252] Also, a titanium film or titanium nitride film and an aluminum film overlaid on the titanium film or titanium nitride film are used. A titanium film or a copper film is laminated, and a titanium film or a titanium nitride film is further formed on the aluminum film or a copper film. Three-layer structure: a molybdenum film or molybdenum nitride film and a molybdenum film or molybdenum nitride film. An aluminum film or copper film is laminated on top of the molybdenum film, and then a molybdenum film or There are three-layer structures in which a molybdenum nitride film is formed. A transparent conductive material containing zinc oxide may also be used.

[0253] The conductor 260 having the function of a gate electrode is made of, for example, aluminum, chromium, or copper. , tantalum, titanium, molybdenum, tungsten, or any of the above metals. It can be formed using an alloy containing the above metals as a component, or an alloy combining the above metals. In particular, metal nitride films such as tantalum nitride films have barrier properties against hydrogen and oxygen. In addition, it is preferable because it has high oxidation resistance. Alternatively, a metal selected from a plurality of metals may be used. Semiconductors such as polycrystalline silicon and silicides such as nickel silicide may also be used. Although the figure shows a single layer structure, a laminated structure of two or more layers may also be used.

[0254] For example, a two-layer structure in which a titanium film is laminated on aluminum is preferable. Two-layer structure in which a titanium film is laminated on a titanium nitride film, and two-layer structure in which a tungsten film is laminated on a titanium nitride film. The structure is a two-layer structure in which a tungsten film is laminated on a tantalum nitride film or a tungsten nitride film. You may do so.

[0255] In addition, a titanium film is laminated on the titanium film, and an aluminum film is laminated on the titanium film. There are also three-layer structures that form aluminium, titanium, tantalum, tungsten, etc. , molybdenum, chromium, neodymium, and scandium. A combined alloy film or nitride film may also be used.

[0256] The conductor 260 may be made of indium tin oxide or indium oxide containing tungsten oxide. , indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Indium tin oxide containing titanium oxide, indium zinc oxide, silicon oxide added A light-transmitting conductive material such as indium tin oxide can also be used. A laminated structure of a light-transmitting conductive material and the above metal may also be used.

[0257] Subsequently, an insulator 280 and an insulator 282 are provided above the transistor 200 .

[0258] The insulator 280 is made of an oxide containing more oxygen than the oxygen required for the stoichiometric composition. That is, the insulator 280 preferably contains excess oxygen compared to the stoichiometric composition. It is preferable that a region containing excess oxygen (hereinafter also referred to as an excess oxygen region) is formed. When an oxide semiconductor is used for the transistor 200, an overcoat is formed in an interlayer film or the like near the transistor 200. By providing an insulator having an oxygen-excess region, oxygen vacancies in the transistor 200 can be reduced. This can improve reliability.

[0259] As an insulator having an excess oxygen region, specifically, an oxide film in which some oxygen is released by heating is used. It is preferable to use a material that releases oxygen when heated. , the amount of oxygen released in terms of oxygen atoms is 1.0 × 10 18 atoms / cm 3 Above, I like Or 3.0 x 10 20 atoms / cm 3 The oxide film is as described above. The surface temperature of the membrane during analysis is 100°C or higher and 700°C or lower, or 100°C or higher. A range of 500°C or less is preferred.

[0260] For example, a material containing silicon oxide or silicon oxynitride is used as such a material. It is preferable to use a metal oxide. Silicon oxynitride refers to a material that contains more oxygen than nitrogen in its composition, Silicon oxide refers to a material whose composition contains more nitrogen than oxygen.

[0261] The insulator 280 covering the transistor 200 is a planarizing layer that covers the uneven surface underneath. It may also function as a membrane.

[0262] The insulator 282 may be an insulator that is resistant to oxygen and water, such as aluminum oxide and hafnium oxide. It is preferable to use an insulating film that has barrier properties against elements. When the oxide 230 is removed, the layer prevents oxygen from being released from the oxide 230 and impurities such as hydrogen from entering from the outside. It functions as:

[0263] With the above structure, a transistor including an oxide semiconductor with large on-state current can be provided. Alternatively, a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, by using a transistor having the above structure in a semiconductor device, Fluctuations in the electrical characteristics of the semiconductor device can be suppressed, and reliability can be improved. This makes it possible to provide a semiconductor device with reduced power consumption.

[0264] <Transistor structure 2> FIG. 13 shows an example of a structure applicable to the transistor 200. 13(A) shows the top surface of the transistor 200. For clarity of the drawing, some of the films are not shown in FIG. 13B corresponds to the dashed line X1-X2 shown in FIG. 13(C) is a cross-sectional view taken along line Y1-Y2.

[0265] In the transistor 200 shown in FIG. 13, the transistor 200 shown in FIG. The same reference numerals are used to designate structures having the same functions as the structures they constitute.

[0266] In the structure shown in Fig. 13, the conductor 260 is provided in a two-layer structure. For example, the conductor 260a As the material, oxides such as In-Ga-Zn oxide can be used. Oxide semiconductors, such as Zn-oxide, can be easily transported by supplying nitrogen or hydrogen. In other words, the oxide conductor (OC) Therefore, by providing a metal nitride as the conductor 260b, it is possible to Since the semiconductor has a high carrier density, the conductor 260a functions as a gate electrode.

[0267] The conductor 260a is made of an oxide semiconductor such as In-Ga-Zn oxide. In addition, the conductor 260a may be made of indium tin oxide (InTinO). Oxide (ITO), indium oxide containing tungsten oxide, tungsten oxide Indium zinc oxide containing titanium oxide, indium oxide containing titanium oxide Indium tin oxide, indium zinc oxide, indium tin oxide with silicon (In-S A conductive material with light-transmitting properties, such as n-Si oxide (also called ITSO), can also be used. Cut.

[0268] By using a metal nitride as the conductor 260b, the constituent elements (especially nitrogen) in the metal nitride can be ) diffuses into the conductor 260a, lowering its resistance, and damage ( For example, the resistance can be reduced by sputtering damage. 260b may have a laminated structure of two or more layers. For example, a low-resistance metal may be formed on a metal nitride. By stacking films, it is possible to provide a transistor with a low driving voltage.

[0269] The conductor 260a is formed by sputtering, and oxygen gas is used during the formation. It is preferable to form the conductor 260 in an atmosphere containing oxygen gas during the formation. By forming a, an excess oxygen region can be formed in the insulator 250. The method for forming the conductor 260a is not limited to sputtering, and other methods, e.g. For example, the ALD method may be used.

[0270] 13, an insulator 270 is provided to cover the conductor 260. When the insulator 280 is made of an oxide material from which oxygen is released, the insulator 270 has a barrier against oxygen. This structure compensates for oxygen deficiency in the conductor 260a. This prevents the carrier density from decreasing, and the conductor 260b can be easily oxidized by the diffused oxygen. This can further prevent oxidation.

[0271] For example, the insulator 270 can be a metal oxide such as aluminum oxide. The insulator 270 may be provided with a thickness sufficient to prevent oxidation of the conductor 260. .

[0272] As shown in the figure, the insulator 220 and the insulator 222 are not provided, and the insulating film 220 has a barrier property. The conductor 205c may be formed using a conductor. Even if there is an excess oxygen region, the conductor 205b reacts with the oxygen in the excess oxygen region and is oxidized. It is possible to suppress the generation of substances.

[0273] In addition, an insulator 243a and an insulator 244b are formed on the conductor 240a and the conductor 240b. The insulators 243a and 243b may have a barrier property against oxygen. With this configuration, the conductor 240a and the conductor 240b are made of a material having an acid. When the oxide 230c is formed, oxidation can be suppressed. The oxygen in the excess oxygen region of 0 reacts with the conductor 240a and the conductor 240b, forming an acid. This can prevent the deterioration of the

[0274] The insulators 243a and 243b may be made of, for example, a metal oxide. In particular, aluminum oxide, hafnium oxide, gallium oxide, etc., are highly resistant to oxygen and hydrogen. It is preferable to use an insulating film with barrier properties. Also, silicon nitride formed by the CVD method is may also be used.

[0275] Therefore, with this configuration, the conductor 240a, the conductor 240b, the conductor 205, and For example, the conductors 205b and 260 can be made of a wide range of materials. The conductor 260b is made of a material such as aluminum that has low oxidation resistance but high conductivity. In addition, for example, a conductive material that is easy to form a film or process can be used. .

[0276] In addition, oxidation of the conductor 205 and the conductor 260 is suppressed, and the insulator 224 and the insulator The desorbed oxygen can be efficiently supplied from 280 to the oxide 230. By using a highly conductive conductor for the conductor 205 and the conductor 260, power consumption is reduced. Therefore, a low-temperature transistor 200 can be provided.

[0277] <Transistor structure 3> FIG. 14 shows an example of a structure applicable to the transistor 200. 14(A) shows the top surface of the transistor 200. For clarity of the drawing, some of the films are not shown in FIG. 14(B) corresponds to the dashed line X1-X2 shown in FIG. 14(C) is a cross-sectional view taken along line Y1-Y2.

[0278] In the transistor 200 shown in FIG. 14, the transistor 200 shown in FIG. The same reference numerals are used to designate structures having the same functions as the structures they constitute.

[0279] In the structure shown in Figure 14, the conductor 260 is provided in a two-layer structure. For example, the conductor 260a may be formed by a thermal CVD method, an MOCVD method, or the like. It is preferably formed by the ALD method. By forming it by the D method or the like, damage to the insulator 250 during film formation can be reduced. In addition, by forming the conductive material 260a by the ALD method or the like, a conductive material 260a with high coating properties can be formed. Therefore, a highly reliable transistor 200 can be provided.

[0280] Subsequently, the conductor 260b is formed by sputtering. Furthermore, by providing the conductor 260a, damage to the conductor 260b during film formation is prevented by the insulator 25. In addition, compared to the ALD method, the sputtering This method has a high film formation rate, resulting in a high yield and improved productivity.

[0281] 14, an insulator 270 is provided to cover the conductor 260. When the insulator 280 is made of an oxide material from which oxygen is released, the insulator 270 has a barrier against oxygen. This structure compensates for oxygen deficiency in the conductor 260a. This prevents the carrier density from decreasing, and the conductor 260b can be easily oxidized by the diffused oxygen. This can further prevent oxidation.

[0282] For example, the insulator 270 can be a metal oxide such as aluminum oxide. The insulator 270 may be provided with a thickness sufficient to prevent oxidation of the conductor 260. .

[0283] <Transistor structure 4> FIG. 15 shows an example of a structure applicable to the transistor 200. 15(A) shows the top surface of the transistor 200. For clarity of the drawing, some of the films are not shown in FIG. 15(B) corresponds to the dashed line X1-X2 shown in FIG. 15(C) is a cross-sectional view taken along line Y1-Y2.

[0284] In the transistor 200 shown in FIG. 15, the transistor 200 shown in FIG. The same reference numerals are used to designate structures having the same functions as the structures they constitute.

[0285] In the structure shown in FIG. 15, the conductor 260 functioning as the gate electrode is made up of conductors 260a, 260b, and 260c. The oxide 230c has a side of the oxide 230b. It is sufficient that the surface is covered, and the cut may be made on the insulator 224 .

[0286] In the structure shown in Figure 15, the conductor 260 is provided in a three-layer structure. Alternatively, a laminated structure of four or more layers may be used. In the case of a two-layer structure, the same material is laminated. For example, the conductor 260a may be formed by a thermal CVD method, an MOCVD method, or an AL method. It is preferable to form the film by the ALD method. By forming the insulating layer 250, damage to the insulating layer 250 during film formation can be reduced. In addition, by forming the conductive material 260a by the ALD method or the like, it is possible to form a film of the conductive material 260a with high coverage. Therefore, a highly reliable transistor 200 can be provided.

[0287] Subsequently, the conductor 260b is formed by sputtering. Furthermore, by providing the conductor 260a, damage to the conductor 260b during film formation is prevented by the insulator 25. In addition, compared to the ALD method, the sputtering This method has a high film formation rate, resulting in a high yield and improved productivity.

[0288] The conductor 260b is made of a highly conductive material such as tantalum, tungsten, copper, or aluminum. Furthermore, the conductor 260c formed on the conductor 260b is made of a nitride material. It is preferable to form the insulating film using a conductor having high oxidation resistance, such as tungsten.

[0289] For example, when an oxide material from which oxygen is released is used for the insulator 280, the insulator 280 has an excess oxygen region. The conductor 260c having a large contact area with the insulator 280 is made of a conductor having high oxidation resistance. Therefore, it is possible to suppress the absorption of oxygen desorbed from the excess oxygen region into the conductor 260. In addition, oxidation of the conductor 260 can be suppressed, and the desorbed oxygen can be efficiently removed from the insulator 280. The conductor 260b can be supplied to the oxide 230. By using the above, it is possible to provide a transistor 200 with low power consumption.

[0290] As shown in FIG. 15C, the oxidized layer is formed in the channel width direction of the transistor 200. The object 230b is covered with the conductor 260. In addition, the insulator 224 has a protrusion. Therefore, the side surface of the oxide 230b can also be covered with the conductor 260. For example, the insulator 224 By adjusting the shape of the convex portion, in the region where the insulator 224 and the oxide 230c contact, It is preferable that the bottom surface of the conductor 260 is closer to the substrate than the bottom surface of the oxide 230b. That is, the transistor 200 is configured such that the electric field of the conductor 260 causes the oxide 230b In this way, the electric field of the conductor can electrically surround the oxide. The transistor structure electrically surrounding the oxide 230b is called the surrounded cha. This is called an s-channel structure. s-channel structure transistor 2 00 can also form a channel throughout the oxide 230b (bulk). The tunnel structure allows for a larger drain current for the transistor, and even larger Obtaining the on-current (the current that flows between the source and drain when the transistor is on) In addition, the electric field of the conductor 260 can form a channel in the oxide 230b. Therefore, the entire region of the s-channel structure can be depleted. The off-state current of the transistor can be further reduced by reducing the channel width. By reducing the s-channel structure, the on-current is increased and the off-current is reduced. etc. can be increased.

[0291] <Transistor structure 5> FIG. 16 shows an example of a structure applicable to the transistor 200. 16(A) shows the top surface of the transistor 200. For clarity of the drawing, some of the films are not shown in FIG. 16(B) corresponds to the dashed line X1-X2 shown in FIG. 16(C) is a cross-sectional view taken along line Y1-Y2.

[0292] In the transistor 200 shown in FIG. 16, the transistor 200 shown in FIG. The same reference numerals are used to designate structures having the same functions as the structures they constitute.

[0293] The structure shown in FIG. 16 has a stacked structure of conductors that function as a source or drain. The conductors 240a and 240b are made of a material that has high adhesion to the oxide 230b. It is preferable that the conductors 241a and 241b are made of a material with high conductivity. , the conductor 240a, and the conductor 240b are preferably formed using an ALD method. Forming the film by the ALD method or the like can improve the coverage.

[0294] For example, when a metal oxide containing indium is used for the oxide 230b, the conductor 240 Titanium nitride or the like may be used for the conductor 241a and the conductor 240b. and the conductor 241b is made of a conductive material such as tantalum, tungsten, copper, or aluminum. By using high-quality materials, a transistor 200 with high reliability and low power consumption can be provided. It is possible.

[0295] As shown in FIG. 16C, the oxidized layer is formed in the channel width direction of the transistor 200. The object 230b is covered with the conductor 260. In addition, the insulator 222 has a protrusion. Therefore, the side surfaces of the oxide 230b can also be covered with the conductor 260.

[0296] Here, when a high-k material such as hafnium oxide is used for the insulator 222, the insulator Since the relative dielectric constant of 222 is large, the equivalent oxide thickness (EOT) Therefore, the oxide thickness can be reduced. Without weakening the influence of the electric field from the conductor 205, the physical thickness of the insulator 222 This allows the distance between the conductor 205 and the oxide 230 to be increased. The distance between the conductor 205 and the oxide 230 can be adjusted by adjusting the thickness of the film 222. Cut.

[0297] For example, by adjusting the shape of the protrusion of the insulator 222, the insulator 222 and the oxide 230c can be In the contact area, the bottom surface of the conductor 260 is closer to the substrate than the bottom surface of the oxide 230b. In other words, the transistor 200 is preferably configured such that the electric field of the conductor 260 Thus, the oxide 230b is electrically surrounded. The structure of the transistor that electrically surrounds the oxide 230b is called the surr This is called a s-channel (rounded channel) structure. The transistor 200 has a structure in which a channel is formed in the entire (bulk) oxide 230b. The s-channel structure allows the drain current of the transistor to be increased. This allows for a larger on-state current (the voltage between the source and drain when the transistor is on). In addition, the electric field of the conductor 260 can be used to generate a current flowing through the oxide 230. The entire channel formation region formed in s-b can be depleted. In the case of a channel structure, the off-state current of the transistor can be further reduced. By reducing the channel width, the on-current is increased due to the s-channel structure. , the effect of reducing the off-state current can be improved.

[0298] <Transistor structure 6> FIG. 17 shows an example of a structure applicable to the transistor 200. 17(A) shows the top surface of the transistor 200. For clarity of the drawing, some of the films are not shown in FIG. 17(B) corresponds to the dashed line X1-X2 shown in FIG. 17(C) is a cross-sectional view taken along line Y1-Y2.

[0299] In the transistor 200 shown in FIG. 17, the transistor 200 shown in FIG. The same reference numerals are used to designate structures having the same functions as the structures they constitute.

[0300] The transistor 200 shown in FIG. 17 includes an oxide 230 in an opening formed in an insulator 280. c, an insulator 250 and a conductor 260 are formed. One end of 240b and the end of the opening formed in the insulator 280 are aligned. The three ends of the conductor 240a and the conductor 240b are covered with the oxide 230a and the oxide The conductors 240a and 240b are aligned with a portion of the end of the conductor 240a. The openings in the oxide 230 or the insulator 280 can be shaped at the same time. This reduces the number of masks and processes, and also improves yield and productivity. can be done.

[0301] Also, the conductor 240a, the conductor 240b, and the oxide 230b have excess oxygen regions. The insulator 280 is in contact with the channel via the oxide 230d. The oxide 230d is interposed between the oxide 230b having the region where the hole is formed. As a result, impurities such as hydrogen, water, and halogens diffuse from the insulator 280 to the oxide 230b. This can prevent the particles from scattering.

[0302] Furthermore, the transistor 200 shown in FIG. 17 includes a conductor 240a and a conductor 240b, Since the conductor 260 and the conductor 240 have a structure in which they hardly overlap, The parasitic capacitance between 240a and 240b can be reduced. It is possible to provide a transistor 200 with a high

[0303] <Transistor structure 8> FIG. 18 shows an example of a structure applicable to the transistor 200. 18(A) shows the top surface of the transistor 200. For clarity of the drawing, some of the films are not shown in FIG. 18(B) corresponds to the dashed line X1-X2 shown in FIG. 18(C) is a cross-sectional view taken along line Y1-Y2.

[0304] In the transistor 200 shown in FIG. 18, the transistor 200 shown in FIG. The same reference numerals are used to designate structures having the same functions as the structures they constitute.

[0305] The transistor 200 shown in FIG. 18 does not have an oxide 230d. When a conductor having high oxidation resistance is used for the conductor 240a and the conductor 240b, the oxide 23 0d is not necessarily provided, so the number of masks and processes can be reduced. In addition, yield and productivity can be improved.

[0306] The insulator 224 is provided only in the region overlapping with the oxide 230a and the oxide 230b. In this case, the insulator 222 may be used as an etching stopper, and the oxide 230a, The oxide 230b and the insulator 224 can be processed. It can improve sexuality.

[0307] Furthermore, the transistor 200 shown in FIG. 18 includes a conductor 240a and a conductor 240b. Since the conductor 260 and the conductor 240 have a structure in which they hardly overlap, The parasitic capacitance between 240a and 240b can be reduced. Therefore, a high transistor 200 can be provided.

[0308] <Transistor manufacturing method> An example of a method for manufacturing the transistor shown in FIG. 12 will be described below with reference to FIGS. 19 to 22. Reveal.

[0309] First, a substrate is prepared (not shown). There are no major limitations on the substrate, but at least For example, barium borate is preferably used. Glass substrates such as borosilicate glass and aluminoborosilicate glass, ceramic substrates, quartz substrates, A sapphire substrate or the like can be used. Also, a single crystal made of silicon or silicon carbide can be used. crystalline semiconductor substrate, polycrystalline semiconductor substrate, silicon germanium, gallium arsenide, indium arsenide Compound semiconductor substrates made of silicon, indium gallium arsenide, and SOI (Silicon On Insulator) Insulator) substrate, GOI (Germanium on Insulator) A semiconductor device provided on such a substrate is called a substrate. It may also be used as a plate.

[0310] A semiconductor device may be manufactured using a flexible substrate as the substrate. To fabricate a semiconductor device, a transistor may be fabricated directly on a flexible substrate, or other fabrication may be performed. A transistor may be formed on a flexible substrate and then peeled off and transferred to a flexible substrate. In order to separate and transfer the transistor from the substrate to a flexible substrate, It is advisable to provide a release layer between the substrate and the heater.

[0311] Next, the insulators 214 and 216 are formed. Then, the insulator 216 is subjected to lithography. A resist mask 290 is formed by a method or the like, and unnecessary portions of the insulators 214 and 216 are removed. Then, the resist mask 290 is removed. This allows the formation of an opening.

[0312] Here, a method for processing a film to be processed will be described. When processing a film to be processed finely, various Various microfabrication techniques can be used. For example, a resist formed by lithography or the like can be used. A method of slimming the mask may be used. A dummy pattern is formed, and a sidewall is formed on the dummy pattern. The sidewall is removed, and the film to be processed is etched using the remaining sidewall as a resist mask. In addition, in order to achieve a high aspect ratio when etching the film to be processed, For this reason, it is preferable to use anisotropic dry etching. A hard mask made of the following may also be used.

[0313] The light used to form the resist mask is, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), H-line (wavelength 405 nm), or a mixture of these can be used. In addition, ultraviolet light, KrF laser light, ArF laser light, etc. can also be used. The exposure may also be performed by immersion exposure. (EUV: Extreme Ultraviolet) or X-rays may also be used. Instead of light used for exposure, an electron beam can be used. The use of a electron beam is preferable because it allows for extremely fine processing. When exposure is performed by scanning any beam, no photomask is required.

[0314] In addition, before forming the resist film that will become the resist mask, the adhesion between the film to be processed and the resist film is An organic resin film having a function of improving the spin property may be formed. The surface is formed so as to cover the steps below it and make the surface flat by a coating method or the like. This makes it possible to reduce variations in the thickness of the resist mask provided above the organic resin film. In particular, when fine processing is performed, the organic resin film should be resistant to the light used for exposure. It is preferable to use a material that functions as an anti-reflection film. As the resin film, for example, BARC (Bottom Anti-Reflection The organic resin film is removed at the same time as the resist mask is removed. Alternatively, it may be removed after removing the resist mask.

[0315] Subsequently, the conductor 205A and the conductor 205B are formed on the insulator 214 and the insulator 216. The conductor 205A and the conductor 205B are formed by a method such as sputtering, vapor deposition, Deposition by CVD (including thermal CVD, MOCVD, PECVD, etc.) In addition, to reduce damage caused by plasma, thermal CVD, MOCVD or The ALD method is preferred (FIG. 19(B)).

[0316] Next, unnecessary portions of the conductor 205A and the conductor 205B are removed. Chip back processing or chemical mechanical polishing (CMP) The conductor is polished until the insulator 216 is exposed by a polishing process or the like. 205A and a part of the conductor 205B are removed to form the conductor 205 (FIG. 19(C)). In this case, the insulator 216 can be used as a stopper layer. 16 may become thinner.

[0317] Here, CMP processing is a process of flattening the surface of a workpiece by a combined chemical and mechanical action. More specifically, a polishing cloth is attached to the polishing stage, and the workpiece and the polishing cloth are The polishing stage and the workpiece are rotated or By shaking, the chemical reaction between the slurry and the surface of the workpiece and the mechanical interaction between the polishing cloth and the workpiece are promoted. This is a method of polishing the surface of a workpiece by mechanical polishing.

[0318] The CMP process may be performed once or multiple times. When performing MP processing, first polishing is performed at a high polishing rate, followed by finishing at a low polishing rate. In this way, polishing with different polishing rates may be combined.

[0319] Next, the insulators 220, 222, and 224 are formed (FIG. 19(D)). It should be noted that the insulators 220 and 222 are not necessarily provided. When 224 has an excess oxygen region, a conductor having barrier properties is formed on the conductor 205. By forming a conductor having a barrier property, the conductor 205 can be prevented from being exposed to the excess oxygen region. It is possible to suppress the reaction with oxygen and the generation of oxides.

[0320] The insulators 220, 222, and 224 may be, for example, silicon oxide, silicon dioxide, or the like. Silicon nitride, silicon oxynitride, silicon nitride, aluminum oxide, aluminum oxynitride Aluminum, aluminum nitride oxide, aluminum nitride, etc. may be used. For 2, it is preferable to use a high-k material such as hafnium oxide.

[0321] The insulators 220, 222, and 224 may be formed by, for example, sputtering, chemical deposition, or the like. Chemical Vapor Deposition (CVD) method (thermal CV D method, Metal Organic Chemical CVD (MOCVD) Vapor Deposition, Plasma Enhanced CVD (PECVD) Enhanced Chemical Vapor Deposition (ECCVD) method, etc. including MBE (Molecular Beam Epitaxy) ) method, atomic layer deposition (ALD) method or Pulsed laser deposition (PLD) method In particular, the insulator can be formed by a CVD method, preferably an ALD method, etc. It is preferable to form the film by plasma, since it is possible to improve the coating property. To reduce damage caused by the deposition, thermal CVD, MOCVD, or ALD is preferred. , TEOS (Tetra-Ethyl-Ortho-Silicate) or silane Silicon oxide with good step coverage formed by reacting the above with oxygen or nitrous oxide. A membrane may also be used.

[0322] It is preferable that the insulators 220, 222, and 224 be successively formed. By successively forming the films, the interface between the insulator 220 and the insulator 222 and the insulator 22 2 and the insulator 224, no impurities are attached to the interface between the insulator 224, forming a highly reliable insulator. It is possible.

[0323] Subsequently, oxide 230A which becomes oxide 230a and oxide 230B which becomes oxide 230b are formed. The oxide films are preferably formed successively without being exposed to the air. It's nice.

[0324] Then, a conductive film 240 which will become a conductor 240a and a conductor 240b is formed on the oxide 230A. The conductive film 240A has a barrier property against hydrogen or oxygen, and It is preferable to use a material with high oxidation resistance. Although the figure shows a single layer, it is possible to use two or more layers. Subsequently, a resist mask 292 is formed in the same manner as above. (Figure 19(E)).

[0325] Using the resist mask 292, unnecessary portions of the conductive film 240A are removed by etching. Then, an island-shaped conductive layer 240B is formed (FIG. 20(A)). Then, the conductive layer 240B is masked. The oxide 230A and the unnecessary portions of the oxide 230B are removed by etching. .

[0326] At this time, the insulator 224 may also be processed into an island shape. By using the insulator 222 as an etching stopper film, the insulator 220 and the insulator 222 Even in a structure in which the total thickness of the insulator 224 is small, the over-layer insulation film 224 reaches the underlying wiring layer. In addition, the insulators 220, 222, and Furthermore, by reducing the total thickness of the insulator 224, the voltage from the conductor 205 is efficiently applied. Therefore, a transistor with low power consumption can be provided.

[0327] Thereafter, the resist mask is removed, and the island-shaped oxide 230a and the island-shaped oxide 23 0b and an island-shaped conductive layer 240B (FIG. 20(B)). .

[0328] Subsequently, it is preferable to carry out a heat treatment (FIG. 20(C), the arrow in the figure indicates the heat treatment). The heat treatment is carried out at a temperature of 250°C to 400°C, preferably 320°C to 380°C. It should be carried out in an inert gas atmosphere, an atmosphere containing 10 ppm or more of oxidizing gas, or under reduced pressure. The heat treatment atmosphere is an inert gas atmosphere, and the desorbed oxygen is removed after the heat treatment. To compensate for the loss of oxygen, the heat treatment may be carried out in an atmosphere containing 10 ppm or more of oxidizing gas. , hydrogen, which is an impurity in oxide 230a and oxide 230b, can be removed. Also, the oxide 230a and the oxide 230b are removed from the insulator formed below the oxide 230a. Oxygen is supplied to 30b, and oxygen vacancies in the oxide can be reduced.

[0329] Next, a resist mask 294 is formed on the island-shaped conductive layer 240B by the same method as above. (FIG. 20(D)). Next, unnecessary portions of the conductive layer 240B were removed by etching. Thereafter, the resist mask 294 is removed, and the conductor 240a and the conductor 240 At this time, a part of the insulator 222 or the insulator 224 is etched. By thinning the film by thinning, an s-channel structure may be formed.

[0330] Here, a heat treatment may be performed. The conditions for the heat treatment are the same as those explained in FIG. 20(C). The heat treatment may be performed under the same conditions as the heat treatment. The hydrogen impurities in the oxide 230a can be removed. Oxygen is supplied to the oxide 230a and the oxide 230b from the insulating material. Furthermore, when heat treatment is performed using an oxidizing gas, the channel The oxidizing gas directly contacts the area where the channel is formed, and the channel is efficiently formed. This can reduce oxygen deficiency in the region where the oxide is present.

[0331] Next, an oxide film 230c is formed. Here, a heat treatment may be performed (see FIG. 21). (B), the arrows in the figure indicate the heat treatment.) The heat treatment conditions were the same as those described in Figure 21(C). The heat treatment may be performed under the same conditions as the heat treatment. In addition, hydrogen, which is an impurity of the oxide 230a, can be removed. Oxygen is supplied to the oxide 230a and the oxide 230b from the insulating material. Furthermore, when heat treatment is performed using an oxidizing gas, the channel The oxidizing gas directly contacts the region where the channel is formed, and the channel is efficiently formed. The oxygen vacancies in the region can be reduced.

[0332] The insulator 250 and the conductive film 260A that will become the conductor 260 are formed in this order. 260A has barrier properties against hydrogen and oxygen, and is made of highly oxidation-resistant materials. Although the figure shows a single layer, it may have a laminated structure of two or more layers. stomach.

[0333] For example, the two-layer structure may be formed by laminating the same material. The first conductive film may be formed by thermal CVD. It is formed by MOCVD or ALD. In particular, it is preferable to form it by ALD. By forming the insulating layer 250 by the ALD method or the like, damage to the insulating layer 250 during film formation can be reduced. In addition, by forming the conductive film 26 by the ALD method or the like, the conductive film 26 can be formed with high coverage. Therefore, the transistor 200 can be formed with high reliability. can be done.

[0334] Subsequently, the second conductive film is formed by sputtering. Furthermore, by having the first conductive film, damage during the formation of the second conductive film is prevented from being transmitted to the insulator 250. Furthermore, compared to the ALD method, the sputtering method The high film formation rate leads to high yield and improved productivity. When forming 260A, it is preferable to use a film forming gas that does not contain chlorine.

[0335] Next, a resist mask 296 is formed on the conductive film 260A by the same method as above. (FIG. 21(C)). Next, unnecessary portions of the conductive film 260A are removed by etching. After the conductor 260 is formed, the resist mask 296 is removed (FIG. 22(A)).

[0336] Next, an insulator 280 is formed on the conductor 260. The insulator 280 is a silicon oxide film. The insulator containing oxygen is an insulator such as a silicon oxynitride film. As a method for this, the film formation conditions in the CVD method or sputtering method are appropriately set to incorporate an acid into the film. It is possible to form a silicon oxide film or a silicon oxynitride film containing a large amount of silicon. After forming a silicon oxide film or a silicon oxynitride film, ion implantation or ion doping is performed. Oxygen may be added by plasma treatment or the like.

[0337] In particular, oxygen plasma treatment is preferable (FIG. 22(B), the arrow in the figure indicates the plasma treatment (This represents the oxygen plasma treatment.) A typical oxygen plasma treatment is a process in which oxygen gas is glow discharged. The purpose of this is to treat the surface of an oxide semiconductor with radicals, but the gas that generates the plasma is The gas may be not only oxygen but also a mixture of oxygen gas and rare gas. At a temperature of 400°C or less, preferably 300°C to 400°C, in an atmosphere containing an oxidizing gas Alternatively, the heating may be carried out under reduced pressure.

[0338] The oxygen plasma treatment dehydrates or dehydrogenates the insulator 280 and the oxide 230. At the same time, excess oxygen is introduced into the insulator 280 to form an excess oxygen region. In addition, oxygen vacancies are generated in the dehydrated or dehydrogenated oxide 230. On the other hand, the excess oxygen in the insulator 280 causes oxygen deficiency in the oxide 230. Therefore, the oxygen plasma treatment causes the insulator 280 to have an excess oxygen region. At the same time, impurities such as hydrogen and water can be removed. 30 can remove impurities such as hydrogen and water while filling oxygen vacancies. Therefore, the electrical characteristics of the transistor 200 are improved and the variations in the electrical characteristics are reduced. It is possible.

[0339] Next, an insulator 282 is formed on the insulator 280 (FIG. 22(C)). It is preferable to form the film by a sputtering device. , it is easy to form an excess oxygen region in the insulator 280 underlying the insulator 282. .

[0340] When forming a film by sputtering, there are ions and sputtered materials between the target and the substrate. For example, the target is connected to a power source and is given a potential E0. In addition, the substrate is given a potential E1 such as a ground potential. It may be floating. In addition, there is an area between the target and the substrate that has a potential E2. The magnitude relationship of the potentials is E2>E1>E0.

[0341] Ions in the plasma are accelerated by the potential difference E2-E0 and collide with the target. The sputtered particles are ejected from the target. The film is formed by the deposition of ions on the surface of the film. The ions recoil from the ion beam and travel through the film formed as recoil ions. In addition, ions in the plasma may be trapped in the insulator 280. The ions are accelerated by E1 and bombard the surface of the film. At this time, some of the ions are The ions are absorbed into the insulator 280, and the ions A trapped region is formed in the insulator 280. That is, if the ions are oxygen-containing ions, In this case, an excess oxygen region is formed in the insulator 280.

[0342] By introducing excess oxygen into the insulator 280, an excess oxygen region can be formed. The excess oxygen in the insulator 280 is supplied to the oxide 230, and the oxygen deficiency in the oxide 230 is compensated for. Here, the conductor 260, the conductor 240a, and the insulator 280 are in contact with each other. When a highly oxidation-resistant conductor is used for the conductor 240b, excess oxygen in the insulator 280 The conductor 260, the conductor 240a, and the conductor 240b are not absorbed and can be efficiently Therefore, the electrical characteristics of the transistor 200 can be improved. This can improve the electrical characteristics and reduce variations in electrical properties.

[0343] Through the above steps, the transistor 200 of one embodiment of the present invention can be manufactured.

[0344] The configurations, methods, etc. shown in this embodiment may be used in conjunction with configurations shown in other embodiments and examples. It can be used in appropriate combination with other compositions, methods, etc.

[0345] (Fourth embodiment) In this embodiment mode, one mode of a semiconductor device will be described with reference to FIGS.

[0346] [Configuration example] 23 to 30 show examples of a semiconductor device (memory device) according to one embodiment of the present invention. 23 to 26 in the form of a circuit diagram. 27 shows an edge of a region where the semiconductor device shown in FIG. 26 is formed.

[0347] <Circuit configuration of semiconductor device> The semiconductor device illustrated in FIG. 30A and FIGS. 23 to 28 includes a transistor 300 and a transistor It includes a transistor 200 and a capacitance element 100 .

[0348] The transistor 200 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. Since the off-state current of the transistor 200 is small, it is used as a semiconductor device (memory device). By using it in a device, it is possible to retain the memory contents for a long period of time. No refresh operation is required, or the frequency of refresh operations is extremely low. This allows the power consumption of the semiconductor device (memory device) to be sufficiently reduced.

[0349] In FIG. 30A, a wiring 3001 is electrically connected to the source of a transistor 300. The wiring 3002 is electrically connected to the drain of the transistor 300. 3003 is electrically connected to one of the source and drain of the transistor 200, and is a wiring 3004 is electrically connected to the gate of the transistor 200. The gate of the transistor 300 and the other of the source and drain of the transistor 200 are connected to a capacitance element. The wiring 3005 is electrically connected to one of the electrodes of the capacitor 100 . and is electrically connected.

[0350] The semiconductor device shown in FIG. 30A is capable of holding the potential of the gate of the transistor 300. By having these characteristics, it is possible to write, retain, and read information as shown below. .

[0351] The writing and retention of information will be explained. First, the potential of the wiring 3004 is changed to the potential of the transistor. This sets the potential at which the transistor 200 is in a conducting state, thereby making the transistor 200 in a conducting state. The potential of the wiring 3003 is applied to the gate of the transistor 300 and the electrode of the capacitor 100. That is, the gate of the transistor 300 is electrically connected to a node FG. A predetermined charge is applied to the Either the low-level charge or the high-level charge is given. After that, the potential of the wiring 3004 is set to a potential at which the transistor 200 is turned off. By setting the potential at the node FG such that the transistor 200 is in a non-conductive state, a charge is held at the node FG. will be held (retained).

[0352] When the off-state current of the transistor 200 is small, the charge of the node FG is held for a long period of time. will be done.

[0353] Next, the reading of information will be described. When a predetermined potential (constant potential) is applied to the wiring 3001, In this state, when an appropriate potential (read potential) is applied to the wiring 3005, the wiring 3002 The potential is determined by the amount of charge held in the FG. When a high level charge is applied to the gate of the transistor 300, Apparent threshold voltage V th_H is a low level charge on the gate of transistor 300. The apparent threshold voltage V th_L This is because the Here, the apparent threshold voltage is the voltage required to make the transistor 300 "conductive." Therefore, the potential of the wiring 3005 is V th_ H and V th_LBy setting the potential V0 between the two nodes, the charge applied to node FG can be determined. For example, if a high level charge is applied to node FG during a write operation, In this case, the potential of the wiring 3005 is V0 (>V th_H ), then the transistor 300 is On the other hand, if a low-level charge is applied to node FG, The potential of the wire 3005 is V0( <V th_L ), transistor 300 remains in a "non-conducting state." Therefore, by determining the potential of the wiring 3002, the node FG is kept in the "state". The information stored in the memory can be read.

[0354] In addition, by arranging the semiconductor device shown in FIG. 30A in a matrix, a memory device (memory A re-cell array can be configured.

[0355] When memory cells are arranged in an array, the information of the desired memory cell is read. For example, if the transistor 300 is a p-channel type, The memory cells are NOR type. Therefore, in memory cells from which information is not read, , so that transistor 300 is in a "non-conducting state" regardless of the charge applied to node FG. potential, that is, V th_H By applying a lower potential to the wiring 3005, the desired memory cell Alternatively, the transistor 300 can be an n-channel type. In this case, the memory cell has a NAND type configuration. In this case, the transistor 300 is in a "conducting state" regardless of the charge applied to the node FG. That is, V th_L By applying a higher potential to the wiring 3005, a desired Only the information in the memory cells can be read.

[0356] <Circuit configuration of semiconductor device 2> The semiconductor device shown in FIG. 30B differs from the semiconductor device shown in FIG. 30A in that it does not include the transistor 300. In this case, the semiconductor device operates in the same manner as the semiconductor device shown in FIG. This allows for writing and holding of information.

[0357] The reading of data from the semiconductor device shown in FIG. When the capacitor 200 is brought into a conductive state, the wiring 3003 in a floating state and the capacitor element 100 are brought into a conductive state. , the charge is redistributed between the wiring 3003 and the capacitor 100. The amount of change in the potential of the wiring 3003 is determined by the potential of one of the electrodes of the capacitor 100 ( or the charge stored in the capacitor element 100).

[0358] For example, the potential of one of the electrodes of the capacitor 100 is V, the capacitance of the capacitor 100 is C, and the wiring 30 The capacitance component of the wiring 3003 is CB, and the potential of the wiring 3003 before the charge is redistributed is VB0. Then, the potential of the wiring 3003 after the charge is redistributed is (CB×VB0+CV) / (CB Therefore, the state of the memory cell is such that one of the electrodes of the capacitor element 100 is in a negative voltage. If the potential takes two states, V1 and V0 (V1>V0), when the potential V1 is maintained, In this case, the potential of the wiring 3003 (=(CB×VB0+CV1) / (CB+C)) is The potential of the wiring 3003 when it is held (=(CB×VB0+CV0) / (CB+C)) It is clear that it will be higher than

[0359] Then, by comparing the potential of the wiring 3003 with a predetermined potential, information can be read out. do.

[0360] In this configuration, for example, silicon is applied to a drive circuit for driving a memory cell. The transistor 200 is a transistor using an oxide semiconductor. The transistors may be stacked on the drive circuit.

[0361] The semiconductor device described above uses a transistor including an oxide semiconductor and having low off-state current. By doing so, it is possible to retain the memory contents for a long period of time. This eliminates the need for refresh operations or makes it possible to reduce the frequency of refresh operations significantly. Therefore, a semiconductor device with low power consumption can be realized. Even if the potential is fixed, it is possible to store the data for a long period of time. It is possible to maintain the volume.

[0362] Furthermore, since the semiconductor device does not require a high voltage to write information, deterioration of the elements does not occur. For example, unlike conventional nonvolatile memory, injection of electrons into the floating gate Since electrons are not introduced or extracted from the floating gate, there is no risk of insulator degradation. That is, the semiconductor device according to one embodiment of the present invention does not have the same problem as the conventional nonvolatile memory. Unlike the conventional semiconductor memory device, there is no limit to the number of times it can be rewritten, and it is a semiconductor device with dramatically improved reliability. Furthermore, information is written depending on whether the transistor is conductive or non-conductive. , high-speed operation becomes possible.

[0363] <Semiconductor device structure 1> The semiconductor device of one embodiment of the present invention includes a transistor 300, a transistor The transistor 200 is disposed above the transistor 300. The capacitor element 100 is provided above the transistor 300 and the transistor 200. It is being done.

[0364] The transistor 300 is disposed on a substrate 311, and includes a conductor 316, an insulator 314, and a substrate 315. 11, a semiconductor region 312, which functions as a source region or a drain region. The low resistance region 318a and the low resistance region 318b are connected to each other.

[0365] Transistor 300 can be either p-channel or n-channel.

[0366] The region in the semiconductor region 312 where the channel is formed, the region in the vicinity thereof, the source region, or the drain region In the low resistance region 318a and the low resistance region 318b, which are the drain region, silicon is It preferably contains a semiconductor such as a silicon-based semiconductor, and preferably contains single crystal silicon. Or Ge (germanium), SiGe (silicon germanium), GaAs (gallium It may be formed of a material containing gallium aluminum arsenide (GaAlAs), GaAlAs (Gallium Aluminum Arsenide), etc. By applying stress to the crystal lattice and changing the lattice spacing, we can control the effective mass of silicon. Alternatively, GaAs and GaAlAs may be used to form a transistor. The 300 is a HEMT (High Electron Mobility Transistor) tor) can also be used.

[0367] The low resistance region 318a and the low resistance region 318b are semiconductor regions applied to the semiconductor region 312. In addition to the body material, elements that impart n-type conductivity, such as arsenic or phosphorus, or p-type conductivity, such as boron, are added. The element imparting electrical conductivity is included.

[0368] The conductor 316 that functions as the gate electrode is made of an element that gives n-type conductivity, such as arsenic or phosphorus. Semiconductor materials such as silicon that contain elements that impart p-type conductivity, such as silicon or boron A conductive material such as a metal material, an alloy material, or a metal oxide material can be used.

[0369] The threshold voltage can be adjusted by determining the work function depending on the conductor material. Specifically, it is preferable to use materials such as titanium nitride and tantalum nitride for the conductor. Furthermore, in order to achieve both conductivity and embeddability, tungsten or aluminum is used as the conductor. It is preferable to use any metal material for the lamination, and tungsten is particularly preferable because of its heat resistance. It is preferable in terms of sex.

[0370] The transistor 300 shown in FIG. 23 is an example, and the structure is not limited to this. An appropriate transistor may be used depending on the circuit and driving method. In this configuration, the transistor 300 does not need to be provided.

[0371] Over the transistor 300 are insulators 320, 322, 324, and The bodies 326 are stacked one on top of the other.

[0372] The insulators 320, 322, 324, and 326 may be, for example, oxide. Silicon, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, oxide Aluminum oxynitride, aluminum nitride oxide, aluminum nitride, etc. may be used.

[0373] The insulator 322 smooths out the steps caused by the transistor 300 and other components disposed below it. For example, the top surface of the insulator 322 may have a function as a flattening film. Chemical Mechanical Polishing (CMP) is used to improve the The surface may be planarized by a planarization process using a polishing method or the like.

[0374] The insulator 324 is also provided with a substrate 311 or a transistor 300 or the like. A film having a barrier property to prevent impurities such as hydrogen from diffusing into the region where the capacitor 200 is provided. Here, the barrier property means high oxidation resistance and resistance to oxygen, hydrogen, and It has the function of suppressing the diffusion of impurities such as water. For example, at 350℃ or 400℃ In an atmosphere, the diffusion distance of oxygen or hydrogen in a film having barrier properties per hour is It is sufficient if the thickness is 50 nm or less. Preferably, the film is formed in an atmosphere of 350°C or 400°C. The diffusion distance of oxygen or hydrogen per hour in a barrier film is 30 nm or less , and more preferably 20 nm or less.

[0375] An example of a film having a barrier property against hydrogen is silicon nitride formed by a CVD method. Here, a semiconductor having an oxide semiconductor such as the transistor 200 can be used. The diffusion of hydrogen into the element may cause a deterioration in the characteristics of the semiconductor element. A film that suppresses hydrogen diffusion is used between the transistor 200 and the transistor 300. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen. do.

[0376] The amount of desorbed hydrogen can be measured, for example, by thermal desorption spectroscopy (TDS). For example, analysis can be performed using methods such as ion spectroscopy. The amount of hydrogen desorption from insulator 324 was measured by TDS analysis in the range of 50°C to 500°C. The amount of desorption converted into hydrogen atoms per area of ​​the insulator 324 is 10 × 10 1 5 atoms / cm 2 Less than or equal to 5 x 10 15 atoms / cm 2 If it's below stomach.

[0377] It is preferable that the insulator 326 has a lower dielectric constant than the insulator 324. For example, The dielectric constant of the insulator 324 is preferably less than 4, more preferably less than 3. The relative dielectric constant of the insulating material 26 is preferably 0.7 times or less than the relative dielectric constant of the insulating material 324, and more preferably 0.6 times or less. It is more preferable to use a material with a low dielectric constant as the interlayer film to reduce the parasitic capacitance that occurs between wiring. It is possible.

[0378] In addition, the insulators 320, 322, 324, and 326 are provided with a capacitance element 1. 00, or a conductor 328 electrically connected to the transistor 200, and a conductor 330 The conductors 328 and 330 are plugs or wiring. As will be described later, the conductor that functions as a plug or wiring is In some cases, multiple structures may be collectively assigned the same symbol. The wiring and the plug electrically connected to the wiring may be integrated. Some of the conductors may function as wiring, and some of the conductors may function as plugs. .

[0379] The materials for each plug and wiring (conductor 328, conductor 330, etc.) are metal materials. Conductive materials such as metal alloys, metal nitrides, or metal oxides are deposited as single layers or They can be used in layers. Materials such as tungsten and molybdenum, which have both heat resistance and conductivity, are It is preferable to use a high melting point material such as tungsten. It is preferable to form the conductive layer from a low-resistance conductive material such as aluminum or copper. By using this, the wiring resistance can be reduced.

[0380] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. An insulator 350, an insulator 352, and an insulator 354 are stacked in this order. In addition, a conductor 356 is formed on the insulators 350, 352, and 354. The conductor 356 functions as a plug or wiring. The conductive material 328 and the conductive material 330 can be formed using the same materials.

[0381] For example, the insulator 350 has a barrier property against hydrogen, similar to the insulator 324. It is preferable to use an insulator. In addition, the conductor 356 has a barrier property against hydrogen. It is preferable that the insulating material 350 contains a conductor. In particular, the insulating material 350 has a barrier property against hydrogen. In the opening, a conductor having a barrier property against hydrogen is formed. The transistor 300 and the transistor 200 can be separated by a barrier layer. This can suppress the diffusion of hydrogen from the resistor 300 to the transistor 200.

[0382] As a conductor having a barrier property against hydrogen, for example, tantalum nitride or the like is used. In addition, by laminating tantalum nitride and highly conductive tungsten, The diffusion of hydrogen from the transistor 300 can be suppressed while maintaining the conductivity of the transistor 300. In this case, the tantalum nitride layer having a barrier property against hydrogen has a barrier property against hydrogen. It is preferable that the insulating material 350 is in contact with the insulating material 350.

[0383] On the insulator 354, an insulator 358, an insulator 210, an insulator 212, an insulator 213, an insulator The insulating body 214 and the insulating body 216 are stacked in this order. 210, insulator 212, insulator 213, insulator 214, and insulator 216 It is preferable to use a material that has barrier properties against oxygen and hydrogen.

[0384] For example, the insulator 358 and the insulator 212 may include, for example, a substrate 311 or a transistor. The area where the transistor 200 is to be provided is provided with impurities such as hydrogen. It is preferable to use a film that has a barrier property that prevents diffusion of substances. The same materials as in 4 can be used.

[0385] As an example of a film with barrier properties against hydrogen, silicon nitride formed by CVD is used. Here, a semiconductor element including an oxide semiconductor such as the transistor 200 can be The diffusion of hydrogen may deteriorate the characteristics of the semiconductor element. It is preferable to use a film that suppresses hydrogen diffusion between the capacitor 200 and the transistor 300. Specifically, a film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0386] In addition, as a film having a barrier property against hydrogen, for example, the insulator 213 and the insulator 2 14 uses metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide. It is preferable.

[0387] In particular, aluminum oxide is a material that can absorb oxygen and hydrogen, which can cause fluctuations in the electrical characteristics of transistors. Therefore, it has a high blocking effect that prevents impurities such as acid and moisture from passing through the membrane. Aluminum oxide is resistant to hydrogen, moisture, etc. during and after the transistor manufacturing process. It is possible to prevent impurities from being mixed into the transistor 200. This can suppress the release of oxygen from the oxide that makes up the transistor. Suitable for use as a protective film against 200.

[0388] For example, the insulators 210 and 216 may be made of the same material as the insulator 320. In addition, by using a material with a relatively low dielectric constant as the interlayer film, the For example, the insulator 216 may be a silicon oxide film or an oxide film. A silicon nitride film or the like can be used.

[0389] Also, the insulator 358, the insulator 210, the insulator 212, the insulator 213, the insulator 214, and The insulator 216 includes a conductor 218 and a conductor (conductor 205) and the like are embedded. The conductor 218 is a capacitor element 100 or a transformer. The conductor 21 functions as a plug or wiring that electrically connects to the resistor 300. 8 can be formed using the same material as the conductors 328 and 330.

[0390] In particular, the area in contact with the insulator 358, the insulator 212, the insulator 213, and the insulator 214 The conductor 218 is preferably a conductor having barrier properties against oxygen, hydrogen, and water. With this configuration, the transistor 300 and the transistor 200 can be easily oxidized. and a layer having a barrier property against water, which can completely separate the transistor. This can suppress the diffusion of hydrogen from the insulating layer 300 to the transistor 200 .

[0391] For example, if the insulator 224 has an excess oxygen region, the insulator 224 and the conductor 218, etc. It is advisable to use a conductor with high oxidation resistance for the conductor in contact with the wire. 218 and the conductor (conductor 205) constituting the transistor 200. With this configuration, the conductor 218 and the transformer The conductor (conductor 205) that constitutes the resistor 200 reacts with oxygen in the excess oxygen region and is oxidized. It is possible to suppress the generation of substances.

[0392] The transistor 200 is provided above the insulator 224. The structure of 00 may be realized by using the transistors described in the above embodiment. The transistor 200 shown in FIG. 1 is an example, and is not limited to this structure. The circuit configuration and driving method may be different. Appropriate transistors may be used accordingly.

[0393] Above the transistor 200 is an insulator 280. The insulator 280 contains excess oxygen regions. In particular, when an oxide semiconductor is used for the transistor 200, a region is preferably formed. In this case, an insulator having an excess oxygen region may be provided in an interlayer film near the transistor 200. As a result, the oxygen vacancies in the transistor 200 can be reduced, thereby improving reliability. do.

[0394] As an insulator having an excess oxygen region, specifically, an oxide film in which some oxygen is released by heating is used. It is preferable to use a material that releases oxygen when heated. , the amount of oxygen released in terms of oxygen atoms is 1.0 × 10 18 atoms / cm 3 Above, I like Or 3.0 x 10 20 atoms / cm 3 The oxide film is as described above. The surface temperature of the membrane during analysis is 100°C or higher and 700°C or lower, or 100°C or higher. A range of 500°C or less is preferred.

[0395] For example, a material containing silicon oxide or silicon oxynitride is used as such a material. It is preferable to use a metal oxide. Silicon oxynitride refers to a material that contains more oxygen than nitrogen in its composition, Silicon oxide refers to a material whose composition contains more nitrogen than oxygen.

[0396] The insulator 280 covering the transistor 200 is a planarizing layer that covers the uneven surface underneath. The insulator 280 may function as a membrane. The insulator 280 may also have conductors 244 and the like embedded therein. .

[0397] The conductor 244 is connected to the capacitor 100, the transistor 200, or the transistor 300. The conductor 244 functions as a plug or wiring for electrical connection. , and can be formed using the same material as the conductor 330.

[0398] For example, when the conductor 244 is provided as a laminated structure, a conductor that is resistant to oxidation (highly resistant to oxidation) is used. In particular, in the region in contact with the insulator 280 having the excess oxygen region, It is preferable to provide a conductor that is highly resistant to oxidation. This can prevent the conductor 244 from absorbing unnecessary oxygen. It is preferable that the conductive material has a barrier property against hydrogen. A conductor having a barrier property against impurities such as hydrogen is provided in the region in contact with the insulator 280. By providing the conductive material 244, impurities in the conductive material 244, diffusion of a part of the conductive material 244, and external It is possible to prevent the silicon dioxide from becoming a diffusion path for impurities.

[0399] Also, on the conductor 244, the conductor 246, the conductor 124, the conductor 112a, and the conductor The conductor 246 and the conductor 124 are connected to the capacitor element 100, the transistor The transistor 200 or the transistor 300 is electrically connected to the plug or wiring. The conductor 112a and the conductor 112b function as a capacitor. The conductor 246 and the conductor 112a are formed at the same time. Also, the conductor 124 and the conductor 112b can be formed simultaneously. do.

[0400] The conductor 246, the conductor 124, the conductor 112a, and the conductor 112b contain molybdenum, Titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, scandium A metal film containing an element selected from the above, or a metal nitride film (nitride film) containing the above elements as a component. The film may be a titanium nitride film, a molybdenum nitride film, a tungsten nitride film, or the like. Or, indium tin oxide, indium oxide containing tungsten oxide, tungsten oxide Indium zinc oxide containing tin oxide, indium oxide containing titanium oxide, titanium oxide Indium tin oxide, indium zinc oxide, indium tin oxide doped with silicon oxide Conductive materials such as oxides can also be applied.

[0401] In particular, the conductor 246 and the conductor 112a are covered with a metal nitride film such as a tantalum nitride film. , has barrier properties against hydrogen and oxygen, and is resistant to oxidation (high oxidation resistance) On the other hand, the conductor 124 and the conductor 112b are preferably made of, for example, tungsten. By using this combination, it is possible to laminate materials with high conductivity. Prevents hydrogen diffusion into the insulator 280 and the transistor 200 while maintaining electrical conductivity. In FIG. 23, the two-layer structure of the conductor 246 and the conductor 124 is However, the present invention is not limited to this configuration, and may be a single layer or a laminated structure of three or more layers. A conductor having a barrier property and a conductor having a high conductivity are placed between the conductor having a barrier property and the conductor having a high conductivity. A conductor having high adhesion may be formed on a conductor having high conductivity.

[0402] A barrier layer 281 may be provided on the conductor 124. Therefore, the conductor 124 can be prevented from being oxidized in a subsequent process. Impurities contained in the conductive material 124 and the diffusion of a part of the conductive material 124 can be suppressed. , conductor 124, conductor 246, and conductor 244, and impurities pass through insulator 28. It is possible to suppress diffusion to 0.

[0403] The barrier layer 281 can be made of an insulating material. The barrier layer 2 may function as a part of the dielectric of the capacitor element 100. 81 may be formed using a conductive material. In that case, it may be used as a part of wiring or an electrode. The function may be as follows.

[0404] The barrier layer 281 may be made of, for example, aluminum oxide, hafnium oxide, tantalum oxide, or the like. It is preferable to use a metal oxide or a metal nitride such as tantalum nitride. Aluminum oxide is a material that can absorb oxygen, hydrogen, and moisture, which can cause fluctuations in the electrical characteristics of transistors. Therefore, the membrane has a high blocking effect against impurities such as aluminum oxide. The aluminum is used as a conductor 124, hydrogen, water, etc. during and after the manufacturing process of the semiconductor device. This can prevent impurities such as atoms from entering the transistor 200.

[0405] An insulator 282 is provided on the barrier layer 281 and the insulator 280. It is preferable that 82 is made of a material that has a barrier property against oxygen and hydrogen. The insulator 282 can be made of the same material as the insulator 214. For example, the insulator 282 For the purpose, metal oxides such as aluminum oxide, hafnium oxide, and tantalum oxide are used. is preferred.

[0406] In particular, aluminum oxide is a material that can absorb oxygen and hydrogen, which can cause fluctuations in the electrical characteristics of transistors. Therefore, it has a high blocking effect that prevents impurities such as acid and moisture from passing through the membrane. Aluminum oxide is resistant to hydrogen, moisture, etc. during and after the transistor manufacturing process. It is possible to prevent impurities from being mixed into the transistor 200. This can suppress the release of oxygen from the oxide that makes up the transistor. Suitable for use as a protective film against 200.

[0407] Therefore, the transistor 200 and the insulator 280 containing the excess oxygen region are separated from the insulator 212 , the insulator 213, and the insulator 214 are laminated together, and the insulator 282 is sandwiched between them. In addition, the insulators 212, 213, 214, and 282 has a barrier property that suppresses the diffusion of impurities such as oxygen, hydrogen, and water.

[0408] The oxygen released from the insulator 280 and the transistor 200 is This can prevent the diffusion of the ions into the layer in which the transistor 300 is formed. The hydrogen and oxygen are introduced from the layers above the insulator 282 and below the insulator 214. This can prevent impurities such as water from diffusing into the transistor 200.

[0409] That is, oxygen is efficiently removed from the excess oxygen region of the insulator 280 to form the It can be supplied to the oxide where the channel is formed, and oxygen vacancies can be reduced. Impurities cause oxygen vacancies in the oxide that forms the channel in the transistor 200. Therefore, the channel in the transistor 200 is prevented from being formed. The oxide to be formed can be an oxide semiconductor having a low density of defect states and stable characteristics. That is, the fluctuation of the electrical characteristics of the transistor 200 can be suppressed and the reliability can be improved. It can be done.

[0410] Here, by dividing the large area substrate into individual semiconductor elements, a plurality of semiconductor devices can be formed into chips. Dicing lines (scribe lines, dividing lines, or (This is sometimes called a cutting line.) As a dividing method, for example, first, After forming grooves (dicing lines) on the substrate to separate the semiconductor elements, In some cases, the die is cut at the die line and divided (divided) into multiple semiconductor devices. A cross-sectional view of the vicinity of the lining line is shown.

[0411] For example, as shown in FIG. 29A, a transistor 200 is provided at the outer edge of the memory cell. Insulator 2 is placed near the area overlapping the dicing line (shown by the dashed line in the figure). 12, insulator 213, insulator 214, insulator 216, insulator 224, and insulator 280. An opening is provided. In addition, the insulators 212, 213, 214, 216, and An insulator 282 is provided to cover the edge 224 and the side surface of the insulator 280 .

[0412] Here, if the barrier layer 281 has insulating properties, the opening is Therefore, it is preferable to provide an insulator 282. By providing the barrier layer 281, impurities can be more effectively prevented. The diffusion of can be suppressed.

[0413] Therefore, in the opening, the insulators 212, 213, and 214, and the burr At this time, the insulating layer 212, the insulating layer 213, and the insulating layer 214 are in contact with each other. At least one of the insulating members 281 and the insulating member 282 is formed using the same material and method, thereby improving adhesion. The barrier layer 281 and the insulator 282 can be formed using the same material. For example, aluminum oxide can be used. After forming a dense film using a method such as ALD, the insulator 282 is formed by sputtering. By forming the film using a method with a high film formation rate, productivity and barrier properties can be improved. can be done.

[0414] With this structure, the insulators 212, 213, 214, and 282 Insulator 280 may encapsulate transistor 200. Insulator 212 may be an insulating The body 213, the insulator 214, and the insulator 282 inhibit the diffusion of oxygen, hydrogen, and water. Therefore, the substrate is formed in each circuit region where the semiconductor element shown in this embodiment mode is formed. By dividing the plate, even if it is processed into multiple chips, water can be removed from the side of the divided substrate. This can prevent impurities such as hydrogen or water from entering and diffusing into the transistor 200. .

[0415] In addition, this structure allows excess oxygen in the insulator 280 to flow into the insulators 282 and 214. Therefore, the excess oxygen in the insulator 280 can be prevented from diffusing to the outside. The oxide that forms the channel of the transistor 200 is supplied with oxygen. Therefore, it is possible to reduce oxygen vacancies in the oxide in which the channel of the transistor 200 is formed. This allows the oxide on which the channel in the transistor 200 is formed to be defect-free. An oxide semiconductor having low potential density and stable characteristics can be obtained. This can suppress fluctuations in the electrical characteristics of the star 200 and improve reliability.

[0416] Also, for example, as shown in FIG. 29(B), the dicing line (shown by the dashed line in the figure) In the regions on both sides, an insulator 212, an insulator 213, an insulator 214, an insulator 216, Openings may be provided in the insulator 224 and the insulator 280. In the figure, there are two openings. However, multiple openings may be provided as needed.

[0417] Therefore, insulator 212 and insulator 2 13 and the insulator 214 contact the barrier layer 281 in at least two places, resulting in a denser In this case, the insulators 212, 213, and At least one of the insulating body 214 and the insulating body 282 is formed using the same material and the same method. This can improve adhesion.

[0418] In addition, by providing a plurality of openings, the insulator 282, the insulator 212, the insulator 213, and The dicing can be performed in a structure in which the insulating material 214 and the insulating material 215 are in contact with each other in multiple areas. Impurities entering from the line can be prevented from reaching the transistor 200. do.

[0419] This structure allows the transistor 200 and the insulator 280 to be tightly sealed. Therefore, the oxide in which the channel of the transistor 200 is formed is made to have a low defect level density. In other words, the transistor 200 can be an oxide semiconductor having stable characteristics. This can suppress fluctuations in the electrical characteristics and improve reliability.

[0420] Next, the capacitor 100 is provided above the transistor 200. 00 is a conductor 112 (conductor 112a and conductor 112b), a barrier layer 281, It has an insulator 282, an insulator 130, and a conductor 116.

[0421] The conductor 112 functions as an electrode of the capacitor 100. For example, in the configuration shown in FIG. is a plug or wiring connecting to the transistor 200 and the transistor 300. A part of the conductor 244 that functions as the conductor 112 is configured to have the function of the conductor 112. When the barrier layer 281 is conductive, the barrier layer 281 is In addition, when the barrier layer 281 is insulating, the barrier layer 281 functions as a capacitor. It functions as part of the dielectric of the capacitor 100.

[0422] This configuration allows the number of steps to be reduced compared to when electrodes and wiring are formed separately. Therefore, productivity can be increased.

[0423] In addition, in the insulator 282, the region sandwiched between the conductor 112 and the conductor 116 is an insulator. For example, the insulator 282 may be made of a material with a high dielectric constant (hi) such as aluminum oxide. When a gh-k material is used, the capacitor 100 can ensure a sufficient capacitance.

[0424] An insulator 130 may be provided as part of the dielectric. The insulator 130 may be, for example, an oxide. silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, Aluminum oxide nitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, oxide Hafnium oxide nitride, hafnium nitride oxide, hafnium nitride, etc. may be used. can be provided in a single layer.

[0425] For example, the insulator 282 may be made of a high-k material such as aluminum oxide. In this case, it is preferable to use a material with high dielectric strength, such as silicon oxynitride, for the insulator 130. With this configuration, the capacitance element 100 has an improved dielectric strength due to the insulator 130. In addition, electrostatic damage to the capacitor element 100 can be suppressed.

[0426] The conductor 116 is connected to the barrier layer 281, the insulator 282, and the insulator 130. The conductive material 112 is provided so as to cover the side and top surfaces thereof. , is wrapped by the conductor 116 via an insulator. Since capacitance is also formed on the surface, the capacitance per projection area of ​​the capacitive element can be increased. Therefore, it becomes possible to reduce the area of ​​the semiconductor device, to increase the integration density, and to miniaturize the device.

[0427] The conductor 116 is made of a conductive material such as a metal material, an alloy material, or a metal oxide material. High-melting-point materials such as tungsten and molybdenum, which have both heat resistance and electrical conductivity, can be used. It is preferable to use a material, and it is particularly preferable to use tungsten. When forming the structure at the same time as other structures such as the above, low-resistance metal materials such as Cu (copper) and Al (aluminum) are used. Minium) or the like can be used.

[0428] An insulator 150 is provided on the conductor 116 and the insulator 130. The insulator 150 can be provided using the same material as the insulator 320. It may also function as a planarizing film that covers the underlying unevenness.

[0429] The above is a description of the configuration example. By using this configuration, In semiconductor devices using transistors, fluctuations in electrical characteristics are suppressed and reliability is improved. Alternatively, a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided. .

[0430] <Variation 1> As a modification of this embodiment, as shown in FIG. 24, a conductor 244 and a barrier That is, a layer 281 may be formed on the insulator 280. 44 and the conductor 112 that will become a part of the electrode of the capacitor element 100, and the conductor 244 A barrier layer 281 may be provided thereon using a conductor or insulator having barrier properties. In this case, the barrier layer 281 is made of a conductive material that not only has barrier properties but also has high oxidation resistance. With this structure, a part of the conductor 244 is preferably an electrode (conductor) of the capacitor. Since the conductor 112 functions as a separate conductor, there is no need to provide a separate conductor.

[0431] Therefore, as shown in FIG. 24, the capacitance element 100 is formed by a conductor 1, which is a region of the conductor 244. 12, insulator 282, insulator 130, and conductor 116.

[0432] The conductor 112 functioning as an electrode of the capacitor 100 is formed at the same time as the conductor 244. This configuration makes it possible to increase productivity. Since a mask for forming the electrodes of the capacitor element is not required, the number of steps can be reduced.

[0433] In addition, on the insulator 216, an insulator 220, an insulator 222, and an insulator 224 are sequentially formed. Any of the insulators 220, 222, and 224 is provided in a stacked manner. It is preferable to use a material that has a barrier property against oxygen and hydrogen for the insulator 22. 0, insulator 222, and insulator 224 are part of transistor 200 (gate insulator). It may function as a

[0434] The insulator 224 contains an oxide containing more oxygen than the oxygen required for the stoichiometric composition. In other words, the insulator 224 contains excess oxygen compared to the stoichiometric composition. It is preferable that a region where oxygen is present (hereinafter also referred to as an excess oxygen region) is formed. When an oxide semiconductor is used for the transistor 200, a base film near the transistor 200 By providing an insulator having an excess oxygen region in the transistor 200, oxygen vacancies in the transistor 200 are reduced. This can improve reliability.

[0435] As an insulator having an excess oxygen region, specifically, an oxide film in which some oxygen is released by heating is used. It is preferable to use a material that releases oxygen when heated. , the amount of oxygen released in terms of oxygen atoms is 1.0 × 10 18 atoms / cm 3 Above, I like Or 3.0 x 10 20 atoms / cm 3 The oxide film is as described above. The surface temperature of the membrane during analysis is 100°C or higher and 700°C or lower, or 100°C or higher. A range of 500°C or less is preferred.

[0436] For example, a material containing silicon oxide or silicon oxynitride is used as such a material. It is preferable to use a metal oxide. Silicon oxynitride refers to a material that contains more oxygen than nitrogen in its composition, Silicon oxide refers to a material whose composition contains more nitrogen than oxygen.

[0437] Also, if the insulator 224 has an excess oxygen region, the insulator 222 or the insulator 220 The insulator 222 preferably has a barrier property against oxygen, hydrogen, and water. Alternatively, the insulator 220 has a barrier property against oxygen, so that the oxygen in the excess oxygen region is The oxide 2 of the transistor 200 is efficiently diffused without diffusing to the transistor 300 side. 30. Also, the conductor 218 and the transistor 200 can be The conductor (conductor 205) reacts with oxygen in the excess oxygen region to prevent the generation of oxides. It can be controlled.

[0438] The above is the description of the modified example. By using this structure, In semiconductor devices using transistors, fluctuations in electrical characteristics are suppressed and reliability is improved. Alternatively, a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided. .

[0439] <Variation 2> As a modification of this embodiment, as shown in FIG. 25, a conductor 219, a conductor 244 In other words, the insulator 280 may be provided with a conductive material 246 having a barrier property. A conductor 244 serving as a gasket or wiring is embedded, and a conductive material having a barrier property is formed on the conductor 244. In this case, the conductor 246 has not only a barrier property but also a resistance property. It is preferable to use a conductor with high oxidizing properties. The conductor 6 and the conductor 112 that functions as an electrode of the capacitor can be formed at the same time. With this configuration, the conductor 246 also functions as a barrier layer, so a separate barrier layer There is no need to set

[0440] Therefore, as shown in FIG. 25, the capacitance element 100 is made up of a conductor 112, an insulator 282, and The capacitor element 100 includes an insulator 130 and a conductor 116. Conductor 112 can be formed simultaneously with conductive material 246 .

[0441] The above is the description of the modified example. By using this structure, In semiconductor devices using transistors, fluctuations in electrical characteristics are suppressed and reliability is improved. Alternatively, a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided. .

[0442] <Variation 3> As a modification of this embodiment, a capacitance element 100 as shown in FIG. 26 may be provided. That is, the conductor 244 that becomes a plug or wiring is embedded in the insulator 280, and the conductor 2 After providing a barrier layer 281 having a barrier property on the substrate 44, an insulator 282 having a barrier property is formed. Then, a highly flat insulator 286 is formed on the insulator 284. By providing the insulator 286, the capacitor 100 can be provided over the insulator 286 with high planarity.

[0443] The capacitance element 100 is provided on an insulator 286 and includes a conductor 112 (conductor 112a, conductor 112b), insulator 130, insulator 132, and insulator 134, and conductor 11 6. Note that the conductor 124 is a capacitor 100, a transistor 200, or a transistor It functions as a plug or wiring that electrically connects to the transistor 300 .

[0444] The conductor 112 is made of a conductive material such as a metal material, an alloy material, or a metal oxide material. High-melting-point materials such as tungsten and molybdenum, which have both heat resistance and electrical conductivity, are used. It is preferable to use tungsten, and it is particularly preferable to use tungsten. When forming the structure at the same time as other structures, low-resistance metal materials such as Cu (copper) and Al (aluminum) are used. It is best to use a

[0445] An insulator 130, an insulator 132, and an insulator 134 are provided on the conductor 112. The insulating layer 130, the insulating layer 132, and the insulating layer 134 may be made of, for example, silicon oxide or silicon oxynitride. Silicon, silicon oxide nitride, silicon nitride, aluminum oxide, aluminum oxide nitride, nitrogen Aluminum oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, nitriding oxide Hafnium oxide, hafnium nitride, etc. can be used. Although the figure shows a three-layer structure, a single layer It may also have a laminated structure of two layers, or four or more layers.

[0446] For example, the insulators 130 and 134 may be made of a material with high dielectric strength such as silicon oxynitride. The insulator 132 is made of a high dielectric constant (high-k) material such as aluminum oxide. With this configuration, the capacitor element 100 has a high dielectric constant. -k) insulator ensures sufficient capacity and has high dielectric strength This improves the dielectric strength and makes it possible to prevent electrostatic breakdown of the capacitor element 100.

[0447] On the conductor 112, through the insulator 130, the insulator 132, and the insulator 134, The conductor 116 is made of a metal material, an alloy material, a metal oxide material, or the like. Any conductive material can be used. Tungsten and molybdenum are suitable because they are both heat-resistant and conductive. It is preferable to use a high melting point material such as aluminum, and it is particularly preferable to use tungsten. In addition, when forming the layer simultaneously with other structures such as conductors, it is recommended to use Cu( Copper (copper) or aluminum (Al) may be used.

[0448] In addition, in the conductor 112 that functions as one of the electrodes, a convex shape such as the conductor 112b is By forming a structure having the above structure, it is possible to increase the capacitance per projected area of ​​the capacitor element. Therefore, it becomes possible to reduce the area, increase the integration density, and miniaturize the semiconductor device.

[0449] The above is the description of the modified example. By using this structure, In semiconductor devices using transistors, fluctuations in electrical characteristics are suppressed and reliability is improved. Alternatively, a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided. .

[0450] <Variation 4> FIG. 27 shows an example of a modification of this embodiment. FIG. 27 shows a modification of FIG. 23. The configurations of the transistor 300 and the transistor 200 are different.

[0451] The transistor 300 shown in FIG. 27 includes a semiconductor region 312 (substrate 311) where a channel is formed. The side and top surfaces of the semiconductor region 312 are covered with an insulator 314. The conductor 316 is provided to cover the conductor 316 through the work function. Such a transistor 300 may be fabricated by utilizing a protruding portion of a semiconductor substrate. It is also called a FIN type transistor because it is in contact with the top of the convex part. The semiconductor device may have an insulator that functions as a mask for forming the semiconductor. In the example shown, a convex portion is formed by processing a part of the SOI substrate. A semiconductor film having the above structure may be formed.

[0452] The details of the structure of the transistor 200 shown in FIG. 27 have been described in the above embodiment. The oxide, gate insulator, and gate conductor are formed in the opening formed in 0. Therefore, at least the conductor 246 having a barrier property is formed on the conductor that becomes the gate. It is preferable to form

[0453] The conductor 112 (conductor 246) may be made of a material containing oxygen, hydrogen, or A conductive material with water barrier properties is combined with a highly conductive material such as tungsten or copper. When used in layers, highly conductive conductors such as tungsten and copper are The barrier layer 281 completely seals the conductive material, thereby preventing the diffusion of the conductive material itself, such as copper. At the same time, impurities are prevented from entering from above the insulator 282 through the conductor 244. This can suppress the above.

[0454] The capacitor 100 is provided above the transistor 200. In the configuration, the capacitor element 100 includes a conductor 112, a conductor 246 having a barrier property, and an insulating material. It has an edge 282, an insulator 130, and a conductor 116.

[0455] The conductor 112 functions as an electrode of the capacitor 100. For example, in the configuration shown in FIG. is a plug or wiring connecting to the transistor 200 and the transistor 300. A part of the conductor 244 that functions as the conductor 112 is configured to have the function of the conductor 112. When the barrier layer 281 is conductive, the barrier layer 281 is When the barrier layer 281 is insulating, the barrier layer 281 functions as a part of the insulating layer. It functions as a dielectric of the capacitive element 100 .

[0456] This configuration allows the number of steps to be reduced compared to when electrodes and wiring are formed separately. Therefore, productivity can be increased.

[0457] The above is the description of the modified example. By using this structure, In semiconductor devices using transistors, fluctuations in electrical characteristics are suppressed and reliability is improved. Alternatively, a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided. .

[0458] <Variation 5> An example of a modification of this embodiment is shown in FIG. 28. FIG. 28 is a circuit diagram of a transistor in FIG. 26. The configuration of the controller 200 is different.

[0459] As shown in FIG. 28, an insulator 279 and a barrier layer 271 may be provided. 9 can be formed using the same materials and manufacturing methods as the insulator 280. , insulator 279, like insulator 280, contains more oxygen than meets the stoichiometric composition. It is preferable to use an oxide containing oxygen. Therefore, the insulator 279 is a silicon oxide film or An insulator containing oxygen, such as a silicon oxynitride film. Form an insulator containing excess oxygen. As a method, the film formation conditions in the CVD method or sputtering method are appropriately set to add oxygen to the film. It is possible to form a silicon oxide film or a silicon oxynitride film containing a large amount of silicon. After forming the insulating material that will become the insulating material 279, the CMP method or the like is used to improve the flatness of the upper surface. Also, the insulator 279 may be subjected to a planarization process to form an excess oxygen region. For example, oxygen can be added by ion implantation, ion doping, or plasma treatment. good.

[0460] The barrier layer 271 is made of an insulating material or a conductor that has barrier properties against oxygen. The aluminum layer 271 may be made of, for example, aluminum oxide, hafnium oxide, tantalum oxide, or tantalum nitride. The metal is deposited by sputtering or atomic layer deposition (ALD). The film can be provided by using a deposition method.

[0461] An insulator 280 is provided on the insulator 279 and the barrier layer 271. By providing the insulator 280 using the same material and manufacturing method, When the excessive oxygen treatment is performed, the introduced excess oxygen is not only insulator 280 but also insulator Therefore, an excess oxygen region is formed in the insulator 280 and the insulator 279. To form the insulating layer 280, for example, ion implantation, ion doping, or plating may be performed. Oxygen may be added by Zuma treatment.

[0462] The above is the description of the modified example. By using this structure, In semiconductor devices using transistors, fluctuations in electrical characteristics are suppressed and reliability is improved. Alternatively, a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided. .

[0463] <Variation 6> An example of a modification of this embodiment is shown in FIG. 31. ) respectively represent the channel length of the transistor 200, and 1 shows a cross section in the channel width direction.

[0464] As shown in FIG. 31, the transistor 200 and the insulator 280 containing the excess oxygen region are The laminated structure of the insulator 212 and the insulator 214 and the laminated structure of the insulator 282 and the insulator 284 The transistor 300 and the capacitor 10 may be wrapped in a stacked structure. 0 and the transistor 200, an insulator 212 and an insulator It is preferable that the laminated structure of 214 contacts the laminated structure of insulator 282 and insulator 284. It's nice.

[0465] Therefore, oxygen released from the insulator 280 and the transistor 200 is released into the capacitor element 10 0 or can suppress diffusion into the layer in which the transistor 300 is formed. Alternatively, water may flow from the layer above the insulator 282 and the layer below the insulator 214. The diffusion of impurities such as hydrogen and water into the transistor 200 can be suppressed. do.

[0466] That is, oxygen is efficiently removed from the excess oxygen region of the insulator 280 to form the It can be supplied to the oxide in which the channel is formed, and oxygen vacancies can be reduced. Impurities cause oxygen vacancies in the oxide that forms the channel in the transistor 200. Therefore, the channel in the transistor 200 is prevented from being formed. The oxide to be formed can be an oxide semiconductor having a low density of defect states and stable characteristics. That is, the fluctuation of the electrical characteristics of the transistor 200 can be suppressed and the reliability can be improved. It can be done.

[0467] <Variation 7> An example of a modification of this embodiment is shown in FIG. 32. FIG. 32(A) shows the same as FIG. 30(A). 1 is a circuit diagram showing a part of a row when the semiconductor device shown in FIG. 1 is arranged in a matrix. FIG. 32B is a cross-sectional view of a semiconductor device corresponding to the circuit diagram of FIG. be.

[0468] FIG. 32 shows a circuit diagram of a semiconductor device having a transistor 300, a transistor 200, and a capacitor element 100. A semiconductor device including a transistor 301, a transistor 201, and a capacitor 101 a semiconductor device having a transistor 302, a transistor 202, and a capacitor 102; The semiconductor devices are arranged in the same row.

[0469] As shown in FIG. 32(B), a plurality of transistors (in the figure, transistors 200 and The insulator 280 containing the excess oxygen region is connected to the insulator 212 and the The laminated structure of the insulating material 214 and the insulating material 282 and the insulating material 284 is used to encase the insulating material. In this case, the transistor 300, the transistor 301, or the transistor The transistor 302 is connected to the capacitance element 100, the capacitance element 101, or the capacitance element 102. a through electrode and a transistor 200, a transistor 201, or a transistor 202 Between the insulators 212 and 214, and the insulators 282 and 284, It is preferable that the layer has a laminated structure.

[0470] Therefore, oxygen released from the insulator 280 and the transistor 200 is released into the capacitor element 10 0 or can suppress diffusion into the layer in which the transistor 300 is formed. Alternatively, water may flow from the layer above the insulator 282 and the layer below the insulator 214. The diffusion of impurities such as hydrogen and water into the transistor 200 can be suppressed. do.

[0471] That is, oxygen is efficiently removed from the excess oxygen region of the insulator 280 to form the It can be supplied to the oxide in which the channel is formed, and oxygen vacancies can be reduced. The oxide in which the channel of the transistor 200 is formed is subject to oxygen vacancies due to impurities. Therefore, the channel in the transistor 200 is prevented from being formed. The oxide to be formed can be an oxide semiconductor having a low density of defect states and stable characteristics. That is, the fluctuation of the electrical characteristics of the transistor 200 can be suppressed and the reliability can be improved. It can be done.

[0472] <Variation 8> An example of a modification of this embodiment is shown in FIG. 33. FIG. 33 shows the semiconductor device shown in FIG. In the device, a semiconductor device in which a transistor 201 and a transistor 202 are integrated is shown. FIG.

[0473] As shown in FIG. 33, the function of a conductor 112 which is one of the electrodes of the capacitor element 101 is changed to a transformer. A conductor that serves as the source electrode or drain electrode of the transistor 201 may be provided. The oxide of the transistor 201 and acts as the gate insulator of the transistor 201 The insulator extends over the conductor that will become the source or drain electrode of the transistor 201. The region functions as an insulator of the capacitor 101. The conductor 116 is formed by depositing an insulator 250 and an oxide 230c on the conductor 240a. This configuration allows for a smaller area, higher integration, and finer design of the semiconductor device. It becomes Noh.

[0474] The transistor 201 and the transistor 202 may be provided overlapping each other. This allows for a smaller area, higher integration, and finer design of the semiconductor device.

[0475] In addition, a plurality of transistors (transistor 201 and transistor 202 in the figure) and an insulator 280 including an excess oxygen region, and a stack of the insulators 212 and 214. The insulating film 281 may be wrapped in a laminated structure of the insulating film 282 and the insulating film 284. At this time, the transistor 300, the transistor 301, or the transistor 302 and the capacitor a through electrode connecting the capacitor element 100, the capacitor element 101, or the capacitor element 102; Between the transistor 200, the transistor 201, or the transistor 202, an insulator 21 is provided. 2 and the insulator 214, and the insulator 282 and the insulator 284 form a laminated structure. is preferred.

[0476] Therefore, oxygen released from the insulator 280 and the transistor 200 is released into the capacitor element 10 0 or can suppress diffusion into the layer in which the transistor 300 is formed. Alternatively, water may flow from the layer above the insulator 282 and the layer below the insulator 214. The diffusion of impurities such as hydrogen and water into the transistor 200 can be suppressed. do.

[0477] That is, oxygen is efficiently removed from the excess oxygen region of the insulator 280 to form the It can be supplied to the oxide where the channel is formed, and oxygen vacancies can be reduced. Impurities cause oxygen vacancies in the oxide that forms the channel in the transistor 200. Therefore, the channel in the transistor 200 is prevented from being formed. The oxide to be formed can be an oxide semiconductor having a low density of defect states and stable characteristics. That is, the fluctuation of the electrical characteristics of the transistor 200 can be suppressed and the reliability can be improved. It can be done.

[0478] This embodiment may be appropriately combined with at least a part of another embodiment described in this specification. It can be implemented in combination.

[0479] (Embodiment 5) In this embodiment, a semiconductor device including a transistor according to one embodiment of the present invention will be described. An example of the circuit will be described.

[0480] <Circuit> An example of a circuit of a semiconductor device using a transistor or the like according to one embodiment of the present invention will be described below. This will be explained with reference to FIGS. 34 and 35.

[0481] <Storage device 1> The semiconductor device shown in FIG. 34 is the same as the semiconductor device shown in FIG. This case is also different from the semiconductor device shown in the previous embodiment. By the same operation, it is possible to write and hold information. 00 may be a transistor similar to the transistor 300 described above.

[0482] The wiring 3006 is electrically connected to the gate of the transistor 3400. One of the source and drain of transistor 00 is electrically connected to the drain of transistor 300. The other of the source and drain of the transistor 3400 is electrically connected to the wiring 3003 .

[0483] <Storage device 2> A modification of the semiconductor device (memory device) will be described with reference to the circuit diagram shown in FIG.

[0484] The semiconductor device illustrated in FIG. 35 includes transistors 4100 to 4400 and a capacitor. The transistor 4100 has a capacitor 4500 and a capacitor 4600. A transistor similar to the transistor 300 can be used, and the transistor 4200 4400 can be transistors similar to transistor 200 described above. In addition, the capacitor element 4500 and the capacitor element 4600 are the same as the capacitor element 100 described above. A similar capacitor element can be used. Although not shown, a plurality of wirings are provided in a matrix. 01, the wiring 4003, and the wirings 4005 to 4009 are connected in accordance with signals or potentials. It is possible to control the writing and reading of the capacitor voltage.

[0485] One of the source and the drain of the transistor 4100 is connected to a wiring 4003. The other of the source and the drain of the transistor 4100 is connected to a wiring 4001. In FIG. 35, the conductivity type of the transistor 4100 is shown as a p-channel type. That's fine too.

[0486] The semiconductor device shown in FIG. 35 has two data holding units. For example, the first data holding unit is , one of the source and drain of the transistor 4400 connected to the node FG1, One electrode of the element 4600 and one of the source and drain of the transistor 4200 The second data storage unit stores a charge between the transistor connected to node FG1 and the transistor connected to node FG2. the gate of the transistor 4100, the other of the source or drain of the transistor 4200, One of the source or drain of the transistor 4300 and one of the electrodes of the capacitor element 4500 The charge is held between

[0487] The other of the source and the drain of the transistor 4300 is connected to a wiring 4003. The other of the source and drain of the transistor 4400 is connected to a wiring 4001. The gate of the transistor 4400 is connected to the wiring 4005. The gate of the transistor 4300 is connected to a wiring 4006. The gate of the transistor 4300 is connected to a wiring 4007. The other electrode of the capacitor 4600 is connected to the wiring 4008. The other electrode of 00 is connected to a wiring 4009 .

[0488] The transistors 4200 to 4400 are transistors that control writing of data voltages and retention of charges. Note that the transistors 4200 to 4400 are in a non-conducting state. In this case, a transistor with a low current (off-state current) that flows between the source and drain is used. As a transistor with a low off-state current, a transistor having an oxidized layer in a channel formation region is preferably used. Preferably, the transistor is an OS transistor. The transistor has advantages such as low off-state current and the ability to be stacked with a silicon-containing transistor. In FIG. 35, the conductivity types of the transistors 4200 to 4400 are n-channel. However, it may be a p-channel type.

[0489] The transistors 4200, 4300, and 4400 are oxidized. Even if the transistor uses a compound semiconductor, it is preferable to provide it in a separate layer. The semiconductor device shown in FIG. 5 includes a transistor 4100, a transistor 4200, and a transistor It is preferable that the transistor 4300 and the transistor 4400 are stacked. By integrating transistors, the circuit area can be reduced, leading to the miniaturization of semiconductor devices. This can be achieved.

[0490] Next, the operation of writing information into the semiconductor device shown in FIG. 35 will be described.

[0491] First, a data voltage write operation (hereinafter, ) will be described below. The data voltage written to the data storage unit is V D1 and the threshold voltage of the transistor 4100 is The voltage is Vth.

[0492] In write operation 1, the wiring 4003 is connected to V D1 Then, after setting the wiring 4001 to the ground potential, The wirings 4005 and 4006 are set to a high level. 007 to 4009 are set to low level. Then, the node FG2 in an electrically floating state The potential of the wiring 40 increases, and a current flows through the transistor 4100. The potential of the transistor 4400 and the transistor 4200 are turned on. Therefore, as the potential of the wiring 4001 increases, the potentials of the nodes FG1 and FG2 also increase. The potential of the node FG2 rises, and a potential difference between the gate and source of the transistor 4100 is When the voltage (Vgs) reaches the threshold voltage Vth of the transistor 4100, the transistor 410 Therefore, the potential of the wiring 4001 and the nodes FG1 and FG2 is The rise stopped, and V D1 Vth has dropped from D1 -Vth" and becomes constant.

[0493] In other words, the V given to wire 4003D1 When a current flows through the transistor 4100, The potential is applied to the wiring 4001, and the potentials of the nodes FG1 and FG2 increase. , the potential of node FG2 is "V D1 -Vth", the Vgs of transistor 4100 is Vth is reached, and the current stops.

[0494] Next, the data voltage is written to the data storage unit connected to the node FG2 (hereinafter, referred to as the write The data holding operation connected to node FG2 is called write operation 2. The data voltage written to the part is V D2 It will be explained as follows.

[0495] In write operation 2, wire 4001 is connected to V D2 Then, after setting the wiring 4003 to the ground potential, The wiring 4007 is set to a high level. 4006, 4008, and 4009 are set to low level. Transistor 4300 is set to the conductive state. Therefore, the potential of the node FG2 is also set to low level. The voltage of the wiring 4003 decreases as the voltage of the wiring 4003 decreases. The potential of the wiring 4003 increases. As the potential at node FG2 rises, the potential at node FG2 also rises. When Vgs of transistor 4100 becomes Vth of transistor 4100, The current flowing through 100 becomes smaller. Therefore, the potential of wiring 4003 and FG2 does not stop rising. Ri, V D2 Vth has dropped from D2 -Vth" and becomes constant.

[0496] In other words, the V given to wire 4001D2 When a current flows through the transistor 4100, The potential of the node FG2 is increased by the increase in the potential. The potential of FG2 is "V D2 -Vth", Vgs of transistor 4100 is Vth. At this time, the potential of the node FG1 is 400 are in a non-conductive state, and the "V D1 -Vth" is maintained can be.

[0497] In the semiconductor device shown in FIG. 35, after writing data voltages to a plurality of data holding units, 4009 is set to high level, and the potentials of the nodes FG1 and FG2 are raised. The transistor is made non-conductive, preventing the movement of charge and maintaining the written data voltage. .

[0498] By the above-described operation of writing data voltages to the nodes FG1 and FG2, multiple data The data voltage can be held in the data holding section. D 1-Vth" and "V D2 -Vth" was used as an example, but these are multi-value data. Therefore, each data storage unit stores 4 bits of data. When holding 16 values ​​of "V D1 -Vth" and "V D2 -Vth" can be used.

[0499] Next, the operation of reading information from the semiconductor device shown in FIG. 35 will be described.

[0500] First, the data voltage is read from the data storage unit connected to node FG2 (hereinafter referred to as (This is called read operation 1.) will now be described.

[0501] In the read operation 1, the wiring 4003 is precharged and then brought into an electrically floating state. The wirings 4005 to 4008 are set to a low level. The potential of the electrically floating node FG2 is set to "V D2 -Vth" When the potential of the node FG2 decreases, a current flows through the transistor 4100. The flow of current reduces the potential of the electrically floating wiring 4003. As the voltage Vgs of transistor 4100 decreases, the voltage Vgs of transistor 4100 decreases. When Vgs becomes Vth of the transistor 4100, the current flowing through the transistor 4100 becomes That is, the potential of the wiring 4003 becomes smaller than the potential of the node FG2 “V D2 -Vth" Vth is larger than Vth. D2 The potential of the wiring 4003 is The data voltage of the data storage section connected to G2 corresponds to the data of the analog value that is read out. The voltage of the capacitor undergoes A / D conversion and acquires data from the data storage section connected to node FG2. .

[0502] That is, the wiring 4003 after precharging is in a floating state, and the potential of the wiring 4009 is set to a high level. Switching the voltage from high to low allows current to flow through transistor 4100. As a result, the potential of the wiring 4003, which was in a floating state, drops to "V D2 ". Tran In register 4100, the "V D2 Vgs between "-Vth" is Vth The current stops. Then, the wiring 4003 is connected to the "V D2 " is read out.

[0503] After acquiring the data of the data storage section connected to node FG2, transistor 4300 is turned on. In the conductive state, the "V D2 -Vth" is discharged.

[0504] Next, the charge held at node FG1 is distributed to node FG2, and the The data voltage of the data storage unit connected to node FG1 is transferred to the data storage unit connected to node FG2. The wiring 4001 and 4003 are set to low level, and the wiring 4006 is set to high level. , the wiring 4005 and the wirings 4007 to 4009 are set to low level. is turned on, the charge of the node FG1 is shared with the node FG2.

[0505] Here, the potential after the charge distribution is the written potential "V D1 -Vth" and Therefore, the capacitance value of the capacitor 4600 is set to be larger than the capacitance value of the capacitor 4500. Alternatively, the potential "V D1 -Vth" is the same data The potential "V D2 It is preferable to set the capacitance value to be larger than "-Vth". By changing the ratio of the potential and increasing the potential to be written in advance, the potential after the charge distribution can be reduced. The fluctuation of the potential due to the distribution of the charge will be described later.

[0506] Next, the data voltage is read from the data storage unit connected to the node FG1 (hereinafter, This will be referred to as read operation 2.

[0507] In the read operation 2, the wiring 4003 is precharged and then placed in an electrically floating state. The wirings 4005 to 4008 are set to a low level. It is set to high level during precharge and then to low level. By using this as a pin, the electrically floating node FG2 is set to the potential "V D1 -Vth" When the potential of the node FG2 decreases, a current flows through the transistor 4100. As a result, the potential of the wiring 4003 in an electrically floating state is reduced. As the voltage drops, the Vgs of transistor 4100 decreases. When gs becomes Vth of the transistor 4100, the current flowing through the transistor 4100 becomes small. That is, the potential of the wiring 4003 becomes lower than the potential of the node FG2 “V D1 -Vth" or Vth is larger than Vth. D1 The potential of the wiring 4003 is The analog value data read out corresponds to the data voltage of the data storage section connected to 1. The voltage undergoes A / D conversion, and data is acquired from the data storage unit connected to node FG1. The above is the operation of reading out the data voltage from the data storage unit connected to node FG1. .

[0508] That is, the wiring 4003 after precharging is in a floating state, and the potential of the wiring 4009 is set to a high level. Switching the voltage from high to low allows current to flow through transistor 4100. As a result, the potential of the wiring 4003, which was in a floating state, drops to "V D1 ". Tran In register 4100, the "V D1 Vgs between "-Vth" is Vth The current stops. Then, the wiring 4003 is connected to the "V D1 " is read out.

[0509] By the above-described operation of reading the data voltages from the nodes FG1 and FG2, a plurality of data For example, the data voltage can be read from the data storage unit. FG2 stores 4 bits (16 values) of data, for a total of 8 bits (256 values) In FIG. 35, the first layer 4021 to the third layer 4022 can store data. However, by forming further layers, the surface of the semiconductor device can be It is possible to increase the storage capacity without increasing the product.

[0510] The potential that is read out is a voltage that is Vth higher than the written data voltage. Therefore, the "V D1 -Vth" and "V D2 - As a result, the Vth of the memory cell can be offset and read. This improves the storage capacity per memory and also brings the read data closer to the correct data. This allows for excellent data reliability.

[0511] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0512] (Sixth embodiment) In this embodiment, a circuit configuration to which the OS transistor described in the above embodiment can be applied is described. An example of this will be described with reference to FIGS.

[0513] The inverter circuit diagram is shown in FIG. 36(A). The inverter 5800 receives the voltage at the input terminal IN. The inverter 5800 outputs a signal obtained by inverting the logic of the signal from the output terminal OUT. The signal S BG Switching the electrical characteristics of OS transistors It is a signal that can be used.

[0514] FIG. 36B shows an example of an inverter 5800. The inverter 5800 is an OS transistor. The inverter 5800 includes an n-channel transistor 5810 and an n-channel OS transistor 5820. Since it can be fabricated with a complementary metal-oxide semiconductor (CMOS) transistor, ary Metal Oxide Semiconductor inverter (CMO It can be manufactured at a lower cost than manufacturing a conventional inverter (S inverter).

[0515] The inverter 5800 having an OS transistor is a C inverter made of Si transistors. It can also be placed on MOS. The inverter 5800 is placed on top of the CMOS circuit. Therefore, the increase in circuit area due to the addition of the inverter 5800 can be suppressed.

[0516] The OS transistors 5810 and 5820 each have a first gate that functions as a front gate; A second gate acts as a back gate and a second gate acts as either a source or a drain. It has a first terminal and a second terminal that functions as the other of the source or drain.

[0517] The first gate of OS transistor 5810 is connected to the second terminal. The second gate of 810 receives the signal S BG The OS transistor 58 is connected to the wiring that supplies the OS transistor 58. The first terminal of the OS transistor 5810 is connected to a wiring that supplies a voltage VDD. The second terminal is connected to the output terminal OUT.

[0518] A first gate of the OS transistor 5820 is connected to the input terminal IN. The second gate of the OS transistor 5820 is connected to the input terminal IN. The first terminal of the OS transistor 5820 is connected to the output terminal OUT. Connected to the wire that supplies VSS.

[0519] FIG. 36C is a timing chart for explaining the operation of the inverter 5800. In the timing chart of Figure 36(C), the signal waveform of the input terminal IN and the signal waveform of the output terminal OUT are Signal waveform, signal S BG The signal waveform of the OS transistor 5810 (FET5810) 4 shows the change in threshold voltage of the

[0520] signal S BG is applied to the second gate of the OS transistor 5810, The threshold voltage of 5810 can be controlled.

[0521] signal S BG is the voltage V for shifting the threshold voltage negatively BG_A , threshold voltage Voltage V BG_B The second gate has a voltage V BG_A To give The OS transistor 5810 has a threshold voltage V TH_A can be negatively shifted to Also, the second gate is connected to a voltage V BG_B By providing Threshold voltage V TH_B can be shifted positively to

[0522] To visualize the above explanation, FIG. 37(A) shows one of the electrical characteristics of a transistor. The Vg-Id curve is shown.

[0523] The electrical characteristics of the OS transistor 5810 described above are such that the voltage of the second gate is V BG_A of By increasing the value, the curve is shifted to the curve shown by the dashed line 5840 in FIG. 37(A). The electrical characteristics of the OS transistor 5810 can be determined by the voltage of the second gate. Voltage V BG_B By making it smaller, the solid line 5841 in Figure 37(A) can be As shown in FIG. 37A, the OS transistor 58 10 is signal S BG voltage V BG_A or voltage V BG_B Switching like this This allows the threshold voltage to be shifted in a positive or negative direction.

[0524] The threshold voltage is V TH_B By shifting it to positive, the OS transistor 5810 This state can be visualized in Figure 37(B). As shown in FIG. 37B, the current I B Extreme Therefore, when the signal applied to the input terminal IN is high level, When the transistor 5820 is in the ON state, it causes the voltage at the output terminal OUT to drop sharply. It can be done.

[0525] As shown in FIG. 37B, the current flowing through the OS transistor 5810 is difficult. Therefore, the output terminal in the timing chart shown in FIG. The signal waveform 5831 can be changed sharply. It is possible to reduce the through current flowing between the wiring that supplies SS, resulting in low power consumption. The following operations can be performed.

[0526] Also, the threshold voltage is V TH_A By shifting the voltage to the negative side, the OS transistor 5810 can be made to be in a state where current can easily flow. As shown in Figure 37(C), the current I A At least Flow I B Therefore, the signal applied to the input terminal IN is low level. When the OS transistor 5820 is in the OFF state, it quickly reduces the voltage of the output terminal OUT. It can be increased sharply.

[0527] As shown in FIG. 37C, the current easily flows through the OS transistor 5810. Therefore, the output terminal in the timing chart shown in FIG. The signal waveform 5832 can be changed sharply.

[0528] In addition, signal S BG The control of the threshold voltage of the OS transistor 5810 by It is preferable to perform this before the state of the controller 5820 is switched, that is, before time T1 or T2. For example, as shown in FIG. 36(C), when the signal applied to the input terminal IN is at a high level, Before the time T1 at which the transistor switches to the threshold voltage V TH_A to threshold voltage V TH_B OS to It is preferable to switch the threshold voltage of the transistor 5810. In this way, before time T2 when the signal applied to the input terminal IN is switched to low level, Threshold voltage V TH_B to threshold voltage V TH_A The threshold voltage of the OS transistor 5810 is then changed. It is preferable to change it.

[0529] In the timing chart of FIG. 36(C), the signal S BG However, other configurations may be used. For example, a configuration for controlling the threshold voltage The voltage for this is held at the second gate of the OS transistor 5810, which is in a floating state. An example of a circuit configuration that can realize this configuration is shown in FIG. Shown below.

[0530] In FIG. 38A, in addition to the circuit configuration shown in FIG. 36B, an OS transistor 5850 The first terminal of OS transistor 5850 is connected to the second gate of OS transistor 5810. The second terminal of OS transistor 5850 is connected to the voltage V BG_B (be or voltage V BG_A ) is connected to the wiring that provides the first gate of the OS transistor 5850. The signal S F The second gate of OS transistor 5850 is connected to a wiring that provides Voltage V BG_B (or voltage V BG_A ) is connected to the wiring that provides

[0531] The operation of FIG. 38(A) will be explained using the timing chart of FIG. 38(B).

[0532] The voltage for controlling the threshold voltage of the OS transistor 5810 is determined by the signal applied to the input terminal IN. Before time T3 when the signal is switched to a high level, the second gate of OS transistor 5810 The signal S F is set to high level to turn on the OS transistor 5850. In this state, node N BG Voltage V for controlling the threshold voltage BG_B Give.

[0533] Node N BG is the voltage V BG_B After this, the OS transistor 5850 is turned off. The OS transistor 5850 has an extremely small off-state current and can be kept in an off state. and node N BG is set to a state close to floating, and then the node N BG to The maintained voltage V BG_B Therefore, the OS transistor 585 Voltage V applied to the second gate of BG_B The number of operations to give the voltage V BG_B Writing In exchange, the power consumption can be reduced.

[0534] In the circuit configurations of FIGS. 36B and 38A, the second transistor of the OS transistor 5810 We have shown a configuration in which the voltage applied to the gate is controlled externally, but we will also consider other configurations. For example, the voltage for controlling the threshold voltage may be set based on the signal applied to the input terminal IN. and provide it to the second gate of the OS transistor 5810. An example of a circuit configuration that can realize the above is shown in FIG.

[0535] In Figure 39(A), the input terminal IN and the OS transformer are connected in the circuit configuration shown in Figure 36(B). A CMOS inverter 5860 is provided between the first gate of the transistor 5810 and the second gate of the transistor 5810. The input terminal of the inverter 5860 is connected to the input terminal IN. The output terminal of 0 is connected to the second gate of OS transistor 5810.

[0536] The operation of FIG. 39(A) will be explained using the timing chart of FIG. 39(B). In the timing chart of 39(B), the signal waveform of the input terminal IN and the signal of the output terminal OUT waveform, the output waveform IN_B of the CMOS inverter 5860, and the OS transistor 581 0 (FET5810) change in threshold voltage.

[0537] The output waveform IN_B, which is the inverted signal of the signal applied to the input terminal IN, is 36(A) can be used as a signal to control the threshold voltage of the resistor 5810. As described in (a) to (c), the threshold voltage of the OS transistor 5810 can be controlled. For example, at time T4 in FIG. 39(B), the signal applied to the input terminal IN is at a high level. At this time, the output waveform IN_B is at a low level. Therefore, the OS transistor 5810 is in a state where it is difficult for current to flow. This allows the voltage at the output terminal OUT to drop sharply.

[0538] At time T5 in FIG. 39(B), the signal applied to the input terminal IN is at a low level. At this time, the OS transistor 5820 is turned off. Therefore, the OS transistor 5810 can be made to be in a state where current can easily flow. This allows the voltage at the output terminal OUT to rise sharply.

[0539] As described above, in the configuration of this embodiment, in the inverter having the OS transistor, The back gate voltage is switched according to the logic of the signal at the input terminal IN. By configuring the OS transistor as a gate, the threshold voltage of the OS transistor can be controlled. The threshold voltage of the OS transistor is controlled by the signal supplied to the output terminal OUT. It is also possible to reduce the through current between the wiring that supplies the power supply voltage. Therefore, it is possible to reduce power consumption.

[0540] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0541] (Embodiment 7) In this embodiment, a plurality of circuits each having the OS transistor described in the above embodiment are An example of a semiconductor device having such a structure will be described with reference to FIGS.

[0542] 40A is a block diagram of a semiconductor device 5900. The semiconductor device 5900 includes a power supply Circuit 5901, circuit 5902, voltage generating circuit 5903, circuit 5904, voltage generating circuit 59 05 and circuit 5906.

[0543] The power supply circuit 5901 supplies a reference voltage V ORG This is a circuit that generates a voltage V ORG teeth, Instead of a single voltage, multiple voltages may be used. Voltage V ORG is the outside of the semiconductor device 5900 The semiconductor device 5900 can be generated based on the voltage V0 given from the external Based on a single power supply voltage, the voltage V ORG Therefore, the semiconductor device 590 0 can operate without multiple external power supply voltages.

[0544] The circuits 5902, 5904, and 5906 are circuits that operate on different power supply voltages. For example, the power supply voltage of the circuit 5902 is V ORG and voltage V SS (V ORG >V SS ) and based on The power supply voltage for the circuit 5904 is V POG and voltage V SS (V POG >V ORG ) and the voltage applied by, for example, circuit 590 The power supply voltage of 6 is V ORG and voltage V SS and voltage V NEG (V ORG >V SS >V NE G ) is the voltage applied based on the voltage V SS is equal to the ground potential (GND). If the voltage is a potential, the number of types of voltages generated by the power supply circuit 5901 can be reduced.

[0545] The voltage generating circuit 5903 generates a voltage V POG The voltage generating circuit 5903 is a circuit that generates , the voltage V given by the power supply circuit 5901 ORG Based on the voltage V POG can be generated. Therefore, the semiconductor device 5900 having the circuit 5904 can be operated with a single power supply voltage given from the outside. It can operate based on

[0546] The voltage generating circuit 5905 generates a voltage V NEG The voltage generating circuit 5905 is a circuit that generates , the voltage V given by the power supply circuit 5901 ORG Based on the voltage V NEG can be generated. Therefore, the semiconductor device 5900 having the circuit 5906 can be operated with a single power supply voltage given from the outside. It can operate based on

[0547] Figure 40(B) shows the voltage V POG FIG. 40C shows an example of a circuit 5904 that operates in the 4 is an example of a waveform of a signal for operating the inverter 4.

[0548] 40B shows the transistor 5911. The gate of the transistor 5911 The signal given to is, for example, voltage V POG and voltage V SS The signal is generated based on When the transistor 5911 is in the conducting state, the voltage V POG , and when operating in a non-conducting state Voltage V SS It is generated based on the voltage V POG As shown in Figure 40(C), the voltage V ORG Therefore, the transistor 5911 has a source (S) and a drain (D). As a result, the circuit 5904 is less likely to malfunction. It can be a circuit.

[0549] Figure 40(D) ​​shows the voltage V NEG FIG. 40(E) shows an example of a circuit 5906 that operates in accordance with the 1 is an example of a waveform of a signal for operating the inverter 6.

[0550] FIG. 40D shows a transistor 5912 having a back gate. The signal applied to the gate of the stator 5912 is, for example, a voltage V ORG and voltage V SS Based on This signal is generated by turning on the transistor 5911 and generating a voltage V ORG , When in a non-conducting state, the voltage V SS Also, the transistor 5912 The signal applied to the back gate is voltage V NEG It is generated based on the voltage V NEG Figure 40 As shown in (E), the voltage V SS (GND). Therefore, transistor 5 The threshold voltage of 912 can be controlled to be shifted in the positive direction. This makes it possible to more reliably make the resistor 5912 non-conductive, and the source (S) and drain (D ) can be reduced. As a result, the malfunction of the circuit 5906 is reduced. In addition, the circuit can be designed to consume less power.

[0551] Furthermore, the voltage V NEG may be directly applied to the back gate of the transistor 5912. Alternatively, the voltage V ORG and voltage V NEG Based on this, the gate of the transistor 5912 is supplied with and applies the signal to the back gate of the transistor 5912. Good too.

[0552] Also, FIGS. 41(A) and (B) show modified examples of FIGS. 40(D) ​​and (E).

[0553] In the circuit diagram shown in FIG. 41(A), a control circuit is provided between a voltage generating circuit 5905 and a circuit 5906. A transistor 5922 whose conduction state can be controlled by a circuit 5921 is shown. The control circuit 5921 outputs a control signal to the OS transistor 5922. signal S BG is a signal that controls the conduction state of the transistor 5922. The transistors 5912A and 5912B in the device 6 are the same OS transistor as the transistor 5922. It is a transistor.

[0554] In the timing chart of FIG. 41(B), the control signal S BG The change in the potential of the transistor The potential state of the back gates of the sta- tors 5912A and 5912B is BG With the change in potential Control signal S BG When is high, transistor 5922 is in a conducting state, and Code N BG is the voltage V NEG Then, the control signal S BG When is low, the node N BG The transistor 5922 is an OS transistor. Therefore, the off-state current is small. BG is electrically floating However, once the voltage V NEG can be maintained.

[0555] FIG. 42A shows an example of a circuit configuration applicable to the voltage generating circuit 5903 described above. The voltage generating circuit 5903 shown in FIG. 42A includes diodes D1 to D5, a capacitor The five-stage charge pump includes C1 to C5 and an inverter INV. The signal CLK is applied to the capacitors C1 to C5 either directly or through an inverter INV. The power supply voltage of the inverter INV is V ORG and voltage V SS and is applied based on If the voltage is V, then by applying a clock signal CLK, the voltage V ORG Five times more positive voltage The voltage V POG In addition, the forward direction of the diodes D1 to D5 The voltage is set to 0 V. By changing the number of stages of the charge pump, the desired voltage V P OG can be obtained.

[0556] FIG. 42B shows an example of a circuit configuration applicable to the voltage generating circuit 5905 described above. The voltage generating circuit 5905 shown in FIG. 42B includes diodes D1 to D5, a capacitor The four-stage charge pump includes C1 to C5 and an inverter INV. The signal CLK is applied to the capacitors C1 to C5 either directly or through an inverter INV. The power supply voltage of the inverter INV is V ORG and voltage V SS and is applied based on Assuming that the voltage is V, applying a clock signal CLK will cause the SS to voltage V ORG The voltage V is stepped down to a negative voltage four times that of NEG You can get The forward voltage of the diodes D1 to D5 is set to 0V. By changing the number, the desired voltage V NEG can be obtained.

[0557] The circuit configuration of the voltage generating circuit 5903 described above is not limited to the configuration of the circuit diagram shown in FIG. Modifications of the voltage generating circuit 5903 are shown in FIGS. 43(A) to 43(C), 44(A), and 44(B). ) shown.

[0558] The voltage generating circuit 5903A shown in FIG. 43A includes transistors M1 to M10, a capacitor, The clock signal CLK is supplied to the inverters C11 to C14 and the inverter INV1. The voltage Vcc is applied directly to the gates of the transistors M1 to M10 or via an inverter INV1. By applying a clock signal CLK, the voltage V ORG is boosted to a positive voltage four times higher than the The voltage V POG By changing the number of stages, the desired voltage VPOG The voltage generating circuit 5903A shown in FIG. By using an OS transistor as M10, the off-state current can be reduced. Therefore, the leakage of the charge held in C14 can be suppressed. ORG Voltage from V POG It is possible to boost the voltage to

[0559] The voltage generating circuit 5903B shown in FIG. 43B includes transistors M11 to M14, The clock signal CLK is generated by: The voltage is applied to the gates of the transistors M11 to M14 directly or via an inverter INV2. By applying a clock signal CLK, the voltage V ORG rises to twice the positive voltage The applied voltage V POG The voltage generating circuit 5903B shown in FIG. By using OS transistors as the transistors M11 to M14, the off-state current can be reduced. This can suppress leakage of the charges stored in the capacitors C15 and C16. Voltage V ORG to voltage V POG It is possible to boost the voltage to

[0560] The voltage generating circuit 5903C shown in FIG. 43(C) includes an inductor I11 and a transistor M 15, diode D6, and capacitor C17. Transistor M15 is controlled The conduction state is controlled by the signal EN. ORG is boosted The applied voltage V POG The voltage generating circuit 5903C shown in FIG. Since the voltage is boosted using the inductor I11, the voltage can be boosted with high conversion efficiency. This can be done.

[0561] The voltage generating circuit 5903D shown in FIG. 44A is the same as the voltage generating circuit 5903 shown in FIG. The diodes D1 to D5 of 903 are connected to the diode-connected transistors M16 to M20. The voltage generating circuit 5903D shown in FIG. By using OS transistors as the transistors M16 to M20, the off-state current can be reduced. This can suppress leakage of the charges held in C1 to C5. ORG from Voltage V POG It is possible to boost the voltage to

[0562] The voltage generating circuit 5903E shown in FIG. 44(B) is the same as the voltage generating circuit 5903 shown in FIG. The transistors M16 to M20 of 903D are connected to the transistor M21 having a back gate. The voltage generating circuit 5903E shown in FIG. Since the same voltage as the gate can be applied to the back gate, the current flowing through the transistor Therefore, the flow rate can be increased efficiently. ORG to voltage V POG Boost to This can be achieved.

[0563] The modified example of the voltage generating circuit 5903 is also applicable to the voltage generating circuit 5905 shown in FIG. The circuit diagram configuration in this case is shown in Figs. 45(A) to (C), 46(A), and The voltage generating circuit 5905A shown in FIG. 45(A) provides a clock signal CLK. By doing so, the voltage V SS to voltage V ORG The voltage V is stepped down to a negative voltage three times that ofNEG can be obtained. Also, the voltage generation circuit 5905B shown in FIG. 45(B) can obtain a voltage V by applying a clock signal SS from voltage V ORG to a negative voltage that is twice the voltage V voltage V NEG .

[0564] In the voltage generation circuits 5905A to 59 05E shown in FIGS. 45(A) to (C) and FIGS. 46(A) and (B), it corresponds to a configuration in which the voltage applied to each wiring is changed or the arrangement of elements is changed in the voltage generation circuits 590 3A to 5903E shown in FIGS. 43(A) to (C) and FIGS. 44(A) and (B). The voltage generation circuits 5905A to 5905E shown in FIGS. 45(A) to (C) and FIGS. 46(A) and (B) can efficiently step down the voltage from voltage V to voltage V in the same manner as the voltage generation circuits 5903A to 5903E and can achieve voltage step-down from voltage V SS to voltage V NEG .

[0565] As described above, in the configuration of the present embodiment, the voltage required for the circuits of the semiconductor device can be generated internally. Therefore, the semiconductor device can reduce the types of power supply voltages supplied from the outside .

[0566] The configuration shown in the present embodiment can be used in appropriate combination with the configurations shown in other embodiments .

[0567] [[ID=4*]](Embodiment 8) In the present embodiment, an example of a CPU including a semiconductor device such as a transistor according to an aspect of the present invention and the above-described storage device will be described .

[0568] <Configuration of CPU> ​The semiconductor device 5400 shown in FIG. 47 includes a CPU core 5401, a power management unit 5402, and a The power management unit 5421 has a power management circuit 5422. , a power controller 5402, and a power switch 5403. 22 is a cache 5404 having a cache memory, a bus interface (BUS I / F) 5405 and Debug I / F 5406 The CPU core 5401 is connected to a data bus 5423, a control device 5407, a PC (program RAM counter) 5408, pipeline register 5409, pipeline register 541 0, ALU (Arithmetic logic unit) 5411, and register field The CPU core 5401 and the peripheral circuits 5404, such as the cache 5404, Data is exchanged with 22 via a data bus 5423.

[0569] The semiconductor device (cell) includes many components, including a power controller 5402 and a control device 5407. In particular, it can be applied to logic circuits that can be configured using standard cells. As a result, a small semiconductor device 5400 can be provided. In addition, a semiconductor device 5400 that can reduce power consumption can be provided. In this way, it is possible to provide a semiconductor device 5400 capable of improving the operating speed. A semiconductor device 5400 capable of reducing fluctuations can be provided.

[0570] The semiconductor device (cell) includes a p-channel Si transistor and an oxide semiconductor layer according to the previous embodiment. A transistor including a compound semiconductor (preferably an oxide containing In, Ga, and Zn) in a channel forming region. By using a transistor and applying the semiconductor device (cell) to the semiconductor device 5400, It is possible to provide a semiconductor device 5400 of this type. In addition, a semiconductor device 5400 capable of improving the operating speed can be provided. In particular, by using only p-channel Si transistors, manufacturing costs can be reduced. It can be suppressed.

[0571] The control unit 5407 includes a PC 5408, a pipeline register 5409, and a pipeline register 5410, ALU 5411, register file 5412, cache 5404, bus interface 5405, debug interface 5406, and power controller By controlling the overall operation of the 5402, the input application and other programs can be It has the function of decoding and executing instructions contained in RAM.

[0572] The ALU 5411 has the function of performing various arithmetic operations such as arithmetic operations and logical operations.

[0573] The cache 5404 has a function of temporarily storing frequently used data. C5408 is a register that stores the address of the next instruction to be executed. Although not shown in FIG. 47, the cache 5404 has a function for controlling the operation of the cache memory. A cache controller is provided to control the cache.

[0574] The pipeline register 5409 is a register that has the function of temporarily storing instruction data. is.

[0575] The register file 5412 has a plurality of registers including general-purpose registers. Data read from memory or data obtained as a result of ALU5411 calculation , etc. can be stored.

[0576] The pipeline register 5410 stores data used in the arithmetic processing of the ALU 5411, or A register with a function to temporarily store data obtained as a result of the ALU5411 calculation process. It's Jista.

[0577] The bus interface 5405 is a bus interface between the semiconductor device 5400 and a device external to the semiconductor device 5400. It functions as a data path between various devices. The switch 5406 is a circuit for inputting instructions for controlling debugging into the semiconductor device 5400. It functions as a signal path.

[0578] The power switch 5403 is a power controller 5402 included in the semiconductor device 5400. It has the function of controlling the supply of power supply voltage to various circuits other than the above. Each circuit belongs to a different power domain, and various circuits that belong to the same power domain are The power switch 5403 controls whether or not the power supply voltage is supplied. The roller 5402 has the function of controlling the operation of the power switch 5403 .

[0579] The semiconductor device 5400 having the above configuration is capable of performing power gating. The flow of the power gating operation will be described using an example.

[0580] First, the CPU core 5401 determines the timing to stop the supply of power voltage by the power controller. Then, the CPU core 5401 sends the power Then, the semiconductor device 54 The various registers and cache 5404 included in 00 start saving data. The power supply voltage to various circuits other than the power controller 5402 included in the semiconductor device 5400 is The supply of pressure is stopped by the power switch 5403. An interrupt signal is then sent to the power By inputting the signal to the controller 5402, the power supply to the various circuits of the semiconductor device 5400 is The supply of voltage is started. Note that a counter is provided in the power controller 5402, The timing at which the supply of power voltage starts is determined by the counter, regardless of the input of an interrupt signal. Then, various registers and cache 5404 determine the data. The controller 5407 then resumes executing instructions.

[0581] Such power gating can be applied to the entire processor or to one of the components of the processor. It can be done in one or more logic circuits. This allows for fine-grained reduction of power consumption in space and time. Reductions can be made.

[0582] When power gating is performed, the information held by the CPU core 5401 and the peripheral circuit 5422 It is preferable to be able to evacuate the data in a short time. This allows the power to be turned on and off in a short time. This results in a greater power saving effect.

[0583] In order to save the information held by the CPU core 5401 and the peripheral circuit 5422 in a short time, It is preferable that the flip-flop circuit can save data within the circuit (backup possible) (This is called a flip-flop circuit.) Also, the SRAM cell can save data within the cell. (called backup-capable SRAM cell) is preferred. The drop circuit and SRAM cell are made of oxide semiconductor (preferably oxide containing In, Ga, and Zn). It is preferable to have a transistor having a channel forming region made of a metal oxide. The low off-state current of the transistor allows it to be used in backup flip-flop circuits and S RAM cells can retain information for long periods without power. By having a high switching speed, it is possible to use a backup flip-flop circuit or RAM cells may be capable of short-term data storage and restoration.

[0584] An example of a flip-flop circuit capable of backing up will be described with reference to FIG.

[0585] The semiconductor device 5500 shown in FIG. 48 is an example of a flip-flop circuit capable of backing up. The semiconductor device 5500 includes a first memory circuit 5501, a second memory circuit 5502, and The semiconductor device 5500 includes a third memory circuit 5503 and a read circuit 5504. The potential difference between potential V1 and potential V2 is supplied as the power supply voltage. One is a high level and the other is a low level. A configuration example of the semiconductor device 5500 will be described below, taking the case where V2 is at a high level as an example. Let's say.

[0586] The first memory circuit 5501 stores the data during a period in which a power supply voltage is supplied to the semiconductor device 5500. When a signal D containing data is input, the data is held. During a period in which a power supply voltage is supplied to the semiconductor device 5500, the first memory circuit 5501 A signal Q including the stored data is output from the first memory circuit 550. 1 holds data during the period when power supply voltage is not supplied to the semiconductor device 5500. That is, the first memory circuit 5501 is called a volatile memory circuit. This can be done.

[0587] The second memory circuit 5502 reads the data stored in the first memory circuit 5501. The third memory circuit 5503 has a function of storing (or saving) data in the second memory circuit. The function of reading and storing (or saving) the data held in the circuit 5502 The read circuit 5504 has the second memory circuit 5502 or the third memory circuit 550 The data held in the memory 3 is read out and stored in the first memory circuit 5501 (or restored). It has the function of

[0588] In particular, the third memory circuit 5503 stores the power supply voltage during a period when the power supply voltage is not supplied to the semiconductor device 5500. In this case, the data held in the second memory circuit 5502 is read and stored (also It has the function of (e.g., to move or evacuate).

[0589] As shown in FIG. 48, the second memory circuit 5502 includes a transistor 5512 and a capacitor 551. The third memory circuit 5503 includes a transistor 5513 and a transistor 551 The read circuit 5504 includes a transistor 5510 and a capacitor 5520. The transistor 5518, the transistor 5509, and the transistor 5517 are included. .

[0590] The transistor 5512 stores a charge according to the data stored in the first memory circuit 5501. The transistor 5512 has a function of charging and discharging the first memory cell. Charge according to data held in the circuit 5501 is quickly charged to the capacitor element 5519. Specifically, the transistor 5512 is preferably made of crystalline silicon. Silicon (preferably polycrystalline silicon, more preferably single crystal silicon) is placed in the channel forming region. It is desirable to include

[0591] The transistor 5513 is turned on or off depending on the charge held in the capacitor 5519. The transistor 5515 is selected to be in a non-conducting state when the transistor 5513 is in a conducting state. When the potential of the wiring 5544 is high, the capacitor 5520 is charged and discharged. It is preferable that the off-state current of the transistor 5515 be extremely small. The transistor 5515 is made of an oxide semiconductor (preferably an oxide semiconductor containing In, Ga, and Zn). It is desirable to include a material in the channel forming region.

[0592] To specifically explain the connection relationship of each element, the source and drain of the transistor 5512 One end is connected to the first memory circuit 5501. The other drain is connected to one electrode of a capacitor 5519, the gate of a transistor 5513, and and the gate of the transistor 5518. The other electrode of the capacitor 5519 is One of the source and drain of the transistor 5513 is connected to a wiring 5542. The other of the source and the drain of the transistor 5513 is connected to a wiring 5544. The transistor 55 is connected to one of the source and drain of the transistor 55. The other of the source and drain of the capacitor 5520 is connected to one electrode of the capacitor 5520 and the other of the drain and the source of the transistor 5520. The other electrode of the capacitor 5520 is connected to the gate of the capacitor 5510. One of the source and drain of the transistor 5510 is connected to a wiring 5541. The other of the source and drain of the transistor 5510 is connected to the The source and drain of transistor 5518 are connected to one of the two terminals. The other of the drain and source is connected to one of the source and drain of a transistor 5509. The other of the source and drain of the transistor 5509 is connected to the source of the transistor 5517. The source and drain of the transistor 5 are connected to the first memory circuit 5501. The other of the source and drain of 517 is connected to a wiring 5540. In this case, the gate of the transistor 5509 is connected to the gate of the transistor 5517. However, the gate of transistor 5509 is not necessarily the same as the gate of transistor 5517. It does not have to be connected.

[0593] The transistor described in the above embodiment can be used as the transistor 5515. Since the off-state current of the transistor 5515 is small, the semiconductor device 5500 can be powered on for a long period of time. The transistor 5515 has good switching characteristics. To be advantageous, the semiconductor device 5500 can perform high-speed backup and recovery. Cut.

[0594] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0595] (Embodiment 9) In this embodiment, an imaging device including a transistor according to one embodiment of the present invention will be described. An example will be described.

[0596] <Imaging device> An imaging device according to one aspect of the present invention will be described below.

[0597] 49(A) is a plan view showing an example of an imaging device 2200 according to one embodiment of the present invention. The device 2200 includes a pixel section 2210 and a peripheral circuit 2260 for driving the pixel section 2210. 22, a peripheral circuit 2270, a peripheral circuit 2280, and a peripheral circuit 2290. 210 is a matrix of p rows and q columns (p and q are integers of 2 or more). The peripheral circuit 2260, the peripheral circuit 2270, the peripheral circuit 2280, and the peripheral circuit 2211 are The side circuits 2290 are connected to the plurality of pixels 2211, respectively, and drive the plurality of pixels 2211. In this specification, the peripheral circuit 2260, The peripheral circuits 2270, 2280, and 2290 are all referred to as "peripherals." For example, the peripheral circuit 2260 is one of the peripheral circuits. It can be said to be a club.

[0598] The imaging device 2200 preferably includes a light source 2291. It is possible to emit an outgoing light P1.

[0599] The peripheral circuits include at least a logic circuit, a switch, a buffer, an amplifier, or a converter. The peripheral circuits may be formed on the same substrate as the pixel portion 2210. Also, semiconductor devices such as IC chips may be used for part or all of the peripheral circuits. The peripheral circuits include a peripheral circuit 2260, a peripheral circuit 2270, a peripheral circuit 2280, and a peripheral circuit One or more of the paths 2290 may be omitted.

[0600] As shown in FIG. 49(B), in a pixel section 2210 included in an imaging device 2200, The pixels 2211 may be arranged at an angle. This allows the pixel interval (pitch) in the vertical and column directions to be shortened. 200, the quality of the image can be further improved.

[0601] <Pixel configuration example 1> One pixel 2211 of the imaging device 2200 is composed of multiple sub-pixels 2212, each of which Each sub-pixel 2212 is combined with a filter (color filter) that transmits light in a specific wavelength range. By combining these, it is possible to obtain information for realizing a color image display.

[0602] FIG. 50(A) is a plan view showing an example of a pixel 2211 for acquiring a color image. The pixel 2211 shown in FIG. 50(A) has a color filter that transmits light in the red (R) wavelength range. The subpixel 2212 (hereinafter also referred to as "subpixel 2212R") has a wavelength range of green (G). A subpixel 2212 (hereinafter referred to as "subpixel 2212G") is provided with a color filter that transmits light of ") and blue (B) wavelength range light-transmitting color filters. The subpixel 2212 has a photodiode 2212 (hereinafter also referred to as "subpixel 2212B"). It can function as a sensor.

[0603] The subpixels 2212 (subpixels 2212R, 2212G, and 2212B) are Electrically connected to wiring 2231, wiring 2247, wiring 2248, wiring 2249, and wiring 2250 The subpixels 2212R, 2212G, and 2212B are connected to each other. Each of them is connected to an independent wiring 2253. The wiring 2248 and the wiring 2249 connected to the eye pixel 2211 are respectively connected to the wiring 224 8[n] and wiring 2249[n]. The connected wiring 2253 is described as wiring 2253[m]. , the wiring 2253 connected to the sub-pixel 2212R of the pixel 2211 in the m-th column is connected to the wiring 225 3[m]R, the wiring 2253 connected to the subpixel 2212G is called a wiring 2253[m]G, and The wiring 2253 connected to the subpixel 2212B is indicated as wiring 2253[m]B. The element 2212 is electrically connected to the peripheral circuitry via the wiring.

[0604] In addition, the imaging device 2200 has color filters 2211 that transmit light in the same wavelength range. The sub-pixels 2212 provided with the filters are electrically connected to each other via switches. In Figure 50(B), there are n rows (n is an integer between 1 and p) and m columns (m is an integer between 1 and q). ) and the sub-pixel 2212 of the pixel 2211 arranged in the n+ An example of connection of sub-pixels 2212 included in a pixel 2211 arranged in 1 row and m columns is shown in FIG. ), the sub-pixel 2212R arranged in the nth row and the mth column and the sub-pixel 2212R arranged in the n+1th row and the mth column are The element 2212R is connected via the switch 2201. The subpixel 2212G and the subpixel 2212G arranged in the n+1th row and the mth column are connected to the switch 2202. In addition, the sub-pixel 2212B arranged in the nth row and the mth column is connected via a The sub-pixel 2212B arranged at the center is connected via the switch 2203.

[0605] The color filters used for the subpixel 2212 are limited to red (R), green (G), and blue (B). color filters that transmit cyan (C), yellow (Y) and magenta (M) light respectively. A single pixel 2211 may have sub-pixels for detecting light in three different wavelength ranges. By providing the element 2212, a full color image can be obtained.

[0606] Alternatively, color filters that transmit red (R), green (G), and blue (B) light are installed. In addition to the sub-pixel 2212, a color filter that transmits yellow (Y) light is provided. A pixel 2211 with a sub-pixel 2212 may be used. Alternatively, cyan (C), Subpixel 221 provided with a color filter that transmits yellow (Y) and magenta (M) light In addition to the pixel 2, the pixel 2212 has a color filter that transmits blue (B) light. A pixel 2211 that detects light in four different wavelength ranges may be used. By providing the sub-pixel 2212, the color reproducibility of the acquired image can be further improved. Cut.

[0607] Also, for example, in FIG. 50(A), a sub-pixel 2212 detects light in the red wavelength range, and a sub-pixel 2213 detects light in the green wavelength range. a subpixel 2212 for detecting light in the wavelength range, and a subpixel 2212 for detecting light in the blue wavelength range. The pixel ratio (or light receiving area ratio) does not have to be 1:1:1. For example, A Bayer array with a light receiving area ratio of red:green:blue=1:2:1 may also be used. The pixel number ratio (light receiving area ratio) may be red:green:blue=1:6:1.

[0608] The number of sub-pixels 2212 provided in the pixel 2211 may be one, but it is preferable that there are two or more. For example, by providing two or more sub-pixels 2212 that detect light in the same wavelength range, redundancy can be increased. This can improve the reliability of the imaging device 2200.

[0609] In addition, IR (IR: Infrared) filters absorb or reflect visible light and transmit infrared light. By using a filter, it is possible to realize an imaging device 2200 that detects infrared light.

[0610] In addition, an ND (Neutral Density) filter (neutral density filter) is used. This prevents output saturation that occurs when a large amount of light is incident on the photoelectric conversion element (light receiving element). By combining ND filters with different light reduction levels, This allows for a wider dynamic range of the device.

[0611] In addition to the above-mentioned filter, a lens may be provided in the pixel 2211. An example of the arrangement of the pixel 2211, the filter 2254, and the lens 2255 will be described using a cross-sectional view of the pixel 2211. By providing the lens 2255, the photoelectric conversion element can efficiently receive incident light. Specifically, as shown in FIG. 51(A), a lens 2255 formed in a pixel 2211 , filter 2254 (filter 2254R, filter 2254G and filter 2254 B), and light 2256 is incident on the photoelectric conversion element 2220 through the pixel circuit 2230, etc. The structure can be such that:

[0612] However, as shown in the area surrounded by the dashed line, a part of the light 2256 indicated by the arrow is connected to the wiring 225 Therefore, as shown in Figure 51(B), A lens 2255 and a filter 2254 are arranged on the photoelectric conversion element 2220 side. The element 2220 preferably has a structure that allows it to efficiently receive light 2256. By making light 2256 incident on the photoelectric conversion element 2220 from the side, an imaging device with high detection sensitivity can be obtained. 2200 can be provided.

[0613] As the photoelectric conversion element 2220 shown in FIG. 51, a pn-type junction or a pin-type junction is formed. Alternatively, a photoelectric conversion element may be used.

[0614] The photoelectric conversion element 2220 is made of a material having a function of absorbing radiation and generating electric charges. The material having the function of absorbing radiation and generating charges may be: Selenium, lead iodide, mercury iodide, gallium arsenide, cadmium telluride, cadmium zinc alloy There is money etc.

[0615] For example, if selenium is used for the photoelectric conversion element 2220, in addition to visible light, ultraviolet light, and infrared light, Photoelectric conversion element 2 that has a light absorption coefficient over a wide wavelength range, such as X-rays and gamma rays 220 can be achieved.

[0616] Here, one pixel 2211 included in the imaging device 2200 is a sub-pixel 2212 shown in FIG. In addition, it may have a subpixel 2212 with a first filter.

[0617] <Pixel configuration example 2> In the following, a transistor using silicon and a transistor using an oxide semiconductor will be described. An example of forming a pixel using the transistors will be described. A transistor similar to that used in the first embodiment can be used.

[0618] Fig. 52 is a cross-sectional view of an element constituting an imaging device. The imaging device shown in Fig. 52 is a silicon A transistor 2351 and a transistor 2352 using silicon provided on a substrate 2300 A transistor 2352 using an oxide semiconductor and a transistor 2353, and a photodiode 2360 provided on the silicon substrate 2300. The cathode 2362 of each transistor and photodiode 2360 is connected to various The photodiode 236 is electrically connected to the electrode 2370 and the wiring 2371. The anode 2361 of the 0 is electrically connected to the plug 2370 through the low resistance region 2363. Has.

[0619] The imaging device also includes a transistor 2351 and a photodiode 2352 provided on a silicon substrate 2300. A layer 2310 having a diode 2360 and a wiring 2371 provided in contact with the layer 2310. a layer 2320 having a transistor 2352 and a transistor A layer 2330 having a transistor 2353, a wiring 2372 and a and a layer 2340 having wiring 2373.

[0620] In the example of the cross section of FIG. 52, the transistor 2351 is formed on the silicon substrate 2300. The light receiving surface of the photodiode 2360 is located on the opposite side to the surface on which the light receiving surface is formed. This configuration ensures an optical path without being affected by various transistors and wiring. Therefore, it is possible to form pixels with a high aperture ratio. The light receiving surface of 2360 may be the same as the surface on which the transistor 2351 is formed.

[0621] In addition, when a pixel is configured using only transistors using an oxide semiconductor, the layer 23 The layer 2310 may be a layer including a transistor using an oxide semiconductor. Alternatively, the pixel may be formed using only a transistor including an oxide semiconductor, without using the transistors.

[0622] The silicon substrate 2300 may be an SOI substrate. Instead of 0, germanium, silicon germanium, silicon carbide, gallium arsenide, arsenic Substrates with aluminum gallium, indium phosphide, gallium nitride or organic semiconductors can also be used.

[0623] Here, a layer 2310 having a transistor 2351 and a photodiode 2360; The layer 2330 having the transistor 2352 and the transistor 2353 is insulated from the However, the position of the insulator 2380 is not limited. An insulator 2379 is provided under the insulator 2380, and an insulator 2381 is provided on the insulator 2380. can be done.

[0624] The conductors 2390a to 2390b are inserted into the openings in the insulators 2379 to 2381. 390e are provided. The conductor 2390c ​​functions as a plug and a wiring. The conductor 2390d functions as the back gate of the transistor 2352. It functions as a back gate.

[0625] The hydrogen in the insulator provided near the channel formation region of the transistor 2351 is This has the effect of terminating dangling bonds and improving the reliability of the transistor 2351. On the other hand, an insulator provided near the transistor 2352 and the transistor 2353 The hydrogen in the oxide semiconductor is one of the factors that generate carriers in the oxide semiconductor. This may cause a decrease in the reliability of the resistor 2352 and the transistor 2353. Therefore, an oxide semiconductor is used as the upper layer of a transistor using a silicon-based semiconductor. When stacking transistors, an insulator having a function of blocking hydrogen is provided between the transistors. It is preferable to provide an insulator 2380. It is possible to confine hydrogen below the insulator 2380. Therefore, the reliability of the transistor 2351 can be improved. This prevents hydrogen from diffusing from the lower layer to the upper layer of the insulator 2380. The reliability of the resistor 2352 and the transistor 2353 can be improved. Furthermore, a conductor 2390a, a conductor 2390b, and a conductor 2390e are formed. This also prevents hydrogen from diffusing into the upper layer through the via holes formed in the insulator 2380. This improves the reliability of transistors such as transistor 2352 and transistor 2353. It can be done.

[0626] In the cross-sectional view of FIG. 52, the photodiode 2360 provided in the layer 2310 and the The transistor 330 can be formed so as to overlap with the transistor 330. In other words, the resolution of the imaging device can be increased.

[0627] Alternatively, the imaging device may be partially or entirely curved. Therefore, it is possible to reduce the surface curvature and astigmatism. For example, the number of lenses required for aberration correction can be reduced. This allows for the realization of smaller and lighter electronic devices that use imaging devices. It also improves the quality of the captured image.

[0628] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0629] (Embodiment 10) In this embodiment, a semiconductor wafer, a chip, and an electronic component according to one aspect of the present invention are We will explain about this.

[0630] <Semiconductor wafers and chips> FIG. 53(A) shows a top view of the substrate 5711 before the dicing process is performed. The substrate 5711 may be, for example, a semiconductor substrate (also called a "semiconductor wafer"). A plurality of circuit regions 5712 are provided on the substrate 5711. 5712 is a semiconductor device according to one embodiment of the present invention, a CPU, an RF tag, or an image A sensor or the like may be provided.

[0631] The plurality of circuit regions 5712 are each surrounded by an isolation region 5713. A separation line (also called a "dicing line") 5714 is set at a position overlapping with 13. The substrate 5711 is cut along the separation line 5714 to form a chip including a circuit region 5712. The chip 5715 can be cut out from the substrate 5711. A large diagram is shown.

[0632] A conductive layer or a semiconductor layer may be provided in the separation region 5713. By providing a semiconductor layer, ESD that may occur during the dicing process can be mitigated, and the dicing process In general, the dicing process involves cooling the substrate, Pure carbon dioxide gas is dissolved in the material to reduce the resistivity, for the purpose of removing debris and preventing static electricity. This is done while water is flowing through the cutting area. This reduces the amount of pure water used, thereby reducing the production costs of semiconductor devices. Furthermore, the productivity of the semiconductor device can be improved.

[0633] The semiconductor layer provided in the separation region 5713 has a band gap of 2.5 eV or more and 4.2 e It is preferable to use a material with an energy of 2.7 eV or less, preferably 2.7 eV or more and 3.5 eV or less. Such materials allow the accumulated charge to be slowly discharged, thus reducing the risk of ESD damage. This suppresses the sudden movement of charges due to electrostatic discharge, making it less likely that electrostatic breakdown will occur.

[0634] <Electronic components> An example of applying the chip 5715 to an electronic component will be described with reference to FIG. The electronic components are also called semiconductor packages or IC packages. There are multiple standards and names depending on the direction of insertion and the shape of the terminal.

[0635] The electronic component is a semiconductor device according to the above embodiment that is used in an assembly process (post-process). The device is completed by combining components other than the semiconductor device.

[0636] The post-process will be explained using the flowchart shown in Figure 54(A). After the element substrate having the semiconductor device shown in the above embodiment is completed, the back surface ( The back surface (the surface on which semiconductor devices are not formed) is ground (step Grinding the substrate to make it thinner reduces warping of the substrate and improves the electrical conductivity. Sub-components can be made smaller.

[0637] Next, a "dicing process" is performed to separate the element substrate into multiple chips (chips 5715). (Step S5722). Then, the separated chips are individually picked up and attached to the lead frames. Then, a "die bonding process" is carried out to bond the die onto the die (step S5723). The bonding between the chip and the lead frame in the packaging process is done using resin or tape. The appropriate method is selected depending on the product, such as bonding. The chip may be bonded onto a transposer substrate.

[0638] Next, the leads of the lead frame and the electrodes on the chip are electrically connected with thin metal wires. Then, a "wire bonding process" is carried out to connect the thin metal wires (step S5724). Silver wire or gold wire can be used for wire bonding. Bonding or wedge bonding can be used.

[0639] The wire-bonded chip is sealed with epoxy resin in the "sealing process (module)". The "encapsulation process" is then carried out (step S5725). The chip is filled with resin, and the circuitry built into the chip and the wires connecting the chip and leads are machined. It can protect from external mechanical forces and also prevents deterioration of characteristics (reduced reliability) due to moisture and dust. can be reduced.

[0640] Next, a "lead plating process" is carried out to plate the leads of the lead frame (step The plating process prevents the leads from rusting and allows for later mounting on a printed circuit board. This allows for more reliable soldering during the process. The leads are then cut and shaped. Then, a "molding process" is carried out (step S5727).

[0641] Next, a "marking process" is carried out, in which printing (marking) is applied to the surface of the package. (Step S5728) Then, an "inspection worker" checks whether the external appearance is good or not, whether there is any malfunction, etc. After passing through the "process" (step S5729), the electronic component is completed.

[0642] A perspective view of the completed electronic component is shown in Figure 54(B). As an example of a product, a perspective view of a QFP (Quad Flat Package) is shown below. The electronic component 5750 shown in FIG. 54(B) includes a lead 5755 and a semiconductor device 575 3 is shown. The semiconductor device 5753 may be any of the semiconductor devices shown in the above embodiments. can be used.

[0643] The electronic component 5750 shown in FIG. 54(B) is mounted on, for example, a printed circuit board 5752. A plurality of electronic components 5750 such as the above are combined, and each is mounted on a printed circuit board 5752. By electrically connecting them, a substrate (mounting substrate 5754) on which electronic components are mounted is completed. The completed mounting board 5754 is used in electronic devices and the like.

[0644] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiments. can.

[0645] (Embodiment 11) In this embodiment, an electronic device including a transistor according to one embodiment of the present invention will be described. We will explain about this.

[0646] <Electronic equipment> A semiconductor device according to one aspect of the present invention includes a display device, a personal computer, and a recording medium. Image playback devices (typically DVD: Digital Versatile Disc) (Devices having a display that can play back recording media such as DVDs and display the images) In addition, electronic devices in which the semiconductor device according to one embodiment of the present invention can be used are Mobile phones, portable game consoles, portable data terminals, e-book terminals, video cameras , cameras such as digital still cameras, goggle-type displays (head-mounted displays) Ray), navigation systems, sound reproduction devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, printer-combined machines, automated teller machines Examples of such electronic devices include ATMs and vending machines. vinegar.

[0647] FIG. 55(A) shows a portable game machine, which includes a housing 1901, a housing 1902, a display unit 1903, Display unit 1904, microphone 1905, speaker 1906, operation keys 1907, The portable game machine shown in Figure 55(A) has two tables. The portable game machine has a display unit 1903 and a display unit 1904. , but is not limited to this.

[0648] FIG. 55(B) shows a portable data terminal, which includes a first housing 1911, a second housing 1912, a first display The first display unit 1913, the second display unit 1914, the connection unit 1915, the operation keys 1916, etc. The display unit 1913 is provided on the first housing 1911, and the second display unit 1914 is provided on the second housing 1912. The first housing 1911 and the second housing 1912 are connected to each other by a connecting portion 1912. 915, and the angle between the first housing 1911 and the second housing 1912 is The image on the first display unit 1913 can be changed by the connection unit 1915. 5, the angle between the first housing 1911 and the second housing 1912 is changed. In addition, at least one of the first display unit 1913 and the second display unit 1914 may be configured as follows. On the other hand, a display device with a function as a position input device may be used. The function as a position input device can ...

Claims

1. An oxide semiconductor film containing indium, an element M, and zinc, the element M includes one or more of Al, Ga, Y, or Sn, the oxide semiconductor film includes a first region and a second region in which indium is present at a higher concentration than in the first region; The second region is an oxide semiconductor film scattered within the first region.

2. An oxide semiconductor film containing indium, an element M, and zinc, the element M includes one or more of Al, Ga, Y, or Sn, the oxide semiconductor film includes a first region and a second region in which indium is present at a higher concentration than in the first region; the second region is contained in the first region of the oxide semiconductor film.

3. In claim 1 or claim 2, the second region contains indium at a concentration 1.1 times or more and 10 times or less than that of the first region.

Images