Integrated circuit structures having pre-spacer deposition cut gates and associated defect test structures

Abstract

To provide integrated circuit structures having pre-spacer-deposition cut gates and associated defect test structures.SOLUTION: In a gate-all-around integrated circuit structure, a starting structure 100 includes a first fin 104A having multiple horizontal nanowires 108 and a second fin 104B having multiple horizontal nanowires 108, on a substrate 102. The first and second fins may be positioned above respective cavities 111 over corresponding sub-fin portions of the substrate, with the sub-fin portions isolated by shallow trench isolation (STI) structures. Each of the first and second fins includes an intervening sacrificial material 110 between the multiple horizontal nanowires. A gate line 112, such as a sacrificial polysilicon gate line, is provided over the first and second fins. The gate line includes a hard mask 114 thereon. Between the first and second fins, one of the gate lines has a narrow polycut 116 formed as a trench.SELECTED DRAWING: Figure 1A

Description

[Background technology]

[0001] Over the past few decades, the scaling of features in integrated circuits has been the driving force behind the ever-growing semiconductor industry. Scaling to smaller and smaller features allows for an increased density of functional units on the limited real estate of a semiconductor chip. For example, reducing the size of transistors allows for a larger number of memory or logic devices to be integrated onto a chip, resulting in an increase in the capabilities of manufactured products. However, this push toward ever greater capacity is not without challenges. The need to optimize the performance of each device is becoming increasingly important.

[0002] In the fabrication of integrated circuit devices, multi-gate transistors, such as tri-gate transistors, have become more widely used as device dimensions continue to shrink. In conventional processes, tri-gate transistors are typically fabricated on either bulk silicon or silicon-on-insulator substrates. In some cases, bulk silicon substrates are preferred due to the lower cost and less complex tri-gate fabrication process they enable. In another aspect, maintaining improved mobility and short-channel control as microelectronic device dimensions scale below the 10-nanometer (nm) node presents challenges for device fabrication. Nanowires, used to fabricate devices, offer improved short-channel control.

[0003] However, multi-gate and nanowire transistors have not been scaled without consequences. As the dimensions of these building blocks of microelectronic circuits decrease, and as the number of very large building blocks fabricated in a given area increases, the constraints on the lithographic processes used to pattern these building blocks become greater. In particular, there can be a trade-off between the minimum dimensions (critical dimensions) of patterned features in the semiconductor stack and the spacing between such features. [Brief explanation of the drawings]

[0004] [Figure 1A] 1A-1C illustrate cross-sectional views of various steps in a method of fabricating a gate-all-around integrated circuit structure using a cut-gate approach before spacer deposition, according to one embodiment of the present disclosure.

[0005] [Figure 1B] 1A-1C illustrate cross-sectional views of various steps in a method of fabricating a gate-all-around integrated circuit structure using a cut-gate approach before spacer deposition, according to one embodiment of the present disclosure.

[0006] [Figure 1C] FIG. 1 is a schematic diagram of a layout for detecting an open trench contact, according to one embodiment of the present disclosure.

[0007] [Figure 1D] FIG. 1 is a schematic diagram of a layout for detecting trench contact shorts, according to one embodiment of the present disclosure.

[0008] [Figure 1E] 10 shows a bright portion of a structure under voltage contrast testing according to one embodiment of the present disclosure.

[0009] [Figure 2A]1A-1C illustrate cross-sectional views of various steps in a method of fabricating a gate-all-around integrated circuit structure using a cut-gate approach before spacer deposition, according to one embodiment of the present disclosure. [Figure 2B] 1A-1C illustrate cross-sectional views of various steps in a method of fabricating a gate-all-around integrated circuit structure using a cut-gate approach before spacer deposition, according to one embodiment of the present disclosure. [Figure 2C] 1A-1C illustrate cross-sectional views of various steps in a method of fabricating a gate-all-around integrated circuit structure using a cut-gate approach before spacer deposition, according to one embodiment of the present disclosure. [Figure 2D] 1A-1C illustrate cross-sectional views of various steps in a method of fabricating a gate-all-around integrated circuit structure using a cut-gate approach before spacer deposition, according to one embodiment of the present disclosure. [Figure 2E] 1A-1C illustrate cross-sectional views of various steps in a method of fabricating a gate-all-around integrated circuit structure using a cut-gate approach before spacer deposition, according to one embodiment of the present disclosure. [Figure 2F] 1A-1C illustrate cross-sectional views of various steps in a method of fabricating a gate-all-around integrated circuit structure using a cut-gate approach before spacer deposition, according to one embodiment of the present disclosure. [Figure 2G] 1A-1C illustrate cross-sectional views of various steps in a method of fabricating a gate-all-around integrated circuit structure using a cut-gate approach before spacer deposition, according to one embodiment of the present disclosure.

[0010] [Figure 3A] 1A-1C show plan views illustrating various steps in a method for patterning a fin with multiple gate spacings to form a local isolation structure. [Figure 3B] 1A-1C show plan views illustrating various steps in a method for patterning a fin with multiple gate spacings to form a local isolation structure.

[0011] [Figure 3C]10A-10C show plan views illustrating various steps in a method for patterning a fin with a single gate spacing to form a local isolation structure according to another embodiment of the present disclosure. [Figure 3D] 10A-10C show plan views illustrating various steps in a method for patterning a fin with a single gate spacing to form a local isolation structure according to another embodiment of the present disclosure. [Figure 3E] 10A-10C show plan views illustrating various steps in a method for patterning a fin with a single gate spacing to form a local isolation structure according to another embodiment of the present disclosure. [Figure 3F] 10A-10C show plan views illustrating various steps in a method for patterning a fin with a single gate spacing to form a local isolation structure according to another embodiment of the present disclosure.

[0012] [Figure 3G] 1A-1C show plan views illustrating various steps in a method for patterning a fin with a single gate spacing to form a local isolation structure at a select gate line cut location according to an embodiment of the present disclosure. [Figure 3H] 1A-1C show plan views illustrating various steps in a method for patterning a fin with a single gate spacing to form a local isolation structure at a select gate line cut location, according to an embodiment of the present disclosure.

[0013] [Figure 3I] 1A-1C show schematic diagrams of an exemplary mask division of a method for fabricating a gate-all-around integrated circuit structure using a cut-gate approach before spacer deposition, according to one embodiment of the present disclosure.

[0014] [Figure 4A] 1A-1D illustrate cross-sectional views of various steps in a method of fabricating a gate-all-around integrated circuit structure according to one embodiment of the present disclosure. [Figure 4B]1A-1D illustrate cross-sectional views of various steps in a method of fabricating a gate-all-around integrated circuit structure according to one embodiment of the present disclosure. [Figure 4C] 1A-1D illustrate cross-sectional views of various steps in a method of fabricating a gate-all-around integrated circuit structure according to one embodiment of the present disclosure. [Figure 4D] 1A-1D illustrate cross-sectional views of various steps in a method of fabricating a gate-all-around integrated circuit structure according to one embodiment of the present disclosure. [Figure 4E] 1A-1D illustrate cross-sectional views of various steps in a method of fabricating a gate-all-around integrated circuit structure according to one embodiment of the present disclosure. [Figure 4F] 1A-1D illustrate cross-sectional views of various steps in a method of fabricating a gate-all-around integrated circuit structure according to one embodiment of the present disclosure. [Figure 4G] 1A-1D illustrate cross-sectional views of various steps in a method of fabricating a gate-all-around integrated circuit structure according to one embodiment of the present disclosure. [Figure 4H] 1A-1D illustrate cross-sectional views of various steps in a method of fabricating a gate-all-around integrated circuit structure according to one embodiment of the present disclosure. [Figure 4I] 1A-1D illustrate cross-sectional views of various steps in a method of fabricating a gate-all-around integrated circuit structure according to one embodiment of the present disclosure. [Figure 4J] 1A-1D illustrate cross-sectional views of various steps in a method of fabricating a gate-all-around integrated circuit structure according to one embodiment of the present disclosure.

[0015] [Figure 5] 1 illustrates a cross-sectional view of a non-planar integrated circuit structure cut along a gate line according to one embodiment of the present disclosure.

[0016] [Figure 6] 1A-1C show cross-sectional views cut through the nanowires and fins of an endcap-free architecture (left side (a)) versus a self-aligned gate endcap (SAGE) architecture (right side (b)), according to one embodiment of the present disclosure.

[0017] [Figure 7] 1A-1C illustrate cross-sectional views illustrating various steps in a method for fabricating a self-aligned gate endcap (SAGE) structure with a gate-all-around device according to one embodiment of the present disclosure.

[0018] [Figure 8A] 1 shows a three-dimensional cross-sectional view of a nanowire-based integrated circuit structure according to one embodiment of the present disclosure.

[0019] [Figure 8B] 8B illustrates a cross-sectional source or drain view of the nanowire-based integrated circuit structure of FIG. 8A taken along the a-a' axis, according to one embodiment of the present disclosure.

[0020] [Figure 8C] FIG. 8B shows a cross-sectional channel view of the nanowire-based integrated circuit structure of FIG. 8A taken along the bb' axis, according to one embodiment of the present disclosure.

[0021] [Figure 9] 1 illustrates a computing device according to an implementation of an embodiment of the present disclosure.

[0022] [Figure 10] 1 illustrates an interposer including one or more embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0023] An integrated circuit structure having a cut gate and associated defect test structure before spacer deposition is described. In the following description, numerous specific details are set forth, such as specific integration and material regimes, to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to those skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as integrated circuit design layouts, have not been described in detail in order to avoid unnecessarily obscuring embodiments of the present disclosure. Furthermore, it should be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

[0024] Certain terms may also be used in the following description for reference purposes only and are not intended to be limiting. For example, terms such as "upper," "lower," "upper," and "lower" refer to directions in the drawings to which reference is made. Terms such as "front," "back," "rear," and "side" describe the orientation and / or location of parts of a component within any consistent frame of reference that becomes apparent by reference to the text describing the component under consideration and the associated drawings. Such terms may include the words specifically mentioned above, derivatives thereof, and words of similar import.

[0025] Embodiments described herein may relate to front-end (FEOL) semiconductor processing and construction. FEOL is the first part of integrated circuit (IC) manufacturing, where individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned into a semiconductor substrate or layer. FEOL generally encompasses everything up to but not including the deposition of metal interconnect layers. After the last FEOL step, the result typically is a wafer with isolated (e.g., free of any wires) transistors.

[0026] The embodiments described herein may relate to back-end (BEOL) semiconductor processes and structures. BEOL is the second part of IC manufacturing where individual devices (e.g., transistors, capacitors, resistors, etc.) are interconnected with wiring on the wafer, e.g., one or more metallization layers. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-package connections. In the BEOL part of the manufacturing stage, contacts (pads), interconnect wires, vias, and dielectric structures are formed. In modern IC processes, more than 10 metal layers can be added in the BEOL.

[0027] The embodiments described below may be applied to FEOL processes and structures, BEOL processes and structures, or both FEOL and BEOL processes and structures. In particular, while example processing schemes may be shown using the context of FEOL processing, such approaches may also be applied to BEOL processing. Similarly, while example processing schemes may be shown using the context of BEOL processing, such approaches may also be applied to FEOL processing.

[0028] One or more embodiments described herein relate to gate-all-around devices fabricated using poly(gate) cuts made prior to deposition of gate spacers, e.g., for gates on top of a stack of nanowires. It should be understood that references to nanowires may refer to nanowires, or nanoribbons, or nanosheets, unless otherwise indicated. One or more embodiments described herein relate to FinFET devices fabricated using poly(gate) cuts made prior to deposition of gate spacers, e.g., for gates on top of a fin. One or more embodiments relate to voltage contrast (VC) structure designs and methods for detecting shorts in trench contact (TCN) STSs.

[0029] To provide context, creating a very narrow poly(gate) cut (PCT) later in the process flow, for example after gate spacer deposition, can be very challenging. The narrow and wide PCTs may need to be split and performed in separate steps in the process flow. Also, separating two gates with a narrow poly(gate) cut (PCT) has proven to be much easier than other approaches being investigated.

[0030] According to one or more embodiments of the present disclosure that address the problems outlined above, an approach is described for performing narrow PCT cuts after hardmask (HM) patterning or immediately after poly (PLY) etch, e.g., an etch used to pattern gate lines, such as dummy polysilicon gate lines ultimately used in a replacement gate process. In one embodiment, a spacer deposition step, e.g., gate spacer deposition, is used to bridge the PCT end-to-end (ETE) after spacer deposition. This approach may simplify the process flow and enable PCT suitable for very small PCT cuts. In one embodiment, narrow PCT is patterned during PLY etch, enabling large-scale scaling that can achieve very small PCT critical dimensions (CD); wide PCT plugs can still be patterned simultaneously with subsequent fin trim isolation (FTI) or through-fin isolation approaches.

[0031] Advantages of implementing the approach described herein include that it may be more cost-effective to add a PCT spacer pre-etch and then perform a standard process flow. This process is independent of the ply profile, so isotropic Si removal can be used to ensure no residual Si remains on the gate. Also, there may be no gate height loss due to the narrow poly cut process.

[0032] According to one or more embodiments of the present disclosure, the PCT mask division results in any narrow cuts, and then any wider PCT cuts result in an FTI mask. As an example, FIG. 1A illustrates cross-sectional views of various steps in a method for fabricating a gate-all-around integrated circuit structure using a cut-gate approach before spacer deposition, according to one embodiment of the present disclosure. FIG. 1B illustrates cross-sectional views of various steps in a method for fabricating a gate-all-around integrated circuit structure using a cut-gate approach before spacer deposition, according to one embodiment of the present disclosure. While described with reference to stacks of nanowires (or nanoribbons, or nanosheets), it should be understood that semiconductor fins may also be encompassed, for example, by embodiments in which the stacks of nanowires are replaced with semiconductor fins. It should also be understood that the resulting structure may be fabricated with associated defect test structures, such as those described below with reference to FIGS. 1C-1E.

[0033] Referring to part (i) of FIG. 1A , the starting structure 100 includes a first fin 104A including a plurality of horizontal nanowires 108 (which may be nanoribbons) and a second fin 104B including a plurality of horizontal nanowires 108 (which may be nanoribbons) on a substrate 102. The first fin 104A and the second fin 104B may overlie respective cavities 111 on respective sub-fin portions of the substrate 102, the sub-fin portions being isolated by shallow trench isolation (STI) structures. The first fin 104A and the second fin 104B may each include an intervening sacrificial material 110 between the plurality of horizontal nanowires 108. Gate lines 112, such as sacrificial polysilicon gate lines, overlie the first fin 104A and the second fin 104B. The gate lines 112 may include a hard mask 114 thereon, as shown. A narrow poly cut 116 is formed as a trench in one of the gate lines 112 between the first fin 104A and the second fin 104B. Referring to portion (ii) of FIG. 1A , structure 120 includes a spacer material formed on starting structure 100. The spacer material includes first and second portions 122A on and along the sidewalls of gate line 112 and a third portion 122B within narrow poly cut 116, where the third portion is continuous with the first and second portions. It should be understood that subsequent etching of the spacer material can be performed to retain the third portion 122B within narrow poly cut 116, while leaving portion 122A only along the sidewalls of gate line 112. The third portion 122B within narrow poly cut 116 may be referred to as a narrow gate plug or a narrow poly cut plug.

[0034] Referring to portion (i) of FIG. 1B , structure 150 shows structure 120 of FIG. 1A after processing to provide trench contact or dummy trench contact structures 156 between gate lines 112. A patterned mask 152 is formed over the structure, and a wide poly cut 154 is formed as a trench in one of the gate lines 112. In one embodiment, wide poly cut 154 is formed adjacent to narrow gate plug or narrow poly cut plug 122B in the same gate line 112. Referring to portion (ii) of FIG. 1B , structure 160 is formed by depositing a dielectric material over structure 150 to form wide gate plug or wide poly cut plug 162. In one embodiment, wide gate plug or wide poly cut plug 162 contacts narrow gate plug or narrow poly cut plug 122B as shown.

[0035] In another aspect, a voltage contrast (VC) structure design and method for detecting shorts in trench contact (TCN) STSs is described.

[0036] To provide context, self-sealing poly-cut (PCT) architectures, where the PCT (poly cut or gate plug) is patterned before poly etch and naturally plugged by gate dielectric spacer deposition, are exposed to trench contact (TCN) STS short defects (through the orthogonal gate direction (OGD) seam where the spacer merges). These shorts can be extremely difficult to detect inline by conventional means, and thus data variability can delay and limit process development.

[0037] Previous approaches have proven inadequate for successfully detecting such failures, which are buried or thin defects after contact metallization, in-line. For such buried defects, processes must rely on end-of-line signals. Several destructive quick turn monitors (QTMs) have been developed that etch plugs after contact metallization to attempt to determine whether there is a metal layer that blocks the etch. However, such QTMs can be difficult to design and destructive, thus requiring the use of replicate wafer silicon resources and can be unreliable because correlations cannot be established for sorting.

[0038] According to one embodiment of the present disclosure, voltage contrast (VC) is used to determine whether contact metal from one TCN is shorted to another TCN in the OGD direction through a gate plug PCT that is then grounded to the substrate. Under the correct electric field, grounded contacts (e.g., conductive trench contacts tied to ground) appear bright under VC after metallization. Floating or isolated contacts (e.g., electrically isolated conductive trench contacts) appear dark / gray. Dense arrays of floating TCNs (isolated TCNs) next to TCNs landing on diffusion (grounded TCNs) with shorts that can be isolated by the intervening PCT will fail, as will large-area testing to identify this.

[0039] Benefits of implementing the embodiments described herein can include reduced time to yield learning time because in-line detection of difficult problems eliminates the need to run potential skews to end-of-line for resolution. VC testing is also non-destructive and can be performed on production wafers that can be run to end-of-line, thereby minimizing cost and establishing correlation to known yield signals at end-of-line.

[0040] Detectability of the embodiments described herein can include observation of VC structures that are large arrays spanning tens / hundreds of microns in a periodic arrangement of alternating floating TCNs (isolated dummy TCNs) and ground TCNs (p-diffused / pTAP TCNs) with one or more PCT plugs between them in the parallel gate direction (PGD). In one embodiment, the gates and TCNs are dummy and do not connect to routing metal layers or power rails. In one embodiment, contact vias land on each floating TCN segment, allowing for detection after via formation. In one embodiment, such structures can be detected by reverse engineering by polishing down to the vias and front-end stack and observing planar TEM images.

[0041] To provide further context, in voltage contrast mode, an E-beam tool can distinguish between grounded and floating features. Under the correct polarity, grounded features appear bright, while floating ones appear darker. This is useful for designing custom structures that can be used to detect electrical opens and shorts. This technique is particularly useful for detecting buried or hidden defects that are otherwise inaccessible for optical metrology detection. Specifically for TCN STS shorts, a dense array of structures is designed with the floating TCN immediately adjacent to the grounded TCN in the PGD, isolated by a PCT (gate plug) between them. The process corner is stressed by using the maximum CD of the PCT plug. In one embodiment, only one PCT is used per floating TCN / ground TCN pair. This can enable faster defect isolation by isolating the exact PCT plug failure location that leads to the TCN STS defect. This scheme can be repeated on large arrays. The gate can be floating and not connected to the ViaG. In one embodiment, there is a ViaT landing on each individual floating / dummy TCN segment that allows for the detection of these shorts in either the contact layer or the via layer.

[0042] As an example, FIG. 1C is a schematic diagram of a layout for detecting an open trench contact, according to one embodiment of the present disclosure.

[0043] 1C, layout 170 includes gate line 171, P diffusion 172, N diffusion 173, isolation trench contact 174A, trench contact 174B, and poly cut location 175 (which may also be a fin trim isolation location). In one embodiment, center trench contact (TCN) 174A, isolated by poly cut (PCT) plugs on either side, is the TCN under test.

[0044] As an example, FIG. 1D is a schematic diagram of a layout for detecting trench contact shorts, according to one embodiment of the present disclosure.

[0045] 1D, layout 180 includes an N diffusion structure 182 (such as an NMOS fin or nanowire stack), a P diffusion / P-tap structure 184 (such as a PMOS fin or nanowire stack), a gate / poly line 186 with a poly cut (PCT) location 187 therebetween, a trench contact 188, and a trench contact via 190. A short circuit path 189 is shown passing through PCT location 187, which in one embodiment is a defect.

[0046] As an example, FIG. 1E shows a bright portion of a structure under voltage contrast testing, according to one embodiment of the present disclosure.

[0047] Referring to Figure 1E, structure 195 shows a portion of an array of alternating trench contact structures and gate lines that have been made to appear "bright" using voltage contrast measurements. Section 197 highlights locations where trench contacts are shorted through polycut (PCT) locations. The open locations in Figure 1E are areas of the array that remain "dark" during voltage contrast measurements. In one embodiment, the bright locations are portions of the array that are electrically "floating."

[0048] In another aspect, as an exemplary process flow, FIGS. 2A-2G illustrate cross-sectional views of various steps in a method for fabricating a gate-all-around integrated circuit structure using a cut-gate approach before spacer deposition, according to one embodiment of the present disclosure. At each step, a source / drain slope (S / D slope) view, a gate slope view, and a through-fin trim isolation fin (through-FTI fin) view are provided. While described with respect to stacks of nanowires (or nanoribbons, or nanosheets), it should be understood that semiconductor fins may also be encompassed, for example, by embodiments in which the stacks of nanowires are replaced with semiconductor fins. It should also be understood that the resulting structure may be fabricated with an associated defect test structure, such as that described above with respect to FIGS. 1C-1E.

[0049] 2A , starting structure 200 includes a first fin 204A including a plurality of horizontal nanowires 208 (which may be nanoribbons) and a second fin 204B including a plurality of horizontal nanowires 208 (which may be nanoribbons) on a substrate 202. The first fin 204A and the second fin 204B may overlie respective cavities 211 on respective sub-fin portions of the substrate 202, with the sub-fin portions being isolated by shallow trench isolation (STI) structures. The first fin 204A and the second fin 204B may each include an intervening sacrificial material 210 between the plurality of horizontal nanowires 208. Gate lines 212, such as sacrificial polysilicon gate lines, overlie the first fin 204A and the second fin 204B. The gate lines 212 may include a hard mask 214 thereon, as shown. A narrow poly cut 216 is formed as a trench in one of the gate lines 212 between the first fin 204A and the second fin 204B.

[0050] 2B, a spacer material is formed over the starting structure 200. The spacer material 218 includes a portion 218A on and along the sidewall of the gate line 212 and a second portion 218B within the narrow poly cut 216.

[0051] 2C, a helmet layer 220 is formed over the structure of FIG. 2B. An etch of the spacer material is then performed to preserve second portion 218B in narrow poly cut 216, while leaving portion 218A' of portion 218A remaining only along the sidewall of gate line 212. Second portion 218B in narrow poly cut 216 may be referred to as a narrow gate plug or narrow poly cut plug, as shown in FIG. 2D.

[0052] Referring to FIG. 2E, epitaxial source or drain structures 223 are formed, trench contact or dummy trench contact structures 222 are formed between gate lines 212, and a planarization step is performed to expose hard mask 214 and narrow gate or narrow poly cut plugs 218B. It should be understood that the poly cut process may be completed at this stage. In such a case, subsequent processing may then include replacement gate and nanowire release processes. Alternatively, a wider cut may be formed later. In such an example, a first patterned mask 224 and a second patterned mask 226 are then formed over the structure of FIG. 2E, as shown in FIG. 2F.

[0053] 2G, a wide poly cut is formed as a trench in one of the gate lines 212 (e.g., as described above in connection with FIG. 1B), a dielectric material is deposited to form a wide gate plug or wide poly cut plug 228, and then planarization and mask removal is performed. In one embodiment, the wide gate plug or wide poly cut plug 228 contacts the narrow gate plug or narrow poly cut plug 218B as shown. It should be understood that subsequent processing may then include replacement gate and nanowire release processing.

[0054] 2E , according to one embodiment of the present disclosure, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is located on the first vertical arrangement of horizontal nanowires, and a second gate stack is located on the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. The integrated circuit structure also includes a dielectric structure having a first portion forming a gate spacer along a sidewall of the first gate stack, a second portion forming a gate spacer along a sidewall of the second gate stack, and a third portion completely filling the gap, the third portion being continuous with the first and second portions.

[0055] Referring again to FIG. 2G , according to one embodiment of the present disclosure, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A gate stack is located on the first vertical arrangement of horizontal nanowires, and a gate plug is located on the second vertical arrangement of horizontal nanowires. An end of the gate plug is spaced apart from an end of the gate stack by a gap. The integrated circuit structure also includes a dielectric structure having a first portion forming a gate spacer along a sidewall of the gate stack, a second portion forming a spacer along a sidewall of the gate plug, and a third portion completely filling the gap, the third portion being continuous with the first and second portions. In one embodiment, a seam is located between the third portion of the dielectric structure and the gate plug.

[0056] In another aspect, fin trim isolation (FTI) and single gate spacing are described for isolated fins. Non-planar transistors utilizing fins of semiconductor material protruding from the substrate surface utilize gate electrodes that cover two, three, or even all sides of the fin (i.e., dual-gate, tri-gate, nanowire transistors). Source and drain regions are then typically formed on either side of the gate electrode, either within the fin or as regrown portions of the fin. A gap or space may be formed between two adjacent fins to separate the source or drain region of a first non-planar transistor from the source or drain region of an adjacent second non-planar transistor. Such a separation gap generally requires some type of masked etch. Once separated, gate stacks are then typically patterned above the individual fins, again using some type of masked etch (e.g., a line etch or an open etch, depending on the particular implementation).

[0057] One potential problem with the fin isolation techniques described above is that the gate is not self-aligned with the edge of the fin; alignment of the gate stack pattern with the semiconductor fin pattern depends on the overlay of these two patterns. As a result, lithographic overlay tolerances are added to the dimensions of the semiconductor fin and isolation gap, requiring the fin to be longer and the isolation gap to be larger than would otherwise be required for a given level of transistor functionality. Therefore, device architectures and fabrication techniques that reduce such excess dimensions offer significant advantages in transistor density.

[0058] Another potential problem with the fin isolation techniques described above is that the stress in the semiconductor fin, which is desirable for improving carrier mobility, can be lost from the channel region of the transistor if too much of the fin surface remains free during fabrication, allowing for relaxation of fin strain. Thus, device architectures and fabrication techniques that maintain higher levels of the desired fin stress would provide advantageous improvements in non-planar transistor performance.

[0059] Described herein are architectures and techniques for through-gate fin isolation according to one embodiment of the present disclosure. In the illustrated exemplary embodiment, non-planar transistors in a microelectronic device, such as an integrated circuit (IC), are isolated from one another in a manner that is self-aligned with the transistor's gate electrode. While embodiments of the present disclosure apply to virtually any IC that utilizes non-planar transistors, exemplary ICs include, but are not limited to, microprocessor cores including logic and memory (SRAM) portions, RFICs (e.g., radio frequency ICs including digital baseband and analog front-end modules), and power ICs.

[0060] In an embodiment, two ends of adjacent semiconductor fins are electrically isolated from each other by an isolation region positioned relative to the gate electrode using only one patterning mask level. In one embodiment, a single mask is utilized to form a plurality of sacrificial placeholder stripes with a fixed pitch, with a first subset of the placeholder stripes defining the location or dimensions of the isolation region, while a second subset of the placeholder stripes defining the location or dimensions of the gate electrode. In a particular embodiment, the first subset of the placeholder stripes are removed and isolation cuts are formed in the semiconductor fin in the openings resulting from the removal of the first subset, while the second subset of the placeholder stripes are ultimately replaced with a non-sacrificial gate electrode stack. Because the subset of placeholders utilized to replace the gate electrode are utilized to form the isolation region, the method and resulting architecture are referred to herein as “through-gate” isolation. One or more through-gate isolation embodiments described herein may enable, for example, higher transistor density and higher levels of advantageous transistor channel stress.

[0061] Isolation defined after the placement or definition of the gate electrode allows for greater transistor density because the pitch of the fin isolation dimensions and placement can be perfectly matched to the gate electrode pitch, resulting in both the gate electrode and isolation regions being integer multiples of the minimum feature pitch of a single masking level. In further embodiments in which the semiconductor fin has a lattice mismatch with the substrate on which the fin is placed, a greater degree of strain is maintained by defining isolation after the placement or definition of the gate electrode. For such embodiments, other features of the transistor (such as the gate electrode and added source or drain material) formed before the edge of the fin is defined help to mechanically maintain the fin strain after the isolation cuts are made in the fin.

[0062] To provide further context, transistor scaling can benefit from denser packing of cells within a chip. Currently, most cells are isolated from their surroundings by two or more dummy gates with buried fins. Cells are isolated by etching fins under these two or more dummy gates that connect one cell to another. Scaling could be significantly beneficial if the number of dummy gates isolating neighboring cells could be reduced from two or more to one. As explained above, one solution requires two or more dummy gates. The fins under the two or more dummy gates are etched during fin patterning. A potential problem with such an approach is that the dummy gates consume space on the chip that could be used for cells. In one embodiment, the approach described herein allows for the isolation of neighboring cells using only a single dummy gate.

[0063] In one embodiment, the fin trim isolation approach is implemented as a self-aligned patterning scheme, where the fin under a single gate is etched away. Thus, neighboring cells can be isolated by a single dummy gate. Advantages of such an approach may include saving space on the chip and enabling more computing power for a given area. The approach may also enable fin trimming to be performed at sub-fin pitch distances.

[0064] For comparison purposes, FIGS. 3A and 3B show plan views illustrating various steps in a method for patterning a fin with multiple gate spacing to form a local isolation structure.

[0065] 3A, a plurality of fins 302 are shown having lengths along a first direction 304. A grid 306 having spaces 307 therebetween and defining locations for the eventual formation of a plurality of gate lines is shown along a second direction 308 orthogonal to the first direction 304.

[0066] 3B , portions of the plurality of fins 302 are cut (e.g., removed by an etching process) to leave fins 310 with cuts 312 therein. Thus, the isolation structures ultimately formed at the cuts 312 have dimensions larger than a single gate line, e.g., the dimensions of three gate lines 306. Thus, the gate structures ultimately formed along the locations of the gate lines 306 will be formed at least partially on top of the isolation structures formed at the cuts 312. As such, the cuts 312 are relatively wide fin cuts.

[0067] 3C-3F show plan views illustrating various steps in a method for patterning a fin with a single gate spacing to form a localized isolation structure according to another embodiment of the present disclosure.

[0068] 3C , a method of fabricating an integrated circuit structure includes forming a plurality of fins 322, each of which has a longest dimension along a first direction 324. A plurality of gate structures 326 overlie the plurality of fins 322, each of which has a longest dimension along a second direction 328 that is orthogonal to the first direction 324. In one embodiment, the gate structures 326 are sacrificial or dummy gate lines fabricated, for example, from polycrystalline silicon. In one embodiment, the plurality of fins 322 are silicon fins and are continuous with a portion of an underlying silicon substrate.

[0069] Referring to FIG. 3D, a dielectric material structure 330 is formed between adjacent ones of the plurality of gate structures 326 .

[0070] 3E , a portion 332 of one of the gate structures 326 has been removed to expose a portion 334 of each of the fins 322. In one embodiment, removing the portion 332 of the one of the gate structures 326 includes using a lithography window 336 that is wider than a width 338 of the portion 332 of the one of the gate structures 326.

[0071] 3F , the exposed portion 334 of each of the multiple fins 322 is removed to form a cut region 340. In one embodiment, the exposed portion 334 of each of the multiple fins 322 is removed using a dry or plasma etching process. In one embodiment, removing the exposed portion 334 of each of the multiple fins 322 includes etching to a depth that is less than the height of the multiple fins 322. In one such embodiment, the depth is greater than the depth of the source or drain regions in the multiple fins 322. In one embodiment, the depth is greater than the depth of the active portions of the multiple fins 322 to provide an isolation margin. In one embodiment, the exposed portion 334 of each of the multiple fins 322 is removed without etching or substantially without etching the source or drain regions (e.g., epitaxial source or drain regions) of the multiple fins 322. In one such embodiment, the exposed portion 334 of each of the multiple fins 322 is removed without laterally etching or substantially without laterally etching the source or drain regions (e.g., epitaxial source or drain regions) of the multiple fins 322. In one embodiment, the cut regions 340, for example at the location of the removed portions 334 of each of the plurality of fins 322, are eventually filled with an insulating layer to form a "poly cut" or "plug" structure.

[0072] In one embodiment, the process of Figures 3C-3F can be used in or with a pre-spacer deposition cut gate approach, such as that described in connection with Figures 1A, 1B, and 2A-2G, and fabricated with an associated defect test structure, such as that described in connection with Figures 1C-1E.

[0073] In another aspect, there may be a relationship between the locations where gate line cuts (poly cuts) are made and the locations where fin trim isolation (FTI) local fin cuts are made. In one embodiment, FTI local fin cuts are made only at locations where poly cuts are made. However, in one such embodiment, FTI cuts are not necessarily made at all locations where poly cuts are made.

[0074] 3G and 3H show plan views illustrating various steps in a method for patterning a fin with a single gate spacing to form a local isolation structure at a select gate line cut location according to an embodiment of the present disclosure.

[0075] 3G, a method of fabricating an integrated circuit structure includes forming a plurality of fins 352, each fin of the plurality of fins 352 having a longest dimension along a first direction 354. A plurality of gate structures 356 overlie the plurality of fins 352, each gate structure of the gate structures 356 having a longest dimension along a second direction 358 that is orthogonal to the first direction 354. In one embodiment, the gate structures 356 are sacrificial or dummy gate lines fabricated, for example, from polycrystalline silicon. In one embodiment, the plurality of fins 352 are silicon fins and are continuous with a portion of an underlying silicon substrate.

[0076] Referring again to FIG. 3G , a dielectric material structure 360 ​​is formed between adjacent ones of the plurality of gate structures 356. Two portions 362 and 363 of the plurality of gate structures 356 are removed to expose a respective portion of the plurality of fins 352. In one embodiment, removing portions 362 and 363 of the two gate structures 356 includes using a lithography window wider than the width of each of portions 362 and 363 of the gate structures 356. The exposed portion of each of the plurality of fins 352 at location 362 is removed to form a cut region 370. In one embodiment, the exposed portion of each of the plurality of fins 352 is removed using a dry or plasma etching process. However, the exposed portion of each of the plurality of fins 352 at location 363 is masked from removal. In one embodiment, regions 362 / 370 both represent a poly cut and an FTI local fin cut. However, location 363 represents only a poly cut. Referring to FIG. 3H, the poly cut and FTI local fin cut locations 362 / 370 and the poly cut location 363 are filled with an insulating structure 380, such as a dielectric plug, or "poly cut," or "plug" structure.

[0077] In one embodiment, the process of Figures 3G-3H can be used in or with a pre-spacer deposition cut gate approach, such as that described in connection with Figures 1A, 1B, and 2A-2G, and fabricated with an associated defect test structure, such as that described in connection with Figures 1C-1E.

[0078] FIG. 3I shows an exemplary mask division schematic of a method for fabricating a gate-all-around integrated circuit structure using a cut-gate approach before spacer deposition, according to one embodiment of the present disclosure.

[0079] Referring to Figure 3I, mask 390 includes wide PCT features 391 between structures 392. Mask 393 includes narrow PCT features 394 (e.g., pre-spacer features) between structures 395. Mask 396 includes PCT / FTI features 397 between structures 398. In one embodiment, the mask of Figure 3I is used in a cut-gate approach before spacer deposition, such as that described in connection with Figures 1A, 1B, and 2A-2G.

[0080] It should be understood that the embodiments described herein may include other implementations, such as nanowires and / or nanoribbons having various widths, thicknesses, and / or materials, including, but not limited to, Si and SiGe. For example, III-V materials may be used.

[0081] It should be understood that in certain embodiments, the nanowires or nanoribbons, or the sacrificial intervening layer, may be composed of silicon. As used throughout, silicon layer may be used to describe a silicon material composed of a substantial amount, if not all, of silicon. However, it should be understood that forming virtually 100% pure Si can be difficult and therefore may contain small percentages of carbon, germanium, or tin. Such impurities may be present as unavoidable impurities or components during Si deposition, or may "contaminate" the Si upon diffusion during post-deposition processing. Therefore, embodiments described herein with respect to silicon layers may include silicon layers containing relatively small amounts of "impurity" levels of non-Si atoms or species, such as Ge, C, or Sn. It should be understood that the silicon layers described herein may be undoped or may be doped with dopant atoms, such as boron, phosphorus, or arsenic.

[0082] It should be understood that in certain embodiments, the nanowires or nanoribbons, or the sacrificial intervening layer, may be composed of silicon germanium. As used throughout, a silicon germanium layer may be used to describe a silicon germanium material composed of a substantial portion of both silicon and germanium, such as at least 5% of both. In some embodiments, the amount of germanium is greater than the amount of silicon. In certain embodiments, the silicon germanium layer comprises about 60% germanium and about 40% silicon (Si 40 Ge 60 In other embodiments, the amount of silicon is greater than the amount of germanium. In a particular embodiment, the silicon germanium layer comprises about 30% germanium and about 70% silicon (Si 70 Ge 30 ). It should be understood that forming virtually 100% pure silicon germanium (commonly referred to as SiGe) can be difficult and therefore may contain small percentages of carbon or tin. Such impurities may be present as unavoidable impurities or components during SiGe deposition, or may "contaminate" the SiGe upon diffusion during post-deposition processing. Therefore, embodiments described herein with respect to silicon germanium layers may include silicon germanium layers containing relatively small amounts of "impurity" levels of non-Ge and non-Si atoms or species, such as carbon or tin. It should be understood that the silicon germanium layers described herein may be undoped or may be doped with dopant atoms, such as boron, phosphorus, or arsenic.

[0083] The following describes various devices and processing schemes that may be used to fabricate devices that can be integrated with cut gates before spacer deposition and fabricated with associated defect test structures, such as those described in connection with FIGS. 1C-1E . It should be understood that exemplary embodiments may not require all of the features described or may include more than the features described. For example, nanowire release processing may be performed through replacement gate trenches. Examples of such release processes are described below. Additionally, in yet another aspect, backend (BE) interconnect scaling can result in lower performance and higher manufacturing costs due to patterning complexity. The embodiments described herein may be implemented to enable integration of front and backside interconnects for nanowire transistors. The embodiments described herein may provide an approach to achieving a relatively wide interconnect pitch. The result may be improved product performance and reduced patterning costs. The embodiments may be implemented to enable robust functioning of scaled nanowire or nanoribbon transistors with low power and high performance.

[0084] One or more embodiments described herein are directional dual epitaxial (EPI) connections for nanowire or nanoribbon transistors using partial source or drain (SD) and asymmetric trench contact (TCN) depths. In one embodiment, an integrated circuit structure is fabricated by forming a source-drain opening of a nanowire / nanoribbon transistor that is partially filled with SD epitaxy. The remainder of the opening is filled with a conductive material. Deep trench formation on one of the source or drain sides allows for direct contact with a backside interconnect level.

[0085] As an exemplary process flow for fabricating gate-all-around devices of a gate-all-around integrated circuit structure, FIGS. 4A-4J illustrate cross-sectional views of various steps in a method for fabricating a gate-all-around integrated circuit structure according to one embodiment of the present disclosure.

[0086] 4A , a method for fabricating an integrated circuit structure includes forming a starting stack including alternating sacrificial layers 404 and nanowires 406 on a fin 402, such as a silicon fin. The nanowires 406 may be referred to as a vertical arrangement of nanowires. As shown, a protective cap 408 may be formed on top of the alternating sacrificial layers 404 and nanowires 406. As also shown, a relaxed buffer layer 452 and a defect correction layer 450 may be formed below the alternating sacrificial layers 404 and nanowires 406.

[0087] 4B, a gate stack 410 is formed on the vertical arrangement of horizontal nanowires 406. A portion of the vertical arrangement of horizontal nanowires 406 is then released by removing a portion of the sacrificial layer 404 to provide a recessed sacrificial layer 404 and a cavity 412, as shown in FIG.

[0088] 4C may be fabricated to completion without first performing the deep etch and asymmetric contact processes described below. In either case (e.g., with or without the asymmetric contact processes), in one embodiment, the fabrication process includes using a process scheme that provides a gate-all-around integrated circuit structure with epitaxial nubs that may be vertically discrete source or drain structures.

[0089] 4D, top gate spacers 414 are formed on the sidewalls of the gate structure 410. Cavity spacers 416 are formed in the cavity 412 below the top gate spacers 414. Optionally, a deep trench contact etch is then performed to form trenches 418 and to form recessed nanowires 406′. As shown, a patterned relaxed buffer layer 452′ and a patterned defect correction layer 450′ may also be present.

[0090] 4E, a sacrificial material 420 is then formed in the trench 418. In other process schemes, an isolated trench bottom or a silicon trench bottom may be used.

[0091] 4F, a first epitaxial source or drain structure (e.g., left feature 422) is formed at a first end of the vertical arrangement of horizontal nanowire 406′. A second epitaxial source or drain structure (e.g., right feature 422) is formed at a second end of the vertical arrangement of horizontal nanowire 406′. In one embodiment, the epitaxial source or drain structure 422 as shown is a vertically discrete source or drain structure and may be referred to as an epitaxial nub.

[0092] An inter-layer dielectric (ILD) material 424 is then formed on the side of the gate electrode 410 and adjacent to the source or drain structure 422, as shown in Figure 4G. Referring to Figure 4H, a replacement gate process is used to form a permanent gate dielectric 428 and a permanent gate electrode 426. The ILD material 424 is then removed, as shown in Figure 41. The sacrificial material 420 is then removed from one of the source-drain locations (e.g., the right side) to form a trench 432, but not from the other of the source-drain locations to form a trench 430.

[0093] 4J , a first conductive contact structure 434 is formed and coupled to the first epitaxial source or drain structure (e.g., left feature 422). A second conductive contact structure 436 is formed and coupled to the second epitaxial source or drain structure (e.g., right feature 422). The second conductive contact structure 436 is formed deeper along the fin 402 than the first conductive contact structure 434. In one embodiment, although not shown in FIG. 4J , the method further includes forming an exposed surface of the second conductive contact structure 436 at the bottom of the fin 402. The conductive contact may include a contact resistance reduction layer and a main contact electrode layer, where examples may include Ti, Ni, Co (as the former; W, Ru, Co as the latter).

[0094] In one embodiment, as shown, the second conductive contact structure 436 is deeper along the fin 402 than the first conductive contact structure 434. In one such embodiment, as shown, the first conductive contact structure 434 is not along the fin 402. In another such embodiment, not shown, the first conductive contact structure 434 is partially along the fin 402.

[0095] In one embodiment, the second conductive contact structure 436 runs along the entire length of the fin 402. In one embodiment, not shown, the second conductive contact structure 436 may have an exposed surface at the bottom of the fin 402 if the bottom of the fin 402 is exposed by a backside substrate removal process.

[0096] In one embodiment, the structure of FIG. 4J, or related structures of FIGS. 4A-4J, can be formed using a cut-gate approach before spacer deposition, such as that described in connection with FIGS. 1A, 1B, 2A-2G, and 3I, and fabricated along with an associated defect test structure, such as that described in connection with FIGS. 1C-1E.

[0097] In another aspect, to enable access to both conductive contact structures of a pair of asymmetric source and drain contact structures, the integrated circuit structures described herein can be fabricated using a backside exposure of front-side structure fabrication approach. In some exemplary embodiments, exposing the backside of a transistor or other device structure involves backside processing at the wafer level. In contrast to conventional TSV-type techniques, exposing the backside of a transistor described herein may be performed at the density of device cells, and even within subregions of a device. Furthermore, such exposing of the backside of a transistor may be performed to remove substantially all of the donor substrate upon which the device layers are disposed during front-side device processing. As such, micron-deep TSVs are unnecessary, since the semiconductor thickness in the device cells after exposing the backside of the transistor is potentially only tens or hundreds of nanometers.

[0098] The exposure techniques described herein may enable a paradigm shift from "bottom-up" device fabrication to "center-out" fabrication, where the "center" is any layer utilized in front-side fabrication, exposed from the backside, and utilized again in backside fabrication. Processing of both the front side and exposed backside of the device structure may address many of the challenges associated with fabricating 3D ICs when relying primarily on front-side processing.

[0099] The approach of exposing the backside of the transistor can be used, for example, to remove at least a portion of the carrier layer and intervening layers of the donor / host substrate assembly. The process flow begins with the input of the donor / host substrate assembly. The thickness of the carrier layer in the donor / host substrate is polished (e.g., CMP) and / or etched using a wet or dry (e.g., plasma) etching process. Any grinding, polishing, and / or wet / dry etching process known to be suitable for the composition of the carrier layer can be used. For example, if the carrier layer is a group IV semiconductor (e.g., silicon), a CMP slurry known to be suitable for thinning semiconductors can be used. Similarly, any wet etchant or plasma etching process known to be suitable for thinning group IV semiconductors can be used.

[0100] In some embodiments, this is preceded by cutting the carrier layer along a fracture plane substantially parallel to the intervening layer. The cutting or fracture process can be utilized to remove a significant portion of the carrier layer as a bulk mass, reducing the polishing or etching time required to remove the carrier layer. For example, if the carrier layer is 400-900 μm thick, 100-700 μm can be cut off by performing any blanket implant known to promote wafer-level fracture. In some exemplary embodiments, a light element (e.g., H, He, or Li) is implanted to a uniform target depth within the carrier layer where the fracture plane is desired. Following such a cutting process, the thickness of the carrier layer remaining in the donor / host substrate assembly can then be polished or etched to achieve complete removal. Alternatively, if the carrier layer is not fractured, grinding, polishing, and / or etching steps can be utilized to remove a greater thickness of the carrier layer.

[0101] The exposure of the intervening layer is then detected. The detection is used to determine when the back surface of the donor substrate has progressed substantially to the device layer. Any endpoint detection technique known to be suitable for detecting the transition between the materials utilized for the carrier layer and the intervening layer may be implemented. In some embodiments, one or more endpoint criteria are based on detecting a change in optical absorption or emission of the back surface of the donor substrate during polishing or etching. In some other embodiments, the endpoint criteria are related to a change in optical absorption or emission of by-products during polishing or etching of the back surface of the donor substrate. For example, the absorption or emission wavelength associated with carrier layer etching by-products may change as a function of the different compositions of the carrier layer and the intervening layer. In other embodiments, the endpoint criteria are related to a change in mass of species in the by-products of polishing or etching the back surface of the donor substrate. For example, the process by-products may be sampled by a quadrupole mass spectrometer, and the change in species mass may be correlated to the different compositions of the carrier layer and the intervening layer. In another exemplary embodiment, the endpoint criterion is related to a change in friction between the back surface of the donor substrate and the polishing surface in contact with the back surface of the donor substrate.

[0102] Detection of the intervening layer can be enhanced if the removal process is selective for the carrier layer compared to the intervening layer, since non-uniformity in the carrier removal process can be mitigated by the etch rate delta between the carrier layer and the intervening layer. Detection can even be skipped if the grinding, polishing, and / or etching process removes the intervening layer at a rate sufficiently lower than the rate at which the carrier layer is removed. If no endpoint criteria are utilized, a grinding, polishing, and / or etching process of a predetermined fixed duration can stop on the intervening layer material if the thickness of the intervening layer is sufficient for etch selectivity. In some instances, the carrier etch rate:intervening layer etch rate is 3:1 to 10:1 or greater.

[0103] Upon exposing the intervening layer, at least a portion of the intervening layer can be removed. For example, one or more component layers of the intervening layer can be removed. The thickness of the intervening layer can be uniformly removed, for example, by polishing. Alternatively, the thickness of the intervening layer can be removed using a mask or blanket etching process. The process can utilize the same polishing or etching process used to thin the carrier, or a different process with different process parameters. For example, if the intervening layer provides an etch stop for the carrier removal process, a subsequent step can utilize a different polishing or etching process that prioritizes removal of the intervening layer over removal of the device layer. When intervening layer thicknesses of less than a few hundred nanometers are to be removed, the removal process can be relatively slow, optimized for uniformity across the wafer, and more precisely controlled than that used for carrier layer removal. The CMP process used can, for example, utilize a slurry that provides very high selectivity (e.g., 100:1 to 300:1 or greater) between the semiconductor (e.g., silicon) and dielectric material (e.g., SiO) surrounding the device layer, e.g., embedded within the intervening layer as electrical isolation between adjacent device regions.

[0104] For embodiments in which the device layer is exposed via complete removal of the intervening layer, backside processing can begin with the exposed backside of the device layer or specific device regions therein. In some embodiments, backside device layer processing includes further polishing or wet / dry etching through the thickness of the device layer that is located between the intervening layer and previously fabricated device regions in the device layer, such as source or drain regions.

[0105] In some embodiments in which the carrier layer, intervening layer, or device layer backside is recessed using wet and / or plasma etching, such etching can be a patterned etch or a substantially selective etch that imparts significant non-planarity or topography to the device layer backside surface. As explained further below, patterning can be done within a device cell (i.e., "intra-cell" patterning) or across a device cell (i.e., "inter-cell" patterning). In some patterned etch embodiments, at least a partial thickness of the intervening layer is utilized as a hard mask for backside device layer patterning. Thus, the mask etch process can be a precursor to a corresponding mask device layer etch.

[0106] The processing schemes described above may result in donor / host substrate assemblies including IC devices with exposed metallization on the backside of an intervening layer, the backside of a device layer, and / or the backside and / or front side of one or more semiconductor regions within the device layer. Additional backside processing of any of these exposed regions may then be performed during downstream processing.

[0107] It should be understood that the structures resulting from the above exemplary processing schemes may be used in the same or similar form for subsequent processing steps to complete device fabrication, such as PMOS and / or NMOS device fabrication. As an example of a completed device, Figure 5 shows a cross-sectional view of a non-planar integrated circuit structure cut along a gate line, according to one embodiment of the present disclosure.

[0108] 5, a semiconductor structure or device 500 includes a non-planar active area (e.g., a fin structure including a protruding fin portion 504 and a sub-fin region 505) within a trench isolation region 506. In one embodiment, instead of a solid fin, the non-planar active area is divided into nanowires (such as nanowires 504A and 504B) above the sub-fin region 505, as represented by the dashed lines. In either case, for ease of description of the non-planar integrated circuit structure 500, the non-planar active area 504 will be referred to below as a protruding fin portion. In one embodiment, as shown, the sub-fin region 505 also includes a relaxed buffer layer 542 and a defect correction layer 540.

[0109] A gate line 508 is disposed over the overhanging portion 504 of the non-planar active area (including surrounding nanowires 504A and 504B, if applicable) and over a portion of the trench isolation region 506. As shown, the gate line 508 includes a gate electrode 550 and a gate dielectric layer 552. In one embodiment, the gate line 508 may also include a dielectric cap layer 554. Also visible from this perspective are a gate contact 514 and an overlying gate contact via 516, along with an overlying metal interconnect 560, all of which are disposed in a multiple interlayer dielectric stack or layer 570. The perspective of FIG. 5 is similar, except that the gate contact 514, in one embodiment, is disposed over the trench isolation region 506 rather than over the non-planar active area. In another embodiment, the gate contact 514 overlies the non-planar active area.

[0110] In one embodiment, the semiconductor structure or device 500 is a non-planar device, such as, but not limited to, a fin-FET device, a tri-gate device, a nanoribbon device, or a nanowire device. In one such embodiment, the corresponding semiconductor channel region is comprised of or formed in a three-dimensional object. In one such embodiment, the gate electrode stack of the gate line 508 encompasses at least a top surface and a pair of sidewalls of the three-dimensional object.

[0111] 5, in one embodiment, there is a boundary 580 between the protruding fin portion 504 and the sub-fin region 505. The boundary 580 can be a transition region between the doped sub-fin region 505 and the lightly doped or undoped upper fin portion 504. In one such embodiment, each fin is about 10 nanometers or less in width, and the sub-fin dopant is optionally supplied from an adjacent solid-state doping layer at the sub-fin location. In certain such embodiments, each fin is less than 10 nanometers wide.

[0112] Although not shown in FIG. 5 , it should be understood that source or drain regions of or adjacent to the protruding fin portion 504 are on both sides of the gate line 508, i.e., the side leading into the page and the side leading out of the page. In one embodiment, material of the protruding fin portion 504 at the source or drain location is removed and replaced with another semiconductor material, for example, by epitaxial deposition to form an epitaxial source or drain structure. The source or drain region may extend below the level of the dielectric layer of the trench isolation region 506, i.e., into the sub-fin region 505. According to one embodiment of the present disclosure, the more heavily doped sub-fin region, i.e., the doped portion of the fin below the boundary 580, inhibits source-to-drain leakage through this portion of the bulk semiconductor fin. In one embodiment, the source and drain regions have the associated asymmetric source and drain contact structure described above in connection with FIG. 4J .

[0113] Referring again to FIG. 5, in one embodiment, fins 504 / 505 (and optionally nanowires 504A and 504B) are composed of a crystalline silicon germanium layer that may be doped with charge carriers such as, but not limited to, phosphorus, arsenic, boron, gallium, or combinations thereof.

[0114] In one embodiment, trench isolation region 506 and the plurality of trench isolation regions (trench isolation structures or trench isolation layers) described throughout may be composed of a material suitable for ultimately electrically isolating or contributing to isolating a portion of a permanent gate structure from the underlying bulk substrate, or for isolating an active area formed in the underlying bulk substrate, such as the active area of ​​an isolation fin. For example, in one embodiment, trench isolation region 506 is composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0115] The gate line 508 may be comprised of a gate electrode stack including a gate dielectric layer 552 and a gate electrode layer 550. In one embodiment, the gate electrode of the gate electrode stack is comprised of a metal gate, and the gate dielectric layer is comprised of a high-k material. For example, in one embodiment, the gate dielectric layer 552 is comprised of a material such as, but not limited to, hafnium oxide, hafnium oxynitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, tantalum scandium lead oxide, lead zinc niobate, or a combination thereof. Additionally, a portion of the gate dielectric layer 552 may include a layer of native oxide formed from the top few layers of the substrate fin 504. In one embodiment, the gate dielectric layer 552 is comprised of a top high-k portion and a bottom portion comprised of an oxide of a semiconductor material. In one embodiment, the gate dielectric layer 552 is composed of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxynitride. In some implementations, a portion of the gate dielectric is a "U" shaped structure with a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate.

[0116] In one embodiment, the gate electrode layer 550 is composed of a metal layer, such as, but not limited to, a metal nitride, a metal carbide, a metal silicide, a metal aluminide, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, or a conductive metal oxide. In a particular embodiment, the gate electrode layer 550 is composed of a non-work function setting fill material formed on a metal work function setting layer. The gate electrode layer 550 may be composed of a P-type work function metal or an N-type work function metal, depending on whether the transistor is a PMOS transistor or an NMOS transistor. In some implementations, the gate electrode layer 550 may be composed of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a conductive fill layer. In a PMOS transistor, metals that can be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, tungsten, and conductive metal oxides, such as ruthenium oxide. The P-type metal layer enables the formation of a PMOS gate electrode having a work function between about 4.9 eV and about 5.2 eV. In an NMOS transistor, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. The N-type metal layer enables the formation of an NMOS gate electrode having a work function between about 3.9 eV and about 4.2 eV. In some implementations, the gate electrode can be configured with a U-shaped structure including a bottom substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers forming the gate electrode can be simply a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the present disclosure, the gate electrode may be comprised of a combination of U-shaped and planar, non-U-shaped structures.For example, the gate electrode may consist of one or more U-shaped metal layers formed on one or more planar, non-U-shaped layers.

[0117] The spacers associated with the gate electrode stack may be comprised of any suitable material that ultimately electrically isolates or contributes to the isolation of the permanent gate structure from adjacent conductive contacts, such as self-aligned contacts. For example, in one embodiment, the spacers are comprised of a dielectric material such as, but not limited to, silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride.

[0118] The gate contact 514 and upper gate contact via 516 may be composed of a conductive material. In one embodiment, one or more of the contacts or vias are composed of a metallic species. The metallic species may be a pure metal such as tungsten, nickel, or cobalt, or may be an alloy such as an intermetallic alloy or a metal-semiconductor alloy (e.g., a silicide material).

[0119] In one embodiment (not shown), a contact pattern is formed that is essentially perfectly aligned to the existing gate pattern 508, eliminating the use of a lithography step with very tight alignment margins. In one embodiment, the contact pattern is a vertically symmetric contact pattern or an asymmetric contact pattern such as that described in connection with FIG. 4J. In other embodiments, all contacts are connected to the front side and are not asymmetric. In one such embodiment, this self-aligned approach inherently enables the use of highly selective wet etches (e.g., relative to conventionally performed dry or plasma etches) to create the contact openings. In one embodiment, the contact pattern is formed by utilizing the existing gate pattern in combination with a contact plug lithography step. In one such embodiment, this approach enables the elimination of the need for an otherwise critical lithography step to create the contact pattern, as used in conventional approaches. In one embodiment, the trench contact grid is formed between the poly (gate) lines rather than being separately patterned. For example, in one such embodiment, the trench contact grid is formed after gate grid patterning but before gate grid cutting.

[0120] In one embodiment, providing the structure 500 involves fabricating the gate stack structure 508 by a replacement gate process. In such a scheme, dummy gate material, such as polysilicon or silicon nitride pillar material, can be removed and replaced with a permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in this process rather than being carried over from previous processing. In one embodiment, the dummy gate is removed by a dry or wet etching process. In one embodiment, the dummy gates are comprised of polycrystalline or amorphous silicon and are removed using a dry etching process including the use of SF. In another embodiment, the dummy gates are comprised of polycrystalline or amorphous silicon and are removed with a wet etching process including the use of aqueous NH4OH or tetramethylammonium hydroxide. In one embodiment, the dummy gate is comprised of silicon nitride and is removed with a wet etch including aqueous phosphoric acid.

[0121] 5, the layout of semiconductor structure or device 500 positions the gate contact above the isolation region. Such a configuration may be considered an inefficient use of layout space. However, in another embodiment, the semiconductor device has a contact structure that contacts a portion of the gate electrode formed in the same layer as the trench contact via above the active region, for example, above fin 505.

[0122] In one embodiment, the structure of FIG. 5 can be formed using a cut gate approach before spacer deposition, such as that described in connection with FIGS. 1A, 1B, 2A-2G, and 3I, and fabricated with an associated defect test structure, such as that described in connection with FIGS. 1C-1E.

[0123] It should be understood that not all aspects of the above-described processes need to be practiced to fall within the spirit and scope of embodiments of the present disclosure. Additionally, the processes described herein may be used to fabricate one or more semiconductor devices. The semiconductor device may be a transistor or similar device. For example, in one embodiment, the semiconductor device is a metal-oxide-semiconductor (MOS) transistor for logic or memory, or a bipolar transistor. Also, in one embodiment, the semiconductor device has a three-dimensional architecture, such as a nanowire device, a nanoribbon device, a tri-gate device, an independently accessed double-gate device, or a FinFET. One or more embodiments may be particularly useful for fabricating semiconductor devices at sub-ten nanometer (10 nm) technology nodes.

[0124] In one embodiment, as used throughout this description, an interlayer dielectric (ILD) material consists of or includes a layer of dielectric or insulator material. Examples of suitable dielectric materials include, but are not limited to, silicon oxide (e.g., silicon dioxide (SiO2)), doped silicon oxide, fluorinated silicon oxide, carbon-doped silicon oxide, various low-k dielectric materials known in the art, and combinations thereof. The interlayer dielectric material may be formed by conventional techniques such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or other deposition methods.

[0125] In one embodiment, as used throughout this description, metal line or interconnect line material (and via material) is composed of one or more metals or other conductive structures. A common example is the use of copper lines and structures, which may or may not include a barrier layer between the copper and the surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of multiple metals. For example, a metal interconnect line may include a barrier layer (e.g., a layer including one or more of Ta, TaN, Ti, or TiN), a stack of different metals or alloys, etc. Thus, the interconnect line may be a single layer of material or may be formed from multiple layers, including conductive liner layers and fill layers. Any suitable deposition process, such as electroplating, chemical vapor deposition, or physical vapor deposition, may be used to form the interconnect line. In one embodiment, the interconnect lines are composed of a conductive material such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au, or alloys thereof, and are sometimes referred to in the art as wiring, wires, lines, metals, or simply interconnects.

[0126] In one embodiment, as also used throughout this specification, the hardmask material, cap layer, or plug is composed of a different dielectric material than the interlayer dielectric material. In one embodiment, different hardmask, cap, or plug materials may be used in different regions to provide different growth or etch selectivities to each other and to the underlying dielectric and metal layers. In some embodiments, the hardmask layer, cap, or plug layer comprises a layer of silicon nitride (e.g., silicon nitride) or a layer of silicon oxide, or both, or a combination thereof. Other suitable materials may include carbon-based materials. Other hardmask, cap, or plug layers known in the art may be used depending on the specific implementation. The hardmask, cap, or plug layer may be formed by CVD, PVD, or other deposition methods.

[0127] In one embodiment, as used interchangeably throughout this description, the lithography process is performed using 193 nm immersion lithography (i193), EUV, and / or EBDW lithography, or the like. Positive-tone or negative-tone resists may be used. In one embodiment, the lithography mask is a three-layer mask comprised of a topography masking portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In certain such embodiments, the topography masking portion is a carbon hard mask (CHM) layer, and the anti-reflective coating layer is a silicon ARC layer.

[0128] In another aspect, one or more embodiments relate to adjacent semiconductor structures or devices separated by a self-aligned gate endcap (SAGE) structure. Particular embodiments relate to the integration of multiple-width (multi-Wsi) nanowires and nanoribbons in a SAGE architecture, which may be separated by SAGE walls. In one embodiment, nanowires / nanoribbons are integrated with multiple Wsi in the SAGE architecture portion of a front-end process flow. Such a process flow may involve the integration of nanowires and nanoribbons of different Wsi to provide robust functionality for next-generation transistors with low power and high performance. Associated epitaxial source or drain regions may be recessed (e.g., a portion of the nanowire is removed, and then source or drain (S / D) growth is performed).

[0129] To provide further context, advantages of the self-aligned gate endcap (SAGE) architecture may include enabling higher layout density and, in particular, scaling of diffusion layer-to-diffusion layer spacing. For an exemplary comparison, Figure 6 shows a cross-section cut through the nanowire and fin of a no-endcap architecture (left side (a)) versus a self-aligned gate endcap (SAGE) architecture (right side (b)), according to one embodiment of the present disclosure.

[0130] Referring to the left side (a) of Figure 6, an integrated circuit structure 600 includes a substrate 602 having a fin 604 that protrudes an amount 606 above an isolation structure 608 that laterally surrounds a lower portion of the fin 604. As shown, the upper portion of the fin may include a relaxed buffer layer 622 and a defect correction layer 620. A corresponding nanowire 605 overlies the fin 604. Gate structures may be formed above the integrated circuit structure 600 for device fabrication. However, discontinuities in such gate structures may be accommodated by increasing the spacing between the fin 604 / nanowire 605 pair.

[0131] In contrast, referring to the right side (b) of FIG. 6 , an integrated circuit structure 650 includes a substrate 652 having a fin 654 that protrudes an amount 656 above an isolation structure 658 that laterally surrounds the bottom of the fin 654. As shown, the top of the fin may include a relaxed buffer layer 672 and a defect correction layer 670. A corresponding nanowire 655 overlies the fin 654. Isolation SAGE walls 660 (which may include a hard mask thereon, as shown) are included between adjacent fin 654 / nanowire 655 pairs within the isolation structure 652. The distance between the isolation SAGE walls 660 and the nearest fin 654 / nanowire 655 pair defines a gate endcap spacing 662. Gate structures can be formed above the integrated circuit structure 600 between the isolating SAGE walls to fabricate devices. The discontinuities in such gate structures are imposed by the isolating SAGE walls. Because the isolating SAGE walls 660 are self-aligned, they can allow for more aggressive diffusion spacing, minimizing the limitations of conventional approaches. Furthermore, because the gate structure includes discontinuities at all locations, individual gate structure portions may be layered and connected by local interconnects formed above the isolating SAGE walls 660. In one embodiment, as shown, each SAGE wall 660 includes a lower dielectric portion and a dielectric cap over the lower dielectric portion. According to one embodiment of the present disclosure, the fabrication process for the structure associated with FIG. 6 involves the use of a process scheme that provides a gate-all-around integrated circuit structure with epitaxial source or drain structures.

[0132] In one embodiment, the structure of portion (b) of Figure 6 is formed using a cut gate approach before spacer deposition, such as that described in connection with Figures 1A, 1B, 2A-2G, and 3I, and can be fabricated with an associated defect test structure, such as that described in connection with Figures 1C-1E.

[0133] The self-aligned gate endcap (SAGE) processing scheme involves the formation of gate / trench contact endcaps that are self-aligned to the fin without requiring additional length to account for mask misalignment. Accordingly, embodiments may be implemented to enable area reduction of transistor layouts. Embodiments described herein may involve the fabrication of gate endcap isolation structures, which may also be referred to as gate walls, isolation gate walls, or self-aligned gate endcap (SAGE) walls.

[0134] In an exemplary processing scheme for a structure having SAGE walls separating adjacent devices, FIG. 7 shows cross-sectional views illustrating various steps in a method for fabricating a self-aligned gate endcap (SAGE) structure with gate-all-around devices according to one embodiment of the present disclosure.

[0135] Referring to portion (a) of Figure 7, a starting structure includes a nanowire patterning stack 704 above a substrate 702. A lithographic patterning stack 706 is formed above the nanowire patterning stack 704. The nanowire patterning stack 704 includes alternating sacrificial layers 710 and nanowire layers 712, which may overlie a relaxed buffer layer 782 and a defect correction layer 780, as shown. A protective mask 714 is between the nanowire patterning stack 704 and the lithographic patterning stack 706. In one embodiment, the lithographic patterning stack 706 is a three-layer mask comprised of a topographic masking portion 720, an antireflective coating (ARC) layer 722, and a photoresist layer 724. In certain such embodiments, the topographic masking portion 720 is a carbon hard mask (CHM) layer, and the antireflective coating layer 722 is a silicon ARC layer.

[0136] Referring to part (b) of FIG. 7, the stack of part (a) is lithographically patterned and then etched to result in a patterned substrate 702 and an etched structure including trenches 730.

[0137] Referring to portion (c) of Figure 7, the structure of portion (b) has an isolation layer 740 and SAGE material 742 formed in trench 730. The structure is then planarized to leave the patterned topographic masking layer 720' as the exposed upper layer.

[0138] Referring to part (d) of Figure 7, an isolation layer 740 is recessed below the upper surface of the patterned substrate 702, for example to define a protruding fin portion, resulting in a trench isolation structure 741 below the SAGE wall 742.

[0139] Referring to part (e) of Figure 7, sacrificial layer 710 is removed in at least the channel region to release nanowires 712A and 712B. After the structure of part (e) of Figure 7 is formed, a gate stack may be formed on the protruding fins of substrate 702 around nanowire 712B or 712A and between SAGE walls 742. In one embodiment, prior to forming the gate stack, remaining portions of protective mask 714 are removed. In another embodiment, remaining portions of protective mask 714 are retained as insulating fin hats as an artifact of the processing scheme.

[0140] Referring again to section (e) of Figure 7, it should be understood that the channel diagram is shown with the source or drain regions positioned into or out of the page. In one embodiment, the channel region containing nanowire 712B has a smaller width than the channel region containing nanowire 712A. Thus, in one embodiment, the integrated circuit structure includes multi-width (multi-Wsi) nanowires. While the structures 712B and 712A may be distinguished as nanowires and nanoribbons, respectively, both such structures are generally referred to herein as nanowires. It should also be understood that references or depictions of fin / nanowire pairs throughout may refer to structures including a fin and one or more overlying nanowires (e.g., two overlying nanowires are shown in Figure 7). According to one embodiment of the present disclosure, the fabrication process for the structure associated with Figure 7 involves the use of a process scheme that provides a gate-all-around integrated circuit structure with epitaxial source or drain structures.

[0141] In one embodiment, the structure of portion (e) of Figure 7 is formed using a cut gate approach before spacer deposition, such as that described in connection with Figures 1A, 1B, 2A-2G, and 3I, and can be fabricated with an associated defect test structure, such as that described in connection with Figures 1C-1E.

[0142] In one embodiment, as described throughout, the self-aligned gate endcap (SAGE) isolation structure may be composed of one or more materials suitable for ultimately electrically isolating or contributing to isolating portions of the permanent gate structure from one another. Exemplary materials or material combinations include single material structures such as silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride. Other exemplary materials or material combinations include multilayer stacks having a bottom silicon dioxide, silicon oxynitride, silicon nitride, or carbon-doped silicon nitride and an upper portion of a high dielectric constant material such as hafnium oxide.

[0143] To highlight an exemplary integrated circuit structure comprising three vertically arranged nanowires, Figure 8A shows a three-dimensional cross-sectional view of a nanowire-based integrated circuit structure according to one embodiment of the present disclosure. Figure 8B shows a cross-sectional source or drain view of the nanowire-based integrated circuit structure of Figure 8A taken along the a-a' axis. Figure 8C shows a cross-sectional channel view of the nanowire-based integrated circuit structure of Figure 8A taken along the b-b' axis.

[0144] Referring to FIG. 8A , an integrated circuit structure 800 includes one or more vertically stacked nanowires (set 804) on a substrate 802. In one embodiment, a relaxed buffer layer 802C, a defect correction layer 802B, and a lower substrate portion 802A are included in the substrate 802 as shown. An optional fin below the bottom nanowire and formed from the substrate 802 is not shown to emphasize the nanowire portion for illustrative purposes. The embodiments herein address both single-wire and multiple-wire devices. As an example, a three-nanowire-based device comprising nanowires 804A, 804B, and 804C is shown for illustrative purposes. For ease of explanation, nanowire 804A is used as an example, with the discussion focusing on one of the nanowires. Where characteristics of a single nanowire are described, it should be understood that embodiments based on multiple nanowires may have the same or essentially the same characteristics for each of the nanowires.

[0145] Each of the nanowires 804 includes a nanowire channel region 806. The channel region 806 has a length (L). Referring to FIG. 8C, the channel region also has a perimeter (Pc) that is orthogonal to the length (L). Referring to both FIGS. 8A and 8C, a gate electrode stack 808 surrounds the entire perimeter (Pc) of each of the channel regions 806. The gate electrode stack 808 includes a gate electrode along with a gate dielectric layer between the channel region 806 and the gate electrode (not shown). In one embodiment, the channel region is discrete in that it is completely surrounded by the gate electrode stack 808 and is free of any intervening material, such as an underlying substrate material or an overlying channel fabrication material. Thus, in embodiments having multiple nanowires 804, the nanowire channel regions 806 are also discrete with respect to one another.

[0146] 8A and 8B, integrated circuit structure 800 includes a pair of non-discrete source or drain regions 810 / 812 on either side of channel region 806 of vertically stacked nanowires 804. Furthermore, the pair of non-discrete source or drain regions 810 / 812 is adjacent to channel region 806 of vertically stacked nanowires 804. In one such embodiment, although not shown, the pair of non-discrete source or drain regions 810 / 812 is directly vertically adjacent to channel region 806 in that epitaxial growth is on and between portions of the nanowires that extend beyond channel region 806, with the nanowire ends shown within the source or drain structures. In another embodiment, as illustrated in FIG. 8A, pairs of non-discrete source or drain regions 810 / 812 are indirectly vertically adjacent with respect to the channel region 806 in that they are formed at the ends of the nanowires rather than between them.

[0147] In one embodiment, as shown, the source or drain regions 810 / 812 are non-discrete in that there is a separate, non-discrete source or drain region for each channel region 806 of the nanowire 804. Thus, in embodiments comprising multiple nanowires 804, the nanowire source or drain regions 810 / 812 are global, or integrated, source or drain regions, as opposed to discrete for each nanowire. That is, the non-discrete source or drain regions 810 / 812 are global in the sense that a single integrated feature serves as a source or drain region for multiple (in this case, three) nanowires 804, and more particularly, for more than one discrete channel region 806. In one embodiment, as shown in FIG. 8B , from a cross-sectional perspective view perpendicular to the length of the discrete channel region 806, each pair of non-discrete source or drain regions 810 / 812 is roughly rectangular in shape, with a tapered portion at the bottom and a vertex portion at the top. However, in other embodiments, the nanowire source or drain regions 810 / 812 are relatively large, yet discrete, non-vertically fused epitaxial structures, such as the nubs described in connection with Figures 4A-4J.

[0148] According to one embodiment of the present disclosure, and as illustrated in FIGS. 8A and 8B , the integrated circuit structure 800 further includes pairs of contacts 814, each contact 814 on one of the pair of non-discrete source or drain regions 810 / 812. In one such embodiment, each contact 814 completely surrounds its respective non-discrete source or drain region 810 / 812 in a vertical sense. In another aspect, as illustrated in FIG. 8B , the entire perimeter of the non-discrete source or drain region 810 / 812 may not be accessible for contact with the contact 814, and the contact 814 therefore only partially surrounds the non-discrete source or drain region 810 / 812. In a contrasting embodiment, not shown, the entire perimeter of the non-discrete source or drain region 810 / 812 is surrounded by the contact 814, as cut along the a-a′ axis.

[0149] 8A , in one embodiment, integrated circuit structure 800 further includes a pair of spacers 816. As shown, outer portions of the pair of spacers 816 may overlap portions of the non-discrete source or drain regions 810 / 812, providing “buried” portions of the non-discrete source or drain regions 810 / 812 beneath the pair of spacers 816. As also shown, the buried portions of the non-discrete source or drain regions 810 / 812 may not extend entirely beneath the pair of spacers 816.

[0150] Substrate 802 may be composed of a material suitable for the fabrication of integrated circuit structures. In one embodiment, substrate 802 includes a lower bulk substrate composed of a single-crystalline material, which may include, but is not limited to, silicon, germanium, silicon germanium, germanium tin, silicon germanium tin, or a III-V compound semiconductor material. An upper insulating layer, which may include, but is not limited to, silicon dioxide, silicon nitride, or silicon oxynitride, is on the lower bulk substrate. Thus, structure 800 may be fabricated from a starting semiconductor on an insulating substrate. Alternatively, structure 800 may be formed directly from a bulk substrate, and localized oxidation may be used to form electrically insulating portions in place of the upper insulating layer described above. In another alternative embodiment, structure 800 may be formed directly from a bulk substrate, and doping may be used to form electrically isolated active regions, such as nanowires, thereon. In one such embodiment, the first nanowire (i.e., closest to the substrate) is in the form of an omegaFET-type structure.

[0151] In one embodiment, the nanowires 804 may be wire or ribbon sized, as described below, and may have square or rounded corners. In one embodiment, the nanowires 804 are composed of materials such as, but not limited to, silicon, germanium, or a combination thereof. In one such embodiment, the nanowires are single crystalline. For example, with respect to silicon nanowires 804, single crystalline nanowires have a global orientation (100), e.g., in the z-direction. <100> The nanowire 804 may be based on a plane. As discussed below, other orientations are also possible. In one embodiment, the dimensions of the nanowire 804 are nanoscale from a cross-sectional perspective view. For example, in certain embodiments, the smallest dimension of the nanowire 804 is less than about 20 nanometers. In one embodiment, the nanowire 804 is composed of a strained material, particularly in the channel region 806.

[0152] 8C, in one embodiment, each channel region 806 has a width (Wc) and a height (Hc), where the width (Wc) is approximately the same as the height (Hc). That is, in both cases, the channel regions 806 have a square-like, or, if the corners are rounded, a circular-like cross-sectional profile. In other aspects, such as in the case of nanoribbons as generally described, the widths and heights of the channel regions need not be the same.

[0153] In one embodiment, as described throughout, the integrated circuit structure includes a non-planar device, such as, but not limited to, a finFET or tri-gate device, having one or more corresponding overlying nanowire structures. In one such embodiment, the corresponding semiconductor channel region is comprised of or formed within a three-dimensional object, with one or more discrete nanowire channel portions in an overlying layer of the three-dimensional object. In one such embodiment, a gate structure surrounds at least a top surface and a pair of sidewalls of the three-dimensional object, and further surrounds each of the one or more discrete nanowire channel portions.

[0154] In one embodiment, the structures of Figures 8A-8C are formed using a cut gate approach before spacer deposition, such as that described in connection with Figures 1A, 1B, 2A-2G, and 3I, and can be fabricated with associated defect test structures, such as those described in connection with Figures 1C-1E.

[0155] In one embodiment, as described throughout, the underlying substrate may be composed of a semiconductor material capable of withstanding fabrication processes and allowing charge transport. In one embodiment, the substrate is a bulk substrate composed of a crystalline silicon, silicon / germanium, or germanium layer doped with charge carriers, such as, but not limited to, phosphorus, arsenic, boron, gallium, or a combination thereof, to form an active region. In one embodiment, the concentration of silicon atoms in the bulk substrate is greater than 97%. In another embodiment, the bulk substrate is composed of an epitaxial layer grown on a separate crystalline substrate, for example, a silicon epitaxial layer grown on a boron-doped bulk silicon single crystal substrate. Alternatively, the bulk substrate may be composed of a III-V material. In one embodiment, the bulk substrate is composed of a III-V material, such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimony, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or a combination thereof. In one embodiment, the bulk substrate is composed of a III-V material and the charge carrier dopant impurity atoms include, but are not limited to, carbon, silicon, germanium, oxygen, sulfur, selenium, or tellurium.

[0156] The embodiments disclosed herein may be used to manufacture a wide variety of different types of integrated circuits and / or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, microcontrollers, and the like. In other embodiments, semiconductor memories may be manufactured. Furthermore, integrated circuits or other microelectronic devices may be used in a wide variety of electronic devices known in the art, such as computer systems (e.g., desktops, laptops, servers), cellular telephones, personal electronic devices, etc. The integrated circuits may be coupled with buses and other components of the system. For example, a processor may be coupled with memory, chipsets, etc. by one or more buses. Each of the processors, memories, and chipsets may potentially be manufactured using the approaches disclosed herein.

[0157] 9 illustrates a computing device 900 according to an implementation of an embodiment of the present disclosure. The computing device 900 houses a board 902. The board 902 may include multiple components, including, but not limited to, a processor 904 and at least one communications chip 906. The processor 904 is physically and electrically coupled to the board 902. In some implementations, the at least one communications chip 906 is also physically and electrically coupled to the board 902. In further implementations, the communications chip 906 is part of the processor 904.

[0158] Computing device 900 may include other components that, depending on its application, may or may not be physically and electrically coupled to board 902. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processors, digital signal processors, cryptographic processors, chipsets, antennas, displays, touchscreen displays, touchscreen controllers, batteries, audio codecs, video codecs, power amplifiers, global positioning system (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and mass storage devices (e.g., hard disk drives, compact discs (CDs), digital versatile discs (DVDs), etc.).

[0159] The communications chip 906 enables wireless communications for the transfer of data to and from the computing device 900. The term “wireless,” and its derivatives, may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation over a non-solid medium. The term does not imply that the associated devices do not include any wires, although in some embodiments they may not. The communications chip 906 may implement any of several wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocols designated as 3G, 4G, 5G, and beyond. The computing device 900 may include multiple communication chips 906. For example, a first communication chip 906 may be dedicated to short-range wireless communications such as Wi-Fi and Bluetooth, and a second communication chip 906 may be dedicated to long-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, and Ev-DO.

[0160] The processor 904 of the computing device 900 includes an integrated circuit die packaged within the processor 904. The integrated circuit die of the processor 904 may include one or more structures, such as an integrated circuit structure having a pre-spacer deposition cut gate and associated defect test structures constructed according to implementations of embodiments of the present disclosure. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory and converts the electronic data into other electronic data that can be stored in registers and / or memory.

[0161] The communications chip 906 further includes an integrated circuit die packaged within the communications chip 906. The integrated circuit die of the communications chip 906 may include one or more structures, such as an integrated circuit structure having a pre-spacer deposition cut gate and associated defect test structures constructed according to implementations of embodiments of the present disclosure.

[0162] In a further implementation, another component within computing device 900 may include an integrated circuit die including one or more structures, such as an integrated circuit structure having a pre-spacer deposition cut gate and associated defect test structure constructed according to an implementation of an embodiment of the present disclosure.

[0163] In various implementations, computing device 900 may be a laptop, netbook, notebook, ultrabook, smartphone, tablet, personal digital assistant (PDA), ultra-mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video recorder. In further implementations, computing device 900 may be any other electronic device that processes data.

[0164] FIG. 10 illustrates an interposer 1000 including one or more embodiments of the present disclosure. The interposer 1000 is an intervening substrate used to bridge a first substrate 1002 and a second substrate 1004. The first substrate 1002 may be, for example, an integrated circuit die. The second substrate 1004 may be, for example, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of the interposer 1000 is to spread connections to a wider pitch or to reroute connections to different connections. For example, the interposer 1000 may bond an integrated circuit die to a ball grid array (BGA) 1006, which may then be bonded to the second substrate 1004. In some embodiments, the first substrate and the second substrate 1002 / 1004 are attached to opposite sides of the interposer 1000. In other embodiments, the first and second substrates 1002 / 1004 are attached to the same side of the interposer 1000. And, in further embodiments, three or more substrates are interconnected by the interposer 1000.

[0165] Interposer 1000 may be formed of a polymeric material such as epoxy, fiberglass reinforced epoxy, ceramic material, or polyimide. In further implementations, interposer 1000 may be formed of alternating rigid or flexible materials, which may include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other III-V and IV materials.

[0166] The interposer 1000 may include metal interconnects 1008 and vias 1010, including but not limited to through-silicon vias (TSVs) 1012. The interposer 1000 may further include embedded devices 1014, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices, such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices, may also be formed on the interposer 1000. According to embodiments of the present disclosure, the apparatus or process disclosed herein may be used in the manufacture of the interposer 1000 or components included in the interposer 1000.

[0167] To this end, embodiments of the present disclosure include integrated circuit structures having cut gates and associated defect test structures before spacer deposition, and methods of fabricating integrated circuit structures having cut gates and associated defect test structures before spacer deposition.

[0168] The above description of illustrated implementations of embodiments of the present disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise form disclosed. While specific implementations and examples of the present disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the present disclosure, as those skilled in the art will recognize.

[0169] These variations can be made to the present disclosure in light of the detailed description above. The terms used in the following claims should not be construed to limit the disclosure to the specific implementations disclosed in the specification and claims. Rather, the scope of the present disclosure should be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

[0170] Exemplary Embodiment 1: An integrated circuit structure including a first fin and a second fin. A first gate stack is on the first fin, and a second gate stack is on the second fin. An edge of the second gate stack is spaced apart from an edge of the first gate stack by a gap. The integrated circuit structure also includes a dielectric structure having a first portion forming a gate spacer along a sidewall of the first gate stack, a second portion forming a gate spacer along a sidewall of the second gate stack, and a third portion completely filling the gap, the third portion being continuous with the first and second portions. The integrated circuit structure also includes an array having a periodic arrangement of alternating floating and grounded conductive trench contacts along a direction parallel to the first and second gate stacks.

[0171] Exemplary Embodiment 2: The integrated circuit structure of exemplary embodiment 1, wherein the array having a periodic arrangement of alternating floating and grounded conductive trench contacts is a test structure configured for voltage contrast (VC) measurements.

[0172] Exemplary Embodiment 3: The integrated circuit structure of Exemplary Embodiment 1 or 2, further including a first pair of epitaxial source or drain structures at the first end and the second end of the first fin, and a second pair of epitaxial source or drain structures at the first end and the second end of the second fin.

[0173] Exemplary Embodiment 4: The integrated circuit structure of Exemplary Embodiment 3, further including: a first pair of conductive contacts on the first pair of epitaxial source or drain structures; and a second pair of conductive contacts on the second pair of epitaxial source or drain structures.

[0174] Exemplary Embodiment 5: The integrated circuit structure of Exemplary Embodiment 3 or 4, wherein the first pair and second pair of epitaxial source or drain structures are first pair and second pair of non-discrete epitaxial source or drain structures.

[0175] Exemplary embodiment 6: An integrated circuit structure includes a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires. A first gate stack is located on the first vertical arrangement of horizontal nanowires, and a second gate stack is located on the second vertical arrangement of horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. The integrated circuit structure also includes a dielectric structure having a first portion forming a gate spacer along a sidewall of the first gate stack, a second portion forming a gate spacer along a sidewall of the second gate stack, and a third portion completely filling the gap, the third portion being continuous with the first and second portions. The integrated circuit structure also includes an array having a periodic arrangement of alternating floating and grounded conductive trench contacts along a direction parallel to the first and second gate stacks.

[0176] Exemplary Embodiment 7: The integrated circuit structure of Exemplary Embodiment 6, wherein the array having a periodic arrangement of alternating floating and grounded conductive trench contacts is a test structure configured for voltage contrast (VC) measurements.

[0177] Exemplary embodiment 8: The integrated circuit structure of exemplary embodiment 6 or 7, further comprising a first pair of epitaxial source or drain structures at the first and second ends of the first vertical arrangement of the horizontal nanowires, and a second pair of epitaxial source or drain structures at the first and second ends of the second vertical arrangement of the horizontal nanowires.

[0178] Exemplary Embodiment 9: The integrated circuit structure of Exemplary Embodiment 8, further including: a first pair of conductive contacts on the first pair of epitaxial source or drain structures; and a second pair of conductive contacts on the second pair of epitaxial source or drain structures.

[0179] Exemplary Embodiment 10: The integrated circuit structure of Exemplary Embodiment 8 or 9, wherein the first pair and second pair of epitaxial source or drain structures are first pair and second pair of non-discrete epitaxial source or drain structures.

[0180] Exemplary embodiment 11: A computing device includes a substrate and a component coupled to the substrate. The component includes an integrated circuit structure including a vertical arrangement of first fins or horizontal nanowires and a vertical arrangement of second fins or horizontal nanowires. A first gate stack is located on the vertical arrangement of the first fins or horizontal nanowires, and a second gate stack is located on the vertical arrangement of the second fins or horizontal nanowires. An end of the second gate stack is spaced apart from an end of the first gate stack by a gap. The integrated circuit structure also includes a dielectric structure having a first portion forming a gate spacer along a sidewall of the first gate stack, a second portion forming a gate spacer along a sidewall of the second gate stack, and a third portion completely filling the gap, the third portion being continuous with the first and second portions. The integrated circuit structure also includes an array having a periodic arrangement of alternating floating and grounded conductive trench contacts along a direction parallel to the first and second gate stacks.

[0181] Exemplary embodiment 12: The computing device of exemplary embodiment 11, including a first fin and a second fin.

[0182] Exemplary Embodiment 13: The computing device of exemplary embodiment 11 or 12, comprising a first vertical arrangement of horizontal nanowires and a second vertical arrangement of horizontal nanowires.

[0183] Exemplary Embodiment 14: The computing device of Exemplary Embodiment 11, 12, or 13, further including a memory coupled to the substrate.

[0184] Exemplary Embodiment 15: The computing device of Exemplary Embodiments 11, 12, 13, or 14, further comprising a communications chip coupled to the substrate.

[0185] Exemplary Embodiment 16: The computing device of exemplary embodiments 11, 12, 13, 14, or 15, further comprising a battery coupled to the substrate.

[0186] Exemplary Embodiment 17: The computing device of exemplary embodiments 11, 12, 13, 14, 15, or 16, further comprising a camera coupled to the substrate.

[0187] Exemplary Embodiment 18: The computing device of Exemplary Embodiments 11, 12, 13, 14, 15, 16, or 17, further comprising a display coupled to the substrate.

[0188] Exemplary Embodiment 19: The computing device of Exemplary Embodiments 11, 12, 13, 14, 15, 16, 17, or 18, wherein the component is a packaged integrated circuit die.

[0189] Exemplary Embodiment 20: The computing device of exemplary embodiments 11, 12, 13, 14, 15, 16, 17, 18, or 19, wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor. [Other possible items] [Item 1] First fin; second fin; a first gate stack over the first fin; a second gate stack on the second fin, an end of the second gate stack spaced apart from an end of the first gate stack by a gap; a dielectric structure having a first portion forming a gate spacer along a sidewall of the first gate stack, a second portion forming a gate spacer along a sidewall of the second gate stack, and a third portion completely filling the gap, the third portion being continuous with the first portion and the second portion; and an array having a periodic arrangement of alternating floating and grounded conductive trench contacts along a direction parallel to the first gate stack and the second gate stack; 1. An integrated circuit structure comprising: [Item 2] Item 10. The integrated circuit structure of item 1, wherein the array having a periodic arrangement of alternating floating and grounded conductive trench contacts is a test structure configured for voltage contrast (VC) measurements. [Item 3] a first pair of epitaxial source or drain structures at a first end and a second end of the first fin; and a second pair of epitaxial source or drain structures at a first end and a second end of the second fin; Item 1. The integrated circuit structure of item 1, further comprising: [Item 4] a first pair of conductive trench contacts on the first pair of epitaxial source or drain structures; and a second pair of conductive trench contacts on the second pair of epitaxial source or drain structures; Item 4. The integrated circuit structure of item 3, further comprising: [Item 5] Item 4. The integrated circuit structure of item 3, wherein the first and second pairs of epitaxial source or drain structures are first and second pairs of non-discrete epitaxial source or drain structures. [Item 6] A first vertical arrangement of horizontal nanowires; a second vertical arrangement of horizontal nanowires; a first gate stack above the first vertical arrangement of horizontal nanowires; a second gate stack on a second vertical arrangement of the horizontal nanowires, an end of the second gate stack being spaced apart from an end of the first gate stack by a gap; a dielectric structure having a first portion forming a gate spacer along a sidewall of the first gate stack, a second portion forming a gate spacer along a sidewall of the second gate stack, and a third portion completely filling the gap, the third portion being continuous with the first portion and the second portion; and an array having a periodic arrangement of alternating floating and grounded conductive trench contacts along a direction parallel to the first gate stack and the second gate stack; 1. An integrated circuit structure comprising: [Item 7] Item 7. The integrated circuit structure of item 6, wherein the array having a periodic arrangement of alternating floating and grounded conductive trench contacts is a test structure configured for voltage contrast (VC) measurements. [Item 8] a first pair of epitaxial source or drain structures at first and second ends of a first vertical arrangement of the horizontal nanowires; and a second pair of epitaxial source or drain structures at first and second ends of the second vertical arrangement of horizontal nanowires; Item 7. The integrated circuit structure of item 6, further comprising: [Item 9] a first pair of conductive trench contacts on the first pair of epitaxial source or drain structures; and a second pair of conductive trench contacts on the second pair of epitaxial source or drain structures; Item 9. The integrated circuit structure of item 8, further comprising: [Item 10] Item 10. The integrated circuit structure of item 8, wherein the first and second pairs of epitaxial source or drain structures are first and second pairs of non-discrete epitaxial source or drain structures. [Item 11] 1. A computing device comprising: substrate; and Components bonded to the substrate the component has an integrated circuit structure, the integrated circuit structure comprising: vertical placement of first fins or horizontal nanowires; vertical placement of second fins or horizontal nanowires; a first gate stack above the first fin or the vertical arrangement of the horizontal nanowires; a second gate stack on the second fin or the vertical arrangement of the horizontal nanowires, an end of the second gate stack being spaced apart from an end of the first gate stack by a gap; a dielectric structure including a first portion forming a gate spacer along a sidewall of the first gate stack, a second portion forming a gate spacer along a sidewall of the second gate stack, and a third portion completely filling the gap, the third portion being continuous with the first portion and the second portion; and an array having an alternating arrangement of electrically isolated conductive trench contacts and conductive trench contacts coupled to ground, the alternating trench contacts oriented along a direction parallel to the first gate stack and the second gate stack; a computing device, [Item 12] Item 12. The computing device of item 11, comprising the first fin and the second fin. [Item 13] Item 12. The computing device of item 11, comprising a first vertical arrangement of the horizontal nanowires and a second vertical arrangement of the horizontal nanowires. [Item 14] a memory coupled to the substrate; Item 12. The computing device of item 11, further comprising: [Item 15] a communications chip coupled to the substrate Item 12. The computing device of item 11, further comprising: [Item 16] a battery coupled to the substrate Item 12. The computing device of item 11, further comprising: [Item 17] a camera coupled to the substrate Item 12. The computing device of item 11, further comprising: [Item 18] a display coupled to the substrate Item 12. The computing device of item 11, further comprising: [Item 19] Item 12. The computing device of item 11, wherein the component is a packaged integrated circuit die. [Item 20] Item 12. The computing device of item 11, wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

Claims

1. First fin; Second fin; a first gate stack over the first fin; a second gate stack on the second fin, an end of the second gate stack being spaced apart from an end of the first gate stack by a gap; a dielectric structure having a first portion forming a gate spacer along a sidewall of the first gate stack, a second portion forming a gate spacer along a sidewall of the second gate stack, and a third portion completely filling the gap, the third portion being contiguous with the first portion and the second portion; and an array having a periodic arrangement of alternating floating and grounded conductive trench contacts along a direction parallel to the first gate stack and the second gate stack; 1. An integrated circuit structure comprising:

2. 10. The integrated circuit structure of claim 1, wherein the array having a periodic arrangement of alternating floating and grounded conductive trench contacts is a test structure configured for voltage contrast (VC) measurements.

3. a first pair of epitaxial source or drain structures at a first end and a second end of the first fin; and a second pair of epitaxial source or drain structures at the first end and the second end of the second fin; 3. The integrated circuit structure of claim 1 or 2, further comprising:

4. a first pair of conductive trench contacts on the first pair of epitaxial source or drain structures; and a second pair of conductive trench contacts on the second pair of epitaxial source or drain structures; 4. The integrated circuit structure of claim 3 further comprising:

5. 4. The integrated circuit structure of claim 3, wherein the first and second pairs of epitaxial source or drain structures are first and second pairs of non-discrete epitaxial source or drain structures.

6. a first vertical arrangement of horizontal nanowires; a second vertical arrangement of horizontal nanowires; a first gate stack above the first vertical arrangement of the horizontal nanowires; a second gate stack on a second vertical arrangement of the horizontal nanowires, an end of the second gate stack being spaced apart from an end of the first gate stack by a gap; a dielectric structure having a first portion forming a gate spacer along a sidewall of the first gate stack, a second portion forming a gate spacer along a sidewall of the second gate stack, and a third portion completely filling the gap, the third portion being contiguous with the first portion and the second portion; and an array having a periodic arrangement of alternating floating and grounded conductive trench contacts along a direction parallel to the first gate stack and the second gate stack; 1. An integrated circuit structure comprising:

7. 7. The integrated circuit structure of claim 6, wherein the array having a periodic arrangement of alternating floating and grounded conductive trench contacts is a test structure configured for voltage contrast (VC) measurements.

8. a first pair of epitaxial source or drain structures at first and second ends of a first vertical arrangement of the horizontal nanowires; and a second pair of epitaxial source or drain structures at first and second ends of the second vertical arrangement of the horizontal nanowires; 8. The integrated circuit structure of claim 6 or 7, further comprising:

9. a first pair of conductive trench contacts on the first pair of epitaxial source or drain structures; and a second pair of conductive trench contacts on the second pair of epitaxial source or drain structures; 9. The integrated circuit structure of claim 8, further comprising:

10. 9. The integrated circuit structure of claim 8, wherein the first and second pairs of epitaxial source or drain structures are first and second pairs of non-discrete epitaxial source or drain structures.

11. 1. A computing device comprising: a substrate; and Components bonded to the substrate the component has an integrated circuit structure, the integrated circuit structure comprising: a vertical arrangement of first fins or horizontal nanowires; Vertical placement of the second fin or horizontal nanowire; a first gate stack above the first fin or the vertical arrangement of the horizontal nanowires; a second gate stack on the second fin or the vertical arrangement of the horizontal nanowires, the end of the second gate stack being spaced apart from the end of the first gate stack by a gap; a dielectric structure including a first portion forming a gate spacer along a sidewall of the first gate stack, a second portion forming a gate spacer along a sidewall of the second gate stack, and a third portion completely filling the gap, the third portion being contiguous with the first portion and the second portion; and an array having an alternating arrangement of electrically isolated conductive trench contacts and conductive trench contacts coupled to ground, the alternating trench contacts oriented along a direction parallel to the first gate stack and the second gate stack; a computing device,

12. The computing device of claim 11 comprising the first fin and the second fin.

13. The computing device of claim 11 , comprising a first vertical arrangement of the horizontal nanowires and a second vertical arrangement of the horizontal nanowires.

14. a memory coupled to the substrate; The computing device of claim 11 or 12, further comprising:

15. a communications chip coupled to the substrate The computing device of claim 11 or 12, further comprising:

16. a battery coupled to the substrate The computing device of claim 11 or 12, further comprising:

17. a camera coupled to the substrate The computing device of claim 11 or 12, further comprising:

18. a display coupled to the substrate The computing device of claim 11 or 12, further comprising:

19. 13. The computing device of claim 11 or 12, wherein the component is a packaged integrated circuit die.

20. 13. The computing device of claim 11 or 12, wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

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