Integrated measurement systems and methods for synchronous, accurate materials property measurement

Abstract

To provide suitable integrated measurement systems and methods for synchronous, accurate materials property measurement.SOLUTION: A measurement system includes a source unit to provide a source signal to a sample, a voltage source and / or a current source, and a memory. The system also includes a measurement unit configured to acquire from the sample a measurement signal that may be responsive to the source signal, a voltage measuring unit, a current measuring unit, and / or a capacitance measuring unit, and a memory. The system also includes a control unit including a digital signal processing unit, a source converter, and a measurement converter. The system further includes a synchronization unit configured to synchronize clocks of the digital signal processing unit, the source converter, the measurement converter, the source unit, and the measurement unit, a calibration unit for calibrating aspects of the system including the control unit, and a reference voltage supply configured to supply a common reference voltage for the control unit.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to U.S. Provisional Patent Application No. 63 / 057,745, entitled "SYNCHRONOUS SOURCE MEASURE SYSTEMS AND METHODS," filed July 28, 2020, to Fortney, U.S. Provisional Patent Application No. 63 / 016,747, entitled "ADVANCED ANALOG-TO-DIGITAL CONVERSION SYSTEMS AND METHODS," filed April 28, 2020, to Fortney, and U.S. Provisional Patent Application No. 63 / 034,052, entitled "ADVANCED DIGITAL-TO-ANALOG SIGNAL GENERATION SYSTEMS AND METHODS," filed June 3, 2020, to Fortney, each of which is incorporated herein by reference in its entirety.

[0002] This disclosure relates to signal delivery and measurement electronics, analytical instrumentation, software, and infrastructure. More specifically, this disclosure relates to systems that can measure signals for materials and device characterization and other applications under difficult experimental conditions that can cause high levels of noise and interference. [Background technology]

[0003] Materials and device property measurements (e.g., electronic transport properties such as hole, mobility, and carrier concentration) are often highly sensitive to noise, interference, and stray signals. For example, superconducting properties are typically measured at extremely low temperatures (e.g., below 4 K) necessary to observe these properties without excessive noise. These measurements can also require very high magnetic field strengths (e.g., above 5 T), which can complicate the experimental setup. Dealing with noise, interference, and stray signals under these compromising conditions is critical to obtaining reliable and accurate data.

[0004] Experimental setups for measuring these properties currently require several different types of equipment (e.g., lock-in amplifiers, other amplifiers, current sources, voltmeters, ammeters, analog-to-digital (A / D) converters, and other devices). For example, lock-in amplifiers are essential for measuring signals under high interference / noise conditions. They use a known carrier wave to extract the measurement signal and block unwanted or interfering signals. Lock-ins are typically sold as separate components designed to be arranged in a laboratory rack along with the other devices mentioned above. In practice, each instrument is incorporated into the experimental setup as a separate, independent unit. Researchers create the experimental setup by physically and electrically connecting the units.

[0005] User-creation of experimental setups from heterogeneous instrument units makes system-wide noise mitigation difficult and ad hoc, if not impossible. Each unit contributes independently and separately to noise. Each unit has unique, often unpredictable, interference susceptibility. Each unit contributes to different stabilization or transient effects. These different contributions and susceptibilities must be addressed individually. Calibration must be performed individually. Thus, the complexity of interference / noise mitigation and calibration scales with the number of devices involved in the measurement, which can easily and quickly grow large even for relatively modest material properties experiments. This sets a hard limit to the accuracy of such measurement systems.

[0006] Because equipment units often come from different commercial suppliers, compatibility issues limit system-wide noise and interference mitigation. Mitigation techniques involving one or more units working in concert may be impossible or impractical. For example, it may be impossible to partition or shut down digital electronics system-wide, even though digital interference would disrupt sensitive measurements. Because each unit typically has its own clock, precise synchronization may be difficult or impossible. Standard connections (e.g., through the use of BNC connectors and cables and conventional instrument racks) introduce problems. Each connection introduces additional impedance and / or noise. Wires add interference. Stray capacitance from any number of sources disrupts measurements.

[0007] These problems reduce measurement repeatability and accuracy. Different experimental setups may produce different results for the same measurement on the same sample. Therefore, there is an unmet need for accurate, consistent, and reliable materials measurement systems that provide system-wide noise mitigation, interference rejection, source / measurement synchronization, and calibration. There is also an unmet need to reduce the number of noise and interference sources, including those generated by excessive connections, wires, and digital electronics interference. Summary of the Invention [Means for solving the problem]

[0008] Aspects of the present disclosure include a measurement system including a source unit configured to provide a source signal to a sample. The source unit includes at least one of a voltage source and a current source and a memory configured to store a source calibration. The system includes a measurement unit configured to obtain a measurement signal responsive to the source signal from the sample. The measurement unit includes at least one of a voltage measurement unit, a current measurement unit, and a capacitance measurement unit and a memory configured to store a measurement calibration. The system includes a control unit including a digital signal processing unit and a source converter connected between the digital signal processing unit and the source unit. The system includes a measurement converter connected between the digital signal processing unit and the measurement unit, a synchronization unit configured to synchronize clocks of the digital signal processing unit, the source converter, and the measurement converter, a calibration unit for calibrating the system including the control unit, and a reference voltage source configured to provide a common reference voltage for the control unit.

[0009] The control unit may be configured to acquire at least one of calibration data from a self-calibration performed by the source unit and the measurement unit, calibration data from a stored factory calibration, calibration data from a remote source via the Internet, calibration data from a user input, source calibration data from the source unit, and measurement calibration data from the measurement unit. The control unit may be configured to acquire the source calibration and the measurement calibration periodically. The control unit may be configured to acquire at least one of the source calibration from a memory of the source unit when the source unit may not be providing a source signal to the sample and the measurement calibration from a memory of the measurement unit when the measurement unit may not be obtaining a measurement signal from the sample. The control unit may be configured to acquire the source calibration and the measurement calibration in parallel. The digital signal processing unit may store calibration data for at least one of the control unit, the source unit, and the measurement unit. The current source unit may be configured to measure a source current associated with the source signal via a sense resistor and vary a resistance range of the sense resistor according to a magnitude of the source current. The system may include a current source protection unit configured to determine whether the source current exceeds a threshold current, and when the source current exceeds the threshold current, to modify a feedback element of at least one of the source unit and the measurement unit so that the source current falls below the threshold current.

[0010] The synchronization unit may be configured to synchronize the digital signal processing unit, the source converter, and the measurement converter relative to an internal clock signal. The digital signal processing unit may be configured to provide a timestamp for data originating from at least one of the measurement unit and the source unit. The data from the measurement unit may comprise a measurement signal. The data from the source unit may comprise a source signal. The source unit may be configured to deactivate non-analog circuitry when providing the source signal. The measurement unit may be configured to deactivate non-analog circuitry when measuring the measurement signal.

[0011] The digital signal processing unit may be configured to perform at least one of the following on at least one of the measurement signal and the source signal: lock-in analysis; alternating current / direct current (AC / DC) measurement; inductance (L), capacitance (C), and resistance (R) (LCR) measurement; time / range domain presentation; frequency domain analysis; noise analysis; AC / DC supply; control looping; and providing a source signal from more than one source.

[0012] The interface between the source unit and the control unit may comprise a low-impedance buffered analog signal. The interface between the measurement unit and the control unit may comprise at least one of a voltage-mode analog signal interface with a low-impedance transmission and a high-impedance receiving circuit, and a current-mode analog signal interface with a high-output impedance transmission and a low-impedance receiving circuit. The interface signal between at least one of the source unit, the measurement unit, and the control unit may comprise a differential approach for either the transmission circuit or the receiving circuit.

[0013] At least one of the interfaces between the source unit and the control unit may comprise a low-impedance buffered analog signal, and the interface between the measurement unit and the control unit may comprise a low-impedance buffered analog signal. The measurement unit and the source unit may be located remotely from the control unit and the digital signal processing unit. The system may comprise a power supply filter for at least one of the measurement unit and the source unit. The system may comprise a first cable connecting the control unit to the measurement unit and a second cable connecting the control unit to the source unit.

[0014] The digital signal in at least one of the measurement unit and the source unit may be isolated from the control unit. At least one of the source converter and the measurement converter may comprise a gain chain configured to amplify an analog input signal, a range selector configured to select a gain between the analog input signal and multiple analog-to-digital converter (ADC) outputs, each ADC output having a path, and the gain of each output path may be configured by a gain stage in the gain chain, and a mixer configured to combine the multiple ADC outputs into a single mixed output.

[0015] The ADC output path may comprise two ADC output paths that can be independently configured to either a high-range or a low-range path, the low-range path having a first gain for converting an analog input signal and the high-range path having a second gain for converting the analog input signal, the second gain being lower than the first gain; a mixing device configured to combine the lower range output with the higher range output; and a device configured to vary the amount of gain combined from the high-range and low-range paths.

[0016] The source converter may comprise two or more digital-to-analog converters (DACs) combined to generate two or more frequency components. The source converter may comprise a first path for generating a substantially low frequency signal, the first path may comprise a first of the DACs. The source converter may comprise a second path for generating a substantially high frequency signal, the second path may comprise a second of the DACs. The source converter may comprise a data processor for processing the input signal, a combining circuit configured to combine outputs of the first and second paths into a source signal, a feedback section configured to sense the source signal, and a servo loop employing the feedback section and configured to maintain the source signal substantially in accordance with the input signal.

[0017] The system may include at least one of a plurality of source units and a plurality of measurement units. The digital signal processing unit may be configured to perform lock-in signal processing. The lock-in signal processing may be synchronized with the synchronization unit. The lock-in signal processing may process at least one of a fundamental frequency and a harmonic frequency. The control unit may be configured to set a phase relationship between the source unit and the measurement unit. The lock-in signal processing may include providing a lock-in reference for communication between the control unit and at least one of the source unit and the measurement unit. The source unit may be configured to provide DC feedback to the control unit through an analog signal. The digital signal processing unit may be configured to digitally convert the DC feedback and set a DC measurement signal according to the digital DC feedback value.

[0018] The control unit may be configured to measure a parameter of the source signal using a DC signal. The DC feedback signal may be a low-frequency AC signal. The control unit may be configured to assess a type of at least one of the measurement unit and the source unit and configure the digital signal processing unit according to the type. The control unit may be configured to output a DC bias as part of the measurement signal. The source unit may be configured to at least one of limiting a voltage of the source signal below a voltage threshold and limiting a current of the source signal below a current threshold. The system may include an enclosure for at least one of the source unit and the measurement unit, the enclosure including at least one of electrostatic shielding and magnetic shielding.

[0019] The control unit may include a single interface that communicates the source signal, the measurement signal, and control information. The control unit may be configured to perform at least one of channel calibration, seamless ranging, spectrum analyzer noise analysis, and square wave or arbitrary wave demodulation for harmonic acquisition. The system may include a configurable display. The control unit may be configured to display real-time oscilloscope readings. The control unit may be configured to display frequency spectrum readings. The control unit may be configured to perform at least one of factory calibration and self-calibration by applying a signal to a more accurate resistor range, measuring the applied signal across the more accurate range, applying a signal to a less accurate resistor range, measuring the applied signal across the less accurate range, and calibrating the less accurate resistor range using the measured applied signal across the more accurate range and the measured applied signal across the less accurate range.

[0020] The control unit may be configured to perform a voltage measurement mode calibration for the measurement unit by measuring an offset error in the measurement unit, storing the offset error in a memory of the measurement unit, connecting an amplifier associated with the measurement unit to a reference voltage, measuring, via the control unit, a gain error from applying the reference voltage to the amplifier, storing the measured gain error in a memory of the measurement unit, reading, via the control unit, at least one of the stored gain errors from the memory of the measurement unit, and applying the offset error and at least one of the stored gain errors to correct the voltage measurement.

[0021] The control unit may be configured to perform current-mode measurement calibration on the measurement unit by disconnecting the input connector of the control unit, connecting the input connector of the measurement unit to ground, configuring the measurement unit in a voltage measurement mode, measuring a voltage offset error of the amplifier via the measurement unit in the voltage measurement mode, applying analog correction to reduce the measured voltage offset to approximately zero, switching the measurement unit to a current measurement mode and floating the input to the measurement unit, determining a voltage offset error between the measurement unit and the control unit by configuring the measurement unit in a high current range via the control unit and measuring the resulting voltage at the control unit, adjusting a leakage current until the current measurement of the measurement unit is approximately zero, storing the adjusted leakage current and voltage offset error in a memory of the measurement unit via the control unit, reading at least one of the adjusted leakage current and voltage offset error via the control unit, and applying the adjusted leakage current and voltage offset error to correct the current measurement of the measurement unit.

[0022] The source unit may be configured to obtain the measurement signal and the measurement unit may be configured to provide the source signal. The system may include a matrix switching control unit configured to provide a set of switches to scan the source signal and the measurement signal. A power supply may be configured to provide power to the control unit, the source unit, and the measurement unit referenced to a common ground.

[0023] Aspects of the present disclosure include a method including providing a source signal to a sample via a source unit including at least one of a voltage source and a current source. The source unit includes a memory configured to store a source calibration. The method includes obtaining a measurement signal responsive to the source signal from the sample via a measurement unit. The measurement unit includes at least one of a voltage measurement unit, a current measurement unit, and a capacitance measurement unit, and a memory configured to store the measurement calibration. The method includes receiving the measurement signal from the measurement unit by a control unit. The control unit includes a digital signal processing unit, a source converter connected between the digital signal processing unit and the source unit, and a measurement converter connected between the digital signal processing unit and the measurement unit. The control unit includes a synchronization unit configured to synchronize clocks of the digital signal processing unit, the source converter, and the measurement converter. The control unit includes a calibration unit for calibrating aspects of the system including the control unit, and a reference voltage source configured to provide a common reference voltage for the control unit. The present invention provides, for example, the following. (Item 1) 1. A measurement system comprising: a source unit configured to provide a source signal to a sample, said source unit comprising: at least one of a voltage source and a current source; a memory configured to store a source calibration; a power source unit comprising: a measurement unit configured to obtain a measurement signal responsive to the source signal from the sample, the measurement unit comprising: at least one of a voltage measurement unit, a current measurement unit, and a capacitance measurement unit; a memory configured to store the measurement calibration; a measurement unit comprising: A control unit, a digital signal processing unit; a source converter connected between the digital signal processing unit and the source unit; a measurement converter connected between the digital signal processing unit and the measurement unit; a synchronization unit configured to synchronize the clocks of the digital signal processing unit, the source converter, and the measurement converter; a calibration unit for calibrating the system including the control unit; a reference voltage source configured to provide a common reference voltage for the control units; a control unit comprising: A system comprising: (Item 2) The control unit calibration data from a self-calibration performed by the source unit and the measurement unit; stored calibration data from the factory calibration; calibration data from a remote source via the internet; Calibration data from user input; and the source calibration data from the source unit; the measurement calibration data from the measurement unit; Item 1. The system of item 1, configured to acquire at least one of: (Item 3) The control unit periodically performing said source calibration and measurement calibration; the source calibration from a memory of the source unit when the source unit is not providing the source signal to the sample; the measurement calibration from a memory of the measurement unit when the measurement unit is not obtaining a measurement signal from the sample; The source calibration and measurement calibration are carried out in parallel. 3. The system of any one of items 1 and 2, configured to obtain at least one of: (Item 4) the digital signal processing unit stores calibration data relating to at least one of the control unit, the source unit, and the measurement unit; the measurement unit and the source unit are located remotely from the control unit and the digital signal processing unit; the system comprising a first cable connecting the control unit to the measurement unit and a second cable connecting the control unit to the source unit; the digital signal in at least one of the measurement unit and the source unit is isolated from the control unit; a measurement interface between the measurement unit and the control unit and a source interface between the source unit and the control unit are separated from each other within a cable; The system comprises a plurality of source units. The system comprises a plurality of measurement units. The source unit is configured to obtain the measurement signal; and The measurement unit is configured to provide the source signal. The system according to any one of items 1-3, wherein the system is at least one of the following: (Item 5) 5. The system of any one of items 1-4, wherein the current source unit is configured to measure a source current associated with the source signal through a sense resistor and vary a resistance range of the sense resistor according to the magnitude of the source current. (Item 6) a current source protection unit configured to determine whether the source current exceeds a threshold current, and when the source current exceeds the threshold current, modify a feedback element of at least one of the source unit and the measurement unit so that the source current falls below the threshold current; a voltage source protection unit configured to determine whether a source voltage exceeds a threshold voltage, and when the source voltage exceeds the threshold voltage, modify a feedback element of at least one of the source unit and the measurement unit so that the source voltage falls below the threshold voltage; Item 6. The system of item 5, further comprising at least one of: (Item 7) 7. The system of any one of items 1-6, wherein the synchronization unit is configured to synchronize the digital signal processing unit, the source converter, and the measurement converter with respect to an internal clock signal. (Item 8) 8. The system of any one of items 1-7, wherein the digital signal processing unit is configured to provide a timestamp for at least one of the measurement signal and the source signal. (Item 9) the source unit is configured to deactivate non-analog circuitry when providing the source signal; and The measurement unit is configured to deactivate a non-analog circuit when measuring the measurement signal. 9. The system according to any one of items 1-8, wherein the system comprises at least one of the following: (Item 10) The digital signal processing unit performs the following on at least one of the measurement signal and the source signal: Lock-in analysis and AC / DC measurement and Inductance (L), capacitance (C), and resistance (R) (LCR) measurements and Time / range domain presentation, Frequency domain analysis and Noise analysis and AC / DC supply and Control looping; providing said source signals from more than one source; 10. The system of any one of items 1-9, configured to implement at least one of: (Item 11) At least one of the interfaces between the source unit and the control unit comprises a low impedance buffered analog signal, and the interface between the measurement unit and the control unit comprises: a voltage mode analog signal interface with low impedance transmit and high impedance receive circuitry; Current-mode analog signal interface with high output impedance transmit and low impedance receive circuitry 11. The system of any one of items 1-10, comprising at least one of: (Item 12) the power supply is configured to provide power to the control unit, the source unit, and the measurement unit referenced to a common ground; the system comprising a power supply filter for at least one of the measurement unit and the source unit; and At least one of the measurement unit and the source unit is powered from at least one of an isolated power converter from the control unit, an isolated external power source, and battery power. 12. The system of any one of items 1-11, wherein the system comprises at least one of: (Item 13) At least one of the source converter and the measurement converter a gain chain configured to amplify the analog input signal; a range selector configured to select a gain between the analog input signal and a plurality of analog-to-digital converter (ADC) outputs, each ADC output having a path, the gain of each output path being configured by a gain stage in the gain chain; a mixer configured to combine the multiple ADC outputs into a single mixed output; 13. The system of any one of items 1-12, comprising: (Item 14) The source converter two or more digital-to-analog converters (DACs) that combine to generate one or more frequency components; a first path for generating a substantially low frequency signal, the first path comprising a first of the DACs; a second path for generating a substantially high frequency signal, the second path comprising a second of the DACs; and a data processor for processing the input signal; a combining circuit configured to combine the outputs of the first and second paths into the source signal; a feedback portion configured to sense the source signal; a servo loop adapted to employ said feedback portion and maintain said source signal substantially in accordance with said input signal; 14. The system of any one of items 1-13, comprising: (Item 15) The digital signal processing unit is configured to perform lock-in signal processing, the lock-in signal processing comprising: synchronized with the synchronization unit; Processing at least one of the fundamental frequency and the harmonic frequency; and providing a lock-in reference for communication between the control unit and at least one of the source unit and the measurement unit. 15. The system of any one of items 1-14, wherein the system comprises at least one of: (Item 16) 16. The system of any one of items 1-15, wherein the control unit is configured to measure a parameter of the source signal using a feedback signal that is one of a DC signal and a low frequency AC signal. (Item 17) 17. The system of any one of items 1-16, wherein the control unit is configured to assess the type of at least one of the measurement unit and the source unit and configure the digital signal processing unit according to the type. (Item 18) an enclosure for at least one of the source unit and the measurement unit, the enclosure comprising at least one of an electrostatic shield and a magnetic shield; 1. A configurable display, the configurable display comprising: Displaying real-time oscilloscope readings; Displaying the frequency spectrum reading; a configurable display configured to perform at least one of: 18. The system of any one of items 1-17, further comprising at least one of: (Item 19) The control unit Applying the signal to a more accurate resistor range; measuring the applied signal across the more accurate range; applying said signal to a less accurate resistor range; measuring the applied signal across the less accurate range; calibrating the less accurate resistor range using the measured applied signal across the more accurate range and the measured applied signal across the less accurate range; and 19. The system of any one of items 1-18, configured to perform at least one of factory calibration and self-calibration by (Item 20) The control unit Measuring an offset error in a measurement unit; storing the offset error in a memory of the measurement unit; connecting an amplifier associated with said measurement unit to a reference voltage; measuring, via the control unit, a gain error from applying the reference voltage to the amplifier; storing the measured gain error in a memory of the measurement unit; reading at least one of the stored gain errors from a memory of the measurement unit via the control unit; applying at least one of the offset error and the gain error to correct the voltage measurement; performing a voltage measurement mode calibration on the measurement unit by disconnecting the input connector of the control unit; connecting the input connector of the measurement unit to ground; configuring the measurement unit in a voltage measurement mode; measuring a voltage offset error of an amplifier via the measurement unit in the voltage measurement mode; applying an analog correction to reduce the measured voltage offset to approximately zero; switching the measurement unit into a current measurement mode and floating the input to the measurement unit; determining a voltage offset error between the measurement unit and the control unit by configuring the measurement unit in a high current range via the control unit and measuring the resulting voltage at the control unit; adjusting the leakage current until the current measurement of the measurement unit is approximately zero; storing, via the control unit, at least one of the adjusted leakage current and the voltage offset error in a memory of the measurement unit; reading at least one of the regulated leakage current and the voltage offset error via the control unit; applying at least one of the adjusted leakage current and the voltage offset error to correct the current measurement of the measurement unit; performing a current mode measurement calibration on the measurement unit by 20. The system of any one of items 1-19, configured to perform at least one of the following: (Item 21) The control unit calibrating the measurement channels against a master voltage reference; commanding the source unit to apply a positive signal in place of the source signal; measuring the commanded positive signal via the calibrated measurement channel to provide a measured positive signal; commanding the source unit to apply a negative signal in place of the source signal; measuring the applied negative signal via the calibrated measurement channel to provide a measured negative signal; commanding the source unit to apply a zero signal in place of the source signal; measuring the applied zero signal via the calibrated measurement channel to provide a measured zero signal; generating a source unit calibration based on a difference between at least one of the commanded positive, negative, and zero signals and the measured positive, negative, and zero signals; 21. The system of any one of items 1-20, configured to: (Item 22) 1. A method comprising: at least one of a voltage source and a current source; a memory configured to store a source calibration; providing a source signal to the sample via a source unit comprising: obtaining a measurement signal from the sample via a measurement unit responsive to the source signal, the measurement unit comprising: at least one of a voltage measurement unit, a current measurement unit, and a capacitance measurement unit; a memory configured to store the measurement calibration; and receiving the measurement signal from the measurement unit by a control unit, the control unit comprising: a digital signal processing unit; a source converter connected between the digital signal processing unit and the source unit; a measurement converter connected between the digital signal processing unit and the measurement unit; a synchronization unit configured to synchronize the clocks of the digital signal processing unit, the source converter, and the measurement converter; a calibration unit for calibrating aspects of the system including the control unit; a reference voltage source configured to provide a common reference voltage for the control units; To have A method comprising: [Brief explanation of the drawings]

[0024] [Figure 1] FIG. 1 illustrates an exemplary M81 platform or system 100 within the context of the present disclosure.

[0025] [Figure 2] FIG. 2 illustrates another variation of the M81 platform or system 200 within the context of the present disclosure.

[0026] [Figure 3A] FIG. 3A illustrates another M81 platform or system 300 within the context of the present disclosure.

[0027] [Figure 3B] FIG. 3B is a first portion of a flowchart 330 illustrating how the head 102 and pod 104 may cooperate to calibrate a measurement unit or pod configured to measure voltage.

[0028] [Figure 3C] FIG. 3C is a continuation of flowchart 330 of FIG. 3B.

[0029] [Figure 3D] FIG. 3D is a first portion of a flowchart 340 illustrating how the head 102 and pod 104 may cooperate to calibrate a measurement unit or pod configured to measure current.

[0030] [Figure 3E] FIG. 3E is a continuation of flowchart 340 of FIG. 3D.

[0031] [Figure 3F] FIG. 3F is a first portion of a flowchart 360 illustrating an example calibration routine 360 ​​for a source pod 104 (or a pod 104 in source mode) driven by a head 102.

[0032] [Figure 3G] FIG. 3G is a second portion of the flowchart 360 of FIG. 3F.

[0033] [Figure 4] FIG. 4 illustrates some example features of a source pod 104 within the context of the present disclosure.

[0034] [Figure 5A] FIG. 5A shows a direct comparison of the noise for a 1 μA current source in systems 100, 200, and 300 with the noise in a more conventional setup.

[0035] [Figure 5B] FIG. 5B shows a stretching of signal A from pod 104 within the context of the present disclosure.

[0036] [Figure 5C] FIG. 5C shows the stretched signal B from FIG. 5A.

[0037] [Figure 6A]FIG. 6A illustrates the effects of mismatched time bases in a conventional instrument rack that may be avoided by using the shared synchronized clock 302 of the present disclosure.

[0038] [Figure 6B] FIG. 6B illustrates another time-based effect of mismatch in a conventional instrument rack.

[0039] [Figure 7] FIG. 7 illustrates a source signal chain 700 between an example head unit 102 and an example source pod 104 in a variation of systems 100, 200, and 300.

[0040] [Figure 8] FIG. 8 illustrates an exemplary source signal chain 800 in a variation of systems 100, 200, and 300 in which alternating current (AC) 802 and direct current (DC) 804 inputs are digitally summed together by a mixer 806.

[0041] [Figure 9] FIG. 9 illustrates an exemplary source signal chain 900 in which AC 902 and DC 904 inputs are separately converted by DACs 906 and 908 in variations of systems 100, 200, and 300, respectively.

[0042] [Figure 10] FIG. 10 illustrates another exemplary source signal chain 1000 in a variation of systems 100, 200, and 300 in which the AC circuitry (the "AC configuration") is prevented from affecting the accuracy of the DC circuitry.

[0043] [Figure 11] FIG. 11 illustrates another example source signal chain 1100 having a DC feedback loop within the context of the present disclosure.

[0044] [Figure 12]FIG. 12 illustrates another example source signal chain 1200 with digitized feedback within the context of this disclosure.

[0045] [Figure 13] FIG. 13 illustrates one exemplary variation of a digitally synthesized source channel 1300 within the context of this disclosure.

[0046] [Figure 14] FIG. 14 shows an example variation of a source wave table 1400 that may be used in conjunction with the digital source 1300 within the context of the present disclosure.

[0047] [Figure 15] FIG. 15 is a waveform 1500 generated by plotting the source wave table 1400 that may be used in conjunction with the digital source 1300 within the context of the present disclosure.

[0048] [Figure 16A] FIG. 16A shows the stepped waveform from low-pass filtering the waveform of FIG.

[0049] [Figure 16B] FIG. 16B shows a smoothed version of the waveform of FIG. 16A.

[0050] [Figure 17] FIG. 17 illustrates exemplary features of the measurement pod 104 within the context of the present disclosure.

[0051] [Figure 18] FIG. 18 illustrates the measurement signal chain between an example head unit and an example measurement pod 104.

[0052] [Figure 19] FIG. 19 compares a voltage measurement with seamless ranging 1902 within the context of the present disclosure with the same measurement made with a conventional setup 1904.

[0053] [Figure 20] FIG. 20 is a block diagram of one variation of implementing seamless ranging 2000 via dual amplification chains within the context of the present disclosure.

[0054] [Figure 21] FIG. 21 shows a block diagram of another example amplification chain 2100 for use in seamless ranging within the context of the present disclosure.

[0055] [Figure 22] Figure 22A provides a schematic example of an automatic ranging algorithm 2200 that may be used in conjunction with seamless ranging within the context of the present disclosure. Figure 22B shows exemplary experimental data used by the automatic ranging algorithm 2200.

[0056] [Figure 22C] FIG. 22C is the first portion of a flowchart detailing the automatic ranging algorithm 2220.

[0057] [Figure 22D] FIG. 22D is the second portion of the flowchart detailing the auto ranging algorithm 2220.

[0058] [Figure 23] FIG. 23 illustrates a lock-in technique for multiplying 2304 a measurement signal 2302 with a known reference source 2306 to generate a demodulated signal 2308 within the context of this disclosure.

[0059] [Figure 24] FIG. 24 shows the phase difference (θ) between the multiplied signals.

[0060] [Figure 25] FIG. 25 shows how the M81 100, 200, and 300 variations may also utilize a phase-locked loop (PLL) 2500.

[0061] [Figure 26] FIG. 26 illustrates an example reference out 2600 within the context of the present disclosure.

[0062] [Figure 27] FIG. 27 shows how the M81 100, 200, and 300 variations can utilize a measurement digital signal processor (DSP) 2700.

[0063] [Figure 28A] FIG. 28A illustrates the housing for the source / measurement pod 104.

[0064] [Figure 28B] FIG. 28B illustrates the housing for the source / measurement pod 104.

[0065] [Figure 29] Figure 29A is an exemplary display for head 102. Figure 29B is another exemplary display for head 102. DETAILED DESCRIPTION OF THE INVENTION

[0066] Detailed Description The platform or system disclosed herein, referred to as "M81," allows for systematic noise and interference mitigation not possible with traditional ad-hoc rack-based systems. It provides an all-in-one experimental platform that combines source and / or measurement amplifier pods, lock-in amplifier capabilities, digital multimeters (DMMs), DC / AC and other signal generators, etc., with time-synchronized operation and advanced source and measurement.

[0067] The term "M81" is used synonymously with the term "system." Thus, the phrase "systems 100, 200, and 300," referring to the systems shown in Figures 1, 2, and 3, is synonymous with the term "M81 100, 200, and 300." The term "M81" will be used generally to describe various systems disclosed herein or otherwise encompassed by the general inventive concept.

[0068] The M81 incorporates numerous innovative solutions for mitigating noise and interference in materials measurement systems. This includes remote, automatic, and periodic calibration of the entire system for noise reduction. It calibrates the entire measurement and signal chain of the entire system, rather than calibrating each of its individual components separately. This provides much more accurate calibration than can be achieved in traditional rack-based systems. The system-wide controlled shutdown of the digital electronics during measurements prevents interference. The system-wide clock synchronizes supply, measurement, and analysis. It provides excitation / input signals from stored digital signal models. It feeds these analog signals to the sample through a hybrid signal chain containing both AC and DC components, both with independently configurable gain. The signal chain can stabilize the output based on feedback from the sample stage. The system includes a balanced current supply that matches the input and output currents to and from the sample, protecting the sample and system from large fluctuations. Its "seamless ranging" technique protects measurements from glitches and transients as they vary over orders of magnitude. These and other solutions are detailed below. Features and capabilities described in the context of one M81 variant apply to other variants of M81, whether explicitly discussed or implied by this disclosure.

[0069] Measurement system overview

[0070] FIG. 1 illustrates an exemplary M81 platform or system 100, including an instrument “head” or control unit 102 and several exemplary remote “pods” 104. As shown in FIG. 1, the pods 104 may be source units 104a-104c that can provide probe signals to a sample (not shown) on a sample stage 106. Note that the words “pod” and “unit” are used interchangeably herein, such that a reference to a “source pod” is synonymous with a reference to a “source unit,” and a reference to a “measurement pod” is synonymous with a reference to a “measurement unit.” Similarly, the words “head” and “control unit” are used interchangeably. The sample stage 106 may include various components 107, such as a cryostat, Peltier cooler, power supply, heat sink, auxiliary electronics, and / or mechanical positioning systems, balancing systems, air tables, weights, etc.

[0071] The pod 104 may include a measurement unit 104d configured to measure a signal from the sample. In this variation, the system 100 includes three remote pods 104a-c that act as signal sources and one remote pod 104d that acts as a signal measurer. It should be understood that this configuration is merely exemplary. In practice, source pods 104a-c may function as measurement pods (e.g., 104d), and vice versa. In variations, each pod 104 may have a certain type or configuration (e.g., the measurement, source, and / or specific feature set shown in Figures 4 and 17 below). In these variations, the head 102 may be capable of detecting the type of pod 104 upon connection. In response to pod 104 type detection, the head 102 may configure itself and the rest of the system in an appropriate manner for the detected pod type. For example, the head 102 may self-calibrate and / or perform an appropriate system-wide calibration for the detected pod type. The head 102 may implement other configurations (eg, it may configure the digital signal processing unit 326, etc.) according to the detected pod type.

[0072] System 100 may include any suitable number of source and measurement pods 104. In other variations, M81 may include head unit 102 without requiring pods 104. Note that system 100 may include any of the features described in other variations below (e.g., variations 200 and 300). These include, for example, shared synchronized clock 302, described in the context of FIG. 3A below.

[0073] While FIG. 1 shows the head 102 with multiple connections (e.g., four connections 102a to the pod 104 and multiple front panel connections 102b), in variations, it may have only one interface with the outside world. For example, the head 102 may have a single universal serial bus (USB) connection, allowing the head to transmit and receive data and control information to and from the pod 104. The data may include data related to providing source signals via the pod 104, reading measurement signals from the pod 104, processing those signals, obtaining other feedback from the measurements, and providing processed data, including processed feedback, to the pod 104. The control information may include any calibration, diagnostic, and configuration information disclosed herein. For example, the control information may include instructions to provide specific input signals to the sample, extract specific outputs, calibrate devices in the system 100, and / or control aspects of the sample stage 106, including the cryogenic nature of that stage 106. This may include calibration information from any unit in the system 100.

[0074] FIG. 1 further shows that the head 102 includes a display 102c. The display 102c may be a touchscreen. It may be configurable, meaning that it may be configured to display any of the data, signals, processed information, and control functions described herein. The display 102c may be configured to display oscilloscope functions, for example, when an aspect of the system 100 is used as an oscilloscope. These oscilloscope readings may be displayed in real time. The display 102c may also display, for example, a frequency spectrum. The display 102c may be configured to display other data, including any data collected by the measurement pod 104. The display 102c may further be configured to display the status of any units in the system 100, the status of any communications to and from any units in the system 100, and diagnostic information regarding any measurement or signal feed to / from the sample 106. The display may be configured to simultaneously display multiple parameters, which may be configurable by the user or through a remote interface. The display 102c may also be configured to display, among other things, signal noise, interference, and / or spectrum analysis. The display 102c may further be configured to display any features of a graphical user interface (GUI) for interacting with any aspect of the system 100.

[0075] FIG. 1 shows that the head 102 can include a case or enclosure 102d. The case or enclosure 102d can be made of a material that provides electrostatic shielding (e.g., plastic or rubber). It can also include a metallic material for electromagnetic shielding. The case can be made of any suitable material. It can include any mechanical or electrical interfaces as needed. For example, the case 102d can include hooks, fasteners, or grooves so that it can fit into a laboratory rack. It can also include legs, support posts, or stands so that it can stand alone on a table or desktop. It can also include wall or ceiling mounts, etc.

[0076] Other variations include any suitable number of heads, source pods, and measurement pods 104. For example, FIG. 2 shows another exemplary variation 200 in which the head unit 102 may have six channels that can support three measurement-type pods 104e and three source-type pods 104f. In this variation, the M81 is also shown connected to an optional computer 108 and three exemplary devices under test (DUTs) 110 in the sample stage 106. Again, this configuration is merely exemplary. There is no requirement for an equal number of measurement pods 104e and source pods 104f. One source 104f may, for example, provide excitation signals for all three DUTs 110.

[0077] As used herein, the acronym "DUT" will be used synonymously with "sample." It should be understood that either a DUT or a "sample" can be a device or a sample of a material. Often, in the context of materials measurements disclosed herein, a device (e.g., a transistor) is created for the express purpose of testing the material (e.g., semiconductor material) in the created device.

[0078] FIG. 3A shows another variation 300 of the M81 as a high-level diagram. FIG. 3A illustrates information shared among the components of variation 300. For example, FIG. 3A shows how the head or control unit 102 may handle analog to digital (and vice versa) signal conversion. The source and measurement pods 104 shown in FIG. 3A are not unique. They can be used for different applications.

[0079] FIG. 3A also shows a shared synchronization clock 302 connected to each of the source channel 304 and the measurement channel 306. The clock 302 may provide shared synchronization to each of the signals derived from the measurement and source pod 104, any converters or other electronics in the source channel 304 and the measurement channel 306, and the head 102 itself. Having a shared clock allows for automatic synchronization of all components in the system 300, avoiding problems caused by synchronization glitches or imperfections between any one of these components. The shared synchronization clock 302 may be synchronized to an external or internal clock of the head 102. The source channel 304 and the measurement channel 206 may also provide an interface between the pod 104 and the head 102 with an analog signal that is immune to cable length and external RF noise. All of these functions of the shared synchronization clock 302, the source channel 304, and the measurement channel 306 will be discussed in further detail below.

[0080] As also shown in FIG. 3A , the head 102 may have ports (e.g., monitor out, reference in, and reference out ports 308, digital I / O port 310, and auxiliary I / O port 312) that allow the head 102 to connect to other hardware 314. The other hardware 314 may include anything suitable for collecting and analyzing data from and / or providing input to the system 300. Examples of other hardware 314 enabled by these connections include a laboratory oscilloscope, a programmable logic controller (PLC), a laptop or other computer, a monitor, a matrix of switches, a reference signal input, etc. FIG. 3A also shows how the head 102 can be connected to the external computer 108 by a suitable connection mechanism 316, including USB, Ethernet, general-purpose interface bus (GPIB), cellular data, and wireless networking technologies (Wi-Fi). A suitable distance 318 can be maintained between the head 102 and the pod 104 so that operation of the head 102, and in particular its digital circuitry, causes little or no interference to measurements at the location of the DUT 110.

[0081] 3A also shows that the head has a calibration memory 320 and the pod has a calibration memory 322 for storing calibrations of any aspect of the system. For example, calibration memories 320 and 322 may store calibration information for each of the heads 102 themselves and / or the pods 104. Calibration memories 320 and 322 may include the following information: actual voltage of the master reference, gain compensation coefficients (measured source), offset compensation coefficients (measured and source), bias current compensation coefficients, voltage compensation, and common mode reduction coefficients.

[0082] Calibration information may be input by any suitable means. For example, calibration information may be installed on calibration memories 320 and 322 at the factory. It may be downloaded from the internet and / or provided via user input. Components including head 102 and pod 104 may each provide information from performing a self-calibration procedure. Head 102 may provide calibration to pod 104, or vice versa. Calibration information may also be stored in other devices (e.g., diagnostic equipment, external computers, multimeters, etc.) connected to system 300, although not shown. Calibration information on either of calibration memories 320 and 322 may be periodically updated. Calibration information stored on the memory of any device (e.g., head 102 or pod 104) may be updated (e.g., via calibration) when the device is not in use. Calibration for head 102 and pod 104 may be stored by digital signal processing unit 324. Calibration may include multiple methods and components for different ranges of calibration. For example, the benefits of resistors with very different resistance accuracy and temperature dependence can be leveraged to calibrate ranges using resistors with less accuracy or that drift more with temperature and time. GΩ resistors can be advantageously used for certain calibration aspects because they offer very low current noise. However, the resistance value of GΩ resistors is not always precisely known and can be somewhat unstable over time. MΩ-range resistors are more stable over time, although their calibration suffers from more noise associated with larger currents. Thus, MΩ-range resistors (100 MΩ) can be used to calibrate the GΩ range, using the low noise benefits of GΩ and the high stability benefits of MΩ, and vice versa. The same can be true for lower-value resistors. For example, a typical 10 Ω resistor has better accuracy and drift compared to a 1 Ω resistor. In many cases, using a 1 Ω resistor is advantageous when measuring larger currents, either as an external sensing element or as part of a source or measurement circuit.

[0083] As discussed above, systems 100, 200, and 300 can be calibrated in several different ways. Although not shown in FIG. 1 , each pod 104 has inputs / outputs that allow connection to precision signal sources and measurement devices (e.g., external voltmeters, ammeters, current sources, voltage sources). These inputs / outputs allow for local calibration on the pod 104 itself, much as this is done for individual components on a conventional rack system.

[0084] However, the M81 systems 100, 200, and 300 also offer full internal calibration. This allows the use of sensitive electronics in the head 102 to calibrate measurement offsets / errors / variations to / from the pod 104 throughout the entire system 100, 200, and 300. That is, full internal calibration calibrates all idiosyncrasies in the entire signal chain, from the measurement / source to the analysis electronics and vice versa. This results in much higher accuracy. It is also much easier to implement. System-wide calibration functions can be initiated via a GUI on the screen 102c and / or a button on the case 102d. They can be set to run automatically and periodically. More specific functionality of full internal calibration is discussed below.

[0085] 3B and 3C are a flowchart 330 illustrating how the head 102 and the pod 104 may cooperate for calibration and both measure, update, and store calibrations in memories 320 and 322. Specifically, the flowchart, algorithm, or routine (used interchangeably herein) 330 calibrates measurements received at the head 102 from the measurement pod 104 when the pod 104 is configured to measure a voltage signal from the sample 110. The routine 330 is primarily driven by the head 102.

[0086] Turning to FIG. 3B , in step 333, the offset error is measured in the pod 104 for at least one hardware input configuration of the pod 104. The hardware configuration generally relates to the type of measurement pod being used and its associated features (see, e.g., the feature list in FIG. 17 ). Typically, different hardware input configurations contain different components that affect the error being calibrated. For example, different hardware configurations may require the use of different feedback resistors, gain / amplifier configurations, or other components (e.g., DACs) to process the signal. The offset error for a particular hardware configuration is the difference between the voltage measured by the hardware configuration and the actual (known) input voltage. In step 333, the input to the pod 104 can be disconnected from external measurement and connected to ground to ensure that the actual known input voltage is zero. Other known input voltages (e.g., a known, stable voltage reference such as a master reference MR) can also be used. The offset error is then the measured voltage under these conditions. The offset error is stored as a calibration correction in the memory of the pod 104. In step 334, the head 102 reads the offset error calibration from the memory of the pod 104. In step 335, the head 102 may apply an offset correction based on the offset error measured in step 334 to the voltage measurement for the hardware configuration. Alternatively, step 334 may be omitted and the correction not applied until step 339. In step 336, the head 102 connects a reference voltage from a master reference MR to the amplifier input. The master reference MR may be, for example, a stable and reliable voltage reference that may be anywhere in the system, for example, within the head 102. The reference voltages may be, for example, positive full-scale, negative full-scale, positive mid-scale, and negative mid-scale voltages. The voltage reference chosen is appropriate for the hardware configuration of the pod 104.

[0087] 3C, in step 337, head 102 measures the gain error for the hardware configuration by applying a reference voltage to the amplifier input in step 336. The gain error is measured, for example, by taking the difference between the predicted, expected, or desired gain and the measured gain. Many factors can contribute to the gain error and changes in the gain error. For example, feedback resistors in an instrumentation amplifier topology can change slightly over time and temperature. If the amplifier is changed for reasons explained below, the new amplifier will have a different gain error that should be compensated for by routine 330.

[0088] The head 102 stores the gain error as a calibration in the memory of the pod 104 in step 338. In step 339, the head 102 reads the gain error stored in the memory of the pod 104 and applies the gain correction to the voltage measurements for at least one hardware configuration of the pod 104. One common technique for applying the gain correction is to multiply the expected result of the voltage measurement by the inverse of the gain error. Any other suitable method of using the gain error correction is envisioned. After this gain correction or calibration is completed, the input may be reconnected to the external signal and measurements may begin. At this stage, the head 102 may also apply the offset error calibration of step 334 as a correction for the voltage measurements. The gain correction and offset error correction may be applied to all voltage measurements by the pod 104 until the head 102 resumes calibration by re-executing the algorithm 330.

[0089] 3D and 3E are another flowchart 340 illustrating how the head 102 and pod 104 may cooperate to calibrate the pod 104 configured to measure a current signal from the sample 110. The routine 340 is primarily driven by the head 102.

[0090] Turning to FIG. 3D, in step 341, the input of measurement pod 104 is disconnected from the front-end amplifier and connected to ground to protect the external sample from possible switching transients. In step 343, measurement pod 104 is configured in a voltage measurement mode with gain (e.g., voltage amplifier topology) to read the voltage offset error associated with the front-end amplifier when the front-end amplifier input is connected to ground. This is similar to the voltage offset error measurement detailed in step 333. The voltage offset error is the difference between the measured voltage and zero (because the amplifier input is set to ground). This is the voltage offset of the “front-end” amplifier, or amplifier that will connect to the sample. The first amplification stage, or front-end amplifier, connects to the device under test and is often the primary source of offset and leakage current. Exemplary “front-end” amplifiers are amplifiers 720, 810, 912, 1018, and 1114 (FIGS. 7, 8, 9, 10, 11, and 18). A front-end amplifier may include one or more amplifiers.

[0091] In step 344, the head 102 applies analog correction to reduce the front-end amplifier voltage offset error measured in step 343 until the pod 104 measures near-zero voltage (e.g., only a few tenths of a volt, a few mV, or a few μV). Analog offset correction may include, for example, applying an equal and opposite voltage to reduce, minimize, or eliminate the voltage offset error. In step 345, the head 102 switches the measurement pod 104 to a current measurement mode. In step 345, the pod 104 input may be disconnected from ground and left floating. In step 346, the head 102 determines the voltage offset error between the measurement pod 104 and the head 102 by configuring the measurement pod 104 in a high current range or even the highest current range (e.g., by switching in a lower feedback resistor) and measuring the resulting voltage at the head 102. Because the voltage offset error of the front-end amplifier was previously nulled in step 344, the front-end amplifier is set to provide the lowest offset current. Any remaining offset measured is due to a voltage offset in the gain component between the front-end amplifier and the measurement converter. Because the offset current flows through the feedback resistor and results in a small voltage at the output of the front-end amplifier, setting the front-end amplifier to a high current range results in a small gain on the current offset. Multi-stage amplifier configurations are typically used when large gain or filtering is required to amplify the signal being measured. These include, for example, system 700 of FIG. 7 or any of the amplifiers dedicated to the head 102 in FIGS. 20 and 21. In step 346, the voltage offset error between the front-end amplifier of the measurement pod 104 and the head 102 measured in step 346 is determined. This voltage offset error will be used to calibrate errors resulting from transmitting the measurement signal from the pod 104 to the head 102.

[0092] 3E , in step 347, the head 102 adjusts the leakage current (e.g., through a feedback resistor in the front-end amplifier) ​​for one or more of the current ranges until the pod 104 measures near-zero current (e.g., only a few tenths of an ampere (A), a few milliamperes (mA), or a few microamperes (μA)). Leakage current compensation for one or more of the ranges is a current applied in the opposite direction of the measured current to reduce, minimize, or zero the measured current when no current is flowing into the pod 104. The head 102 may use analog techniques to adjust the leakage current, for example, by installing a converter that couples a compensation current into the circuit until the net measured current is zero. The leakage current adjustment may be implemented for hardware input configurations. In step 348, the head 102 stores the leakage current of step 347 and / or the voltage offset error of step 343 in memory on the pod 104 as a calibration correction. In step 349, head 102 reads the calibration corrections stored in memory of pod 104 in step 348 and applies at least one of the calibration corrections to measurements for each hardware configuration of pod 104. Note that current measurement gain error can also be calibrated to a master voltage reference MR or by using an accurate current source derived from a stable current source located within pod 104. The calibration correction of step 349 can be applied to all current measurements by pod 104 until head 102 resumes calibration by re-executing algorithm 340.

[0093] 3F and 3G present another flowchart illustrating an exemplary calibration routine 360 ​​for a source pod 104 (or a pod 104 in source mode) driven by a head 102. Unlike the calibration routine 350, this calibration compares the source signal measured by the head 102 via a fully calibrated measurement channel to the actual source signal.

[0094] In step 361, head 102 calibrates the measurement channels against master reference 351a. This is an internal calibration for head 102 that calibrates its own measurement capabilities.

[0095] In step 362, head 102 commands source pod 104 to apply a full positive source signal. This high amplitude signal will be used to calibrate delivery accuracy. In step 363, head 102 measures the full positive source signal generated in step 362 using the measurement channel calibrated in step 361. In step 364, head 102 commands source pod 104 to apply a negative full-scale source signal. In step 365, head 102 measures the negative full-scale source signal generated in step 364 using the measurement channel calibrated in step 361. In step 366, head 102 commands source pod 104 to apply a zeroed source signal. This signal is then measured by head 102 in step 367 using the measurement channel calibrated in step 361.

[0096] In step 368, head 102 compares the measurements of the fully positive, fully negative, and nulled source signals (i.e., the values ​​measured in steps 363, 365, and 367) with the corresponding commanded values ​​of the fully positive, fully negative, and nulled source signals (in steps 362, 364, and 366, respectively) to determine an error. Finally, in step 369, head 102 uses the error determined in step 368 to generate and store a measured signal calibration for source pod 104. The calibration can be used to precisely deliver a signal to a sample.

[0097] Turning again to FIG. 3A , the diagram shows that the head 102 includes a digital signal processing unit 324. While the digital signal processing unit 324 is not shown in FIG. 3A as being connected to other aspects of the system 300, it may have multiple variable connections. For example, it may be connected to and synchronized with the shared synchronous clock 302. It may also receive and process signals from the digital I / O 310, the source and measurement channels 304 and 306, the auxiliary I / O, and the interface 316. Generally, the digital signal processing unit 324 may process signals from any of these components and provide processed signals to it. The digital signal processing unit 324 may provide timestamps for data originating from the pod 104 and / or head 102 using synchronization with the shared synchronous clock 302.

[0098] The digital signal processing unit 324 may provide various functions to the system 300. For example, it may provide any one of lock-in analysis, alternating current / direct current (AC / DC) measurement, inductance (L), capacitance (C), and resistance (R) (LCR) measurement, time / range domain presentation, frequency domain analysis, and noise analysis for the sample 110 measurement signal. Details of some of these operations will be described below. The digital signal processing unit 324 may also provide AC / DC supply, control looping, and providing a source signal from more than one source for the sample 110 source signal.

[0099] 3A also shows the head 102 with a power supply 326. The power supply 326 may supply not only the head 102 but also other components of the system. In some applications, for example, it is advantageous for each of the pods 104 and heads 102, and possibly some of the other hardware 314, to all share the power supply 326. This can be advantageous for noise and interference mitigation and glitch prevention. The power supply 326 may include being referenced to a common ground (not shown) in the system, such as a common ground for the head 102 and pods 104. This may also include a power supply filter for at least one of the pods 104.

[0100] 3A, head 102 may provide a single voltage reference to be used by all components in systems 100, 200, and 300. The reference voltage may be used to scale measurements in the calibrations described herein, in noise determination and mitigation, and for other suitable uses, whether explicitly described or implied by this disclosure. Other system-wide references may also be provided for similar purposes.

[0101] Any feature described in the context of one of the M81 platforms / systems 100, 200, and 300 should be understood to apply and / or be compatible with any of the others. These features give the M81 platforms / systems 100, 200, and 300 several advantages over traditional laboratory settings, including from the perspective of traditional instrument racks. For example, they can exhibit extremely low noise. This is because the sensitive analog circuitry in the pods 104 is separated from the noisy digital circuitry in the heads (see, e.g., separation distance 318 in FIG. 3A). The M81 platforms / systems 100, 200, and 300 can be highly configurable / reconfigurable. In variations, the combination of pods 104 connected to the heads 102 can be configured for a wide variety of experiments. The system is designed so that the digital and power supply circuitry is isolated from the sensitive analog circuitry to minimize noise and interference, and the digital functions in the sensitive analog circuitry are suspended or shut down while the pod 104 is taking measurements.

[0102] The M81 systems 100, 200, and 300 can also support multiple methods of communication between the pod 104, the head 102, and any other devices included within the system. These communication methods include using Standard Commands for Programmable Instruments (SCPI) and queries. In various variations, communication methods can include USB-Serial, TCP over Ethernet or Wi-Fi, General Purpose Interface Bus (GPIB), etc. With respect to the data streaming buffer, information can be read from various variations of the M81, for example, at up to 10,000 samples per second. In various variations, for any channel, the buffer can include any combination of the following: source amplitude, source offset, source frequency, source range, source compliance, source sensing error, DC reading, RMS reading, high peak, low peak, peak-to-peak, in-phase reading (I), out-of-phase reading (Q), lock-in magnitude, lock-in phase difference, measurement range, overload status, stabilization status, lock, lock-in reference frequency, etc.

[0103] The M81 systems 100, 200, and 300 described herein can be utilized in a variety of applications, such as in solid-state electronics, DC and AC resistivity, diode and transistor I / V curves, PIN (P-type, intrinsic, and N-type materials) diode operating regions, subthreshold MOSFET characterization, capacitor dielectric absorption, deep level transient spectroscopy, etc. In quantum and superconducting materials, I / V of superconducting materials, thin film kinetic inductance, spin Hall magnetoresistance, anomalous Hall effect, magnetic field and angle dependence in magnetic tunnel junctions, spin torque ferromagnetic resonance, etc.

[0104] Variations of the M81 100, 200, and 300 systems have pods 104 capable of hybrid supply. This means that in some variations, the source pod 104 output can combine a DC component signal chain with an AC component signal chain. The signal chains can be independent, allowing for the combination of high-precision AC signals and DC offsets. Variations of the M81 100, 200, and 300 also allow for seamless ranging while in measurement mode. This means that in some variations, the measurement pod 104 can have two or more ranging amplifiers and two analog-to-digital converters. This arrangement can suppress glitches that would otherwise affect measurements as the measurement signal traverses a measurement range that spans multiple orders of magnitude. Variations of the M81 100, 200, and 300 can also support flexible lock-in, meaning that each source and measurement pod 104 can be referenced to each other or to an external reference. Variations of the M81 100, 200, and 300 can also support an external phase relationship. This means that, in a variant, the phase shift of each source pod 104 can be configured independently using the same reference. Each of these advantages will be explained in more detail below.

[0105] signal supply

[0106] Overview of Features

[0107] The M81 platform / systems 100, 200, and 300 can utilize any type of source pod 104 described herein. FIG. 4 illustrates several example source pod configurations with example features. For example, an enhanced combination source / measurement pod can combine the capabilities of a source and a measurement pod by using respective channels. A precision source pod can include an I (current) or V (voltage) source with built-in current or voltage readback. This can help reject environmental noise that would otherwise disrupt cryogenic experiments with strict power limitations. The source pod 104 may also include a balanced current supply (BCS), as described further below, which can ensure that the same amount of current is returned as is provided. This helps protect sensitive equipment against surges.

[0108] It should be understood that Figure 4 illustrates a combination of features that may be practical for certain applications. In some cases, it may be advantageous to include more or fewer features than those shown in Figure 4. For example, in some cases, it may be advantageous to have an enhanced combined source / measurement pod and precision source pod to provide common-mode noise rejection. In some cases, it may be advantageous to have a balanced current source pod to accommodate a hybrid AD / DC supply. All of these variations should be considered within the context of this disclosure.

[0109] Noise reduction in the source signal

[0110] FIG. 5A shows a direct comparison of the signaling noise of M81 (e.g., systems 100, 200, and 300) with a more conventional setup. More specifically, FIG. 5A is a screen capture of the noise of an exemplary M81 current source pod 104 (labeled "A" in FIG. 5A) and a more conventional laboratory current source (a conventional commercial current source labeled "B" in FIG. 5A). Both sources deliver currents in the 1 μA range. FIG. 5B shows a blowup of signal A from the M81 pod 104. FIG. 5C shows a blowup of signal B from the same section of FIG. 5A. A comparison of FIGS. 5B and 5C shows the favorable signal-to-noise ratio for pod 104 signal A. Notably, the 1 μA signal amplitude 502 of signal A is several times larger than the exemplary noise amplitude 504 of signal A. In contrast, the 1 μA signal amplitude of signal B is essentially buried within its noise amplitude 506, which is several times larger than the signal amplitude 502 of signal A, which is also many times larger than the noise amplitude 504 of signal A.

[0111] synchronization

[0112] The M81 systems 100, 200, and 300 are essentially synchronized via a shared synchronized clock 302 (FIG. 3A). In particular, the synchronization allows signals transmitted from the source pod 104 to the sample 110 to be synchronized with the analysis hardware (e.g., digital signal processor 322) in the measurement pod 104 and head 102 itself.

[0113] 6A and 6B depict the effects of misaligned time bases in a conventional instrument rack, which can be avoided by using a shared synchronized clock 302. In a conventional instrument rack, the clock and timestamp of the source signal 602, and the sampled measurement signal clock 1 604 and sampled measurement signal clock 2 606 can be misaligned as shown in FIG.

[0114] Also, mismatches between clocks 604 and 606 can develop over time. For example, compare different mismatches 610, 612, and 614 and different times t1, t2, and t3. These mismatches result in differences in measurement signal 608, shown at 616, 618, and 620 in FIG. 6B at t1, t2, and t3. These frequency and phase differences can create significant problems in data analysis. They lead to inaccuracies and errors. The problem can be subtle and difficult to correct because time variations can appear unsystematic. While FIGS. 6A and 6B present the synchronization issue in the context of measurement and source signals, it should be understood that this is merely exemplary. Lack of synchronization can plague more than experimental measurements. It can also confuse and disrupt system-wide command, calibration, and data analysis.

[0115] Synchronization issues are avoided by the M81 100, 200, and 300 systems sharing one clock sample clock (e.g., clock 302) between all source and measurement pods 104 and heads 102. This essentially and automatically synchronizes all instrumentation, avoiding mismatches between source and measurement signals shown in Figures 6A and 6B.

[0116] Hybrid Supply

[0117] A "hybrid supply" generates an analog output source signal from both AC and DC components. This technique can leverage the benefits of both AC and DC supply electronics by creating separate gain paths for the AC and DC signals. This can also construct a source signal with lower levels of noise, higher resolution, and more flexibility than a traditional single converter supply. Variations of the M81 100, 200, and 300 have hybrid supply capabilities, as discussed in more detail below and in co-pending U.S. Provisional Patent Application No. 63 / 034,052, which is incorporated herein by reference.

[0118] FIG. 7 illustrates a source signal chain between an exemplary head unit 102 and an exemplary source pod 104 in variations of systems 100, 200, and 300. 1 700. The components shown as part of the head 102 in Figure 7 (i.e., components 702, 706-714, 722, and 726-730) may be part of the digital signal processing unit 324 shown in Figure 3A. [1] The terms "chain" and "path" with respect to signal routing are used interchangeably herein. Used.

[0119] As shown in FIG. 7 , M81 includes a source channel 702. In the exemplary case shown in FIG. 7 , there are three source channels 702; however, it should be understood that any suitable number of source channels is possible. The source channel 702 is fed a reference signal 704 via a phase-locked loop (PLL) 706. The source channel 702 may also include signals from other source channels 708 and measurement channels 710 from other pods 104. The input signals 708, 710, and 704 can then be selected for delivery by a reference select 712. Various aspects of the selected signal, including waveform shape, amplitude, frequency, and phase, can then be sent to an AC component digital-to-analog converter (DA1) 714. The operation of the AC component DAC 714 will be discussed further below. The AC component source signal can be combined with the DC component signal and sent to the sample 110 via suitable amplification.

[0120] Both the AC and DC component signals can have independent configurations through their separate DACs and separate amplification. The DC component signal is derived from DC feedback from the combined signal to adjust the sampled source signal. Incorporating feedback and independent AC and DC configurations into a hybrid supply can improve the resolution and update rate of the source signal. Real-time feedback and independent configurations can avoid or minimize error sources such as offset error, gain error, differential nonlinearity error, integral nonlinearity error, calibration error, output noise, dynamic range, output bandwidth, source impedance, output drive capability, switching noise, phase error, drift over time, and drift over temperature.

[0121] 7 shows an exemplary hybrid source 700 configuration. The sample source signal (i.e., the signal transmitted by chain 700 to DUT 110) is a combination of an AC signal ("AC component signal") and a DC signal ("DC component signal"). These signals are combined to generate the sample source signal via a variable gain 720 that can be dynamically ranged to avoid glitching in the signal. The DC component signal is generated based on DC feedback from the combination of the AC and DC component signals.

[0122] More specifically, AC configuration DAC 714 provides an AC configuration source signal to amplifier 716 in source pod 104, where it is combined with a DC configuration source signal by 718 and provided to amplifier 720 where it is ranged and then provided onto sample (DUT) 110. The source waveform shape, amplitude, frequency, and phase provided to AC configuration DAC 714 may be pre-programmed, selected by a user, and / or selected from among options by head 102 according to user preferences and / or protocols (e.g., measurement or diagnostic). The output of 718 is also provided as DC feedback via amplifier 724 to DC configuration ADC 726 of head 102. The DC feedback signal is then sent to DC configuration DAC 730 via offset 728 and then routed to 718 via amplifier 732.

[0123] 7, the range of the ranged amplifier 720, along with other settings, can be selected via a "range and other settings" signal transmitted via a range and other settings element 722 of the head 102. The range and other settings may be pre-programmed, selected by the user, and / or selected from among options by the head 102 according to user preferences and / or protocols (e.g., measurement or diagnostic).

[0124] The source pod 104 may further include digital (non-analog) circuitry capable of performing various functions, including analysis, communication of data, command information, power regulation, timing, and communication with external devices. In a variation, the source pod 104 has the ability to deactivate this non-analog circuitry while providing its source signal or performing measurements. Doing so reduces the amount of interference and noise in the signal or measurement. For the same reason, the digital signals in the source pod 104 may be isolated from the measurement pod 104 and head 102.

[0125] Before delving into hybrid supplies in more detail, it is useful to consider a more conventional non-hybrid source. FIG. 8 illustrates one such non-hybrid source signal chain 800, in which AC 802 and DC 804 inputs are digitally summed together by 806. Chain 800 is suitable when the AC 802 and DC 804 inputs are generally within the same or similar ranges. In this configuration, the small AC signal relative to the DC signal has only a few bits of resolution. DAC 808 converts the combined AC / DC signal to analog and provides it to variable amplifier 720, amplifier 810, and then sample 110. While FIG. 8 does not explicitly show a DC feedback mechanism as shown in FIG. 7, it should be understood that this could include such feedback, for example, through DC input 804.

[0126] Although chain 800 can be included in systems 100, 200, and 300, it has several drawbacks. Chain 800 must provide gain simultaneously to AC and DC input signals. Therefore, there is no opportunity for independent configuration of the AC and DC signal chains. In addition, there is little flexibility in gain configuration. The only flexibility in chain 800 comes from variable gain 720, which must be configured simultaneously for both AC and DC.

[0127] In contrast, Figures 9-12 show exemplary alternative approaches to hybrid feeds that offer much greater flexibility and accuracy. Each of these systems allows for independent configuration of the DC and AC signal paths. They can be used in conjunction with source signal chain 700 and systems 100, 200, and 300. Other approaches that can be used for hybrid feeds are laid out in U.S. Provisional Patent Application No. 63 / 034,052.

[0128] FIG. 9 illustrates an exemplary source signal chain 900 in which the AC 902 and DC 904 inputs are separately converted by DACs 906 and 908, respectively, in a combined configuration ("must configure both"), while the AC and DC configurations occur in parallel. This allows the AC 902 and DC 904 inputs to be separately and independently configured and ranged, providing further flexibility in defining the ranges for the AC 902 and DC 904 contributions to the signal ultimately transmitted to the sample 110. Each AC 902 and DC 904 input is also separately applied to variable gains 720a and 720b, respectively. The variable gains 720a and 720b may be set by range and other settings 722 (FIG. 7), or by user preferences, protocols, or may be preset. The DC gain 720b may or may not depend on the output to the sample 110, as disclosed in the context of system 700 and FIG. 7. After variable amplification, both the AC and DC signals are summed ( 910 ) and sent to amplifier 912 and transmitted onto sample 110 .

[0129] 10 illustrates another example source signal chain 1000 in which the AC and DC components are separate and parallel. In chain 1000, the AC circuit (the "AC component") is prevented from affecting the accuracy of the DC circuit. In this case, it is advantageous for the bandwidths of the AC and DC paths to be substantially different from the transition frequency in order to obtain a flat frequency response when they are summed and sent to sample 110.

[0130] As shown in FIG. 10 , first, the sum of the AC 1002 and DC 1004 inputs at 1006 is sent to the DAC 1008 in the DC component path. The AC 1002 input is sent to the DAC 1010 in the AC component path. Both the AC and DC signals are then amplified by variable amplifiers (720a and 720b, respectively). The gains 720a and 720b for the DC and AC component circuits can be different and configurable, respectively. They may be set in the same manner as described above with respect to the gains 720a and 720b in the context of FIG. 9 . Next, the AC component signal is high-pass filtered (1012) to remove low-frequency components. The DC component signal is low-pass filtered (1014) to remove high-frequency components. The filtered AC and DC signals are then summed at 1016. The summed signal is amplified at 1018 and sent to the sample 110.

[0131] FIG. 11 illustrates another example source signal chain 1100 with a DC feedback loop. The AC and DC inputs 1102 and 1104, respectively, are summed (1106) and sent to the DC constituent path via a DAC 1108. The AC input 1102 is fed to the AC constituent path via a DAC 1110. The AC constituent path then passes through a variable amplifier 720a, which is then summed (1112) with the signal from the DC constituent path after it is amplified by 720b. The gains 720a and 720b may be set as discussed above in the context of FIGS. 9 and 10. The sum 1112 is then fed to the sample 110 via amplifier 1114.

[0132] DC feedback is accomplished as follows: The DC component path from DAC 1108 is summed 1116 with the DC input signal after DAC 1108 processing and then sent to variable amplifier 720c via 1118. The gain 720c may be set as discussed above with respect to 720a and 720b. The DC component signal is then summed with the AC component signal at 1112. This feedback loop essentially treats the AC path as a disturbance to the DC path, allowing for a flat frequency output to sample 110.

[0133] 12 illustrates another exemplary source signal chain 1200 in which the DC feedback is digitized using an ADC. This introduces less DC inaccuracy and enhances DC DAC resolution. Chain 1200 also takes advantage of the fact that ADCs are typically more accurate than DACs, resulting in better control.

[0134] The AC component path in chain 1200 is the same as in chain 1100 of FIG. 11 . The DC component path in chain 1200 differs from that of chain 1100 primarily by the inclusion of ADC 1202 in the DC feedback. However, several other subtle differences exist. Specifically, DC feedback from sample 110 is fed to ADC 1202 via variable amplifier 720c, where it is converted to an analog signal. That signal is then summed 1204 with the combined DC input / AC input signal from 1106, DC. The combined signal is then fed via DAC 1108, 1206, to amplifier 720b, which is then summed with the AC component signal at 1112. Gains 720a, 720b, and 720c can all be set as described above with respect to FIG. 11 .

[0135] balanced current source

[0136] 7, the source pod 104 may further include a balanced current supply (BCS) capability 732. The BCS 732 is described in more detail in U.S. Patent No. 6,501,255 (the '255 patent) to Pomeroy, entitled "DIFFERENTIAL CURRENT SOURCE WITH ACTIVE COMMON MODE REDUCTION," filed October 4, 2001, which is incorporated herein by reference in its entirety.

[0137] Simply put, measurement systems (e.g., systems 100, 200, and 300) can be vulnerable to inconsistent loads that cause current spikes and / or asymmetries between the input and output. These spikes can harm components of those systems. Another problem with single-ended current sources is that the output current return is uncontrolled if the load is grounded to the source return. Single-ended current sources also generate common-mode voltages across the load. In such current sources, the output and return have different impedances, which creates an unbalanced load. Common-mode noise that couples to leads with different impedances reacts to cause common-mode noise, which can adversely affect the desired current excitation. There is a need for current balancing in the materials measurement context, where both floating and grounded loads can be addressed without substantially modifying or rewiring the circuit. The BCS732 addresses this need.

[0138] As discussed in the '255 patent, the BCS 732 drives the load using two modified Howland current sources that deliver equal currents in opposite directions to each side of the load. In the context of systems 100, 200, and 300, the BCS 732 uses a sense resistor to measure the source current associated with the source signal transmitted from the source pod 104 to the sample (the "sample source signal" in FIG. 7). This then varies the resistance range of the sense resistor according to the magnitude of the measured source current. The BCS 732 can also balance the load by altering the resistance of one (or both) of the source and measurement pods 104 based on the source signal measurement. For example, when the measured source current exceeds a certain threshold, the BCS 732 can increase or decrease the resistance of one or both pods 104 to reduce the current below the threshold. The threshold current may represent, for example, a current above which damage will occur to one or more of the components of the systems 100 , 200 , and 300 .

[0139] Digital Source Compositing

[0140] Variations of M81 100, 200, and 300 can generate the source signal using direct digital synthesis. Direct digital signals provide more consistency and control over the source signal. Digital signals also tend to have less variability and drift. These problems ultimately result in noise or ambiguity in the output signal, so using direct digital synthesis can improve measurement accuracy and repeatability. While a specific example is described below, it should be understood that any suitable mechanism for providing a digital source signal can be used in conjunction with any of the variations described herein.

[0141] 13 illustrates one exemplary variation of a digitally synthesized source channel 1300. The digitally synthesized source channel 1300 may be part of the digital signal processing unit 324 shown in FIG.

[0142] The source may be derived primarily from a waveform table 1302. Table 1302 may be an algorithm (software or firmware) that generates a waveform based on several inputs 1304. The inputs 1304 may instruct table 1302 to select a particular waveform to deliver. The inputs 1304 may select, among other things, frequency, phase shift, and lag. Each of these inputs 1304 is not necessarily used in all variations. The inputs 1304 may be stored locally, entered directly by a user, generated by other software, and / or according to a measurement or diagnostic protocol.

[0143] Reference signals 1306 may also be included as inputs to table 1302. References 1306 include source references from lock-in amplifiers (e.g., source lock-in references from channels 1-3) and phase-locked loop (PLL) references. References 1306 may be selected by mux 1308 and sent to multiplexer (mux) 1310, where they are combined with waveform settings 1304 and additional references 1316. References 1306 may be selected by a user, other software, and / or according to a measurement or diagnostic protocol. They are then sent to table 1302 for selection of a specific waveform to output as the source signal. The output waveform from table 1302 may then be further processed 1302 by any signal processing method described herein and provided to source pod 104. Channel 1300 can also use lock-in references with an optional phase shift 1304 rather than being selected directly via input 1304. In this case, the frequency and phase of the source can be determined by a lock-in reference signal (e.g., reference 1312). An optional phase shift 1304 can set the phase relationship with reference 1312. The external phase relationship can be configured to be different for each channel.

[0144] Figures 14 and 15 show exemplary variations of source wave table 1400 that may be provided by element 1302 of digital source 1300. Waveform 1500 of Figure 15 is generated by plotting the data in table 1400. Figure 15 plots a single period of waveform 1500 in relative units.

[0145] In one variation, the source signal supply algorithm can iteratively increment through a table 1400 that represents one or more periods of the waveform. Table 1400 provides waveform amplitude (output) versus time (position), both in normalized units. Using normalized units is not a requirement. It is convenient to scale either the voltage or time dependence of the waveform based on input 1304. In this way, table 1400 determines the shape of waveform 1500. The rate at which the algorithm cycles through table 1400, called the phase increment (element 1304, FIG. 13), determines the frequency of waveform 1500.

[0146] The "position" in table 1400 need not change by integer numbers. In some variations, for example, a higher resolution phase accumulator (element 1304, FIG. 13) can be used to track the phase of waveform 1500. Phase accumulator 1304 can increment by a non-integer amount and convert this phase to a position in table 1400.

[0147] 15 can be smoothed and / or continuous either by the table 1302 itself or in the source process 1302. For low-pass smoothing, the waveform 1500 of FIG. wDiscrete output values ​​with non-zero width in can replace the values ​​in the table of FIG. 14. This produces a "stepped" output waveform 1602, as shown in FIG. 16A. Applying an analog low-pass filter to 1602 produces a smooth waveform 1604, shown in FIG. 16B. The AC waveform 1604 can be combined with a DC offset setting (not shown) and fed into a closed-loop DC supply system in the source processing 1302. This can be part of the hybrid supply variant discussed above in the context of FIGS. 8-13.

[0148] Advanced Measurement Technology

[0149] The M81 platforms / systems 100, 200, and 300 can utilize measurement pods 104 with several different features. The specific type of pod 104 used and its measurement features can depend on application and / or practical considerations. FIG. 17 presents several example measurement pod 104 variations with their feature sets. An "enhanced combination source / measurement pod" can combine the capabilities of a source and a measurement pod by using respective channels. A "voltage measurement pod" can have single-ended or differential voltage measurements with continuity through multiple orders of magnitude. A "current measurement pod" can include a transimpedance amplifier that measures current to a virtual ground. While FIG. 17 illustrates feature combinations that may be practical for certain applications, it should be understood that in some cases it may be advantageous to include more features than those shown in FIG. 17. For example, in some cases it may be advantageous for an enhanced combination source / measurement pod to measure voltage, current, and have the lowest noise, analog filtering, and seamless ranging. All of these variations should be considered within the context of this disclosure.

[0150] 18 illustrates a measurement signal chain 1800 between an example head unit 102 and an example measurement pod 104 in variations of systems 100, 200, and 300. Portions of signal chain 1800 in head 102 (i.e., 1802, 1806-1816) may be part of digital signal processing unit 324 shown in FIG.

[0151] As shown in FIG. 18 , the head 102 includes a measurement channel 1802. In the exemplary case, there are two input measurement channels, one for range A and one for range B, each with its associated ADC. It should be understood that any suitable number of measurement channels is possible, depending on the particular measurement and the number of ranges involved, which may be substantially more than two (e.g., three, four, or more). The measurement channel 1802 may be obtained from the measurement pod 104 via a number of variable amplifiers 720 and analog filters 1804, as shown in FIG. 18 . The gain on the amplifiers 720 may be set as described in the context of the gains 720a-720c of FIGS. 10-12 . As described in more detail below with respect to FIG. 23 , the channel 1802 may be combined 1806 with a range mixing signal 1808 and sent for demodulation 1810 via lock-in. Demodulation is informed by reference signals (e.g., Reference (Lock-in) and Reference +90 Degrees (Lock-in) 1812) and may undergo digital filters 1814 for signal refinement. The digital filters 1814 may be, for example, finite impulse response and infinite impulse response.

[0152] As shown in FIG. 18 , range mixer 1808 further provides outputs related to range and setting 1816 that are ultimately fed back to amplifier 720 and analog filter 1804, which may adjust the gain and processing of the measured sample signal for ranges A and B, respectively. This process is referred to as continuous measurement ranging and / or range mixing. Its purpose is to ensure that there are no glitches or measurement discrepancies that might otherwise occur when measurement pod 104 must change its acquisition parameters to adjust for changes in the range of the measured sample signal. The operation of range mixer 1808 and continuous ranging between ranges A and B will be discussed further below.

[0153] The measurement pod 104 may further include digital (non-analog) circuitry capable of performing various functions, including analysis, communication of data, command information, power regulation, timing, and communication with external devices. In a variation, the measurement pod 104 has the ability to deactivate this non-analog circuitry while performing measurements or providing a source signal. Doing so reduces the amount of interference and noise in the signal or measurement. For the same reason, the digital signals in the measurement pod 104 may be isolated from the source pod 104 and head 102.

[0154] Continuous Measurement Ranging

[0155] Materials measurements, especially those performed at cryogenic temperatures and involving properties related to electronic structure, can span decades and orders of magnitude. These wide ranges can tax traditional measurement equipment. Often, different instruments are required to measure values ​​at different ranges. Switching between different instruments to cover multiple ranges in a single experiment can cause glitches in the measurement data. Several factors, such as accuracy and gain differences between different range measurement systems, cause these glitches. Range changes can also result in measurement discontinuities over time, leading to gaps in the collected data. Either scenario is undesirable. Both reduce the overall accuracy of the measurement. To address these issues, variants of the M81 100, 200, and 300 have "seamless ranging" capabilities, as discussed below and in more detail in co-pending U.S. Provisional Patent Application No. 63 / 016,745.

[0156] FIG. 19 compares voltage measurements with seamless (continuous) ranging 1902 at M81 100, 200, and 300 with the same measurements made with a conventional setup 1904 lacking seamless ranging capability. FIG. 19 shows how conventional ranging 1904 produces a discontinuity D in the measurement data 1904 across the range transition Δt because different sets of devices with different measurement profiles (e.g., accuracy, gain, etc.) are used to measure data in ranges r1 and r2. Additionally, switching between ranges r1 and r2 may involve transient signals, noise, or glitches resulting from the “warm-up” or start-up of equipment dedicated to measuring across the transition-to range (r2 in the exemplary case shown in FIG. 19).

[0157] FIG. 19 also illustrates how the transition Δt can be smoothed by the seamless ranging capabilities included within the M81 platform / systems 100, 200, and 300 (continuous ranging measurement data 1902). This smoothing effect is represented graphically in FIG. 19 as the avoidance of discontinuities D by continuous ranging data 1902. While only two example ranges r1 and r2 are discussed in the context of FIG. 19, it should be understood that the continuous ranging technique may be applied to any suitable number of ranges associated with a particular measurement. For example, the number of ranges may be three, four, or more in some cases. In each of these cases, the continuous ranging can be configured to ensure a smooth transition between each range change, regardless of the direction of the range change (i.e., regardless of whether the range change involves an increase as shown in FIG. 19 or a decrease in the measurement value (not shown)).

[0158] Continuous ranging addresses the two ranges r1 and r2 using separate signal amplification / gain chains that can be applied independently and / or in parallel. Specific implementations will be discussed below in the context of Figures 20 and 21. Addressing each range r1 and r2 separately and / or in parallel can be achieved by using an inactive range (i.e., a range not currently employed in the measurement, e.g., t) based on the data collected with active amplification changes. <t TR The range r2 or t>t when TR This allows for the configuration of amplification chains for range r1) when r2 is 0. Keeping the amplification chains for the inactive ranges online in parallel with the active range measurements can avoid start-up transients when the inactive ranges are finally engaged. This also allows for "range mixing," where gain chains per range are applied in combination to promote a smooth change in data over the transition Δt from range r1 to r2 (or vice versa). That is, amplification chains from both ranges can be applied simultaneously to smooth the data over the range transition Δt. This can be done, for example, via a software mixer, and / or can then smoothly transition from r1 to r2, and vice versa.

[0159] 20 is a variation 2000 that implements seamless ranging via dual amplification chains. Variation 2000 may be implemented, for example, by range mixer 1808 shown in FIG.

[0160] As shown in FIG. 20, the lower gain chain 2002 and the higher gain chain 2004 are identical except for 1) different ADCs (2008a and 2008b, respectively) and 2) an additional amplifier 2006 in the higher gain chain 2004, which gives it a higher gain than the lower gain chain 2002. The outputs from the ADCs 2008a and 2008b are combined by a mixer 2010 and used in the acquisition routine of the measurement pod 104 for ranging measurements. In chain 2000, the combination can be weighted by a factor α. α can be dynamically selected to ensure a smooth transition over the ranging transition Δt (e.g., using range blending to avoid discontinuity D of FIG. 19). α can be set by the user, but is often set by a ranging algorithm (e.g., algorithm 2200 shown in FIG. 22A).

[0161] 21 shows another exemplary amplification chain 2100 used in seamless ranging. Variation 2100 may be implemented, for example, by range mixer 1808 shown in FIG.

[0162] Chain 2100 includes a lower gain section 2102 and a higher gain section 2104, which are identical except for 1) different ADCs (2108a and 2108b, respectively), 2) an additional amplifier 2106 in the higher gain section 2104, which gives it a higher gain than the low gain section 2102, and 3) the lower gain section 2102 and the higher gain section 2104 are connected to gain stage 2112 via muxes 2114a and 2114b, respectively.

[0163] As shown in FIG. 21 , the amplification provided from gain stages 2112a and 2112b to the lower and higher gain sections 2102 and 2104 can be selected via muxes 2114a and 2114b, respectively. In this way, chain 2100 may use fewer dedicated amplifiers than chain 2000 to provide the combination to mixer 2110. Using identical gain stages 2112a and 2112b (and amplifiers) for the lower and higher gain sections 2102 and 2104 is not only more efficient; it also introduces less noise into the system that can arise due to glitches or mismatches between different amplifiers. For example, each amplifier may have transients that are avoided when they are used all the time, regardless of the range being applied.

[0164] As with chain 2000, the combinations in chain 2100 can be weighted by a factor α, which can be chosen dynamically to ensure a smooth transition over the ranging transition Δt (e.g., using range blending to avoid discontinuity D of FIG. 19). α can be set by the user, but is often set by the ranging algorithm (e.g., algorithm 2200 shown in FIG. 22A).

[0165] In variations involving chains 2000 and 2100, and others, seamless ranging may include automatic ranging. Figure 22A provides a schematic example of an automatic ranging algorithm 2200 that may be used in conjunction with seamless ranging. Figure 22C shows the algorithm 2200 in flowchart form. This can be implemented by the range mixer 1808 of Figure 18, among other components in the digital signal processing unit 324.

[0166] The algorithm 2200 varies the range as the measurement signal 2250 shown in Figure 22B varies incrementally from ranges r1, r2, and r3. The signal 2250 varies incrementally from ranges r1, r2, and r3 at t = t TR(1-2)At t, the range r1 transitions to r2. TR(3-4) 22A shows the response of algorithm 2200 in terms of applying dedicated gain chains for ranges r1, r2, and r3 across those transitions.

[0167] As shown in FIGS. 22A and 22C, the algorithm 2200 calculates the transition from r1 to r2 (t TR(1-2) ), provides the configured gain for 100% r1 during period 2202 (e.g., draws from the higher gain portion 2004 in chain 2000 of FIG. 20 and provides the higher gain to the lower of the two ranges). FIGS. 22A and 22C also illustrate that algorithm 2200 detects when the measurement signal reaches transition t TR(1-2) 2004. The r1 / r2 blending period before this transition is labeled 2204. As discussed above, blending avoids glitches and / or gaps in the data during the r1 / r2 range transition. t TR(1-2) After the r1 / r2 transition in t, algorithm 2200 applies the r2 gain without blending (e.g., by pulling from the lower gain portion 2002 in chain 2000 of FIG. 20). FIGS. 22A, 22B, and 22C show that the algorithm similarly blends the gain profiles for r2 and r3 during period 2208, and then applies only the r3 constituent gain during period 2210. TR(3-4) This indicates that r2 changes to r3.

[0168] FIG. 22A also shows a region of hysteresis 2212 during period 2206 (r2 only). During hysteresis 2212, there is no anticipated ranging (i.e., only one gain portion of the gain chain is active, in this case the gain chain for r2). This avoids back-and-forth switching between ranges due to noise or signal fluctuations. Once measurement signal 2250 moves closer to r3, hysteresis period 2212 ends. Period 2214 represents the period during which the range change from r2 to r3 is anticipated by engaging the gain chain for r3 (not shown). The gain chain corresponding to r3 is engaged during 2214 for both calibration and transient avoidance purposes as discussed above. While no hysteresis or anticipation of the upper portion of the range is shown for the r1 / r2 transition, it should be understood that it may be applied to that transition as well.

[0169] While FIG. 22A shows the operation of algorithm 2200 as the measurement signal increases, it should be understood that the algorithm equally applies as the measurement signal decreases (e.g., from a higher range r3 to a lower range r2, and then to the lowest range r1). This is illustrated via flowchart 2220 in FIG. 22D. In this case, rather than predicting an upper range period, algorithm 2200 would predict a lower range period (e.g., t TR(2-3) r1, r2, and r3 (e.g., transition downward from r3 to r2 at step 2224 of chart 2220). While Figures 22A, 22B, and 22C show algorithms 2200 and 2220 handling range changes between three example ranges r1, r2, and r3, it should be understood that this may handle range changes between any number of ranges suitable for experimentation in the same manner. Other variations of algorithms 2200 and 2220 may include many other algorithms and / or range / parameter settings and any suitable number of range transitions.

[0170] Lock-in Measurement

[0171] The M81 100, 200, and 300 variations can include, among other things, a head 102 with lock-in measurement capabilities to accurately extract measurements from noisy measurement signals. Figure 23 shows one example variation 2300 that can be implemented by the digital signal processing unit 324. In variation 2300, a measurement signal 2302 can be multiplied 2304 by a known reference source 2306 to create a demodulated signal 2308. After demodulation, a low-pass filter 2310 can remove noise and generate a reading 2312.

[0172] In one example implementation, the sample 110 resistance R1 can be measured by supplying an AC current and measuring the voltage 2302. Multiplying 2304 the measured voltage reading 2302 with the current source 104 output as a reference signal 2306 can allow for extraction of only the voltage generated by the current through the resistance R1 via the lock-in technique of FIG.

[0173] The lock-in technique 2300 utilizes the following signal processing concept: multiplication of signals at different frequencies (ω r ≠ω m ) averages out to zero, which is useful for signal extraction in this case. [ka] However, the multiplied signals have the same frequency (ω r =ω m ), the product of the signals will be, on average, half the signal amplitude. [ka] Thus, the lock-in technique 2300 of FIG. 23 can be used to isolate the measurement signal 2302 from interference and noise that does not include the reference 2306 signal.

[0174] The M81 100, 200, and 300 variations can also demodulate harmonics (i.e., multiples of a reference frequency) for signal extraction. This is particularly useful when there is a phase difference (θ) between the signals, as shown in FIG. 24 for signals 1902 and 1904.

[0175] If a phase difference θ exists between the reference and measurement signals (FIG. 24), the value of the single lock-in reading will depend on θ. [ka]

[0176] The M81 100, 200, and 300 variants can interpret this phase dependence by using a demodulation phase shift that matches θ. The demodulation phase shift proceeds as follows: First, a biphasic measurement determines the amount of phase difference. The measured signal can be multiplied by both the reference and a 90-degree phase-shifted reference. This produces in-phase (I) and out-of-phase (Q) signal portions. [ka] The amount of phase difference can then be calculated using (1) and (2). [ka]

[0177] The phase difference calculated via (3) is the demodulation phase [ka] This makes the reading the in-phase component and zero the out-of-phase component. [ka] The M81, 100, 200, and 300 variants can automatically calculate and apply the demodulation phase.

[0178] 25 shows how the head 102 may also use a phase-locked loop (PLL) 2500 to achieve the reference to be supplied to 2300. The PLL 2500 may be part of the digital signal processing unit 324.

[0179] A reference is selected (either by the user or an algorithm) via mux 2502 from an external signal 2504, a power line frequency 2506, and / or one of three measurement channel signals 2508. In some variations, the user can bypass 2510 the high pass filter 2512 to apply a lower frequency signal. The user can choose to invert (shift 180°) the incoming signal.

[0180] In a variation of the PLL 2500, one signal can be used to generate the reference at a given time. The PLL 2500 can ensure that the frequency and phase of the reference matches that of the incoming signal. f ) and phase control loop (k p ) can track changes with the incoming signal. High-pass filter 2512 can allow locking in to a reference square wave or AC signal + / - 5V. MAC 2502 can select one of the measurement channels as a reference.

[0181] The M81 100, 200, and 300 variations can utilize a reference-out. One exemplary reference-out 2600 is shown in Figure 26. The reference-out 2600 may be implemented by the digital signal processing unit 324.

[0182] A user can choose to output one of the source reference 2602 or PLL reference 2604 via mux 2608. A timer peripheral 2610 (e.g., triggers after a certain amount of time or clock cycles) or other timing device can generate a signal synchronized with a sampling clock (e.g., shared synchronous clock 302 of FIG. 3A). In some variations, a user can also choose to invert the signal via optional inverter 2612. In variations, one reference signal at a time can be transmitted.

[0183] The M81 100, 200, and 300 variations can utilize a measurement digital signal processor / processing (DSP) implemented by the digital signal processing unit 324. One example variation 2700 is shown in FIG. 27. For example, with respect to signal in, the A and B measurement channels can be read by two independent ADCs 2552 and 2554, respectively. The signals sent to ADCs 2552 and 2554 can be interpolated for seamless ranging, as described in detail above in the context of FIGS. 19-22C.

[0184] The larger of the two signals A and B can be sent to a PLL, such as PLL 2500 described in the context of FIG. 25. Peak detection can be used to make automatic ranging decisions in a seamless ranging algorithm, such as algorithm 2200 described in FIGS. 22A and 22C and / or algorithm 2220 of FIG. 22C. An optional / configurable digital filter 2756 may be applied to the measurement. In one variation, the filter is a cascaded biquad, which can be configured for low-pass, high-pass, band-pass, or notch filtering. In some variations, when making AC / DC measurements, switches 2758 and 2760 can select their upper signals 2758a and 2760a, respectively. This causes the measurement to be multiplied by itself in multiplier 2762 and by one (i.e., unchanged) in multiplier 2764. After averaging, upper signal 2768 is the RMS measurement reading from A and B. The bottom signal 2770 is a DC reading. The peak detection 2766 can remain the same regardless of the type of measurement being made. The measurement can be converted to the appropriate units based on the type of pod and its range.

[0185] For variations involving PLL 2500, the user can select the reference signal to use and also set the demodulation harmonic and phase. Two waveforms can be generated from the reference. For example, as shown in FIG. 24, waveforms 1902 and 1904 are 90° out of phase. In variations involving lock-in measurements, switches 2758 and 2760 select their lower signals, i.e., 2758b and 2760b. After averaging, top signal 2768 is the Q (quadrature) indication and bottom signal 2770 is the I (in-phase) indication (Equations 2 and 1 above, respectively). Packet builder 2772 can synchronously time-stamp the synchronized signals via shared synchronous clock 302 and buffer them to the rest of head 102.

[0186] M81 100, 200, and 300 System Integration

[0187] As an integrated system, the M81 100, 200, and 300 variations can include pod mountings, such as mountings 2802 and 2804 shown in FIGS. 28A and 28B, respectively. FIG. 28A shows that mountings 2802 and 2804 have two halves (e.g., halves 2802a and 2802b) that can fit together in a clamshell configuration. Other configurations are also possible and within the context of this disclosure. Mountings 2802 and 2804 can be made of a material for electrostatic shielding (e.g., plastic, resin, rubber, etc.). Mountings 2802 and 2804 can be made of a material for magnetic shielding, such as steel, mu-metal, or other magnetic alloys. Pods 104 can be stacked together and rack-mounted via housings 2802 and 2804.

[0188] These mountings generally include several through-connections, such as BNC connection 2806a in FIG. 28B. While only BNC connection 2806a is shown, it should be understood that any number of suitable connections can be used. FIG. 28B also shows several additional through-holes 2806b that can accommodate such connections. Through-holes 2806b may be occupied by connections. They may also be empty and have caps to prevent internal exposure, as shown in FIG. 28b. Suitable connections include coaxial, triaxial, and the like. As shown in FIG. 28B, mountings 2802 and 2804 may also include sliding mounts 2808 for mounting onto fixtures such as racks or sections of a sample stage (e.g., sample stage 106 in FIG. 1). While sliding mounts 2808 are shown in the figure, it should be understood that any suitable mounting system (e.g., bolts, snap-fits, guide rails, screws, etc.) can be used. 28A and 28B also show the legs (2802c, 2802d, 2804c, and 2804d) upon which the mountings 2802 and 2804 may stand.

[0189] 29A and 29B show details of the touchscreen 102c in source (FIG. 29A) and measure (FIG. 29B) configurations. While the source and measure configurations are shown separately in FIGS. 29A and 29B, it should be understood that they need not be separate. The source and measure configurations can be shown simultaneously with each other, on the same screen 102c, and with other indicators, diagnostics, or information disclosed herein. As an example, the head 102 may include oscilloscope functionality and display waveforms on the same screen 102c as the measure and source displays of FIGS. 29A and 29B.

[0190] Because 102c is a touchscreen, various elements of FIGS. 29A and 29B may be adjusted by touch input. For example, FIG. 29A shows how source mode 2902 can be adjusted by touch (e.g., to change from I (current) to V (voltage)). FIG. 29A shows how source range 2904, source level 2906, compliance limit 2908, sense line 2910, and measurement mode 2912 can all be adjusted by touch. FIG. 29B shows how measurement mode 2914, averaging time 2916, and range 2918 are adjusted. Additionally, screen 102c can allow for input current and voltage (shown in FIGS. 29A and 29B). Generally, any measurements and settings described herein can be viewed and configured via front-panel touchscreen 102c, whether explicitly shown in FIGS. 29A and 29B or not.

[0191] While various inventive aspects, concepts, and features of the invention may be described and illustrated herein as embodied in combination in exemplary embodiments, these various aspects, concepts, and features may be used in many alternative embodiments, either individually or in various combinations and subcombinations thereof. Unless expressly excluded herein, all such combinations and subcombinations are intended to be within the scope of the invention. Still further, while various alternative embodiments of various aspects, concepts, and features of the invention may be described herein, such as alternative materials, structures, configurations, methods, circuits, devices and components, software, hardware, control logic, form, compatibility, and function, such descriptions are not intended to be a complete or exhaustive list of available alternative embodiments, whether currently known or later developed. Those skilled in the art may readily adopt one or more of the inventive aspects, concepts, or features into additional embodiments and uses within the scope of the invention, even if such embodiments are not expressly disclosed herein. Additionally, while some features, concepts, or aspects of the invention may be described herein as being preferred arrangements or methods, such description is not intended to imply that such features are required or necessary unless expressly so stated. Still further, exemplary or representative values ​​and ranges may be included to aid in understanding the present disclosure; however, such values ​​and ranges are not intended to be limiting and are intended to be critical values ​​or ranges only when expressly so stated. Still further, exemplary or representative values ​​and ranges may be included to aid in understanding the present disclosure; however, such values ​​and ranges are not intended to be limiting and are intended to be critical values ​​or ranges only when expressly so stated. Parameters identified as "approximately" or "about" a specified value are intended to include both the specified value and values ​​within 10% of the specified value, unless expressly stated otherwise.Furthermore, it is understood that the drawings accompanying this application may, but need not be, to scale and, therefore, may be understood as teaching various proportions and ratios apparent in the drawings. Also, while various aspects, features, and concepts may be expressly identified herein as inventive or forming part of the present invention, such identification is not intended to be exclusive; rather, there may be inventive aspects, concepts, and features that are fully described herein without being expressly identified as such or as part of a specific invention, and the invention may instead be set forth in the appended claims. The description of an exemplary method or process is not limited to the inclusion of every step as required in all cases, nor should the order in which the steps are presented be construed as required or necessary unless expressly so stated.

Claims

[Claim 1] The invention described in this specification.

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