Semiconductor integrated circuit device

Abstract

To provide a semiconductor integrated circuit device capable of performing a current load driving capability test for a pad on a semiconductor wafer without an error.SOLUTION: A semiconductor integrated circuit device includes: an input-output pad 105 connected to an external input-output terminal; an output buffer 115 connected to the input-output pad 105; an AD converter 120 that is connected so that the input-output pad 105 serves as an input, the AD converter being configured to acquire the potential of the input-output pad 105 and convert the potential into a digital value when, in a case where the input-output pad 105 is in the low-level output state, a predetermined amount of constant current is supplied from a tester 200 externally connected to the input-output pad 105 or when, in a case where the input-output pad 105 is in the high-level output state, a predetermined amount of constant current is supplied to the tester 200 from the input-output pad 105; and a measurement value output pad 130 that outputs the digital value converted by the AD converter 120.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device capable of performing, without error, a current load driving capability test, which is one of the wafer tests performed after forming integrated circuits on a semiconductor wafer. [Background technology]

[0002] Generally, semiconductor integrated circuit devices undergo wafer testing after integrated circuits are formed on a semiconductor wafer. The semiconductor wafer is then cut into chip sizes and packaged, followed by a final test before shipping. One type of wafer test involves a current load drive capability test, in which the integrated circuits formed on the semiconductor wafer are operated and a predetermined current is forced into (forced) or forcibly drawn from (sinked) the pads within the integrated circuits from an external source. This test measures output characteristics. In this current load drive capability test, a tester's probe pins are brought into contact with the pads within the integrated circuits on the semiconductor wafer to source and sink current, and the output voltage of the pads is determined to meet specifications.

[0003] When the probe pin is brought into contact with the pad, the contact resistance between the probe pin and the pad changes depending on the contact condition, and the measured output voltage may differ from the actual output voltage of the pad. This causes the output voltage value to deviate from the expected value, resulting in a non-defective semiconductor integrated circuit chip being determined to be defective, making accurate testing impossible. This can ultimately lead to a decrease in product yield.

[0004] Therefore, for example, Patent Document 1 below discloses a semiconductor integrated circuit device that converts the voltage at a point to be measured in an analog circuit block using an AD converter and outputs it as a digital signal from an output terminal. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-329682 Summary of the Invention [Problem to be solved by the invention]

[0006] However, the point to be measured in the invention described in Patent Document 1 is located within an analog circuit block, and is not applicable to a current load driving capability test that is performed by forcibly injecting or absorbing current from the outside.

[0007] SUMMARY OF THE INVENTION In view of the above circumstances, an object of the present invention is to provide a semiconductor integrated circuit device that can perform a current load driving capability test on pads on a semiconductor wafer without error. [Means for solving the problem]

[0008] In order to solve the above problem, a semiconductor integrated circuit device according to the present invention comprises an input / output pad connected to an external input / output terminal, an output buffer connected to the input / output pad, an AD converter connected to use the input / output pad as an input, which acquires and converts the potential of the input / output pad into a digital value when the input / output pad is in a low-level output state and a constant current of a predetermined magnitude is caused to flow from an externally connected tester to the input / output pad, or when the input / output pad is in a high-level output state and a constant current of a predetermined magnitude is caused to flow from the input / output pad to the tester, and a measurement value output pad which outputs the digital value converted by the AD converter. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a schematic diagram showing the configuration of a semiconductor integrated circuit device according to a first embodiment. [Figure 2] FIG. 2 is a schematic diagram showing a configuration when a current load driving capability test is carried out on the semiconductor integrated circuit device of the first embodiment. [Figure 3]10 is a schematic diagram showing the configuration of a semiconductor integrated circuit device according to a second embodiment, and the configuration when a current load driving capability test is carried out. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[0011] [Embodiment 1] First, a semiconductor integrated circuit device 100 according to the first embodiment will be described with reference to Fig. 1. As shown in Fig. 1, the semiconductor integrated circuit device 100 includes an input / output pad 105, a ground pad 110, an output buffer 115, an AD converter 120, an input switch 125, a measurement value output pad 130, an internal test control circuit 135, and an ADC control circuit 140.

[0012] After the semiconductor integrated circuit device 100 is packaged, the input / output pad 105 and the ground pad 110 will be connected to an external input / output terminal (not shown) and a ground terminal (not shown), respectively, by bonding wires (not shown).

[0013] The output buffer 115 is connected to the input / output pad 105. The output buffer 115 is composed of, for example, a PMOS transistor 145 and an NMOS transistor 150. The source of the PMOS transistor 145 is connected to a voltage source V DD . The drain of the PMOS transistor 145 and the drain of the NMOS transistor 150 are connected to each other and to the input / output pad 105. The source of the NMOS transistor 150 is connected to the ground pad 110. The gates of the PMOS transistor 145 and the NMOS transistor 150 are connected to the internal test control circuit 135. As a result, the conduction state between the drain and source of the PMOS transistor 145 and between the drain and source of the NMOS transistor 150 is controlled in accordance with the output signal from the internal test control circuit 135.

[0014] That is, suppose that an “H” level signal is input from the internal test control circuit 135 to the gate of the PMOS transistor 145 and the gate of the NMOS transistor 150. Then, the source-drain of the PMOS transistor 145 becomes non-conductive, and the drain-source of the NMOS transistor 150 becomes conductive, and a low-level (“L” level) signal is output to the input / output pad 105.

[0015] On the other hand, suppose that an “L” level signal is input from the internal test control circuit 135 to the gate of the PMOS transistor 145 and the gate of the NMOS transistor 150. Then, the source-drain of the PMOS transistor 145 becomes conductive, and the drain-source of the NMOS transistor 150 becomes non-conductive, and a high-level (“H” level) signal is output to the input / output pad 105.

[0016] A node between the output buffer 115 and the input / output pad 105 is connected to an input node 155 of the AD converter 120 via an input switch 125. The input switch 125 is controlled to be turned "on" or "off" by the internal test control circuit 135. That is, the input node 155 of the AD converter 120 is connected to the input / output pad 105 so as to acquire the potential of the input / output pad 105 when the input switch 125 is "on." Furthermore, the AD converter 120 includes an upper reference voltage node 160 and a lower reference voltage node 165. The upper reference voltage node 160 is connected to a reference voltage source 170, and the lower reference voltage node 165 is connected to the ground pad 110.

[0017] The AD converter 120 has a digital output node 175, and converts the potential difference between the analog potential input to the input node 155 and the potential input to the lower reference voltage node 165 into a digital value and outputs it to the digital output node 175. The digital output node 175 is connected to the measurement value output pad 130 via the ADC control circuit 140, and outputs the digital value converted by the AD converter 120. Note that while only one digital output node 175 and one measurement value output pad 130 of the AD converter 120 are shown in FIG. 1, multiple nodes may be formed as needed.

[0018] The ADC control circuit 140 controls the operation of the AD converter 120 in response to instructions from the internal test control circuit 135. That is, the ADC control circuit 140 controls the sequential switching of the comparison circuits inside the AD converter 120 in response to instructions from the internal test control circuit 135, and converts the input signal input to the input node 155 of the AD converter 120 into a digital value of a predetermined number of bits. The ADC control circuit 140 also outputs the output result output from the digital output node 175 of the AD converter 120 to the measurement value output pad 130.

[0019] A method for testing the current load driving capability of the semiconductor integrated circuit device 100 configured as described above will now be described. As shown in FIG. 2, a tester 200 is externally connected to the semiconductor integrated circuit device 100. The tester 200 has a first probe pin 205, a second probe pin 210, and a third probe pin 215. The tester 200 also has a current load module 220 that generates a constant current of a predetermined magnitude and supplies it to the first probe pin 205, and an evaluation module 225 that evaluates a digital output signal input via the third probe pin 215. The tester 200 also has a setting module 230 that sends setting signals such as a test start signal and a test end signal to the internal test control circuit 135 of the semiconductor integrated circuit device 100. The second probe pin 210 is connected to ground.

[0020] The first probe pin 205 of the tester 200 configured as described above is brought into contact with the input / output pad 105, the second probe pin 210 is brought into contact with the ground pad 110, and the third probe pin 215 is brought into contact with the measurement value output pad 130. Next, the tester 200 sends a test start signal to the internal test control circuit 135 of the semiconductor integrated circuit device 100 via the probe pin and pad (both of which are not given reference numerals for the sake of simplicity) connected to the setting module 230, thereby operating the internal test control circuit 135. In response to this, the internal test control circuit 135 turns the input switch 125 "on," i.e., into a closed state.

[0021] The internal test control circuit 135 also controls the conductive or non-conductive state of the PMOS transistor 145 and NMOS transistor 150 of the output buffer 115 to set the input / output pad 105 to an "L" level output state or an "H" level output state.

[0022] Furthermore, the internal test control circuit 135 sets the number of output bits of the AD converter 120 to the ADC control circuit 140, and outputs a control signal to the ADC control circuit 140 to convert the potential input to the input node 155 of the AD converter 120 into a digital value. For example, in the first embodiment, the internal test control circuit 135 instructs the ADC control circuit 140 to perform AD conversion on a 10-bit output signal.

[0023] When the I / O pad 105 is in the "L" level output state, the current load module 220 of the tester 200 forces a constant current of a preset magnitude into the I / O pad 105 via the first probe pin 205. At this time, the source-drain of the PMOS transistor 145 of the output buffer 115 is non-conductive, and the drain-source of the NMOS transistor 150 is conductive.

[0024] Therefore, the constant current of the preset magnitude flows through a path from the input / output pad 105 to the ground of the tester 200 via the drain-source path of the NMOS transistor 150, the ground pad 110, and the second probe pin 210. At this time, the potential of the input / output pad 105 is applied to the input node 155 of the AD converter 120.

[0025] For example, suppose the voltage value of the reference voltage source 170 is 5.0 [V], the current value flowing from the current load module 220 is 0.010 [A], the contact resistance value between the first probe pin 205 and the input / output pad 105 is 10 [Ω], the contact resistance value between the second probe pin 210 and the ground pad 110 is 10 [Ω], and the on-resistance value of the NMOS transistor 150 is 10 [Ω].

[0026] Also, assume that the current input to the AD converter 120 is sufficiently smaller than the current supplied from the current load module 220 and can be ignored. In this case, the potential of the upper reference voltage node 160 of the AD converter 120 is 5.0 [V]. Furthermore, the potential of the lower reference voltage node 165 is 0.1 [V], taking into account the contact resistance between the second probe pin 210 and the ground pad 110.

[0027] When the AD converter 120 is set to output a 10-bit output signal as described above, the resolution of the AD converter 120, 1 [lsb], is 0.0047 [V]. Here, taking into consideration the contact resistance between the second probe pin 210 and the ground pad 110 and the on-resistance of the NMOS transistor 150, a potential of 0.2 [V] is input to the input node 155 of the AD converter 120.

[0028] A potential of 0.2 [V] is input to input node 155 of AD converter 120, but because the potential of lower-order reference voltage node 165 is 0.1 [V], AD converter 120 converts 0.1 [V], which is the difference between the input potential and the potential of lower-order reference voltage node 165. When AD converter 120 performs AD conversion with the above-mentioned resolution of 0.0047 [V], a value of "20" or "21" is output to measurement value output pad 130. The voltage value corresponding to the output value "20" is 0.097 [V], and the voltage value corresponding to the output value "21" is 0.102 [V].

[0029] Tester 200 receives the output value via third probe pin 215 and evaluates it by comparing it with an expected value using evaluation module 225. If the output value is equal to or less than the expected value of "20" or "21," the current load driving capability test is deemed "passed," and if it is any other value, it is deemed "failed." In other words, when input / output pad 105 outputs an "L" level, normal operation is assumed when the potential of said input / output pad 105 is approximately 0.1 V or less, and the configuration of semiconductor integrated circuit device 100 makes it possible to perform testing without error.

[0030] In contrast, in the conventional method of measuring the potential difference between the input / output pad 105 and the ground pad 110 using the first probe pin 205 and the second probe pin 210, a voltage value of 0.3 [V] is measured under the same conditions as above. Therefore, there is a large error from the actual potential of the input / output pad 105, which is 0.1 [V]. This is because the measurement result is affected by the contact resistance between the first probe pin 205 and the input / output pad 105, the contact resistance between the second probe pin 210 and the ground pad 110, and the power consumption in the on-resistance of the NMOS transistor 150.

[0031] When the input / output pad 105 is in the "H" level output state, the source-drain of the PMOS transistor 145 of the output buffer 115 is conductive, and the drain-source of the NMOS transistor 150 is non-conductive. At this time, the current load module 220 of the tester 200 forcibly draws, or sinks, a constant current of a preset magnitude from the input / output pad 105 via the first probe pin 205.

[0032] Then, the constant current of the preset magnitude is supplied to the voltage source V DD Current flows from the source to the drain of the PMOS transistor 145, through the input / output pad 105, and the first probe pin 205 to the current load module 220 of the tester 200. At this time, the potential of the input / output pad 105 is applied to the input node 155 of the AD converter 120.

[0033] For example, the voltage value of the reference voltage source 170 is set to 5.0 [V], and the voltage source V DD Assume that the voltage value of the first probe pin 205 is 5.0 [V], the current value absorbed by the current load module 220 is 0.010 [A], the contact resistance value between the first probe pin 205 and the input / output pad 105 is 10 [Ω], the contact resistance value between the second probe pin 210 and the ground pad 110 is 10 [Ω], and the on-resistance value of the PMOS transistor 145 is 10 [Ω].

[0034] Furthermore, the current input to the AD converter 120 is sufficiently smaller than the current supplied from the current load module 220 and can be ignored. At this time, the potential of the upper reference voltage node 160 of the AD converter 120 becomes 5.0 [V]. Furthermore, since the drain-source of the NMOS transistor 150 is in a non-conductive state, no current flows between the second probe pin 210 and the ground pad 110. Therefore, the contact resistance value between the second probe pin 210 and the ground pad 110 can be ignored, and the potential of the lower reference voltage node 165 becomes 0 [V].

[0035] As described above, when the AD converter 120 is set to output a 10-bit output signal, the resolution of 1 [lsb] is 0.0047 [V] as described above. Here, taking into account the on-resistance value of the PMOS transistor 145, a potential of 4.9 [V] is input to the input node 155 of the AD converter 120.

[0036] A potential of 4.9 [V] is input to input node 155 of AD converter 120, but because the potential of lower-order reference voltage node 165 is 0 [V], AD converter 120 converts 4.9 [V], which is the difference between the input potential and the potential of lower-order reference voltage node 165. When AD converter 120 performs AD conversion with the above-mentioned resolution of 0.0047 [V], a value of "1042" or "1043" is output to measurement value output pad 130. The voltage value corresponding to the output value "1042" is 4.897 [V], and the voltage value corresponding to the output value "1022" is 4.902 [V].

[0037] Tester 200 receives the output value via third probe pin 215 and evaluates the output value using evaluation module 225. If the output value is equal to or greater than the expected value of "1042" or "1043," the current load driving capability test is deemed "passed." If the output value is any other value, the test is deemed "failed." In other words, when input / output pad 105 outputs an "H" level, normal operation is achieved when the potential of input / output pad 105 is approximately 4.9 V or greater, and the configuration of semiconductor integrated circuit device 100 allows testing to be performed without error.

[0038] In contrast, in the conventional method of measuring the potential difference between the input / output pad 105 and the ground pad 110 using the first probe pin 205 and the second probe pin 210, the voltage value measured is 4.8 [V] under the same conditions as above. Therefore, there is a large error from the actual potential of the input / output pad 105, which is 4.9 [V]. This is because the measurement result is affected by the contact resistance between the first probe pin 205 and the input / output pad 105 and the power consumption in the on-resistance of the PMOS transistor 145.

[0039] In this way, in the semiconductor integrated circuit device 100 of embodiment 1, the potential of the input / output pad 105 can be measured more accurately without being affected by the contact resistance between the first probe pin 205 and the input / output pad 105, and the contact resistance between the second probe pin 210 and the ground pad 110.

[0040] This also reduces the yield loss in the current load drive capability test for the input / output pad 105. It also makes it possible to reduce the frequency of polishing the probe pins of the tester 200, thereby reducing the time required for the current load drive capability test and the time associated therewith.

[0041] [Second embodiment] Next, a semiconductor integrated circuit device 100A of embodiment 2 will be described with reference to FIG. 3. The semiconductor integrated circuit device 100A of embodiment 2 has two or more ports. That is, the semiconductor integrated circuit device 100A of embodiment 2 differs from embodiment 1 in that it has a plurality of input / output pads 105 and output buffers 115 of the semiconductor integrated circuit device 100 of embodiment 1, and in that it includes an input selector switch 125A and a port control circuit 180A. However, other than that, the configuration is basically similar. Therefore, in the following description, components similar to those of embodiment 1 will be designated by the suffix "A," and detailed description thereof will be omitted.

[0042] That is, the semiconductor integrated circuit device 100A of the second embodiment includes a plurality of, i.e., N, input / output pads 105A_1 to 105A_N, a ground pad 110A, and N output buffers 115A_1 to 115A_N. Each of the input / output pads 105A_1 to 105A_N is connected to a corresponding one of the output buffers 115A_1 to 115A_N, thereby forming a plurality of, i.e., N, ports. The semiconductor integrated circuit device 100A also includes an AD converter 120A, an input selector switch 125A, a measurement value output pad 130A, an internal test control circuit 135A, and a port control circuit 180A.

[0043] Each of the output buffers 115A_1 to 115A_N is composed of a PMOS transistor and an NMOS transistor (not shown), and the gates of the PMOS transistor and the NMOS transistor are connected to the port control circuit 180A. The port control circuit 180A selectively operates a port in response to a control signal from the internal test control circuit 135A, i.e., selects one of the output buffers 115A_1 to 115A_N to output an output signal. That is, when the Xth port is to be set to a low level ("L" level) output state or a high level ("H" level) output state, the port control circuit 180A sends a control signal to the PMOS transistor and NMOS transistor constituting the output buffer 115A_X. This causes the input / output pad 105A_X to be set to an "L" level output state or an "H" level output state.

[0044] Each node between the output buffers 115A_1 to 115A_N and the input / output pads 105A_1 to 105A_N is connected to an input node 155A of the AD converter 120A via an input selector switch 125A. The input selector switch 125A is switched by a control signal from the port control circuit 180A so that the port selected by the port control circuit 180A and the input node 155A of the AD converter 120A are electrically connected. That is, the input selector switch 125A operates to selectively obtain the potentials of the N input / output pads 105A_1 to 105A_N and use them as inputs to the AD converter 120A.

[0045] Furthermore, the upper reference voltage node 160A of the AD converter 120A is connected to a reference voltage source 170A, and the lower reference voltage node 165A is connected to the ground pad 110A. Furthermore, the digital output node 175A of the AD converter 120A is connected to the measurement value output pad 130A via the ADC control circuit 140A, and outputs the digital value converted by the AD converter 120A.

[0046] A method for testing the current load driving capability of the semiconductor integrated circuit device 100A of the second embodiment configured as described above will be described. As shown in Fig. 3, the tester 200A has a plurality of first probe pins 205A_1 to 205A_N. The tester 200A also has a second probe pin 210A and a third probe pin 215A. The tester 200A also has a current load module 220A, which generates a constant current of a preset magnitude and selectively supplies it to the plurality of first probe pins 205A_1 to 205A_N.

[0047] The tester 200A further includes an evaluation module 225A that evaluates the digital output signal input via the third probe pin 215A. The tester 200A further includes a setting module 230A that sends a test start signal, a test end signal, and an instruction to select a port for forcing or sinking current to the internal test control circuit 135A of the semiconductor integrated circuit device 100A. The second probe pin 210A is connected to ground.

[0048] The first probe pins 205A_1 to 205A_N of the tester 200A configured as described above are brought into contact with the input / output pads 105A_1 to 105A_N, respectively. The second probe pin 210A is brought into contact with the ground pad 110A, and the third probe pin 215A is brought into contact with the measurement value output pad 130A. Next, the tester 200A sends a test start signal to the internal test control circuit 135A of the semiconductor integrated circuit device 100A via the probe pins and pads (both of which are not designated by reference numerals for simplicity) connected to the setting module 230A, thereby operating the internal test control circuit 135A. The setting module 230A also sends a selection instruction to the internal test control circuit 135A regarding which port a constant current of a preset magnitude is to be forced or sunk.

[0049] In response to this, the internal test control circuit 135A selects a port to be tested. For example, when testing the Xth port, the internal test control circuit 135A outputs a control signal to the port control circuit 180A to select the output buffer 115A_X.

[0050] The port control circuit 180A controls the conductive or non-conductive state of the PMOS transistor and NMOS transistor that constitute the output buffer 115A_X of the Xth port in response to a control signal from the internal test control circuit 135A, thereby setting the input / output pad 105A_X of the selected Xth port to an "L" level output state or an "H" level output state.

[0051] The internal test control circuit 135A sets the number of output bits of the AD converter 120A to the ADC control circuit 140A, and outputs a control signal to convert the potential input to the input node 155A of the AD converter 120A into a digital value.

[0052] When the input / output pad 105A_X of the selected Xth port outputs an "L" level, the current load module 220A forces a constant current of a preset magnitude into the input / output pad 105A_X via the selected Xth first probe pin 205A_X.

[0053] Furthermore, in response to an instruction from the setting module 230A of the tester 200A, the port control circuit 180A switches the input selector switch 125A so that the input / output pad 105A_X of the Xth port is in a conductive state with the input node 155A of the AD converter 120A. That is, the input selector switch 125A selectively acquires the potential of the input / output pad 105A_X of the Xth port and uses it as the input of the AD converter 120A.

[0054] Then, a constant current of a preset magnitude flows from the input / output pad 105A_X through the drain-source of the NMOS transistor constituting the output buffer 115A_X, the ground pad 110A, and the second probe pin 210A_X to the ground of the tester 200A. At this time, the potential of the input / output pad 105A_X is applied to the input node 155A of the AD converter 120A.

[0055] Then, as in the first embodiment, the AD converter 120A converts the potential difference between the input / output pad 105A_X and the ground pad 110A into a digital value and outputs it to the measurement value output pad 130A via the ADC control circuit 140A. The tester 200A receives the output value via the third probe pin 215A and evaluates the output value using the evaluation module 225A.

[0056] When the input / output pad 105A_X of the selected Xth port outputs an "H" level, the current load module 220A sinks a constant current of a preset magnitude from the input / output pad 105A_X via the selected Xth first probe pin 205A_X.

[0057] Furthermore, the port control circuit 180A controls the switching operation of the input changeover switch 125A so that the input / output pad 105A_X of the selected Xth port is brought into a conductive state with the input node 155A of the AD converter 120A.

[0058] Then, a constant current of a preset magnitude flows through the source-drain of the PMOS transistor constituting the output buffer 115A_X, the input / output pad 105A_X, and the first probe pin 205A_X to the tester 200A. At this time, the potential of the input / output pad 105A_X is applied to the input node 155A of the AD converter 120A.

[0059] As in the first embodiment, the AD converter 120A converts the potential difference between the input / output pad 105A_X and the ground pad 110A into a digital value and outputs it to the measurement value output pad 130A via the ADC control circuit 140A. The tester 200A receives the output value via the third probe pin 215A and evaluates it by comparing it with an expected value using the evaluation module 225A.

[0060] The semiconductor integrated circuit device 100A of the above-described embodiment 2 can achieve the same effects as those of embodiment 1. That is, testing can be performed without being affected by the contact resistance between the first probe pins 205A_1 to 205A_N and the input / output pads 105A_1 to 105A_N, and between the second probe pin 210A and the ground pad 110A. That is, the potential of the input / output pads 105A_1 to 105A_N can be accurately measured without being affected by the contact resistance between the probe pins and the pads.

[0061] This also reduces the yield reduction in the current load driving capability test performed on the input / output pads 105A_1 to 105A_N. Also, it becomes possible to reduce the frequency of polishing the probe pins of the tester 200A, thereby reducing the time required for the current load driving capability test and related tests. [Explanation of symbols]

[0062] 100, 100A semiconductor integrated circuit device 105, 105A_1~105A_N Input / Output Pads 110, 110A ground pad 115, 115A_1 to 115A_N output buffer 120, 120A AD converter 125 Input Switch 125A input selector switch 130, 130A Measurement Output Pad 135, 135A Internal test control circuit 140, 140A ADC control circuit 145 PMOS transistors 150 NMOS transistors 155, 155A input node 160, 160A Upper reference voltage node 165, 165A Lower Reference Voltage Node 170, 170A Reference Voltage Source 175, 175A Digital Output Node 180A port control circuit 200, 200A tester 205, 205A_1~205A_N 1st probe pin 210, 210A Second probe pin 215, 215A 3rd probe pin 220, 220A Current Load Module 225, 225A Evaluation Module 230, 230A Setting Module

Claims

1. an input / output pad connected to an external input / output terminal; an output buffer connected to the input / output pad; an AD converter connected to the input / output pad as an input, which acquires and converts into a digital value the potential of the input / output pad when the input / output pad is in a low level output state and a constant current of a preset magnitude is caused to flow from an externally connected tester to the input / output pad, or when the input / output pad is in a high level output state and a constant current of a preset magnitude is caused to flow from the input / output pad to the tester; a measurement value output pad that outputs the digital value converted by the AD converter.

2. two or more input / output pads and two or more output buffers connected to the input / output pads; 2. The semiconductor integrated circuit device according to claim 1, further comprising an input changeover switch that operates to selectively acquire potentials of said two or more input / output pads and use the acquired potentials as inputs to said AD converter.

3. 3. The semiconductor integrated circuit device according to claim 2, wherein said input changeover switch is controlled to selectively obtain potentials of said two or more input / output pads in response to an instruction from said tester and use the potentials as inputs to said AD converter.

4. 4. A test method for a semiconductor integrated circuit device according to claim 1, comprising: a step of causing a constant current of a preset magnitude to flow from a tester externally connected to the input / output pad, or causing a constant current of a preset magnitude to flow from the input / output pad to the tester; comparing the digital value output from the measurement value output pad with an expected value; A method for testing a semiconductor integrated circuit device.

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