Semiconductor package

Abstract

To provide a semiconductor package with improved structural stability, and a manufacturing method for the same.SOLUTION: A chip stack CS includes two chip structures 300 and 300' stacked in a vertical direction. The chip structure 300 includes a first semiconductor chip 100 and a second semiconductor chip 200 disposed thereon. The first semiconductor chip includes a first penetration via 112 penetrating a first semiconductor substrate 110, a first substrate pad 130 on a first active surface of the first semiconductor substrate, a second substrate pad 160 on a first inactive surface, and a subpad 150 disposed between the first and second substrate pads. The second semiconductor chip includes a second penetration via 212 penetrating a second semiconductor substrate 210, a third substrate pad 230 on a second active surface of the second semiconductor substrate, and a fourth substrate pad 250 directly connected to the second penetration via on a second inactive surface. The fourth substrate pad of the chip structure 300 and a second substrate pad 160' of the chip structure 300' are directly bonded together.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a semiconductor package and a method for manufacturing the same. [Background technology]

[0002] With the development of the electronics industry, there is an increasing demand for high performance, high speed, and miniaturization of electronic components. In response to this trend, recent packaging technology has progressed toward mounting multiple semiconductor chips in a single package.

[0003] Recently, the rapid increase in demand for portable devices has led to a demand for smaller and lighter electronic components mounted on these products. To meet this demand, not only is there a demand for technology to reduce the individual size of mounted components, but there is also a demand for semiconductor packaging technology that can integrate multiple individual elements into a single package. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] US Patent No. 11,594,521 B2 Summary of the Invention [Problem to be solved by the invention]

[0005] SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor package having improved structural stability and a method for manufacturing the same.

[0006] Another problem to be solved by the present invention is to provide a miniaturized semiconductor package. [Means for solving the problem]

[0007] A semiconductor package according to an embodiment of the present invention includes two vertically stacked chip structures, each of which includes a first semiconductor chip and a second semiconductor chip disposed on the first semiconductor chip. The first semiconductor chip may include a first through-via extending through a first semiconductor substrate, a first integrated circuit disposed on a first active surface of the first semiconductor substrate, a first substrate pad on the first active surface of the first semiconductor substrate, a second substrate pad on a first non-active surface of the first semiconductor substrate, and a sub-pad disposed between the first through-via and the second substrate pad. The second semiconductor chip may include a second through-via extending through a second semiconductor substrate, a second integrated circuit disposed on a second active surface of the second semiconductor substrate, a third substrate pad on the second active surface of the second semiconductor substrate, and a fourth substrate pad on the second non-active surface of the second semiconductor substrate directly connected to the second through-via. The first active surface may face the second active surface. The first substrate pad and the third substrate pad may be directly bonded. The fourth substrate pad of a lower chip structure among the chip structures may be directly bonded to the second substrate pad of an upper chip structure among the chip structures, and a distance from the first inactive surface to a lower surface of the second substrate pad may be greater than a distance from the second inactive surface to an upper surface of the fourth substrate pad.

[0008] A semiconductor package according to an embodiment of the present invention may include a base chip including a base integrated circuit disposed on a front surface of the base chip, external connection terminals disposed on the front surface of the base chip, and base substrate pads disposed on a rear surface of the base chip; a chip structure vertically stacked on the base chip; and a molding film surrounding the chip structure on the base chip. Each of the chip structures may include a first semiconductor chip and a second semiconductor chip disposed on the front surface of the first semiconductor chip. The first semiconductor chip may include a first integrated circuit disposed on a first active surface of a first semiconductor substrate, first substrate pads on the first active surface, and a second pad structure on a first non-active surface of the first semiconductor substrate. The second semiconductor chip may include a second integrated circuit disposed on a second active surface of a second semiconductor substrate, third substrate pads on the second active surface, and fourth substrate pads on the second non-active surface of the second semiconductor substrate. In each of the chip structures, the first substrate pad and the third substrate pad contact each other, the back surface of the base chip faces the first inactive surface of the lowest chip structure among the chip structures, and the base substrate pad and the second pad structure of the lowest chip structure may be vertically aligned.

[0009] A semiconductor package according to an embodiment of the present invention may include a first chip structure including a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip and connected to the first semiconductor chip, and a second chip structure including a third semiconductor chip and a fourth semiconductor chip stacked on the third semiconductor chip and connected to the third semiconductor chip. The second chip structure may be stacked on the first chip structure, and the third semiconductor chip may be stacked on the second semiconductor chip and connected to the second semiconductor chip. An active surface of the first semiconductor chip having a first integrated circuit may face an active surface of a second semiconductor chip having a second integrated circuit. A non-active surface of the third semiconductor chip opposite to the active surface of the third semiconductor chip having a third integrated circuit may face a non-active surface of the second semiconductor chip opposite to the active surface of the second semiconductor chip. [Effects of the Invention]

[0010] In the semiconductor package according to the embodiment of the present invention, the semiconductor chips are directly bonded, and metal pads are provided only on the bottom of one of the two bonded semiconductor chips, thereby providing a miniaturized semiconductor package.

[0011] In the semiconductor package according to an embodiment of the present invention, when semiconductor chips are stacked, the active surfaces of the semiconductor chips face each other, so that pressure generated by distortion is offset, thereby providing a semiconductor package with improved structural stability. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention; [Figure 2] 1 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention; [Figure 3] 1 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention; [Figure 4] 1 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention; [Figure 5] 1 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention; [Figure 6] 1 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention; [Figure 7] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 8] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 9] 1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 10]1A to 1C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0013] A semiconductor package according to the concept of the present invention will now be described with reference to the drawings.

[0014] FIG. 1 is a cross-sectional view showing a semiconductor package according to an embodiment of the present invention. Referring to FIG. 1, a first semiconductor chip 100 may be provided. The first semiconductor chip 100 may include a first semiconductor substrate 110 and a first wiring layer 120 on the first semiconductor substrate 110. The first semiconductor chip 100 may have a front surface and a back surface. Hereinafter, the front surface may be defined as a surface of a semiconductor chip on which a wiring pattern is formed, and the back surface may be defined as the surface opposite the front surface. The first semiconductor chip 100 may be provided face-up. For example, the front surface of the first semiconductor chip 100 may be the top surface of the first semiconductor chip 100.

[0015] The first semiconductor substrate 110 may include a semiconductor substrate. The first semiconductor substrate 110 may include a semiconductor material. For example, the first semiconductor substrate 110 may include silicon (Si). The first semiconductor substrate 110 may have an active surface and a non-active surface. Hereinafter, the active surface is defined as a surface of a semiconductor substrate on which an integrated device or integrated circuit is formed, and the non-active surface may be defined as the surface opposite the active surface. Although not shown, an integrated device or integrated circuit may be formed on the top surface of the first semiconductor substrate 110. The top surface of the first semiconductor substrate 110 may be the active surface. The integrated device or integrated circuit may include a memory circuit. That is, the first semiconductor chip 100 may be a memory chip such as a DRAM, SRAM, MRAM, or flash memory. Alternatively, the integrated device or integrated circuit may include other types of circuits, such as a logic circuit.

[0016] The first semiconductor chip 100 may include a first through via 112 and a first wiring layer 120. The first wiring layer 120 may be provided on the active surface of the first semiconductor substrate 110. The first wiring layer 120 may be electrically connected to the integrated device or the integrated circuit on the first semiconductor substrate 110. The first wiring layer 120 may have a first insulating pattern 124 and a first wiring pattern 122 provided within the first insulating pattern 124. The first insulating pattern 124 may cover the integrated device or the integrated circuit on the active surface of the first semiconductor substrate 110. The first wiring pattern 122 may be electrically connected to the integrated device or the integrated circuit on the first semiconductor substrate 110. An upper end of the first wiring pattern 122 may be exposed on an upper surface of the first insulating pattern 124. The first wiring pattern 122 may be made of a conductive material such as a metal. For example, the first wiring pattern 122 may include copper (Cu). The first insulating pattern 124 may include an oxide such as silicon dioxide (SiOx).

[0017] The first through via 112 may penetrate the first semiconductor substrate 110 in a first direction D1. In this specification, the first direction D1 may be a direction perpendicular to the active surface of the first semiconductor substrate 110. One end of the first through via 112 may be connected to the first wiring pattern 122. The other end of the first through via 112 may be exposed on the non-active surface of the first semiconductor substrate 110.

[0018] A first substrate pad 130 may be provided on the first wiring layer 120. In this case, the first substrate pad 130 may be disposed on the upper end of the first wiring pattern 122 and connected to the first wiring pattern 122. The first substrate pad 130 may include a conductive material. For example, the first substrate pad 130 may include copper (Cu). A first insulating layer 140 may be provided on the first wiring layer 120. The first insulating layer 140 may cover the upper surface of the first wiring layer 120 and surround the first substrate pad 130. The upper surface of the first substrate pad 130 may be exposed on the upper surface of the first insulating layer 140. The first insulating layer 140 may include silicon oxide (SiOx), silicon nitride (SiNx), etc.

[0019] A subpad 150 and a test pad 180 may be provided on the lower surface of the first through via 112. As shown, the first through via 112 may be connected to each of the subpad 150 and the test pad 180. The subpad 150 may be connected to a portion of the lower surface of the first through via 112, and the test pad 180 may be connected to the remaining portion of the lower surface of the first through via 112. More specifically, the subpad 150 and the test pad 180 may be connected to the first through via 112 through a metal via. The metal via may be disposed between the subpad 150 and the test pad 180 and the first through via 112. The metal via may be provided separately from the subpad 150 and the test pad 180 and the first through via 112, or may be formed of the same material as the subpad 150 and the test pad 180 and be provided integrally. The metal via may not be provided if necessary. In this case, the subpad 150 and the test pad 180 may be connected to the lower surface of the first through via 112 .

[0020] The subpads 150 and the test pads 180 may be spaced apart from each other in the horizontal direction. The number of test pads 180 may be less than the number of subpads 150. The test pads 180 may be located between the subpads 150. However, the present invention is not limited thereto. The first width W1 of the test pads 180 may be equal to or greater than the second width W2 of the subpads 150. The subpads 150 and the test pads 180 may include at least one of gold, silver, copper, aluminum, nickel, tin, lead, and tungsten.

[0021] Although not shown, if necessary, a wiring pattern may be further provided on the lower surface of the first through via 112. The wiring pattern may be disposed between the first through via 112 and the subpad 150 and between the first through via 112 and the test pad 180. In this case, the subpad 150 and the test pad 180 may be electrically connected to the first through via 112 through the metal via and the wiring pattern. The wiring pattern may include a conductive material such as copper (Cu).

[0022] Second substrate pads 160 may be provided on the lower surfaces of the subpads 150. The second substrate pads 160 may be vertically spaced apart from the first semiconductor substrate 110 and the first through vias 112. Each of the second substrate pads 160 may contact the lower surface of the corresponding subpad 150. The second substrate pads 160 may be electrically connected to the first through vias 112 through the subpads 150. The second substrate pads 160 may not be provided on the lower surfaces of the test pads 180. The second substrate pads 160 may include a conductive material. For example, the second substrate pads 160 may include copper (Cu). A second insulating layer 170 may be provided on the non-active surface of the first semiconductor substrate 110. The second insulating layer 170 may surround the subpads 150, the test pads 180, and the second substrate pads 160 on the non-active surface of the first semiconductor substrate 110. The test pads 180 may be embedded within the second insulating layer 170. For example, the test pads 180 may not be exposed on the lower surface of the second insulating film 170. The lower surfaces of the second substrate pads 160 may be exposed on the back surface of the first semiconductor chip 100. The lower surfaces of the second substrate pads 160 may be exposed on the lower surface of the second insulating film 170. The second insulating film 170 may include silicon oxide (SiOx), silicon nitride (SiNx), etc.

[0023] The second semiconductor chip 200 may be provided on the active surface of the first semiconductor chip 100. The second semiconductor chip 200 and the first semiconductor chip 100 may be arranged face to face. That is, the second semiconductor chip 200 may be provided face down on the first semiconductor chip 100. The second semiconductor chip 200 may include a second semiconductor substrate 210 and a second wiring layer 220 on the second semiconductor substrate 210. The second semiconductor chip 200 may be arranged such that a front surface of the second semiconductor chip 200 faces the front surface of the first semiconductor chip 100. In other words, the bottom surface of the second semiconductor chip 200 may be the front surface of the second semiconductor chip 200.

[0024] The second semiconductor substrate 210 may include a semiconductor substrate. The second semiconductor substrate 210 may include a semiconductor material. For example, the second semiconductor substrate 210 may include silicon (Si). The active surface of the second semiconductor substrate 210 may face the active surface of the first semiconductor substrate 110. An integrated device or an integrated circuit may be formed on the active surface of the second semiconductor substrate 210. For example, the integrated device or the integrated circuit may include a memory circuit. That is, the second semiconductor chip 200 may be a memory chip such as a DRAM, SRAM, MRAM, or flash memory. Alternatively, the integrated device or the integrated circuit may include other types of circuits such as a logic circuit. The first semiconductor chip 100 and the second semiconductor chip 200 may be the same type of semiconductor chip. That is, the first semiconductor chip 100 and the second semiconductor chip 200 may include the same integrated device or integrated circuit. However, the present invention is not limited thereto.

[0025] The second semiconductor chip 200 may include a second through via 212 and a second wiring layer 220. The second wiring layer 220 may be provided on the active surface of the second semiconductor substrate 210. The second wiring layer 220 may be electrically connected to the integrated device or the integrated circuit on the second semiconductor substrate 210. The second wiring layer 220 may include a second insulating pattern 224 and a second wiring pattern 222 within the second insulating pattern 224. The second insulating pattern 224 may cover the integrated device or the integrated circuit on the active surface of the second semiconductor substrate 210. The second wiring pattern 222 may be electrically connected to the integrated device or the integrated circuit on the second semiconductor substrate 210. A lower end of the second wiring pattern 222 may be exposed on the lower surface of the second insulating pattern 224. The second wiring pattern 222 may be made of a conductive material such as a metal. For example, the second wiring pattern 222 may include copper (Cu). The second insulating pattern 224 may include an oxide such as silicon dioxide (SiOx).

[0026] The second through via 212 may penetrate the second semiconductor substrate 210 in a first direction D1. One end of the second through via 212 may be connected to the second wiring pattern 222. The second through via 212 may be electrically connected to the second wiring layer 220. The other end of the second through via 212 may be exposed on the non-active surface of the second semiconductor substrate 210.

[0027] A third substrate pad 230 may be provided on the active surface of the second semiconductor substrate 210. In this case, the third substrate pad 230 may be disposed on the lower end of the second wiring pattern 222 and connected to the second wiring pattern 222. The third substrate pad 230 may include a conductive material. For example, the third substrate pad 230 may include copper (Cu). A third insulating layer 240 may be provided on the second wiring layer 220. The third insulating layer 240 may cover the lower surface of the second wiring layer 220 and surround the third substrate pad 230. The lower surface of the third substrate pad 230 may be exposed on the lower surface of the third insulating layer 240. The third insulating layer 240 may include silicon oxide (SiOx), silicon nitride (SiNx), etc.

[0028] A fourth substrate pad 250 may be provided on the upper surface of the second through via 212. The fourth substrate pad 250 may be a pad disposed on the other exposed end of the second through via 212 and connected to the second wiring pattern 222. The fourth substrate pad 250 may include a conductive material. For example, the fourth substrate pad 250 may include copper (Cu). A fourth insulating layer 260 may be provided on the non-active surface of the second semiconductor substrate 210. The fourth insulating layer 260 may cover the non-active surface of the second semiconductor substrate 210 and surround the fourth substrate pad 250. The fourth substrate pad 250 may be exposed on the back surface of the second semiconductor chip 200. Specifically, the upper surface of the fourth substrate pad 250 may be exposed on the upper surface of the fourth insulating layer 260. The fourth insulating layer 260 may include silicon oxide (SiOx), silicon nitride (SiNx), etc.

[0029] The fourth substrate pad 250 may contact the second semiconductor substrate 210. The fourth substrate pad 250 may be directly connected to the second through via 212. The second substrate pad 160 of the first semiconductor chip 100 is vertically separated from the first through via 112 by the subpad 150, so that the distance from the non-active surface of the first semiconductor substrate 110 to the lower surface of the second substrate pad 160 may be greater than the distance from the non-active surface of the second semiconductor substrate 210 to the upper surface of the fourth substrate pad 250. Because the subpad 150 is provided only on the back surface of the first semiconductor chip 100 and the fourth substrate pad 250 is directly connected to the second through via 212, a miniaturized semiconductor package may be provided.

[0030] The second semiconductor chip 200 may be mounted on the first semiconductor chip 100. The active surface of the first semiconductor substrate 110 and the active surface of the second semiconductor substrate 210 may face each other. The third substrate pads 230 of the second semiconductor chip 200 and the first substrate pads 130 of the first semiconductor chip 100 may be aligned vertically. A side surface of the first semiconductor chip 100 and a side surface of the second semiconductor chip 200 may be aligned in a first direction D1. The side surface of the first semiconductor chip 100 and the side surface of the second semiconductor chip 200 may be coplanar. The front surface of the first semiconductor chip 100 and the front surface of the second semiconductor chip 200 may contact each other so that the third substrate pads 230 and the first substrate pads 130 are connected to each other.

[0031] The first insulating film 140 of the first semiconductor chip 100 and the third insulating film 240 of the second semiconductor chip 200 may be bonded at the interface between the first semiconductor chip 100 and the second semiconductor chip 200. In this case, the first insulating film 140 and the third insulating film 240 may form oxide, nitride, or oxynitride hybrid bonding. In this specification, hybrid bonding refers to bonding in which two components including the same material fuse at their interface. For example, the bonded first insulating film 140 and the third insulating film 240 may have a continuous structure, and the interface between the first insulating film 140 and the third insulating film 240 may be invisible visually. The first insulating film 140 and the third insulating film 240 may be formed of the same material and provided as a single component. That is, the first insulating film 140 and the third insulating film 240 may be bonded to form a single component. However, the present invention is not limited thereto. The first insulating film 140 and the third insulating film 240 may be made of different materials, and the first insulating film 140 and the third insulating film 240 may not have a continuous structure.

[0032] The first semiconductor chip 100 and the second semiconductor chip 200 may be in contact with each other. The first substrate pads 130 of the first semiconductor chip 100 and the third substrate pads 230 of the second semiconductor chip 200 may be directly bonded to each other at the interface between the first semiconductor chip 100 and the second semiconductor chip 200. For example, the first substrate pads 130 and the third substrate pads 230 may form metal-to-metal hybrid bonding. The bonded first substrate pads 130 and the third substrate pads 230 may have a continuous structure, and the interface between the first substrate pads 130 and the third substrate pads 230 may be invisible. For example, the first substrate pads 130 and the third substrate pads 230 may be made of the same material and provided as a single component. For example, the first substrate pads 130 may be bonded to the third substrate pads 230 to form a single component. Hereinafter, the coupling between the first substrate pad 130 and the third substrate pad 230 will be described in more detail based on one first substrate pad 130 and one third substrate pad 230.

[0033] Referring to FIG. 1, the width of the first substrate pad 130 may be the same as the width of the third substrate pad 230. Although FIG. 1 illustrates the width of the first substrate pad 130 as being the same as the width of the third substrate pad 230, the present invention is not limited thereto. Either the width of the first substrate pad 130 or the width of the third substrate pad 230 may be larger than the other. In this case, at least a portion of the third substrate pad 230 may vertically overlap at least a portion of the first substrate pad 130. The planar shape of the first substrate pad 130 may be the same as the planar shape of the third substrate pad 230. The planar shapes of the first substrate pad 130 and the third substrate pad 230 may be circular or rectangular. However, the present invention is not limited thereto. The first semiconductor chip 100 and the second semiconductor chip 200 bonded together may form a single first structure 300.

[0034] Although not shown, a molding film may be further provided to surround the first semiconductor chip 100 and the second semiconductor chip 200, if necessary. The upper surface of the molding film may be coplanar with the back surface of the second semiconductor chip 200. The lower surface of the molding film may be coplanar with the back surface of the first semiconductor chip 100. The molding film may include an insulating polymer material. For example, the molding film may include epoxy molding compound (EMC).

[0035] Referring to FIG. 2, a semiconductor package having a two-tier structure may be provided by stacking two structures vertically. The two-tier semiconductor package may be formed by vertically stacking two first structures 300 described with reference to FIG. 1. For ease of explanation, one of the two structures may be referred to as the first structure 300, and the other structure disposed on the top surface of the first structure 300 may be referred to as the second structure 300'. Although referred to as the second structure 300', the type and configuration of the second structure 300' may be substantially the same as those of the first structure 300. For example, the second structure 300' may include a first semiconductor chip 100' and a second semiconductor chip 200', which may be substantially the same as the first semiconductor chip 100 and the second semiconductor chip 200 of the first structure 300 described with reference to FIG. 1, respectively.

[0036] A second structure 300' may be provided on the top surface of the first structure 300. The first and second structures 300, 300' may be arranged back-to-back. For example, the back surface of the second semiconductor chip 200 of the first structure 300 and the back surface of the first semiconductor chip 100 of the second structure 300' may contact each other. The non-active surface of the second semiconductor substrate 210 of the first structure 300 and the non-active surface of the first semiconductor substrate 110 of the second structure 300' may face each other. The fourth substrate pad 250 of the first structure 300 and the second substrate pad 160' of the second structure 300' may be vertically aligned. The side of the first structure 300 and the side of the second structure 300' may be spaced apart from each other. The first structure 300 and the second structure 300' may be electrically connected.

[0037] The fourth insulating film 260 of the first structure 300 and the second insulating film 170' of the second structure 300' may be bonded at the interface between the first structure 300 and the second structure 300'. In this case, the fourth insulating film 260 of the first structure 300 and the second insulating film 170' of the second structure 300' may form oxide, nitride, or oxynitride hybrid bonding. The bonded fourth insulating film 260 and second insulating film 170' may have a continuous structure, and the interface between the fourth insulating film 260 and the second insulating film 170' may be visually invisible. For example, the fourth insulating film 260 and the second insulating film 170' may be formed of the same material and provided as a single component. That is, the fourth insulating film 260 and the second insulating film 170' may be bonded to form a single integral structure. However, the present invention is not limited thereto. The fourth insulating layer 260 and the second insulating layer 170' may be made of different materials, and the fourth insulating layer 260 and the second insulating layer 170' may not be continuous.

[0038] The fourth substrate pad 250 of the first structure 300 and the second substrate pad 160' of the second structure 300' may be directly bonded to each other at the interface between the first structure 300 and the second structure 300'. For example, the fourth substrate pad 250 of the first structure 300 and the second substrate pad 160' of the second structure 300' may form a metal-to-metal hybrid bond. The bonded fourth substrate pad 250 of the first structure 300 and the second substrate pad 160' of the second structure 300' may have a continuous structure, and the interface between the fourth substrate pad 250 and the second substrate pad 160' may not be visible. For example, the fourth substrate pad 250 and the second substrate pad 160' may be made of the same material and provided as a single component.

[0039] 3, a third semiconductor chip 400 may be further provided on the bottom surface of the first structure 300 described with reference to FIG. 1. The third semiconductor chip 400 may be arranged back-to-back on the bottom surface of the first structure 300. That is, the third semiconductor chip 400 may be provided face-down. For example, the front surface of the third semiconductor chip 400 may be the bottom surface of the third semiconductor chip 400. The third semiconductor chip 400 may include a third semiconductor substrate 410 and a third wiring layer 420.

[0040] The third semiconductor substrate 410 may include a semiconductor substrate. The third semiconductor substrate 410 may include a semiconductor material. For example, the third semiconductor substrate 410 may include silicon (Si). An integrated device or an integrated circuit may be formed on the active surface of the third semiconductor substrate 410. For example, the integrated device or the integrated circuit may include a logic circuit. In this case, the third semiconductor chip 400 may be a logic chip. Alternatively, the integrated device or the integrated circuit may include a memory circuit. That is, the third semiconductor chip 400 may be a memory chip such as a DRAM, an SRAM, an MRAM, or a flash memory.

[0041] The third semiconductor chip 400 may include a third through via 412 and a third wiring layer 420. The third wiring layer 420 may be provided on the active surface of the third semiconductor substrate 410. The third wiring layer 420 may be electrically connected to the integrated device or the integrated circuit on the third semiconductor substrate 410. The third wiring layer 420 may have a third insulating pattern 424 and a third wiring pattern 422 provided in the third insulating pattern 424. The third insulating pattern 424 may cover the integrated device or the integrated circuit on the active surface of the third semiconductor substrate 410. The third wiring pattern 422 may be electrically connected to the integrated device or the integrated circuit on the third semiconductor substrate 410. One end of the third through via 412 may be connected to the third wiring pattern 422. The third wiring pattern 422 may be electrically connected to the third through via 412. A portion of the third wiring pattern 422 may protrude above the lower surface of the third insulating pattern 424. The protruding portion of the third wiring pattern 422 may be a first external connection pad connected to a first external terminal 430 (described later). The third wiring pattern 422 may be made of a conductive material such as a metal. For example, the third wiring pattern 422 may include copper (Cu). The third insulating pattern 424 may include an oxide such as silicon oxide (SiOx).

[0042] The third through via 412 may penetrate the third semiconductor substrate 410 in a first direction D1. One end of the third through via 412 may be connected to the third wiring pattern 422. The other end of the third through via 412 may be exposed on the non-active surface of the third semiconductor substrate 410. A first external terminal 430 may be provided on a lower surface of the first external connection pad. The first external terminal 430 may be electrically connected to the third semiconductor chip 400 through the first external connection pad. The first external terminal 430 may include a solder ball or a solder bump.

[0043] A fifth substrate pad 440 may be provided on the upper surface of the third through via 412. The fifth substrate pad 440 may be a pad disposed on the other exposed end of the third through via 412 and connected to the third wiring pattern 422. The fifth substrate pad 440 may include a conductive material. For example, the fifth substrate pad 440 may include copper (Cu). A fifth insulating layer 450 may be provided on the non-active surface of the third semiconductor substrate 410. The fifth insulating layer 450 may cover the non-active surface of the third semiconductor substrate 410 and surround the fifth substrate pad 440. The upper surface of the fifth substrate pad 440 may be exposed on the upper surface of the fifth insulating layer 450. The fifth insulating layer 450 may include silicon oxide (SiOx), silicon nitride (SiNx), etc.

[0044] The first structure 300 may be mounted on the third semiconductor chip 400. The back surface of the third semiconductor chip 400 and the back surface of the first semiconductor chip 100 of the first structure 300 may face each other. The fifth substrate pads 440 of the third semiconductor chip 400 and the second substrate pads 160 of the first structure 300 may be vertically aligned. The first semiconductor chip 100 and the third semiconductor chip 400 may contact each other such that the aligned fifth substrate pads 440 and second substrate pads 160 are connected to each other. The width of the third semiconductor chip 400 may be the same as or wider than the width of the first structure 300.

[0045] The second insulating film 170 of the first semiconductor chip 100 and the fifth insulating film 450 of the third semiconductor chip 400 may be bonded to each other at the interface between the first semiconductor chip 100 and the third semiconductor chip 400. The second insulating film 170 and the fifth insulating film 450 may form oxide, nitride, or oxynitride hybrid bonding. The bonded second insulating film 170 and the fifth insulating film 450 may have a continuous structure, and the interface between the second insulating film 170 and the fifth insulating film 450 may be invisible. For example, the second insulating film 170 and the fifth insulating film 450 may be formed of the same material and provided as a single component. That is, the second insulating film 170 and the fifth insulating film 450 may be bonded to form a single unit. However, the present invention is not limited thereto. The second insulating film 170 and the fifth insulating film 450 may be formed of different materials, and the second insulating film 170 and the fifth insulating film 450 do not have to have a continuous structure.

[0046] The second substrate pad 160 of the first semiconductor chip 100 and the fifth substrate pad 440 of the third semiconductor chip 400 may be bonded to each other at the interface between the first semiconductor chip 100 and the third semiconductor chip 400. In this case, the second substrate pad 160 and the fifth substrate pad 440 may be directly bonded to each other. For example, the second substrate pad 160 and the fifth substrate pad 440 may form a metal-to-metal hybrid bond. The bonded second substrate pad 160 and the fifth substrate pad 440 may have a continuous structure, and the interface between the second substrate pad 160 and the fifth substrate pad 440 may be invisible. For example, the second substrate pad 160 and the fifth substrate pad 440 may be formed of the same material and provided as a single component. That is, the second substrate pad 160 may be bonded to the fifth substrate pad 440 to form a single component. The first semiconductor chip 100 and the third semiconductor chip 400 bonded together can form one stacked structure.

[0047] 3 illustrates the third semiconductor chip 400 and the first structure 300 being in contact with each other, but the present invention is not limited thereto. The first structure 300 may be mounted on the third semiconductor chip 400 using connecting terminals. The connecting terminals may include solder balls or solder bumps. The connecting terminals may be disposed between the second substrate pads 160 and the fifth substrate pads 440. An underfill film may be provided on the underside of the first structure 300 to surround the connecting terminals. Since the third semiconductor chip 400 and the first structure 300 are connected using the connecting terminals, the third semiconductor chip 400 and the first structure 300 may be spaced apart in the vertical direction.

[0048] 3 illustrates one first structure 300 mounted on the third semiconductor chip 400, but the present invention is not limited thereto. A plurality of first structures 300 may be stacked on the third semiconductor chip 400. In this case, any two adjacent first structures 300 among the plurality of first structures 300 may be coupled back-to-back as described with reference to FIG.

[0049] 4, a chip stack CS may be provided that is substantially similar to the stack structure of FIG. 3, in that one first structure 300 is further stacked vertically on the stack structure of FIG. Two adjacent first structures 300 may be arranged back-to-back and hybrid-bonded to each other, as shown in FIG. 2. The chip stack CS may include a third semiconductor chip 400, a first structure 300 stacked on the third semiconductor chip 400, a fourth semiconductor chip 500 on the first structure 300, and a first molding film 520 surrounding the first structure 300 and the fourth semiconductor chip 500. The configuration of the chip stack CS will be described in detail below.

[0050] The chip stack CS may include a first structure 300 stacked on a third semiconductor chip 400. Although FIG. 4 illustrates two first structures 300 stacked on the third semiconductor chip 400, the present invention is not limited thereto, and the number of first structures 300 stacked on the third semiconductor chip 400 may vary as needed. The width of the third semiconductor chip 400 may be wider than the width of the first structures 300. The first structures 300 may be disposed at the center of the third semiconductor chip 400. Hereinafter, for convenience of explanation, as with FIG. 2, of the two first structures 300 illustrated in FIG. 4, the one disposed at the bottom may be referred to as the first structure 300, and the other first structure 300 disposed on the top surface of the lower first structure 300 may be referred to as the second structure 300'. Although referred to as second structure 300', second structure 300' may be substantially identical to first structure 300 and may include first semiconductor chip 100' and second semiconductor chip 200'.

[0051] In this case, the second semiconductor chip 200' of the second structure 300' may not include the second through via 212' (see FIG. 2) and the fourth substrate pad 250' (see FIG. 2). When three or more first structures 300 are stacked, the second semiconductor chip 200 of the uppermost first structure 300 among the first structures 300 may not include the second through via 212 and the fourth substrate pad 250. However, when two first structures 300 are stacked, the second semiconductor chip 200 on top of the first structure 300 may have the same structural elements including the second through via 212 and the fourth substrate pad 250.

[0052] The first semiconductor chip 100 and the second semiconductor chip 200 of each first structure 300 may be bonded face-to-face, and two adjacent first structures 300 may be bonded back-to-back. In other words, the first semiconductor chip 100 and the second semiconductor chip 200 may be alternately stacked on the third semiconductor chip 400, thereby providing alternate back-to-back and face-to-face structures.

[0053] A fourth semiconductor chip 500 may be disposed on the upper surface of the second structure 300′. The fourth semiconductor chip 500 may be a semiconductor substrate. For example, the fourth semiconductor chip 500 may be a semiconductor substrate such as a semiconductor wafer. The fourth semiconductor chip 500 may not include an integrated circuit. A sixth insulating film 510 may be provided on the lower surface of the fourth semiconductor chip 500. The sixth insulating film 510 may cover the lower surface of the fourth semiconductor chip 500. The sixth insulating film 510 may include silicon oxide (SiOx), silicon nitride (SiNx), etc. At the interface between the second structure 300′ and the fourth semiconductor chip 500, the sixth insulating film 510 and the fourth insulating film 260′ of the second structure 300′ may be in contact with each other. In this case, the fourth insulating film 260′ and the sixth insulating film 510 may form oxide, nitride, or oxynitride hybrid bonding. The fourth insulating film 260′ and the sixth insulating film 510 bonded together may have a continuous structure, and the interface between the fourth insulating film 260′ and the sixth insulating film 510 may not be visible. For example, the fourth insulating film 260′ and the sixth insulating film 510 may be made of the same material, and the fourth insulating film 260′ and the sixth insulating film 510 may be bonded together to form a single film. However, the present invention is not limited to this. The fourth insulating film 260′ and the sixth insulating film 510 may be made of different materials, and the fourth insulating film 260′ and the sixth insulating film 510 may not have a continuous structure.

[0054] If necessary, an adhesive layer may be provided instead of the sixth insulating layer 510 and the fourth insulating layer 260' of the second structure 300'. The adhesive layer may be disposed between the fourth semiconductor chip 500 and the second structure 300'. The adhesive layer may be provided on at least one of the bottom surface of the fourth semiconductor chip 500 and the back surface of the uppermost second semiconductor chip 200'. The adhesive layer may bond the bottom surface of the fourth semiconductor chip 500 and the back surface of the second semiconductor chip 200' to each other.

[0055] A first molding film 520 may be disposed on the back surface of the third semiconductor chip 400. The first molding film 520 may cover the back surface of the third semiconductor chip 400. The first molding film 520 may surround the first structure 300, the second structure 300′, and the fourth semiconductor chip 500 on the back surface of the third semiconductor chip 400. The top surface of the first molding film 520 may be coplanar with the top surface of the fourth semiconductor chip 500. The top surface of the fourth semiconductor chip 500 may be exposed on the top surface of the first molding film 520. The first molding film 520 may include an insulating polymer material. For example, the first molding film 520 may include an epoxy molding compound (EMC).

[0056] 5, the chip stack CS may be substantially similar to the chip stack CS (see FIG. 4) described with reference to FIG. 4, except that the chip stack CS further includes a connecting chip 600 instead of the first molding film 520. The connecting chip 600 may include a first connecting chip 610 and a second connecting chip 620.

[0057] The first connecting chip 610 may be disposed on the back surface of the third semiconductor chip 400. The first connecting chip 610 may contact the back surface of the third semiconductor chip 400. The top surface of the first connecting chip 610 may be coplanar with the non-active surface of the second semiconductor substrate 210 of the first structure 300. The first connecting chip 610 may include a first connecting substrate 612 and a first connecting layer 614 provided on the bottom surface of the first connecting substrate 612. The first connecting substrate 612 may be a semiconductor substrate such as a semiconductor wafer. For example, the first connecting substrate 612 may be a silicon (Si) substrate. However, the present invention is not limited thereto, and the first connecting substrate 612 may be made of a material having high thermal conductivity, such as ceramic, glass, or metal.

[0058] The first connecting chip 610 may have a first opening 616 penetrating therethrough. For example, the first opening 616 may have an open hole shape connecting the upper and lower surfaces of the first connecting chip 610. The first structure 300 may be disposed in the first opening 616 of the first connecting chip 610. The first structure 300 may be spaced apart from an inner wall of the first opening 616. A side surface of the first structure 300 may face the inner wall of the first opening 616. A first filling layer 618 may be provided to fill a gap between the first opening 616 and the first structure 300. Specifically, the first filling layer 618 may fill a gap between the inner wall of the first opening 616 and the side surface of the first structure 300. The first filling layer 618 may include an insulating polymer, silicon oxide (SiOx), silicon nitride (SiNx), or the like.

[0059] 4, the fourth insulating film 260 may be provided on the upper surface of the first connecting chip 610. Unlike in FIG. 4, the fourth insulating film 260 may extend from the non-active surface of the second semiconductor substrate 210 to cover the upper surface of the first connecting chip 610. The fourth insulating film 260 may surround the fourth substrate pads 250 and fill the gap between the non-active surface of the second semiconductor substrate 210 and the lower surface of the second structure 300′, and the gap between the upper surface of the first connecting chip 610 and the lower surface of a second connecting chip 620 (described later).

[0060] A first connecting layer 614 may be provided on the lower surface of the first connecting substrate 612. The first connecting layer 614 and the fifth insulating layer 450 may be in contact with each other. The first connecting layer 614 may include silicon oxide (SiOx), silicon nitride (SiNx), etc. The first connecting layer 614 and the fifth insulating layer 450 may form an oxide, nitride, or oxynitride hybrid bonding.

[0061] A second connecting chip 620 may be provided on the upper surface of the first connecting chip 610. The second connecting chip 620 may be vertically spaced apart from the first connecting chip 610. At least a portion of the second connecting chip 620 may vertically overlap at least a portion of the first connecting chip 610. The upper surface of the second connecting chip 620 may be coplanar with the non-active surface of the second semiconductor substrate 210' of the second structure 300'. The second connecting chip 620 may include a second connecting substrate 622 and a second connecting layer 624 provided on the lower surface of the second connecting substrate 622. The second connecting substrate 622 may be a semiconductor substrate such as a semiconductor wafer. For example, the second connecting substrate 622 may be a silicon (Si) substrate. However, the present invention is not limited thereto, and the second connecting substrate 622 may be made of a material having high thermal conductivity, such as ceramic, glass, or metal. The first connecting substrate 612 and the second connecting substrate 622 may be made of the same material. However, the present invention is not limited thereto.

[0062] The second connecting substrate 622 may have a second opening 626 penetrating therethrough. For example, the second opening 626 may have an open hole shape connecting the upper and lower surfaces of the second connecting chip 620. A second structure 300′ may be disposed within the opening 626 of the second connecting chip 620. The second structure 300′ may be disposed spaced apart from the inner wall of the second opening 626. The side of the second structure 300′ may face the inner wall of the second opening 626. A second filling layer 628 may be provided to fill the gap between the second opening 626 and the second structure 300′. Specifically, the second filling layer 628 may fill the gap between the inner wall of the second opening 626 and the side of the second structure 300′. The second filling layer 628 may include an insulating polymer, silicon oxide (SiOx), silicon nitride (SiNx), etc. The material forming the first filling layer 618 and the material forming the second filling layer 628 can be the same.

[0063] 4, the fourth insulating layer 260' may be provided on the top surface of the second connecting chip 620. Unlike in FIG. 4, the fourth insulating layer 260' may extend from the non-active surface of the second semiconductor chip 200' to cover the top surface of the second connecting chip 620. The fourth insulating layer 260' may fill the gap between the non-active surface of the second semiconductor chip 200' and the bottom surface of the fourth semiconductor chip 500, and the gap between the top surface of the second connecting chip 620 and the bottom surface of the sixth insulating layer 510.

[0064] A second connecting layer 624 may be provided on the lower surface of the second connecting substrate 622. The second connecting layer 624 and the fourth insulating layer 260 of the first structure 300 may be in contact with each other. The second connecting layer 624 may include silicon oxide (SiOx), silicon nitride (SiNx), etc. The second connecting layer 624 and the fourth insulating layer 260 may form an oxide, nitride, or oxynitride hybrid bonding.

[0065] The fourth semiconductor chip 500 may be disposed on the top surface of the second connecting chip 620 and the second structure 300′. In this case, the fourth semiconductor chip 500 may be substantially similar to the fourth semiconductor chip 500 (see FIG. 4) described with reference to FIG. 4. However, unlike what is shown in FIG. 4, the width of the fourth semiconductor chip 500 may be wider than the width of the second structure 300′. The width of the fourth semiconductor chip 500 may be the same as the width of the second connecting chip 620. For example, the fourth semiconductor chip 500 may cover the top surface of the second connecting chip 620.

[0066] The sixth insulating film 510 and the fourth insulating film 260′ of the second structure 300′ may contact each other. The sixth insulating film 510 and the fourth insulating film 260′ may form oxide, nitride, or oxynitride hybrid bonding. Although FIG. 5 illustrates the connecting chip 600 including the first connecting chip 610 and the second connecting chip 620, the present invention is not limited thereto. The connecting chip 600 may be provided as a single substrate on the back surface of the third semiconductor chip 400. The single substrate may include at least one of silicon (Si), ceramic, glass, and metal. The single substrate may be attached to the back surface of the third semiconductor chip 400 through an insulating film provided on its bottom surface, similar to the first connecting chip 610. The top surface of the single substrate may be coplanar with the non-active surface of the second semiconductor chip 200' of the second structure 300'. The single substrate may have a third opening penetrating therethrough. For example, the third opening may have an open hole shape connecting the top and bottom surfaces of the single substrate. The first structure 300 and the second structure 300' may be disposed in the third opening. The first structure 300 and the second structure 300' may be spaced apart from the inner wall of the third structure. The side surfaces of the first and second structures 300 and 300' may face the inner wall of the third opening. A third filling layer may be provided to fill the space between the side surfaces of the first and second structures 300 and 300' and the inner wall of the third opening. The third filling layer may be formed of the same material as the first and second filling layers 618 and 628.

[0067] In other words, the single substrate may be the same as the first and second connecting substrates 612 and 622 connected without an interface. In this case, the second connecting layer 624 between the first connecting substrate 612 and the second connecting substrate 622 may not be provided. Also, the fourth insulating layer 260 may not extend onto the first connecting substrate 612. For example, as shown in FIG. 4, the fourth insulating layer 260 may fill the gap between the first structure 300 and the second structure 300′. The first connecting substrate 612 may extend onto the bottom surface of the fourth semiconductor chip 500 and be connected to the second connecting substrate 622. The connected first connecting substrate 612 and second connecting substrate 622 may be integrally formed without an interface therebetween. The connected first connecting substrate 612 and second connecting substrate 622 may be attached to the back surface of the third semiconductor chip 400 through the first connecting layer 614 disposed on the bottom surface thereof. Furthermore, the first and second filling layers 618 and 628 may be integrally formed to form a single filling layer. The single filling layer may fill the spaces between the side surfaces of the first and second structures 300 and 300′ and the inner walls of the connected first and second connecting substrates 612 and 622.

[0068] 6, a fifth semiconductor chip 700 disposed on the upper surface of the first structure 300 and a second molding film 750 surrounding the first structure 300 may further be provided. In this case, the first structure 300 may be substantially the same as the first structure 300 (see FIG. 1) described with reference to FIG. 1. The fifth semiconductor chip 700 may include a fifth semiconductor substrate 710 and a fifth wiring layer 720 on the fifth semiconductor substrate 710. The fifth semiconductor chip 700 may be provided face down. That is, the front surface of the fifth semiconductor chip 700 may be the bottom surface of the fifth semiconductor chip 700.

[0069] The fifth semiconductor substrate 710 may include a semiconductor substrate. The fifth semiconductor substrate 710 may include a semiconductor material. For example, the fifth semiconductor substrate 710 may include silicon (Si). Although not shown, an integrated device or an integrated circuit may be formed on the active surface of the fifth semiconductor substrate 710. For example, the integrated device or the integrated circuit may include a logic circuit. That is, the fifth semiconductor chip 700 may be a logic chip.

[0070] The fifth semiconductor chip 700 may include a fifth wiring layer 720. The fifth wiring layer 720 may be provided on the active surface of the fifth semiconductor substrate 710. The fifth wiring layer 720 may be electrically connected to the integrated device or the integrated circuit on the fifth semiconductor substrate 710. The fifth wiring layer 720 may have a fifth insulation pattern 724 and a fifth wiring pattern 722 provided within the fifth insulation pattern 724. The fifth insulation pattern 724 may cover the integrated device or the integrated circuit on the active surface of the fifth semiconductor substrate 710. The fifth wiring pattern 722 may be electrically connected to the integrated device or the integrated circuit on the fifth semiconductor substrate 710. A lower end of the fifth wiring pattern 722 may protrude from a lower surface of the fifth insulation pattern 724. The fifth wiring pattern 722 may be made of a conductive material such as a metal. For example, the fifth wiring pattern 722 may include copper (Cu). The fifth insulation pattern 724 may include an oxide such as silicon dioxide (SiOx). The protruding lower end of the fifth wiring pattern 722 may be a sixth board pad 730. However, the present invention is not limited thereto, and the sixth board pad 730 may be a separate pad disposed on the lower surface of the fifth wiring pattern 722 and connected to the fifth wiring pattern 722.

[0071] A seventh insulating film 740 may be provided on the lower surface of the fifth wiring layer 720. The seventh insulating film 740 may cover the lower surface of the fifth wiring layer 720 and surround the sixth substrate pads 730. The lower surfaces of the sixth substrate pads 730 may be exposed on the lower surfaces of the seventh insulating film 740. The seventh insulating film 740 may include silicon oxide (SiOx), silicon nitride (SiNx), or the like. The width of the fifth semiconductor chip 700 may be wider than the width of the first structure 300. The upper surface of the first structure 300 may be located on the center of the front surface of the fifth semiconductor chip 700. In a plan view, the fifth semiconductor chip 700 may vertically overlap the entire first structure 300.

[0072] A second molding film 750 may be provided that surrounds the first structure 300 in the horizontal direction, and a molding through-film via 752 may be provided that penetrates the second molding film 750 in the vertical direction. In a plan view, the second molding film 750 may vertically overlap the outer portion of the fifth semiconductor chip 700. An upper surface of the second molding film 750 may be coplanar with the upper surface of the first structure 300. A lower surface of the second molding film 750 may be coplanar with the lower surface of the first structure 300. The second molding film 750 may include an insulating polymer material. For example, the second molding film 750 may include epoxy molding compound (EMC). One end of the molding through-film via 752 may contact the lower surface of the sixth substrate pad 730. The other end of the molding through-film via 752 may be exposed on the lower surface of the second molding film 750. The molding through-film via 752 may include copper (Cu). The molding through-film vias 752 may be electrically connected to the integrated circuit through the fifth wiring layer 720 .

[0073] Second external connection pads 770 may be disposed on the lower surface of the second molding film 750 and the lower surface of the first structure 300. The second external connection pads 770 may be disposed spaced apart from each other in the horizontal direction. Some of the second external connection pads 770 may be electrically connected to the exposed other ends of the molding through-film vias 752. Other parts of the second external connection pads 770 may be electrically connected to the second substrate pads 160. A protective layer 760 surrounding the second external connection pads 770 may be provided on the lower surfaces of the second molding film 750 and the first structure 300. The protective layer 760 may cover the lower surfaces of the second molding film 750 and the first structure 300 and surround the second external connection pads 770. The lower surfaces of the second external connection pads 770 may be exposed on the lower surfaces of the protective layer 760. A second external terminal 780 may be provided on the second external connection pads 770. Each of the second external terminals 780 may be disposed on the lower surface of the corresponding second external connection pad 770. The second external terminals 780 may be electrically connected to the first structure 300 and the fifth semiconductor chip 700 through the second external connection pad 770. The second external terminals 780 may include solder balls or solder bumps.

[0074] 7 to 10 are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention.

[0075] 7, a second semiconductor substrate 210 may be provided. A second through via 212 may be formed inside the second semiconductor chip 200. A second wiring layer 220 may be formed on the second semiconductor substrate 210. An insulating material may be deposited on the second wiring layer 220 to form a third insulating layer 240. The third insulating layer 240 may be patterned to form holes in which third substrate pads 230 are provided. The third substrate pads 230 may be formed on the third insulating layer 240 to fill the holes. The third substrate pads 230 may be formed through a plating process. The top surface of the third substrate pads 230 may be exposed on the top surface of the third insulating layer 240.

[0076] 8, a first semiconductor substrate 110 may be provided. A first through via 112 may be formed inside the first semiconductor chip 100. A first wiring layer 120 may be formed on an active surface of the first semiconductor substrate 110. An insulating material may be deposited on the first wiring layer 120 to form a first insulating film 140. The first insulating film 140 may be patterned to form holes in which first substrate pads 130 are to be provided. The first substrate pads 130 may be formed on the first insulating film 140 to fill the holes. The first substrate pads 130 may be formed through a plating process. The top surfaces of the first substrate pads 130 may be exposed on the top surface of the first insulating film 140.

[0077] The active surface of the second semiconductor substrate 210 may be provided facing the active surface of the first semiconductor substrate 110. For example, the first semiconductor substrate 110 may be disposed upside down so that the exposed upper surface of the first substrate pad 130 faces the exposed upper surface of the third substrate pad 230. In other words, the first wiring layer 120 and the second wiring layer 220 may be disposed facing each other so that the first substrate pad 130 and the third substrate pad 230 are vertically aligned.

[0078] Then, the first semiconductor substrate 110 and the second semiconductor substrate 210 may be brought into contact with each other. A heat treatment process may be performed on the first and second semiconductor substrates 110 and 210. The heat treatment process may include applying heat to the first and second semiconductor substrates 110 and 210 and bonding the first substrate pad 130 and the third substrate pad 230 to form a single body using the heat. Bonding of the first substrate pad 130 and the third substrate pad 230 may occur naturally. In particular, the first substrate pad 130 and the third substrate pad 230 may be made of the same material (e.g., copper (Cu)), and the first substrate pad 130 and the third substrate pad 230 may be bonded to each other using a surface activation-based intermetallic hybrid bonding process (e.g., Cu-Cu hybrid bonding) at the bonding surfaces of the first and third substrate pads 130 and 230. The heat treatment process may bond the first insulating layer 140 and the third insulating layer 240. For example, the first insulating layer 140 and the third insulating layer 240 may be bonded to form an integral layer.

[0079] Referring to FIG. 9 , subpads 150, second substrate pads 160, and test pads 180 may be formed on the non-active surface of a first semiconductor substrate 110. A grinding process may be performed on the non-active surface of the first semiconductor substrate 110. The grinding process may expose top surfaces of first through vias 112 disposed within the first semiconductor substrate 110. The subpads 150 and test pads 180 may be formed on the ground non-active surface of the first semiconductor substrate 110. A first insulating material may be deposited on the ground top surface of the first semiconductor substrate 110. The deposited first insulating material may be patterned to form holes for the subpads 150 and test pads 180, respectively. The subpads 150 and test pads 180 may be formed on the deposited first insulating material, filling the holes. The process of forming the subpads 150 and the process of forming the test pads 180 may be performed simultaneously. A second insulating material may be deposited on the first insulating material. The deposited second insulating material may be patterned to form holes for providing second substrate pads 160. The second substrate pads 160 may be formed on the deposited second insulating material by filling the holes. The deposited first insulating material and the deposited second insulating material may form the second insulating film 170. Although FIG. 10 illustrates the first and second insulating materials forming the second insulating film 170, the type and number of insulating materials forming the second insulating film 170 may vary as needed. The test pads 180 may be pads for evaluating electrical characteristics of the first semiconductor substrate 110 and the second semiconductor substrate 210. The electrical characteristic evaluation may include a test that applies a voltage to the test pads 180. For example, the test may include an EDS (electrical die sorting) test. The electrical characteristic evaluation may be performed between the process of forming the test pads 180 and the process of forming the second substrate pads 160.

[0080] 10, a carrier substrate 1000 may be provided. The resultant structure of FIG. 9 may be disposed upside down on the top surface of the carrier substrate 1000. Thus, the second semiconductor chip 200 may be positioned on top of the first semiconductor chip 100. The subpad 150 may be disposed facing the top surface of the carrier substrate 1000.

[0081] A fourth substrate pad 250 and a fourth insulating layer 260 may be formed on the non-active surface of the second semiconductor substrate 210. First, a grinding process may be performed on the non-active surface of the second semiconductor substrate 210. The grinding process may expose an upper surface of the second through via 212 disposed within the second semiconductor substrate 210. The ground non-active surface of the second semiconductor substrate 210 may be coplanar with the upper surface of the second through via 212. An insulating material may be deposited on the ground non-active surface of the second semiconductor substrate 210 to form a fourth insulating layer 260. The fourth insulating layer 260 may be patterned to form a hole for providing the fourth substrate pad 250. The fourth substrate pad 250 may be formed on the fourth insulating layer 260, filling the hole. The upper surface of the fourth substrate pad 250 may be exposed on the upper surface of the fourth insulating layer 260.

[0082] Thereafter, the carrier substrate 1000 may be removed. A sawing process may be performed along the sawing lines SL to form a plurality of first structures. Referring again to FIG. 1, each of the first structures separated by the sawing process may correspond to the chip structure 300 (see FIG. 1) of FIG. 1. [Explanation of symbols]

[0083] 100 First semiconductor chip 110 First semiconductor substrate 112 First through via 120 1st wiring layer 122 First wiring pattern 124 First insulation pattern 130 First board pad 140 First insulating film 150 Subpad 160 2nd board pad 170 Second insulating film 180 Test Pad 200 Second semiconductor chip 210 second semiconductor substrate 212 Second through via 220 2nd wiring layer 222 Second wiring pattern 224 Second insulation pattern 230 3rd board pad 240 Third insulating film 250 4th board pad 260 4th insulating film 300 Chip Structure 400 Third Semiconductor Chip 410 third semiconductor substrate 412 3rd Through Via 420 3rd wiring layer 422 Third wiring pattern 424 Third insulation pattern 430 First external terminal 440 5th PCB pad 450 5th insulating film 500 4th semiconductor chip 520 First molding film CS Chip Stack

Claims

1. comprising two vertically stacked chip structures; Each of the chip structures includes a first semiconductor chip and a second semiconductor chip disposed on the first semiconductor chip; The first semiconductor chip a first through via that penetrates the first semiconductor substrate; a first integrated circuit disposed on a first active surface of the first semiconductor substrate; a first substrate pad on the first active surface of the first semiconductor substrate; a second substrate pad on a first non-active surface of the first semiconductor substrate; a subpad disposed between the first through via and the second substrate pad; The second semiconductor chip is a second through via that penetrates the second semiconductor substrate; a second integrated circuit disposed on a second active surface of the second semiconductor substrate; a third substrate pad on the second active surface of the second semiconductor substrate; a fourth substrate pad on a second non-active surface of the second semiconductor substrate, the fourth substrate pad being directly connected to the second through via; the first active surface faces the second active surface, and the first substrate pad and the third substrate pad are directly bonded to each other; the fourth substrate pad of the lower chip structure among the chip structures and the second substrate pad of the upper chip structure among the chip structures are directly bonded; A semiconductor package in which a distance from the first non-active surface to a lower surface of the second substrate pad is greater than a distance from the second non-active surface to an upper surface of the fourth substrate pad.

2. further comprising a third semiconductor chip disposed on a lower surface of the lower chip structure; the third semiconductor chip includes a third integrated circuit disposed on a third active surface of a third semiconductor substrate and a fifth substrate pad on a third inactive surface of the third semiconductor substrate; the width of the third semiconductor chip is wider than the width of the chip structure; 2. The semiconductor package of claim 1, wherein the first inactive surface of the lower chip structure faces the third inactive surface, and the second substrate pad and the fifth substrate pad of the lower chip structure are directly bonded.

3. 2. The semiconductor package of claim 1, further comprising a first insulating film surrounding the first substrate pad on the first active surface and a second insulating film surrounding the third substrate pad on the second active surface, the first insulating film and the second insulating film being in contact with each other.

4. the fourth substrate pad is directly connected to the second through via; the second substrate pad is vertically spaced apart from the first through via; The semiconductor package of claim 1 , wherein the second substrate pad is electrically connected to the first through via through the subpad.

5. 2. The semiconductor package of claim 1, further comprising a test pad spaced apart from the subpad in a horizontal direction, the test pad having a width greater than a width of the subpad.

6. The semiconductor package of claim 1 , wherein a side surface of the first semiconductor chip and a side surface of the second semiconductor chip are aligned in a direction perpendicular to the first active surface.

7. a molding film surrounding the chip structure; a molding through-film via vertically penetrating the molding film; an external connection terminal disposed on a lower surface of the molding film; and a fourth semiconductor chip disposed on the second inactive surface of the upper chip structure, the fourth semiconductor chip includes a fourth integrated circuit disposed on a fourth active surface of a fourth semiconductor substrate and a sixth substrate pad on the fourth active surface, the width of the fourth semiconductor chip being wider than the width of the chip structure; the second inactive surface of the upper chip structure faces the fourth active surface, and the fourth substrate pad and the sixth substrate pad of the upper chip structure are directly bonded to each other; The semiconductor package of claim 1 , wherein the molding through-film via extends from the fourth active surface and is connected to the external connection terminal.

8. a fifth semiconductor chip disposed on the upper surface of the chip structure; and a third insulating film interposed between the upper surface of the upper chip structure and the fifth semiconductor chip, The semiconductor package of claim 1 , wherein the fifth semiconductor chip is attached to the top surface of the upper chip structure through the third insulating film.

9. a base chip including a base integrated circuit disposed on a front surface of the base chip, external connection terminals disposed on the front surface of the base chip, and base substrate pads disposed on a rear surface of the base chip; a chip structure stacked vertically on the base chip; a molding film surrounding the chip structure on the base chip; each of the chip structures includes a first semiconductor chip and a second semiconductor chip provided on a front surface of the first semiconductor chip; the first semiconductor chip includes a first integrated circuit disposed on a first active surface of a first semiconductor substrate, a first substrate pad on the first active surface, and a second pad structure on a first non-active surface of the first semiconductor substrate; the second semiconductor chip includes a second integrated circuit disposed on a second active surface of a second semiconductor substrate, third substrate pads on the second active surface, and fourth substrate pads on a second non-active surface of the second semiconductor substrate; In each of the chip structures, the first substrate pad and the third substrate pad are in contact with each other, the back surface of the base chip faces the first inactive surface of the lowest chip structure among the chip structures, and the base substrate pad and the second pad structure of the lowest chip structure are aligned vertically.

10. a base insulating layer surrounding the base substrate pad on the back surface of the base chip and a first insulating layer surrounding the second pad structure on the first non-active surface of the bottom chip structure, The semiconductor package of claim 9 , wherein the base insulating film and the first insulating film are in contact with each other.

11. the first semiconductor chip further includes a first through via that penetrates the first semiconductor substrate and is electrically connected to the first integrated circuit; the second pad structure includes a subpad and a second substrate pad; 10. The semiconductor package of claim 9, wherein the subpad is disposed between the first through via and the second substrate pad, and the second substrate pad is electrically connected to the first integrated circuit through the subpad and the first through via.

12. 12. The semiconductor package of claim 11, further comprising a test pad disposed on the first non-active surface and spaced apart from the subpad in a horizontal direction, the test pad and the subpad being made of the same material.

13. The semiconductor package of claim 11 , wherein a distance from the first non-active surface to a lower surface of the second substrate pad is greater than a distance from the second non-active surface to an upper surface of the fourth substrate pad.

14. a third semiconductor chip disposed on an upper surface of an uppermost chip structure among the chip structures; and a second insulating film interposed between the upper surface of the uppermost chip structure and the third semiconductor chip, The semiconductor package of claim 9 , wherein the third semiconductor chip is attached to the top surface of the uppermost chip structure through the second insulating film.

15. a connecting substrate disposed on the back surface of the base chip and having an opening; The chip structure is disposed within the opening; a top surface of the connecting substrate and a top surface of the uppermost chip structure are coplanar; the third semiconductor chip covers the top surface of the connecting substrate and the top surface of the uppermost chip structure; 15. The semiconductor package of claim 14, wherein the second insulating film extends from between the third semiconductor chip and the uppermost chip structure toward the upper surface of the connecting substrate, and the second insulating film fills the space between the connecting substrate and the third semiconductor chip.

16. an inner surface of the opening spaced apart from a side surface of the tip structure; The semiconductor package according to claim 15 , further comprising a first filling layer filling a space between the inner surface of the opening and the side surface of the chip structure.

17. a first chip structure including a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip and connected to the first semiconductor chip; a second chip structure including a third semiconductor chip and a fourth semiconductor chip stacked on the third semiconductor chip and connected to the third semiconductor chip, the second chip structure is stacked on the first chip structure, and the third semiconductor chip is stacked on the second semiconductor chip and connected to the second semiconductor chip; an active surface of the first semiconductor chip having a first integrated circuit facing an active surface of a second semiconductor chip having a second integrated circuit; A semiconductor package in which a non-active surface of the third semiconductor chip opposite an active surface of the third semiconductor chip having a third integrated circuit faces a non-active surface of the second semiconductor chip opposite the active surface of the second semiconductor chip.

18. 20. The semiconductor package of claim 17, wherein the active surface of the third semiconductor chip faces an active surface of the fourth semiconductor chip having a fourth integrated circuit.

19. a base chip on which the first chip structure is stacked and connected to the first chip structure; a molding layer or a connecting substrate surrounding the first and second chip structures on the base chip; 18. The semiconductor package of claim 17, wherein the inactive surface of the first semiconductor chip faces the base chip.

20. a test pad provided on the inactive surface of the first semiconductor chip; The semiconductor package of claim 19 , wherein the test pad is not connected to the base chip.

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