Isolation device having inductive and capacitive isolation circuit

Abstract

To provide an isolated gate driver for high frequency operation.SOLUTION: An isolation circuit arrangement may include an isolation barrier and may be configured to receive one or more input signals on a low voltage side and deliver one or more output signals on a high voltage side. The isolation barrier may include a first capacitor, arranged along a first input line, a second capacitor arranged along a second input line, electrically parallel to the first capacitor, and a first inductor having a first end that is coupled to a first electrode of the first capacitor and having a second end that is coupled to a first electrode of the second capacitor. The isolation barrier may further include a center tap, connected to the first inductor, and a second inductor that is inductively coupled to the first inductor and is arranged with a first output end and a second output end on a high voltage side of the isolation circuit arrangement.SELECTED DRAWING: Figure 1A

Description

[Technical Field]

[0001] Embodiments relate to the field of circuit protection devices, including isolated gate drivers and digital isolators. [Background technology]

[0002] An insulated gate bipolar transistor (IGBT) or power metal oxide semiconductor field effect transistor (MOSFET) each represents a voltage-controlled device used as a switching element in power supply circuits and motor drives, among other systems. The gate is the electrically isolated control terminal for each device. The other terminals for a MOSFET are the source and drain, while for an IGBT the other terminals are called the collector and emitter. To operate a MOSFET / IGBT, a voltage is applied to the gate, which is referenced to the source / emitter of the device. A dedicated driver is used to apply voltage and provide drive current to the gate of the power device.

[0003] In order for an IGBT / power MOSFET to operate as a switch, a voltage sufficiently greater than the gate threshold voltage should be applied between the gate and source / emitter terminals. A gate driver can be provided to convert a low power input from a microcontroller into a high current drive input for the gate of a high power transistor such as an IGBT or power MOSFET.

[0004] For systems using gate drivers, galvanic isolation may be necessary for functional purposes and may also be a safety requirement. In particular, galvanic isolation may be a requirement between the high-power side and the low-voltage control circuitry if there is any human involvement on the control side. Isolation also protects the low-voltage electronics from any damage caused by a fault on the high-power side. In one example, an isolated gate driver circuit may employ a capacitive structure to provide galvanic isolation from the controller side (low voltage) to the high-power switch side (high voltage).

[0005] A parameter of interest for the operation of isolated gate drivers for high-frequency operation is common-mode transient immunity (CMTI). CMTI can refer to the maximum allowable rate of rise or fall of the common-mode voltage applied between two isolated circuits. It is usually expressed in units of kV / μs or V / ns. A relatively higher CMTI means that the two isolated circuits, i.e., both the transmitter and receiver sides, will perform relatively better without error when very large rising or falling slew rates hit the isolation barrier.

[0006] In recent years, wide bandgap (WBG) semiconductors have attracted increasing attention for use as power transistors, including SiC, GaN, and other known WBG materials. These materials enable faster switching speeds compared to, for example, silicon. In particular, fast switching on the order of 3 ns or less is possible in the context of isolated gate driver circuits. This fast switching can generate disturbances across the isolation barrier, ultimately impairing gate driver operation. In particular, switching from 0 to 1000 V in 3 ns may require a CMTI of at least 300 kV / ms, a capability that may not be readily available in today's gate driver circuits. Furthermore, even higher CMTI may be required for switching at higher voltages.

[0007] It is with respect to the above that the present disclosure is provided. Summary of the Invention

[0008] In one embodiment, an isolation circuit device is provided. The isolation circuit device may include an isolation barrier configured to receive one or more input signals on a low-voltage side and send one or more output signals on a high-voltage side. The isolation barrier may include a first capacitor disposed along a first input line and a second capacitor disposed along a second input line in electrical parallel with the first capacitor. The isolation barrier may also include a first inductor having a first end coupled to a first electrode of the first capacitor and a second end coupled to a first electrode of the second capacitor. The isolation barrier may further include a center tap connected to the first inductor and a second inductor inductively coupled to the first inductor and disposed on the high-voltage side of the isolation circuit device with first and second output ends.

[0009] In another embodiment, a gate driver device is provided. The gate driver device includes a signal source that generates one or more control signals and an isolation barrier that receives the one or more control signals, and the isolation barrier may include an isolation circuit. The isolation circuit may include a first capacitor disposed along a first input line and a second capacitor disposed along a second input line in a manner electrically parallel to the first capacitor. The isolation circuit may also include a first inductor having a first end coupled to the first capacitor and a second end coupled to the second capacitor. The isolation circuit may further include a center tap connected to the first inductor and a second inductor inductively coupled to the first inductor and disposed on the high-voltage side of the gate driver device with a first output end and a second output end.

[0010] In a further embodiment, a gate driver apparatus is provided, comprising a signal source that generates one or more control signals and an isolation barrier that receives the one or more control signals. The isolation barrier may have an isolation circuit including a first capacitor disposed along a first input line and a second capacitor disposed along a second input line in a manner electrically parallel to the first capacitor. The isolation barrier may also include a first inductor having a first end coupled to the first capacitor and a second end coupled to the second capacitor. The isolation barrier may further include a grounded center tap connected to the first inductor, and a second inductor inductively coupled to the first inductor and disposed on a high-voltage side of the gate driver apparatus with a first output end and a second output end. The gate driver apparatus may also include a demodulator coupled to the second inductor, and a gate driver coupled to the demodulator and configured to output a drive signal to a gate of a power switch. [Brief explanation of the drawings]

[0011] [Figure 1A] FIG. 2 is a diagram of a gate driver apparatus according to an embodiment of the present disclosure.

[0012] [Figure 1B] FIG. 10 is a diagram of another gate driver apparatus according to an embodiment of the present disclosure.

[0013] [Figure 2A] FIG. 1C is a diagram of one instance of operation of the device of FIG. 1B.

[0014] [Figure 2B] FIG. 10 is a detailed diagram of a common mode voltage pulse.

[0015] [Figure 3] FIG. 1 is a top view of an insulating tip according to some embodiments of the present disclosure.

[0016] [Figure 4] FIG. 10 is a diagram of another gate driver apparatus according to a further embodiment of the present disclosure.

[0017] [Figure 5A] FIG. 10 is a diagram of an isolation circuit arrangement according to a further embodiment of the present disclosure.

[0018] [Figure 5B] 5B is an image of one embodiment of the connection between the isolation circuits of FIG. 5A.

[0019] [Figure 6] FIG. 10 is a diagram of an isolation circuit arrangement according to an additional embodiment of the present disclosure.

[0020] [Figure 7] FIG. 10 is a diagram of an isolation circuit arrangement according to an additional embodiment of the present disclosure.

[0021] [Figure 8] FIG. 10 is a diagram of an isolation circuit arrangement according to an additional embodiment of the present disclosure.

[0022] [Figure 9] FIG. 10 is a diagram of an isolation circuit arrangement according to a further embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0023] The present embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments are shown. These embodiments should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the embodiments to those skilled in the art. In the drawings, like numbers refer to like elements throughout.

[0024] In the following description and / or claims, the terms "on," "overlying," "disposed on," and "over" may be used in the following description and claims. "On," "overlying," "disposed on," and "over" may be used to indicate that two or more elements are in direct physical contact with each other. The terms "on," "overlying," "disposed on," and "over" may also mean that two or more elements are not in direct contact with each other. For example, "over" may mean that one element is on top of another element but is not in contact with each other, and there may be another element or elements between the two elements. Additionally, the term "and / or" can mean "and," it can mean "or," it can mean "exclusive-or," it can mean "one," it can mean "some, but not all," it can mean "neither," and / or it can mean "both," although the scope of the claimed subject matter is not limited in this respect.

[0025] In various embodiments, systems, devices, and techniques are provided for isolated gate driver circuits. According to some embodiments, circuit configurations are disclosed to provide examples of functional equivalents for implementing isolated gate driver circuits, as described below, where the actual component details and circuit arrangements for implementing the gate drive signals may vary, as will be understood by those skilled in the art.

[0026] 1A, an isolation circuit device 10 according to some embodiments of the present disclosure is shown. The isolation circuit device 10 implements an isolation function to provide galvanic isolation between signal sources located on the low voltage (LV) side of the isolation circuit device 10. The signal source 102 may be, for example, a microcontroller that outputs a control signal used to control the gate of a power switch located on the HV side of the isolation circuit device 10.

[0027] 1A, the isolation circuit apparatus 10 includes an isolation circuit 104. This circuit can function as an isolation barrier to provide galvanic isolation between the signal source 102 and other circuitry operating at low voltages and circuitry operating on the high voltage (HV) side of the isolation circuit apparatus 10.

[0028] Isolation circuit 104 includes a novel configuration of capacitive and inductive elements that provide galvanic isolation between the low voltage (LV) side and the HV side within isolation circuit apparatus 10. As depicted in FIG. 1A , isolation circuit 104 may include a first capacitor 112 disposed along a first input line 122 and a second capacitor 114 disposed along a second input line 124. Second capacitor 114 is disposed in an electrically parallel manner to first capacitor 112. In various embodiments, first capacitor 112 and second capacitor 114 may be configured to have the same capacitance.

[0029] The isolation circuit 104 may further include an inductive circuit configured, for example, like a coreless transformer having first and second inductors. As shown in FIG. 1A, a first inductor 116 is provided having a first end coupled to the first capacitor 112 and a second end coupled to the second capacitor 114. A second inductor 118 is provided and is inductively coupled to the first inductor 116 and is arranged to be coupled to a component such as a demodulator 128.

[0030] In various non-limiting embodiments, the isolation circuit 104 may be located within a semiconductor chip that may be a standalone chip separate from the signal source 102, while in other embodiments, the isolation circuit 104 may be integrated on the same chip as the signal source 102. Similarly, in some embodiments, the isolation circuit may be provided on a chip separate from HV side components such as the demodulator 128, while in other embodiments, the isolation circuit 104 may be integrated on the same chip as other HV side components such as the demodulator 128.

[0031] Referring to FIG. 1B , an isolation circuit arrangement 100 according to some embodiments of the present disclosure is shown. The isolation circuit arrangement 100 implements an isolated gate driver function for controlling the operation of a power switching circuitry 106. The power switching circuitry may be implemented using known power transistors, such as IGBTs or power MOSFETs. In either case, the isolation circuit arrangement is structured to provide a control signal to the gate of the power transistor of the power switching circuitry 106. In some examples, the voltage across the main terminal of the high-side switch of the power switching circuitry 106 may be up to 1 kV or greater. The isolation circuit arrangement 100 may include a drive signal source, shown as signal source 102, such as a microcontroller that outputs a gate driver signal used to control the gate of the power switching circuitry 106. This signal source 102 may operate on the low-voltage side of the isolation circuit arrangement 100. 2A and 2B, the signal source 102 may output a series of drive pulses that cause the power switching circuitry 106 to output a series of voltage pulses having an amplitude corresponding to the maximum voltage across the power switching circuitry 106.

[0032] 1B, the isolation circuit arrangement 100 includes an isolation circuit 104 configured to provide galvanic isolation between the signal source 102 and other circuitry operating at low voltage, and power switching circuitry 106 operating on the high voltage (HV) side of the isolation circuit arrangement 100.

[0033] Isolation circuit 104 includes a novel configuration of capacitive and inductive elements that provide galvanic isolation between the low voltage (LV) side and the HV side within isolation circuit apparatus 100. As depicted in FIG. 1B , isolation circuit 104 may include a first capacitor 112 disposed along a first input line 122 and a second capacitor 114 disposed along a second input line 124. Second capacitor 114 is disposed in an electrically parallel manner to first capacitor 112. In various embodiments, first capacitor 112 and second capacitor 114 may be configured to have the same capacitance.

[0034] The isolation circuit 104 may further include an inductive circuit configured, for example, like a coreless transformer having first and second inductors. As shown in FIG. 1B , a first inductor 116 is provided, having a first end coupled to the first capacitor 112 and a second end coupled to the second capacitor 114. A second inductor 118 is provided, inductively coupled to the first inductor 116 and disposed with a first output end electrically coupled to a demodulator 128. The output of the demodulator 128 connects to a gate driver for a gate terminal 130 of a power switch 132. The second end of the second inductor 118 may be coupled to the low-voltage side of the power switch 132 via the demodulator 128, as shown.

[0035] In various non-limiting embodiments, the isolation circuit 104 may be located within a semiconductor chip, which may be a standalone chip separate from the signal source 102 and the power switch 132. For example, the isolation circuit 104 may be formed within a silicon substrate-based semiconductor chip in some embodiments, while the power switch 132 may be embodied within a separate semiconductor substrate, such as a GaN substrate, a SiC substrate, or a silicon substrate, according to different embodiments. In the example shown, the isolation circuit apparatus 100 may include a demodulator 128 and a gate driver circuit 126, with both components located on the high voltage (HV) side.

[0036] 2A illustrates one instance of the operation of the apparatus of FIG. 1B. To control the operation of the power switch 132, the signal source 102 may be configured to output a control signal 140 that is ultimately used to switch the gate terminal 130 of the power switch 132 from an on state to an off state and, in turn, drive current / voltage pulses through the power switch 132. As an example, the signal source 102 may be configured to generate the control signal 140 as a pulse-width modulated pulse train. After passing through the isolation circuit 104 and the demodulator 128, the resulting gate signal 142 may be generated by the gate driver circuit 126 to control the opening and closing of the gate terminal 130.

[0037] To illustrate the benefits of isolation circuit 104, note that in known isolated gate driver circuits, based on capacitive isolation, for example, the gate driver may be referenced to the switching node 144 of power switch 132. In such conventional circuits, when the power switch transitions between on and off states, V CM A voltage signal 146, also denoted as dV / dt, is generated. Depending on the voltage magnitude and switching speed, the slope, or dV / dt, of the voltage signal can be on the order of 100 kV / ms, 300 kV / ms, 500 kV / ms, or 1000 kV / ms or greater. This common-mode transient voltage can propagate through the isolation barrier in known isolation circuits and impair gate driver operation. In contrast, the isolation circuit 104 also provides galvanic isolation via the first capacitor 112 and the second capacitor 114, as in known gate drivers, but the isolation circuit 104 provides immunity to common-mode transients. This result is due in particular to the arrangement of the first inductor 116 and the second inductor 118 in a transformer configuration, with the center tap 120 located at the center of the current discharge.

[0038] In principle, the configuration of the isolation circuit 104 can provide protection equivalent to relatively higher values ​​of CMTI, such as at least 100 kV / ms, at least greater than 200 kV / ms, or even greater than 300 kV / ms. Therefore, if the power switching circuitry 106 is implemented in an HBG chip, such as GaN or SiC, even if the HBG chip operates at a switching speed of approximately 1 ns, the circuitry of the isolation circuit device 100, including the low-voltage side circuitry, is protected from common-mode transients that could otherwise cross the isolation barrier, thereby ensuring noise-free operation. In particular, providing a ground connection for the center tap 120 provides a path for diverting current generated in a CMT event directly to ground, so that circuitry such as the demodulator 128 is not subjected to CMT. Note that in an optional embodiment, the center tap need not be grounded, in which case the CMT immunity may not be as significant as with a grounded center tap. In some variations of the embodiment of FIG. 2B, the first inductor 116, the second inductor 118, and the center tap 120 may be arranged in a symmetrical transformer configuration to avoid the generation of any common mode signals due to asymmetry in the transformer.

[0039] FIG. 3 shows a top view of an insulating chip 148 according to some embodiments of the present disclosure. In this example, the isolation circuit 104 may be embedded within the insulating chip 148, which may be formed within any suitable semiconductor substrate, such as silicon. In this embodiment, the first capacitor 112 and second capacitor 114 of the isolation circuit 104 are arranged in a planar manner as a parallel plate structure with a pair of electrodes (only the top electrode is visible) disposed along a major plane of the semiconductor chip. Note that the first capacitor 112 and second capacitor 114 are symmetrically disposed within the insulating chip 148 and have a somewhat rectangular shape. However, according to various embodiments of the present disclosure, the first capacitor 112 and second capacitor 114 may have any suitable shape and arrangement.

[0040] In this embodiment, the first inductor 116 and second inductor 118 of the isolation circuit 104 are also arranged in a planar configuration along a major plane of the isolation chip 148. According to some embodiments, the first inductor 116 may be positioned in an interleaved manner with the second inductor 118. It should be noted that the exact shapes of the first inductor 116 and second inductor 118 may vary in different embodiments.

[0041] FIG. 4 depicts another isolation circuit device according to a further embodiment of the present disclosure. In this example, isolation circuit device 150 may include similar components to the embodiment of FIGS. 1A-1B, where similar components are numbered the same. In this example, the isolation circuit function is provided by two sections, including a first isolation circuit, represented by previously described isolation circuit 104, and a second isolation circuit, represented by isolation circuit 154. As shown, isolation circuit 104 and isolation circuit 154 are electrically arranged in series with each other. Referring to the previously described components of isolation circuit 104, each of these circuits may include a first capacitor and a second capacitor arranged in an electrically parallel manner with the first capacitor, and a first inductor and a second inductor, the first inductor having a first end coupled to the first capacitor and a second end coupled to the second capacitor. The first inductor is also center-tapped as shown.

[0042] Note that in this configuration, the first capacitor of isolation circuit 104 is conductively connected to the first capacitor of the second isolation circuit, i.e., isolation circuit 154, and the second capacitor of isolation circuit 104 is conductively connected to the second capacitor of the second isolation circuit. According to various embodiments of the present disclosure, isolation circuit 104 may be located in a first semiconductor chip, while isolation circuit 154 may be located in a second semiconductor chip.

[0043] During operation of isolation circuit apparatus 150, each transformer section directs one polarity of CMT current, i.e., one center tap is used for positive-slope CMTI events and the other center tap is used for negative-slope CMTI events. The splitting of the capacitor sections allows for implementation of isolation circuit apparatus 150 in two different chips. Note also that the ground domain within isolation circuit 104 is different from the ground domain of isolation circuit 154, as shown.

[0044] FIG. 5A depicts an isolation circuit device 200 according to a further embodiment of the present disclosure. The isolation circuit device 200 in this embodiment and in the embodiments disclosed in FIGS. 6-8 can be used, for example, as a gate driver device for controlling a switch on the high-voltage side of an isolation barrier, where the switch is a gated semiconductor device such as a MOSFET or an IGBT. The isolation circuit device 200, according to some embodiments, can be implemented in a package including two semiconductor chips. In operation, the isolation circuit device 200 can be used to couple a signal source operating on the low-voltage (LV) side to a high-voltage (HV) side component, such as the switch described above. Thus, the isolation circuit device 200 can provide galvanic isolation between the LV and HV sides, further providing the enhanced CMTI described above. In the illustrated example, the isolation circuit device 200 includes a first chip 202 and a second chip 204, and these components can be disposed in a common package, as described. In this embodiment, the isolation barrier 210 is distributed between the first chip 202 and the second chip 204. In one example, the first chip 202 may include the transmitter circuit 206, while the second chip 204 includes the demodulator 128 and the gate driver circuit 126. In the example shown, the first chip 202 may include the isolation circuit 154, while the second chip 204 includes the isolation circuit 104, as previously described. Note that the isolation circuit 154 may be located on the outer edge of the first chip 202, while the isolation circuit 104 is located on the outer edge of the second chip 204. The isolation circuit 154 may be connected to the isolation circuit 104 using any suitable conductive connector, such as bond wires (BW), and these wires may extend from each electrode of the capacitor of the isolation barrier 210. An image of one embodiment of the connection between the isolation circuit 154 and the isolation circuit 104 is shown in FIG. 5B. Thus, capacitor C1 of isolation circuit 104 is connected to capacitor C3 of isolation circuit 154 through a bond wire, while capacitor C2 of isolation circuit 104 is connected to capacitor C4 of isolation circuit 154 through a bond wire.Together, isolation circuit 104, isolation circuit 154, and bond wires BW form isolation barrier 210, and this arrangement provides galvanic isolation and enhanced CMTI. Note also that the ground domain within isolation circuit 104 is different from the ground domain of isolation circuit 154, as shown.

[0045] FIG. 6 depicts an isolation circuit device 250 according to an additional embodiment of the present disclosure. The isolation circuit device 250, according to some embodiments, may be implemented in a package including two semiconductor chips. In operation, the isolation circuit device 250 may be used to couple a signal source operating on the low voltage (LV) side to a high voltage (HV) side component, such as the switch described above. As such, the isolation circuit device 250 may provide galvanic isolation between the LV and HV sides and may further provide enhanced CMTI as described above. In the example shown, the isolation circuit device 250 includes a first chip 202 and a second chip 262, and these components may be disposed in a common package, as described. In this embodiment, the isolation barrier 260 is distributed between the first chip 202 and the second chip 262. In one example, the first chip 202 may include the transmitter circuit 206, while the second chip 262 includes the demodulator 128 and the gate driver circuit 126. In the illustrated example, the first chip 202 may include the isolation circuit 154, while the second chip 262 includes the isolation circuit 264. Note that the isolation circuit 154 may be located on the outer edge of the first chip 202, while the isolation circuit 264 is located on the outer edge of the second chip 262. As generally described above with respect to FIGS. 5A and 5B , the isolation circuit 154 may be connected to the isolation circuit 264 using any suitable conductive connector, such as bond wires (BW), which may extend from each electrode of the capacitors of the isolation barrier 260. In this case, the capacitor electrodes are connected to the inductor electrodes through the bond wires. Together, the isolation circuit 104, the isolation circuit 264, and the bond wires BW form the isolation barrier 260, and this arrangement provides galvanic isolation and enhanced CMTI. In this embodiment, the isolation circuit 264 includes a first inductor L1 and a second inductor L2, but does not include a set of capacitors. Thus, the galvanic isolation of isolation barrier 260 is provided by capacitors C3 and C4 in isolation circuit 154. Note also that the ground domain in isolation circuit 154 is different from the ground domain of isolation circuit 264, as shown.

[0046] FIG. 7 depicts an isolation circuit device 280 according to an additional embodiment of the present disclosure. The isolation circuit device 280, according to some embodiments, may be implemented in a package including two semiconductor chips. In operation, the isolation circuit device 280 may be used to couple a signal source operating on the low voltage (LV) side to a high voltage (HV) side component, such as the switch described above. As such, the isolation circuit device 280 may provide galvanic isolation between the LV side and the HV side, further providing the enhanced CMTI described above. In the example shown, the isolation circuit device 280 includes a first chip 292 and a second chip 204, and these components may be disposed in a common package as described. In this embodiment, the isolation barrier 290 is distributed between the first chip 292 and the second chip 204. In one example, the first chip 292 may include the transmitter circuit 206, while the second chip 204 includes the demodulator 128 and the gate driver circuit 126. In the illustrated example, as previously described, the first chip 292 may include the isolation circuit 294, while the second chip 204 includes the isolation circuit 104. Note that the isolation circuit 294 may be located on the outer edge of the first chip 292, while the isolation circuit 104 is located on the outer edge of the second chip 204. As generally described above with respect to FIGS. 5A and 5B , the isolation circuit 294 may be connected to the isolation circuit 104 using any suitable conductive connector, such as bond wires (BW), which may extend from each electrode of the capacitors of the isolation barrier 290. In this case, the capacitor electrodes are connected to the inductor electrodes through the bond wires. Together, the isolation circuit 104, the isolation circuit 294, and the bond wires BW form the isolation barrier 290, and this arrangement provides galvanic isolation and enhanced CMTI. In this embodiment, the isolation circuit 294 includes a first inductor L1 and a second inductor L2, but does not include a set of capacitors. Thus, the galvanic isolation of isolation barrier 290 is provided by capacitors C1 and C2 in isolation circuit 104. Note also that the ground domain in isolation circuit 104 is different from the ground domain of isolation circuit 294, as shown.

[0047] FIG. 8 depicts an isolation circuit device 300 according to an additional embodiment of the present disclosure. The isolation circuit device 300, according to some embodiments, may be implemented in a package including a single semiconductor chip, shown as chip 302. In operation, the isolation circuit device 300 may be used to couple a signal source operating on the low voltage (LV) side to a high voltage (HV) side component, such as the switch described above. As such, the isolation circuit device 300 may provide galvanic isolation between the LV side and the HV side and may further provide enhanced CMTI as described above. In the example shown, the isolation circuit device 300 includes the chip 302, which may be disposed in a package that couples the HV side components to the LV side components. In one example, the chip 302 may include the transmitter circuit 206, the demodulator 128, and the gate driver circuit 126. In the example shown, the chip 302 may include an isolation barrier 310, which provides galvanic isolation and enhanced CMTI. In this embodiment, the isolation barrier 310 includes a first inductor L1 and a second inductor L2 located on the HV side, and a third inductor L3 and a fourth inductor L4 located on the LV side. A single set of capacitors, shown as capacitors C1 and C2, is provided in the isolation circuit to provide galvanic isolation for the isolation barrier 310. Note that for implementation within a single semiconductor chip, the isolation means is required to be within the semiconductor substrate, such as in a silicon-on-insulator (SOI) architecture. Note also that the ground regions are different between the two different center taps, CT1 and CT2, as shown.

[0048] 9 illustrates an isolation circuit arrangement 400 according to a further embodiment of the present disclosure. The isolation circuit arrangement 400 may be implemented as a digital isolator for applications such as isolating communication interfaces. In this embodiment, an isolation barrier, such as any of the isolation barriers of the previous embodiments, may be disposed between a transmitter 402 on the LV side and a demodulator 404 on the HV side.

[0049] Although the present embodiments have been disclosed with reference to particular embodiments, numerous modifications, alterations, and variations can be made to the described embodiments without departing from the sphere and scope of the present disclosure, as defined by the appended claims. Accordingly, the present embodiments should not be limited to the described embodiments, but rather may have the full scope defined by the language of the following claims and their equivalents.

Claims

1. 1. An isolation circuit device configured to receive one or more input signals on a low voltage side and to provide one or more output signals on a high voltage side, the isolation circuit device comprising: a first capacitor disposed along the first input line; a second capacitor disposed along a second input line in an electrically parallel manner to the first capacitor; a first inductor having a first end coupled to the first electrode of the first capacitor and a second end coupled to the first electrode of the second capacitor; a center tap connected to the first inductor; and a second inductor inductively coupled to the first inductor and disposed on the high voltage side of the isolation circuit device with a first output end and a second output end; 1. An isolation circuit device comprising an isolation barrier having:

2. 10. The isolation circuit device of claim 1, wherein the isolation barrier is disposed within a single semiconductor chip.

3. The isolation circuit device includes: a third inductor having a first end coupled to the first capacitor and a second end coupled to the second capacitor; a center tap connected to the third inductor; and a fourth inductor inductively coupled to the third inductor and disposed on the low voltage side of the isolation circuit device with a first input end and a second input end; The isolation circuit device according to claim 2 , further comprising:

4. The first capacitor, the second capacitor, the first inductor, and the second inductor are disposed in a first isolation circuit, and a second isolation circuit is installed in the isolation circuit device, and the second isolation circuit comprises: a third capacitor connected to the first capacitor; a fourth capacitor connected to the second capacitor; a third inductor having a first end coupled to the third capacitor and a second end coupled to the fourth capacitor; and a fourth inductor inductively coupled to the third inductor and disposed on the low voltage side of the isolation circuit device with a first input end and a second input end; 3. The isolation circuit device according to claim 1, further comprising:

5. 5. The isolation circuit device of claim 4, wherein the first isolation circuit and the second isolation circuit together form an isolation barrier, the first isolation circuit is located in a first semiconductor chip, the second isolation circuit is located in a second semiconductor chip, and the first isolation circuit is connected to the second isolation circuit via a pair of conductive connectors.

6. 6. The isolation circuit device according to claim 5, wherein the first semiconductor chip further includes a transmitter, and the second semiconductor chip further includes a demodulator and a gate driver.

7. a third inductor having a first end coupled to the second electrode of the first capacitor and a second end coupled to the second end of the second capacitor; a center tap connected to the third inductor; and a fourth inductor inductively coupled to the third inductor and disposed on the low voltage side of the isolation circuit device with a first input end and a second input end; 3. The isolation circuit device according to claim 1, further comprising an inductor circuit having:

8. 8. The isolation circuit device according to claim 7, wherein the inductor circuit and the first and second capacitors are located within a first semiconductor chip, and the first and second inductors are located within a second semiconductor chip.

9. 8. The isolation circuit device according to claim 7, wherein the first capacitor, the second capacitor, the first inductor, and the second inductor are arranged in a first isolation circuit, the first isolation circuit is arranged in a first chip, and the inductor circuit is arranged in a second semiconductor chip.

10. 8. The isolation circuit device according to claim 7, wherein the first capacitor, the second capacitor, the first inductor, the second inductor, and the inductor circuit are arranged together in a single semiconductor chip, and the single semiconductor chip is a silicon-on-insulator chip.

11. a signal source that generates one or more control signals; 1. A gate driver apparatus comprising: an isolation barrier receiving the one or more control signals, the isolation barrier having an isolation circuit, the isolation circuit comprising: a first capacitor disposed along the first input line; a second capacitor disposed along a second input line in an electrically parallel manner to the first capacitor; a first inductor having a first end coupled to the first capacitor and a second end coupled to the second capacitor; a center tap connected to the first inductor; and a second inductor inductively coupled to the first inductor and disposed on the high voltage side of the gate driver device with a first output end and a second output end; Including, Gate driver device.

12. a demodulator disposed on the high voltage side; and a gate driver coupled to the demodulator and configured to output a gate drive signal to a high-side switch; The gate driver apparatus of claim 11 further comprising:

13. The insulating barrier is a third inductor having a first end coupled to the first capacitor and a second end coupled to the second capacitor; a center tap connected to the third inductor; and a fourth inductor inductively coupled to the third inductor and disposed on the low voltage side of the gate driver device with a first input end and a second input end; 13. The gate driver device according to claim 11 or 12, further comprising:

14. 14. The gate driver device of claim 13, wherein the third inductor, the fourth inductor, the first capacitor, and the second capacitor are located within a first semiconductor chip, and the first inductor and the second inductor are located within a second semiconductor chip.

15. 14. The gate driver apparatus of claim 13, wherein the first capacitor, the second capacitor, the first inductor, and the second inductor are disposed in a first isolation circuit, the first isolation circuit is disposed in a first chip, and the third inductor and the fourth inductor are disposed in a second semiconductor chip.

16. The gate driver apparatus of claim 13 , wherein the isolation barrier is disposed within a single semiconductor chip.

17. The first capacitor, the second capacitor, the first inductor, and the second inductor are disposed within a first isolation circuit, and a second isolation circuit is disposed within the isolation barrier, the second isolation circuit comprising: a third capacitor connected to the first capacitor; a fourth capacitor connected to the second capacitor; a third inductor having a first end coupled to the third capacitor and a second end coupled to the fourth capacitor; and a fourth inductor inductively coupled to the third inductor and disposed on the low voltage side of the gate driver device with a first input end and a second input end; 13. The gate driver device according to claim 11 or 12, comprising:

18. 18. The gate driver apparatus of claim 17, wherein the first isolation circuit is located in a first semiconductor chip, the second isolation circuit is located in a second semiconductor chip, and the first isolation circuit is connected to the second isolation circuit via a pair of bond wires.

19. 20. The gate driver apparatus of claim 18, wherein the first semiconductor chip further includes a transmitter, and the second semiconductor chip further includes a demodulator and a gate driver.

20. 1. A gate driver apparatus comprising: a signal source that generates one or more control signals; an isolation barrier receiving the one or more control signals, the isolation barrier having an isolation circuit, wherein the isolation circuit comprises: a first capacitor disposed along the first input line; a second capacitor disposed along a second input line in an electrically parallel manner to the first capacitor; a first inductor having a first end coupled to the first capacitor and a second end coupled to the second capacitor; a grounded center tap connected to the first inductor; and a second inductor inductively coupled to the first inductor and disposed on the high voltage side of the gate driver device with a first output end and a second output end; Includes; a demodulator coupled to the second inductor; and a gate driver coupled to the demodulator and configured to output a drive signal to a gate of the power switch; A gate driver device comprising:

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