Equivalence verification apparatus, equivalence verification method, and equivalence verification program

Abstract

To efficiently perform equivalence verification between an arithmetic operation circuit including a combinational logic circuit and a sequential circuit and a design specification.SOLUTION: An equivalence verification apparatus 10 generates, for each output bit, a Boolean polynomial corresponding to each bit output when an arithmetic operation circuit in a netlist is operated based on a timing chart of specification description. Then, the equivalence verification apparatus 10 generates a Boolean polynomial corresponding to each bit of primary output based on the specification description by using a Boolean polynomial ring of the Boolean polynomial calculated based on the netlist. Thereafter, the equivalence verification apparatus 10 calculates difference between the Boolean polynomial calculated based on the netlist and the Boolean polynomial calculated based on the specification description, and determines that the designed netlist satisfies the specification description when the difference is 0 for all bits.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to an equivalence checking device, an equivalence checking method, and an equivalence checking program that can efficiently check the equivalence between an arithmetic operation circuit including a combinational logic circuit and a sequential circuit and a design specification. [Background technology]

[0002] Conventionally, it is important to verify whether a circuit including arithmetic operations such as multiplication over a Galois field (hereinafter referred to as an "arithmetic operation circuit") conforms to predetermined design specifications. For this reason, a technique for verifying the equivalence between a circuit including arithmetic operations and the design specifications is known.

[0003] For example, Non-Patent Document 1 describes the formal verification of integer arithmetic units closed with finite digits in the Galois field GF(2 m ) and is capable of verifying up to m=163. Non-Patent Document 2 discloses a technique that applies a zero-suppressed binary decision diagram (ZDD) to efficiently store Boolean polynomials in a computer and efficiently calculate their operations, and m For b-SMPO (Sequential Multiplier with Parallel Output)_I and AG-SMPO, which are implementations of multipliers on the SMPO, technology has been disclosed that can be verified up to m=410. Non-Patent Document 3 discloses a technology that improves the verification algorithm using ZDD to further significantly reduce the verification time. [Prior art documents] [Patent documents]

[0004] [Non-Patent Document 1] J. Lv, P. Kalla and F. Enescu, “Efficient Grobner Basis Reductions for Formal Verification of Galois Field Arithmetic Circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.32, no.9, Sept. 2013. [Non-patent document 2] U. Gupta, P. Kalla and V. Rao, “Boolean Groner Basis Reductions on Finite Field Datapath Circuits Using the Unate Cube Set Algebra,” IEEE Transactions of Computer-Adid Design of Integrated Circuits and Systems, vol. 38, no.3, March 2019. [Non-patent document 3] A. Ito, R. Ueno and N. Homma, “Efficient Formal Verification of Galois-Field Arithmetic Circuits Using ZDD Representation of Boolean Polynomials,” IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, vol 41, no.3, March 2022. Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the above-mentioned Non-Patent Documents 1 to 3, when verifying the equivalence between an arithmetic operation circuit and a design specification, the equivalence is verified for a data path consisting only of combinational logic circuits that form the arithmetic operation circuit, but the sequential circuits around the data path that control the arithmetic operation circuit are not included in the equivalence verification. As a result, there is a problem in that it is not possible to verify the equivalence between an arithmetic operation circuit that includes combinational logic circuits and sequential circuits and a design specification.

[0006] The present invention has been made to solve the problems (issues) associated with the above-mentioned conventional technology, and aims to provide an equivalence checking device, an equivalence checking method, and an equivalence checking program that can efficiently verify the equivalence between an arithmetic operation circuit, including a combinational logic circuit and a sequential circuit, and a design specification. [Means for solving the problem]

[0007] In order to solve the above-mentioned problems and achieve the object, the present invention provides an equivalence verification device that verifies the equivalence between a netlist of an arithmetic operation circuit including a combinational logic circuit and a sequential circuit and a specification description of a design specification using computer algebra, and is characterized by comprising: first generation means that generates a first Boolean polynomial based on the netlist and a timing chart included in the specification description; second generation means that generates a second Boolean polynomial based on a logic function included in the specification description; calculation means that calculates the difference between the first Boolean polynomial generated by the first generation means and the second Boolean polynomial generated by the second generation means; and determination means that determine the equivalence between the netlist and the specification description based on the difference calculated by the calculation means.

[0008] Furthermore, in the present invention, the first generation means, when the arithmetic operation circuit indicated by the netlist is operated based on the timing chart, generates a first Boolean polynomial having a plurality of inputs to the arithmetic operation circuit and a plurality of outputs from the sequential circuit in the arithmetic operation circuit as variables.

[0009] Furthermore, in the present invention, the first generating means generates a first Boolean polynomial using, as variables, a plurality of inputs to the arithmetic operation circuit immediately before a rising edge of a clock in the timing chart and a plurality of outputs from the sequential circuit in the arithmetic operation circuit immediately before the rising edge.

[0010] Furthermore, in the above invention, the present invention is characterized in that the determining means determines that the netlist and the specification description are equivalent when the difference calculated by the calculating means is 0.

[0011] Furthermore, in the above invention, the present invention is characterized in that the determination means determines that an error dependent on an internal initial state of the arithmetic operation circuit or the inclusion of an incorrect circuit exists when the difference calculated by the calculation means includes variables corresponding to a plurality of outputs from the sequential circuit.

[0012] Furthermore, in the above invention, the determining means determines that an error that depends only on the input of the arithmetic operation circuit or the inclusion of an incorrect circuit exists when the difference calculated by the calculating means includes a Boolean polynomial that is not zero.

[0013] The present invention also provides an equivalence checking method for an equivalence checking device that verifies the equivalence between a netlist of an arithmetic operation circuit including a combinational logic circuit and a sequential circuit and a specification description of a design specification using computer algebra, the method comprising: a first generation step of generating a first Boolean polynomial based on the netlist and a timing chart included in the specification description; a second generation step of generating a second Boolean polynomial based on a logic function included in the specification description; a calculation step of calculating the difference between the first Boolean polynomial generated by the first generation step and the second Boolean polynomial generated by the second generation step; and a determination step of determining the equivalence between the netlist and the specification description based on the difference calculated by the calculation step.

[0014] The present invention also provides an equivalence checking program executed by an equivalence checking device that verifies the equivalence between a netlist of an arithmetic operation circuit including a combinational logic circuit and a sequential circuit and a specification description of a design specification using computer algebra, the program causing a computer to execute the following steps: a first generation procedure for generating a first Boolean polynomial based on the netlist and a timing chart included in the specification description; a second generation procedure for generating a second Boolean polynomial based on a logic function included in the specification description; a calculation procedure for calculating the difference between the first Boolean polynomial generated by the first generation procedure and the second Boolean polynomial generated by the second generation procedure; and a determination procedure for determining the equivalence between the netlist and the specification description based on the difference calculated by the calculation procedure. [Effects of the Invention]

[0015] According to the present invention, it is possible to efficiently verify the equivalence between an arithmetic operation circuit including a combinational logic circuit and a sequential circuit and a design specification. [Brief explanation of the drawings]

[0016] [Figure 1] FIG. 1 is a diagram showing an overview of an equivalence checking device according to an embodiment. [Figure 2] FIG. 2 is a functional block diagram showing the configuration of the equivalence checking device shown in FIG. [Figure 3] FIG. 3 is a timing chart in the specification description of a Galois field multiplier. [Figure 4] FIG. 4 is a diagram showing a logic function in a specification description of a Galois field multiplier. [Figure 5] FIG. 5 is a block diagram showing the configuration of a Galois field multiplier. [Figure 6] FIG. 6 is a netlist diagram of a Galois field multiplier. [Figure 7] FIG. 7 is a conversion table for converting a logic circuit into a Boolean polynomial. [Figure 8] FIG. 8 is a flowchart showing the processing procedure of the equivalence verifying apparatus shown in FIG. [Figure 9] FIG. 9 is a flowchart showing the processing procedure for generating Boolean polynomials for a netlist. [Figure 10] FIG. 10 is a diagram illustrating an example of a hardware configuration. DETAILED DESCRIPTION OF THE INVENTION

[0017] Hereinafter, an equivalence checking apparatus, an equivalence checking method, and an equivalence checking program according to the present invention will be described in detail with reference to the accompanying drawings. Here, the circuit description will be described as a gate-level design description, that is, a netlist.

[0018] <Outline of the equivalence verification device 10> An outline of an equivalence checking device 10 according to this embodiment will be described below. Fig. 1 is an explanatory diagram for explaining an outline of an equivalence checking device 10 according to this embodiment.

[0019] Generally, to verify the equivalence between a specification description and a circuit description in hardware design, it is necessary to verify that when an arithmetic circuit in a netlist is operated according to the specification description, the primary output always matches the specification description for the value of the primary input. However, as the circuit scale increases, this type of equivalence verification has the problem that the calculation time becomes enormous and the equivalence verification cannot be completed within the specified time.

[0020] Therefore, by using a computer algebra system and Boolean polynomials obtained from the netlist for equivalence verification, we were able to verify the equivalence between the netlist and the specification description, and by also considering sequential circuits as the subject of verification, we were able to verify the existence of errors and malicious modifications including those in sequential circuits.

[0021] 1, an equivalence checking device 10 according to the present invention generates a Boolean polynomial corresponding to each bit of the primary output based on a netlist. Specifically, when an arithmetic operation circuit in the netlist is operated based on the timing chart of the specification description, a Boolean polynomial is generated for each bit of the primary output, which corresponds one-to-one to a logic function whose inputs are the primary input values ​​immediately before the rising edges of multiple operating clocks that determine the values ​​of each bit of the primary output and the initial output values ​​of all D flip-flops in the netlist.

[0022] Here, in the case where the netlist is an arithmetic operation circuit composed only of logic gates, by using a conversion table of Boolean polynomials that correspond one-to-one to the logic functions of basic logic gates, the Boolean polynomial corresponding to each bit of the primary output can be obtained as a composition of Boolean polynomials corresponding to all logic gates.

[0023] Next, the equivalence checking device 10 generates a Boolean polynomial corresponding to each bit of the primary output based on the specification description. Specifically, the equivalence checking device 10 generates a Boolean polynomial corresponding to each bit of the primary output based on the specification description using the Boolean polynomial ring of the Boolean polynomial generated based on the netlist.

[0024] The equivalence checking device 10 then determines the equivalence of the two Boolean polynomials. Specifically, it calculates the difference between the Boolean polynomial generated based on the netlist and the Boolean polynomial generated based on the specification description, and if the difference is 0 for all bits, it determines that the designed netlist satisfies the specification description.

[0025] <Configuration of the equivalence verification device 10> Next, the configuration of the equivalence verification device 10 shown in Fig. 1 will be described. Note that the case of a 3-bit Galois field multiplier will be described here. Fig. 2 is a functional block diagram showing the configuration of the equivalence verification device 10 shown in Fig. 1. As shown in Fig. 2, the equivalence verification device 10 has a display unit 11, an input unit 12, a memory unit 14, and a control unit 15. The display unit 11 is a display device such as a liquid crystal display that displays various information. The input unit 12 is an input device such as a mouse or keyboard.

[0026] The memory unit 14 is a storage device such as a hard disk drive or nonvolatile memory, and stores specification description data 14a, netlist data 14b, Boolean polynomial conversion data 14c, netlist Boolean polynomial data 14d, specification description Boolean polynomial data 14e, and judgment result data 14f.

[0027] The specification description data 14a includes data such as timing charts, logic functions corresponding to each primary output, and I / O port descriptions. The logic functions may be logical expressions, polynomials, or relational expressions that can uniquely determine the logic functions. As shown in Figure 3, the timing chart describes signal changes over time, such as the number of clock cycles, the clock signal CLK, the reset signal RSTn, the input signal Ain of the first input port, the input signal Bin of the second input port, and the output signal Dout of the output port.

[0028] As shown in Figure 4, the I / O description is data such as the port name, input / output, bit width, and description. Here, for the port name "Ain", the input / output is "in", the bit width is "3", and the description is "multiplication input. The multiplicand A is in the Galois field GF(2 3 ), where A=Ain0[0]β+Ain0[1]β 2 +Ain0[2]β 4 The port name "Bin" corresponds to the input / output "in", the bit width "3", and the description "Multiplication input. The multiplicand B is in the Galois field GF(2 3 ), where B=Bin0[0]β+Bin0[1]β2 +Bin0[2]β 4 holds true. " is associated with

[0029] Also, for the port name "Dout", input / output "out", bit width "3", description "Multiplication output. The multiplication result D = AB is in the Galois field GF(2 3 ), where D=Dout4[0]β+Dout4[1]β 2 +Dout4[2]β 4 is true." is associated with the port name "CLK," and the input / output "in," bit width "1," and description "System clock. All flip-flops operate synchronously at the rising edge of this signal." is associated with the port name "RSTn," and the input / output "in," bit width "1," and description "Reset signal. When RSTn=0 and on the rising edge of CLK, the multiplied input value is taken in from Ain and Bin." is associated with the port name "RSTn."

[0030] The netlist data 14b is gate-level design description data of an arithmetic operation circuit designed based on the specification description. For example, when the designed arithmetic operation circuit is a 3-bit b-SMPO_I, the block diagram BLK has two input shift registers (SR1, SR2), one output shift register (SR3), and an arithmetic circuit CAL, as shown in Figure 5. Note that the reset signal RSTn and the clock signal CLK are omitted here for simplicity of explanation.

[0031] The input signal Ain and the input signal Bin are signal lines with a 3-bit width. Also, the output signal Dout is a signal line with a 3-bit width. When the reset signal RSTn is 0, the shift register SR1 reads the value of the input signal Ain into the shift register SR1. When the reset signal RSTn is other than 0, at the rising timing of the clock signal CLK, the value input in the direction of the arrow is cyclically shifted by one. Similarly to the shift register SR1, when the reset signal RSTn is 0, the shift register SR2 reads the value of the input signal Bin into the shift register SR2. When the reset signal RSTn is other than 0, at the rising timing of the clock signal CLK, the value input in the direction of the arrow is cyclically shifted by one.

[0032] The shift register SR3 cyclically shifts the captured value in the direction of the arrow while capturing the intermediate data of the multiplication from the arithmetic circuit CAL described later. When the reset signal RSTn is 0, the values of d0, d1, and d2 of the shift register SR3 are reset to 0. When the reset signal RSTn is other than 0, at the rising timing of the clock signal CLK, the intermediate value of the multiplication is cyclically shifted by one in the direction of the arrow. In the case of this example, after the reset signal RSTn becomes 1, when the clock signal CLK reaches the third cycle, the multiplication result is held in d0, d1, and d2 of the shift register SR3. The arithmetic circuit CAL is a circuit that performs a multiplication calculation composed of AND gates and XOR gates.

[0033] As shown in FIG. 6, the netlist of the block diagram in FIG. 5 has a 3-bit input signal Ain and a 3-bit input signal Bin, and the result of multiplying Ain and Bin is output as a 3-bit output signal to Dout. Each signal line of the netlist is labeled with w1 to w 32 up to, but this label, after performing the topological sort described later, in the subsequent order, if w i appears before w j , the label is assigned so that i < j.

[0034] The Boolean polynomial conversion data 14c is data that is referenced when converting logic gates in a netlist into Boolean polynomials when generating Boolean polynomials based on a netlist, which will be described later. For example, as shown in Fig. 7, the Boolean polynomial conversion data 14c is data in which Boolean polynomials are associated with gate names.

[0035] Here, a Boolean polynomial is associated with each of the gate names "AND(a, b, y)", "OR(a, b, y)", "NOT(a, y)", "XOR(a, b, y)", and "MUX(a, b, s, y)".

[0036] The netlist Boolean polynomial data 14d is data of a Boolean polynomial generated based on the netlist data 14b. The specification description Boolean polynomial data 14e is data of a Boolean polynomial generated based on the specification description. The judgment result data 14f is data of the result of a judgment made by comparing the Boolean polynomial generated based on the netlist with the Boolean polynomial generated based on the specification description.

[0037] Control unit 15 is a control unit that performs overall control of equivalence checking device 10, and includes initial parameter setting unit 15a, netlist Boolean polynomial generation unit 15b, specification description Boolean polynomial generation unit 15c, difference calculation unit 15d, and judgment unit 15e. In practice, by loading these programs into a CPU and executing them, the initial parameter setting unit 15a, netlist Boolean polynomial generation unit 15b, specification description Boolean polynomial generation unit 15c, difference calculation unit 15d, and judgment unit 15e execute their respective corresponding processes.

[0038] The initial parameter setting unit 15a is a processing unit that performs a process of topologically sorting logic gates in a netlist based on input / output dependency relationships, and a process of assigning variables to primary inputs and outputs of D flip-flops in the netlist. Specifically, a directed acyclic graph G=(V, E) is a graph in which the vertex set V is the set of all signal lines in the netlist, the edge set E is the set of all signal lines in the netlist, and the iFrom w j An edge to exists if there exists a logic gate i is the input, and w j is its output if and only if. Then, a topological sort is performed on this graph G. Since every signal line except for the primary inputs is the output of only one element, the input-output dependencies can be found by sorting all logic gates in the netlist in the order in which their output signal lines appear.

[0039] Furthermore, the initial parameter setting unit 15a assigns variables to the primary inputs and outputs of the D flip-flops in the netlist. For example, in the case of the netlist shown in Fig. 6, variables (a0, a1, a2) are assigned to the input signal Ain, variables (b0, b1, b2) are assigned to the input signal Bin, and variables (q0, ..., q8) are assigned to the outputs of all the D flip-flops present in the netlist.

[0040] The netlist Boolean polynomial generation unit 15b is a processing unit that generates Boolean polynomials with variables being multiple inputs to the arithmetic operation circuit and multiple outputs from the sequential circuit in the arithmetic operation circuit when the arithmetic operation circuit in the netlist is operated based on the timing chart of the specification description. Specifically, it generates Boolean polynomials for each bit of the output signal Dout of the arithmetic operation circuit, which correspond one-to-one to logic functions with input values ​​immediately before the rising edges of multiple clocks that determine the value of each bit in the output signal Dout of the arithmetic operation circuit and initial values ​​of all D flip-flops immediately before the rising edge of CLK1. Here, the Boolean polynomials are generated for each bit of the output signal Dout of the arithmetic operation circuit in GF(2 3 ) will be explained as an example. Regarding the description of the logic function, the value of the i-th bit for an arbitrary output signal D is D[i], CLK j+1 The value of the output signal D just before the rising edge is D j This will be expressed as follows.

[0041] The netlist Boolean polynomial generator 15b generates a Boolean polynomial ring by assigning the variables assigned by the initial parameter setting unit 15a to all primary inputs except CLK and RSTn and the initial outputs of all D flip-flops. Here, the Boolean polynomial ring of the netlist shown in FIG. 6 is BP(a0, a1, a2, b0, b1, b2, q0, ..., q8). First, the netlist Boolean polynomial generator 15b generates Boolean polynomials corresponding to all signal lines immediately before the rising edge of CLK1 in accordance with the timing chart by converting the logic gates in the netlist with reference to the Boolean polynomial conversion data 14c. Then, the netlist Boolean polynomial generator 15b calculates the operation of the D flip-flops. This calculation sets the input Boolean polynomials of all D flip-flops to the output Boolean polynomials of those D flip-flops.

[0042] Thereafter, netlist Boolean polynomial generator 15b replaces the Boolean polynomial of the primary input with the one immediately before the rising edge of CLK2. This simply involves converting the Boolean polynomial corresponding to RSTn from the timing chart to 1. Netlist Boolean polynomial generator 15b then generates Boolean polynomials corresponding to all signal lines immediately before the rising edge of CLK2 by converting the logic gates in the netlist with reference to Boolean polynomial conversion data 14c.

[0043] The netlist Boolean polynomial generator 15b calculates the operation of the D flip-flop and the CLK j By repeating the process of converting the Boolean polynomials corresponding to all signal lines immediately before the rising edge of CLK1 to CLK4 by referring to the Boolean polynomial conversion data 14c, the logic gates in the netlist are converted. j It is possible to generate a Boolean polynomial corresponding to a logic function that determines the value of the output signal Dout4 of an arithmetic operation circuit that receives as input the primary input immediately before the rising edge of CLK1 and the outputs of all D flip-flops immediately before the rising edge of CLK2.

[0044] The specification description Boolean polynomial generation unit 15c is a processing unit that generates a Boolean polynomial based on a logic function included in the specification description. Specifically, the Boolean polynomial corresponding to the output signal Dout4 of the arithmetic operation circuit is generated by using the Boolean polynomial ring defined by the netlist Boolean polynomial generation unit 15b in the specification description of FIG.

[0045] For example, a i , b j Let Ain0[i] and Bin0[j] be the values ​​of Ain0[i] and Bin0[j]. In this case, A and B∈GF(2 3 ) is A=a0β+a1β 2 +a2β 4 , B=b0β+b1β 2 +b2β 4 Then, D=AB∈GF(2 3 ), D=d0β+d1β 2 +d2β 4 d0, d1, d2∈GF(2) can be uniquely calculated, and a Boolean polynomial corresponding to the output signal Dout4 of the arithmetic operation circuit can be generated.

[0046] The difference calculation unit 15d is a processing unit that calculates the difference between the netlist Boolean polynomial generated by the netlist Boolean polynomial generation unit 15b and the specification description Boolean polynomial generated by the specification description Boolean polynomial generation unit 15c.

[0047] The determination unit 15e is a determination unit that determines equivalence based on the difference calculated by the difference calculation unit 15d. Specifically, if the difference between the output signals Dout4[i] of the arithmetic operation circuit is 0 for all i, it determines that the arithmetic operation circuit in the netlist and the specification description are equivalent. Furthermore, if the difference includes a variable for the initial output of the D flip-flop of the arithmetic operation circuit, it determines that an error dependent on the initial state in the circuit or an incorrect circuit has been introduced. Furthermore, if the difference includes a Boolean polynomial that is not 0, it determines that an error dependent only on the input in the circuit or an incorrect circuit has been introduced.

[0048] <Principle of Equivalence Verification> Next, the principle of equivalence verification according to the present invention will be explained. Here, the circuit design description of the Galois field multiplier is as shown in FIG. 6, and the specification description is as shown in FIG. 3 and FIG. 4. Here, β is a function of GF(2 3 ) and elements of GF(2 3 )=GF(2)(α) and α is an irreducible polynomial x 3 +x+1, then β=α 3 This β is assumed to satisfy {β, β 2 , β 4} in GF(2 3 ) form a normal basis for

[0049] From the given specification description, it can be seen that the value of each bit of the output signal Dout4 of the arithmetic operation circuit is uniquely determined for the values ​​of Ain0 and Bin0. 3 ) are normalized to the normal basis {β, β 2 , β 4}, the logical function φ i :GF(2) 6 →Dout4[i]=φ in GF(2) i It can be seen that (Ain0, Bin0) exist. On the other hand, let Dout4 (netlist) be the value of Dout just before the rising edge of CLK5 when the arithmetic operation circuit in the netlist is operated as specified in the timing chart. The equivalence verification problem between the netlist and the specification description is that when the arithmetic operation circuit in the netlist is operated according to the specification description, the value of the primary output for the value of the primary input is always as described in the specification description. In other words, the equivalence verification problem between the netlist in Figure 6 and the specification descriptions in Figures 3 and 4 is that for any Ain0, Bin0, Dout4 (netlist)[i]=φ i (Ain0, Bin0) is true.

[0050] Generalizing the above example, the netlist has one RSTn as a primary input port, m Din[1], ..., Din[m] as primary output ports, n Dout[1], ..., Dout[n] as primary output ports, and s D flip-flop outputs Q[1], ..., Q[s]. jThe value of Q0 is the initial output value of the D flip-flop just before the rising edge of CLK1, and the value of Q1 is the value of Q2. j+1 The value of Din just before each rising edge: Din0, ..., Din j In other words, we only consider netlists of arithmetic operation circuits where the output value is always unique for the initial state and input sequence of the arithmetic operation circuit. k+1 The logic function φ just before the rising edge of i DeDout k [i]=φ i (Din0, ..., Din k , Q0). Then, the equivalence verification problem is solved for any Q0, Din0, ..., Din k For the value of Dout k (Netlist)=φ i (Din0, ..., Din k , Q0) holds.

[0051] The equivalence verification problem defined above is the Dout when the arithmetic operation circuit in the netlist is operated according to the specification description. k (Netlist)[i] also has a logic function φ imp In Dout k (netlist)[i]=φ imp (Din0, ..., Din k , Q0). Therefore, the equivalence problem can be solved by two logic functions φ, ψ:GF(2) n →For any a1, ..., a in GF(2), n For ∈GF(2), φ(a1, ..., a n )=ψ(a1, ..., a n ) is true. To determine whether they are equivalent, n There are a1, ..., a n For all combinations of φ(a1, ..., a n )=ψ(a1, ..., a n) However, since the number of combinations to be checked grows exponentially with n, it is difficult to check all combinations within the required time. Therefore, to overcome this problem, we consider replacing logical functions.

[0052] GF(2) coefficient n-variable polynomial ring GF(2) [x1, ..., x n ] that ideal <x1 2 +x1, …, x n 2 +x n > the surplus ring GF(2) [x1, ..., x n ] / <x1 2 +x1, …, x n 2 +x n > is called the Boolean polynomial ring, BP(x1, ..., x n ) is the Boolean polynomial ring BP(x1, ..., x n ) is x with coefficients in GF(2)={0, 1} j …x k The set of all polynomials that can be expressed as a sum of monomials of the form, addition is the sum of polynomials, and multiplication is the multiplication of polynomials and then the power of each variable x i j When j=0, it is 1, and when j>0, it is x i For example, when f=x1x2+x3 and g=x3+x4, f+g and fg are shown in Equation 1 and Equation 2.

[0053]

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[0054]

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[0055] Note that in GF(2), 1+1=0, i.e., f ∈BP(x1, ..., x n ) f + f = 0. The necessary condition for replacing a logic function with a Boolean polynomial is that for any n-argument logic function φ:GF(2) n→For GF(2), there is a class f ∈BP(x1, ..., x n ) exists uniquely and for any a1, ..., a n For ∈GF(2), φ(a1, ..., a n )=f(a1, …, a n ) holds true.

[0056] The above condition is satisfied by f∈BP(x1, ..., x n ) is proved by induction on n. Now, let n = 1. Then there are only two types of one-argument logic functions φ:GF(2) → GF(2): one where ψ0 holds for ψ0, so ψ0(0) = 0 and ψ0(1) = 1, and the other where ψ1(0) = 1 and ψ1(1) = 0 for ψ1. If f0 = x1∈BP(x1) for ψ0, then ψ0(0) = 0 = f0(0) and ψ0(1) = 1 = f0(1). For any a1∈GF(2) excluding this f0, there is no f∈BP(x1) such that ψ0(a1) = f(a1).

[0057] Similarly, for ψ1, if f1=1+x1∈BP(x1), then ψ1(0)=1=1+0=f1(0), ψ1(1)=0=1+1=f1(1), and there are no others except for f1. From the above, we can see that this holds true when n=1.

[0058] Next, let n>1, and assume that existence can be shown for n or less. Fix an n-argument logic function φ. Let ψ0 and ψ1 be n-1 argument logic functions, and let a1, ..., a n-1 ∈GF(2), ψ0(a1, ..., a n-1 )=φ(a1, ..., a n-1 , 0), ψ1(a1, ..., a n-1 )=φ(a1, ..., a n-1 , 1) holds. Then, by induction hypothesis, g0, g1∈BP(x1, ..., x n-1 ) such that for any a1, ..., a n-1 ∈GF(2), ψ0(a1, ..., a n-1 )=g0(a1, …, a n-1 ), ψ1(a1, ..., a n-1 )=g1(a1, …, a n-1) holds, where g∈BP(x1, ..., x n ) to g=(1+x n )g0+x n If we choose g1 as g, then for any a1, ..., a n-1 Equations 3 and 4 hold for ∈GF(2).

[0059]

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[0060]

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[0061] From the above, any a1, ..., a n ∈GF(2), φ(a1, ..., a n )=g(a1, …, a n ) such that g∈BP(x1,...,x n ) was shown to exist.

[0062] Next, f∈BP(x1,...,x n ) is unique using induction on n. Now, let n=1. For f, g∈BP(x1), let f≠g. If h=fg, then h≠0∈BP(x1), so h is either 1, x1, or 1+x1. When h=1, h(a1)≠0 regardless of the value of a1∈GF(2). When h=x1, by setting a1=1, we get h(a1)=1≠0. When h=1+x1, by setting a1=0, we get h(a1)=1+0=1≠0.

[0063] From the above, there exists a certain a1∈GF(2) such that f(a1)≠g(a1), so the case of n=1 has been proved. Suppose n>1 and uniqueness can be proved for n less than n. f, g∈BP(x1, ..., x n ), let f ≠ g. For f, f0, f1∈BP(x1, ..., x n-1 ) exists and f=f0+x n Similarly, g can be expressed as g0, g1∈BP(x1, ..., x n-1) exists such that g=g0+x n Since f≠g, either f0≠g0 or f1≠g1. If f0≠g0, then by induction hypothesis, there are a1, ..., a n-1 ∈GF(2) such that f0(a1, ..., a n-1 ) ≠ g0(a1, …, a n-1 ) This a1, ..., a n-1 Taking this, Equation 5 holds.

[0064]

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[0065] On the other hand, the same can be said when f1 ≠ g1. By induction hypothesis, if there are b1, ..., b n-1 ∈GF(2) such that f1(b1, ..., b n-1 )≠g1(b1, …, b n-1 ) holds. This b1, ..., b n-1 If f0(b1, ..., b n-1 ) ≠ g0(b1, …, b n-1 ) then Equation 6 holds.

number

[0066] Also, f0(b1, ..., b n-1 )=g0(b1, …, b n-1 ) then Equation 7 holds.

[0067]

number

[0068] From the above, for n-argument Boolean function φ, f∈BP(x1, ..., x n ) exists uniquely such that for any a1, ..., a n ∈GF(2), φ(a1, ..., a n )=f(a1, …, a n ) was shown to hold.

[0069] It can also be seen that the Boolean polynomial corresponding to each bit in the primary output of an arithmetic circuit in the netlist is obtained as a composition of the Boolean polynomials corresponding to the logic gates in the arithmetic circuit.

[0070] <Processing Procedure of Equivalence Verification Device 10> Next, a processing procedure of the equivalence checking device 10 will be described. Fig. 8 is a flowchart showing the processing procedure of the equivalence checking device 10 shown in Fig. 2. As shown in Fig. 8, the equivalence checking device 10 topologically sorts all logic gates based on the netlist (step S101). Then, the equivalence checking device 10 assigns variables to the primary inputs and outputs of D flip-flops in the netlist (step S102).

[0071] Thereafter, the equivalence checking device 10 performs a netlist Boolean polynomial generation process based on the netlist (step S103). The equivalence checking device 10 also generates Boolean polynomials based on the specification description (step S104). Then, the equivalence checking device 10 calculates the difference between the two Boolean polynomials (step S105).

[0072] Then, the equivalence checking device 10 determines whether the difference between the two Boolean polynomials includes a variable for the initial output of the D flip-flop (step S106). If the difference includes a variable in the initial output of the D flip-flop (step S106: Yes), the equivalence checking device 10 determines that an error dependent on the initial state in the circuit or the inclusion of a faulty circuit exists (step S107).

[0073] On the other hand, if the difference does not include a variable for the initial output of the D flip-flop (step S106: No), the equivalence checking device 10 determines whether the difference between the two Boolean polynomials includes a non-zero Boolean polynomial (step S108).If the difference between the two Boolean polynomials includes a non-zero Boolean polynomial (step S108: Yes), the equivalence checking device 10 determines that an error that depends only on the input within the circuit or the inclusion of a faulty circuit exists (step S109).

[0074] On the other hand, if the difference between the two Boolean polynomials does not include a Boolean polynomial that is not 0 (step S108: No), the equivalence verifying device 10 determines that the netlist and the specification description are equivalent (step S110), and ends the process.

[0075] <Processing procedure for generating Boolean polynomials from a netlist> Next, the processing procedure for generating a Boolean polynomial for a netlist will be described. Fig. 9 is a flowchart showing the processing procedure for generating a Boolean polynomial for a netlist. As shown in Fig. 9, the equivalence checking device 10 initializes Boolean polynomials corresponding to the primary inputs and the outputs of the D flip-flops (step S201). Then, the equivalence checking device 10 generates Boolean polynomials for the output signal lines of all logic gates (step S202).

[0076] Thereafter, the equivalence checking device 10 sets a counter value j for clock counter to 0 (step S203) and determines whether the counter value j is smaller than a predetermined counter value k (step S204). If the counter value j is smaller than k (step S204: Yes), the equivalence checking device 10 calculates the operation of the D flip-flop (step S205). Then, the equivalence checking device 10 initializes the Boolean polynomials of the primary inputs (step S206) and generates Boolean polynomials for the output signal lines of all logic gates (step S207).

[0077] Then, the equivalence verifying device 10 sets the counter value j of the clock counter to j+1 (step S208) and proceeds to step S204. On the other hand, if the counter value j of the clock counter is not smaller than the predetermined counter value k (step S204: No), the equivalence verifying device 10 proceeds to S105 of the main flow in FIG.

[0078] <Example of equivalence verification> Next, GF(2 3An example of equivalence checking for a Galois field multiplier on a netlist will be described below. The equivalence checking device 10 first sets input / output dependencies for all logic gates in the netlist using topological sorting. Then, the equivalence checking device 10 assigns variables to primary inputs in the netlist whose possible values ​​in GF(2)={0, 1} are unclear from the specification description. Here, a0, a1, a2, b0, b1, and b2 are assigned to Ain[0], Ain[1], Ain[2], Bin[0], Bin[1], and Bin[2], respectively.

[0079] Similarly, we assign variables to the output of each D flip-flop. Here, we assign variables to signal lines w7, w8, w9, and w 11 , w 12 , w 13 ,w 14 ,w 15 , w 16 Finally, we assign the variables q0, ..., q8 to the Boolean polynomial ring BP(a0, a1, a2, b0, b1, b 2、 q0, ..., q8) are defined. Then, the equivalence checking device 10 initializes Boolean polynomials corresponding to the primary inputs and the D flip-flop outputs.

[0080] Then, the equivalence checking device 10 initializes the Boolean polynomials corresponding to the primary inputs and the D flip-flop outputs. The equivalence checking device 10 checks whether each z[i] corresponds to each signal line w iAn array Z is prepared so that the Boolean polynomials corresponding to the above equations are obtained. After initialization, the following equations are obtained: z[0]=0, z[1]=a0, z[2]=a1, z[3]=a2, z[4]=b0, z[5]=b1, z[6]=b2, z[7]=q0, z[8]=q1, z[9]=q2, z

[10] =0, z

[11] =q3, z

[12] =q4, z

[13] =q5, z

[14] =q6, z

[15] =q7, z

[16] =q8. Then, the equivalence checking device 10 generates Boolean polynomials for the output signal lines of all logic gates. The elements of array Z after generating the Boolean polynomial are z[0]=0, z[1]=a0, z[2]=a1, z[3]=a2, z[4]=b0, z[5]=b1, z[6]=b2, z[7]=q0, z[8]=q1, z[9]=q2, z

[10] =0, z

[11] =q3, z

[12] =q4, z

[13] =q5, z

[14] =q6, z

[15] =q7, z

[16] =q8, z

[17] =a1, z

[18] =a2, z

[19] =a0, z

[20] =q3+q5, z

[21] =b1, z

[22] =b2, z

[23] =b0, z

[24] =q5q8, z

[25] =q6+q8, z

[26] =0, z

[27] =(q3+q5)(q6+q8), z[28 ]=q1+(q3+q5)(q6+q8), z

[29] =q5q8+(q3+q5)(q6+q8), z

[30] =0, z

[31] =q2+q5q8+(q3+q5)(q6+q8), z

[32] =0.

[0081] Then, the equivalence checking device 10 initializes the counter value j of the clock counter to j=0 and calculates the operation of the D flip-flops. Calculating the operation of the D flip-flops is a process of setting the input Boolean polynomial of each D flip-flop as the output Boolean polynomial. The outputs of each D flip-flop after calculating the operation of the D flip-flops are z[7]=0, z[8]=0, z[9]=0, z

[11] =a0, z

[12] =a1, z

[13] =a2, z

[14] =b0, z

[15] =b1, and z

[16] =b2. Then, when the equivalence checking device 10 initializes the Boolean polynomials for the primary inputs, z[0] corresponding to RSTn becomes z[0]=1.

[0082] Then, the equivalence checking device 10 generates Boolean polynomials for the output signal lines of all the logic gates. The elements of the array Z after generating the Boolean polynomials are z[0]=1, z[1]=a0, z[2]=a1, z[3]=a2, z[4]=b0, z[5]=b1, z[6]=b2, z[7]=0, z[8]=0, z[9]=0, z

[10] =0, z

[11] =a0, z

[12] =a1, z

[13] =a2, z

[14] =b0, z

[15] =b1, z

[16] =b2, z

[17] =a0, z

[18] =a1, z

[19] =a2, z

[20] =a0+a2, z

[21] =a0+a2, z

[22] =a0+a2, z

[23] =a0+a2, z

[24] =a0+a2, z

[25] =a0+a2, z

[26] =a0+a2, z

[27] =a0+a2, z

[28] =a0+a2, z

[29] =a0+a2, z

[30] =a0+a2, z

[31] =a0+a2, z

[32] =a0+a2, z

[33] =a0+a2, z

[34] =a0+a2, z

[35] =a0+a2, z

[36] =a0+a2, z

[37] =a0+a2, z

[38] =a0+a2, z

[39] =a0+a2, z

[40] =a0+a2, z

[41] =a0+a2, z

[42] =a0+a2, z

[43] =a0+a2, z

[44] =a0+a 1]=b0, z

[22] =b1, z

[23] =b2, z

[24] =a2b2, z

[25] =b0+b2, z

[26] =0, z

[27] =(a0+a2)(b0+b2), z

[28] =(a0+a2)(b0+b2), z[ 29]=a2b2+(a0+a2)(b0+b2), z

[30] =(a0+a2)(b0+b2), z

[31] =a2b2+(a0+a2)(b0+b2), z

[32] =a2b2+(a0+a2)(b0+b2).

[0083] Then, the equivalence verification device 10 sets the counter value j of the clock counter to j=1. Because the counter value j is smaller than the predetermined counter value k=4, the operation of the D flip-flop is calculated. Note that the Galois field multiplier over GF(23) initializes the clock counter and outputs the multiplication result at the fourth clock, so the predetermined counter value k is set to 4. After calculating the operation of the D flip-flop, the outputs of each D flip-flop are z[7]=a2b2+(a0+a2)(b0+b2), z[8]=0, z[9]=(a0+a2)(b0+b2), z

[11] =a2, z

[12] =a0, z

[13] =a1, z

[14] =b2, z

[15] =b0, and z

[16] =b1. The equivalence verification device 10 then initializes the Boolean polynomial for the primary input, but the value of z does not change.

[0084] Then, the equivalence checking device 10 generates Boolean polynomials for the output signal lines of all the logic gates. Each element of the array Z after generating the Boolean polynomial is z[0]=1, z[1]=a0, z[2]=a1, z[3]=a2, z[4]=b0, z[5]=b1, z[6]=b2, z[7]=a2b2+(a0+a2)(b0+b2), z[8]=0, z[9]=(a0+a2)( b0+b2), z

[10] =0, z

[11] =a2, z

[12] =a0, z

[13] =a1, z

[14] =b2, z

[15] =b0 , z

[16] =b1, z

[17] =a2, z

[18] =a0, z

[19] =a1, z

[20] =a1+a2, z

[21] =b2, z[ 22]=b0, z

[23] =b1, z

[24] =a1b1, z

[25] =b1+b2, z

[26] =a2b2+(a0+a2)(b 0+b2), z

[27] =(a1+a2)(b1+b2), z

[28] =(a1+a2)(b1+b2), z

[29] =a1b1+( a1+a2)(b1+b2), z

[30] =(a1+a2)(b1+b2), z

[31] =a1b1+(a0+a2)(b0+b2) +(a1+a2)(b1+b2), z

[32] =a1b1+(a0+a2)(b0+b2)+(a1+a2)(b1+b2).

[0085] After that, the equivalence checking device 10 sets the counter value j of the clock counter to j=2. Because the counter value j is smaller than the predetermined counter value k=4, the operation of the D flip-flop is calculated. The outputs of each D flip-flop after the operation of the D flip-flop is calculated are z[7]=(a0+a2)(b0+b2)+a1b1+(a1+a2)(b1+b2), z[8]=a2b2+(a0+a2)(b0+b2), z[9]=(a1+a2)(b1+b2), z

[11] =a1, z

[12] =a2, z

[13] =a0, z

[14] =b1, z

[15] =b2, and z

[16] =b0. After that, the equivalence checking device 10 initializes the Boolean polynomial for the primary input, but the value of z does not change.

[0086] Then, the equivalence checking device 10 generates Boolean polynomials for the output signal lines of all the logic gates. The elements of the array Z after generating the Boolean polynomials are z[0]=1, z[1]=a0, z[2]=a1, z[3]=a2, z[4]=b0, z[5]=b1, z[6]=b2, z[7]=a1b1+(a0+a2)(b0+b2)+(a1+a2)(b1+b2), z[8]=a2b2+(a0+a2)(b0+b2), z[ 9]=(a1+a2)(b1+b2), z

[10] =0, z

[11] =a1, z

[12] =a2, z

[13] =a0, z

[14] =b1, z

[15] =b2 , z

[16] =b0, z

[17] =a1, z

[18] =a2, z

[19] =a0, z

[20] =a0+a1, z

[21] =b1, z

[22] =b2, z[23 ]=b0, z

[24] =a0b0, z

[25] =b0+b1, z

[26] =a1b1+(a0+a2)(b0+b2)+(a1+a2)(b1+b2), z

[27] =(a0+a1)(b0+b1), z

[28] =a2b2+(a0+a1)(b0+b1)+(a0+a2)(b0+b2), z

[29] =a0b0 +(a0+a1)(b0+b1), z

[30] =a2b2+(a0+a1)(b0+b1)+(a0+a2)(b0+b2), z

[31] =a0b0+(a0 +a1)(b0+b1)+(a1+a2)(b1+b2), z

[32] =a0b0+(a0+a1)(b0+b1)+(a1+a2)(b1+b2).

[0087] After that, the equivalence verifying device 10 sets the counter value j of the clock counter to j=3. Because the counter value j is smaller than the predetermined counter value k=4, the operation of the D flip-flops is calculated. The outputs of the D flip-flops after the operation of the D flip-flops is calculated are z[7]=(a1+a2)(b1+b2)+a0b0+(a0+a1)(b0+b1), z[8]=(a0+a2)(b0+b2)+a1b1+(a1+a2)(b1+b2), z[9]=a2b2+(a0+a2)(b0+b2)+(a0+a1)(b0+b1), z

[11] =a0, z

[12] =a1, z

[13] =a2, z

[14] =b0, z

[15] =b1, z

[16] =b2. Thereafter, the equivalence checking device 10 initializes the Boolean polynomial for the primary input, but the value of z does not change.

[0088] Then, the equivalence checking device 10 generates Boolean polynomials for the output signal lines of all the logic gates. The elements of the array Z after generating the Boolean polynomials are z[0]=1, z[1]=a0, z[2]=a1, z[3]=a2, z[4]=b0, z[5]=b1, z[6]=b2, z[7]=a0b0+(a0+a1)(b0+b1)+(a1+a2)(b1+b2), z[8]=a1b1+(a 0+a2)(b0+b2)+(a1+a2)(b1+b2), z[9]=a2b2+(a0+a1)(b0+b1)+(a0+a2)(b0 +b2), z

[10] =0, z

[11] =a0, z

[12] =a1, z

[13] =a2, z

[14] =b0, z

[15] =b1, z

[16] =b2, z

[17] =a0, z

[18] =a1, z

[19] =a2, z

[20] =a0+a2, z

[21] =b0, z

[22] =b1, z[ 23]=b2, z

[24] =a2b2, z

[25] =b0+b2, z

[26] =a0b0+(a0+a1)(b0+b1)+(a1+a2) (b1+b2), z

[27] =(a0+a2)(b0+b2), z

[28] =a1b1+(a1+a2)(b1+b2), z

[29] =a2 b2+(a0+a2)(b0+b2), z

[30] =a1b1+(a1+a2)(b1+b2), z

[31] =0, z

[32] =0.

[0089] Thereafter, the equivalence checking device 10 sets the counter value j of the clock counter to j=4. Since the counter value j is the same as the predetermined counter value k=4, the equivalence checking device 10 ends the generation of the Boolean polynomial. At this time, the Boolean polynomials z[7], z[8], and z[9] corresponding to the primary outputs w7, w8, and w9 in the netlist, respectively, are the Boolean polynomials corresponding to each bit in the primary output of the arithmetic operation circuit in the netlist. Therefore, the netlist Boolean polynomial generated based on the netlist is Dout4(netlist)[0]=a0b1+a1b0+a1b2+a2b1+a2b 2、 Dout4(netlist)[1]=a0b0+a0b2+a1b2+a2b0+a2b 1、 Dout4(netlist)[2]=a0b1+a0b2+a1b0+a1b1+a2b0.

[0090] Then, the equivalence checking device 10 generates a specification description Boolean polynomial corresponding to each bit of the primary output of the arithmetic operation circuit based on the logic function included in the specification description. 3 ) for A=a0β+a1β 2 +a2β 4 , B=b0β+b1β 2 +b2β 4 It can be expressed as follows, where a 0、 a 1、 a 2、 b 0、 b 1、 b2∈GF(2). Then, D∈GF(2 3 ) is a function of GF(2 3 ) and calculate the multiplication AB. D=d0β+d1β 2 +d2β 4 Then, d 0= a0b1+a1b0+a1b2+a2b1+a2b2, d 1= a0b0+a0b2+a1b2+a2b0+a2b1, d 2= a0b1+a0b2+a1b0+a1b1+a2b0. d0, d1, and d2 are a 0、 a 1、 a 2、 b 0、 b 1、 These can be thought of as Boolean functions with arguments a0, a1, a2, b0, b1, b 2、 Boolean polynomial a0b1+a1b0+a1b2+a2b1+a2b in q0, ..., q8) 2、 a0b0+a0b2+a1b2+a2b0+a2b 1、 It is a0b1+a0b2+a1b0+a1b1+a2b0 itself.

[0091] Therefore, the specification description Boolean polynomial corresponding to each bit of the primary output of the arithmetic operation circuit based on the logic function included in the specification description is Dout4(specification description)[0]=a0b1+a1b0+a1b2+a2b1+a2b 2、Dout4(specification description)[1]=a0b0+a0b2+a1b2+a2b0+a2b 1、 Dout4(specification description)[2]=a0b1+a0b2+a1b0+a1b1+a2b0.

[0092] Then, the equivalence verifying device 10 calculates the difference Dout4 (difference) between the netlist Boolean polynomial generated based on the netlist and the specification description Boolean polynomial corresponding to each bit of the primary output of the arithmetic operation circuit based on the logic function included in the specification description. In the above example, Dout4 (difference) [0] = Dout4 (difference) [1] = Dout4 (difference) [2] = 0. Therefore, the difference Dout4 (difference) does not include a Boolean polynomial that is not 0, and therefore the netlist and specification description are determined to be equivalent.

[0093] As described above, in this embodiment, the equivalence checking device 10 generates, for each bit of the primary output, Boolean polynomials that correspond one-to-one to logic functions whose inputs are the primary input values ​​immediately before the rising edges of multiple operating clocks that determine the values ​​of each bit output when an arithmetic operation circuit in the netlist is operated based on the timing chart of the specification description and the initial output values ​​of all D flip-flops in the netlist. The equivalence checking device 10 then generates Boolean polynomials corresponding to each bit of the primary output based on the specification description using the Boolean polynomial ring of the Boolean polynomials calculated based on the netlist. The equivalence checking device 10 then calculates the difference between the Boolean polynomials generated based on the netlist and the Boolean polynomials generated based on the specification description. If the difference is zero for all bits, the designed netlist is determined to satisfy the specification description.

[0094] <Relationship with hardware> Next, the correspondence between the equivalence checking device 10 according to this embodiment and the main hardware configuration of a computer will be described. Fig. 10 is a diagram showing an example of the hardware configuration.

[0095] Generally, a computer has a configuration in which a CPU 81, a ROM 82, a RAM 83, a nonvolatile memory 84, etc. are connected via a bus 85. A hard disk drive may be provided instead of the nonvolatile memory 84. For the sake of convenience of explanation, only the basic hardware configuration is shown.

[0096] Here, the ROM 82 or non-volatile memory 84 stores programs required to start the operating system (hereinafter simply referred to as "OS"), and the CPU 81 reads and executes the OS program from the ROM 82 or non-volatile memory 84 when the power is turned on.

[0097] On the other hand, various application programs executed on the OS are stored in non-volatile memory 84, and the CPU 81 executes the application programs while using RAM 83 as the main memory, thereby executing processes corresponding to the applications.

[0098] The equivalence checking program of the equivalence checking device 10 according to this embodiment is stored in the nonvolatile memory 84 or the like, like other application programs, and the CPU 81 loads and executes the equivalence checking program. In the case of the equivalence checking device 10 according to this embodiment, an equivalence checking program including routines corresponding to the initial parameter setting unit 15a, netlist Boolean polynomial generation unit 15b, specification description Boolean polynomial generation unit 15c, difference calculation unit 15d, and judgment unit 15e shown in FIG. 2 is stored in the nonvolatile memory 84 or the like. When the CPU 81 loads and executes the equivalence checking program, equivalence checking processes corresponding to the initial parameter setting unit 15a, netlist Boolean polynomial generation unit 15b, specification description Boolean polynomial generation unit 15c, difference calculation unit 15d, and judgment unit 15e are generated.

[0099] The configurations illustrated in the above embodiments are merely functional schematics and are not necessarily physically configured as shown. In other words, the distribution and integration of each device is not limited to that illustrated, and all or part of the devices can be functionally or physically distributed and integrated in any unit depending on various loads, usage conditions, etc. [Industrial Applicability]

[0100] The equivalence checking device, the equivalence checking method and the equivalence checking program according to the present invention are suitable for efficiently verifying the equivalence between an arithmetic operation circuit including a combinational logic circuit and a sequential circuit and a design specification. [Explanation of symbols]

[0101] 10 Equivalence Verification Device 11 Display section 12 Input section 14 Storage section 14a Specification description data 14b Netlist data 14c Boolean Polynomial Transformation Data 14d Netlist Boolean Polynomial Data 14e Specification of Boolean Polynomial Data 14f Judgment result data 15 Control Unit 15a Initial parameter setting section 15b Netlist Boolean Polynomial Generator 15c Specification Boolean Polynomial Generator 15d Difference calculation part 15e Judgment section 81 CPU 82 ROM 83 RAM 84 Non-volatile memory 85 Bus

Claims

1. An equivalence verification device that verifies the equivalence between a netlist of an arithmetic operation circuit including a combinational logic circuit and a sequential circuit and a specification description of a design specification by computer algebra, comprising: a first generating means for generating a first Boolean polynomial based on the netlist and a timing chart included in the specification description; a second generating means for generating a second Boolean polynomial based on a logic function included in the specification description; a calculation means for calculating a difference between the first Boolean polynomial generated by the first generation means and the second Boolean polynomial generated by the second generation means; a determination means for determining equivalence between the netlist and the specification description based on the difference calculated by the calculation means; An equivalence verification device comprising:

2. The first generating means 2. The equivalence verifying device according to claim 1, wherein, when the arithmetic operation circuit indicated by the netlist is operated based on the timing chart, the first Boolean polynomial is generated with a plurality of inputs to the arithmetic operation circuit and a plurality of outputs from the sequential circuit in the arithmetic operation circuit as variables.

3. The first generating means 3. The equivalence verifying device according to claim 2, wherein the first Boolean polynomial is generated using, as variables, a plurality of inputs to the arithmetic operation circuit immediately before a rising edge of the clock in the timing chart and a plurality of outputs from the sequential circuit in the arithmetic operation circuit immediately before the rising edge.

4. The determination means 2. The equivalence verifying apparatus according to claim 1, wherein when the difference calculated by said calculation means is zero, it is determined that said netlist and said specification description are equivalent.

5. The determination means 2. The equivalence verifying device according to claim 1, wherein if the difference calculated by the calculation means includes variables corresponding to a plurality of outputs from the sequential circuit, it is determined that an error dependent on an internal initial state of the arithmetic operation circuit or the inclusion of an incorrect circuit exists.

6. The determination means 2. The equivalence verifying device according to claim 1, wherein if the difference calculated by said calculation means includes a Boolean polynomial that is not zero, it is determined that an error that depends only on the input of said arithmetic operation circuit or the inclusion of an incorrect circuit is present.

7. An equivalence checking method for an equivalence checking device that verifies the equivalence between a netlist of an arithmetic operation circuit including a combinational logic circuit and a sequential circuit and a specification description of a design specification by computer algebra, comprising: a first generation step of generating a first Boolean polynomial based on the netlist and a timing chart included in the specification description; a second generation step of generating a second Boolean polynomial based on a logic function included in the specification description; a calculation step of calculating a difference between the first Boolean polynomial generated in the first generation step and the second Boolean polynomial generated in the second generation step; a determination step of determining equivalence between the netlist and the specification description based on the difference calculated in the calculation step; 1. An equivalence verification method comprising:

8. An equivalence checking program executed by an equivalence checking device that verifies the equivalence between a netlist of an arithmetic operation circuit including a combinational logic circuit and a sequential circuit and a specification description of a design specification by computer algebra, comprising: a first generation procedure for generating a first Boolean polynomial based on the netlist and a timing chart included in the specification description; a second generation step of generating a second Boolean polynomial based on a logic function included in the specification description; a calculation step of calculating a difference between the first Boolean polynomial generated by the first generation step and the second Boolean polynomial generated by the second generation step; a determination step for determining equivalence between the netlist and the specification description based on the difference calculated by the calculation step; An equivalence verification program that causes a computer to execute the above.

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