Microelectronic assemblies with sealed liners for glass cores

Abstract

To provide related devices and methods for alleviating CTE mismatch-induced stresses.SOLUTION: A microelectronic assembly may include: a glass core having a first face and a second face opposite the first face; and a TGV in the glass core, the TGV extending from the first face towards the second face and including a conductive material. The microelectronic assembly may further include: an organic material in the TGV, between the conductive material and the glass core, where a modulus of the organic material is smaller than about 30 GPa; and an inorganic material over the organic material in the TGV, the inorganic material comprising silicon and nitrogen. In such a microelectronic assembly, the glass core, the conductive material and the inorganic material may completely enclose the organic material to reduce or eliminate degradation (e.g., oxidation and / or crystallization) of the organic material.SELECTED DRAWING: Figure 1

Description

[Background technology]

[0001] For the past few decades, the scaling of features in integrated circuits (ICs) has been a driving force behind the ever-growing semiconductor industry and emerging applications in areas such as big data, artificial intelligence, mobile communications, and autonomous driving. Scaling to smaller and smaller features allows for an increased density of functional units on a semiconductor chip's limited real estate. For example, reducing the size of transistors allows for a greater number of memory or logic devices to be packed onto a chip, leading to the production of more capable products. However, the drive for ever-increasing capacity is not without challenges. The need to optimize the manufacturing and performance of each component (e.g., each transistor) is becoming increasingly important.

[0002] In parallel with transistor-level optimization, the landscape of advanced IC packaging is rapidly evolving to keep up with performance expectations and shrinking transistor size requirements. Currently, multiple IC dies are commonly bonded together in multi-die IC packages to integrate multiple features or functions and facilitate connection to other components, such as a package substrate. For example, an IC package may include an embedded multi-die interconnect bridge (EMIB) to bond two or more IC dies.

[0003] Integrating multiple dies into a single IC package offers significant benefits but also introduces additional complexity due to the proximity of multiple materials with different material properties. When an IC package undergoes multiple processing steps involving various temperatures and pressure loads, the individual materials within the package may behave differently from each other, resulting in out-of-plane deformation of various layers, known as "package warpage." One approach to addressing package warpage is to use a stiffer core to which the different IC dies are attached. In recent years, glass cores have been explored as an alternative to organic resin-based cores (e.g., cores based on the use of Ajinomoto Build-Up Film (ABF)). Glass is believed to be stronger than organic resin-based materials and to offer several advantages, including excellent thermal properties, a low coefficient of thermal expansion (CTE), high electrical insulation, chemical resistance, optical transparency, and compatibility with improved semiconductor properties. However, a major challenge to the widespread adoption of glass cores is that glass is highly susceptible to damage due to mechanical and / or thermal stresses, for example, damage due to stresses induced by metal-filled through-glass vias (TGVs). [Brief explanation of the drawings]

[0004] The embodiments will be readily understood from the following detailed description in conjunction with the accompanying drawings, in which: To facilitate this description, like structural elements are given like reference numerals; and the embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.

[0005] [Figure 1] 1 is a schematic cross-sectional side view of an exemplary microelectronic assembly according to some embodiments of the present disclosure.

[0006] [Figure 2] 1 is a schematic cross-sectional side view of another exemplary microelectronic assembly according to some embodiments of the present disclosure.

[0007] [Figure 3]1 illustrates the surface of a glass core from which TGV stresses may initiate, according to some embodiments of the present disclosure.

[0008] [Figure 4A] 1 shows a side cross-sectional view of an exemplary glass core with a sealing liner according to some embodiments of the present disclosure. [Figure 4B] 1 shows a side cross-sectional view of an exemplary glass core with a sealing liner according to some embodiments of the present disclosure. [Figure 4C] 1 shows a side cross-sectional view of an exemplary glass core with a sealing liner according to some embodiments of the present disclosure.

[0009] [Figure 5] FIG. 2 is a flow diagram of a first method of providing a glass core with a sealing liner, according to some embodiments.

[0010] [Figure 6A] 6 provides a cross-sectional side view at a stage in the manufacture of an exemplary glass core having a sealing liner according to the method of FIG. 5, according to some embodiments. [Figure 6B] 6 provides a cross-sectional side view at a stage in the manufacture of an exemplary glass core having a sealing liner according to the method of FIG. 5, according to some embodiments. [Figure 6C] 6 provides a cross-sectional side view at a stage in the manufacture of an exemplary glass core having a sealing liner according to the method of FIG. 5, according to some embodiments. [Figure 6D] 6 provides a cross-sectional side view at a stage in the manufacture of an exemplary glass core having a sealing liner according to the method of FIG. 5, according to some embodiments. [Figure 6E] 6 provides a cross-sectional side view at a stage in the manufacture of an exemplary glass core having a sealing liner according to the method of FIG. 5, according to some embodiments. [Figure 6F] 6 provides a cross-sectional side view at a stage in the manufacture of an exemplary glass core having a sealing liner according to the method of FIG. 5, according to some embodiments.

[0011] [Figure 7] FIG. 10 is a flow diagram of a second method of providing a glass core with a sealing liner, according to some embodiments.

[0012] [Figure 8A] 8A-8D provide cross-sectional side views at various stages in the manufacture of an exemplary glass core having a sealing liner according to the method of FIG. 7, according to some embodiments. [Figure 8B] 8A-8D provide cross-sectional side views at various stages in the manufacture of an exemplary glass core having a sealing liner according to the method of FIG. 7, according to some embodiments. [Figure 8C] 8A-8D provide cross-sectional side views at various stages in the manufacture of an exemplary glass core having a sealing liner according to the method of FIG. 7, according to some embodiments.

[0013] [Figure 9] FIG. 10 is a flow diagram of a third method of providing a glass core with a sealing liner, according to some embodiments.

[0014] [Figure 10A] 10 provides cross-sectional side views at different stages in the manufacture of an exemplary glass core having a sealing liner according to the method of FIG. 9, according to some embodiments. [Figure 10B] 10 provides cross-sectional side views at different stages in the manufacture of an exemplary glass core having a sealing liner according to the method of FIG. 9, according to some embodiments. [Figure 10C] 10 provides cross-sectional side views at different stages in the manufacture of an exemplary glass core having a sealing liner according to the method of FIG. 9, according to some embodiments.

[0015] [Figure 11] FIG. 1 is a top view of a wafer and die that may be included in a microelectronic assembly having a glass core according to some embodiments of the present disclosure, according to any of the embodiments disclosed herein.

[0016] [Figure 12] 1 is a cross-sectional side view of an IC device that may be included in a microelectronic assembly having a glass core according to some embodiments of the present disclosure, according to any of the embodiments disclosed herein.

[0017] [Figure 13] FIG. 1 is a cross-sectional side view of an IC device assembly according to some embodiments of the present disclosure, which may include a glass core according to any of the embodiments disclosed herein.

[0018] [Figure 14] FIG. 1 is a block diagram of an exemplary communication device that may include a microelectronic assembly having a glass core according to any of the embodiments disclosed herein, according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0019] As described above, glass has properties that make it promising for integration in advanced IC packaging. When a glass core is included in a microelectronic assembly, it may be desirable to transfer electrical signals within and / or through the glass core. To that end, conductive vias may be provided within the glass core, and such conductive vias are generally referred to as TGVs. TGVs may also support efficient thermal management by providing a path for heat dissipation from active components to the package's external environment. In some implementations, TGVs may extend between the top and bottom surfaces of the glass core to provide electrical connection between electronic components, such as a die and / or package substrate, bonded to the top and bottom surfaces of the glass core. In other implementations, TGVs may be blind vias that do not reach from the top / bottom surfaces of the glass core but extend toward the opposite surface to provide electrical connection from the surface of the glass core to conductive traces or IC components embedded in the glass core, for example.

[0020] Providing TGVs within a glass core allows for a more compact and efficient design for microelectronic assemblies. However, integrating TGVs within a glass core is not trivial. Traditionally, TGV fabrication involves forming an opening for the future TGV, lining the opening with a seed material, and then depositing a conductive fill material into the lined opening. The seed material typically comprises a low-resistivity metal, such as copper, which can be deposited in a thin layer on the substantially non-conductive surfaces (e.g., sidewalls) of the opening in the glass core. The seed material is intended to provide a conductive surface for uniform and controlled deposition of the conductive fill material in a subsequent deposition step, when the conductive fill material is deposited in the lined opening using a process such as electroplating. One challenge associated with integrating TGVs within a glass core arises from the difference in CTE between the materials that can be used for the seed material and the glass core and the metal of the conductive fill material deposited in the TGV. CTE is a measure of how a material expands or contracts with a change in temperature and is typically defined as the fractional increase in length per unit of temperature increase, measured, for example, in parts per million (ppm) per degree Kelvin (K), or ppm / K. The glass materials that can be used for the glass core and metal have significantly different CTEs. Metals have relatively high CTEs, meaning they can expand and contract significantly with changes in temperature. Glass materials, on the other hand, have much lower CTEs and are less sensitive to temperature changes. For example, the CTE of glass is on the order of about 3.5 ppm / K, while the CTE of a metal such as copper is on the order of about 15 ppm / K. When a metal is in intimate contact with glass (e.g., a seed material or conductive fill material in a TGV within a glass core) and the assembly is subjected to temperature fluctuations, such as heating or cooling, the metal heats or cools significantly faster than the glass. This leads to the generation of significant thermal stresses at the interface between these two materials. High thermal stresses can exceed the strength of the glass, leading to the formation of cracks which can then propagate and compromise the structural integrity of the glass.Even if cracks do not form immediately, repeated thermal cycling can gradually weaken the glass surface, potentially leading to surface flaws or micro-cracks. Prolonged exposure to CTE mismatch-induced stresses can cause gradual degradation of the glass, making it more susceptible to failure over time.

[0021] Embodiments of the present disclosure relate to various technologies and related devices and methods for mitigating (e.g., alleviating or reducing) CTE mismatch-induced stress caused by the proximity of a conductive material of a TGV to the glass material of a glass core. As used herein, such stress is referred to as "TGV stress." Embodiments of the present disclosure are based on the recognition that including a liner material in the sidewall of a TGV as a buffer layer between the glass core and the conductive material within the TGV can help reduce TGV stress because the liner material separates the glass and metal of the seed material and the conductive fill material deposited within the TGV. In particular, selecting the liner material as a material with a relatively low modulus, e.g., a Young's modulus below about 30 gigapascals (GPa), can be particularly advantageous for reducing TGV stress. Embodiments of the present disclosure are further based on the recognition that such liner materials can be damaged / degraded due to, for example, oxidation or crystallization that can occur during processes associated with glass core substrate fabrication. For example, one type of material that has a relatively low modulus but may be susceptible to degradation due to, for example, oxidation and / or crystallization is parylene; as used herein, the name "parylene" refers to a group of polymers known as poly-para-xylenes. The inventors of the present disclosure have determined that while decoupling the conductive material of a TGV from the glass sidewall through a low-modulus liner material such as parylene can significantly reduce TGV stress, one other problem that may arise is that of adhesion failure of the liner material, which may be due to degradation of the liner material due to, for example, oxidation (e.g., degradation of a parylene film during annealing of copper in open air) or crystallization. Accordingly, the microelectronic assemblies described herein further include a sealant that can seal the liner material, thus reducing or eliminating oxidation and / or crystallization of the liner material. In the context of the present disclosure, a liner material sealed with a sealant may be referred to as a "sealed liner."In one aspect, a microelectronic assembly according to an embodiment of the present disclosure may include a glass core having a first surface and a second surface opposite the first surface, and a TGV within the glass core, the TGV extending from the first surface toward the second surface and including a conductive material. The microelectronic assembly may further include an organic liner material within the TGV between the conductive material and the glass core, where the modulus of the organic material is less than about 30 GPa, and an encapsulant provided as an inorganic material above the organic material within the TGV, where the inorganic material includes silicon and nitrogen. In such a microelectronic assembly, the glass core, the conductive material, and the inorganic material may completely surround the organic material to reduce or eliminate degradation (e.g., oxidation and / or crystallization) of the organic material.

[0022] In particular, integrating layers of different materials (e.g., multiple dies, redistribution layers, package substrates) within a single IC package or microelectronic assembly is challenging due to package warpage. Providing an IC package or microelectronic assembly with a glass core having TGVs including the sealing liner described herein can be helpful. Various of the embodiments disclosed herein can help achieve reliable integration of multiple layers of different materials within a single microelectronic assembly at lower cost and / or greater design flexibility relative to conventional approaches. Various of the microelectronic assemblies disclosed herein can exhibit reduced warpage relative to microelectronic assemblies without a glass core. The microelectronic assemblies disclosed herein can be particularly advantageous for small and thin applications in computers, tablets, industrial robots, and consumer electronics (e.g., wearable devices).

[0023] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof. In the accompanying drawings, where like reference numerals refer to like parts throughout, there are shown by way of illustration embodiments that may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.

[0024] Any of the features described with reference to any of the accompanying drawings herein may be combined with any other features to form a microelectronic assembly 100, a glass core 110, an IC device 1600, an IC device assembly 1700, or a communication device 1800, as appropriate. For convenience, the term "die 114" may be used to refer to a collection of dies 114-1, 114-2, etc. Elements of the drawings bearing the same reference numeral may be shared among different drawings; for simplicity of explanation, a description of these elements provided with respect to one of the drawings will not be repeated for the other drawings, and these elements may take the form of any of the embodiments disclosed herein. To avoid cluttering the drawings, when multiple instances of a particular element are shown, only some of the elements may be labeled with a reference numeral (e.g., FIG. 1 shows multiple conductive contacts 122, but only one of them is labeled with a reference numeral). Also, to avoid cluttering the drawings, not all reference numerals shown in one of the drawings are shown in other similar drawings.

[0025] The drawings are not necessarily to scale. While many of the drawings depict rectilinear structures with flat walls and right-angled corners, this is merely for ease of illustration and may not reflect actual process limitations that may cause various features to appear less than “ideal” when any of the structures described herein are inspected using, for example, scanning electron microscope (SEM) or transmission electron microscope (TEM) images. Possible processing defects, such as less-than-perfectly straight edges of material, tapered vias or other openings, unintentional corner rounding, or thickness variations in different material layers, may also be visible in such images of the actual structure. Other defects not listed here but that are common within the semiconductor device manufacturing and packaging field may be present. Inspection and reverse engineering of the device's component layout and mask data to reconstruct the circuitry, for example, using an optical microscope, TEM, or SEM, and / or inspection of a cross-section of the device to detect the shape and location of the various device elements described herein, for example, using physical failure analysis (PFA), may enable determination of the presence of a glass core having one or more sealing liners described herein.

[0026] For purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C). When used to describe a dimensional range, the phrase "between X and Y" refers to a range that includes X and Y. When used to describe the location of an element, the phrase "between X and Y" refers to the area spatially between element X and element Y. The terms "substantially," "close," "approximately," "near," and "about" generally refer to within + / - 20%, e.g., within + / - 5% or + / - 2% of a target value based on the context of a particular value described herein or known in the art. Similarly, terms indicating the orientation of various elements, such as "coplanar," "perpendicular," "orthogonal," "parallel," or any other angle between these elements, generally refer to within + / - 10% of the exact orientation, e.g., within + / - 5% or within + / - 2%.

[0027] The description uses the phrases "in one embodiment" or "in an embodiment," which may each refer to one or more of the same or different embodiments. Furthermore, terms such as "comprising," "including," and "having" when used with respect to embodiments of the present disclosure are synonymous. As used herein, the terms "package" and "IC package" are synonymous with the terms "die" and "IC die." Furthermore, the terms "chip," "chiplet," "die," and "IC die" may be used interchangeably herein.

[0028] Although certain elements may be referred to in the singular herein, such elements may include multiple subelements. For example, a "dielectric material" may include one or more dielectric materials, or an "insulator material" may include one or more insulator materials. Terms such as "oxide," "carbide," and "nitride" refer to compounds containing oxygen, carbon, nitrogen, etc., respectively. The term "high-k dielectric" refers to a material with a dielectric constant higher than that of silicon oxide, while the term "low-k dielectric" refers to a material with a dielectric constant lower than that of silicon oxide. Unless otherwise specified, the term "insulating" and variations thereof (e.g., "insulative" or "insulator") mean "electrically insulating," and the term "conducting" and variations thereof (e.g., "conductive" or "conductor") mean "electrically conducting." In reference to optical signals and / or device components and elements that operate on or using optical signals, the term "conducting" can also mean "optically conducting." The term "insulating material" refers to solid materials (and / or liquid materials that solidify after processing as described herein) that are substantially non-conductive. They may include, by way of example and not limitation, organic polymers and plastics, and inorganic materials such as ionic crystals, porcelain, glass, silicon, and alumina, or combinations thereof. They may include dielectric materials, highly polarizable materials, and / or piezoelectric materials. They may be transparent or opaque without departing from the scope of the present disclosure. Further examples of insulating materials are materials such as underfills and molds used in packaging applications, including materials used in organic interposers, package supports, and other such components.

[0029] 1 is a schematic cross-sectional side view of an exemplary microelectronic assembly 100 in which a glass core with one or more encapsulant liners described herein according to some embodiments of the present disclosure may be implemented. The microelectronic assembly 100 may include a substrate 107 having a double-sided bridge die 114-1 in a cavity 119 within the substrate 107, where the die 114-1 may be electrically coupled to a conductive path, e.g., a conductive trace 108A or a conductive via 108B, within a metal layer N-1 of the substrate 107 underlying a bottom of the cavity 119. The substrate 107 may include a dielectric material 112 (e.g., a first dielectric material layer 112A and a second dielectric material layer 112B, together referred to as “one or more layers of dielectric material 112,” as shown), and a conductive material 108 disposed within the one or more layers of the dielectric material 112 to provide a conductive path (e.g., the conductive trace 108A and the conductive via 108B) through the substrate 107 and to provide conductive pads and contacts. The substrate 107 may include a first surface 120-1 and an opposing second surface 120-2. The die 114-1 may be surrounded by a dielectric material 112 on the substrate 107. The die 114-1 may include a bottom surface (e.g., the surface facing the first surface 120-1) having first conductive contacts 122, an opposing top surface (e.g., the surface facing the second surface 120-2) having second conductive contacts 124, and through-silicon vias (TSVs) 125 coupling the respective first and second conductive contacts 122, 124. In some embodiments, the pitch of the first conductive contacts 122 on the first die 114-1 may be between 25 microns and 250 microns. As used herein, pitch is measured center-to-center (e.g., from the center of a conductive contact to the center of an adjacent conductive contact). In some embodiments, the pitch of the second conductive contacts 124 on the first die 114-1 may be between 25 microns and 100 microns. The dies 114-2, 114-3 may include a set of conductive contacts 122 on the bottom surfaces of the dies (e.g., the surfaces facing toward the first surface 120-1).Die 114 may include other conductive paths (e.g., including lines and vias) to other circuits (not shown) coupled to respective conductive contacts (e.g., conductive contacts 122, 124) on the surface of die 114. As used herein, the terms “die,” “microelectronic component,” and similar variations may be used interchangeably. As used herein, the terms “interconnect,” “component,” “bridge die,” and similar variations may be used interchangeably. Bridge die 114-1 may be electrically coupled to dies 114-2, 114-3 by die-to-die (DTD) interconnects 130 on the second surface 120-2. In particular, conductive contact 124 on the top surface of die 114-1 may be coupled to conductive contacts 122 on the bottom surfaces of dies 114-2, 114-3 by conductive vias 108B through second dielectric material layer 112B.

[0030] As used herein, a "conductive contact" can refer to a portion of a conductive material (e.g., a metal) that serves as an electrical interface between different components (e.g., a portion of a conductive interconnect); a conductive contact may be recessed into, flush with, or extend away from a surface of a component (e.g., have a pillar shape), and may take any suitable form (e.g., a conductive pad or socket, or a portion of a conductive line or via). In a general sense, an "interconnect" refers to any element that provides a physical connection between two other elements. For example, an electrical interconnect provides an electrical connection between two electrical components to facilitate the communication of electrical signals between them; an optical interconnect provides an optical connection between two optical components to facilitate the communication of optical signals between them. As used herein, both electrical interconnects and optical interconnects are included in the term "interconnect." The nature of the interconnects being described should be understood herein with reference to their associated signal media. Thus, when used with reference to an electronic device, such as an IC, that operates with electrical signals, the term “interconnect” describes any element formed of a conductive material for providing electrical connection to one or more elements associated with the IC and / or between various such elements. In such cases, the term “interconnect” may refer to both conductive traces (sometimes also referred to as “metal traces,” “lines,” “metal lines,” “wires,” “metal wires,” “trenches,” or “metal trenches”) and conductive vias (sometimes also referred to as “vias” or “metal vias”). In some cases, conductive traces and vias may be referred to as “metal traces” and “metal vias,” respectively, to emphasize that these elements comprise a conductive material such as a metal. Similarly, when used with reference to a device that also operates with optical signals, such as a photonic IC (PIC), “interconnect” may also describe any element formed of an optically conductive material for providing optical connection to one or more elements associated with the PIC.In such instances, the term "interconnect" may refer to optical waveguides (eg, structures that guide and confine light waves), including optical fibers, optical splitters, optical combiners, optical couplers, and optical vias.

[0031] The die 114 disclosed herein may include an insulating material (e.g., a dielectric material formed in multiple layers, as known in the art) and multiple conductive paths formed through the insulating material. In some embodiments, the insulating material of the die 114 may include a dielectric material such as silicon dioxide, silicon nitride, oxynitride, polyimide material, glass-reinforced epoxy matrix material, or a low- or ultra-low-k dielectric (e.g., a carbon-doped dielectric, a fluorine-doped dielectric, a porous dielectric, an organic polymer dielectric, a photoimageable dielectric, and / or a benzocyclobutene-based polymer). In some embodiments, the insulating material of the die 114 may include a semiconductor material such as silicon, germanium, or a III-V material (e.g., gallium nitride), and one or more additional materials. For example, the insulating material may include silicon oxide or silicon nitride. The conductive paths within the die 114 may include conductive traces and / or conductive vias, and may connect any of the conductive contacts within the die 114 in any suitable manner (e.g., connecting multiple conductive contacts on the same or different surfaces of the die 114). Exemplary structures that may be included within the die 114 disclosed herein are described below with reference to IC device 1600. The conductive paths within the die 114 may be bounded by a liner material, such as an adhesive liner and / or a barrier liner, as appropriate. In some embodiments, the die 114 is a wafer. In some embodiments, the die 114 is a monolithic silicon, fan-out or fan-in packaged die or die stack (e.g., stacked wafers, stacked dies, or stacked multi-layer dies).

[0032] In some embodiments, die 114 may include conductive paths for transferring power, ground, and / or signals between other dies 114 included within microelectronic assembly 100. For example, die 114-1 may include TSVs 125, which include conductive vias, such as metal vias (insulated from the surrounding silicon or other semiconductor material by a barrier oxide), or other conductive paths through which power, ground, and / or signals may be transmitted between package substrate 102 and one or more dies 114 "on top" of die 114-1 (e.g., dies 114-2 and / or 114-3 in the embodiment of FIG. 1). In some embodiments, die 114-1 may not transfer power and / or ground to dies 114-2 and 114-3; instead, dies 114-2, 114-3 may be directly coupled to power and / or ground lines in package substrate 102 via substrate-to-package substrate (STPS) interconnect 150, conductive paths provided by conductive material 108 in substrate 107, and die-to-substrate (DTS) interconnect 140. In some embodiments, die 114-1 may be thicker than dies 114-2, 114-3. In some embodiments, die 114-1 may be a memory device or a high-frequency serializer and deserializer (SerDes) such as, for example, a Peripheral Component Interconnect (PCI) Express. In some embodiments, die 114-1 may be a processing die, a radio frequency chip, a power converter, a network processor, a workload accelerator, a voltage regulator die, or a security encryptor. In some embodiments, die 114-2 and / or die 114-3 may be a processing die, a radio frequency chip, a power converter, a network processor, a workload accelerator, a voltage regulator die, or a security encryptor. In some embodiments, die 114 may be described below with reference to die 1502 of FIG. 11 .

[0033] The dielectric material 112 of the substrate 107 may be formed in multiple layers (e.g., at least a first dielectric material layer 112A and a second dielectric material layer 112B). In some embodiments, the dielectric material 112 may include an organic material, such as an organic build-up film. In some embodiments, the dielectric material 112 may include, for example, a ceramic, an epoxy film with filler particles therein, glass, an inorganic material, or a combination of organic and inorganic materials. In some embodiments, the conductive material 108 may include a metal (e.g., copper). In some embodiments, the substrate 107 may include multiple layers of dielectric material 112 / conductive material 108, where a line / trace / pad / contact of the conductive material 108 (e.g., conductive trace 108A) in one layer is electrically coupled to a line / trace / pad / contact of the conductive material 108 (e.g., conductive trace 108A) in an adjacent layer by a conductive material 108 via (e.g., 108B) extending through the dielectric material 112. The conductive traces 108A may be referred to herein as “conductive lines,” “conductive elements,” “conductive pads,” or “conductive contacts.” A substrate 107 including such multiple layers may be formed, for example, using printed circuit board (PCB) manufacturing techniques.

[0034] An individual layer of dielectric material 112 (e.g., first dielectric material layer 112A) may include a cavity 119, and bridge die 114-1 may be at least partially nested within cavity 119. Bridge die 114-1 may be surrounded (e.g., embedded) by a next individual layer of dielectric material 112 (e.g., second dielectric material layer 112B). In some embodiments, cavity 119 is tapered, narrowing toward a bottom surface of cavity 119 (e.g., a surface facing first surface 120-1 of substrate 107). Cavity 119 may be indicated by a seam between dielectric material 112A and dielectric material 112B. In the case where bridge die 114-1 is partially nested within cavity 119, as shown in FIG. 1 , a top surface of bridge die 114-1 may extend above a top surface of dielectric material 112A. In cases where bridge die 114-1 is fully nested within cavity 119 (not shown), the top surface of bridge die 114-1 may be flush with the top surface of dielectric material 112A or may be below the top surface of dielectric material 112A.

[0035] Substrate 107 may include N layers of conductive material 108, where N is an integer greater than or equal to 1. In FIG. 1 , these layers are labeled in descending order (e.g., layer N, layer N-1, layer N-2, etc.) from the second surface 120-2 (e.g., top surface) of substrate 107. In particular, as shown in FIG. 1 , substrate 107 may include four metal layers (e.g., N, N-1, N-2, and N-3). The N metal layers may include conductive contacts 121 on second surface 120-2 of substrate 107 coupled to conductive contacts 122 on the bottom surfaces of dies 114-2, 114-3 by DTS interconnects 140. The N-2 metal layer may include conductive traces 108A having a top surface (e.g., the surface facing toward the second surface 120-2 of the substrate 107), an opposing bottom surface (e.g., the surface facing toward the first surface 120-1 of the substrate 107), and side surfaces extending between the top and bottom surfaces of the conductive traces 108A. The substrate 107 may further include an N-1 metal layer above the N-2 metal layer and below the metal layer, a portion of the N-1 metal layer including a metal ring 118 exposed at the periphery of the bottom of the cavity 119. As shown, the metal ring 118 may be coplanar with the conductive traces 108A of the N-1 metal layer and may be adjacent to the edge of the cavity 119.

[0036] While particular numbers and arrangements of layers of dielectric material 112 / conductive material 108 are shown in various of the accompanying figures, these particular numbers and arrangements are merely exemplary, and any desired number and arrangement of dielectric material 112 / conductive material 108 may be used. Additionally, while a particular number of layers (e.g., four layers) are shown in substrate 107, these layers may represent only a portion of substrate 107, and, for example, additional layers may be present (e.g., layers N-4, N-5, N-6, etc.).

[0037] As shown in FIG. 1 , the substrate 107 may further include a glass core 110 with TGVs 115, and additional layers 111 may reside below the glass core 110 and be coupled to the package substrate 102 by interconnects 150. Any of the TGVs 115 may be conductive vias with a sealing liner as described herein. As used herein, the term “glass core” refers to a layer (e.g., a glass layer) or structure (e.g., a portion of a glass layer) of any glass material, such as quartz, silica, fused silica, silicate glass (e.g., borosilicate, aluminosilicate, aluminoborosilicate), soda-lime glass, soda-lime silica, BOROFLOAT glass, lead borate glass, photosensitive glass, non-photosensitive glass, or ceramic glass. In particular, the glass core 110 may be bulk glass or a solid volume / layer of glass opposed to a material that may contain particles of glass, such as, for example, a glass fiber-reinforced polymer (e.g., a substrate / board constructed with glass fiber and an epoxy binder). Such glass materials are typically amorphous and often transparent amorphous solids. In some embodiments, the glass core 110 can be an amorphous solid glass layer. In some embodiments, the glass core 110 can include a material containing silicon and oxygen, as well as any one or more of aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, and zinc. In some embodiments, the glass core 110 can include a material such as any of the above-mentioned materials, including at least about 0.5% silicon by weight, e.g., between about 0.5% and 50%, between about 1% and 48%, or at least about 23% silicon by weight. For example, if the glass core 110 is fused silica, the silicon weight percentage can be about 47%. In some embodiments, the glass core 110 can include a material having at least 23% silicon by weight and / or at least 26% oxygen by weight, and in some further embodiments, the glass core 110 can further include at least 5% aluminum by weight.In some embodiments, the glass core 110 may include any of the materials described above and may further include one or more additives, such as Al2O3, BO3, MgO, CaO, SrO, BaO, SnO2, Na2O, KO, SrO, PO3, ZrO2, Li2O, Ti, and Zn. In some embodiments, the glass core 110 may be a layer of glass that does not include organic adhesives or organic materials. The glass core 110 may be distinguished from, for example, the "prepreg" or "RF4" core of a PCB substrate, which typically includes glass fibers embedded in a resinous organic material such as epoxy. In such conventional core / substrates including glass fibers and epoxy, the diameter of the glass fibers is generally in the range of 5 microns to 200 microns. During shrinkage, the glass core 110 may be a layer of glass that is approximately 10 millimeters on one side to approximately 250 millimeters on one side (e.g., 10 millimeters by 10 millimeters to 250 millimeters by 250 millimeters). In some embodiments, the cross-section of glass core 110 in the x-z, y-z, and / or x-y planes of exemplary coordinate system 105 shown in FIG. 1 may be substantially rectangular (the axes shown in subsequent figures refer to the axes of coordinate system 105), while in some further embodiments, glass core 110 may have rounded or beveled edges / sides / sidewalls. In some embodiments, in a top view of glass core 110 (e.g., in the x-y plane of coordinate system 105), glass core 110 may have a first length in the range of 10 millimeters to 250 millimeters and a second length in the range of 10 millimeters to 250 millimeters, where the first length is perpendicular to the second length. The thickness of glass core 110 (e.g., the dimension measured along the z-axis of coordinate system 105) may be in the range of approximately 50 microns to 1.4 millimeters. In some embodiments, the glass core 110 can be a glass core substrate, with the glass core substrate having a thickness in the range of approximately 50 microns to 1.4 millimeters.In some embodiments, the glass core 110 may be a layer of glass including a rectangular prismatic volume, possibly with rounded or sloping edges / sides / sidewalls. In some such embodiments, the rectangular prismatic volume may have a first side and a second side perpendicular to the first side, the first side having a length in the range of 10 millimeters to 250 millimeters, and the second side having a length in the range of 10 millimeters to 250 millimeters. In some embodiments, the glass core 110 may be a rectangular prismatic volume, such as a TGV 115, with a section (e.g., a via) removed and filled with another material (e.g., a metal). In some embodiments, the glass core 110 may be a layer of glass having a thickness in the range of 50 microns to 1.4 millimeters, a first length in the range of 10 millimeters to 250 millimeters, and a second length in the range of 10 millimeters to 250 millimeters, the first length being perpendicular to the second length.

[0038] In some implementations, the substrate 107, including the glass core 110, and the die 114 may together be referred to as the "multilayer die subassembly 104." The glass core 110 may provide mechanical stability to the multilayer die subassembly 104, the substrate 107, and / or the microelectronic assembly 100. The glass core 110 may reduce warpage and provide a more robust surface for attaching the multilayer die subassembly 104 to the package substrate 102 or other substrate (e.g., an interposer or circuit board).

[0039] In some implementations, the dielectric material 112 of the substrate 107 and the glass core 110 together may be referred to as a "multilayer glass substrate." In some such embodiments, the multilayer glass substrate may be a coreless substrate. In some such embodiments, the glass core 110 may be a glass layer having a thickness in the range of about 25 microns to 50 microns. In some embodiments, an additional layer 111 may be part of the multilayer glass substrate.

[0040] The TGVs 115 may be vias extending between the first and second sides of the glass core 110 (e.g., between the bottom and top surfaces of the glass core 110), e.g., the vias comprise any suitable conductive material, e.g., a metal such as copper, silver, nickel, gold, aluminum, or other metals or alloys. Any suitable process may be used to form the openings for the TGVs 115, including, for example, direct laser drilling or a laser-induced etching process (which may also be referred to as laser patterning or selective laser activation). For any of the TGVs 115, via metallization may be performed using any of the fabrication methods utilizing a sealing liner described herein, e.g., any of the methods shown in FIG. 5 , FIG. 7 , or FIG. 9 . Thus, although not specifically shown in FIG. 1 or FIG. 2 , any of the TGVs 115 shown in these figures may be implemented as described with respect to the fabrication methods shown in FIG. 5 , FIG. 7 , or FIG. 9 (e.g., as a conductive via with a sealing liner as shown in any of FIGS. 4A-4C ). In some embodiments, the TGVs 115 disclosed herein may have a pitch between 50 microns and 500 microns, for example, measured from the center of one TGV 115 to the center of an adjacent TGV 115. The TGVs 115 may have any suitable size and shape. In some embodiments, the TGVs 115 may have a cross-section that is circular, rectangular, or other shape. In some embodiments, at least some of the TGVs 115 may have an hourglass shape, as shown, for example, in FIG. 2. In some embodiments, at least some of the TGVs 115 may taper downward from one side of the glass core 110 to another, for example, from the top surface of the glass core 110 to the bottom surface of the glass core 110.

[0041] Substrate 107 (e.g., further layer 111) may be coupled to package substrate 102 by STPS interconnects 150. In particular, the top surface of package substrate 102 may include a set of conductive contacts 146. Conductive contacts 144 on the bottom surface of substrate 107 may be electrically and mechanically coupled to conductive contacts 146 on the top surface of package substrate 102 by STPS interconnects 150. Package substrate 102 may include insulating material (e.g., a dielectric material formed in multiple layers, as known in the art) and one or more conductive paths for transferring power, ground, and signals through the dielectric material (e.g., including conductive traces and / or conductive vias, as shown). In some embodiments, the insulating material of the package substrate 102 may be a dielectric material, such as organic dielectric materials, flame-retardant grade 4 materials (FR-4), bismaleimide triazine (BT) resins, polyimide materials, glass-reinforced epoxy matrix materials, organic dielectrics with inorganic fillers, or low-k and ultra-low-k dielectrics (e.g., carbon-doped dielectrics, fluorine-doped dielectric porous dielectrics, and organic polymer dielectrics). In particular, when the package substrate 102 is formed using standard PCB processes, the package substrate 102 may include FR-4, and the conductive paths within the package substrate 102 may be formed by patterned sheets of copper separated by build-up layers of FR-4. The conductive paths within the package substrate 102 may be optionally bounded by a liner material, such as an adhesive liner and / or a barrier liner. In some embodiments, the package substrate 102 may be formed using a lithographically defined via packaging process. In some embodiments, the package substrate 102 may be manufactured using standard organic package manufacturing processes, and thus the package substrate 102 may take the form of an organic package. In some embodiments, the package substrate 102 may be a set of redistribution layers formed on a panel carrier by laminating or spinning on a dielectric material and creating conductive vias, and lining by laser drilling and plating.In some embodiments, the package substrate 102 may be formed on the removable carrier using any suitable technique, such as a redistribution layer technique. Any method known in the art for manufacturing the package substrate 102 may be used, and for the sake of brevity, such methods will not be described in further detail herein.

[0042] In some embodiments, the package substrate 102 may be a lower-density medium, and the die 114 may be a higher-density medium or may have areas with higher-density medium. As used herein, the terms “lower-density” and “higher-density” are relative terms indicating that the conductive paths (e.g., including conductive interconnects, conductive lines, and conductive vias) in the lower-density medium are larger and / or have a larger pitch than the conductive paths in the higher-density medium. In some embodiments, the higher-density medium may be fabricated using a modified semi-additive process or a semi-additive build-up process involving advanced lithography (with small vertical interconnect features formed by advanced laser or lithography processes), while the lower-density medium may be a PCB fabricated using a standard PCB process (e.g., a standard subtractive process with coarse vertical interconnect features formed by standard laser processes using etching chemistries to remove areas of unwanted copper). In other embodiments, the higher-density medium may be fabricated using a semiconductor fabrication process, such as a single damascene process or a dual damascene process. In some embodiments, additional dies may be disposed on the top surfaces of dies 114-2, 114-3. In some embodiments, additional components may be disposed on the top surfaces of dies 114-2, 114-3. Additional passive components, such as surface-mount resistors, capacitors, and / or inductors, may be disposed on the top or bottom surface of package substrate 102 or embedded in package substrate 102.

[0043] The microelectronic assembly 100 of FIG. 1 may also include an underfill material 127. In some embodiments, the underfill material 127 may extend between the substrate 107 and the package substrate 102 around the associated STPS interconnects 150. In some embodiments, the underfill material 127 may extend between different ones of the top dies 114-2, 114-3 and the top surface of the substrate 107 around the associated DTS interconnects 140, and between the bridge die 114-1 and the top dies 114-2, 114-3 around the DTD interconnects 130. The underfill material 127 may be an insulating material, such as a suitable epoxy material. In some embodiments, the underfill material 127 may include a capillary underfill, a non-conductive film (NCF), or a molded underfill. In some embodiments, the underfill material 127 may include an epoxy bundle that aids in soldering the multilayer die subassembly 104 to the package substrate 102 when forming the STPS interconnects 150, and then polymerizes and encapsulates the STPS interconnects 150. The underfill material 127 may be selected to have a CTE that may reduce or minimize stress between the substrate 107 and the package substrate 102 resulting from non-uniform thermal expansion within the microelectronic assembly 100. In some embodiments, the CTE of the underfill material 127 may have a value that is intermediate the CTE of the package substrate 102 (e.g., the CTE of the dielectric material of the package substrate 102) and the CTE of the die 114 and / or dielectric material 112 of the substrate 107.

[0044] The STPS interconnects 150 disclosed herein may take any suitable form. In some embodiments, the set of STPS interconnects 150 may comprise solder (e.g., solder bumps or balls that undergo thermal reflow to form the STPS interconnects 150), as shown in FIG. 1 , for example, where the STPS interconnects 150 may comprise solder between the conductive contacts 144 on the bottom surface of the substrate 107 and the conductive contacts 146 on the top surface of the package substrate 102. In some embodiments, the set of STPS interconnects 150 may comprise an anisotropic conductive material, such as an anisotropic conductive film or an anisotropic conductive paste. The anisotropic conductive material may comprise a conductive material dispersed within a non-conductive material.

[0045] The DTD interconnects 130 disclosed herein may take any suitable form. The DTD interconnects 130 may have a finer pitch than the STPS interconnects 150 in a microelectronic assembly. In some embodiments, the die 114 on either side of the set of DTD interconnects 130 may be unpackaged die, and / or the DTD interconnects 130 may include small conductive bumps (e.g., copper bumps). The DTD interconnects 130 may have a pitch that is too fine to be directly bonded to the package substrate 102 (e.g., too fine to function as DTS interconnects 140 or STPS interconnects 150). In some embodiments, the set of DTD interconnects 130 may include solder. In some embodiments, the set of DTD interconnects 130 may include an anisotropic conductive material, such as any of the materials described above. In some embodiments, the DTD interconnects 130 may be used as data transfer lanes, while the STPS interconnects 150 may be used for power and ground lines, among other things. In some embodiments, some or all of the DTD interconnects 130 in the microelectronic assembly 100 may be metal-to-metal interconnects (e.g., copper-to-copper interconnects or plated interconnects). In such embodiments, the DTD interconnects 130 may be joined together (e.g., under high pressure and / or temperature) without the use of an intervening solder or anisotropic conductive material. Any of the conductive contacts disclosed herein (e.g., conductive contacts 122, 124, 144, and / or 146) may include, for example, bond pads, solder bumps, conductive posts, or any other suitable conductive contact. In some embodiments, some or all of the DTD interconnects 130 and / or DTS interconnects 140 in the microelectronic assembly 100 may be solder interconnects including a solder having a higher melting point than the solder included in some or all of the STPS interconnects 150.For example, if the DTD interconnects 130 and DTS interconnects 140 in the microelectronic assembly 100 are formed before the STPS interconnects 150 are formed, the solder-based DTD interconnects 130 and DTS interconnects 140 may use a higher temperature solder (e.g., having a melting point above 200°C), while the STPS interconnects 150 may use a lower temperature solder (e.g., having a melting point below 200°C). In some embodiments, the higher temperature solder may include tin; tin and gold; or tin, silver, and copper (e.g., 96.5% tin, 3% silver, and 0.5% copper). In some embodiments, the lower temperature solder may include tin and bismuth (e.g., eutectic tin), bismuth, or tin, silver, and bismuth. In some embodiments, the lower temperature solder may include indium, indium and tin, or gallium.

[0046] In the microelectronic assembly 100 disclosed herein, some or all of the DTS interconnects 140 and STPS interconnects 150 may have a larger pitch than some or all of the DTD interconnects 130. The DTD interconnects 130 may have a smaller pitch than the STPS interconnects 150 due to the greater similarity of materials within different dies 114 on either side of a set of DTD interconnects 130 than between the substrate 107 and the top die 114-2, 114-3 on either side of a set of DTS interconnects 140 and between the substrate 107 and the package substrate 102 on either side of a set of STPS interconnects 150. In particular, differences in material composition of the substrate 107 and the die 114 or package substrate 102 may result in differences in expansion and contraction due to heat generated during operation (and heat applied during various manufacturing operations). To mitigate damage caused by this differential expansion and contraction (e.g., cracking of solder bridges, etc.), the DTS interconnects 140 and STPS interconnects 150 may be formed larger and farther apart than the DTD interconnects 130, so that they may experience less thermal stress due to the greater material similarity of the pair of dies 114 on either side of the DTD interconnect. In some embodiments, the DTS interconnects 140 disclosed herein may have a pitch between 25 microns and 250 microns. In some embodiments, the STPS interconnects 150 disclosed herein may have a pitch between 55 microns and 1000 microns, while the DTD interconnects 130 disclosed herein may have a pitch between 25 microns and 100 microns.

[0047] The microelectronic assembly 100 of FIG. 1 may also include a circuit board (not shown). The package substrate 102 may be coupled to the circuit board by second-level interconnects on the bottom surface of the package substrate 102. The second-level interconnects may be any suitable second-level interconnects, including solder balls for a ball grid array arrangement, pins in a pin grid array arrangement, or lands in a land grid array arrangement. The circuit board may be, for example, a motherboard and may have other components attached to it. The circuit board may include conductive paths and other conductive contacts for transferring power, ground, and signals through the circuit board, as is known in the art. In some embodiments, the second-level interconnects may not couple the package substrate 102 to the circuit board, but may instead couple the package substrate 102 to another IC package, an interposer, or any other suitable component. In some embodiments, the substrate 107 may not be coupled to the package substrate 102, but may instead be coupled to a circuit board such as a PCB.

[0048] While FIG. 1 illustrates microelectronic assembly 100 with a substrate including a particular number of dies 114 and conductive paths provided by conductive material 108 bonded to other dies 114, this number and arrangement is merely exemplary, and microelectronic assembly 100 may include any desired number and arrangement of dies 114. While FIG. 1 illustrates die 114-1 as a double-sided die and dies 114-2 and 114-3 as single-sided dies, dies 114-2 and 114-3 may be double-sided dies, and dies 114 may be single-pitch or mixed-pitch dies. In some embodiments, additional components may be disposed on the top surface of dies 114-2 and / or 114-3. In this context, a double-sided die refers to a die having connections on both surfaces. In some embodiments, a double-sided die may include TSVs for forming connections on both surfaces. The active surface of a double-sided die, which is the surface containing one or more active devices and the majority of the interconnects, may face either direction, depending on design and electrical requirements.

[0049] Many of the elements of the microelectronic assembly 100 of FIG. 1 are included in other of the accompanying drawings; when describing these drawings, the description of these elements will not be repeated, and any of these elements may take any of the forms disclosed herein. Additionally, while various elements are shown in FIG. 1 as being included in the microelectronic assembly 100, in various embodiments, some of these elements may not be included. For example, in various embodiments, additional layer 111, underfill material 127, and package substrate 102 may not be present in the microelectronic assembly 100. In some embodiments, individual ones of the microelectronic assemblies 100 disclosed herein may function as a system-in-package (SiP) with multiple dies 114 having different functions included therein. In such embodiments, the microelectronic assembly 100 may be referred to as a SiP.

[0050] FIG. 2 is a schematic cross-sectional view of another exemplary microelectronic assembly 100 according to some embodiments of the present disclosure. The configuration of the embodiment shown in this figure is similar to that of FIG. 1, except for differences that will be further described. Instead of including a glass core 110 as part of the substrate 107 as shown in FIG. 1, the microelectronic assembly 100 of FIG. 2 includes the glass core 110 alone, and one or more dies 114 may be bonded to the glass core 110. In FIG. 2, a multi-layer die subassembly 104 includes the glass core 110 and multiple dies 114 described above. The multi-layer die subassembly 104 may have a first surface 160-1 (e.g., a bottom surface) and an opposing second surface 160-2 (e.g., a top surface). The glass core 110 may provide mechanical stability to the multi-layer die subassembly 104 and / or the microelectronic assembly 100 of FIG. 2, may reduce warpage, and may provide a more robust surface for attaching the multi-layer die subassembly 104 to a package substrate 102 or other substrate (e.g., an interposer or circuit board).

[0051] The glass core 110 may include a cavity 129 having an opening facing the second surface 160-2, and the die 114-1 may be fully or at least partially nested within the cavity 129. As shown in FIG. 2 , in the case where the die 114-1 is fully nested within the cavity 129, the top surface of the die 114-1 may be flush with or below the top surface of the glass core 110. In the case where the die 114-1 is partially nested within the cavity 129, the top surface of the die 114-1 may extend above the top surface of the glass core 110. The cavity 129 may be at least partially filled with the dielectric material 112A or 112B described above. The die 114-1 may be attached to the bottom surface of the cavity 129 by a die attach film (DAF) 132. DAF 132 may be any suitable material, including a non-conductive adhesive, a die attach film, a B-stage underfill, or a polymer film with adhesive properties. DAF 132 may have any suitable dimensions, for example, in some embodiments, DAF 132 may have a thickness (e.g., height or z-height) of between 5 microns and 10 microns.

[0052] The die 114-1 may be coupled to the dies 114-2, 114-3 in layers above the die 114-1 through a DTD interconnect 130. The DTD interconnect 130 may be disposed between some of the conductive contacts 122 at the bottom of the dies 114-2, 114-3 and some of the conductive contacts 124 at the top of the die 114-1. Some other conductive contacts 122 at the bottom of the dies 114-2 and / or 114-3 may further couple one or more of the dies 114-2, 114-3 to the glass core 110 by a glass core-to-die (GCTD) interconnect 142. The GCTD interconnect 142 may be disposed between some of the conductive contacts 122 at the bottom of the dies 114-2, 114-3 and some of the conductive contacts 128 at the top of the glass core 110. The GCTD interconnect 142 may be similar to the DTS interconnect 140 described above. In some embodiments, underfill material 127 may extend between different ones of dies 114 around associated DTD interconnects 130 and / or GCTD interconnects 142. In some embodiments, die 114-2 and / or die 114-3 may be embedded in insulating material 133. In some embodiments, the overall thickness (e.g., z-height) of insulating material 133 may be between 200 microns and 800 microns (e.g., substantially equal to the thickness of die 114-2 or 114-3 and underfill material 127). In some embodiments, insulating material 133 may form multiple layers (e.g., a dielectric material formed in multiple layers, as known in the art) and may embed one or more dies 114 in the layers. In some embodiments, the insulating material 133 may be a dielectric material, such as an organic dielectric material, a flame-retardant grade 4 material (FR-4), a BT resin, a polyimide material, a glass-reinforced epoxy matrix material, or low-k and ultra-low-k dielectrics (e.g., carbon-doped dielectrics, fluorine-doped dielectric porous dielectrics, and organic polymer dielectrics). In some embodiments, the insulating material 133 may be a molding material, such as an organic polymer containing inorganic silica particles.

[0053] 2, the glass core 110 may further include a conductive contact 126 at the bottom of the glass core 110, and the TGVs 115 may extend between and electrically couple the conductive contact 126 at the bottom of the glass core 110 and the conductive contact 128 at the top of the glass core 110. The conductive contacts 126, 128 may be similar to other conductive contacts disclosed herein (e.g., conductive contacts 122, 124, 144, and / or 146) and may include, for example, bond pads, solder bumps, conductive posts, or any other suitable conductive contacts. As shown in FIG. 2, in some embodiments, at least some of the TGVs 115 may have an hourglass shape. For example, at least some of the TGVs 115 may have a first width at a first surface of the glass core 110 (e.g., at a bottom surface of the glass core 110), a second width at a second surface of the glass core 110 (e.g., at a top surface of the glass core 110), and a third width between the first and second surfaces of the glass core 110, where the third width is smaller than the first and second widths.

[0054] The dies 114-2, 114-3 may be electrically coupled to the package substrate 102 through TGVs 115 and glass core-package substrate (GCTPS) interconnects 152, which may be power supply interconnects or high-speed signal interconnects. The GCTPS interconnects 152 may be similar to the STPS interconnects 150 described above. The top surface of the package substrate 102 may include a set of conductive contacts 146, the multi-layer die subassembly 104 may include a set of conductive contacts 126 on a first surface 160-1, and the GCTPS interconnects 152 may be between and couple corresponding ones of the conductive contacts 126. In some embodiments, an underfill material 127 may extend between the glass core 110 and the package substrate 102 around associated GCTPS interconnects 152.

[0055] A glass core 110 included in the microelectronic assembly 100 described with reference to FIG. 1 or FIG. 2, or included in any other microelectronic assembly or device, may be subjected to TGV stress prior to inclusion in the microelectronic assembly 100. For example, FIG. 3 illustrates surfaces of the glass core 110 from which TGV stress may initiate, according to some embodiments of the present disclosure. As shown in FIG. 3, when the glass core 110 is included in the microelectronic assembly 100, the glass core 110 may have a first face 190-1, e.g., a bottom and a top face, and an opposing second face 190-2 (the first and second faces 190-1, 190-2 may both be referred to as "faces 190"). The glass core 110 may also include a side face 190-3, which may be referred to as an edge or sidewall of the glass core 110, i.e., a surface extending between the first face 190-1 and the second face 190-2. 3, a TGV aperture 192 may be formed in glass core 110, extending between first face 190-1 and second face 190-2. Sidewall 190-4, in turn, may refer to one or more sidewalls of TGV aperture 192. If a conductive material is deposited in TGV aperture 192, TGV stress may initiate from sidewall 190-4 due to a CTE mismatch between the glass material of glass core 110 and the conductive material in TGV aperture 192.

[0056] Prior to including the glass core 110 in the microelectronic assembly 100, one or more techniques for TGV stress relief described herein may be applied to reduce TGV stresses in the sidewall 190-4. In particular, various techniques for TGV stress relief are based on implementing conductive vias (e.g., TGVs 115) in the glass core as conductive vias with sealing liners. To that end, three different manufacturing methods for providing conductive vias with sealing liners are described herein, as shown in FIGS. 5, 7, and 9. As a result of performing the methods of FIGS. 5, 7, and 9, microelectronic assemblies 400A, 400B, and 400C having different arrangements of sealing liners may be realized, as shown in FIGS. 4A, 4B, and 4C, respectively. Each of the microelectronic assemblies 400A through 400C may be an example of a portion of any of the microelectronic assemblies 100 described herein. 4A, 4B, and 4C show side cross-sectional views (e.g., views of the yz plane of the exemplary coordinate system 105 described herein) of a portion of a glass core 110 in which three conductive vias with sealing liners are fabricated using the metallization processes of methods 500, 700, and 900, respectively.

[0057] 4A-4C each show glass core 110 having three TGVs 415 extending between first and second faces 190-1, 190-2, each TGV 415 including a TGV aperture 420, a liner material 422 on the sidewalls of the TGV aperture 420, a seed material 424 above the liner material 422, and a conductive filler material 426 filling the remaining space of the TGV aperture 420, with conductive contacts 428 provided at both ends of the TGV 415. Each of FIGS. 4A-4C further show an encapsulant 430 configured to seal the liner material 422 within the TGV 415; for example, the glass core 110, the conductive material within the TGV apertures (e.g., the seed material 424 and the conductive filler material 426), and the encapsulant 430 may completely surround the liner material 422 to reduce or eliminate oxidation of the liner material 422. Thus, due to the presence of the sealant 430 described herein, the liner material 422 may be referred to as the "sealing liner" of the TGV 415. Figures 4A-4C further show an additional layer 432 on the opposing surface 190 of the glass core 110.

[0058] While the TGVs 415 are shown in this figure as extending throughout the thickness of the glass core 110, in other embodiments, any of the TGVs 415 may be blind vias, in which case the encapsulant 430 would be provided only over one face 190 of the glass core 110, the face from which the blind via originates. Additionally, while FIGS. 4A-4C show an additional layer 432 on both faces 190-1 and 190-2 of the glass core 110, in some embodiments, the additional layer 432 may be absent from the first face 190-1, the second face 190-2, or both faces 190-1 and 190-2. Furthermore, although three TGVs 415 are shown in this figure, in other embodiments, the microelectronic assembly 400-400C may include any number of one or more TGVs 415.

[0059] 4A-4C differ in how the encapsulant 430 is implemented relative to the glass core 110. In particular, in the microelectronic assembly 400A shown in FIG. 4A, the encapsulant 430 may be in contact with one or more portions of the first surface 190-1 and / or one or more portions of the second surface 190-2 of the glass core 110. As used herein, unless otherwise specified, a statement that element A is "in contact" with element B includes element A being in direct physical contact with element B. 4A , in the microelectronic assembly 400B shown in FIG. 4B , the encapsulant 430 does not contact any portion of the first face 190-1 or the second face 190-2 of the glass core 110 because, for example, for the first face 190-1, a buffer layer 434 is provided over these faces, such that the buffer layer 434 is between the first face 190-1 and the encapsulant 430, e.g., between the liner material 422 over the first face 190-1 and the encapsulant 430. In the microelectronic assembly 400C shown in FIG. 4C , two of the layers of the encapsulant 430 may be provided, one layer as shown in FIG. 4B and the other layer of the encapsulant 430 between the buffer layer 434 and the first face 190-1, e.g., between the buffer layer 434 and the liner material 422 over the first face 190-1.

[0060] Referring to details of how the TGV 415 with the sealing liner of Figures 4A-4C may be manufactured, Figures 5, 7, and 9 are flow diagrams of methods 500, 700, and 900, respectively, for providing a glass core with a sealing liner, according to various embodiments. Figures 6A-6F provide side cross-sectional views at various stages in the manufacture of an exemplary glass core with a sealing liner according to method 500 of Figure 5, according to some embodiments. Figures 8A-8C provide side cross-sectional views at various stages in the manufacture of an exemplary glass core with a sealing liner according to method 700 of Figure 7, according to some embodiments. Figures 10A-10C provide side cross-sectional views at various stages in the manufacture of an exemplary glass core with a sealing liner according to method 900 of Figure 9, according to some embodiments. Similar to Figures 4A to 4C, Figures 6A to 6F, Figures 8A to 8C, and Figures 10A to 10C each show a side cross-sectional view (e.g., a view of the yz plane of the exemplary coordinate system 105 described herein) of a portion of a glass core 110 in which three conductive vias with sealing liners are fabricated using the metallization processes of methods 500, 700, and 900.

[0061] Although the operations of methods 500, 700, and 900 are each shown once and in a particular order, these operations may be performed in any suitable order and may be repeated as necessary. For example, one or more operations may be performed in parallel to substantially simultaneously produce multiple conductive vias with sealing liners. In another example, one or more operations may be performed in parallel to substantially simultaneously produce multiple conductive vias with sealing liners in multiple glass cores.

[0062] 5, 7, and 9, such as various cleaning or planarization operations as are known in the art. For example, in some embodiments, the glass core 110 and various other material layers subsequently deposited thereon may be cleaned before, after, or during any of the processes of methods 500, 700, and 900 described herein to remove, for example, oxides, surface-bound organic and metallic contaminants, and sub-surface contamination. In some embodiments, cleaning may be performed, for example, with a chemical solution (such as peroxide) and / or with ultraviolet (UV) radiation in combination with ozone, and / or by oxidizing the surface (e.g., using thermal oxidation) and then removing the oxide (e.g., using hydrofluoric acid (HF)).

[0063] Method 500 may begin with process 502, which includes providing one or more TGV apertures within the glass core. Figure 6A illustrates an assembly 602 that may be an exemplary result of process 502, showing glass core 110 with an internal TGV aperture 420. Again, while Figure 6A, as well as Figures 6B-6F, 8A-8C, and 10A-10C, illustrate TGV apertures 420 within glass core 110 extending between first and second faces 190-1, 190-2 of glass core 110, the description provided herein is applicable to blind apertures, e.g., apertures that begin at one of faces 190 and extend toward, but do not reach, the other of faces 190. In some embodiments, TGV openings 420 can be formed in glass core 110 using any suitable subtractive technique, such as direct laser drilling or laser-induced etching processes, possibly in combination with any suitable patterning technique, such as photolithography or electron beam (e-beam) patterning. In other embodiments, TGV openings 420 can be formed during the manufacture of glass core 110 itself, for example, when molten glass is filled into a mold having spaces for future TGV openings 420.

[0064] Next, method 500 may include process 504, in which TGV opening 420 of process 502 may be lined with a liner material. To that end, a layer of liner material may be deposited on the sidewalls of TGV opening 420 of process 502, and in some cases, also on the bottom of TGV opening 420 for TGV openings 420 that may be implemented as blind openings. FIG. 6B illustrates assembly 604, which may be an exemplary result of process 504, showing glass core 110 with TGV opening 420 lined with a layer of liner material 422, thus creating a lined TGV opening. In various embodiments, liner material 422 may be deposited using any suitable deposition technique, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). In some embodiments, in addition to being placed as a liner within TGV opening 420, liner material 422 may also be deposited over first surface 190-1, second surface 190-2, or both surfaces 190-1 and 190-2, depending on how liner material 422 is deposited. In such embodiments, liner material 422 deposited over first surface 190-1 and / or second surface 190-2 may be materially continuous with liner material 422 on the sidewalls of TGV opening 420. In some embodiments, the portion of liner material 422 on the sidewalls of TGV opening 420 may be in contact with the sidewalls of TGV opening 420 (e.g., in contact with glass core 110 at the sidewalls of TGV opening 420). In some embodiments, the thickness of liner material 422 may be between about 200 nanometers and about 10 microns, e.g., between about 200 nanometers and about 5 microns, or between about 500 nanometers and about 1 micron. In some embodiments, the liner material 422 may be deposited as a conformal layer, ie, conformal to the topography of the underlying surface over which the liner material 422 is deposited.

[0065] Liner material 422 may include any suitable material capable of separating the glass material of glass core 110 at the sidewalls of TGV opening 420 and the conductive material that will be later deposited in TGV opening 420. In some embodiments, liner material 422 may include a material having a relatively low modulus, e.g., a Young's modulus below about 30 GPa, e.g., below about 10 GPa, e.g., between about 3 GPa and 30 GPa, or between about 1 GPa and 30 GPa, where Young's modulus may be defined as the ratio of stress to strain in a material that has undergone deformation. In some embodiments, liner material 422 may include a material having a modulus (e.g., Young's modulus) less than that of glass core 110 and / or a modulus (e.g., Young's modulus) less than that of conductive fill material 426 that will be deposited in a later process. In some embodiments, the CTE of the liner material 422 may be less than the CTE of the conductive fill material 426, for example, less than about 17 ppm / K, or less than about 15 ppm / K or 10 ppm / K.

[0066] In some embodiments, the liner material 422 may include a polymeric material, such as an organic polymer. In other embodiments, the liner material 422 may include an organic material other than a polymer, such as a monomer or oligomer. In some embodiments, the liner material 422 may include a homopolymer, which is a polymer composed of repeating units of a single type of monomer. Simple signal chemistry organic liners, such as homopolymers, may be particularly advantageous for use as the liner material 422 because they may be relatively easy to manufacture and may be readily adopted for use as the liner material 422. In some embodiments, the liner material 422 may include a polyparaxylylene (also commonly referred to as "parylene"), such as Parylene N, Parylene C, Parylene D, or para-free (halogen-free). In other embodiments, the liner material 422 may include a heteropolymer, which is a polymer composed of repeating units of two or more types of monomers or oligomers. For example, the liner material 422 may include a heteropolymer such as polyester (PET), polyurethane (PU), polycarbonate (PC), or polyvinyl chloride (PVC).

[0067] In other embodiments, the liner material 422 may include a non-polymeric material, such as an inorganic non-polymeric material, hi some such embodiments, the liner material 422 may include an inorganic material, such as carbon-doped oxide (CDO), low modulus SiOx, silicon oxycarbide (SiOC), or other low-k dielectrics.

[0068] Method 500 may then proceed to process 506, where TGV metallization may be performed on assembly 604 having TGV opening 420 lined with liner material 422. FIG. 6C illustrates assembly 606, which may be an example result of process 506, showing that TGV metallization may include depositing a layer of seed material 424 to lining TGV opening 420 lined with liner material 422 and then at least partially filling the remaining space within TGV opening 420 with conductive fill material 426, thus creating a conductive via in the form of TGV 415. TGV 415 is an example of any one of the TGVs 115 described herein. Seed material 424 may include any suitable conductive material, e.g., a metal, metal alloy, or combination of metals, e.g., a low-resistivity metal such as copper, that may be deposited in a thin layer on the substantially non-conductive surfaces (e.g., sidewalls) of TGV opening 420 lined with liner material 422. The seed material 424 provides a conductive surface for uniform and controlled deposition of conductive fill material in subsequent stages of TGV metallization in process 506. For example, the seed material 424 can serve as a foundation or base for subsequent electroplating of a thicker layer of metal. In some embodiments, the seed material 424 can include one or more metals, such as copper, ruthenium, nickel, gold, palladium, platinum, or silver. In various embodiments, the layer thickness of the seed material 424 can be, for example, between about 5 nanometers and 20 microns, e.g., between about 10 nanometers and 15 microns, or between about 10 nanometers and 1 micron, measured in a direction perpendicular to the sidewall of the TGV opening 420. In various embodiments, the seed material 424 can be deposited using any suitable deposition technique, such as CVD, ALD, or PVD. In some embodiments, the seed material 424 can be deposited as a conformal layer. In some embodiments, the seed material 424 can include two or more layers of different conductive materials sequentially deposited on the liner material 422.For example, the seed material 424 may include a layer of a first material deposited on the liner material 422 and then a layer of a second material deposited on the first material. The first material may be a conductive material that has good adhesion properties for adhesion between the first material and the liner material 422, and in some cases, for adhesion between the first material and the second material. The second material may be a conductive material that can protect the first material from oxidation before and / or during deposition of a conductive filler material in a subsequent process. For example, the first layer of the seed material 424 may include titanium, while the second layer of the seed material 424 may include copper. In other embodiments, the seed material 424 may include a single layer of a conductive material, such as a layer of copper or a layer of ruthenium. The conductive fill material 426 may include any suitable conductive material, such as any of the materials described with reference to the seed material 424. In some embodiments, the material compositions of the seed material 424 and the conductive fill material 426 may be substantially the same, e.g., both may be or may include copper. In other embodiments, the material compositions of the seed material 424 and the conductive fill material 426 may be different. The conductive fill material 426 may be deposited using any suitable deposition technique, such as electroplating, ALD, CVD, or PVD.

[0069] Next, method 500 may include process 508, in which conductive contacts may be formed at the ends of TGV aperture 420 of assembly 606. FIG. 6D illustrates assembly 608, which may be an example result of process 508, showing glass core 110 with conductive contacts 428 at both ends of TGV aperture 420. In some embodiments, conductive contacts 428 may be fabricated by removing remnants of the covering film of conductive fill material 426 that may be deposited above surface 190 in process 506, using, for example, any suitable etching process, possibly in combination with any suitable patterning technique, such as photolithography or electron beam patterning.

[0070] Method 500 may further include process 510, in which the seed material 424 and liner material 422 exposed by the removal of conductive fill material 426 to form conductive contacts 428 in process 508 may also be removed. FIG. 6E shows an assembly 610 that may be an example result of process 510, illustrating that the seed material 424 and liner material 422 on portions of face 190 outside the footprint of conductive contacts 428 may be removed to expose the surface of glass core 110. In some embodiments, process 510 may include any suitable etching process, such as a two-step etching process in which a first set of one or more etchants is used to remove seed material 424, thus exposing liner material 422, and then a second set of one or more etchants is used to remove liner material 422. In other embodiments, the conductive contacts 428 may be provided using any other suitable technique, such as using an additive technique, to add the conductive contacts 428, so long as the conductive fill material 426 of the TGVs 415 can be brought into conductive contact with the conductive material of the conductive contacts 428. The description provided with respect to the conductive contacts (e.g., conductive contacts 122) of the microelectronic assembly 100 shown in Figures 1 and 2 is applicable to the conductive contacts 428 and therefore will not be repeated for the sake of brevity.

[0071] Next, the method 500 may include process 512, in which an encapsulant is deposited to encapsulate the liner material 422. FIG. 6F illustrates an assembly 612 that may be an example result of process 512, showing a layer of encapsulant 430 deposited over the top and bottom surfaces of the assembly 610 to enclose the liner material 422 within the TGV 415. The encapsulant 430 may be deposited using any suitable deposition technique, such as electroplating, ALD, CVD, or PVD. In some embodiments, the thickness of the encapsulant 430 may be between about 100 nanometers and about 10 microns, e.g., between about 200 nanometers and about 5 microns, or between about 250 nanometers and about 1 micron. In some embodiments, the encapsulant 430 may be deposited as a conformal layer.

[0072] In some embodiments, the encapsulant 430 may include any suitable material that can reduce or eliminate oxidation of the liner material 422. For example, in some such embodiments, the encapsulant 430 may include an inorganic material, such as silicon nitride. In other such embodiments, the encapsulant 430 may include other nitrides or other materials that do not readily oxidize and can withstand subsequent processes that may be applied to the assembly 612. In other embodiments, the encapsulant 430 may include any suitable material that can reduce or eliminate crystallization of the liner material 422. For example, in some such embodiments, the encapsulant 430 may include an inorganic material, such as silicon oxide. In other such embodiments, the encapsulant 430 may include other oxides or other materials that can reduce or eliminate crystallization of the liner material 422 and can withstand subsequent processes that may be applied to the assembly 612. The choice of material used as the encapsulant 430 may depend on the particular application, environmental conditions, and choice of liner material 422 to be sealed. In various embodiments, the sealant 430 may include one or more of silicone, polyurethane, an acrylic material, fluorosilicone, butyl rubber, epoxy, neoprene, or polyvinyl chloride.

[0073] Method 500 may further include process 514, in which an additional layer is provided above first surface 190-1 and / or above second surface 190-2 of glass core 110 of assembly 612. FIG. 4A, discussed above, illustrates an exemplary result of process 514, showing additional layer 432 provided above first surface 190-1 and above second surface 190-2 of glass core 110. In some embodiments, additional layer 432 may include a build-up layer, such as those described with reference to FIGS. 1-2. In some embodiments, additional layer 432 may include ABF. In some embodiments, encapsulant 430 may be a material capable of promoting adhesion of additional layer 432 to the top and / or bottom surfaces of assembly 612.

[0074] Performing method 500 may result in several features of use of method 500. One such feature may be that in some embodiments, a portion of encapsulant 430 may be in contact with a portion of first surface 190-1 of glass core 110, e.g., a portion of encapsulant 430 that is not on conductive contact 428, and / or a portion of encapsulant 430 may be in contact with a portion of second surface 190-2 of glass core 110. An example of this may be seen in dashed outline 620 shown in FIG. 6F. Another feature of use of method 500 may be that a portion of liner material 422 above a given surface 190 of glass core 110 may be in contact with a portion of encapsulant 430. An example of this may be seen in dashed outline 622 shown in FIG. 6F. Similarly, as can also be seen within dashed outline 622 in FIG. 6F , a portion of the seed material 424 above a given surface 190 of the glass core 110 may be in contact with a portion of the encapsulant 430. Yet another feature of the use of method 500 can be that a portion of the liner material above a given surface 190 of the glass core 110 may be in contact with a portion of that surface 190 of the glass core 110. An example of this can be seen within dashed outline 624 shown in FIG. 6F . Because in method 500, the encapsulant 430 is deposited after the formation of the conductive contacts 428, in some embodiments, a portion of the encapsulant 430 may be on the sidewalls of the conductive contacts 428, for example, as shown within dashed outline 626 shown in FIG. 6F , while another portion of the encapsulant 430 may be on the top surface of the conductive contacts 428, for example, as shown within dashed outline 628 shown in FIG. 6F .

[0075] Referring to a second method of providing a glass core with a sealing liner, method 700 shown in FIG. 7 may include processes 702, 704, and 706, which may be substantially the same as processes 502, 504, and 506, respectively, described with reference to method 500. For brevity, the description of these processes will not be repeated, and their illustrations are not shown in FIGS. 8A-8C . After process 706, method 700 may include process 708, in which the TGV metal deposited above face 190 during the TGV metallization of process 706 may be planarized, and a buffer layer may be provided above first face 190-1 and / or second face 190-2. FIG. 8A shows assembly 808, which may be an exemplary result of process 708, showing buffer layer 434 provided above first face 190-1 and another buffer layer 434 provided above second face 190-2. The use of a buffer layer 434 above one or more of the surfaces 190 of the glass core 110 can be advantageous for providing isolation between the conductive contacts 428 and the glass core 110 in an attempt to minimize CTE mismatch issues. In some embodiments, the buffer layer 434 can include an insulator material such as ABF, polyimide, or any other suitable dielectric material that can reduce stresses generated from CTE mismatch between the glass core and the conductive contacts, which are typically made of copper. These materials have a modulus much lower than copper, typically less than 60 GPa. In some embodiments, the thickness of the buffer layer 434 can be between about 5 microns and about 50 microns, e.g., between about 5 microns and about 35 microns or between about 15 microns and about 35 microns.

[0076] Next, method 700 may include process 710, in which one or more openings may be formed in buffer layer 434 to expose conductive fill material 426 in one or more TGVs 415 of assembly 808. FIG. 8B shows assembly 810, which may be an example result of process 710, showing openings 438 in buffer layer 434 on either side of TGV opening 420. In some embodiments, openings 438 may be formed using any suitable etching process, possibly in combination with any suitable patterning technique, such as photolithography or electron beam patterning.

[0077] Method 700 may further include process 712, in which conductive contacts are formed at the ends of the openings 438 of assembly 808 and an encapsulant is deposited to encapsulate the liner material 422. FIG. 8C illustrates assembly 812, which may be an exemplary result of process 712, showing glass core 110 with conductive contacts 428 at either end of opening 438 in buffer layer 434 and further illustrating a layer of encapsulant 430 deposited over the top and bottom surfaces of assembly 812 after the conductive contacts 428 are formed surrounding the liner material 422 in TGVs 415. For example, the conductive contacts 428 may be formed in process 712 using any suitable technique known in the art, so long as the conductive material of the conductive contacts 428 is in conductive contact with the conductive fill material 426 of the TGVs 415 by filling the openings 438 with a conductive material. The description of encapsulant 430 provided with reference to method 500 is applicable to the encapsulant 430 deposited in process 712 and, therefore, will not be repeated for brevity.

[0078] Method 700 may further include process 714, in which an additional layer is provided above first side 190-1 and / or above second side 190-2 of glass core 110 of assembly 812. FIG. 4B, discussed above, illustrates an exemplary result of process 714, showing additional layer 432 provided above first side 190-1 and above second side 190-2 of glass core 110. The description of additional layer 432 provided with reference to method 500 is applicable to additional layer 432 provided in process 714 and therefore will not be repeated for the sake of brevity.

[0079] Similar to method 500, performing method 700 may result in several features of use of method 700. One such feature may be that, in some embodiments, a portion of buffer layer 434 may be between a given surface 190 of glass core 110 and liner material 422 above encapsulant 430. An example of this may be seen in dashed outline 820 shown in FIG. 8C . Another feature of use of method 700 may be that a portion of buffer layer 434 may be in contact with a portion of conductive contact 428. An example of this may be seen in dashed outline 822 shown in FIG. 8C . Yet another feature of use of method 700 may be that a portion of encapsulant 430 may be in contact with a portion of buffer layer 434. An example of this may be seen in dashed outline 824 shown in FIG. 8C . In method 700, because the encapsulant 430 is deposited after the formation of the conductive contacts 428, similar to method 500, in some embodiments, a portion of the encapsulant 430 may be on the sidewalls of the conductive contacts 428, for example, as shown within dashed outline 826 in FIG. 8C, while another portion of the encapsulant 430 may be on the top surface of the conductive contacts 428, for example, as shown within dashed outline 828 in FIG. 8C.

[0080] Referring to a third method of providing a glass core with a sealing liner, method 900 shown in FIG. 9 may include processes 902, 904, and 906, which may be substantially the same as processes 502, 504, and 506, respectively, described with reference to method 500. For brevity, the description of these processes will not be repeated, and their illustrations are not shown in FIGS. 10A to 10C . After process 906, method 900 may include process 908, in which the TGV metal deposited above face 190 during the TGV metallization of process 906 may be planarized, and a first layer of encapsulant may be provided above first face 190-1 and / or second face 190-2, followed by providing a buffer layer above the first encapsulant. 10A illustrates an assembly 1008 that may be an exemplary result of process 908, showing encapsulant 430 deposited over first surface 190-1 and second surface 190-2, followed by a buffer layer 434 over encapsulant 430. The description of buffer layer 434 provided with reference to method 700 is applicable to buffer layer 434 provided in process 912 and therefore will not be repeated for the sake of brevity.

[0081] Next, the method 900 may include a process 910 in which one or more openings may be formed in the buffer layer 434 and the first layer of the encapsulant 430 to expose the conductive fill material 426 in one or more TGVs 415 of the assembly 1008. FIG. 10B shows an assembly 1010 that may be an example result of the process 910, showing openings 440 in the buffer layer 434 and the first layer of the encapsulant 430 on either side of the TGV opening 420. In some embodiments, the openings 440 may be formed using any suitable etching process, possibly in combination with any suitable patterning technique, such as photolithography or electron beam patterning.

[0082] Method 900 may further include process 912, in which conductive contacts are formed at the ends of the openings 440 of assembly 1008 and a second layer of encapsulant is deposited to encapsulate liner material 422. FIG. 10C illustrates assembly 1012, which may be an exemplary result of process 912, showing glass core 110 with conductive contacts 428 at either end of opening 440 in buffer layer 434, and further illustrating a second layer of encapsulant 430 deposited over the top and bottom surfaces of assembly 1012 after conductive contacts 428 are formed surrounding liner material 422 in TGVs 415. For example, conductive contacts 428 may be formed in process 912 using any suitable technique known in the art, so long as the conductive material of conductive contacts 428 is in conductive contact with conductive fill material 426 of TGVs 415, for example, by filling opening 440 with a conductive material. The description of the encapsulant 430 provided with reference to method 500 is applicable to the first layer of encapsulant 430 deposited in process 910 and the second layer of encapsulant 430 deposited in process 912, and therefore will not be repeated for the sake of brevity. In some embodiments, the material composition of the first layer of encapsulant 430 (i.e., that deposited in process 910) can be different from the material composition of the second layer of encapsulant 430 (i.e., that deposited in process 912). In other embodiments, these material compositions can be substantially the same.

[0083] Method 900 may further include process 914, in which an additional layer is provided above first side 190-1 and / or above second side 190-2 of glass core 110 of assembly 1012. FIG. 4C, discussed above, illustrates an exemplary result of process 914, showing additional layer 432 provided above first side 190-1 and above second side 190-2 of glass core 110. The description of additional layer 432 provided with reference to method 500 is applicable to additional layer 432 provided in process 914 and therefore will not be repeated for the sake of brevity.

[0084] Similar to methods 500 and 700, performing method 900 may result in several features of use of method 900. Some such features are the same as those shown within dashed outlines 822, 824, 826, and 828 described with reference to FIG. 8C . Accordingly, dashed outlines 822, 824, 826, and 828 are also shown in FIG. 10C . Another feature not present in FIG. 8C is the presence of encapsulant 430 (the first layer of encapsulant 430 deposited in process 910) between buffer layer 434 and liner material 422 above given surface 190 of glass core 110. An example of this can be seen within dashed outline 1020 shown in FIG. 10C . Similarly, one other feature is that a portion of buffer layer 434 may be in contact with a portion of the first layer of encapsulant 430, as also seen within dashed outline 1020 shown in FIG. 10C . A related feature of using method 900 may be that a portion of buffer layer 434 may be between first layer encapsulant 430 and second layer encapsulant 430. An example of this can be seen within dashed outline 1022 shown in Figure 10C.

[0085] The various embodiments of the conductive vias with encapsulating liners described above can advantageously be readily fabricated in parallel with conventional fabrication techniques for glass core substrates. The various arrangements of microelectronic assembly 100 and glass core 110 shown in FIGS. 1 through 10C do not represent an exhaustive set of microelectronic assemblies and glass cores in which one or more conductive vias with encapsulating liners described herein may be implemented, but merely provide some illustrative examples. Notably, the number and locations of the various elements shown in FIGS. 1 through 10C are purely illustrative; in various other embodiments, other numbers of these elements in other locations relative to one another may be used in accordance with the general architectural considerations described herein. For example, although not specifically shown in the figures, in some embodiments, microelectronic assembly 100 may include a redistribution layer (RDL) between any pair of layers shown in FIGS. 1 and 2, the RDL including multiple interconnect structures (e.g., conductive lines and conductive vias) to support signal and / or power transfer between components. In another example, although also not specifically shown in this figure, in some embodiments, the package substrate 102 of the microelectronic assembly 100 may include one or more recesses. In such embodiments, the bottom of the recess in the package substrate 102 may be provided by the solid material of the package substrate 102. The recess may be formed in the package substrate 102 in any suitable manner (e.g., via 3D printing, laser cutting, or drilling a recess into an existing package substrate, etc.). At least a portion of the substrate 107 or glass core 110 may be located above or at least partially within such a recess. In yet another example, features of any one of FIGS. 1 through 10C may be combined with features of any other one of FIGS. 1 through 10C. For example, in some embodiments, some portions of the glass core 110 may include one or more conductive vias with a sealing liner fabricated using method 500, while other portions of the glass core 110 may include one or more conductive vias with a sealing liner fabricated using method 700 and / or method 900.

[0086] The microelectronic assemblies 100 and / or glass cores 110 disclosed herein, particularly glass cores 110 having one or more conductive vias with sealing liners as described herein, can be included within any suitable electronic component. Figures 11 through 14 show various examples of devices that may include or be included in any of the microelectronic assemblies 100 and / or glass cores 110 disclosed herein.

[0087] FIG. 11 is a top view of a wafer 1500 and a die 1502 that may be included in any of the microelectronic assemblies 100 described herein. For example, the die 1502 may be any of the die 114 described herein. The wafer 1500 may be composed of a semiconductor material and may include one or more die 1502 having multiple IC structures formed on the surface of the wafer 1500. Each of the die 1502 may be a repeating unit of a semiconductor product including any suitable IC. After fabrication of the semiconductor product is complete, the wafer 1500 may undergo a singulation process in which the die 1502 are separated from one another to provide individual "chips" of the semiconductor product. The die 1502 may include one or more transistors (e.g., some of the transistors 1640 in FIG. 12 , described below) and / or support circuitry for transferring electrical signals to the transistors and any other IC components. In some embodiments, wafer 1500 or die 1502 may include memory devices (e.g., random-access memory (RAM) devices such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM®) devices, conductive-bridging RAM (CBRAM) devices, etc.), logic devices (e.g., AND gates, gates, NAND gates, or NOR gates), or any other suitable circuit elements. Multiple of these devices may be combined on a single die 1502. For example, a memory array formed by multiple memory devices may be formed on the same die 1502 as a processing device (e.g., processing device 1802 of FIG. 14 ) or other logic configured to store information in the memory devices or execute instructions stored in the memory array.

[0088] FIG. 12 is a cross-sectional side view of an IC device 1600 that may be included in any of the microelectronic assemblies 100 described herein. For example, the IC device 1600 may be provided on / within any of the die 114 described herein. The IC device 1600 may be formed on a substrate 1602 (e.g., wafer 1500 of FIG. 11) or included in a die (e.g., die 1502 of FIG. 11). The substrate 1602 may be a semiconductor substrate composed of a semiconductor material system, including, for example, an n-type or p-type material system (or a combination of both). The substrate 1602 may include, for example, a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the substrate 1602 may be formed using alternative materials, which may or may not be combined with silicon, including, but not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Additional materials classified as III-V materials (i.e., materials from groups III and V of the periodic system of elements), II-VI (i.e., materials from groups II and IV of the periodic system of elements), or group IV materials (i.e., materials from group IV of the periodic system of elements) may also be used to form substrate 1602. A few examples of materials from which substrate 1602 may be formed are described here, although any material that can serve as the foundation of IC device 1600 may be used. Substrate 1602 may be part of a singulated die (e.g., die 1502 of FIG. 11 ) or a wafer (e.g., wafer 1500 of FIG. 11 ).

[0089] The IC device 1600 may include one or more device layers 1604 disposed on a substrate 1602. The device layer 1604 may include features of one or more transistors 1640 (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)) formed on the substrate 1602. The device layer 1604 may include, for example, one or more source and / or drain (S / D) regions 1620, a gate 1622 for controlling the flow of current in the transistor 1640 between the S / D regions 1620, and one or more S / D contacts 1624 for transferring electrical signals to and from the S / D regions 1620. The transistor 1640 may include additional features not shown for clarity, such as device isolation regions, gate contacts, etc. The transistor 1640 is not limited to the type and configuration shown in FIG. 12 and may include a wide variety of other types and configurations, such as, for example, planar transistors, non-planar transistors, or a combination of both. Planar transistors may include bipolar junction transistors (BJTs), heterojunction bipolar transistors (HBTs), or high electron mobility transistors (HEMTs). Non-planar transistors may include FinFET transistors, such as double-gate or tri-gate transistors, and wrap-around or all-around gate transistors, such as nanoribbon and nanowire transistors.

[0090] Each transistor 1640 may include a gate 1622 formed of at least two layers, a gate dielectric, and a gate electrode. The gate dielectric may include one layer or a stack of layers. One or more layers may include silicon oxide, silicon dioxide, silicon carbide, and / or high-k dielectric materials. The high-k dielectric materials may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be performed on the gate dielectric to improve the quality of the gate dielectric when high-k materials are used.

[0091] A gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether transistor 1640 is to be a p-type metal oxide semiconductor (PMOS) or n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode may consist of a stack of two or more metal layers, with one or more metal layers being work function metal layers and at least one metal layer being a filler metal layer. Additional metal layers, such as barrier layers, may be included for other purposes. For PMOS transistors, metals that may be used in the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals described below with reference to NMOS transistors (e.g., for work function tuning). For NMOS transistors, metals that may be used in the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals mentioned above with reference to PMOS transistors (e.g., for work function tuning).

[0092] In some embodiments, when viewed as a cross-section of transistor 1640 along the source-channel-drain direction, the gate electrode can comprise a U-shaped structure including a bottom portion substantially parallel to the surface of the substrate and two sidewall portions substantially perpendicular to the top surface of the substrate. In other embodiments, at least one of the metal layers forming the gate electrode can simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In other embodiments, the gate electrode can comprise a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode can comprise one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0093] In some embodiments, a pair of sidewall spacers may be formed on opposing sides of the gate stack to surround the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, or silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, multiple spacer pairs may be used; for example, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

[0094] The S / D regions 1620 may be formed in the substrate 1602 adjacent to the gate 1622 of each transistor 1640. The S / D regions 1620 may be formed using, for example, an implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion-implanted into the substrate 1602 to form the S / D regions 1620. An annealing process that activates the dopants and diffuses them further into the substrate 1602 may follow the ion-implantation process. In the latter process, the substrate 1602 may first be etched to form recesses at the locations of the S / D regions 1620. An epitaxial deposition process may then be performed to fill the recesses with the material used to fabricate the S / D regions 1620. In some implementations, the S / D regions 1620 may be fabricated using silicon alloys such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorus. In some embodiments, the S / D regions 1620 may be formed using one or more alternative semiconductor materials, such as germanium or III-V materials or alloys. In further embodiments, one or more layers of metal and / or metal alloys may be used to form the S / D regions 1620.

[0095] Electrical signals, such as power and / or input / output (I / O) signals, may be transferred to and / or from devices (e.g., transistor 1640) in device layer 1604 through one or more interconnect layers (shown in FIG. 12 as interconnect layers 1606, 1608, and 1610) disposed on device layer 1604. For example, conductive features (e.g., gate 1622 and S / D contacts 1624) in device layer 1604 may be electrically coupled to interconnect structures 1628 in interconnect layers 1606, 1608, and 1610. One or more interconnect layers 1606, 1608, and 1610 may form a metallization stack (also referred to as an “ILD stack”) 1619 of IC device 1600.

[0096] Interconnect structures 1628 may be arranged within interconnect layers 1606-1610 to transfer electrical signals according to a wide variety of designs (notably, such arrangements are not limited to the particular configuration of interconnect structures 1628 shown in Figure 12). Although a particular number of interconnect layers 1606, 1608, and 1610 are shown in Figure 12, embodiments of the present disclosure include IC devices having more or fewer interconnect layers than those shown.

[0097] In some embodiments, the interconnect structures 1628 may include lines 1628a and / or vias 1628b filled with a conductive material, such as a metal. The lines 1628a may be arranged to transfer electrical signals in a plane that is substantially parallel to the surface of the substrate 1602 on which the device layer 1604 is formed. For example, the lines 1628a may transfer electrical signals in a direction into and out of the page from the perspective of FIG. 12 . The vias 1628b may be arranged to transfer electrical signals in a plane that is substantially perpendicular to the surface of the substrate 1602 on which the device layer 1604 is formed. In some embodiments, the vias 1628b may electrically couple together the lines 1628a of different interconnect layers 1606, 1608, and 1610.

[0098] 12, the interconnect layers 1606, 1608, and 1610 may include a dielectric material 1626 disposed between interconnect structures 1628. In some embodiments, the dielectric material 1626 disposed between the interconnect structures 1628 in different ones of the interconnect layers 1606, 1608, and 1610 may have different compositions; in other embodiments, the composition of the dielectric material 1626 between different interconnect layers 1606, 1608, and 1610 may be the same.

[0099] A first interconnect layer 1606 may be formed over the device layer 1604. As shown, in some embodiments, the first interconnect layer 1606 may include lines 1628a and / or vias 1628b. The lines 1628a of the first interconnect layer 1606 may be coupled to contacts (e.g., S / D contacts 1624) of the device layer 1604.

[0100] A second interconnect layer 1608 may be formed over the first interconnect layer 1606. In some embodiments, the second interconnect layer 1608 may include vias 1628b for coupling lines 1628a of the second interconnect layer 1608 with lines 1628a of the first interconnect layer 1606. Although the lines 1628a and vias 1628b are structurally depicted as lines within each interconnect layer (e.g., within the second interconnect layer 1608) for clarity, in some embodiments, the lines 1628a and vias 1628b may be structurally and / or materially continuous (e.g., filled simultaneously during a dual damascene process).

[0101] The third interconnect layer 1610 (and additional interconnect layers, if desired) may be formed successively on the second interconnect layer 1608 according to techniques and configurations similar to those described in connection with the second interconnect layer 1608 or the first interconnect layer 1606. In some embodiments, interconnect layers "higher" in the metallization stack 1619 within the IC device 1600 (i.e., farther away from the device layer 1604) may be thicker.

[0102] The IC device 1600 may include a solder resist material 1634 (e.g., polyimide or a similar material) and one or more conductive contacts 1636 formed on the interconnect layers 1606, 1608, and 1610. In FIG. 12 , the conductive contacts 1636 are shown to take the form of bond pads. The conductive contacts 1636 may be electrically coupled to the interconnect structure 1628 and may be configured to transfer electrical signals of the transistor 1640 to other external devices. For example, solder bonds may be formed on one or more of the conductive contacts 1636 to mechanically and / or electrically couple a chip including the IC device 1600 to another component (e.g., a circuit board). The IC device 1600 may include additional or alternative structures for transferring electrical signals from the interconnect layers 1606, 1608, and 1610. For example, the conductive contacts 1636 may include other similar features (e.g., posts) that transfer electrical signals to external components.

[0103] 13 is a side cross-sectional view of an IC device assembly 1700 that may include a glass core with one or more encapsulant liners according to any of the embodiments disclosed herein. The IC device assembly 1700 includes multiple components disposed on a circuit board 1702 (which may be, for example, a motherboard). The IC device assembly 1700 includes components disposed on a first side 1740 of the circuit board 1702 and an opposing second side 1742 of the circuit board 1702; generally, components may be disposed on one or both sides 1740 and 1742. Any of the IC packages described below with reference to the IC device assembly 1700 may take the form of any of the microelectronic assembly 100 embodiments described above, and may, for example, include one or more microelectronic assemblies 100 described with reference to FIGS. 1 and 2 and / or may include one or more glass cores described with reference to FIGS. 3 through 10C.

[0104] In some embodiments, circuit board 1702 may be a PCB including multiple metal layers separated from one another by layers of dielectric material and electrically interconnected by conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to transfer electrical signals (optionally in conjunction with other metal layers) between components coupled to circuit board 1702. In other embodiments, circuit board 1702 may be a non-PCB substrate.

[0105] The IC device assembly 1700 illustrated in Figure 13 includes a package-on-interposer structure 1736 coupled to a first surface 1740 of a circuit board 1702 by a coupling component 1716. The coupling component 1716 may electrically and mechanically couple the package-on-interposer structure 1736 to the circuit board 1702 and may include solder balls (shown in Figure 13), male and female portions of a socket, adhesive, underfill material, and / or any other suitable electrical and / or mechanical coupling structure.

[0106] The package-on-interposer structure 1736 may include an IC package 1720 coupled to a package interposer 1704 by a coupling component 1718. The coupling component 1718 may take any suitable form for the application, such as those described above with reference to the coupling component 1716. While a single IC package 1720 is shown in FIG. 13 , multiple IC packages may be coupled to the package interposer 1704; indeed, additional interposers may be coupled to the package interposer 1704. The package interposer 1704 may provide an intervening substrate used to bridge the circuit board 1702 and the IC package 1720. The IC package 1720 may be or include, for example, a die (die 1502 in FIG. 5 ), an IC device (e.g., any of the IC devices described herein, or any combination of such IC devices), or any other suitable component. In general, the package interposer 1704 may spread connections to a wider pitch or reroute certain connections to different connections. For example, the package interposer 1704 may couple an IC package 1720 (e.g., a die) to a set of ball grid array (BGA) conductive contacts of the mating component 1716 for coupling to the circuit board 1702. In the embodiment shown in Figure 13, the IC package 1720 and the circuit board 1702 are attached to opposite sides of the package interposer 1704; in other embodiments, the IC package 1720 and the circuit board 1702 may be attached to the same side of the package interposer 1704. In some embodiments, three or more components may be interconnected by the package interposer 1704.

[0107] In some embodiments, the package interposer 1704 may be formed as a glass core with one or more encapsulant liners described herein, such as any embodiment of the glass core 110 described herein. In some embodiments, the package interposer 1704 may be formed as a PCB. In some embodiments, the package interposer 1704 may be formed of a polymeric material such as epoxy, fiberglass-reinforced epoxy, epoxy with inorganic filler, ceramic material, or polyimide. In some embodiments, the package interposer 1704 may be formed of alternative rigid or flexible materials, including the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other III-V and IV materials. In any of these embodiments, the package interposer 1704 may include multiple metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. The package interposer 1704 may include vias 1708, including, but not limited to, metal lines 1710 and conductive vias 1706. If the package interposer 1704 is a glass core, such as the glass core 110 described herein, the conductive vias 1706 may be TGVs 115 described herein, such as conductive vias with an encapsulating liner described herein. The package interposer 1704 may further include embedded devices 1714, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices, such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices, may also be formed on the package interposer 1704. The package-on-interposer structure 1736 may take the form of any package-on-interposer structure known in the art.

[0108] IC device assembly 1700 may include an IC package 1724 coupled to a first surface 1740 of circuit board 1702 by a coupling component 1722. Coupling component 1722 may take the form of any of the embodiments described above with reference to coupling component 1716, and IC package 1724 may take the form of any of the embodiments described above with reference to IC package 1720.

[0109] 13 includes a package-on-package structure 1734 coupled to a second surface 1742 of a circuit board 1702 by a coupling component 1728. The package-on-package structure 1734 may include an IC package 1726 and an IC package 1732 coupled together by a coupling component 1730 such that the IC package 1726 is disposed between the circuit board 1702 and the IC package 1732. The coupling components 1728 and 1730 may take the form of any of the embodiments of the coupling component 1716 described above, and the IC packages 1726 and 1732 may take the form of any of the embodiments of the IC package 1720 described above. The package-on-package structure 1734 may be configured according to any of the package-on-package structures known in the art.

[0110] FIG. 14 is a block diagram of an exemplary communication device 1800 that may include one or more microelectronic assemblies 100 and / or one or more glass cores 110 according to any of the embodiments disclosed herein. A handheld or laptop communication device may be an example of the communication device 1800. Any suitable ones of the components of the communication device 1800 may include one or more of the IC packages 1720, 1724, microelectronic assemblies 100, IC device assemblies 1700, IC devices 1600, or dies 1502 disclosed herein. In particular, any suitable ones of the components of the communication device 1800 may include one or more glass cores 110 described herein, for example, as part of the microelectronic assemblies 100 described herein. While numerous components are shown in FIG. 14 as being included in the communication device 1800, any one or more of these components may be omitted or duplicated if appropriate for the application. In some embodiments, some or all of the components included in the communication device 1800 may be mounted on one or more motherboards. In some embodiments, some or all of these components are fabricated on a single system-on-chip (SoC) die.

[0111] 14 , but the communications device 1800 may include interface circuitry for coupling to one or more components. For example, the communications device 1800 may not include a display device 1806, but may include display device interface circuitry (e.g., connectors and driver circuits) to which the display device 1806 may be coupled. In another set of examples, the communications device 1800 may not include an audio input device 1824 or an audio output device 1808, but may include audio input or output device interface circuitry (e.g., connectors and support circuits) to which the audio input device 1824 or the audio output device 1808 may be coupled.

[0112] The communications device 1800 may include a processing device 1802 (e.g., one or more processing devices). As used herein, the terms “processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and / or memory and converts the electronic data into other electronic data that may be stored in registers and / or memory. The processing device 1802 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (dedicated processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing devices. The communications device 1800 may include a memory 1804, which may itself include one or more memory devices, such as volatile memory (e.g., dynamic RAM (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or a hard drive. In some embodiments, the memory 1804 may include memory that shares a die with the processing device 1802. This memory may be used as cache memory and may include embedded DRAM (eDRAM) or spin-transfer torque magnetic RAM (STT-MRAM).

[0113] In some embodiments, communication device 1800 may include a communication module 1812 (e.g., one or more communication modules). For example, communication module 1812 may be configured to manage wireless communication for the transfer of data to and from communication device 1800. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that may communicate data through the use of modulated electromagnetic radiation over a non-solid medium. This term does not imply that the associated device does not include any wires, although in some embodiments this may not be the case. Communication module 1812 may be or include any of the microelectronic assemblies 100 disclosed herein.

[0114] The communications module 1812 may implement any of several wireless standards or protocols, including, but not limited to, Wi-Fi® (IEEE 802.11 family), Institute of Electrical and Electronics Engineers (IEEE) standards, including the IEEE 802.16 standard (e.g., IEEE 802.16-2005 amendment), and any amendments, updates, and / or revisions (e.g., the Long Term Evolution (LTE) project, including the Advanced LTE project, the Ultra Mobile Broadband (UMB) project (also known as "3GPP®2"), etc.). IEEE 802.16-compatible broadband wireless access (BWA) networks are commonly referred to as WiMAX® networks. This acronym stands for Worldwide Interoperability for Microwave Access, and is a certification mark for products that have passed IEEE 802.16 standard compliance and interoperability testing. The communications module 1812 may operate according to Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA or LTE network). The communications module 1812 may operate according to Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communications module 1812 may operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO) and their derivatives, as well as any other wireless protocols designated as 3G, 4G, 5G, and beyond. In other embodiments, the communications module 1812 may operate according to other wireless protocols. Communications device 1800 may include an antenna 1822 for facilitating wireless communication and / or for receiving other wireless communications (such as AM or FM radio transmissions).The antenna 1822 may include one or more microelectronic assemblies 100 and / or one or more glass cores 110 described herein, for example, as part of a microelectronic assembly 100 described herein.

[0115] In some embodiments, the communications module 1812 may manage wired communications, such as electrical, optical, or any other suitable communications protocol (e.g., Ethernet). As noted above, the communications module 1812 may include multiple communications modules. For example, a first communications module 1812 may be dedicated to shorter-range wireless communications, such as Wi-Fi or Bluetooth, and a second communications module 1812 may be dedicated to longer-range wireless communications, such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, the first communications module 1812 may be dedicated to wireless communications, and the second communications module 1812 may be dedicated to wired communications. In some embodiments, the communications module 1812 may support millimeter wave communications.

[0116] The communications device 1800 may include battery / power circuitry 1814. The battery / power circuitry 1814 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of the communications device 1800 to an energy source (e.g., AC line power) separate from the communications device 1800.

[0117] Communications device 1800 may include a display device 1806 (or corresponding interface circuitry as described above). Display device 1806 may include any visual indicator, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

[0118] The communications device 1800 may include an audio output device 1808 (or corresponding interface circuitry as described above). The audio output device 1808 may include any device that generates an audible indicator, such as a speaker, a headset, or earphones.

[0119] The communications device 1800 may include an audio input device 1824 (or corresponding interface circuitry as described above). The audio input device 1824 may include any device that generates a signal representing sound, such as a microphone, a microphone array, or a digital device (e.g., a device with a Musical Instrument Digital Interface (MIDI) output).

[0120] Communications device 1800 may include a GPS device 1818 (or corresponding interface circuitry as described above), which may communicate with a satellite-based system and receive the location of communications device 1800 in a manner known in the art.

[0121] Communications device 1800 may include other output devices 1810 (or corresponding interface circuits as described above). Examples of other output devices 1810 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or additional storage devices.

[0122] The communications device 1800 may include other input devices 1820 (or corresponding interface circuits as described above). Examples of other input devices 1820 may include an accelerometer, a gyroscope, a compass, an imaging device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a barcode reader, a quick response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0123] Communications device 1800 may have any desired form factor, including, for example, a handheld or mobile communications device (e.g., a mobile phone, smartphone, mobile internet device, music player, tablet computer, laptop computer, netbook computer, ultrabook computer, personal digital assistant (PDA), ultra-mobile personal computer, etc.), desktop communications device, server or other networked computing component, printer, scanner, monitor, set-top box, entertainment control unit, vehicle control unit, digital camera, digital video recorder, or wearable communications device. In some embodiments, communications device 1800 may be any other electronic device that processes data.

[0124] The following paragraphs provide examples of various of the embodiments disclosed herein.

[0125] Example 1 includes a glass core (e.g., a layer of glass, e.g., a layer of glass having a substantially rectangular prismatic volume, possibly including rounded or beveled edges) having a first surface and a second surface opposite the first surface; a TGV within the glass core, the TGV extending from the first surface toward the second surface (the TGV may extend at least partially through the glass core), i.e., in some embodiments, the TGV may extend to the second surface, but in other embodiments, the TGV does not reach the second surface and may be a blind via including a conductive material; a conductive A microelectronic assembly is provided comprising: a liner material (or, more generally, an organic material) in the TGV between the glass core and the conductive material, where the modulus (e.g., Young's modulus) of the liner material is less than about 30 GPa, e.g., between about 1 GPa and 30 GPa; and an encapsulant (or, more generally, an inorganic material) above the liner material in the TGV, where the encapsulant comprises silicon and nitrogen, where the glass core, conductive material, and encapsulant completely surround the liner material to reduce or eliminate degradation (oxidation and / or crystallization) of the liner material.

[0126] Example 2 provides the microelectronic assembly of Example 1, wherein the liner material comprises / is a polymeric material.

[0127] Example 3 provides the microelectronic assembly of Example 1 or 2, wherein the liner material comprises / is a homopolymer.

[0128] Example 4 provides the microelectronic assembly of any one of the preceding examples, wherein the liner material comprises / is polyparaxylylene.

[0129] Example 5 provides the microelectronic assembly of any one of the preceding examples, wherein the thickness of the liner material is between about 200 nanometers and about 10 microns, e.g., between about 200 nanometers and about 5 microns, or between about 500 nanometers and about 1 micron.

[0130] Example 6 provides the microelectronic assembly of any one of the preceding examples, wherein a portion of the liner material is in contact (e.g., direct physical contact) with a sidewall of the TGV (e.g., in contact with a glass core in the sidewall of the TGV).

[0131] Example 7 provides the microelectronic assembly of any one of the preceding examples, further comprising a liner material over the first surface of the glass core, wherein the liner material over the first surface of the glass core is materially continuous with the liner material in the TGV.

[0132] Example 8 provides the microelectronic assembly of Example 7, wherein a portion of the encapsulant is in contact (eg, direct physical contact) with a portion of the first surface of the glass core.

[0133] Example 9 provides the microelectronic assembly of Example 7, wherein a portion of the liner material above the first surface of the glass core is in contact (eg, direct physical contact) with a portion of the encapsulant.

[0134] Example 10 provides the microelectronic assembly of Example 7 or 9, wherein a portion of the liner material above the first surface of the glass core is in contact (e.g., direct physical contact) with a portion of the first surface of the glass core.

[0135] Example 11 provides the microelectronic assembly of any one of Examples 7 to 10, further comprising a conductive contact above the first surface, wherein the conductive material of the TGV is in conductive contact with the conductive material of the conductive contact, and wherein a portion of the encapsulant is on a sidewall of the conductive contact.

[0136] Example 12 provides the microelectronic assembly of Example 11, wherein an additional portion of the encapsulant is on a surface of the conductive contact that is furthest from the first surface.

[0137] Example 13 provides the microelectronic assembly of Example 7, further comprising a buffer layer over the first surface of the glass core, wherein the buffer layer is between the liner material over the first surface of the glass core and the encapsulant.

[0138] Example 14 provides the microelectronic assembly of Example 13, further comprising a conductive contact above the buffer layer, wherein the conductive material of the TGV is in conductive contact with the conductive material of the conductive contact, and wherein a portion of the encapsulant is on a sidewall of the conductive contact.

[0139] Example 15 provides the microelectronic assembly of Example 14, wherein an additional portion of the encapsulant is on a surface of the conductive contact that is furthest from the first surface.

[0140] Example 16 provides the microelectronic assembly of Examples 14 or 15, wherein a portion of the buffer layer contacts (eg, is in direct physical contact with) a portion of the conductive contact.

[0141] Example 17 provides the microelectronic assembly of any one of Examples 13 to 16, wherein a portion of the encapsulant is in contact (eg, direct physical contact) with a portion of the buffer layer.

[0142] Example 18 provides the microelectronic assembly of any one of Examples 7 to 17, wherein the encapsulant is a first encapsulant, and the microelectronic assembly further comprises a second encapsulant, the second encapsulant having silicon and nitrogen, the second encapsulant being between the buffer layer and the liner material above the first surface of the glass core.

[0143] Example 19 provides the microelectronic assembly of Example 18, wherein a portion of the buffer layer is in contact (eg, direct physical contact) with a portion of the second encapsulant.

[0144] Example 20 provides the microelectronic assembly of Examples 18 or 19, wherein the buffer layer is between the first encapsulant and the second encapsulant.

[0145] Example 21 is a glass core having a first surface and a second surface opposite the first surface, and having a conductive via extending from the first surface toward the second surface (the via may extend at least partially through the glass core, i.e., in some embodiments, the via may extend to the second surface, but in other embodiments, the via may be a blind via that does not reach the second surface); an organic material within the conductive via, where the organic material is on a sidewall of the conductive via between the conductive material of the conductive via and the glass core; and an inorganic material surrounding the organic material within the conductive via. A microelectronic assembly is provided, comprising:

[0146] Example 22 provides the microelectronic assembly of Example 21, wherein the modulus (eg, Young's modulus) of the organic material is less than the modulus (eg, Young's modulus) of the glass core.

[0147] Example 23 provides the microelectronic assembly of Examples 21 or 22, wherein the modulus (e.g., Young's modulus) of the organic material is less than the modulus (e.g., Young's modulus) of the conductive material of the conductive via.

[0148] Example 24 provides the microelectronic assembly of any one of Examples 21 to 23, wherein the organic material comprises / is an organic polymer, for example, an organic homopolymer.

[0149] Example 25 provides the microelectronic assembly of any one of Examples 21 to 24, wherein the organic material comprises / is polyparaxylylene (also commonly referred to as "parylene").

[0150] Example 26 provides the microelectronic assembly of any one of Examples 21 to 25, wherein the organic material comprises / is Parylene N, Parylene C, Parylene D, or Parafree.

[0151] Example 27 provides the microelectronic assembly of any one of Examples 21 to 26, wherein the thickness of the organic material is between about 200 nanometers and about 10 microns, e.g., between about 200 nanometers and about 5 microns, or between about 500 nanometers and about 1 micron.

[0152] Example 28 provides the microelectronic assembly of any one of Examples 21 to 27, wherein the inorganic material comprises silicon and nitrogen.

[0153] Example 29 provides the microelectronic assembly of any one of Examples 21 to 28, wherein the inorganic material comprises a material for reducing or eliminating oxidation of the organic material.

[0154] Example 30 provides the microelectronic assembly of any one of Examples 21 to 29, wherein the inorganic material comprises a material for reducing or eliminating crystallization of the organic material. Example 31 provides the microelectronic assembly of any one of Examples 21 to 30, wherein the organic material is a liner material and the inorganic material is the encapsulant of any one of Examples 7 to 20.

[0155] Example 32 provides the microelectronic assembly of any one of the preceding examples, wherein a cross-section of the glass core in a plane perpendicular to a surface of the component is substantially rectangular.

[0156] Example 33 provides the microelectronic assembly of any one of the preceding examples, wherein a cross-section of the glass core in a plane parallel to a surface of the component is substantially rectangular.

[0157] Example 34 provides the microelectronic assembly of any one of the preceding examples, wherein the glass core is a layer of glass containing at least 23% silicon by weight.

[0158] Example 35 provides the microelectronic assembly of any one of the preceding examples, wherein the glass core is a layer of glass containing at least 26% oxygen by weight.

[0159] Example 36 provides the microelectronic assembly of any one of the preceding examples, wherein the glass core is a layer of glass comprising at least 23% silicon by weight and at least 26% oxygen by weight.

[0160] Example 37 provides the microelectronic assembly of any one of the preceding examples, wherein the glass core is a layer of glass comprising at least 5% by weight aluminum.

[0161] Example 38 provides the microelectronic assembly of any one of the preceding examples, wherein the glass core is a layer of glass that is free of organic adhesives or organic materials.

[0162] Example 39 provides the microelectronic assembly of any one of the preceding examples, wherein the glass core is a layer of glass having a thickness in the range of 50 microns (μm) to 1.4 millimeters (mm), a first length in the range of 10 mm to 250 mm, and a second length in the range of 10 mm to 250 mm, wherein the first length is perpendicular to the second length.

[0163] Example 40 provides the microelectronic assembly of any one of the preceding examples, wherein the glass core is a layer of glass having a thickness in the range of 50 μm to 1.4 mm.

[0164] Example 41 provides the microelectronic assembly of any one of the preceding examples, wherein the glass core is a layer of glass having a first length in the range of 10 mm to 250 mm and a second length in the range of 10 mm to 250 mm, the first length being perpendicular to the second length.

[0165] Example 42 provides the microelectronic assembly of any one of the preceding examples, wherein the glass core is a layer of glass including a rectangular prismatic volume.

[0166] Example 43 provides the microelectronic assembly of any one of the preceding examples, wherein the glass core is a layer of glass including a rectangular prism volume having a first side and a second side perpendicular to the first side, the first side having a length in the range of 10 mm to 250 mm, and the second side having a length in the range of 10 mm to 250 mm.

[0167] Example 44 provides the microelectronic assembly of any one of the preceding examples, wherein the glass core is a layer of glass comprising a rectangular prismatic volume and a via extending from a first side of the rectangular prismatic volume to a second side of the rectangular prismatic volume, wherein the via comprises a metal.

[0168] Example 45 provides the microelectronic assembly of any one of the preceding examples, wherein the glass core is a solid layer of glass. Example 46 provides the microelectronic assembly of any one of the preceding examples, wherein the conductive material is a metal or metal alloy. Example 47 provides the microelectronic assembly of any one of the preceding examples, wherein the conductive material comprises one or more of copper, silver, nickel, gold, or aluminum.

[0169] Example 48 provides a method for manufacturing a microelectronic assembly, the method comprising: depositing an organic material on a sidewall of a via opening in a glass core, the glass core including a first surface and a second surface opposite the first surface, the via opening extending from the first surface toward the second surface; depositing a seed material over the organic material on the sidewall of the via opening, the organic material being between the sidewall of the via opening and the seed material; depositing a conductive fill material in the via opening, the seed material being between the organic material and the conductive fill material; forming a conductive contact on the first surface of the glass core above the via opening, the conductive contact being electrically continuous with the conductive fill material in the via opening; and depositing an encapsulant over the conductive contact and over the first surface of the glass core.

[0170] Example 49 provides a method according to Example 48, wherein depositing the organic material comprises depositing the organic material using CVD.

[0171] Example 50 provides a method according to example 48 or 49, wherein the organic material is deposited as a liner that is conformal with the sidewalls of the via opening.

[0172] Example 51 provides the method of any one of Examples 48 to 50, wherein depositing the conductive fill material comprises depositing the conductive fill material using electroplating.

[0173] Example 52 provides the method of any one of Examples 48 to 51, further comprising providing one or more build-up layers over the encapsulant.

[0174] Example 53 provides the method of any one of Examples 48 to 52, wherein the microelectronic assembly is the microelectronic assembly of any one of Examples 1 to 47.

[0175] The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise form disclosed. While specific implementations and examples of the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as will be apparent to those skilled in the art. These modifications can be made to the disclosure in light of the above detailed description. [Other possible items] [Item 1] a layer of glass having a first surface and a second surface opposite the first surface; a through-glass via (TGV) in the layer of glass, the TGV extending from the first surface toward the second surface and having a conductive material; an organic material in the TGV between the conductive material and the layer of glass, wherein the modulus of the organic material is less than about 30 gigapascals; and an inorganic material above the organic material in the TGV, the inorganic material comprising silicon and nitrogen; A microelectronic assembly comprising: [Item 2] Item 10. The microelectronic assembly of item 1, wherein the organic material comprises a homopolymer. [Item 3] 3. The microelectronic assembly according to claim 1 or 2, wherein the organic material comprises polyparaxylylene. [Item 4] 4. The microelectronic assembly of claim 1, further comprising the organic material above the first surface of the layer of glass, wherein the organic material above the first surface of the layer of glass is materially continuous with the organic material in the TGV. [Item 5] Item 5. The microelectronic assembly of item 4, wherein a portion of the inorganic material is in contact with a portion of the first surface of the glass layer, or a portion of the organic material above the first surface of the glass layer is in contact with a portion of the inorganic material. [Item 6] Item 6. The microelectronic assembly of item 4 or 5, wherein a portion of the organic material above the first surface of the layer of glass is in contact with a portion of the first surface of the layer of glass. [Item 7] 7. The microelectronic assembly of any one of items 4 to 6, further comprising a conductive contact above the first surface, wherein the conductive material of the TGV is in conductive contact with the conductive material of the conductive contact, and wherein a portion of the inorganic material is on a sidewall of the conductive contact. [Item 8] Item 8. The microelectronic assembly of item 7, wherein a further portion of the inorganic material is on a surface of the conductive contact that is furthest from the first surface. [Item 9] Item 5. The microelectronic assembly of item 4, further comprising a buffer layer above the first surface of the layer of glass, the buffer layer being between the organic material and the inorganic material above the first surface of the layer of glass. [Item 10] Item 10. The microelectronic assembly of item 9, further comprising a conductive contact above the buffer layer, wherein the conductive material of the TGV is in conductive contact with the conductive material of the conductive contact, and wherein a portion of the inorganic material is on a sidewall of the conductive contact. [Item 11] Item 11. The microelectronic assembly of item 10, wherein a further portion of the inorganic material is on a surface of the conductive contact that is furthest from the first surface. [Item 12] Item 12. The microelectronic assembly of item 10 or 11, wherein a portion of the buffer layer is in contact with a portion of the conductive contact. [Item 13] 13. The microelectronic assembly of any one of items 9 to 12, wherein a portion of the inorganic material is in contact with a portion of the buffer layer. [Item 14] the inorganic material is a first inorganic material, the microelectronic assembly further comprising a second inorganic material; the second inorganic material comprises silicon and nitrogen; the second inorganic material is between the buffer layer and the organic material above the first surface of the glass layer; 14. The microelectronic assembly according to any one of items 9 to 13. [Item 15] Item 15. The microelectronic assembly of item 14, wherein a portion of the buffer layer is in contact with a portion of the second inorganic material. [Item 16] Item 16. The microelectronic assembly of item 14 or 15, wherein the buffer layer is between the first inorganic material and the second inorganic material. [Item 17] a glass core having a first surface and a second surface opposite the first surface, and having a conductive via extending from the first surface toward the second surface; a liner material within the conductive via, wherein the liner material is on a sidewall of the conductive via between the conductive material of the conductive via and the glass core, wherein the thickness of the liner material is between about 200 nanometers and about 10 microns; and an encapsulant surrounding the liner material within the conductive via; A microelectronic assembly comprising: [Item 18] Item 18. The microelectronic assembly of item 17, wherein the modulus of the liner material is less than the modulus of the glass core, the liner material comprises an organic polymer, and the encapsulant comprises silicon and nitrogen. [Item 19] 1. A method of manufacturing a microelectronic assembly, comprising: depositing an organic material on a sidewall of a via opening in a glass core, wherein the glass core includes a first surface and a second surface opposite the first surface, wherein the via opening extends from the first surface toward the second surface; depositing a seed material over the organic material on the sidewall of the via opening, wherein the organic material is between the sidewall of the via opening and the seed material; depositing a conductive fill material in the via opening, wherein the seed material is between the organic material and the conductive fill material; forming a conductive contact on the first surface of the glass core above the via opening, wherein the conductive contact is electrically continuous with the conductive fill material in the via opening; and depositing an encapsulant over the conductive contacts and over the first surface of the glass core; A method comprising: [Item 20] 20. The method of claim 19, wherein the organic material is deposited as a liner that is conformal with the sidewalls of the via opening.

Claims

1. a layer of glass having a first surface and a second surface opposite the first surface; a through-glass via (TGV) in the layer of glass, the TGV extending from the first surface toward the second surface and comprising a conductive material; an organic material in the TGV between the conductive material and the layer of glass, wherein the modulus of the organic material is less than about 30 gigapascals; and an inorganic material above the organic material in the TGV, the inorganic material comprising silicon and nitrogen; A microelectronic assembly comprising:

2. The microelectronic assembly of claim 1 , wherein the organic material comprises a homopolymer.

3. The microelectronic assembly of claim 1 , wherein the organic material comprises polyparaxylylene.

4. 10. The microelectronic assembly of claim 1, further comprising the organic material above the first surface of the layer of glass, wherein the organic material above the first surface of the layer of glass is materially continuous with the organic material in the TGV.

5. 5. The microelectronic assembly of claim 4, wherein a portion of the inorganic material is in contact with a portion of the first surface of the glass layer, or a portion of the organic material above the first surface of the glass layer is in contact with a portion of the inorganic material.

6. The microelectronic assembly of claim 4 , wherein a portion of the organic material above the first surface of the glass layer is in contact with a portion of the first surface of the glass layer.

7. 5. The microelectronic assembly of claim 4, further comprising a conductive contact above the first surface, wherein the conductive material of the TGV is in conductive contact with the conductive material of the conductive contact, and wherein a portion of the inorganic material is on a sidewall of the conductive contact.

8. 8. The microelectronic assembly of claim 7, wherein a further portion of said inorganic material is on a surface of said conductive contact furthest from said first surface.

9. 5. The microelectronic assembly of claim 4, further comprising a buffer layer over the first surface of the layer of glass, the buffer layer being between the organic material and the inorganic material over the first surface of the layer of glass.

10. 10. The microelectronic assembly of claim 9, further comprising a conductive contact above the buffer layer, wherein the conductive material of the TGV is in conductive contact with the conductive material of the conductive contact, and wherein a portion of the inorganic material is on a sidewall of the conductive contact.

11. The microelectronic assembly of claim 10 , wherein a further portion of the inorganic material is on a surface of the conductive contact furthest from the first surface.

12. The microelectronic assembly of claim 10 , wherein a portion of the buffer layer contacts a portion of the conductive contact.

13. The microelectronic assembly of claim 9 , wherein a portion of the inorganic material is in contact with a portion of the buffer layer.

14. the inorganic material is a first inorganic material, the microelectronic assembly further comprising a second inorganic material; the second inorganic material comprises silicon and nitrogen; the second inorganic material is between the buffer layer and the organic material above the first surface of the glass layer; A microelectronic assembly according to any one of claims 9 to 13.

15. 15. The microelectronic assembly of claim 14, wherein a portion of the buffer layer is in contact with a portion of the second inorganic material.

16. 15. The microelectronic assembly of claim 14, wherein the buffer layer is between the first inorganic material and the second inorganic material.

17. a glass core having a first surface and a second surface opposite the first surface, and having a conductive via extending from the first surface toward the second surface; a liner material within the conductive via, wherein the liner material is on a sidewall of the conductive via between the conductive material of the conductive via and the glass core, wherein the thickness of the liner material is between about 200 nanometers and about 10 microns; and an encapsulant surrounding the liner material within the conductive via; A microelectronic assembly comprising:

18. 18. The microelectronic assembly of claim 17, wherein the modulus of the liner material is less than the modulus of the glass core, the liner material comprises an organic polymer, and the encapsulant comprises silicon and nitrogen.

19. 1. A method of manufacturing a microelectronic assembly, comprising: depositing an organic material on a sidewall of a via opening in a glass core, wherein the glass core includes a first surface and a second surface opposite the first surface, wherein the via opening extends from the first surface toward the second surface; depositing a seed material over the organic material on the sidewall of the via opening, wherein the organic material is between the sidewall of the via opening and the seed material; depositing a conductive fill material in the via opening, wherein the seed material is between the organic material and the conductive fill material; forming a conductive contact on the first surface of the glass core above the via opening, wherein the conductive contact is electrically continuous with the conductive fill material in the via opening; and depositing an encapsulant over the conductive contacts and over the first surface of the glass core; A method comprising:

20. 20. The method of claim 19, wherein the organic material is deposited as a liner that is conformal with the sidewalls of the via opening.

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