Semiconductor device and manufacturing method thereof

Abstract

To provide a technology that can suppress step discontinuities of a barrier metal film in a semiconductor device having a structure in which a contact portion protrudes from an adjacent peripheral region.SOLUTION: A semiconductor device includes a silicon carbide contact portion (11), a metal silicide film (23) provided on a top surface (11c) of the contact portion and disposed apart from at least part of the edges (11a, 11b) of the contact portion, and a barrier metal film (24) covering the metal silicide film and in contact with the top surface and side surfaces that define at least part of the edges of the contact portion.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device manufactured using a silicon carbide semiconductor layer. In this semiconductor device, a trench gate and an interlayer insulating film are embedded in a trench formed in the main surface of the semiconductor layer. A structure in which a trench gate and an interlayer insulating film are embedded in a trench is called a self-aligned contact structure. In a semiconductor device with a self-aligned contact structure, a nickel film is formed on the main surface of the semiconductor layer, a nickel silicide film is formed on the main surface of the semiconductor layer by annealing, and then the unreacted nickel film is removed, thereby forming a metal silicide film in ohmic contact with the main surface of the semiconductor layer. In a semiconductor device with a self-aligned contact structure, an interlayer insulating film is not provided on the main surface of the semiconductor layer, so there is no need to form a contact hole in the interlayer insulating film, and the metal silicide film can be formed in a self-aligned manner. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2023-055162 Summary of the Invention [Problem to be solved by the invention]

[0004] In the semiconductor device described above, contact portions are provided in the upper layer of the semiconductor layer between adjacent trenches, and a metal silicide film is formed on the contact portions. The contact portions protrude from the interlayer insulating film buried in the adjacent trenches. Therefore, the metal silicide film formed on the protruding contact portions is formed on both the top and side surfaces of the contact portions, and has portions (hereinafter referred to as eaves-shaped portions) that protrude laterally at the corners of the top and side surfaces of the contact portions.

[0005] A barrier metal film and a metal electrode film are sequentially formed on a metal silicide film. However, if a metal silicide film has an overhang, the barrier metal film may not adhere well below the overhang, resulting in a step in the barrier metal film. If the barrier metal film is step-disconnected, metal atoms constituting the metal silicide film may diffuse into the metal electrode film through the step in the barrier metal film, potentially increasing the resistance of the metal electrode film.

[0006] This problem does not occur only in semiconductor devices with a self-aligned contact structure, but also occurs widely in semiconductor devices with a structure in which a contact portion protrudes from an adjacent peripheral region. This specification provides a technology that can suppress step discontinuities in a barrier metal film in a semiconductor device with a structure in which a contact portion protrudes from an adjacent peripheral region. [Means for solving the problem]

[0007] The semiconductor device disclosed herein may include a silicon carbide contact portion (11), a metal silicide film (23) provided on a top surface (11c) of the contact portion and spaced apart from at least a portion of an edge (11a, 11b) of the contact portion, and a barrier metal film (24) covering the metal silicide film and contacting the top surface and side surface (11d) that define at least a portion of the edge of the contact portion. In this semiconductor device, no overhanging portion of the metal silicide film is formed on at least a portion of the edge of the contact portion. This allows the barrier metal film to adhere well without discontinuity at at least a portion of the edge of the contact portion.

[0008] This specification can also provide a method for manufacturing the above-mentioned semiconductor device. This manufacturing method may include a modified region forming step of forming a modified region (44) in a portion of the top surface of the contact portion, the modified region being a region modified from hexagonal to cubic or amorphous; a metal film forming step of forming a metal film (46) on the top surface of the contact portion; a metal silicide film forming step of reacting the metal film with the modified region of the contact portion to form a metal silicide film; a metal film removing step of removing unreacted metal film in the metal silicide film forming step; and a barrier metal film forming step of forming a barrier metal film covering the metal silicide film and extending beyond at least a portion of the edge of the contact portion to a peripheral region. In the manufacturing method, a modified region is formed in a portion of the top surface of the contact portion by modifying the region from hexagonal to cubic or amorphous. Such a modified region is more susceptible to silicidation than an unmodified region (i.e., a region with a hexagonal crystal structure) on the top surface of the contact portion. Therefore, in the above manufacturing method, by forming a modified region on a portion of the top surface of the contact portion, a metal silicide film can be formed in a self-aligned manner in the modified region. According to the above manufacturing method, a metal silicide film can be formed away from at least a portion of the edge of the contact portion. [Brief explanation of the drawings]

[0009] [Figure 1]FIG. 1 is a schematic cross-sectional view of a main part of a semiconductor device. [Figure 2] FIG. 2 is a perspective view of a main part of the semiconductor device, and is a diagram schematically showing a perspective view of a main part of the semiconductor device in a state where a source electrode is removed. [Figure 3] 3 is a diagram showing a manufacturing flow of a first manufacturing method for manufacturing the semiconductor device of FIG. 1 and FIG. 2. [Figure 4] 3 is a schematic cross-sectional view of a main part of a semiconductor layer in a step of a first manufacturing method for manufacturing the semiconductor device of FIGS. 1 and 2.

[0023] FIG. [Figure 5] 3 is a schematic cross-sectional view of a main part of a semiconductor layer in a step of a first manufacturing method for manufacturing the semiconductor device of FIGS. 1 and 2.

[0023] FIG. [Figure 6] 3 is a schematic perspective view of a main part of a semiconductor layer in a step of a first manufacturing method for manufacturing the semiconductor device of FIGS. 1 and 2.

[0023] FIG. [Figure 7] 3 is a schematic cross-sectional view of a main part of a semiconductor layer in a step of a first manufacturing method for manufacturing the semiconductor device of FIGS. 1 and 2.

[0023] FIG. [Figure 8] 3 is a schematic cross-sectional view of a main part of a semiconductor layer in a step of a first manufacturing method for manufacturing the semiconductor device of FIGS. 1 and 2.

[0023] FIG. [Figure 9] 3 is a schematic cross-sectional view of a main part of a semiconductor layer in a step of a first manufacturing method for manufacturing the semiconductor device of FIGS. 1 and 2.

[0023] FIG. [Figure 10] 3 is a schematic cross-sectional view of a main part of a semiconductor layer in a step of a first manufacturing method for manufacturing the semiconductor device of FIGS. 1 and 2.

[0023] FIG. [Figure 11] 3 is a schematic cross-sectional view of a main part of a semiconductor layer in a step of a first manufacturing method for manufacturing the semiconductor device of FIGS. 1 and 2.

[0023] FIG. [Figure 12] 3 is a schematic cross-sectional view of a main part of a semiconductor layer in a step of a first manufacturing method for manufacturing the semiconductor device of FIGS. 1 and 2.

[0023] FIG. [Figure 13] 3 is a schematic cross-sectional view of a main part of a semiconductor layer in a step of a first manufacturing method for manufacturing the semiconductor device of FIGS. 1 and 2.

[0023] FIG. [Figure 14]3 is a schematic cross-sectional view of a main part of a semiconductor layer in a step of a first manufacturing method for manufacturing the semiconductor device of FIGS. 1 and 2.

[0023] FIG. [Figure 15] 3 is a schematic cross-sectional view of a main part of a semiconductor layer in a step of a first manufacturing method for manufacturing the semiconductor device of FIGS. 1 and 2.

[0023] FIG. [Figure 16] 3 is a schematic cross-sectional view of a main part of a semiconductor layer in a step of a first manufacturing method for manufacturing the semiconductor device of FIGS. 1 and 2.

[0023] FIG. [Figure 17] 3 is a schematic cross-sectional view of a main part of a semiconductor layer in a step of a first manufacturing method for manufacturing the semiconductor device of FIGS. 1 and 2.

[0023] FIG. [Figure 18] In a comparative example, (A) is a diagram showing a schematic enlarged cross-sectional view of a main part near one edge of a mesa portion after a metal film deposition process, and (B) is a diagram showing a schematic enlarged cross-sectional view of a main part near one edge of a mesa portion after a metal silicide film deposition process. [Figure 19] FIG. 2 is a diagram schematically illustrating an enlarged cross-sectional view of a main portion near one edge of a mesa portion of the semiconductor device. [Figure 20] 3 is a diagram showing a manufacturing flow of a second manufacturing method for manufacturing the semiconductor device of FIG. 1 and FIG. 2. [Figure 21] 3 is a schematic cross-sectional view of a main part of a semiconductor layer in a step of a second manufacturing method for manufacturing the semiconductor device of FIGS. 1 and 2. FIG. [Figure 22] 3 is a schematic cross-sectional view of a main part of a semiconductor layer in a step of a second manufacturing method for manufacturing the semiconductor device of FIGS. 1 and 2. FIG. [Figure 23] FIG. 10 is a schematic cross-sectional view of a main part of a modified example of the semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, a semiconductor device disclosed in this specification will be described with reference to the drawings. Note that for the purpose of clarity in the drawings, only some of the repeatedly arranged components are denoted by reference numerals.

[0011] As shown in FIGS. 1 and 2, the semiconductor device 1 is a type of semiconductor device known as an n-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and includes a semiconductor layer 10 having a first main surface 10a and a second main surface 10b, a drain electrode 22 covering the second main surface 10b of the semiconductor layer 10, a source electrode 26 covering the first main surface 10a of the semiconductor layer 10, and a plurality of trench gates 30 provided in the upper layer portion of the semiconductor layer 10. Note that FIG. 2 illustrates the semiconductor layer 10 with the source electrode 26 removed. Here, the first main surface 10a and the second main surface 10b are a pair of surfaces extending in parallel on the surface of the semiconductor layer 10, and are surfaces perpendicular to the thickness direction of the semiconductor layer 10 (in this example, the vertical direction on the paper). The semiconductor layer 10 is an n-channel MOSFET. + a n-type drain region 12, an n-type drift region 14, a p-type body region 16, and a p + a body contact region 17 of type n + and a source region 18. The material of the semiconductor layer 10 is silicon carbide (SiC).

[0012] The drain region 12 is provided in a lower layer portion of the semiconductor layer 10, and is disposed at a position exposed to the second main surface 10b of the semiconductor layer 10. The drain region 12 contains a high concentration of n-type impurities and is in ohmic contact with the drain electrode 22. As will be described later, the drain region 12 is a silicon carbide substrate for epitaxially growing the drift region 14.

[0013] The drift region 14 is provided in contact with the upper surface of the drain region 12 and is disposed between the drain region 12 and the body region 16. The drift region 14 is in contact with the bottom surface and lower side surfaces of the trench gate 30. The drift region 14 is formed by epitaxial growth from the upper surface of the drain region 12.

[0014] The body region 16 is provided in contact with the upper surface of the drift region 14, and is arranged between the drift region 14 and the body contact region 17, and between the drift region 14 and the source region 18. The body region 16 is in contact with the side surface of the trench gate 30. The body region 16 is a region formed by ion-implanting p-type impurities (e.g., aluminum) from the first main surface 10a of the semiconductor layer 10.

[0015] Both the body contact region 17 and the source region 18 are provided in contact with the upper surface of the body region 16, are provided in the upper layer portion of the semiconductor layer 10, and are arranged at positions exposed at the first major surface 10a of the semiconductor layer 10. Both the body contact region 17 and the source region 18 are in contact with the upper part of the side surface of the trench gate 30. When the first major surface 10a of the semiconductor layer 10 is viewed in plan, the body contact region 17 and the source region 18 are arranged alternately and repeatedly along one direction.

[0016] The body contact region 17 contains a high concentration of p-type impurities and is in ohmic contact with the source electrode 26. The body contact region 17 is a region formed by ion-implanting p-type impurities (e.g., aluminum) from the first main surface 10a of the semiconductor layer 10.

[0017] The source region 18 contains a high concentration of n-type impurities and is in ohmic contact with the source electrode 26. The source region 18 is a region formed by ion-implanting n-type impurities (for example, nitrogen) from the first main surface 10a of the semiconductor layer 10.

[0018] The body contact region 17 and the source region 18 are provided in an upper layer portion of the semiconductor layer 10 outside the trenches TR (i.e., a portion of the semiconductor layer 10 between the trenches TR, hereinafter also referred to as a "mesa portion 11"). The mesa portion 11 in which the body contact region 17 and the source region 18 are provided is a portion for contacting the source electrode 26 and is an example of a contact portion. When the source electrode 26, which is the contact target, is removed, the mesa portion 11 protrudes from an adjacent peripheral region (a region adjacent to the mesa portion 11 when the semiconductor layer 10 is viewed from above; in this example, the interlayer insulating film 42 embedded in the trench TR).

[0019] The source electrode 26 is provided on the first major surface 10a of the semiconductor layer 10, and includes a metal silicide film 23, a barrier metal film 24, and a metal electrode film 25.

[0020] The metal silicide film 23 is provided on a part of the top surface 11c of the mesa portion 11, and is in ohmic contact with the body contact region 17 and the source region 18. The metal silicide film 23 is nickel silicide (NiSi) formed by silicidation of nickel (Ni). Alternatively, the metal silicide film 23 may be formed by silicidation of, for example, titanium (Ti), tantalum (Ta), tungsten (W), or molybdenum (Mo), although the metal silicide film 23 is not particularly limited to this example.

[0021] The metal silicide film 23 is provided away from a pair of edges 11a, 11b of the mesa portion 11. The pair of edges 11a, 11b are boundaries that define the trench TR in the first main surface 10a of the semiconductor layer 10, and are corners defined by the top surface 11c and side surface 11d of the mesa portion 11. In this example, the pair of edges 11a, 11b are edges of the top surface 11c of the mesa portion 11 that extend parallel to the longitudinal direction of the trench TR when the semiconductor layer 10 is viewed in a plan view. In this manner, the metal silicide film 23 is provided on a portion of the inner side of the top surface 11c of the mesa portion 11 when the semiconductor layer 10 is viewed in a plan view. Therefore, the pair of edges 11a, 11b of the mesa portion 11 are not covered with the metal silicide film 23.

[0022] The barrier metal film 24 is formed to cover the first main surface 10a of the semiconductor layer 10. Specifically, the barrier metal film 24 covers the metal silicide film 23 and extends beyond the pair of edges 11a, 11b of the mesa portion 11 to the interlayer insulating film 42. The barrier metal film 24 is in contact with the top surface 11c and the side surface 11d that define the pair of edges 11a, 11b of the mesa portion 11, and covers the pair of edges 11a, 11b of the mesa portion 11 without any discontinuities. The barrier metal film 24 prevents metal elements contained in the metal electrode film 25 from diffusing beyond the barrier metal film 24 into the metal silicide film 23 and the interlayer insulating film 42, and also prevents metal elements contained in the metal silicide film 23 from diffusing beyond the barrier metal film 24 into the metal electrode film 25. The barrier metal film 24 is not particularly limited, and may be formed by laminating titanium (Ti) and titanium nitride (TiN), for example.

[0023] The metal electrode film 25 is formed so as to cover the first main surface 10a of the semiconductor layer 10, and functions as a metal pad. The metal electrode film 25 is not particularly limited, but may be made of aluminum silicon (AlSi).

[0024] The trench gate 30 is provided in a trench TR that extends from the first main surface 10a of the semiconductor layer 10, passing through the body region 16, and reaching the drift region 14. The trench gate 30 includes a gate insulating film 32 and a gate electrode 34. The gate insulating film 32 contacts the side and bottom surfaces of the trench TR. The gate electrode 34 is provided inside the gate insulating film 32, and its side and bottom surfaces are covered with the gate insulating film 32. The gate electrode 34 is not particularly limited, and may be made of, for example, polysilicon doped with a high concentration of n-type impurities.

[0025] The gate electrode 34 is provided below the pair of edges 11a, 11b of the mesa portion 11. That is, the gate electrode 34 is buried in a part of the trench TR. The gate electrode 34 is insulated from the source electrode 26 by an interlayer insulating film 42. The interlayer insulating film 42 is buried in the upper part of the trench TR on the gate electrode 34. The interlayer insulating film 42 is also located below the pair of edges 11a, 11b of the mesa portion 11. In this way, the semiconductor device 1 is a semiconductor device having a self-aligned contact structure.

[0026] Next, the operation of the semiconductor device 1 will be described. When a positive voltage higher than that of the source electrode 26 is applied to the drain electrode 22 and a positive voltage higher than the threshold voltage is applied to the gate electrode 34, the semiconductor device 1 turns on. At this time, an inversion layer channel is formed in the body region 16 that contacts the side surface of the trench gate 30. Electrons injected from the source region 18 are injected into the drift region 14 through the inversion layer in the body region 16 and then move from the drift region 14 to the drain region 12, turning the semiconductor device 1 on. When the positive voltage applied to the gate electrode 34 falls below the threshold voltage, the inversion layer in the body region 16 disappears, turning the semiconductor device 1 off. In this way, the semiconductor device 1 can perform a switching operation by controlling the current flowing through the inversion layer depending on the voltage applied to the gate electrode 34.

[0027] (First manufacturing method) Next, a first manufacturing method of the semiconductor device 1 will be described with reference to the manufacturing flow of FIG. 3 and FIGS.

[0028] 4, a semiconductor layer 10 is prepared in which a drain region 12, a drift region 14, a body region 16, and a source region 18 (and further including a body contact region 17 adjacent to the source region 18) are stacked. This semiconductor layer 10 is prepared by growing an epitaxial layer with a low concentration of n-type impurities from the upper surface of the drain region 12, which is a silicon carbide substrate, using an epitaxial growth technique, and then introducing n-type impurities and p-type impurities into the upper layer of the epitaxial layer using an ion implantation technique, thereby forming the body region 16 and the source region 18 (and further including the body contact region 17).

[0029] 5 and 6, a shielding film 52 that exposes a partial region of the first main surface 10a of the semiconductor layer 10 is formed on the first main surface 10a of the semiconductor layer 10 by, for example, a CVD (Chemical Vapor Deposition) method (step S1 in FIG. 3). The shielding film 52 has openings 52a that extend along the repeating direction of the body contact regions 17 and the source regions 18, and parts of the body contact regions 17 and the source regions 18 are exposed from the openings 52a in the shielding film 52.

[0030] Next, as shown in FIG. 7, atomic ions are implanted into a portion of the first main surface 10a of the semiconductor layer 10 exposed through the opening 52a of the shielding film 52, for example, using ion implantation technology, to form a modified region 44 (step S2 in FIG. 3). The modified region 44 is a region modified from a hexagonal crystal to a cubic crystal or an amorphous crystal. The implanted ion atoms are not particularly limited, but may be, for example, argon (Ar), aluminum (Al), or phosphorus (P). The modified region 44 is formed in a region corresponding to the formation area of ​​the metal silicide film 23 (see FIG. 1). Note that, instead of ion implantation technology, the modified region forming step may modify a portion of the first main surface 10a of the semiconductor layer 10 from a hexagonal crystal to a cubic crystal or an amorphous crystal by other methods. The modified region forming step may also form the modified region 44 by, for example, laser irradiation technology.

[0031] Next, as shown in Fig. 8, trenches TR are formed by, for example, dry etching, penetrating the body region 16 from the first main surface 10a of the semiconductor layer 10 to reach the drift region 14 (step S3 in Fig. 3). A mesa portion 11 is formed between the trenches TR. The trenches TR are formed at positions away from the modified region 44. As a result, the modified region 44 is located away from the pair of edges 11a, 11b of the mesa portion 11.

[0032] Next, as shown in FIG. 9, a gate insulating film 32 is formed on the first main surface 10a of the semiconductor layer 10 including the side and bottom surfaces of the trenches TR by, for example, CVD (Step S4 in FIG. 3).

[0033] 10, a gate electrode 34 is buried in a portion of the trench TR by, for example, CVD (step S5 in FIG. 3). Specifically, after forming a film of polysilicon doped with n-type impurities on the first main surface 10a of the semiconductor layer 10 including the inside of the trench TR, unnecessary polysilicon is removed by etch-back, thereby burying the gate electrode 34 in a portion of the trench TR. In this way, a trench gate 30 is formed in the trench TR.

[0034] 11, an interlayer insulating film 42 is formed on the first main surface 10a of the semiconductor layer 10 by, for example, a CVD method (step S6 in FIG. 3). The interlayer insulating film 42 is formed so that a portion of it is embedded in the trench TR to cover the gate electrode 34 and also to cover the gate insulating film 32 on the mesa portion 11.

[0035] 12, the interlayer insulating film 42 and the gate insulating film 32 are etched back by, for example, dry etching until the mesa portion 11 is exposed (step S7 in FIG. 3). The etch-back process is performed such that the interlayer insulating film 42 and the gate insulating film 32 are over-etched so that the mesa portion 11 is reliably exposed, and the interlayer insulating film 42 and the gate insulating film 32 are positioned below the pair of edges 11a, 11b of the mesa portion 11.

[0036] 13, a metal film 46 is formed on the first main surface 10a of the semiconductor layer 10 by, for example, sputtering (step S8 in FIG. 3). In this example, the metal film 46 is a nickel film, but it may also be a titanium film, a tantalum film, a tungsten film, or a molybdenum film.

[0037] Next, as shown in FIG. 14, annealing is performed at a predetermined temperature to form a metal silicide film 23 (step S9 in FIG. 3). Here, the modified region 44 is a region that has been modified from hexagonal to cubic or amorphous, and is silicided at a temperature lower than that of the unmodified region (a hexagonal region, i.e., a corner including the pair of edges 11a and 11b of the mesa portion 11). The predetermined temperature for this annealing is set to a temperature at which the silicon in the modified region 44 reacts with the nickel in the metal film 46, but the silicon in the unmodified region does not substantially react with the nickel in the metal film 46. The predetermined temperature is not particularly limited, but is, for example, between 200 and 600°C. As a result, the metal silicide film 23 is selectively formed in the region of the top surface 11c of the mesa portion 11 that corresponds to the modified region 44.

[0038] 15, the metal film 46 that has not reacted in the annealing step is removed by, for example, wet etching (step S10 in FIG. 3). As a result, the metal silicide film 23 is formed in a self-aligned manner on part of the inner side of the top surface 11c of the mesa portion 11.

[0039] 16, a barrier metal film 24 is formed on the first main surface 10a of the semiconductor layer 10 by, for example, sputtering (step S11 in FIG. 3). The barrier metal film 24 covers the metal silicide film 23 and extends beyond the pair of edges 11a, 11b of the mesa portion 11 to the interlayer insulating film 42. As will be described in detail later, in this barrier metal film forming step, the barrier metal film 24 can cover the pair of edges 11a, 11b of the mesa portion 11 without any discontinuities.

[0040] 17, a metal electrode film 25 is formed on the first main surface 10a of the semiconductor layer 10 by, for example, sputtering (step S12 in FIG. 3). As a result, a source electrode 26 is formed in which the metal silicide film 23, the barrier metal film 24, and the metal electrode film 25 are stacked.

[0041] Finally, a drain electrode 22 is formed on the second major surface 10b of the semiconductor layer 10, thereby completing the semiconductor device 1.

[0042] Here, a metal silicide film formation process in a comparative example in which the modified region 44 is not formed in the mesa portion 11 will be described. Figure 18 shows enlarged cross-sectional views of a main portion near one edge 11a of the mesa portion 11 in the comparative example, where (A) shows an enlarged cross-sectional view of the main portion after the metal film 46 has been formed, and (B) shows an enlarged cross-sectional view of the main portion after the metal silicide film 23 has been formed by annealing. The mesa portion 11 protrudes from the interlayer insulating film 42 embedded in the adjacent trench TR. Therefore, if the modified region 44 is not formed in the mesa portion 11, the metal silicide film 23 formed in the protruding mesa portion 11 will be formed on both the top surface 11c and the side surface 11d of the mesa portion 11, and will have eaves-shaped portions 23a that protrude laterally at the corners of the top surface 11c and the side surface 11d of the mesa portion 11. If the overhanging portion 23a is formed in the metal silicide film 23, the barrier metal film 24 may not adhere well to the area below the overhanging portion 23a in the subsequent barrier metal film formation process, resulting in a step discontinuity in the barrier metal film 24. If the barrier metal film 24 is discontinuous, nickel from the metal silicide film 23 may diffuse into the metal electrode film 25 through the step discontinuity in the barrier metal film 24, possibly increasing the resistance of the metal electrode film 25.

[0043] On the other hand, in the first manufacturing method disclosed in this specification, by forming the modified region 44 in part of the top surface 11c of the mesa portion 11, the metal silicide film 23 can be formed at a position away from the pair of edges 11a, 11b of the mesa portion 11. This prevents the formation of the eaves-shaped portion 23a in the metal silicide film 23, and also prevents the barrier metal film 24 from being discontinuous.

[0044] FIG. 19 shows an enlarged cross-sectional view of a main portion of the semiconductor device 1 according to this embodiment. The lower portion of the metal silicide film 23 has an inverted tapered shape that widens toward the lower surface 23b that contacts the top surface 11c of the mesa portion 11. This inverted tapered shape results from variations in the ion implantation angle when forming the modified region 44 using ion implantation technology. Taking into account variations in ion implantation, a sufficient distance D1 is ensured between the edge 11a of the mesa portion 11 and the metal silicide film 23, so that the edge 23c of the lower surface 23b of the metal silicide film 23 does not reach the side surface 11d of the mesa portion 11. By ensuring a sufficient distance D1, the metal silicide film 23 is prevented from being formed on the side surface 11d of the mesa portion 11, effectively preventing discontinuities in the barrier metal film 24.

[0045] (Second manufacturing method) Next, a second manufacturing method of the semiconductor device 1 will be described with reference to the manufacturing flow of Fig. 20 and Fig. 21 and Fig. 22. In comparison with the first manufacturing method, the second manufacturing method is characterized in that a shielding film forming step and a modified region forming step are performed between the etch-back step and the metal film forming step.

[0046] The steps from the trench formation step to the etch-back step are the same as those in the first manufacturing method. Next, as shown in Fig. 21, a shielding film 54 that exposes a partial region of the top surface 11c of the mesa portion 11 is formed on the first main surface 10a of the semiconductor layer 10 by, for example, CVD (step S6 in Fig. 19). The partial region of the top surface 11c of the mesa portion 11 exposed from the opening 54a of the shielding film 54 is spaced apart from the pair of edges 11a, 11b.

[0047] 22, atomic ions are implanted into a partial region of the top surface 11c of the mesa portion 11 exposed from the opening 54a of the shielding film 54 using, for example, an ion implantation technique, to form the modified region 44 (step S7 in FIG. 19). Thereafter, the processes from the metal film formation step to the metal electrode film formation step are the same as those in the first manufacturing method.

[0048] In the second manufacturing method disclosed in this specification, by forming the modified region 44 in part of the top surface 11c of the mesa portion 11, the metal silicide film 23 can be formed in a self-aligned manner at a position away from the pair of edges 11a, 11b of the mesa portion 11. This prevents the formation of the eaves-shaped portion 23a in the metal silicide film 23, and also prevents the barrier metal film 24 from being discontinuous.

[0049] Although the technology disclosed in this specification has been described using a semiconductor device with a self-aligned contact structure as an example, the technology disclosed in this specification is not limited to this example and can also be applied to semiconductor devices with various other structures.

[0050] 23 shows a semiconductor device 2 having a planar gate 130. The semiconductor device 2 has an n-type gate formed on the main surface of a semiconductor substrate 100. + a p-type drain region 112, a p-type body region 116, and an n + The planar gate 130 has a planar-type source region 118. The drain region 112, body region 116, and source region 118 are regions formed by ion implantation into a silicon carbide semiconductor layer provided to protrude from the main surface of the semiconductor substrate 100. The planar-type gate 130 has a gate insulating film 132 in contact with the upper surface of the body region 116, and a gate electrode 134 facing the body region 116 with the gate insulating film 132 interposed therebetween. A portion of the silicon carbide semiconductor layer in which the drain region 112 is formed is a portion for contacting the drain electrode 122 and is an example of a contact portion. A portion of the silicon carbide semiconductor layer in which the source region 118 is formed is a portion for contacting the source electrode 126 and is an example of a contact portion. A portion of the silicon carbide semiconductor layer in which the drain region 112 and the source region 118 are formed protrudes from the adjacent peripheral region (the region adjacent to the drain region 112 and the source region 118 when the portion of the silicon carbide semiconductor layer is viewed in plan; in this example, the semiconductor substrate 100) when the drain electrode 122 and the source electrode 126, which are to be contacted, are removed.

[0051] A drain electrode 122, which is a stack of a metal silicide film 123, a barrier metal film 124, and a metal electrode film 125, is in ohmic contact with the drain region 112. The metal silicide film 123 is provided at a position away from an edge 111a of a portion of the silicon carbide semiconductor layer where the drain region 112 is formed. The barrier metal film 124 covers the metal silicide film 123 and is in contact with the top surface and side surfaces that define the edge 111a of the portion of the silicon carbide semiconductor layer. Because the metal silicide film 123 is away from the edge 111a of the silicon carbide semiconductor layer, no overhanging portion of the metal silicide film 23 is formed at the edge 111a of the silicon carbide semiconductor layer. Therefore, the barrier metal film 124 can be well adhered to the edge 111a of the silicon carbide semiconductor layer without being discontinuous.

[0052] A source electrode 126, which is a stack of a metal silicide film 123, a barrier metal film 124, and a metal electrode film 125, is in ohmic contact with the source region 118. The metal silicide film 123 is provided at a position away from the edge 111b of the portion of the silicon carbide semiconductor layer where the source region 118 is formed. The barrier metal film 124 covers the metal silicide film 123 and is in contact with the top surface and side surfaces that define the edge 111b of the portion of the silicon carbide semiconductor layer. Because the metal silicide film 123 is away from the edge 111b of the portion of the silicon carbide semiconductor layer, no overhanging portion of the metal silicide film 123 is formed at the edge 111b of the portion of the silicon carbide semiconductor layer. Therefore, the barrier metal film 124 can be well adhered to the edge 111b of the portion of the silicon carbide semiconductor layer without being discontinuous.

[0053] Although specific examples of the present invention have been described in detail above, these are merely examples and do not limit the scope of the claims. The claimed technology includes various modifications and variations of the specific examples described above. While the above embodiments illustrate MOSFETs, the technology disclosed in this specification is also applicable to other types of semiconductor devices with trench gates, such as IGBTs (Insulated Gate Bipolar Transistors). Furthermore, while the above embodiments illustrate n-channel semiconductor devices, the technology disclosed in this specification is also applicable to p-channel semiconductor devices. Furthermore, the technical elements described in this specification or drawings exhibit technical utility alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology illustrated in this specification or drawings can achieve multiple objectives simultaneously, and achieving one of these objectives alone is technically useful. [Explanation of symbols]

[0054] 1: semiconductor device, 10: semiconductor layer, 11: mesa portion, 12: drain region, 14: drift region, 16: body region, 17: body contact region, 18: source region, 22: drain electrode, 23: metal silicide film, 24: barrier metal film, 25: metal electrode film, 26: source electrode, 30: trench gate, 32: gate insulating film, 34: gate electrode, 42: interlayer insulating film

Claims

1. a silicon carbide contact portion (11); a metal silicide film (23) provided on the top surface (11c) of the contact portion and spaced apart from at least a portion of the edges (11a, 11b) of the contact portion; a barrier metal film (24) that covers the metal silicide film and is in contact with a top surface and a side surface (11d) that define at least a portion of the edge of the contact portion.

2. 2. The semiconductor device according to claim 1, wherein an edge (23c) of a lower surface (23b) of said metal silicide film in contact with said top surface of said contact portion does not reach a side surface of said contact portion.

3. a trench gate (30) provided in a trench (TR) adjacent to the contact portion; an interlayer insulating film (42) provided in the trench and covering the trench-type gate, 3. The semiconductor device according to claim 1, wherein the interlayer insulating film is located below the top surface of the contact portion.

4. a silicon carbide contact portion (11); a metal silicide film (23) provided on the top surface (11c) of the contact portion and spaced apart from at least a portion of the edges (11a, 11b) of the contact portion; a barrier metal film (24) that covers the metal silicide film and is in contact with a top surface and a side surface (11 d) that define at least a portion of an edge of the contact portion, a modified region forming step of forming a modified region (44) in a partial region of the top surface of the contact portion, the modified region being a region modified from a hexagonal crystal to a cubic crystal or an amorphous crystal; a metal film deposition step of depositing a metal film (46) on the top surface of the contact portion; a metal silicide film forming step of forming the metal silicide film by reacting the modified region of the contact portion with the metal film; a metal film removing step of removing the metal film that has not reacted in the metal silicide film forming step; and forming a barrier metal film to cover the metal silicide film and extend beyond at least a portion of the edge of the contact portion.

5. 5. The method for manufacturing a semiconductor device according to claim 4, wherein said modified region forming step comprises forming said modified region by utilizing an ion implantation technique.

6. 6. The method for manufacturing a semiconductor device according to claim 5, wherein the modified region formed in the modified region forming step has an edge of its lower surface that does not reach a side surface of the contact portion.

7. 5. The method for manufacturing a semiconductor device according to claim 4, wherein the metal silicide film forming step comprises annealing at a temperature at which the metal silicide film is formed in the modified region of the contact portion and the metal silicide film is not formed in the unmodified region of the contact portion.

8. The semiconductor device includes: a trench gate (30) provided in a trench (TR) adjacent to the contact portion; an interlayer insulating film (42) provided in the trench and covering the trench-type gate, 8. The method for manufacturing a semiconductor device according to claim 4, wherein the interlayer insulating film is located below the top surface of the contact portion.

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