Digital-to-time converter

Abstract

To reduce power consumption of a circuit.SOLUTION: A digital-to-time converter receives an input signal, applies a delay corresponding to a control code, and generates an output signal. The digital-to-time converter includes: a slope generation circuit which includes a capacitor and a current source and generates a slope voltage; a pre-charge circuit which applies, to the capacitor, an analog voltage corresponding to the control code; a comparison circuit which compares the slope voltage with a threshold value and generates an output signal corresponding to a comparison result; and a control circuit controlling the slope generation circuit and the pre-charge circuit according to the input signal and the output signal. The control circuit repeats the following operations: (i) turning on the pre-charge circuit during a pre-charge period; (ii) transitioning to a slope period in response to the input signal, and turning off the pre-charge circuit and turning on the slope generating circuit during the slope period; and (iii) turning off the slope generating circuit in response to transition of the output signal.SELECTED DRAWING: Figure 23

Description

[Technical Field]

[0001] The present invention relates to a digital-to-time converter. [Background technology]

[0002] A phase locked loop (PLL) is used to generate a clock of any frequency by multiplying a reference clock. A digital PLL (D-PLL) is known as one type of PLL circuit.

[0003] 1 is a circuit diagram showing the basic architecture of a fractional-N D-PLL circuit 100R. The D-PLL circuit 100R receives a reference clock REF and a frequency control word (FCW) that specifies the multiplication factor, and generates an output clock OUT by multiplying the reference clock REF according to the FCW.

[0004] The clock signal generator includes a digital-to-time converter (DTC) 102, a time-to-digital converter (TDC) 104, a digital loop filter (DLF) 106, a digitally controlled oscillator (DCO) 108, a buffer 110, a multi-modulous divider (MMD) 112, a controller 114, and a retiming circuit 116.

[0005] DCO108 is a digital control data CNTThe output clock OUT of the DCO 108 is input to the MMD 112 via the buffer 110. The MMD 112 divides the output clock OUT by a division ratio set by the controller 114. The controller 114 is designed based on the architecture of a ΔΣ modulator. In a fractional N type PLL circuit, the controller 114 switches the division ratio of the MMD 112 by multiple integer values ​​in a time-division manner to obtain a fractional multiplication ratio. The reciprocal of the average value of the division ratios set in the MMD 112 is the multiplication ratio N of the D-PLL circuit 100R. F This becomes:

[0006] The divided clock DIV is input to the retiming circuit 116. The retiming circuit 116 retimes the divided clock DIV using the output clock CKV that has passed through the buffer 110, and generates the feedback clock FB.

[0007] The DTC 102 applies a delay set by the controller 114 to the reference clock REF and outputs the reference clock REFA. The amount of delay is selected according to the division ratio applied to the MMD 112.

[0008] The TDC 104 converts the time difference between the reference clock REFA and the feedback clock FB into a digital value. The DLF 106 removes high frequency components from the output of the TDC 104 and converts them into control data D CNT Generate.

[0009] The above is the basic architecture of the D-PLL circuit 100R. FIG. 2 is a time chart of the D-PLL circuit 100R of FIG. 1. The divided clock DIV is retimed by the clock CKV. The sampling delay τ SAM Therefore, the edge E1 of the feedback clock FB is shifted by τ SAMThe feedback loop consisting of the TDC 104 and DLF 106 applies feedback so that the time difference between the edge E3 of the reference clock REFA and the edge E1 of the feedback clock FB becomes zero, and the phase is locked. At this time, the frequency of the output clock OUT (and CKV) of the DCO 108 is N times the frequency of the reference clock REFA (and REF). F It doubles. Summary of the Invention [Problem to be solved by the invention]

[0010] 1 has the advantages of high frequency accuracy and robustness against frequency interference, but has the problem of high power consumption because the MMD 112 and the retiming circuit 116 continue to operate in synchronization with the high-frequency clock CKV.

[0011] The present invention has been made in view of the above-mentioned problems, and one exemplary purpose of an embodiment of the present invention is to provide a D-PLL circuit with reduced power consumption. [Means for solving the problem]

[0012] A related aspect of the present invention relates to a phase-locked loop circuit that receives a first reference clock and generates an output clock. The phase-locked loop circuit includes a delay circuit that delays the first reference clock to generate a second reference clock, a feedback circuit that generates a control signal corresponding to a phase difference between the second reference clock and a feedback clock, an oscillator that oscillates at a frequency corresponding to the control signal to generate an output clock, and a frequency divider that can be switched on and off and divides the output clock when in the on state. This phase-locked loop circuit can be switched between a first mode and a second mode. In the first mode, the feedback clock is a signal obtained by retiming the output of the frequency divider with the output clock. In the second mode, the feedback clock is a signal obtained by retiming the first reference clock with the output clock.

[0013] A related aspect of the present invention relates to a digital phase-locked loop circuit that receives an input reference clock and a frequency control word and generates an output clock. The digital phase-locked loop circuit includes: a digital-to-time converter that receives the input reference clock and generates a first reference clock; a delay circuit that delays the first reference clock and generates a second reference clock; a time-to-digital converter that converts the phase difference between the second reference clock and a feedback clock into a digital signal; a digitally controlled oscillator that oscillates at a frequency corresponding to the output of the time-to-digital converter and generates an output clock; and a frequency divider that is switchable between on and off and, when on, divides the output clock by a division ratio corresponding to the frequency control word. The digital phase-locked loop circuit is switchable between a first mode and a second mode. In the first mode, the feedback clock is a signal obtained by retiming the output of the frequency divider with the output clock, and in the second mode, the feedback clock is a signal obtained by retiming the first reference clock with the output clock.

[0014] A related aspect of the present invention is a digitally controlled oscillator. The digitally controlled oscillator includes an upper unit and a lower unit connected in series between a power supply line and a ground line, and a variable capacitor connected to at least one of the upper unit and the lower unit. The upper unit and the lower unit each include a pair of cross-coupled circuit elements and an inductor connected to the pair of circuit elements. The inductors of the upper unit and the lower unit are coupled to form a transformer.

[0015] One aspect of the present invention is a digital-to-time converter that receives an input signal, applies a delay corresponding to a control code, and generates an output signal. The digital-to-time converter includes: a slope generation circuit including a capacitor and a current source and generating a slope voltage; a precharge circuit that applies an analog voltage corresponding to the control code to the capacitor; a comparison circuit that compares the slope voltage with a threshold and generates an output signal corresponding to the comparison result; and a control circuit that controls the slope generation circuit and precharge circuit according to the input signal and output signal. The control circuit (i) turns on the precharge circuit during the precharge period, (ii) transitions to the slope period in response to the input signal, turns off the precharge circuit and turns on the slope generation circuit during the slope period, and (iii) repeatedly turns off the slope generation circuit in response to a transition of the output signal.

[0016] Any combination of the above components or mutual substitution of the components or expressions of the present invention between methods, devices, systems, etc. are also valid aspects of the present invention. [Effects of the Invention]

[0017] According to an embodiment of the present invention, power consumption can be reduced. [Brief explanation of the drawings]

[0018] [Figure 1] FIG. 1 is a circuit diagram showing the basic architecture of a fractional-N D-PLL circuit. [Figure 2] 2 is a time chart of the D-PLL circuit of FIG. 1; [Figure 3] 1 is a circuit diagram showing the basic architecture of a D-PLL circuit according to an embodiment. [Figure 4] FIG. 10 is an equivalent circuit diagram of a D-PLL circuit in a subsampling mode (EN=0). [Figure 5] 10 is a time chart of the D-PLL circuit in the subsampling mode. [Figure 6]6(a) and 6(b) are time charts showing the operation of the D-PLL circuit in the sampling mode and the sub-sampling mode in comparison. [Figure 7] FIG. 10 is a waveform diagram of the output frequency fOUT of the D-PLL circuit in the sub-sampling mode. [Figure 8] FIG. 1 is a circuit diagram of a D-PLL circuit according to a first embodiment. [Figure 9] 9(a) and 9(b) are diagrams for explaining the operation of the mode selector in the D-PLL circuit of FIG. [Figure 10] FIG. 10 is a circuit diagram of a D-PLL circuit according to a second embodiment. [Figure 11] FIG. 10 is a diagram illustrating the operation of a mode selector in the D-PLL circuit. [Figure 12] 9 is a waveform diagram of the output frequency fOUT of the D-PLL circuit of FIG. 8. [Figure 13] FIG. 10 is a circuit diagram of a D-PLL circuit according to a third embodiment. [Figure 14] 14(a) and 14(b) are circuit diagrams of a conventional DCO. [Figure 15] FIG. 1 is a circuit diagram showing the basic architecture of a DCO according to an embodiment. [Figure 16] FIG. 16 is an equivalent circuit diagram of the DCO of FIG. 15. [Figure 17] FIG. 10 is a diagram illustrating the relationship between a bias current IBIAS and an amplitude VAMP of an output signal. [Figure 18] FIG. 10 is a circuit diagram of a DCO according to a first modification. [Figure 19] FIG. 10 is a circuit diagram of a DCO according to a second modification. [Figure 20] 20(a) to 20(f) are circuit diagrams showing further modified examples of the DCO. [Figure 21] FIG. 1 is a circuit diagram of a conventional DTC. [Figure 22] FIG. 22 is an operational waveform diagram of the DTC of FIG. 21. [Figure 23] FIG. 2 is a circuit diagram of a DTC according to an embodiment. [Figure 24] FIG. 2 is a circuit diagram showing an example of the configuration of a control circuit; [Figure 25] 24 is a time chart illustrating the operation of the DTC of FIG. 23. [Figure 26] 1A and 1B are diagrams showing operational waveforms of a DTC according to the present embodiment (i) and an operational waveform of a conventional DTC (ii). DETAILED DESCRIPTION OF THE INVENTION

[0019] (Outline of the embodiment) 1. One embodiment disclosed herein relates to a phase-locked loop circuit that receives a first reference clock and generates an output clock. The phase-locked loop circuit includes: a delay circuit that delays the first reference clock to generate a second reference clock; a feedback circuit that generates a control signal corresponding to a phase difference between the second reference clock and a feedback clock; an oscillator that oscillates at a frequency corresponding to the control signal to generate an output clock; and a frequency divider that is switchable between on and off and divides the output clock when in the on state. The phase-locked loop circuit is switchable between a first mode and a second mode. In the first mode, the feedback clock is a signal obtained by retiming the output of the frequency divider with the output clock. In the second mode, the feedback clock is a signal obtained by retiming the first reference clock with the output clock.

[0020] According to this embodiment, by selecting the second mode, the operation of the frequency divider is stopped and phase synchronization is performed using the second reference clock as a feedback clock, thereby reducing power consumption. Also, by selecting the first mode as needed, if phase synchronization is lost, it is possible to restore the phase synchronization state.

[0021] In one embodiment, the phase locked loop may include a mode controller that generates an enable signal that indicates the first mode or the second mode, a multiplexer that receives the output of the frequency divider and the first reference clock and selects one of them in response to the enable signal, and a retiming circuit that retimes the output of the multiplexer using the output clock. The on / off of the frequency divider may be controlled in response to the enable signal, and the output of the retiming circuit may be the feedback clock.

[0022] In one embodiment, the phase locked loop circuit further includes a dead zone detector that determines whether a phase error between the second reference clock and the feedback clock is within a dead zone, and the first mode and the second mode may be determined based on an output of the dead zone detector, thereby preventing the phase locked loop circuit from entering a mode in which phase locking is not achieved.

[0023] In one embodiment, the dead zone detector may include a phase frequency detector that compares the phase difference or frequency difference between the second reference clock and the feedback clock and outputs a pulse based on the comparison result, and a determination unit that generates a phase error based on the output of the phase frequency detector and determines whether the phase error is included in the dead zone.

[0024] In one embodiment, the digital phase-locked loop may further include a frequency-locked loop that monitors the relationship between the frequency of the output clock and the frequency of the input reference clock and detects a frequency error in which the frequency of the output clock deviates from a target frequency determined based on the division ratio of the divider. The first and second modes may be determined according to the output of the frequency-locked loop. This makes it possible to prevent phase locking at an incorrect frequency.

[0025] The frequency locked loop may include a counter that counts the output clock for a period that is K times the period of the input reference clock (K is an integer). A frequency error may be detected based on the count value of the counter and a value obtained by multiplying the multiplication ratio, which is the reciprocal of the division ratio, by K.

[0026] In one embodiment, the phase locked loop may further include a duty cycle controller that generates a control pulse having a predetermined duty ratio. The frequency locked loop may operate intermittently in response to the control pulse. By operating the frequency locked loop intermittently, an increase in power consumption can be suppressed.

[0027] In one embodiment, the digital phase-locked loop may further include a phase frequency detector that compares the phase difference or frequency difference between the second reference clock and the feedback clock and outputs a pulse based on the comparison result, and a PLL (Phase Locked Loop) circuit that operates in the first mode and feedback-controls the frequency of the digitally controlled oscillator based on the output of the phase frequency detector. The accuracy of the feedback loop including the phase frequency detector and the PLL circuit may be coarser than the accuracy of the feedback circuit. This allows for quick phase locking from an unlocked state to a locked state.

[0028] The phase-locked loop may be a digital phase-locked loop. The feedback circuit may include a time-to-digital converter that converts the phase difference between the second reference clock and the feedback clock into a digital signal. The oscillator may be a digitally controlled oscillator that oscillates at a frequency corresponding to the output of the time-to-digital converter.

[0029] The phase locked loop may be a fractional divider. The divider may be a multi-modulus divider. The phase locked loop may further include a digital-to-time converter that receives an input reference clock and generates a first reference clock, and a controller that controls the digital-to-time converter and the multi-modulus divider in response to a frequency control word that specifies a frequency of the output clock.

[0030] 2. One aspect of the present invention is a digitally controlled oscillator. The digitally controlled oscillator includes an upper unit and a lower unit connected in series between a power supply line and a ground line, and a variable capacitor connected to at least one of the upper unit and the lower unit. The upper unit and the lower unit each include a pair of cross-coupled circuit elements and an inductor connected to the pair of circuit elements. The inductors of the upper unit and the lower unit are coupled to form a transformer.

[0031] According to this configuration, the bias current required to obtain the same amplitude can be reduced by the gain amplification effect of the transformer, or the amplitude can be increased when the bias current is maintained.

[0032] At least one of the upper unit and the lower unit may be N-type, in which the pair of circuit elements is an N-channel Metal Oxide Semiconductor (NMOS) transistor, or both the upper unit and the lower unit may be N-type.

[0033] At least one of the upper unit and the lower unit may be a P-type in which the pair of circuit elements is a PMOS (P-channel Metal Oxide Semiconductor) transistor.

[0034] At least one of the upper unit and the lower unit may be of a complementary metal oxide semiconductor (CMOS) type in which a pair of circuit elements is a CMOS inverter.

[0035] The digitally controlled oscillator may further include a bias current source inserted between the power supply line and the ground line.

[0036] The digitally controlled oscillator may further include a capacitor connected to the connection node between the upper unit and the lower unit.

[0037] 3. Yet another embodiment of the present invention is a digital-to-time converter. This digital-to-time converter receives an input signal, applies a delay corresponding to a control code, and generates an output signal. The digital-to-time converter includes: a slope generation circuit including a capacitor and a current source and generating a slope voltage; a precharge circuit that applies an analog voltage corresponding to the control code to the capacitor; a comparison circuit that compares the slope voltage with a threshold and generates an output signal corresponding to the comparison result; and a control circuit that controls the slope generation circuit and precharge circuit according to the input signal and the output signal. The control circuit repeats the following operations: (i) turning on the precharge circuit during the precharge period; (ii) transitioning to the slope period in response to the input signal, turning off the precharge circuit and turning on the slope generation circuit during the slope period; and (iii) turning off the slope generation circuit in response to a transition of the output signal.

[0038] According to this embodiment, unnecessary charging and discharging of the capacitor is suppressed, thereby reducing power consumption.

[0039] The comparison circuit may be configured to be switchable between on and off, and the control circuit may turn off the comparison circuit during the precharge period.

[0040] (Embodiment) The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, parts, and processes shown in each drawing will be given the same reference numerals, and redundant explanations will be omitted where appropriate. Furthermore, the embodiments are illustrative and do not limit the invention, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

[0041] In this specification, "a state in which component A is connected to component B" includes not only a case in which component A and component B are directly physically connected to each other, but also a case in which component A and component B are indirectly connected to each other via other components that do not substantially affect the electrical connection between them or that do not impair the function or effect achieved by their connection.

[0042] Similarly, "a state in which component C is provided between component A and component B" includes not only cases in which components A and C, or components B and C, are directly connected, but also cases in which they are indirectly connected via other components that do not substantially affect the electrical connection state between them or impair the functions or effects achieved by their combination.

[0043] (D-PLL circuit) 3 is a circuit diagram showing the basic architecture of a D-PLL circuit 100 according to an embodiment. The D-PLL circuit 100 is a fractional division type PLL circuit that receives an input reference clock REF and a frequency control word FCW and generates a REF The output clock OUT has a frequency that is a fractional multiple of the frequency F of the input signal.

[0044] 1, the D-PLL circuit 100 further includes a multiplexer 120, a delay circuit 122, and a mode selector 130. The MMD 112A is configured to be switchable between enable and disable (on / off).

[0045] The D-PLL circuit 100 can switch between two modes (referred to as sampling mode and sub-sampling mode), and the two modes are selected according to an enable signal EN. When the enable signal EN is 1 (high), the D-PLL circuit 100 is set to the sampling mode, and when the enable signal EN is 0 (low), the D-PLL circuit 100 is set to the sub-sampling mode.

[0046] The multiplexer 120 receives the divided clock DIV, which is the output of the MMD 112, and the first reference clock REFA, which is output by the DTC 102, and selects one of them according to the enable signal EN. The output of the multiplexer 120 is retimed by the retiming circuit 116 to become the feedback clock FB. For the retiming, the output clock CKV via the buffer 110 can be used. Note that if the output impedance of the DCO 108 is sufficiently low, the buffer 110 may be omitted.

[0047] Here, when the enable signal EN is 1 (high), the feedback clock FB is generated based on the divided clock DIV, and when it is 0 (low), the feedback clock FB is generated based on the first reference clock REFA.

[0048] The function of the MMD 112A is the same as that of FIG. 1, but it is configured so that it can be switched on and off in response to an enable signal EN. For example, the MMD 112A includes a gate circuit 113 in addition to the MMD 112 of FIG. 1. The gate circuit 113 is inserted in the preceding stage of the MMD 112 and gates the clock signal CKV in response to the enable signal EN. That is, when the enable signal EN is 1, the clock CKG that has passed through the gate circuit 113 is input to the MMD 112, enabling the MMD 112. When the EN signal is 0, the clock CKG is fixed low, and therefore the MMD 112 is disabled.

[0049] The delay circuit 122 is inserted after the DTC 102 and adds a delay τ FB and outputs the second reference clock REFB. The TDC 104 applies feedback so that the edges of the second reference clock REFB and the feedback clock FB coincide with each other.

[0050] The mode selector 130 generates an enable signal EN based on the operating state of the D-PLL circuit 100 and controls the mode of the D-PLL circuit 100 .

[0051] The above is the basic configuration of the D-PLL circuit 100. Next, its operation will be explained. FIG. 4 is an equivalent circuit diagram of the D-PLL circuit 100 in sub-sampling mode (EN=0). In sub-sampling mode, the operation of the MMD 112 stops. Because the frequency of the first reference clock REFA and the frequency of the divided clock DIV are equal, the first reference clock REFA is input to the retiming circuit 116 instead of the divided clock DIV. The retiming circuit 116 then retimes the first reference clock REFA at the edges of the clock signal CKV to generate the feedback clock FB.

[0052] 5 is a time chart of the D-PLL circuit 100 in the sub-sampling mode. In the sub-sampling mode, the first reference clock REFA is retimed by the clock CKV instead of the divided clock DIV. The sampling delay τ SAM Therefore, the edge E1 of the feedback clock FB is shifted by τ SAM The feedback loop including the TDC 104 and the DLF 106 applies feedback so that the time difference between the edge E4 of the second reference clock REFB and the edge E1 of the feedback clock FB becomes zero, thereby locking the phase.

[0053] In the sub-sampling mode, since the feedback clock FB is generated by retiming the first reference clock REFA, the edge of the feedback clock FB lags behind the edge of the first reference clock REFA. Therefore, even if feedback is applied, the edge (phase) of the feedback clock FB cannot be aligned with the edge of the first reference clock REFA. Therefore, in consideration of the phase delay when generating the feedback clock FB by retiming, the delay amount τ of the delay circuit 122 is set to offset it. FB By determining the phase of the second reference clock REFB (=REFA+τ FB ) and the phase of the feedback clock FB delayed by retiming (=REFA+Δt+τSAM ) is included within one cycle of the clock signal CKV, making it possible to achieve phase synchronization.

[0054] 6(a) and 6(b) are time charts showing the operation of the D-PLL circuit 100 in sampling mode and sub-sampling mode in comparison. The operation in the sampling mode of FIG. 6(a) is the same as that of FIG. 2. The difference is that the phase of the feedback clock FB is locked based on the phase of the second reference clock REFB, not the first reference clock REFA. The operation in the sub-sampling mode of FIG. 6(b) is the same as that of FIG. 5.

[0055] The above is the operation of the D-PLL circuit 100. Next, we will explain the advantages of this mode. When the D-PLL circuit 100 operates in subsampling mode, the operation of the MMD 112 is stopped, which allows for a significant reduction in power consumption compared to sampling mode.

[0056] In sub-sampling mode, the frequency of the output clock OUT is f OUT However, the target value (=f REF × N), phase synchronization can be maintained with low power consumption, but OUT ≠f REF From the state of ×N, f OUT =f REF ×N state. This is because the MMD112 is not used and the multiplication ratio N is not involved in the circuit operation.

[0057] Therefore, the mode selector 130 monitors the operating state of the D-PLL circuit 100, and when the D-PLL circuit 100 is started up or when the phase synchronization is lost, the enable signal EN is temporarily set to high (1) to set the D-PLL circuit 100 in the sampling mode. OUT =f REF ×N states.

[0058] The above is the basic architecture of the D-PLL circuit 100 according to the embodiment. Next, specific implementations of the D-PLL circuit 100 will be described with reference to several examples.

[0059] First, problems that may occur in the sub-sampling mode will be described. Figure 7 shows the output frequency f of the D-PLL circuit 100 in the sub-sampling mode. OUT This is a waveform diagram (simulation) of f REF = 10MHz, N = 240 + 0.5. In the phase-locked state, the output frequency f OUT is stabilized to 2405MHz (=2.405GHz).

[0060] Figure 7 shows waveforms (i) to (iii) when frequency interference of -1 MHz, +6 MHz, and +11 MHz is injected. As shown in (i), when frequency interference of -1 MHz is introduced, the phase lock state can be maintained.

[0061] In subsampling mode, the edges of the clock CKV used for retiming move back and forth due to the wide first reference clock REFA being retimed by the clock CKV. This can result in false locking at N'=241+0.5, as shown in Figure 7(ii). Alternatively, phase synchronization can be lost, resulting in frequency oscillation, as shown in Figure 7(iii).

[0062] That is, the mode selector 130 must be implemented so as to monitor the state of the D-PLL circuit 100 and control the mode of the D-PLL circuit 100 so as to avoid situations (ii) and (iii) in FIG.

[0063] Example 1 8 is a circuit diagram of a D-PLL circuit 100A according to Example 1. In this example, a mode selector 130A is configured to be able to detect a phase-unsynchronized state such as that shown by the waveform (iii) in FIG.

[0064] The mode selector 130A includes a dead zone detector 140 and a state machine 132. The dead zone detector 140 detects the phase error t between REFB and FB. ERR But the dead zone DZ If the signal is outside the range, the detection signal ODZ (Out of Dead Zone) is at a first level (for example, high, 1), and if the signal is within the range, the detection signal ODZ (Out of Dead Zone) is at a second level (for example, low, 0).

[0065] The configuration of the dead zone detector 140 is not particularly limited, but includes, for example, a phase frequency detector (PFD) 142 and a determination unit 144. The PFD 142 compares the phase difference or frequency difference between the second reference clock REFB and the feedback clock FB, and outputs two pulses (an UP pulse and a DN pulse) based on the comparison result.

[0066] The decision unit 144 receives the output UP / DN of the PFD 142 and determines the phase error t ERR and generate the phase error t ERR is included in the dead zone and outputs an ODZ signal.

[0067] The state machine 132 synchronizes the ODZ signal with the reference clock REF to generate the enable signal EN. The state machine 132 can be configured with a flip-flop.

[0068] The above is the configuration of the D-PLL circuit 100A. Next, its operation will be described. Figures 9(a) and 9(b) are diagrams illustrating the operation of the mode selector 130A in the D-PLL circuit 100A of Figure 8. Figure 9(a) shows the input / output characteristics of the dead zone detector 140.

[0069] 9(b) shows the overall operation of the D-PLL circuit 100A. Before time t0, the D-PLL circuit 100A operates in the sub-sampling mode. If, for some reason, the phase error t ERR Dead ZoneDZ When the phase error t falls outside the range, the ODZ signal periodically goes high and the enable signal EN goes high (1). As a result, the mode switches to sampling mode. When operating in sampling mode, the phase error t ERR becomes smaller, and at time t2, the dead zone t DZ When the ODZ signal returns to low, the enable signal EN goes low, and the device enters sub-sampling mode.

[0070] The above is the operation of the D-PLL circuit 100 A. By implementing the dead zone detector 140 and running it in the background, it is possible to prevent the situation where phase synchronization is not possible, as shown in (iii) of FIG.

[0071] Example 2 10 is a circuit diagram of a D-PLL circuit 100B according to Example 2. In this example, a mode selector 130B is configured to be able to detect frequency jumps of an integer multiple, as shown by the waveform (ii) in FIG.

[0072] The mode selector 130B includes an intermittent operation frequency locked loop (FLL) 150 in addition to a dead zone detector 140 and a state machine 132. The intermittent operation FLL is also referred to as a DC-FLL (Duty Cycled FLL).

[0073] The intermittent operation FLL 150 includes an FLL 152 and a duty cycle controller 154 .

[0074] The FLL 152 is configured to be switchable between enabled and disabled states. In the enabled state, the FLL 152 monitors the relationship between the frequency of the clock signal CKV(OUT) and the frequency of the reference clock REF, and asserts (e.g., high) the frequency lock error signal FLE if the frequency of the clock signal CKV deviates from the target frequency determined based on the FCW. Conversely, the FLL 152 monitors how many times the period of the reference clock REF is compared with the period of the clock signal CKV, and determines whether or not this matches the multiplication ratio determined based on the FCW. The state machine 132 switches the enable signal EN to high in response to the assertion of the frequency lock error signal FLE.

[0075] The configuration of the FLL 152 is not limited, but may include, for example, a frequency detector 160, a subtractor 170, and a comparator 172. The frequency detector 160 counts the clock signal CKV for an integer multiple (K=4 in this example) of the period of the reference clock REF. In a frequency-locked state, this count value becomes K times the FCW (multiplication factor).

[0076] The frequency detector 160 includes a frequency divider 162, D flip-flops 164 and 168, and a counter 166. The frequency divider 162 divides the reference clock REF by 1 / K (K=4). The divided clock is synchronized with the clock CKV in the flip-flop 164. The counter 166 counts the number of pulses of the clock CKV. The flip-flop 168 captures the count value of the counter 166 in synchronization with the output of the frequency divider 162. The output of the flip-flop 168 indicates how many pulses of the clock CKV are contained in a period that is K times the period of the reference clock REF.

[0077] A subtractor 170 calculates the difference (frequency error) between the output of the flip-flop 168 and its target value (K×FCW). A comparator 172 compares the output of the subtractor 170 with a threshold value, and asserts a frequency lock error signal FLE if the frequency error exceeds a tolerance.

[0078] FLL152 is a high frequency signal (f OUTSince the FLL 152 includes a counter 166 that operates at a frequency of 1.5 GHz (=2.4 GHz), power consumption increases if it is operated constantly. Therefore, a duty cycle controller 154 generates a control pulse DC having a predetermined duty ratio, and the FLL 152 operates intermittently based on this control pulse DC. For example, the duty ratio can be set to 1% or less, for example, about 0.5%. This reduces the power consumption of the FLL 152.

[0079] The above is the configuration of the D-PLL circuit 100B. Next, its operation will be described. Figure 11 is a diagram illustrating the operation of the mode selector 130B in the D-PLL circuit 100B.

[0080] The intermittent operation FLL 150 repeatedly turns on and off at a predetermined cycle, and if a frequency error is detected during the on period, it transitions to sampling mode and operates to lock the frequency.

[0081] 11 shows the power consumption of the D-PLL circuit 100B. The power consumption during the suspension period of the intermittent operation FLL 150 is, for example, 262 μW. During the operation period of the intermittent operation FLL 150, the power consumption of the D-PLL circuit 100B increases (for example, to 762 μW). However, when the duty ratio is 0.5%, the average power consumption P AVE The power consumption is 265 μW, which is only an increase of 3 μW.

[0082] The above is the operation of the D-PLL circuit 100B. The mode selector 130B can detect frequency jumps of integer multiples, and in that case, by operating in sampling mode, it is possible to prevent continued phase synchronization in an erroneous state as shown in Figure 7(ii). Note that the mode selector 130B in Figure 10 includes a dead zone detector 140 in addition to the intermittent operation FLL 150, and therefore, like the first embodiment, it is possible to prevent the state shown in Figure 7(iii).

[0083] FIG. 12 shows the output frequency f OUT7 shows waveforms (simulation) of the above. As in Figure 7, waveforms (i) to (iii) are shown when frequency interference of -1 MHz, +6 MHz, and +11 MHz is injected. As shown in (i), when frequency interference of -1 MHz is introduced, the phase synchronization state can be maintained.

[0084] As shown in (ii), when +11 MHz frequency interference is introduced, the intermittent operation FLL 150 dead zone detector 140 detects the abnormal state and switches to sampling mode, allowing the system to return to the correct phase synchronization state. Note that in waveform (ii), a high frequency state persists for a while, but this is a detection delay caused by the intermittent operation of the intermittent operation FLL 150.

[0085] As shown in (iii), when a +6 MHz frequency disturbance is introduced, the dead zone detector 140 detects the abnormal state and switches to the sampling mode, thereby enabling the correct phase synchronization state to be restored.

[0086] Example 3 FIG. 13 is a circuit diagram of a D-PLL circuit 100C according to a third embodiment. The D-PLL circuit 100C further includes a coarse second PLL circuit 180. The second PLL circuit 180 receives a clock CKG when the enable signal EN is high. The second PLL circuit 180 operates while the enable signal EN is high, i.e., in subsampling mode, and performs feedback control of the frequency of the DCO 108 based on the output (UP / DN) of the PFD 182. In other words, the D-PLL circuit 100C of FIG. 13 includes a fine feedback loop including the TDC 104 and DLF 106 and a coarse feedback loop including the PFD 182 and the second PLL 180, which operate in parallel. The PFD 182 can be the PFD 142 built into the mode selector 130. In the third embodiment, the configuration of the mode selector 130 is not limited, and the configuration of the first or second embodiment or other configurations can be adopted.

[0087] According to the third embodiment, by adding the second coarse PLL 180, the phase acquisition speed can be increased in the sub-sampling mode.

[0088] Next, a modification of the D-PLL circuit 100 will be described.

[0089] (Variation 1) A circuit in which the dead zone detector 140 is omitted from the mode selector 130B in Fig. 10 is also effective as an embodiment. In this case, errors in which phase synchronization is not achieved can be dealt with by a different method.

[0090] (Variation 2) Although the embodiment has been described with reference to a fractional-N PLL, the present invention is not limited to this and can also be applied to an integer-N PLL. In this case, the DTC 102 and the controller 114 can be deleted, and the MMD 112 can be replaced with a simple divider.

[0091] (Variation 3) The present invention can also be applied to analog PLL circuits, in which case the set of TDC 104, DLF 106, and DCO 108 can be replaced with a phase frequency detector (PFD), a charge pump circuit, an analog loop filter, and a voltage-controlled oscillator (VCO).

[0092] (DCO) DCO is an important element technology in the D-PLL circuit 100 and other applications. Figures 14(a) and 14(b) are circuit diagrams of a conventional DCO 200R. The DCO 200R is a CMOS oscillator and includes a pair of inverters 202 and 204 whose inputs and outputs are cross-coupled, a tank circuit 206 provided between the outputs of the inverter pair 202 and 204, and a current source 208 that supplies a bias current to the inverter pair 202 and 204. The tank circuit 206 is a parallel resonant circuit including an inductor L and a variable capacitor C. Resistor Rs is the series resistance component of the inductor L. The capacitance value of the variable capacitor C is digitally controllable, and the DCO 200R oscillates at an oscillation frequency that corresponds to the impedance of the tank circuit 206.

[0093] 14(b) shows an equivalent circuit of the tank circuit 206. The equivalent parallel resistance R TANK is R TANK =ωL·Q, where Q is the quality factor of the LC resonant circuit in Figure 12, and is expressed as Q=ωL / Rs.

[0094] The amplitude V of the DCO200R output in Figure 14(a) AMP is expressed by equation (1), and the equivalent parallel resistance R TANK and bias current I BIAS is proportional to. V AMP ≒4 / π×R TANK ×I BIAS …(1)

[0095] To reduce the power consumption of the DCO200R, the bias current I BIAS However, to stably oscillate the DCO200R, the output amplitude V AMP Since it is necessary to increase the bias current I BIAS In exchange for a decrease in resistance R TANK However, when the tank circuit 206 is made into an MMIC (Monolithic Microwave Integrated Circuit) and integrated on the same chip as the CMOS circuit, the resistance RTANK is at most 200 to 1000 Ω.

[0096] Therefore, the power consumption of the DCO 200R in Figure 14(a) is limited by the impedance of the tank circuit. Below, we will explain a new DCO that can further reduce power consumption.

[0097] 15 is a circuit diagram showing the basic architecture of a DCO 200 according to an embodiment. The DCO 200 comprises an upper unit 210 and a lower unit 220. The upper unit 210 includes a pair of cross-coupled circuit elements 212 and 214 and an inductor (primary winding) L1 with a tap T1. The inductor L1 is connected between the outputs (between the inputs) of the pair of circuit elements 212 and 214. The tap T1 of the inductor L1 is connected to a power supply V DD or to a bias current source as described below.

[0098] In FIG. 15, circuit elements 212 and 214 are NMOS transistors, and the sources of the NMOS transistors are connected to a reference node 216 .

[0099] Similarly, the lower unit 220 includes a cross-coupled pair of circuit elements 222, 224 and an inductor L2 (secondary winding) with a tap T2, which is connected between the outputs (between the inputs) of the pair of circuit elements 222, 224.

[0100] Tap T2 of the lower unit 220 is connected to the reference node 216 of the upper unit 210. This reference node 216 is connected to a capacitor 242, which is a virtual ground. This node is designated as CEN.

[0101] The circuit elements 222 and 224 are also NMOS transistors, and the sources of the NMOS transistors are connected to a reference node 226. The reference node 226 is also connected to a bias current source 240.

[0102] An upper unit 210 and a lower unit 220 in FIG. 15 in which the cross-coupled circuit elements are NMOS transistors are called an N-type unit.

[0103] The inductor L1 of the upper unit 210 and the inductor L2 of the lower unit 220 are coupled to form a transformer 230. The coupling coefficient between the winding Ls of the inductor L1 and the winding Lp of the inductor L2 is defined as k.

[0104] A variable capacitor Cv is connected to the upper unit 210. The variable capacitor Cv forms an LC tank circuit together with the transformer 230, and the DCO 200 oscillates at a frequency according to the capacitance value of the variable capacitor Cv. The output may be taken from any location, but may be taken from the drains of the NMOS transistors 222 and 224 of the lower unit 220, for example.

[0105] The above is the basic configuration of the DCO 200. Next, its operation will be explained. Figure 16 is an equivalent circuit diagram of the DCO 200 in Figure 15. N is the passive gain, and is expressed as N = k√(Ls / Lp) using the coupling coefficient k.

[0106] In FIG. 16, the amplitude V AMP is expressed by equation (2). V AMP ≒4 / π×I BIAS ×R TANKP ×G TF …(2) G TF is the gain of the transformer 230 and is expressed by equation (3). G TF =k 2 Ls / Lp+k√(Ls / Lp)+R TANKS / R TANKP …(3) G TF can take a value of 2 or more, and in the circuit designed by the inventors, G TF =4.35.

[0107] Figure 17 shows the bias current I BIAS and the amplitude of the output signal V AMP This figure (simulation) shows the relationship between (i) and (ii). (i) shows the characteristics of the DCO200 in Figure 15, and (ii) shows the characteristics of the conventional DCO200R. When compared at the same bias current, the DCO200 in Figure 15 can increase amplitude by 46% compared to the conventional DCO200R. In other words, the bias current required to obtain the same amplitude can be significantly reduced.

[0108] Next, a modified example of the DCO 200 will be described.

[0109] Fig. 18 is a circuit diagram of a DCO 200A according to Modification 1. In Modification 1, the lower unit 220 is N-type like the lower unit 220 in Fig. 15, but the upper unit 210 is replaced with a P-type unit.

[0110] The P-type unit has an inverted configuration, with the pair of circuit elements 212, 214 in the N-type unit replaced with PMOS transistors. Specifically, an inductor L1 is connected between the drains of the PMOS transistors 212, 214, and the tap of the inductor L1 is connected to the virtual ground line CEN. The sources of the PMOS transistors 212, 214 form a reference node 216, and the power supply voltage V DD is supplied.

[0111] 19 is a circuit diagram of a DCO 200B according to Modification 2. In Modification 2, upper unit 210 and lower unit 220 are configured as CMOS type (push-pull type) units.

[0112] In the CMOS type unit, the pair of cross-coupled circuit elements is a CMOS inverter, and the tap of the inductor L can be omitted.

[0113] Figures 20(a) to 20(f) are circuit diagrams showing further modifications of the DCO 200. In Figures 20(a) to 20(f), N represents an N-type unit, P represents a P-type unit, and C represents a CMOS-type unit.

[0114] The combinations of the upper unit 210 and the lower unit 220 are not limited to those described above. In Fig. 20(a), the upper unit 210 is a CMOS type and the lower unit 220 is an NMOS type. In Fig. 20(b), both the upper unit 210 and the lower unit 220 are PMOS types. In Fig. 20(c), the upper unit 210 is an NMOS type and the lower unit 220 is a CMOS type. In Fig. 20(d), the upper unit 210 is a PMOS type and the lower unit 220 is a CMOS type.

[0115] As shown in FIG. 20(e), the bias current source 240 may be omitted, or may be provided on the power supply side as shown in FIG. 20(f).

[0116] The output signal of the DCO 200 may be taken from the upper unit 210 side or the lower unit 220 side. The variable capacitor Cv may be connected to the lower unit 220 side.

[0117] (TDC) In the D-PLL circuit 100 and other applications, a digital-to-time converter (DTC) is also an important component technology.

[0118] FIG. 21 is a circuit diagram of a conventional DTC 300R. This DTC 300R is called a single-slope DTC. The DTC 300R includes a charging circuit 302, a capacitor 304, switches S1 to S3, inverters 306 and 308, and a DAC (D / A converter) 310. The DTC 300R applies a delay to an input signal IN according to a digital control code CODE and outputs the delayed signal. The DAC 309 generates an analog voltage V according to the control code CODE. DAC The charging circuit 302 charges the capacitor 304 when the first switch S1 is in the on state. The inverter 306 outputs the voltage V of the capacitor 304. P , the threshold V TH (=V DDWhen the third switch S3 is in the on state, it discharges the capacitor 304 and functions as a comparison circuit that compares the voltage V P Initialize.

[0119] Fig. 22 is an operational waveform diagram of the DTC 300R of Fig. 21. At time t0, the third switch S3 is turned on, the capacitor 304 is discharged, and the voltage V P is initialized.

[0120] At time t1, the second switch S2 is turned on, and the capacitor 304 is connected to the output voltage V DAC This causes V P =V DAC This becomes:

[0121] At time t2, the first switch S1 is turned on in response to the input signal IN. As a result, the current I C The capacitor 304 is charged by the voltage V P increases linearly.

[0122] At time t3, the voltage V P is the threshold V TH When the delay time τ of the output OUT relative to the input IN is τ=(V TH -V DAC )×C / I C where C is the capacitance of the capacitor 304.

[0123] As a result of examining the DTC 300R shown in FIG. 21, the inventors have come to recognize the following problem.

[0124] 22, only a portion of the current generated by the charging circuit 302 contributes to the delay Delay, and the rest is wasted. The inventors' investigations have revealed that 58% of the power is consumed by the current source during periods T1 and T2.

[0125] In other words, there is room for reducing power consumption in the DTC300R. Below, we will explain the DTC with reduced power consumption.

[0126] 23 is a circuit diagram of a DTC 300 according to an embodiment of the present invention. The DTC 300 includes a slope generating circuit 310, a precharge circuit 320, a comparison means (comparison circuit) 330, and a control circuit 340.

[0127] The slope generating circuit 310 includes a capacitor 312, a current source 314, and a first switch S1. The current source 314 supplies a constant current Ic to the capacitor 312, and generates a slope voltage V that changes at a constant slope across the capacitor 312. P The first switch S1 is provided to cut off the constant current Ic. The first switch S1 may be incorporated inside the current source 314.

[0128] The precharge circuit 320 applies an analog voltage V corresponding to the control code CODE to the capacitor 312. DAC The precharge circuit 320 includes a D / A converter 322 and a second switch S2. When the second switch S2 is on, the output voltage V DAC is applied to the capacitor 312 and the second switch S2 is off, the D / A converter 322 is disconnected from the capacitor 312. Note that if the D / A converter 322 can have its output in a high impedance state, the second switch S2 may be omitted and the D / A converter 322 may be controlled to turn the second switch S2 off.

[0129] The comparison means 330 compares the slope voltage V across the capacitor 312. P is the threshold V TH The comparison means 330 may include two stages of inverters 332 and 334 connected in cascade. The first stage inverter 332 generates a slope voltage V Pis compared with the threshold value of inverter 332 and converted into a binary signal according to the comparison result. The subsequent inverter 334 is provided to convert the logic value of the signal and / or to provide a low impedance sufficient to drive a load.

[0130] Preferably, the comparison means 330 is configured to be switchable between on and off, and a third switch S3 is provided for this purpose. The third switch S3 is provided between the inverter 332 and the ground. The third switch S3 may be inserted on the power supply line side.

[0131] The control circuit 340 controls the slope generating circuit 310 and the precharge circuit 320 in response to the input signal IN and the output signal OUT.

[0132] The control circuit 340 turns on the precharge circuit 320 during the precharge period. Specifically, it turns on the second switch S2. This causes the capacitor 312 to be charged to the voltage V DAC The length of the precharge period may be determined in consideration of a time constant determined according to the output impedance of the D / A converter 322 and the capacitance C of the capacitor 312, in other words, the time required for charging.

[0133] Furthermore, the control circuit 340 turns off the comparing means 330 during the precharge period. Specifically, it turns off the third switch S3.

[0134] Furthermore, the control circuit 340 transitions to the slope period in response to the input signal IN. During the slope period, the control circuit 340 turns off the precharge circuit 320 and turns on the slope generation circuit 310. Specifically, the control circuit 340 turns off the second switch S2, turns on the first switch S1, and turns on the third switch S3.

[0135] During the slope period, when the slope generating circuit 310 is turned on, the slope voltage V P changes at a constant slope. The slope voltage V P is the threshold V THWhen crossing the GND line, the output signal OUT transitions.

[0136] In response to the transition of the output signal OUT, the control circuit 340 turns off the slope generating circuit 310 and supplies the constant current I C The control circuit 340 repeats this series of operations.

[0137] 24 is a circuit diagram showing an example configuration of the control circuit 340. The control circuit 340 is configured with a logic circuit. The control circuit 340 includes a first edge detection circuit 342, a second edge detection circuit 344, a first delay circuit 346, a second delay circuit 348, a first flip-flop FF1, a second flip-flop FF2, a first inverter INV1, and a second inverter INV2.

[0138] The first edge detection circuit 342 generates a first pulse signal Sp1 having a predetermined pulse width in response to a positive edge (also called a rising edge or leading edge) of the input signal IN. The second edge detection circuit 344 generates a second pulse signal Sp2 having a predetermined pulse width in response to a positive edge of the output signal OUT.

[0139] The first delay circuit 346 delays the first pulse signal Sp1 by a delay amount τ1 and supplies the delayed signal to the set terminal (S) of the first flip-flop FF1. This delay amount τ1 ensures that the third switch S3 is turned on and the first switch S1 is turned on only after a state in which voltage comparison is possible is reached. The second pulse signal Sp2 is input to the reset terminal (R) of the first flip-flop FF1. The on / off state of the first switch S1 is controlled by the output Sig1 of the first flip-flop FF1.

[0140] The second delay circuit 348 delays the second pulse signal Sp2 by a delay amount τ2 and supplies the delayed signal to the set terminal of the second flip-flop FF2. P is the threshold V TH, there is a delay of two stages, that of inverter 332 and inverter 334, before the output OUT rises completely to high (VDD). Therefore, by introducing a delay τ2, it is possible to turn off the third switch S3 after the output OUT rises completely to high (VDD).

[0141] The second flip-flop FF2 receives a reset terminal receiving a first pulse signal Sp1. The second switch S2 and the third switch S3 are controlled based on the state of the second flip-flop FF2. Specifically, an inverted signal Sig3 of the output Q of the second flip-flop FF2 is supplied to the third switch S3, and an inverted signal Sig2 of the inverted output QB of the second flip-flop FF2 is supplied to the second switch S2.

[0142] The second flip-flop FF2 is reset at the timing of the negative edge of the first pulse signal Sp1. Therefore, the timing at which the second switch S2 is turned on and the third switch S3 is turned off is determined by the pulse width of the first pulse signal Sp1.

[0143] The above is the configuration of DTC 300. Next, we will explain its operation. Figure 25 is a time chart that explains the operation of DTC 300 of Figure 23.

[0144] At time t0, the second switch S2 is turned on, and the capacitor 312 is charged by the DAC 309. This causes the voltage V P is the voltage value V according to the control code DAC This becomes:

[0145] At time t1, when the input signal IN transitions to high, the first switch S1 is turned on and the capacitor 312 flows through the current I generated by the current source 314. C The capacitor 312 is charged by the voltage V P At this time, the third switch S3 is also turned on, and the inverter 306 is in a state where it can compare voltages.

[0146] At time t2, the voltage VP is the threshold V TH When the voltage V reaches V, the output OUT transitions to high. In response, the control circuit 340 turns off the first switch S1. As a result, the charging of the capacitor 312 stops. As a result, the voltage V P is the threshold voltage V TH Then, at time t3 after the time corresponding to the delay amount of the second delay circuit 348 has elapsed, the second switch S2 is turned on and the third switch S3 is turned off. This completes one cycle of operation. Next, the advantages of this operation will be explained.

[0147] 26 is a diagram showing the operating waveforms of the DTC according to this embodiment (i) and the operating waveforms of the conventional DTC (ii). In this embodiment, the voltage V P The fluctuation of the current I generated by the current source 314 is suppressed to a minimum. In other words, the unnecessary supply of charge to the capacitor 312 and the unnecessary release of charge from the capacitor 312 are reduced, thereby reducing power consumption. In particular, in this embodiment, the first switch S1 is turned on only during the slope generation period. In other words, the current I generated by the current source 314 is C is used to generate the slope, reducing power consumption.

[0148] In addition, the third switch S3 is placed on the path of the inverter 306 and is turned on only during the voltage comparison period. DAC is the threshold voltage V of the inverter (comparator) 306. TH When the voltage is close to 0 V, a through current can be prevented from flowing through the inverter 306, further reducing power consumption.

[0149] 23, the comparison means 330 may be configured as a voltage comparator. In this case, a switch S3 may be incorporated into the voltage comparator to cut off the bias current of the voltage comparator.

[0150] The present invention has been described using specific terms based on the embodiments, but the embodiments merely illustrate the principles and applications of the present invention, and many modifications and changes in arrangement are permitted to the embodiments as long as they do not deviate from the concept of the present invention defined in the claims. [Industrial Applicability]

[0151] The present invention can be used in electronic circuits. [Explanation of symbols]

[0152] 100 D-PLL circuit 102 DTC 104 TDC 106 DLF 108 DCO 110 buffers 112 MMD 113 Gate Circuit 114 Controller 116 Retiming Circuit 120 Multiplexer 122 Delay Circuit 130 Mode Selector 132 State Machine 140 Dead Zone Detector 142 PFD 144 Judgment section 150 Intermittent operation FLL 152 FLL 154 Duty Cycle Controller 160 Frequency Detector 162 Frequency divider 164 Flip-Flop 166 Counters 168 Flip-Flop 170 Subtractor 172 Comparator 180 2nd PLL 200 DCO 210 Upper unit 220 Lower Unit 230 Transformer 300 DTC 310 Slope generation circuit 312 Capacitor 314 Current Source S1 First switch 320 Precharge Circuit 322 D / A converter S2 Second switch 330 Comparison means 332,334 Inverter 340 Control Circuit 342 First Edge Detection Circuit 344 Second Edge Detector Circuit 346 First Delay Circuit 348 Second Delay Circuit FF1 1st Flip-Flop FF2 Second flip-flop INV1 1st inverter INV2 Second inverter

Claims

1. a digital-to-time converter that receives an input signal, applies a delay according to a control code, and generates an output signal; a slope generating circuit including a capacitor and a current source for generating a slope voltage; a precharge circuit that applies an analog voltage to the capacitor according to a control code; a comparison circuit that compares the slope voltage with a threshold value and generates the output signal according to the comparison result; a control circuit that controls the slope generating circuit and the precharge circuit in response to the input signal and the output signal; Equipped with The control circuit repeats the following operations: (i) turning on the precharge circuit during a precharge period; (ii) transitioning to a slope period in response to a transition of the input signal, turning off the precharge circuit during the slope period, and turning on the slope generation circuit; and (iii) turning off the slope generation circuit in response to a transition of the output signal.

2. 2. The digital-to-time converter according to claim 1, wherein the comparison circuit is configured to be switchable between on and off, and the control circuit turns off the comparison circuit during the precharge period.

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