Semiconductor device

Abstract

To provide a semiconductor device including a hydrogen trap region that prevents the entry of hydrogen to a channel region.SOLUTION: A semiconductor device includes a first oxide insulating layer, an oxide semiconductor layer on the first oxide insulating layer, a second oxide insulating layer covering the oxide semiconductor layer, a nitride insulating layer on the second oxide insulating layer, a gate electrode on the nitride insulating layer, and an insulating layer covering the gate electrode. The nitride insulating layer includes a first side wall with a shape along the pattern of the gate electrode in a plan view, and the first side wall is in contact with the insulating layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] An embodiment of the present invention relates to a semiconductor device that uses an oxide semiconductor as a channel. [Background technology]

[0002] In recent years, development of semiconductor devices using oxide semiconductors as channels instead of silicon semiconductors such as amorphous silicon, low-temperature polysilicon, and single-crystal silicon has been progressing (see, for example, Patent Document 1). Semiconductor devices including such oxide semiconductors have a simple structure and can be formed by a low-temperature process, similar to thin-film transistors including amorphous silicon. Semiconductor devices including oxide semiconductors are known to have higher field-effect mobility than semiconductor devices including amorphous silicon. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2021-141338 Summary of the Invention [Problem to be solved by the invention]

[0004] In an oxide semiconductor, carriers are generated when hydrogen bonds to oxygen defects. In a semiconductor device, this mechanism can be utilized to form oxygen defects in an oxide semiconductor layer and supply hydrogen to the formed oxygen defects to form low-resistance source and drain regions. On the other hand, diffusion of hydrogen into the channel region of the oxide semiconductor layer reduces its function as a channel of the semiconductor device. Specifically, the diffusion of hydrogen into the channel region changes the threshold voltage in the electrical characteristics of the semiconductor device, increasing the variation in threshold voltage and reducing the manufacturing yield of the semiconductor device. Therefore, by using an oxide layer containing excess oxygen capable of trapping hydrogen as an insulating layer in contact with the oxide semiconductor layer, the penetration of hydrogen into the channel region is suppressed.

[0005] However, an oxide layer containing excess oxygen functions as an electron trap, which significantly reduces the reliability of a semiconductor device including such an oxide layer. Therefore, a semiconductor device is desired that can supply hydrogen to the source and drain regions of an oxide semiconductor layer while suppressing the penetration of hydrogen into the channel region of the oxide semiconductor layer to prevent a decrease in reliability.

[0006] In view of the above-mentioned problems, one object of one embodiment of the present invention is to provide a semiconductor device including a hydrogen trapping region that prevents hydrogen from entering a channel region. [Means for solving the problem]

[0007] A semiconductor device according to one embodiment of the present invention includes a first oxide insulating layer, an oxide semiconductor layer on the first oxide insulating layer, a second oxide insulating layer covering the oxide semiconductor layer, a nitride insulating layer on the second oxide insulating layer, a gate electrode on the nitride insulating layer, and an insulating layer covering the gate electrode, wherein the nitride insulating layer has a first sidewall shaped to follow the pattern of the gate electrode in a planar view, and the first sidewall is in contact with the insulating layer. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a cross-sectional view showing an overview of a semiconductor device according to an embodiment of the present invention; [Figure 2] 1 is a plan view showing an overview of a semiconductor device according to an embodiment of the present invention; [Figure 3] 1 is a schematic partially enlarged cross-sectional view showing the configuration of a semiconductor device according to one embodiment of the present invention; [Figure 4] 3 is a graph showing profiles of impurity concentrations in first to third regions in a semiconductor device according to one embodiment of the present invention. [Figure 5] 1 is a sequence diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 6] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 8] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 9] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 10] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 11] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 12] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 13] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 14] 4 is a schematic cross-sectional view illustrating the hydrogen trapping function in the second region and the third region in the semiconductor device according to the embodiment of the present invention. FIG. [Figure 15] 4 is a schematic cross-sectional view illustrating the hydrogen trapping function in the second region and the third region in the semiconductor device according to the embodiment of the present invention. FIG. [Figure 16]1A and 1B are a schematic cross-sectional view illustrating the effect of hydrogen trapping in a semiconductor device according to one embodiment of the present invention and a diagram showing the electrical characteristics of the semiconductor device; [Figure 17] 1 is a cross-sectional view showing an overview of a semiconductor device according to an embodiment of the present invention; [Figure 18] 1 is a schematic partially enlarged cross-sectional view showing the configuration of a semiconductor device according to one embodiment of the present invention; [Figure 19] 3 is a graph showing profiles of impurity concentrations in first to third regions in a semiconductor device according to one embodiment of the present invention. [Figure 20] 1 is a sequence diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 21] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 22] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 23] 1 is a cross-sectional view showing an overview of a semiconductor device according to an embodiment of the present invention; [Figure 24] 4 is a schematic cross-sectional view illustrating the hydrogen trapping function in the second region and the third region in the semiconductor device according to the embodiment of the present invention. FIG. [Figure 25] 3 is a graph showing profiles of impurity concentrations in first to third regions in a semiconductor device according to one embodiment of the present invention. [Figure 26] 1 is a sequence diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 27] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 28] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 29] 1 is a cross-sectional view showing an overview of a semiconductor device according to an embodiment of the present invention; [Figure 30] 1 is a sequence diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention; [Figure 31]1 is a cross-sectional view showing an overview of a semiconductor device according to an embodiment of the present invention; [Figure 32] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 33] 1A to 1C are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0009] Each embodiment of the present invention will be described below with reference to the drawings. The following disclosure is merely an example. Configurations that a person skilled in the art can easily arrive at by appropriately modifying the configuration of the embodiment while maintaining the gist of the invention are naturally included within the scope of the present invention. For clarity of explanation, the drawings may show the width, thickness, shape, etc. of each part more schematically than the actual form. However, the illustrated shapes are merely examples and do not limit the interpretation of the present invention. In this specification and each drawing, components similar to those described above with reference to the previous drawings are designated by the same reference numerals, and detailed descriptions may be omitted as appropriate.

[0010] In each embodiment of the present invention, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "upper." Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "downper." For convenience of explanation, the terms "up" and "downper" are used in the description. However, for example, the vertical relationship between the substrate and the oxide semiconductor layer may be different from that illustrated. In the following description, for example, the expression "oxide semiconductor layer on a substrate" merely describes the vertical relationship between the substrate and the oxide semiconductor layer as described above, and other components may be disposed between the substrate and the oxide semiconductor layer. "Above" or "below" refers to the stacking order in a structure in which multiple layers are stacked. When a pixel electrode is referred to as being above a transistor, the transistor and the pixel electrode may not overlap in a planar view. On the other hand, when a pixel electrode is referred to as being vertically above a transistor, the transistor and the pixel electrode may overlap in a planar view.

[0011] In this specification, the terms "film" and "layer" may be used interchangeably in some cases.

[0012] The term "display device" refers to a structure that displays an image using an electro-optical layer. For example, the term "display device" may refer to a display panel including an electro-optical layer, or may refer to a structure in which other optical components (e.g., polarizing components, backlights, touch panels, etc.) are attached to a display cell. The term "electro-optical layer" may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer, unless technically inconsistent.

[0013] In this specification, unless otherwise specified, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A to C. Furthermore, these expressions do not exclude cases where α includes other elements.

[0014] The following embodiments can be combined with each other as long as no technical contradiction occurs.

[0015] [1. First embodiment] A semiconductor device according to one embodiment of the present invention will be described with reference to Figures 1 to 16. For example, the semiconductor device according to the embodiment described below may be used in an integrated circuit (IC) such as a microprocessor (micro-processing unit: MPU) or a memory circuit, in addition to a transistor used in a display device.

[0016] [1-1. Configuration of semiconductor device 10] The configuration of a semiconductor device 10 according to one embodiment of the present invention will be described with reference to Figures 1 and 2. Figure 1 is a cross-sectional view showing an overview of a semiconductor device according to one embodiment of the present invention. Figure 2 is a plan view showing an overview of a semiconductor device according to one embodiment of the present invention.

[0017] As shown in FIG. 1, a semiconductor device 10 is provided above a substrate 100. The semiconductor device 10 includes a light-shielding layer 105, a nitride insulating layer 110, an oxide insulating layer 120, an oxide semiconductor layer 140, an oxide insulating layer 150, a nitride insulating layer 155, a gate electrode 160, insulating layers 170 and 180, a source electrode 201, and a drain electrode 203. When the source electrode 201 and the drain electrode 203 are not particularly distinguished, they may be collectively referred to as the source-drain electrode 200. The oxide insulating layer 120 may be referred to as the "first oxide insulating layer." The oxide insulating layer 150 may be referred to as the "second oxide insulating layer."

[0018] The light-shielding layer 105 is provided on the substrate 100. The nitride insulating layer 110 and the oxide insulating layer 120 are provided on the substrate 100 and the light-shielding layer 105. The nitride insulating layer 110 covers the upper surface and edges of the light-shielding layer 105. The oxide semiconductor layer 140 is provided on the oxide insulating layer 120. The oxide semiconductor layer 140 is patterned. A portion of the oxide insulating layer 120 extends beyond the edges of the oxide semiconductor layer 140 and outside the pattern of the oxide semiconductor layer 140.

[0019] In this embodiment, a configuration in which the oxide insulating layer 120 and the oxide semiconductor layer 140 are in contact with each other is illustrated; however, the present invention is not limited to this configuration. For example, a metal oxide layer may be provided between the oxide insulating layer 120 and the oxide semiconductor layer 140, and the oxide insulating layer 150 may not be in contact with the oxide insulating layer 120. For example, a metal oxide containing aluminum as a main component may be used as the metal oxide layer. Specifically, aluminum oxide may be used as the metal oxide layer.

[0020] The gate electrode 160 is above the oxide semiconductor layer 140 and faces the oxide semiconductor layer 140. The oxide insulating layer 150 and the nitride insulating layer 155 are provided between the oxide semiconductor layer 140 and the gate electrode 160. The oxide insulating layer 150 and the nitride insulating layer 155 function as gate insulating layers of the semiconductor device 10. In the following description, when there is no need to distinguish between the oxide insulating layer 150 and the nitride insulating layer 155, they may be collectively referred to as the "gate insulating layer."

[0021] The nitride insulating layer 155 is provided on the oxide insulating layer 150. The oxide insulating layer 150 covers the upper surface and edges of the oxide semiconductor layer 140. On the other hand, the pattern edges of the nitride insulating layer 155 approximately coincide with the pattern edges of the gate electrode 160. That is, in a planar view, the pattern of the nitride insulating layer 155 approximately coincides with the pattern of the gate electrode 160. In other words, the above configuration is expressed in other words as follows: the sidewall 157 of the nitride insulating layer 155 has a shape that follows the pattern of the gate electrode 160 in a planar view. The sidewall 157 is in contact with the insulating layer 170. The sidewall 157 may be referred to as a "first sidewall." The gate electrode 160 is provided on the nitride insulating layer 155.

[0022] The oxide insulating layer 150 is in contact with the oxide semiconductor layer 140. Of the main surfaces of the oxide semiconductor layer 140, the surface in contact with the oxide insulating layer 150 is the upper surface 141. Of the main surfaces of the oxide semiconductor layer 140, the surface in contact with the oxide insulating layer 120 is the lower surface 142. The surface between the upper surface 141 and the lower surface 142 is the side surface 143. The oxide insulating layer 150 covers the upper surface 141 and the side surface 143 of the oxide semiconductor layer 140, and is in contact with the oxide insulating layer 120 in a region (a third region A3 described later) outside the pattern of the oxide semiconductor layer 140. In other words, the oxide insulating layer 150 covers the oxide semiconductor layer 140 and is provided on the oxide insulating layer 120 and the oxide semiconductor layer 140.

[0023] The insulating layer 170 is provided on the oxide insulating layer 150 and the gate electrode 160. The insulating layer 170 covers the gate electrode 160. The insulating layer 170 is in contact with the oxide insulating layer 150 in a region that does not overlap with the gate electrode 160 in a planar view. The insulating layer 180 is provided on the insulating layer 170. Openings 171 and 173 that reach the oxide semiconductor layer 140 are provided in the insulating layers 170 and 180 and the oxide insulating layer 150. The source electrode 201 is provided inside the opening 171. The source electrode 201 is in contact with the oxide semiconductor layer 140 at the bottom of the opening 171. The drain electrode 203 is provided inside the opening 173. The drain electrode 203 is in contact with the oxide semiconductor layer 140 at the bottom of the opening 173.

[0024] The light-shielding layer 105 functions as a light-shielding film for the oxide semiconductor layer 140. The nitride insulating layer 110 functions as a barrier film that blocks impurities diffusing from the substrate 100 toward the oxide semiconductor layer 140. The light-shielding layer 105 may also function as a bottom gate of the semiconductor device 10. In this case, the nitride insulating layer 110 and the oxide insulating layer 120 function as gate insulating layers for the bottom gate.

[0025] The operation of the semiconductor device 10 is mainly controlled by the voltage supplied to the gate electrode 160. When the light-shielding layer 105 has a function as a bottom gate, an auxiliary voltage is supplied to the light-shielding layer 105. However, the same voltage as the voltage supplied to the gate electrode 160 may be supplied to the light-shielding layer 105. On the other hand, when the light-shielding layer 105 is used simply as a light-shielding film, no specific voltage may be supplied to the light-shielding layer 105, and the potential of the light-shielding layer 105 may be floating. Alternatively, the light-shielding layer 105 may be an insulator.

[0026] The semiconductor device 10 is divided into a first region A1, a second region A2, and a third region A3 based on the patterns of the gate electrode 160 and the oxide semiconductor layer 140. The first region A1 is a region that overlaps with the gate electrode 160 in a planar view. The second region A2 is a region that does not overlap with the gate electrode 160 in a planar view but overlaps with the oxide semiconductor layer 140. The third region A3 is a region that does not overlap with either the gate electrode 160 or the oxide semiconductor layer 140 in a planar view.

[0027] The oxide insulating layer 150 is provided across the first region A1, the second region A2, and the third region A3. On the other hand, the nitride insulating layer 155 is provided only in the first region A1. The oxide insulating layer 150 and the nitride insulating layer 155 are sometimes collectively referred to as the "gate insulating layer." In this case, the above configuration can be expressed as follows: The thickness of the gate insulating layer in the second region A2 and the third region A3 is smaller than the thickness of the gate insulating layer in the first region A1. In other words, the thickness of the gate insulating layer in the region that does not overlap with the gate electrode 160 in a plan view is smaller than the thickness of the gate insulating layer in the region that overlaps with the gate electrode 160.

[0028] The total thickness of the oxide insulating layer 150 and the nitride insulating layer 155 in the first region A1 is 200 nm or more. The total thickness of the oxide insulating layer 150 and the nitride insulating layer 155 in the first region A1 may be 250 nm or more, or 300 nm or more. The thickness of the oxide insulating layer 150 in the second region A2 and the third region A3 is 100 nm or less. The thickness of the oxide insulating layer 150 in the second region A2 and the third region A3 may be 50 nm or less, or 30 nm or less. For example, by setting the thickness of the oxide insulating layer 150 in the second region A2 and the third region A3 to be 50 nm or more and 100 nm or less, it is possible to introduce sufficient impurities into the oxide insulating layer 120 in the second region A2 and the third region A3 by ion implantation while ensuring the blocking function of hydrogen diffused from the insulating layer 170.

[0029] 1 illustrates a configuration in which the thickness of the oxide insulating layer 150 in the first region A1 is the same as the thickness of the oxide insulating layer 150 in the second region A2 and the third region A3, but this configuration is not limiting. The thickness of the oxide insulating layer 150 in the first region A1 may be greater than the thickness of the oxide insulating layer 150 in the second region A2 and the third region A3. In this case, the oxide insulating layer 150 has a sidewall (second sidewall) shaped along the pattern of the gate electrode 160 in a plan view. The second sidewall is in contact with the insulating layer 170.

[0030] The oxide semiconductor layer 140 is divided into a source region S, a drain region D, and a channel region CH based on the pattern of the gate electrode 160. The source region S and the drain region D correspond to the second region A2. The channel region CH corresponds to the first region A1. In a plan view, an edge of the channel region CH coincides with an edge of the gate electrode 160. The oxide semiconductor layer 140 in the channel region CH has semiconductor properties. The oxide semiconductor layer 140 in each of the source region S and the drain region D has conductive properties. That is, the carrier concentration of the oxide semiconductor layer 140 in the source region S and the drain region D is higher than the carrier concentration of the oxide semiconductor layer 140 in the channel region CH. The source electrode 201 and the drain electrode 203 are in contact with the oxide semiconductor layer 140 in the source region S and the drain region D, respectively, and are electrically connected to the oxide semiconductor layer 140. The oxide semiconductor layer 140 may have a single-layer structure or a multilayer structure.

[0031] In this embodiment, a top-gate transistor in which the gate electrode 160 is provided above the oxide semiconductor layer 140 is exemplified as the semiconductor device 10, but the semiconductor device 10 is not limited to this configuration. For example, as described above, the semiconductor device 10 may be a dual-gate transistor in which the light-shielding layer 105 functions as a gate in addition to the gate electrode 160. Alternatively, the semiconductor device 10 may be a bottom-gate transistor in which the light-shielding layer 105 mainly functions as a gate. The above configuration is merely one embodiment, and the present invention is not limited to the above configuration.

[0032] 2, the width of the light-shielding layer 105 is greater than the width of the gate electrode 160 in the D1 direction. The D1 direction is a direction connecting the source electrode 201 and the drain electrode 203, and is a direction indicating the channel length L of the semiconductor device 10. Specifically, the length in the D1 direction of a region (channel region CH) where the oxide semiconductor layer 140 and the gate electrode 160 overlap is the channel length L, and the width in the D2 direction of the channel region CH is the channel width W. The light-shielding layer 105 and the gate electrode 160 extend in the D2 direction. An opening 161 is provided in the nitride insulating layer 110, the oxide insulating layer 120, and the oxide insulating layer 150, and the light-shielding layer 105 and the gate electrode 160 are connected to each other via the opening 161.

[0033] 2 illustrates a configuration in which the source-drain electrode 200 does not overlap the light-shielding layer 105 and the gate electrode 160 in a plan view, but the present invention is not limited to this configuration. For example, the source-drain electrode 200 may overlap at least one of the light-shielding layer 105 and the gate electrode 160 in a plan view. The above configuration is merely one embodiment, and the present invention is not limited to the above configuration.

[0034] [1-2. Materials of Components of Semiconductor Device 10] The substrate 100 may be a rigid substrate having optical transparency, such as a glass substrate, a quartz substrate, or a sapphire substrate. When the substrate 100 needs to be flexible, a substrate containing a resin, such as a polyimide substrate, an acrylic substrate, a siloxane substrate, or a fluororesin substrate, may be used. When a substrate containing a resin is used as the substrate 100, impurities may be introduced into the resin to improve the heat resistance of the substrate 100. In particular, when the semiconductor device 10 is a top-emission display, the substrate 100 does not need to be transparent, and therefore impurities that deteriorate the transparency of the substrate 100 may be used. When the semiconductor device 10 is used in an integrated circuit other than a display device, a substrate not having optical transparency, such as a semiconductor substrate such as a silicon substrate, a silicon carbide substrate, or a compound semiconductor substrate, or a conductive substrate such as a stainless steel substrate, may be used as the substrate 100.

[0035] Common metal materials are used for the light-shielding layer 105, gate electrode 160, and source / drain electrodes 200. Examples of materials that can be used for these components include aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys or compounds thereof. The above materials may be used as the light-shielding layer 105, gate electrode 160, and source / drain electrodes 200 in a single layer or a multilayer configuration. If electrical conductivity is not required for the light-shielding layer 105, materials other than the above metal materials may be used. For example, a black matrix such as a black resin may be used as the light-shielding layer 105. The light-shielding layer 105 may have a single-layer structure or a multilayer structure. For example, the light-shielding layer 105 may have a multilayer structure of red, green, and blue color filters.

[0036] A general insulating material is used for the nitride insulating layer 110, the oxide insulating layer 120, the oxide insulating layer 150, the nitride insulating layer 155, and the insulating layers 170 and 180. For example, silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y The nitride insulating layers 110, 155 and the insulating layer 170 are made of inorganic insulating layers such as silicon nitride (SiN x ), silicon oxynitride (SiN x O y ), aluminum nitride (AlN x ), aluminum oxide nitride (AlN x O y However, the insulating layer 170 may be made of an inorganic insulating layer such as silicon oxide (SiO x ), silicon oxynitride (SiO x Ny ), aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ) may be used as the insulating layer 180. x ), silicon oxynitride (SiN x O y ), aluminum nitride (AlN x ), aluminum oxide nitride (AlN x O y ) or other inorganic insulating layers may also be used.

[0037] An insulating layer having a function of releasing oxygen by heat treatment is used as the oxide insulating layer 120. That is, an oxide insulating layer containing excess oxygen is used as the oxide insulating layer 120. The temperature of heat treatment at which the oxide insulating layer 120 releases oxygen is, for example, 600°C or lower, 500°C or lower, 450°C or lower, or 400°C or lower. That is, the oxide insulating layer 120 releases oxygen at a heat treatment temperature that is used in the manufacturing process of the semiconductor device 10 when a glass substrate is used as the substrate 100. Similar to the oxide insulating layer 120, an insulating layer having a function of releasing oxygen by heat treatment may be used for at least one of the insulating layers 170 and 180.

[0038] An insulating layer with few defects is used as the oxide insulating layer 150. For example, when the oxygen composition ratio in the oxide insulating layer 150 is compared with the oxygen composition ratio in an insulating layer having the same composition as the oxide insulating layer 150 (hereinafter referred to as "another insulating layer"), the oxygen composition ratio in the oxide insulating layer 150 is closer to the stoichiometric ratio for the insulating layer than the oxygen composition ratio in the other insulating layer. Specifically, the oxide insulating layer 150 and the insulating layer 180 each contain silicon oxide (SiO x ), the oxygen composition ratio in the silicon oxide used as the oxide insulating layer 150 is closer to the stoichiometric ratio of silicon oxide than the oxygen composition ratio in the silicon oxide used as the insulating layer 180. For example, the oxide insulating layer 150 may be a layer in which no defects are observed when evaluated by electron spin resonance (ESR).

[0039] The above SiO x N y and AlO x N y is a silicon and aluminum compound containing a smaller proportion (x>y) of nitrogen (N) than oxygen (O). SiN x O y and AlN x O y are silicon and aluminum compounds containing a smaller proportion of oxygen than nitrogen (x>y).

[0040] The oxide semiconductor layer 140 may be made of a metal oxide having semiconductor properties. For example, the oxide semiconductor layer 140 may be made of an oxide semiconductor containing indium (In), gallium (Ga), zinc (Zn), and oxygen (O). For example, the oxide semiconductor layer 140 may be made of an oxide semiconductor having a composition ratio of In:Ga:Zn:O=1:1:1:4. However, the oxide semiconductor containing In, Ga, Zn, and O used in this embodiment is not limited to the above composition. An oxide semiconductor having a composition different from the above may be used as the oxide semiconductor. For example, an oxide semiconductor layer having a higher In ratio than the above may be used to improve mobility. On the other hand, an oxide semiconductor layer having a higher Ga ratio than the above may be used to increase the band gap and reduce the influence of light irradiation.

[0041] In addition to indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconia (Zr), and lanthanoids may be used for the oxide semiconductor layer 140. Elements other than those mentioned above may also be used for the oxide semiconductor layer 140.

[0042] The oxide semiconductor layer 140 may be formed by adding other elements, such as metal elements such as Al and Sn, to an oxide semiconductor containing In, Ga, Zn, and O. In addition to the above oxide semiconductors, the oxide semiconductor layer 140 may also be formed by using an oxide semiconductor containing In and Ga (IGO), an oxide semiconductor containing In and Zn (IZO), an oxide semiconductor containing In, Sn, and Zn (ITZO), an oxide semiconductor containing In and W, or the like.

[0043] When the ratio of indium element is high, the oxide semiconductor layer 140 is likely to crystallize. As described above, by using a material in which the ratio of indium element to all metal elements in the oxide semiconductor layer 140 is 50% or more, the oxide semiconductor layer 140 can have a polycrystalline structure. The oxide semiconductor layer 140 preferably contains gallium as a metal element other than indium. Gallium belongs to the same Group 13 element as indium. Therefore, the crystallinity of the oxide semiconductor layer 140 is not impaired by gallium, and the oxide semiconductor layer 140 has a polycrystalline structure.

[0044] Although the detailed manufacturing method of the oxide semiconductor layer 140 will be described later, the oxide semiconductor layer 140 can be formed by a sputtering method. The composition of the oxide semiconductor layer 140 formed by a sputtering method depends on the composition of the sputtering target. Even when the oxide semiconductor layer 140 has a polycrystalline structure, the composition of the sputtering target and the composition of the oxide semiconductor layer 140 are approximately the same. In this case, the composition of the metal elements in the oxide semiconductor layer 140 can be specified based on the composition of the metal elements in the sputtering target.

[0045] When the oxide semiconductor layer 140 has a polycrystalline structure, the composition of the oxide semiconductor layer may be determined by X-ray diffraction (XRD). Specifically, the composition of the metal elements in the oxide semiconductor layer can be determined based on the crystal structure and lattice constant of the oxide semiconductor layer obtained by XRD. Furthermore, the composition of the metal elements in the oxide semiconductor layer 140 can also be determined by X-ray fluorescence analysis or electron probe microanalyzer (EPMA) analysis. However, the oxygen element contained in the oxide semiconductor layer 140 may not be determined by these methods because it varies depending on the sputtering process conditions, etc.

[0046] As described above, the oxide semiconductor layer 140 may have an amorphous structure or a polycrystalline structure. An oxide semiconductor having a polycrystalline structure can be fabricated using Poly-OS (Polycrystalline Oxide Semiconductor) technology. Hereinafter, an oxide semiconductor having a polycrystalline structure may be referred to as Poly-OS to distinguish it from an oxide semiconductor having an amorphous structure.

[0047] As described above, when a metal oxide layer is provided between the oxide insulating layer 120 and the oxide semiconductor layer 140, a metal oxide containing aluminum as a main component is used as the metal oxide layer. For example, aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), and aluminum oxide nitride (AlN x O y ) is used. "A metal oxide layer containing aluminum as a main component" means that the ratio of aluminum contained in the metal oxide layer is 1% or more of the entire metal oxide layer. The ratio of aluminum contained in the metal oxide layer may be 5% to 70%, 10% to 60%, or 30% to 50% of the entire metal oxide layer. The above ratio may be a mass ratio or a weight ratio.

[0048] [1-3. Hydrogen trapping area configuration] The hydrogen trapping regions are formed in the oxide insulating layers 120 and 150. The configuration of the hydrogen trapping regions formed in the oxide insulating layers 120 and 150 will now be described with reference to FIGS. 3 and 4. FIG. 3 is a schematic, partially enlarged cross-sectional view showing the configuration of a semiconductor device according to one embodiment of the present invention. Specifically, FIG. 3 is an enlarged cross-sectional view of region P in FIG. 1. Region P shown in FIG. 3 is a region near the drain region D, but the region near the source region S also has a similar configuration to region P.

[0049] The oxide insulating layers 120 and 150 are divided into a first region A1, a second region A2, and a third region A3. The oxide insulating layer 120 in each region is referred to as oxide insulating layer 120-1, 120-2, and 120-3, respectively. Similarly, the oxide insulating layer 150 in each region is referred to as oxide insulating layer 150-1, 150-2, and 150-3, respectively. The oxide insulating layers 120-1 and 120-2 contact the oxide semiconductor layer 140. The oxide insulating layer 120-3 contacts the oxide insulating layer 150-3. The oxide insulating layer 150-1 contacts the oxide semiconductor layer 140 in the channel region CH. The oxide insulating layer 150-2 contacts the oxide semiconductor layer 140 and the insulating layer 170 in the drain region D. The oxide insulating layer 150-3 is located outside the drain region D and is in contact with the oxide insulating layer 120 and the insulating layer 170.

[0050] As will be described in detail later, the oxide semiconductor layer 140 in the source region S and the drain region D is formed by ion implantation of an impurity using the gate electrode 160 as a mask. Examples of impurities that can be used include boron (B), phosphorus (P), argon (Ar), and nitrogen (N). The ion implantation generates oxygen defects in the oxide semiconductor layer 140 in the source region S and the drain region D. Hydrogen is trapped in the generated oxygen defects, thereby reducing the resistance of the oxide semiconductor layer 140 in the source region S and the drain region D. Because a silicon nitride layer contains more hydrogen than a silicon oxide layer, for example, using silicon nitride as the insulating layer 170 can reduce the resistance of the oxide semiconductor layer 140 in the source region S and the drain region D.

[0051] Because the ion implantation is performed through the oxide insulating layer 150, dangling bond defects DB are generated in the oxide insulating layer 150. In the second region A2, the ion-implanted impurities reach the oxide insulating layer 120 by passing through the oxide insulating layer 150 and the oxide semiconductor layer 140. Similarly, in the third region A3, the ion-implanted impurities reach the oxide insulating layer 120 by passing through the oxide insulating layer 150. Therefore, dangling bond defects DB are also generated in the oxide insulating layer 120 in the second region A2 and the third region A3.

[0052] Because impurity ions are implanted using gate electrode 160 as a mask, impurities are not implanted into oxide insulating layer 120-1 and oxide insulating layer 150-1 in first region A1. Therefore, dangling bond defects DB are not generated in oxide insulating layer 120-1 and oxide insulating layer 150-1. On the other hand, as described above, dangling bond defects DB are generated in oxide insulating layers 120-2 and 120-3 and oxide insulating layers 150-2 and 150-3. For example, when silicon oxide is used for oxide insulating layers 120 and 150, silicon dangling bond defects DB are formed in oxide insulating layers 120-2 and 120-3 and oxide insulating layers 150-2 and 150-3.

[0053] Dangling bond defects DB formed in the oxide insulating layer 120 and the oxide insulating layer 150 trap hydrogen. That is, in the semiconductor device 10, the oxide insulating layers 120-2 and 120-3 and the oxide insulating layers 150-2 and 150-3 function as hydrogen trapping regions. Therefore, for example, hydrogen diffused from the insulating layer 170 during the formation of the insulating layer 170 is trapped by the dangling bond defects DB in these insulating layers, thereby preventing hydrogen from penetrating into the oxide semiconductor layer 140 in the channel region CH. Therefore, after the insulating layer 170 is formed, the hydrogen concentrations of the oxide insulating layers 120-2 and 120-3 are higher than that of the oxide insulating layer 120-1. Similarly, the hydrogen concentrations of the oxide insulating layers 150-2 and 150-3 are higher than that of the oxide insulating layer 150-1.

[0054] Because the above-described dangling bond defects DB are formed by ion implantation, the oxide insulating layers 120-2 and 120-3 and the oxide insulating layers 150-2 and 150-3 contain impurities introduced by ion implantation. The distribution of the amount of dangling bond defects DB formed in the oxide insulating layers 120-2 and 120-3 and the oxide insulating layers 150-2 and 150-3 corresponds to the concentration profile of the impurities contained therein. In other words, the position and amount of the dangling bond defects DB can be adjusted by adjusting the impurity profile obtained by ion implantation.

[0055] Although the details will be described later, in order to suppress the occurrence of abnormalities in the electrical characteristics of the semiconductor device 10 due to hydrogen penetrating into the oxide semiconductor layer 140 in the channel region CH, it is effective to form dangling bond defects DB in the oxide insulating layer 120. Therefore, it is necessary to implant impurities so that they reach the oxide insulating layer 120 through the oxide insulating layer 150.

[0056] For example, in the case of a semiconductor device requiring a gate insulating layer with high voltage resistance, the thickness of the gate insulating layer (the insulating layer between the oxide semiconductor layer and the gate electrode) is required to be 200 nm or more. On the other hand, when impurities are to be introduced into the oxide insulating layer 120 by ion implantation, the thickness of the gate insulating layer in the second region A2 and the third region A3 is required to be 100 nm or less due to limitations imposed by the acceleration voltage of the ion implantation device. The above configuration is adopted to satisfy these requirements.

[0057] 4 is a graph showing impurity concentration profiles in the first region A1 to the third region A3 in a semiconductor device according to one embodiment of the present invention. The vertical axis of each of the three concentration profiles shown in FIG. 4 indicates the impurity concentration per unit volume (Concentration [ / cm3]), and the horizontal axis indicates the name of the layer in the depth direction. "UC" on the horizontal axis corresponds to the oxide insulating layer 120 and the nitride insulating layer 110. "OS" corresponds to the oxide semiconductor layer 140. "GI" in the first region A1 corresponds to the oxide insulating layer 150 and the nitride insulating layer 155. "GI" in the second region A2 and the third region A3 corresponds to the oxide insulating layer 150. "GL" corresponds to the gate electrode 160. "PAS" corresponds to the insulating layer 170.

[0058] As shown in FIG. 4 , in the first region A1, the impurity concentration profile has a peak in the gate electrode 160 (GL). Therefore, in the depth direction in the first region A1, the amount of impurity contained at a predetermined position in the gate electrode 160 is greater than the amount of impurity contained at a predetermined position in the oxide insulating layer 150, the amount of impurity contained at a predetermined position in the oxide semiconductor layer 140, and the amount of impurity contained at a predetermined position in the oxide insulating layer 120. The "depth direction" above refers to the thickness direction of each layer. Metallic materials have a high blocking power for impurities introduced by ion implantation. When a metallic material is used for the gate electrode 160, the impurities are blocked by the gate electrode 160 and do not reach the oxide insulating layer 150 (GI). Therefore, dangling bond defects DB due to the introduction of impurities are not formed in the oxide insulating layers 120 and 150 in the first region A1. However, impurities may reach the oxide insulating layer 150 as long as they do not affect the electrical characteristics of the semiconductor device 10.

[0059] In the second region A2, the impurity concentration profile has a peak in the oxide semiconductor layer 140 (OS). Therefore, in the depth direction in the second region A2, the amount of impurity contained at a predetermined position in the oxide semiconductor layer 140 is greater than the amount of impurity contained at a predetermined position in the oxide insulating layer 150, and is greater than the amount of impurity contained at a predetermined position in the oxide insulating layer 120. The purpose of introducing the impurity is to reduce the resistance of the oxide semiconductor layer 140 in the source region S and the drain region D, so the ion implantation conditions are set to obtain the above-described concentration profile. The amount of impurity contained in the oxide semiconductor layer 140 in the second region A2 is greater than the amount of impurity contained in the oxide semiconductor layer 140 in the first region A1. Similarly, the amount of impurity contained in the oxide insulating layer 120 (UC) in the second region A2 is greater than the amount of impurity contained in the oxide insulating layer 120 in the first region A1. Similarly, the amount of impurity contained in the oxide insulating layer 150 (GI) in the second region A2 is greater than the amount of impurity contained in the oxide insulating layer 150 in the first region A1.

[0060] Due to the above-described impurity concentration profile, impurities are also introduced into the oxide insulating layers 120 and 150 in the second region A2. Therefore, dangling bond defects DB associated with the introduction of impurities are formed in the oxide insulating layers 120 and 150. However, in the second region A2, the concentration of impurities present in the oxide insulating layers 120 and 150 is lower than the concentration of impurities present in the oxide semiconductor layer 140.

[0061] In the third region A3, the impurity concentration profile has a peak in the oxide insulating layer 120 (UC). Therefore, in the depth direction in the third region A3, the amount of impurities contained at a predetermined position in the oxide insulating layer 120 is greater than the amount of impurities contained at a predetermined position in the oxide insulating layer 150. In the third region A3, the oxide semiconductor layer 140 is not provided on the oxide insulating layer 120. Furthermore, the thickness of the oxide insulating layer 150 is the same in the second region A2 and the third region A3. As a result, instead of the peak of the concentration profile in the oxide semiconductor layer 140 in the second region A2, the peak of the concentration profile is in the oxide insulating layer 120 in the third region A3. In other words, the amount of impurities contained in the oxide insulating layer 120 in the third region A3 is greater than the amount of impurities contained in the oxide insulating layer 120 in the first region A1 and is greater than the amount of impurities contained in the oxide insulating layer 120 in the second region A2. Similarly, the amount of impurities contained in the oxide insulating layer 150 in the third region A3 is greater than the amount of impurities contained in the oxide insulating layer 150 in the first region A1, and is equal to the amount of impurities contained in a predetermined position of the oxide insulating layer 150 in the depth direction in the second region A2.

[0062] Due to the above-described impurity concentration profile, dangling bond defects DB are formed in the oxide insulating layer 120 due to the introduction of the impurity. As described above, a peak of the concentration profile exists in the oxide insulating layer 120 in the third region A3, and therefore the amount of dangling bond defects DB present in the oxide insulating layer 120 in the third region A3 is greater than the amount of dangling bond defects DB present in the oxide insulating layer 120 in the second region A2. Therefore, the oxide insulating layer 120 in the third region A3 can trap more hydrogen than the oxide insulating layer 150 in the third region A3, and can trap more hydrogen than the oxide insulating layer 120 in the second region A2.

[0063] In this embodiment, the amount of impurities contained at a predetermined position in the oxide insulating layer 120 in the depth direction in the third region A3 is 1×10 16 / cm 3 That's it, 1 x 10 17 / cm 3 or more, or 1 x 10 18 / cm 3 That is all. The predetermined position may be a peak position of the concentration profile or a position corresponding to the interface between the oxide insulating layer 120 and the oxide insulating layer 150. Alternatively, the predetermined position may be a position shifted a predetermined depth toward the oxide insulating layer 120 from the position corresponding to the interface.

[0064] Although the present embodiment exemplifies a configuration in which the amount of impurities contained in the oxide insulating layer 120 in the third region A3 is greater than the amount of impurities contained in the oxide insulating layer 120 in the second region A2, this configuration is not limited to this. Similarly, the present embodiment exemplifies a configuration in which the peak of the impurity concentration profile in the third region A3 exists in the oxide insulating layer 120, but this configuration is not limited to this. The peak may also exist in the oxide insulating layer 150. That is, the amount of impurities contained in the oxide insulating layer 120 in the third region A3 may be less than the amount of impurities contained in the oxide insulating layer 150. In this case, the peak of the impurity concentration profile in the second region A2 also exists in the oxide insulating layer 150. That is, the amount of impurities contained in the oxide semiconductor layer 140 in the second region A2 may be less than the amount of impurities contained in the oxide insulating layer 150. Furthermore, the present embodiment exemplifies a configuration in which the peak of the impurity concentration profile in the second region A2 exists in the oxide semiconductor layer 140, but this configuration is not limited to this. The peak may also exist in the oxide insulating layer 120.

[0065] 1 and 2, the channel region CH corresponds to the first region A1, the source region S and the drain region D correspond to the second region A2, and the region other than the channel region CH, the source region S, and the drain region D corresponds to the third region A3. That is, the channel region CH is sandwiched between the second regions A2 and surrounded by the third region A3. Therefore, for example, hydrogen diffused from the insulating layer 170 during the formation of the insulating layer 170 is trapped by dangling bond defects DB formed in the oxide insulating layers 120 and 150 provided in the second region A2 and the third region A3 located around the channel region CH. As a result, the hydrogen can be prevented from penetrating into the oxide semiconductor layer 140 in the channel region CH.

[0066] [1-4. Manufacturing Method of Semiconductor Device 10] A method for manufacturing a semiconductor device 10 according to one embodiment of the present invention will be described with reference to Fig. 5 to Fig. 13. Fig. 5 is a sequence diagram showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. Fig. 6 to Fig. 13 are cross-sectional views showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0067] As shown in FIGS. 5 and 6, a light-shielding layer 105 is formed on a substrate 100, and a nitride insulating layer 110 and an oxide insulating layer 120 are formed on the light-shielding layer 105 (step S1001, "Insulating layer / light-shielding layer formation" in FIG. 5). Silicon nitride, for example, is formed as the nitride insulating layer 110. Silicon oxide, for example, is formed as the oxide insulating layer 120. The nitride insulating layer 110 and the oxide insulating layer 120 are formed by a chemical vapor deposition (CVD) method. For example, the thickness of the nitride insulating layer 110 is 50 nm to 500 nm, or 150 nm to 300 nm. The thickness of the oxide insulating layer 120 is 50 nm to 500 nm, or 150 nm to 300 nm.

[0068] When silicon nitride is used for the nitride insulating layer 110, the nitride insulating layer 110 can block impurities diffusing from the substrate 100 toward the oxide semiconductor layer 140. For example, silicon oxide used for the oxide insulating layer 120 is silicon oxide that has the physical property of releasing oxygen by heat treatment.

[0069] 5 and 7, an oxide semiconductor layer 140 is formed on the oxide insulating layer 120 ("OS film formation" in step S1002 in FIG. 5). The oxide semiconductor layer 140 is formed by sputtering or atomic layer deposition (ALD).

[0070] When a metal oxide layer containing aluminum as its main component is provided between the oxide insulating layer 120 and the oxide semiconductor layer 140, the metal oxide layer is also formed by sputtering or atomic layer deposition in the same manner as described above.

[0071] The oxide semiconductor layer 140 has a thickness of, for example, 10 nm to 100 nm, 15 nm to 70 nm, or 20 nm to 40 nm. In this embodiment, the oxide semiconductor layer 140 has a thickness of 30 nm. The oxide semiconductor layer 140 is amorphous before heat treatment (OS annealing) described later.

[0072] When the oxide semiconductor layer 140 is crystallized by OS annealing, which will be described later, the oxide semiconductor layer 140 is preferably amorphous (having a small amount of crystalline components in the oxide semiconductor) after deposition and before OS annealing. That is, the deposition conditions for the oxide semiconductor layer 140 are preferably such that the oxide semiconductor layer 140 immediately after deposition is as little crystallized as possible. For example, when the oxide semiconductor layer 140 is deposited by a sputtering method, the oxide semiconductor layer 140 is deposited while controlling the temperature of the object to be deposited (the substrate 100 and a structure formed thereon).

[0073] When a film is formed on a target by sputtering, ions generated in the plasma and atoms recoiled from the sputtering target collide with the target, causing the temperature of the target to rise during the film formation process. If the temperature of the target increases during the film formation process, the oxide semiconductor layer 140 may contain microcrystals immediately after film formation, which may hinder crystallization by subsequent OS annealing. To control the temperature of the target, for example, the target can be cooled during film formation. For example, the target can be cooled from the side opposite the target surface so that the temperature of the target surface (hereinafter referred to as the "film formation temperature") is 100°C or less, 70°C or less, 50°C or less, or 30°C or less. By forming the oxide semiconductor layer 140 while cooling the target, the oxide semiconductor layer 140 can be formed with a small amount of crystalline components immediately after film formation. The oxide semiconductor layer 140 is formed under a partial pressure of oxygen of 2% to 20%, 3% to 15%, or 3% to 10%.

[0074] As shown in FIGS. 5 and 8, a pattern of the oxide semiconductor layer 140 is formed ("OS pattern formation" in step S1003 of FIG. 5). Although not shown, a resist mask is formed on the oxide semiconductor layer 140, and the oxide semiconductor layer 140 is etched using the resist mask. The oxide semiconductor layer 140 may be etched by wet etching or dry etching. Wet etching can be performed using an acidic etchant. Examples of the etchant that can be used include oxalic acid, PAN, sulfuric acid, hydrogen peroxide solution, and hydrofluoric acid. Because the oxide semiconductor layer 140 in step S1003 is amorphous, the oxide semiconductor layer 140 can be easily patterned into a predetermined shape by wet etching.

[0075] After the oxide semiconductor layer 140 is patterned, heat treatment (OS annealing) is performed on the oxide semiconductor layer 140 ("OS annealing" in step S1004 of FIG. 5). In the OS annealing, the oxide semiconductor layer 140 is held at a predetermined target temperature for a predetermined time. The predetermined target temperature is 300°C or higher and 500°C or lower, or 350°C or higher and 450°C or lower. The holding time at the target temperature is 15 minutes or higher and 120 minutes or lower, or 30 minutes or higher and 60 minutes or lower. In this embodiment, the oxide semiconductor layer 140 is crystallized by this OS annealing. However, the oxide semiconductor layer 140 does not necessarily have to be crystallized by the OS annealing.

[0076] As shown in FIGS. 5 and 9 , an oxide insulating layer 150 and a nitride insulating layer 155 are formed (step S1005 “GI formation” in FIG. 5 ). For example, silicon oxide is formed as the oxide insulating layer 150. For example, silicon nitride is formed as the nitride insulating layer 155. The oxide insulating layer 150 and the nitride insulating layer 155 are formed by a CVD method. For example, in order to form an insulating layer with few defects as the oxide insulating layer 150 as described above, the oxide insulating layer 150 may be formed at a film formation temperature of 350° C. or higher. The total thickness of the oxide insulating layer 150 and the nitride insulating layer 155 is, for example, 200 nm to 500 nm, 200 nm to 400 nm, or 250 nm to 350 nm. The thickness of the oxide insulating layer 150 is, for example, 100 nm or less, 50 nm or less, or 30 nm or less. After the oxide insulating layer 150 is formed, a process of implanting oxygen into the upper part of the oxide insulating layer 150 may be performed. As the oxygen implantation treatment, a metal oxide layer may be formed over the oxide insulating layer 150 by a sputtering method.

[0077] After the oxide insulating layer 150 and the nitride insulating layer 155 are formed on the oxide semiconductor layer 140, a heat treatment (oxidation annealing) is performed to supply oxygen to the oxide semiconductor layer 140 ("oxidation annealing" in step S1006 of FIG. 5). During the process from when the oxide semiconductor layer 140 is formed until when the oxide insulating layer 150 is formed on the oxide semiconductor layer 140, many oxygen vacancies are generated on the top surface 141 and side surface 143 of the oxide semiconductor layer 140. By the above-mentioned oxidation annealing, oxygen released from the oxide insulating layer 120 and the oxide insulating layer 150 is supplied to the oxide semiconductor layer 140, and the oxygen vacancies are repaired. If a process of implanting oxygen into the oxide insulating layer 150 is not performed, the oxidation annealing may be performed in a state where an insulating layer that releases oxygen by heat treatment is formed on the oxide insulating layer 150.

[0078] In order to increase the amount of oxygen supplied from the oxide insulating layer 150 to the oxide semiconductor layer 140, a metal oxide layer containing aluminum as its main component may be formed on the oxide insulating layer 150 by a sputtering method, and oxidation annealing may be performed in this state. By using aluminum oxide, which has a high gas barrier property, as the metal oxide layer, outward diffusion of oxygen implanted into the oxide insulating layer 150 during oxidation annealing can be suppressed. By forming the metal oxide layer and performing oxidation annealing as described above, oxygen implanted into the oxide insulating layer 150 is efficiently supplied to the oxide semiconductor layer 140. The metal oxide layer is removed after oxidation annealing. Note that the metal oxide layer may be formed on the nitride insulating layer 155, and oxidation annealing may be performed in this state.

[0079] As shown in FIGS. 5 and 10 , the gate electrode 160 is formed, and the gate insulating layer is half-etched (step S1007 in FIG. 5 , “GE formation + GI half-etching”). Specifically, in S1007, only the nitride insulating layer 155 is etched so that the oxide insulating layer 150 remains. The gate electrode 160 is formed by sputtering or atomic layer deposition. Note that, when a voltage is supplied to the light-shielding layer 105, openings may be formed in the nitride insulating layer 110, the oxide insulating layer 120, the oxide insulating layer 150, and the nitride insulating layer 155 before the gate electrode 160 is formed, and the light-shielding layer 105 and the gate electrode 160 may be connected through the openings. The gate electrode 160 is patterned by a photolithography process. The gate electrode 160 and the nitride insulating layer 155 may be etched in the same process (under the same conditions) or in different processes (under different conditions). In other words, the half-etching of the gate insulating layer may be performed by over-etching in the etching process for the gate electrode 160, or may be performed after etching of the gate electrode 160 by etching different from the etching for the gate electrode 160 using the gate electrode 160 as a mask.

[0080] In this embodiment, a configuration in which the thickness of the oxide insulating layer 150 in the first region A1 is the same as the thickness of the oxide insulating layer 150 in the second region A2 and the third region A3 has been exemplified, but this configuration is not limiting. For example, the thickness of the oxide insulating layer 150 in the second region A2 and the third region A3 may be smaller than the thickness of the oxide insulating layer 150 in the first region A1 by over-etching the oxide insulating layer 150 in the second region A2 and the third region A3 due to etching of the nitride insulating layer 155.

[0081] By half-etching the gate insulating layer (etching the nitride insulating layer 155), the thickness of the gate insulating layer in the second region A2 and the third region A3 (thickness of the oxide insulating layer 150) is thinned to 100 nm or less. The thickness of the oxide insulating layer 150 after the nitride insulating layer 155 is etched may be 100 nm or less, 50 nm or less, or 30 nm or less. The thickness of the oxide insulating layer 150 after etching is determined so that impurities reach the oxide insulating layer 120 by ion implantation, which will be described later.

[0082] 11 , after the gate electrode 160 is patterned and the nitride insulating layer 155 in the second region A2 and the third region A3 is etched, impurity ions are implanted into the oxide semiconductor layer 140 ("implantation of impurity ions" in step S1008 of FIG. 5). Specifically, impurities are implanted into the oxide insulating layer 120, the oxide semiconductor layer 140, and the oxide insulating layer 150 using the gate electrode 160 as a mask. By the ion implantation, elements such as boron (B), phosphorus (P), argon (Ar), or nitrogen (N) are implanted into the oxide insulating layer 120, the oxide semiconductor layer 140, and the oxide insulating layer 150.

[0083] In the oxide semiconductor layer 140 in the second region A2 that does not overlap with the gate electrode 160, oxygen defects are generated by ion implantation. Hydrogen is trapped in the generated oxygen defects, thereby reducing the resistance of the oxide semiconductor layer 140 in the second region A2. On the other hand, in the oxide semiconductor layer 140 in the first region A1 that overlaps with the gate electrode 160, impurities are not implanted, so no oxygen defects are generated and the resistance in the first region A1 does not decrease. Through the above steps, a channel region CH is formed in the oxide semiconductor layer 140 in the first region A1, and a source region S and a drain region D are formed in the oxide semiconductor layer 140 in the second region A2.

[0084] The ion implantation generates dangling bond defects DB in the oxide insulating layer 120 and the oxide insulating layer 150 in the second region A2 and the third region A3. The positions and amounts of the dangling bond defects DB can be controlled by adjusting the process parameters of the ion implantation (e.g., dose, acceleration voltage, plasma power, etc.). For example, the dose is 1×10 14 / cm 2 That's it, 5 x 10 14 / cm 2 or more, or 1 x 10 15 / cm 2 For example, the acceleration voltage is 10 keV or more, 15 keV or more, or 20 keV or more.

[0085] As shown in FIGS. 5 and 12, insulating layers 170 and 180 are formed as interlayer films on the oxide insulating layer 150 and the gate electrode 160 (step S1009 "interlayer film formation" in FIG. 5). The insulating layers 170 and 180 are formed by a CVD method. For example, a silicon nitride layer is formed as the insulating layer 170, and a silicon oxide layer is formed as the insulating layer 180. The materials used for the insulating layers 170 and 180 are not limited to those mentioned above. The thickness of the insulating layer 170 is 50 nm or more and 500 nm or less. The thickness of the insulating layer 180 is 50 nm or more and 500 nm or less.

[0086] 5 and 13, openings 171 and 173 are formed in the oxide insulating layer 150 and the insulating layers 170 and 180 ("contact hole" in step S1010 of FIG. 5). The opening 171 exposes the oxide semiconductor layer 140 in the source region S. The opening 173 exposes the oxide semiconductor layer 140 in the drain region D. Source-drain electrodes 200 are formed on the oxide semiconductor layer 140 exposed by the openings 171 and 173 and on the insulating layer 180 ("SD formation" in step S1011 of FIG. 5), thereby completing the semiconductor device 10 shown in FIG. 1.

[0087] In conventional configurations, the gate insulating layer was composed solely of an oxide insulating layer. Therefore, the half-etching process was performed by setting the etching time based on the etching rate of the oxide insulating layer, which was previously investigated. However, this method had the problem of making it difficult to control the thickness of the insulating layer in the second region A2 and the third region A3. Furthermore, in conventional configurations, because the gate insulating layer was composed solely of an oxide insulating layer, oxygen in the oxide insulating layer used as the gate insulating layer was absorbed by the metal used in the gate electrode during deposition, resulting in a decrease in the amount of oxygen supplied from the oxide insulating layer to the oxide semiconductor layer. To address this problem, conventional configurations have taken measures such as providing titanium as the bottom layer of the gate electrode. However, titanium has a low etching rate when dry-etched using fluorine-based process gases, which is commonly used for dry etching of metals, resulting in reduced throughput.

[0088] On the other hand, in the manufacturing method of the semiconductor device 10 according to this embodiment, when the nitride insulating layer 155 is etched and the oxide insulating layer 150 is exposed, the spectrum of the plasma emission generated during dry etching changes. Therefore, by analyzing the spectrum, the timing at which the nitride insulating layer 155 is removed can be detected. This allows for accurate control of the film thickness of the oxide insulating layer 150 in the second region A2 and the third region A3. Furthermore, the nitride insulating layer 155 on the oxide insulating layer 150 prevents oxygen from diffusing upward from the oxide insulating layer 150 during the formation of the gate electrode 160, eliminating the need to provide titanium in the bottom layer of the gate electrode.

[0089] [1-5. Hydrogen traps in dangling bond defects (DB)] 4, 5, and 14, impurities are also implanted into the oxide insulating layer 150 (GI) and the oxide insulating layer 120 (UC) in the second region A2 and the third region A3 by the ion implantation in step S1008. This impurity ion implantation generates dangling bond defects DB in the oxide insulating layers 120, 150 in the second region A2 and the third region A3. That is, the oxide insulating layers 120, 150 contain impurities such as boron (B), phosphorus (P), argon (Ar), or nitrogen (N). In this embodiment, of the oxide insulating layers 120, 150 in the second region A2 and the third region A3, the oxide insulating layer 120 in the third region A3 contains the largest amount of impurities. The amounts of impurities contained in the oxide insulating layers 150 in the second region A2 and the third region A3 are the same. FIG. 14 schematically shows dangling bond defects DB formed in the oxide insulating layers 120, 150 when impurities are introduced as described above.

[0090] In order for the insulating layer 170 to have the function of blocking impurities diffused from above, it is preferable that the insulating layer 170 be a dense film with few defects. To obtain such an insulating layer 170, the insulating layer 170 needs to be formed at a high temperature. For example, if a silicon nitride layer is formed as the insulating layer 170 at a high temperature, the insulating layer 170 contains a large amount of hydrogen, and a large amount of hydrogen diffuses from the insulating layer 170 to the oxide insulating layer 150 due to the film formation temperature. Therefore, if a hydrogen trapping region is not formed in the oxide insulating layers 120 and 150, hydrogen will diffuse through the oxide insulating layers 120 and 150 not only into the oxide semiconductor layer 140 in the source region S and the drain region D but also into the oxide semiconductor layer 140 in the channel region CH.

[0091] In step S1008, if the dangling bond defects DB shown in FIG. 14 are formed in the oxide insulating layers 120 and 150, hydrogen H diffused from the insulating layer 170 during the formation of the insulating layer 170 is trapped by the dangling bond defects DB as shown in FIG. 15 (shown with a circle overlaid on an x). Therefore, in step S1009, hydrogen H diffused from the insulating layer 170 during or after the formation of the insulating layer 170 can be prevented from penetrating into the oxide semiconductor layer 140 in the channel region CH. Therefore, a film containing a large amount of hydrogen can be used as the insulating layer 170, and therefore the insulating layer 170 can have a high impurity blocking function. Furthermore, the resistance of the oxide semiconductor layer 140 in the source region S and the drain region D can be sufficiently reduced.

[0092] In this embodiment, the amount of hydrogen H trapped in the oxide insulating layer 120 in the third region A3 is the largest among the oxide insulating layers 120, 150 in the second region A2 and the third region A3. The amount of hydrogen H trapped in the oxide insulating layer 150 in the second region A2 and the third region A3 is the same.

[0093] 16 is a schematic cross-sectional view illustrating the effect of hydrogen traps in a semiconductor device according to one embodiment of the present invention, and a diagram illustrating electrical characteristics of the semiconductor device. The electrical characteristics illustrated in FIG. 16 show the results 300 of investigating the influence of the location (layer) where hydrogen traps are formed on the electrical characteristics. The electrical characteristics illustrated in 310 in FIG. 16 are electrical characteristics when no hydrogen traps (relatively few hydrogen traps) are formed in both the oxide insulating layer 120 and the oxide insulating layer 150. The electrical characteristics illustrated in 320 in FIG. 16 are electrical characteristics when hydrogen traps are formed only in the oxide insulating layer 150. The electrical characteristics illustrated in 330 in FIG. 16 are electrical characteristics when hydrogen traps are formed only in the oxide insulating layer 120.

[0094] The hydrogen traps are not formed by ion implantation of impurities as in this embodiment, but are formed by adjusting the deposition conditions of each insulating layer. In the configuration of FIG. 16 , silicon oxide layers are used as the oxide insulating layer 120 and the oxide insulating layer 150. It is known that when a silicon oxide layer is formed under conditions containing excess oxygen, the silicon oxide layer contains many hydrogen traps. That is, under the conditions shown in 320 of FIG. 16 , a silicon oxide layer containing excess oxygen is used as the oxide insulating layer 150. Under the conditions shown in 330 of FIG. 16 , a silicon oxide layer containing excess oxygen is used as the oxide insulating layer 120. The configuration of FIG. 16 is the same as that of FIG. 1 except that the oxide insulating layer 150 is removed in a region that does not overlap with the gate electrode 160 and that the nitride insulating layer 155 is not provided.

[0095] As shown in 310 of FIG. 16 , when hydrogen traps are not formed in either the oxide insulating layer 120 or the oxide insulating layer 150, a hump in the electrical characteristics is observed. It has been found that the hump in the electrical characteristics occurs when hydrogen penetrates into the oxide semiconductor layer 140 in the channel region CH during the formation of the insulating layer 170. As shown in 320 of FIG. 16 , when hydrogen traps are formed only in the oxide insulating layer 150, the hump in the electrical characteristics is not improved. On the other hand, as shown in 330 of FIG. 16 , when hydrogen traps are formed only in the oxide insulating layer 120, the hump in the electrical characteristics is reduced. These results demonstrate that it is important to form hydrogen traps in the oxide insulating layer 120 in order to prevent hydrogen from penetrating into the oxide semiconductor layer 140 in the channel region CH during the formation of the insulating layer 170.

[0096] 2, 4, and 14, in the third region A3 surrounding the channel region CH, many dangling bond defects DB are formed in the oxide insulating layer 120. This configuration can suppress hydrogen from penetrating into the oxide semiconductor layer 140 in the channel region CH. As a result, a semiconductor device 10 having electrical characteristics in which humps are suppressed can be obtained.

[0097] [2. Second Embodiment] 17 to 22, a semiconductor device according to one embodiment of the present invention will be described. The semiconductor device 10 according to this embodiment is similar to the semiconductor device 10 according to the first embodiment, but differs therefrom in that the oxide insulating layer 150 is patterned in the same manner as the gate electrode 160 and the nitride insulating layer 155. In the following description, a description of the configuration common to the semiconductor device 10 according to the first embodiment will be omitted, and the description will focus mainly on the configuration different from the semiconductor device 10 according to the first embodiment.

[0098] 2-1. Configuration of semiconductor device 10 The configuration of a semiconductor device 10 according to one embodiment of the present invention will be described with reference to Fig. 17. Fig. 17 is a cross-sectional view showing an overview of a semiconductor device according to one embodiment of the present invention. The planar shape of the semiconductor device 10 according to this embodiment is the same as that of the semiconductor device 10 according to the first embodiment, and therefore description thereof will be omitted.

[0099] As shown in FIG. 17 , the oxide insulating layer 150 is patterned. Similar to the nitride insulating layer 155, the pattern edges of the oxide insulating layer 150 substantially coincide with the pattern edges of the gate electrode 160. That is, in plan view, the pattern of the oxide insulating layer 150 substantially coincides with the pattern of the gate electrode 160. In other words, the above configuration is expressed in other words such that the sidewall 152 of the oxide insulating layer 150 has a shape that follows the pattern of the gate electrode 160 in plan view. In the second region A2 (a region that does not overlap with the gate electrode 160 in plan view), the oxide semiconductor layer 140 contacts the insulating layer 170. The sidewall 152, together with the sidewall 157, contacts the insulating layer 170. The sidewall 152 may be referred to as a "second sidewall." In this embodiment, an oxide insulating layer is used as the insulating layer 170, and a nitride insulating layer is used as the insulating layer 180.

[0100] [2-2. Hydrogen trapping area configuration] In the semiconductor device 10 of this embodiment, the hydrogen trapping region is formed in the oxide insulating layer 120. The configuration of the hydrogen trapping region formed in the oxide insulating layer 120 will now be described with reference to FIGS. 18 and 19. FIG. 18 is a schematic partially enlarged cross-sectional view showing the configuration of a semiconductor device according to one embodiment of the present invention. Specifically, FIG. 18 is an enlarged cross-sectional view of region P in FIG. 17. Region P shown in FIG. 18 is a region near the drain region D, but the region near the source region S also has a similar configuration to region P.

[0101] The oxide insulating layer 120 is divided into a first region A1, a second region A2, and a third region A3. The oxide insulating layer 120 in each region is referred to as oxide insulating layers 120-1, 120-2, and 120-3, respectively. The oxide insulating layers 120-1 and 120-2 are in contact with the oxide semiconductor layer 140. The oxide insulating layer 120-3 is in contact with the insulating layer 170.

[0102] As will be described in detail later, in the semiconductor device 10 according to this embodiment, the gate insulating layer (oxide insulating layer 150 and nitride insulating layer 155) is removed by etching in the second region A2 and the third region A3, and ion implantation is performed in a state in which the oxide semiconductor layer 140 in the second region A2 and the oxide insulating layer 120 in the third region A3 are exposed. In the second region A2, the ion-implanted impurities reach the oxide insulating layer 120 through the oxide semiconductor layer 140. Similarly, in the third region A3, the ion-implanted impurities are introduced into the exposed oxide insulating layer 120. Therefore, dangling bond defects DB are generated in the oxide insulating layer 120 in the second region A2 and the third region A3.

[0103] In the first region A1, impurity ions are implanted using the gate electrode 160 as a mask. Therefore, in the first region A1, impurities are not implanted into the nitride insulating layer 155, the oxide insulating layer 150, and the oxide insulating layer 120-1, and dangling bond defects DB are not generated in these insulating layers. On the other hand, as described above, dangling bond defects DB are generated in the oxide insulating layers 120-2 and 120-3. For example, when silicon oxide is used as the oxide insulating layer 120, silicon dangling bond defects DB are formed in the oxide insulating layers 120-2 and 120-3.

[0104] The dangling bond defects DB formed in the oxide insulating layer 120 trap hydrogen. That is, in the semiconductor device 10, the oxide insulating layers 120-2 and 120-3 function as hydrogen trapping regions. Therefore, for example, hydrogen diffused from the insulating layers 170 and 180 during the formation of the insulating layers 170 and 180 is trapped by the dangling bond defects DB in the oxide insulating layers 120-2 and 120-3, thereby preventing hydrogen from penetrating into the oxide semiconductor layer 140 in the channel region CH. Therefore, after the insulating layers 170 and 180 are formed, the hydrogen concentrations in the oxide insulating layers 120-2 and 120-3 are higher than the hydrogen concentration in the oxide insulating layer 120-1.

[0105] Because the dangling bond defects DB are formed by ion implantation, the oxide insulating layers 120-2 and 120-3 contain impurities introduced by ion implantation. The distribution of the amount of dangling bond defects DB formed in the oxide insulating layers 120-2 and 120-3 corresponds to the concentration profile of the impurities contained therein. In other words, the positions and amounts of the dangling bond defects DB can be adjusted by adjusting the impurity profile obtained by ion implantation.

[0106] 19 is a graph showing impurity concentration profiles in the first region A1 to the third region A3 in a semiconductor device according to one embodiment of the present invention. The vertical axis of each of the three concentration profiles shown in FIG. 19 indicates the impurity concentration per unit volume (Concentration [ / cm3]), and the horizontal axis indicates the name of the layer in the depth direction. On the horizontal axis, "UC" corresponds to the oxide insulating layer 120 and the nitride insulating layer 110. "OS" corresponds to the oxide semiconductor layer 140. "GI" corresponds to the oxide insulating layer 150 and the nitride insulating layer 155. "GL" corresponds to the gate electrode 160. "PAS" corresponds to the insulating layer 170 and the insulating layer 180.

[0107] As shown in FIG. 19 , in the first region A1, the impurity concentration profile has a peak in the gate electrode 160 (GL). Therefore, in the depth direction in the first region A1, the amount of impurity contained at a predetermined position in the gate electrode 160 is greater than the amount of impurity contained at a predetermined position in the nitride insulating layer 155 and the oxide insulating layer 150 (GI), the amount of impurity contained at a predetermined position in the oxide semiconductor layer 140 (OS), and the amount of impurity contained in the oxide insulating layer 120 (UC). The “depth direction” above refers to the thickness direction of each layer. Metal materials have a high blocking power for impurities introduced by ion implantation. When a metal material is used for the gate electrode 160, the impurities are blocked by the gate electrode 160 and do not reach the nitride insulating layer 155. Therefore, dangling bond defects DB due to the introduction of impurities are not formed in the nitride insulating layer 155, the oxide insulating layer 150, and the oxide insulating layer 120 in the first region A1. However, impurities may reach the nitride insulating layer 155 and the oxide insulating layer 150 as long as they do not affect the electrical characteristics of the semiconductor device 10 .

[0108] In the second region A2, the impurity concentration profile has a peak in the oxide semiconductor layer 140 (OS). Therefore, in the depth direction in the second region A2, the amount of impurities contained at a predetermined position in the oxide semiconductor layer 140 is greater than the amount of impurities contained at a predetermined position in the oxide insulating layer 120 (UC). Since the purpose of introducing the impurities is to reduce the resistance of the oxide semiconductor layer 140 in the source region S and the drain region D, the ion implantation conditions are set to obtain the above-described concentration profile. The amount of impurities contained in the oxide semiconductor layer 140 in the second region A2 is greater than the amount of impurities contained in the oxide semiconductor layer 140 in the first region A1. Similarly, the amount of impurities contained in the oxide insulating layer 120 (UC) in the second region A2 is greater than the amount of impurities contained in the oxide insulating layer 120 in the first region A1.

[0109] As described above, in the second region A2, the impurity is also introduced into the oxide insulating layer 120. Therefore, dangling bond defects DB associated with the introduction of the impurity are formed in the oxide insulating layer 120-2 (see FIG. 18).

[0110] In the third region A3, the impurity concentration profile has a peak in the oxide insulating layer 120 (UC). In the third region A3, the oxide semiconductor layer 140 is not provided on the oxide insulating layer 120. As a result, instead of the peak of the concentration profile being in the oxide semiconductor layer 140 in the second region A2, the peak of the concentration profile is in the oxide insulating layer 120 in the third region A3. In other words, the amount of impurities contained in the oxide insulating layer 120 in the third region A3 is greater than the amount of impurities contained in the oxide insulating layer 120 in the first region A1 and is greater than the amount of impurities contained in the oxide insulating layer 120 in the second region A2.

[0111] Due to the above-described impurity concentration profile, dangling bond defects DB are formed in the oxide insulating layer 120-3 due to the introduction of the impurity (see FIG. 18). As described above, a peak of the concentration profile exists in the oxide insulating layer 120 in the third region A3, and therefore the amount of dangling bond defects DB present in the oxide insulating layer 120 in the third region A3 is greater than the amount of dangling bond defects DB present in the oxide insulating layer 120 in the second region A2. Therefore, the oxide insulating layer 120 in the third region A3 can trap more hydrogen than the oxide insulating layer 120 in the second region A2.

[0112] In this embodiment, the amount of impurities contained at a predetermined position in the oxide insulating layer 120 in the depth direction in the third region A3 is 1×10 16 / cm 3 That's it, 1 x 10 17 / cm 3 or more, or 1 x 10 18 / cm 3That is all. The predetermined position may be the peak position of the concentration profile, or may be a position corresponding to the interface between the oxide insulating layer 120 and the insulating layer 170. Alternatively, the predetermined position may be a position shifted a predetermined depth toward the oxide insulating layer 120 from the position corresponding to the interface.

[0113] Although the present embodiment exemplifies a configuration in which the amount of impurities contained in the oxide insulating layer 120 in the third region A3 is greater than the amount of impurities contained in the oxide insulating layer 120 in the second region A2, the present embodiment is not limited to this configuration. Similarly, the present embodiment exemplifies a configuration in which the peak of the impurity concentration profile in the second region A2 exists in the oxide semiconductor layer 140, but the present embodiment is not limited to this configuration. For example, the peak may exist in the oxide insulating layer 120 in the depth direction of the second region A2.

[0114] 2-3. Manufacturing Method of Semiconductor Device 10 A method for manufacturing a semiconductor device 10 according to one embodiment of the present invention will be described with reference to Figures 20 to 22. Figure 20 is a sequence diagram showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figures 21 and 22 are cross-sectional views showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0115] The sequence of the semiconductor device 10 according to this embodiment is similar to the sequence of the semiconductor device 10 according to the first embodiment (FIG. 5), but differs in that GI etching is performed in S1020 in Fig. 20 instead of GI half etching in S1007 in Fig. 5. In the following explanation, the steps of S1001 to S1006 are the same as those in Fig. 5, and therefore will not be described again.

[0116] As shown in FIGS. 20 and 21 , the gate electrode 160 is formed, and then the gate electrode 160, the nitride insulating layer 155, and the oxide insulating layer 150 are etched together (“GE formation+GI etching” in step S1020 of FIG. 5 ). The gate electrode 160 is formed by sputtering or atomic layer deposition. The gate electrode 160, the nitride insulating layer 155, and the oxide insulating layer 150 are patterned by a photolithography process. The gate electrode 160, the nitride insulating layer 155, and the oxide insulating layer 150 may be etched in the same process (under the same conditions), or may be etched in different processes (under different conditions). That is, the etching of the nitride insulating layer 155 and the oxide insulating layer 150 may be performed by over-etching in the etching process for the gate electrode 160, or may be performed after the etching of the gate electrode 160 by etching the gate electrode 160 using the gate electrode 160 as a mask, which is different from the etching of the gate electrode 160.

[0117] 22, the gate electrode 160, the nitride insulating layer 155, and the oxide insulating layer 150 are patterned to expose the oxide semiconductor layer 140 in the second region A2 and the oxide insulating layer 120 in the third region A3. In this state, impurity ions are implanted into the exposed oxide insulating layer 120 and the oxide semiconductor layer 140 ("implantation of impurity ions" in step S1008 of FIG. 20). Specifically, the gate electrode 160 is used as a mask to implant the impurities into the exposed oxide insulating layer 120 and the oxide semiconductor layer 140.

[0118] Through the above steps, a channel region CH is formed in the oxide semiconductor layer 140 in the first region A1, and a source region S and a drain region D are formed in the oxide semiconductor layer 140 in the second region A2.

[0119] The ion implantation generates dangling bond defects DB in the oxide insulating layer 120 in the second region A2 and the third region A3. The positions and amount of the dangling bond defects DB can be controlled by adjusting the process parameters of the ion implantation (e.g., dose, acceleration voltage, plasma power, etc.). For example, the dose is 1×10 14 / cm 2 That's it, 5 x 10 14 / cm 2 or more, or 1 x 10 15 / cm 2 For example, the acceleration voltage is 10 keV or more, 15 keV or more, or 20 keV or more.

[0120] In the semiconductor device 10 of this embodiment, many dangling bond defects DB are formed in the oxide insulating layer 120 in the third region A3 surrounding the channel region CH, and therefore, the same effect as that of the semiconductor device 10 of the first embodiment can be obtained.

[0121] 3. Third Embodiment 23 to 28, a semiconductor device according to one embodiment of the present invention will be described. The semiconductor device 10 according to this embodiment is similar to the semiconductor device 10 according to the second embodiment, but differs therefrom in that an oxide insulating layer 165 is provided between the gate electrode 160 and the insulating layer 170. In the following description, a description of the configuration common to the semiconductor device 10 according to the second embodiment will be omitted, and the description will focus mainly on the configuration different from the semiconductor device 10 according to the second embodiment.

[0122] 3-1. Configuration of Semiconductor Device 10 The configuration of a semiconductor device 10 according to one embodiment of the present invention will be described with reference to Fig. 23. Fig. 23 is a cross-sectional view showing an overview of a semiconductor device according to one embodiment of the present invention. The plan view of the semiconductor device 10 is the same as the plan view shown in Fig. 2, so a description thereof will be omitted.

[0123] 23, the semiconductor device 10 includes an oxide insulating layer 165 in addition to a light-shielding layer 105, a nitride insulating layer 110, an oxide insulating layer 120, an oxide semiconductor layer 140, an oxide insulating layer 150, a nitride insulating layer 155, a gate electrode 160, insulating layers 170 and 180, and a source / drain electrode 200. As described above, a nitride insulating layer is used as the insulating layer 170.

[0124] The oxide insulating layer 165 covers the oxide semiconductor layer 140 and the gate electrode 160. That is, the oxide insulating layer 165 is provided between the gate electrode 160 and the insulating layer 170 in the first region A1, between the oxide semiconductor layer 140 and the insulating layer 170 in the second region A2, and between the oxide insulating layer 120 and the insulating layer 170 in the third region A3. The thickness of the oxide insulating layer 165 is 50 nm or more and 100 nm or less, or 70 nm or more and 100 nm or less.

[0125] [3-2. Hydrogen trapping area configuration] 24 is a schematic partially enlarged cross-sectional view illustrating a configuration of a semiconductor device according to one embodiment of the present invention. As will be described in detail later, dangling bond defects DB generated in the oxide insulating layer 120 and the oxide insulating layer 165 illustrated in FIG. 24 are generated by ion implantation performed after the oxide insulating layer 165 is formed.

[0126] 25 is a graph showing impurity concentration profiles in the first region A1 to the third region A3 in a semiconductor device according to one embodiment of the present invention. The vertical axis of each of the three concentration profiles shown in FIG. 25 indicates the impurity concentration per unit volume (Concentration [ / cm3]), and the horizontal axis indicates the name of the layer in the depth direction. On the horizontal axis, "UC" corresponds to the oxide insulating layer 120 and the nitride insulating layer 110. "OS" corresponds to the oxide semiconductor layer 140. "GI" corresponds to the oxide insulating layer 150 and the nitride insulating layer 155. "GL" corresponds to the gate electrode 160. "PAS1" corresponds to the oxide insulating layer 165. "PAS2" corresponds to the insulating layer 170.

[0127] 25, in the first region A1, the impurities are contained in the gate electrode 160 (GL) and the oxide insulating layer 165 (PAS1), and the concentration profile of the impurities has a peak in the gate electrode 160. Therefore, in the depth direction in the first region A1, the amount of impurities contained in a predetermined position in each of the gate electrode 160 and the oxide insulating layer 165 is greater than the amount of impurities contained in a predetermined position in the nitride insulating layer 155 and the oxide insulating layer 150 (GI), the amount of impurities contained in a predetermined position in the oxide semiconductor layer 140 (OS), and the amount of impurities contained in the oxide insulating layer 120 (UC).

[0128] In the second region A2, impurities are contained in the oxide insulating layer 120 (UC), the oxide semiconductor layer 140 (OS), and the oxide insulating layer 165 (PAS1), and the concentration profile of the impurities has a peak in the oxide semiconductor layer 140. Therefore, in the depth direction in the second region A2, the amount of impurities contained at a predetermined position in the oxide semiconductor layer 140 is greater than the amount of impurities contained at a predetermined position in the oxide insulating layer 120, and is greater than the amount of impurities contained at a predetermined position in the oxide insulating layer 165.

[0129] As described above, in the second region A2, impurities are introduced into the oxide insulating layer 120 and the oxide insulating layer 165. Therefore, dangling bond defects DB are formed in the oxide insulating layer 120 and the oxide insulating layer 165 due to the introduction of the impurities.

[0130] In the third region A3, impurities are contained in the oxide insulating layer 120 and the oxide insulating layer 165, and the concentration profile of the impurities has a peak in the oxide insulating layer 120 (UC). In the third region A3, the oxide semiconductor layer 140 is not provided on the oxide insulating layer 120. As a result, instead of the peak of the concentration profile being in the oxide semiconductor layer 140 in the second region A2, the peak of the concentration profile is in the oxide insulating layer 120 in the third region A3. In other words, the amount of impurities contained in the oxide insulating layer 120 in the third region A3 is greater than the amount of impurities contained in the oxide insulating layer 120 in the first region A1 and is greater than the amount of impurities contained in the oxide insulating layer 120 in the second region A2.

[0131] Due to the above-described impurity concentration profile, dangling bond defects DB are formed in the oxide insulating layer 120 and the oxide insulating layer 165 due to the introduction of the impurity. As described above, a peak in the concentration profile exists in the oxide insulating layer 120 in the third region A3, and therefore the amount of dangling bond defects DB present in the oxide insulating layer 120 in the third region A3 is greater than the amount of dangling bond defects DB present in the oxide insulating layer 120 in the second region A2. Therefore, the oxide insulating layer 120 in the third region A3 can trap more hydrogen than the oxide insulating layer 120 in the second region A2. A thickness of the oxide insulating layer 165 of 50 nm or more can achieve a significant effect by trapping hydrogen from the insulating layer 170.

[0132] In this embodiment, as described above, a configuration has been exemplified in which the impurity concentration profile in the first region A1 has a peak in the gate electrode 160, in the second region A2 the concentration profile has a peak in the oxide semiconductor layer 140, and in the third region A3 the concentration profile has a peak in the oxide insulating layer 120, but this configuration is not limited to this.

[0133] For example, when the oxide semiconductor layer 140 is relatively thin, the concentration profile in the second region A2 may have a peak in the oxide insulating layer 120 or near the interface between the oxide semiconductor layer 140 and the oxide insulating layer 120. On the other hand, when the oxide insulating layer 165 is relatively thick, the concentration profile in the first region A1 to the third region A3 may have a peak in the oxide insulating layer 165 or near the interface between the oxide insulating layer 165 and a layer below the oxide insulating layer 165. The layers below the oxide insulating layer 165 are the gate electrode 160 in the first region A1, the oxide semiconductor layer 140 in the second region A2, and the oxide insulating layer 120 in the third region A3.

[0134] In this embodiment, the amount of impurities contained at a predetermined position in the oxide insulating layer 120 in the depth direction in the third region A3 is 1×10 16 / cm 3 That's it, 1 x 10 17 / cm 3 or more, or 1 x 10 18 / cm 3 That is all. The predetermined position may be a peak position of the concentration profile or a position corresponding to the interface between the oxide insulating layer 120 and the oxide insulating layer 165. Alternatively, the predetermined position may be a position shifted a predetermined depth toward the oxide insulating layer 120 from the position corresponding to the interface.

[0135] 3-3. Manufacturing Method of Semiconductor Device 10 A method for manufacturing a semiconductor device 10 according to one embodiment of the present invention will be described with reference to Figures 26 to 28. Figure 26 is a sequence diagram showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figures 27 to 28 are cross-sectional views showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. Steps S1001 to S1006 and S1020 shown in Figure 26 are similar to steps S1001 to S1006 and S1020 shown in Figure 20, and therefore description thereof will be omitted.

[0136] 21, the gate electrode 160 is formed, and the gate electrode 160, the nitride insulating layer 155, and the oxide insulating layer 150 are etched together. Then, as shown in FIG. 27, an oxide insulating layer 165 is formed on the oxide insulating layer 120, the oxide semiconductor layer 140, and the gate electrode 160 (step S1021 "oxide insulating layer formation" in FIG. 26). The oxide insulating layer 165 is formed by a CVD method. For example, a silicon oxide layer is formed as the oxide insulating layer 165. An insulating layer with a relatively low hydrogen content is used as the oxide insulating layer 165. For example, the hydrogen content of the oxide insulating layer 165 is 1×10 21 cm -3 The following is the result.

[0137] When a silicon oxide layer is used as the oxide insulating layer 165, the silicon oxide layer is formed under conditions where the ratio of silane (SiH4) to dinitrogen monoxide (N2O) is relatively small, for example, [N2O / SiH4] is 30 or less.

[0138] When impurities are implanted by ion implantation to reach the oxide insulating layer 120, there is a limit imposed by the acceleration voltage of the ion implantation device, so the thickness of the oxide insulating layer 165 is less than 100 nm.

[0139] As shown in FIGS. 26 and 28, impurity ions are implanted into the oxide insulating layer 165 ("implantation of impurity ions" in step S1022 of FIG. 26). In this embodiment, the impurities are implanted so that peaks of the impurity concentration profile are present in the oxide semiconductor layer 140 (second region A2) and the oxide insulating layer 120 (third region A3) provided below the oxide insulating layer 165. By the ion implantation, elements such as boron (B), phosphorus (P), argon (Ar), or nitrogen (N) are implanted into the oxide semiconductor layer 140 and the oxide insulating layer 120 through the oxide insulating layer 165. By this ion implantation, dangling bond defects DB are generated in the oxide insulating layer 120 in the second region A2, the oxide insulating layer 120 in the third region A3, and the oxide insulating layer 165 in the first region A1 to the third region A3. The position and amount of dangling bond defects DB can be controlled by adjusting the process parameters of ion implantation (e.g., dose, acceleration voltage, plasma power, etc.). For example, the dose is 1×10 14 / cm 2 That's it, 5 x 10 14 / cm 2 or more, or 1 x 10 15 / cm 2 For example, when the element to be implanted is boron (B), the acceleration voltage is 10 keV or more and 50 keV or less.

[0140] After the above ion implantation, insulating layers 170 and 180 are formed as interlayer films on the oxide insulating layer 165 (step S1009, "interlayer film formation," in FIG. 26), and openings 171 and 173 are formed in the insulating layers 170 and 180 (step S1010, "contact hole opening," in FIG. 26). Source-drain electrodes 200 are formed on the oxide semiconductor layer 140 exposed by the openings 171 and 173 and on the insulating layer 180 (step S1011, "SD formation," in FIG. 26), thereby completing a semiconductor device 10 similar to that shown in FIG. 23.

[0141] In this embodiment, as shown in FIGS. 24 and 25 , dangling bond defects DB are formed not only in the oxide insulating layer 120 but also in the oxide insulating layer 165, thereby suppressing hydrogen penetration into the oxide semiconductor layer 140 in the channel region CH. As a result, a semiconductor device 10 having electrical characteristics in which humps are suppressed can be obtained. Furthermore, in this embodiment, an insulating layer with a relatively low hydrogen content is used as the oxide insulating layer 165, thereby suppressing hydrogen penetration into the oxide semiconductor layer 140 in the channel region CH when the oxide insulating layer 165 is formed. Furthermore, dangling bond defects DB can be formed in both the oxide insulating layer 120 and the oxide insulating layer 165 by a single ion implantation step.

[0142] [4. Fourth Embodiment] 29 and 30, a semiconductor device according to one embodiment of the present invention will be described. The semiconductor device 10 according to this embodiment is similar to the semiconductor device 10 according to the third embodiment, but differs therefrom in that a nitride insulating layer 169 is provided instead of the oxide insulating layer 165. In the following description, a description of the configuration common to the semiconductor device 10 according to the third embodiment will be omitted, and the description will focus mainly on the configuration different from the semiconductor device 10 according to the third embodiment.

[0143] 4-1. Configuration of the semiconductor device 10 Fig. 29 is a cross-sectional view showing an overview of a semiconductor device according to one embodiment of the present invention. The plan view of the semiconductor device 10 is the same as the plan view shown in Fig. 2, so a description thereof will be omitted. As shown in Fig. 29, in the semiconductor device 10 according to this embodiment, a nitride insulating layer 169 is provided on the gate electrode 160, and an insulating layer 180 is provided on the nitride insulating layer 169. As described above, an oxide insulating layer is used as the insulating layer 180.

[0144] The nitride insulating layer 169 covers the oxide semiconductor layer 140 and the gate electrode 160. That is, the nitride insulating layer 169 is provided between the gate electrode 160 and the insulating layer 180 in the first region A1, between the oxide semiconductor layer 140 and the insulating layer 180 in the second region A2, and between the oxide insulating layer 120 and the insulating layer 180 in the third region A3. In the second region A2 (a region that does not overlap with the gate electrode 160 in a plan view), the nitride insulating layer 169 is in contact with the oxide semiconductor layer 140. The thickness of the nitride insulating layer 169 is 50 nm or more and 300 nm or less, or 70 nm or more and 100 nm or less.

[0145] 4-2. Manufacturing Method of Semiconductor Device 10 A method for manufacturing a semiconductor device 10 according to one embodiment of the present invention will be described with reference to Fig. 30. Fig. 30 is a sequence diagram showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. Steps S1001 to S1006 and S1020 shown in Fig. 30 are similar to steps S1001 to S1006 and S1020 shown in Fig. 26, and therefore description thereof will be omitted.

[0146] 21, the gate electrode 160 is formed, and the gate electrode 160, the nitride insulating layer 155, and the oxide insulating layer 150 are etched together. Then, the nitride insulating layer 169 is formed on the oxide insulating layer 120, the oxide semiconductor layer 140, and the gate electrode 160 (step S1030 "Nitride insulating layer formation" in FIG. 30) as in FIG. 27. The nitride insulating layer 169 is formed by a CVD method. For example, a silicon nitride layer is formed as the nitride insulating layer 169.

[0147] When the nitride insulating layer 169 is formed on the oxide semiconductor layer 140 while the surface of the oxide semiconductor layer 140 is exposed, oxygen vacancies are generated in the oxide semiconductor layer 140 in the regions where the nitride insulating layer 169 is formed (the source region S and the drain region D). Hydrogen is trapped in the generated oxygen vacancies, thereby reducing the resistance of the oxide semiconductor layer 140 in the source region S and the drain region D. That is, in the manufacturing method of the semiconductor device 10 according to this embodiment, the resistance of the oxide semiconductor layer 140 can be reduced without implanting impurity ions into the oxide semiconductor layer 140. Steps S1009 to S1011 in FIG. 30 are the same as steps S1009 to S1011 in FIG. 26 , and therefore description thereof will be omitted.

[0148] In this embodiment, the resistance of the oxide semiconductor layer 140 in the source region S and the drain region D can be reduced without implanting impurity ions into the oxide semiconductor layer 140 as described above. [5. Fifth Embodiment] 31 to 33, a semiconductor device according to one embodiment of the present invention will be described. The semiconductor device 10 according to this embodiment is similar to the semiconductor device 10 according to the first embodiment, but differs from the semiconductor device 10 according to the first embodiment in that a nitride insulating layer 155 is formed on an oxide insulating layer 150 also in the second region A2 and the third region A3. In the following explanation, a description of the configuration common to the semiconductor device 10 according to the first embodiment will be omitted, and the configuration different from the semiconductor device 10 according to the first embodiment will be mainly explained.

[0149] 5-1. Configuration of Semiconductor Device 10 Fig. 31 is a cross-sectional view showing an overview of a semiconductor device according to one embodiment of the present invention. The plan view of the semiconductor device 10 is the same as the plan view shown in Fig. 2, and therefore description thereof will be omitted. As shown in Fig. 31, in the semiconductor device 10 according to this embodiment, the nitride insulating layer 155 is half-etched using the gate electrode 160 as a mask. In other words, the thickness of the nitride insulating layer 155 in the second region A2 and the third region A3 (regions that do not overlap with the gate electrode 160 in a plan view) is smaller than the thickness of the nitride insulating layer 155 in the first region A1 (region that overlaps with the gate electrode 160 in a plan view).

[0150] The total thickness of the oxide insulating layer 150 and the nitride insulating layer 155 in the first region A1 is 200 nm or more. The total thickness of the oxide insulating layer 150 and the nitride insulating layer 155 in the second region A2 and the third region A3 is 100 nm or less. FIG. 31 illustrates a configuration in which the nitride insulating layer 155 remains uniformly in the second region A2 and the third region A3, but this configuration is not limiting. For example, the nitride insulating layer 155 may not remain in some regions of the second region A2 and the third region A3. In other words, the nitride insulating layer 155 may be completely etched in those regions.

[0151] 5-2. Manufacturing Method of Semiconductor Device 10 The sequence diagram showing the manufacturing method of the semiconductor device 10 according to this embodiment is the same as that shown in Fig. 5, and therefore the description thereof will be omitted. In the first embodiment, the nitride insulating layer 155 is completely etched in the GI half etching in S1007 in Fig. 5, whereas in this embodiment, the nitride insulating layer 155 is etched so as to leave a portion of it in the GI half etching.

[0152] As shown in FIG. 32, a gate electrode 160 is formed, and then the nitride insulating layer 155 is half-etched using the gate electrode 160 as a mask. The half-etching of the nitride insulating layer 155 is performed by investigating in advance the etching rate of the nitride insulating layer 155 under the etching conditions used for the half-etching, and setting the etching time based on the etching rate. The half-etching reduces the total thickness of the nitride insulating layer 155 and the oxide insulating layer 150 in the second region A2 and the third region A3 to 100 nm or less. After the half-etching, the total thickness of the nitride insulating layer 155 and the oxide insulating layer 150 in the second region A2 and the third region A3 may be 50 nm or less, or 30 nm or less.

[0153] 33, impurity ions are implanted into the oxide semiconductor layer 140 with the nitride insulating layer 155 half-etched. Specifically, impurities are implanted into the oxide insulating layer 120, the oxide semiconductor layer 140, the oxide insulating layer 150, and the nitride insulating layer 155 using the gate electrode 160 as a mask. By the ion implantation, elements such as boron (B), phosphorus (P), argon (Ar), or nitrogen (N) are implanted into the oxide insulating layer 120, the oxide semiconductor layer 140, and the oxide insulating layer 150. Thereafter, the same processes as those in steps S1009 to S1011 of FIG. 5 are performed to complete the semiconductor device 10.

[0154] The semiconductor device 10 according to this embodiment can achieve the same effects as the semiconductor device 10 according to the first embodiment.

[0155] The above-described embodiments of the present invention may be combined as appropriate as long as they are not mutually inconsistent. Furthermore, even if a person skilled in the art appropriately adds or deletes components or modifies the design, or adds or omits steps or modifies conditions based on the embodiments, such combinations are included within the scope of the present invention as long as they include the gist of the present invention.

[0156] Even if there are other effects and advantages different from those brought about by the aspects of each of the above-mentioned embodiments, those that are clear from the description in this specification or that can be easily predicted by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0157] 10: semiconductor device, 100: substrate, 105: light-shielding layer, 110: nitride insulating layer, 120: oxide insulating layer, 140: oxide semiconductor layer, 141: upper surface, 142: lower surface, 143: side surface, 150: oxide insulating layer, 152, 157: sidewall, 155: nitride insulating layer, 160: gate electrode, 161: opening, 165: oxide insulating layer, 169: nitride insulating layer, 170: insulating layer, 171, 173: opening, 180: insulating layer, 200: source-drain electrode, 201: source electrode, 203: drain electrode, 300: result, A1: first region, A2: second region, A3: third region, CH: channel region, D: drain region, DB: dangling bond defect, L: channel length, P: region, S: source region, W: channel width

Claims

1. a first oxide insulating layer; an oxide semiconductor layer on the first oxide insulating layer; a second oxide insulating layer covering the oxide semiconductor layer; a nitride insulating layer on the second oxide insulating layer; a gate electrode on the nitride insulating layer; an insulating layer covering the gate electrode; the nitride insulating layer has a first sidewall having a shape that follows the pattern of the gate electrode in a plan view; The first sidewall is in contact with the insulating layer.

2. The semiconductor device according to claim 1 , wherein said second oxide insulating layer is in contact with said insulating layer in a region not overlapping with said gate electrode in a plan view.

3. 2. The semiconductor device according to claim 1, wherein the thickness of said nitride insulating layer in a region not overlapping said gate electrode in a plan view is smaller than the thickness of said nitride insulating layer in a region overlapping said gate electrode in a plan view.

4. a thickness of the second oxide insulating layer in a region not overlapping with the gate electrode in a plan view is 100 nm or less; 4. The semiconductor device according to claim 2, wherein the total thickness of the second oxide insulating layer and the nitride insulating layer in a region overlapping with the gate electrode in a plan view is 200 nm or more.

5. the second oxide insulating layer has a second sidewall having a shape that follows the pattern of the gate electrode in a plan view; The semiconductor device according to claim 1 , wherein the second sidewall is in contact with the insulating layer.

6. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer is in contact with the insulating layer in a region that does not overlap with the gate electrode in a plan view.

7. 7. The semiconductor device according to claim 6, wherein said insulating layer is an oxide insulating layer.

8. 7. The semiconductor device according to claim 6, wherein said insulating layer is a nitride insulating layer.

9. a thickness of the insulating layer in a region not overlapping with the gate electrode in a plan view is 100 nm or less; 9. The semiconductor device according to claim 5, wherein a total thickness of said second oxide insulating layer and said nitride insulating layer in a region overlapping with said gate electrode in a plan view is 200 nm or more.

10. 9. The semiconductor device according to claim 1, wherein an amount of impurities contained in the oxide semiconductor layer in a second region that does not overlap with the insulating layer gate electrode in a planar view is greater than an amount of the impurities contained in the oxide semiconductor layer in a first region that overlaps with the gate electrode in a planar view.

11. 11. The semiconductor device according to claim 10, wherein the amount of the impurity contained in the first oxide insulating layer in the second region is greater than the amount of the impurity contained in the first oxide insulating layer in the first region.

12. 12. The semiconductor device according to claim 11, wherein an amount of the impurity contained in the first oxide insulating layer in a third region that does not overlap with the oxide semiconductor layer in a plan view is greater than an amount of the impurity contained in the first oxide insulating layer in the second region.

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