Illuminance sensor

Abstract

To alleviate an influence of noise in an illuminance sensor including photodiodes.SOLUTION: An illuminance sensor comprises: an illuminance detection circuit (2) for detecting the illuminance of incidence light (IL) using a first and a second photodiode (10, 20); and a shading metal (235) for shielding the incidence of incidence light on the second photodiode. The illuminance detection circuit generates a first signal according to photocurrent generated in the first photodiode when the incidence light is incident on the first photodiode, and according to dark current of the first photodiode, and generates a second signal according to dark current of the second photodiode, in order to detect the illuminance of incidence light based on the first signal and the second signal. The shading metal is insulated from the illuminance detection circuit.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present disclosure relates to an illuminance sensor. [Background technology]

[0002] Illuminance sensors having photodiodes are widely used (see, for example, Patent Document 1 below). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-134704

[0004] [overview] It is important to reduce the influence of noise in an ambient light sensor having a photodiode.

[0005] An illuminance sensor according to one embodiment of the present disclosure comprises an illuminance detection circuit configured to detect the illuminance of light incident on the illuminance sensor using a first photodiode and a second photodiode, and a light-shielding metal that blocks the incident light from reaching the second photodiode, wherein the illuminance detection circuit comprises: a first sense circuit having the first photodiode and configured to generate a first signal corresponding to a photocurrent generated in the first photodiode when the incident light reaches the first photodiode and a dark current of the first photodiode; and a second sense circuit having the second photodiode and configured to generate a second signal corresponding to the dark current of the second photodiode, and detects the illuminance of the incident light based on the first signal and the second signal, and the light-shielding metal is insulated from the illuminance detection circuit. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is an external perspective view of an illuminance sensor according to an embodiment of the present disclosure. [Figure 2]FIG. 2 is a schematic diagram of a semiconductor chip according to an embodiment of the present disclosure. [Figure 3] FIG. 3 is a schematic top view of a semiconductor substrate according to an embodiment of the present disclosure. [Figure 4] FIG. 4 is a diagram showing the positional relationship between each region in a semiconductor substrate and a metal film according to an embodiment of the present disclosure. [Figure 5] FIG. 5 is a diagram showing the positional relationship between each region in a semiconductor substrate and a metal film according to an embodiment of the present disclosure. [Figure 6] FIG. 6 is a diagram illustrating a schematic vertical structure of a semiconductor chip according to an embodiment of the present disclosure. [Figure 7] FIG. 7 is a configuration diagram of an illuminance detection circuit according to an embodiment of the present disclosure. [Figure 8] FIG. 8 is a diagram showing a state in which an illuminance sensor and a host device are connected according to an embodiment of the present disclosure. [Figure 9] FIG. 9 is a diagram showing the positional and dimensional relationship between the photodiode region and the specific metal film according to the embodiment of the present disclosure. [Figure 10] FIG. 10 is a diagram illustrating a state of the illuminance detection circuit when detecting illuminance according to an embodiment of the present disclosure. [Figure 11] FIG. 11 is a diagram showing waveforms of two sense signals during an integration period and its surrounding period according to an embodiment of the present disclosure. [Figure 12] FIG. 12 is a diagram illustrating the influence of noise on the illuminance sensor according to a reference example. [Figure 13] FIG. 13 is a diagram illustrating the influence of noise on the illuminance sensor according to a reference example. [Figure 14] FIG. 14 is a diagram illustrating the influence of noise on the illuminance sensor according to a reference example. [Figure 15] FIG. 15 is a diagram illustrating the influence of noise on the illuminance sensor according to the embodiment of the present disclosure. [Figure 16] FIG. 16 is a configuration diagram of an illuminance detection circuit according to a first example belonging to an embodiment of the present disclosure. [Figure 17] FIG. 17 is a diagram showing the states of four switches and the waveforms of two sense signals in an illuminance detection circuit according to a first example of an embodiment of the present disclosure. [Figure 18] FIG. 18 is a diagram showing the positions at which a plurality of photodiode regions are formed according to a second example of the embodiment of the present disclosure. [Figure 19] FIG. 19 is a diagram showing a modified configuration of each sense circuit according to a third example belonging to an embodiment of the present disclosure.

[0007] [Detailed explanation] Hereinafter, examples of embodiments of the present disclosure will be described in detail with reference to the drawings. In each of the drawings, the same parts are designated by the same reference numerals, and duplicate descriptions of the same parts will be omitted as a general rule. In this specification, for the sake of simplicity, symbols or signs referring to information, signals, physical quantities, functional units, circuits, elements, or components may be used, and the names of the information, signals, physical quantities, functional units, circuits, elements, or components corresponding to the symbols or signs may be omitted or abbreviated.

[0008] First, some terms used in describing the embodiments of the present disclosure will be explained. Ground refers to a reference conductor having a reference potential of 0 V (zero volts), or refers to the 0 V potential itself. The reference conductor may be formed using a conductor such as metal. The 0 V potential may also be referred to as ground potential. In the embodiments of the present disclosure, a voltage indicated without a specific reference represents a potential seen from ground. Unless otherwise specified, a connection between multiple parts that form a circuit, such as any circuit element, wiring, or node, may be understood to refer to an electrical connection.

[0009] Fig. 1 is an external perspective view of an illuminance sensor LS according to an embodiment of the present disclosure. The illuminance sensor LS is an electronic component (semiconductor device) including a semiconductor chip 1, a housing CS that houses the semiconductor chip 1, and a plurality of external terminals that are exposed to the outside of the illuminance sensor LS from the housing CS. The illuminance sensor LS is formed by enclosing the semiconductor chip 1 in the housing CS. Note that the number of external terminals of the illuminance sensor LS and the type of housing for the illuminance sensor LS shown in Fig. 1 are merely examples, and can be designed as desired.

[0010] In FIG. 1, IL represents light incident on the illuminance sensor LS (hereinafter referred to as incident light). For the sake of clarity, the following definitions are given for the mutually orthogonal X, Y, and Z axes. The incident light IL travels parallel to the Z axis from a light source (not shown) of the incident light IL and enters the illuminance sensor LS. The light source of the incident light IL may be, for example, the sun or any lighting device, and may be a reflector that reflects light from the sun or the lighting device. The direction in which the incident light IL travels is from the positive side to the negative side of the Z axis. The up-down direction is considered to be parallel to the Z axis. The direction toward the positive side of the Z axis as viewed from the negative side of the Z axis is upward, and the direction toward the negative side of the Z axis as viewed from the positive side of the Z axis is downward. Therefore, the incident light IL travels downward and enters the illuminance sensor LS. Note that the plane parallel to the X and Y axes is referred to as the XY plane.

[0011] The housing CS is made of transparent resin. Therefore, incident light IL passes through the housing CS and enters the semiconductor chip 1. Although not shown in FIG. 1, a metal die pad that fixes the semiconductor chip 1 within the housing CS is provided below the semiconductor chip 1. Because the die pad is opaque, no light is incident on the semiconductor chip 1 (and therefore on each photodiode, which will be described later) from below the semiconductor chip 1.

[0012] 2 shows a schematic configuration of the semiconductor chip 1. The semiconductor chip 1 includes a semiconductor substrate 100 on which a semiconductor integrated circuit is formed, and a stacked layer 200 provided on the semiconductor substrate 100 by film formation. The semiconductor substrate 100 has two surfaces facing each other, one of which is referred to as the main surface P1 (or front surface P1) and the other as the back surface P2. The main surface P1 and back surface P2 are parallel to the XY plane. The circuit elements that constitute the illuminance sensor LS are formed on the main surface P1 side of the semiconductor substrate 100. In the vertical structure of the semiconductor integrated circuit, the direction from the back surface P2 toward the main surface P1 is upward, and the opposite direction is downward. The semiconductor substrate 100 is a P-type semiconductor substrate.

[0013] A P-type semiconductor substrate is prepared and subjected to various processes to form a semiconductor integrated circuit on the P-type semiconductor substrate. Of the entire region of the semiconductor substrate 100, the region that remains a P-type semiconductor region before and after the various processes is referred to as a substrate region 101. The substrate region 101 is exposed on the back surface P2 side of the semiconductor substrate 100 and is connected to ground. In other words, the substrate region 101 is a P-type semiconductor region that is connected to ground and therefore has ground potential.

[0014] In the semiconductor substrate 100, a P-type semiconductor region 111 (P-type diffusion region) is formed above a substrate region 101, and an N-type semiconductor region 112 (N-type diffusion region) is formed at a position surrounding the P-type semiconductor region 111. The N-type semiconductor region 112 is provided between the P-type semiconductor region 111 and the substrate region 101. A combined region of the semiconductor regions 111 and 112 is referred to as a photodiode region 110. A photodiode 10 is formed in the photodiode region 110. The semiconductor region 111 functions as an anode of the photodiode 10, and the semiconductor region 112 functions as a cathode of the photodiode 10.

[0015] In the semiconductor substrate 100, a P-type semiconductor region 121 (P-type diffusion region) is formed above the substrate region 101, and an N-type semiconductor region 122 (N-type diffusion region) is formed at a position surrounding the P-type semiconductor region 121. The N-type semiconductor region 122 is provided between the P-type semiconductor region 121 and the substrate region 101. A combined region of the semiconductor regions 121 and 122 is referred to as a photodiode region 120. A photodiode 20 is formed in the photodiode region 120. The semiconductor region 121 functions as an anode of the photodiode 20, and the semiconductor region 122 functions as a cathode of the photodiode 20.

[0016] Hereinafter, photodiode may be abbreviated as PD. Therefore, photodiodes 10 and 20 may be written as PD10 and 20. Similarly, photodiode region may be abbreviated as PD region. Therefore, photodiode regions 110 and 120 may be written as PD regions 110 and 120. In the semiconductor substrate 100, the PD region 110 and the PD region 120 are formed at positions spaced apart from each other. In the example of FIG. 2, the formation position of the PD region 120 is shifted in the X-axis direction from the formation position of the PD region 110.

[0017] The semiconductor substrate 100 also has a circuit region 130 located above the substrate region 101. In the circuit region 130, all circuit elements of the semiconductor integrated circuit formed on the semiconductor substrate 100 except for PDs 11 and 12 are formed.

[0018] A laminated portion 200 is provided by a film formation process above a semiconductor substrate 100 on which a semiconductor integrated circuit is formed. Although not clear from FIG. 2, the laminated portion 200 is formed by stacking multiple thin films parallel to the XY plane along the Z-axis direction.

[0019] The stacked unit 200 includes a multilayer filter 210. The multilayer filter 210 is formed by alternately stacking silicon nitride films and silicon oxide films. The silicon nitride film is a thin film made of a compound of silicon and nitrogen, and the silicon oxide film is a thin film made of silicon dioxide. The multilayer filter 210 selectively transmits light components of a specific wavelength band of incident light IL. The light components of the specific wavelength band refer to light components having wavelengths within the specific wavelength band. Specifically, the multilayer filter 210 has a first transmittance for light having wavelengths within the specific wavelength band and a second transmittance for light having wavelengths outside the specific wavelength band, the first transmittance being higher than the second transmittance. For example, the light having a wavelength within the specific wavelength band is visible light, and the specific wavelength band may be a wavelength band of 400 nm (nanometers) or more and 700 nm or less.

[0020] The multilayer filter 210 is also provided between the light source of the incident light IL and the semiconductor substrate 100. Therefore, the incident light IL arriving downward from the light source of the incident light IL passes through the multilayer filter 210 before heading toward the semiconductor substrate 100. Although not clear from FIG. 2 , a light-shielding metal is provided in the stacked portion 200 between the multilayer filter 210 and the semiconductor substrate 100 to block the incident light IL from entering the PD region 120 and the circuit region 130. Therefore, of the PD regions 110 and 120 and the circuit region 130, light components in a specific wavelength band are incident only on the PD region 110. In reality, some light components of the incident light IL having wavelengths outside the specific wavelength band are also incident on the PD region 110.

[0021] FIG. 3 is a schematic top view of a semiconductor substrate 100. In the semiconductor substrate 100, the PD regions 110 and 120 and the circuit region 130 are disposed at different positions. In FIG. 3, for convenience of illustration, the circuit region 130 is represented by a hatched region filled with dots. In the example of FIG. 3, the PD regions 110 and 120 are disposed adjacent to each other in the X-axis direction. In a two-dimensional region obtained by projecting the semiconductor substrate 100 onto the XY plane, the circuit region 130 is disposed at a position surrounding the PD regions 110 and 120 on all sides and corresponds to the region (a square-shaped region) remaining when the second rectangular region is removed from the first rectangular region. The second rectangular region is a rectangular region located inside the outline of the first rectangular region, and the PD regions 110 and 120 are disposed within the second rectangular region.

[0022] The light-shielding metal is made up of multiple metal films stacked in the vertical direction. The multiple-layer metal film may be three or more layers, but here we focus on the upper and lower metal films included in the multiple-layer metal film. Each metal film is a thin metal body with a thickness in the Z-axis direction, and is opaque to the incident light IL. Both the upper and lower metal films are provided between the multilayer filter 210 and the semiconductor substrate 100. The upper metal film is provided above the lower metal film. In other words, the upper metal film is provided between the multilayer filter 210 and the lower metal film.

[0023] The upper metal film includes the metal film 220 shown in FIG. 4, which is disposed above the circuit region 130 in a position covering the entire circuit region 130. The lower metal film includes the metal film 230 shown in FIG. 5, which is also disposed above the circuit region 130 in a position covering the entire circuit region 130. For convenience of illustration, the metal film 220 is represented by a hatched area in FIG. 4, and the metal film 230 is represented by another hatched area in FIG. 5. To avoid cluttering the illustration, the location of the circuit region 130 is not hatched with dots in FIGS. 4 and 5. To ensure that the entire circuit region 130 is covered above the circuit region 130, each of the metal films 220 and 230 is slightly larger than the circuit region 130 in the XY plane. Neither the metal film 220 nor the metal film 230 exists above the locations of the PD regions 110 and 120. The metal films 220 and 230 block the incident light IL from entering the circuit region 130. Each of the metal films 220 and 230 has slits formed in various places to prevent breakage when subjected to stress (the slits are not shown in FIGS. 4 and 5). For this reason, it is difficult to achieve the required light blocking using only one of the metal films 220 and 230. Therefore, sufficient light blocking is achieved by using multiple layers of metal films including the metal films 220 and 230 (i.e., sufficient blocking of the incident light IL from entering the circuit region 130).

[0024] Note that the semiconductor chip 1 is provided with a separate structure (not shown) for blocking light incident from the side of the housing CS from entering the PD regions 110 and 120. As described above, light from below the housing CS is blocked by the metal die pad and does not reach the PD regions 110 and 120. In addition, as will be described later, incident light IL is also blocked from entering the PD region 120. Therefore, it is only necessary to consider incident light IL from above as the light that is the source of the current generated in the PD 10.

[0025] Fig. 6 shows a schematic vertical structure of the semiconductor chip 1, focusing particularly on PDs 10 and 20. Fig. 7 shows the configuration of the illuminance detection circuit 2 provided in the illuminance sensor LS. The illuminance detection circuit 2 is included in a semiconductor integrated circuit formed on the semiconductor chip 1. The illuminance detection circuit 2 detects the illuminance of light IL incident on the illuminance sensor LS, which is an optical sensor, and outputs an illuminance detection signal S as a signal indicating the detection result of the illuminance of the incident light IL. DET As shown in Fig. 8, a system having an illuminance sensor LS is provided with a host device HOST consisting of a microcomputer or the like. The illuminance sensor LS and the host device HOST are connected to each other in a manner that allows two-way communication. The illuminance detection circuit 2 generates and outputs the generated illuminance detection signal S DET The bidirectional communication between the illuminance sensor LS and the host device HOST can be performed, for example, by 2 The communication may be via an Inter-Integrated Circuit (C) or a Serial Peripheral Interface (SPI).

[0026] The illuminance detection circuit 2 includes a PD 10, an integrating amplifier circuit 11, a PD 20, an integrating amplifier circuit 21, and a detection signal generation circuit 30. The PD 10 and the integrating amplifier circuit 11 form a sense circuit SNS1. The PD 20 and the integrating amplifier circuit 21 form a sense circuit SNS2. The integrating amplifier circuit 11 includes an operational amplifier 11a and a capacitor 11b. The integrating amplifier circuit 21 includes an operational amplifier 21a and a capacitor 21b. The detection signal generation circuit 30 includes AD conversion circuits 31 and 32, a difference calculation circuit 33, a signal output circuit 34, and a control circuit 35.

[0027] The integrating amplifier circuit 11 (first signal generating circuit), the integrating amplifier circuit 21 (second signal generating circuit), and the detection signal generating circuit 30 are integrated and formed within the circuit region 130. The metal films 220 and 230 shown in Figures 4 and 5 are light-shielding metals (non-specific light-shielding metals) that block the incidence of incident light IL on the circuit region 130. The metal films 220 and 230 suppress the photoelectric effect that can occur when the incident light IL is incident on each circuit (11, 21, 30), and as a result, malfunction of those circuits or deterioration of the illuminance detection accuracy is suppressed.

[0028] 6, a metal film 220 belonging to the upper metal film and a metal film 230 belonging to the lower metal film are connected to a conductive terminal 51. Therefore, the metal films 220 and 230 have a potential at the conductive terminal 51. Although the two metal films 220 are shown separately in FIG. 6, they are actually an integrated metal film.

[0029] 6, a capacitance C4 is a parasitic capacitance formed between the metal film 220 and the multilayer filter 210. Between the metal film 220 and the multilayer filter 210, an insulator such as a silicon oxide film is interposed.

[0030] In FIG. 6, capacitance C1 is a parasitic capacitance formed between the PD region 110 and the multilayer filter 210. An insulator such as a silicon oxide film is interposed between the PD region 110 and the multilayer filter 210. Specifically, the parasitic capacitance C1 is formed between the semiconductor region 111 in the PD region 110 and the multilayer filter 210. Therefore, the parasitic capacitance C1 can be equivalently considered to be formed between the anode of the PD 10 and the multilayer filter 210 (see also FIG. 7). In FIG. 6, resistance R1 represents a portion of the resistance component of the multilayer filter 210. The resistance R1 has a value on the order of TΩ (teraohms). A series circuit of the parasitic capacitance C4, resistance R1, and parasitic capacitance C1 is interposed between the metal film 220 (and therefore the conductive end 51) and the semiconductor region 111 (the anode of the PD 10), as shown in FIG. 7.

[0031] 6, a specific metal film 235 (specific light-shielding metal) is provided between the multilayer filter 210 and the semiconductor substrate 100, in addition to the metal films 220 and 230. The specific metal film 235 belongs to the lower metal films. The specific metal film 235 is disposed above the semiconductor substrate 100 in a position that covers the PD region 120, and blocks incident light IL from entering the PD region 120 (and therefore PD 20). The specific metal film 235 is a thin metal film that extends along the X-axis and Y-axis directions and has a thickness in the Z-axis direction.

[0032] In a direction parallel to the XY plane (i.e., in a direction parallel to a plane perpendicular to the direction in which the multilayer filter 210 and the semiconductor substrate 100 are arranged), the size of the specific metal film 235 is equal to or larger than the size of the PD region 120, and preferably, the size of the specific metal film 235 is larger than the size of the PD region 120. Specifically, the size of the specific metal film 235 is equal to or larger than the size of the PD region 120 in the X-axis direction, and the size of the specific metal film 235 is equal to or larger than the size of the PD region 120 in the Y-axis direction. FIG. 9 shows a plan view of the specific metal film 235 and the PD region 120 observed from above. When the specific metal film 235 is observed from above, the entire PD region 120 is hidden below the specific metal film 235. In other words, when the outline of the PD region 120 is projected onto the specific metal film 235 along the Z-axis direction, the projected image of the outline of the PD region 120 fits within the outline of the specific metal film 235. Therefore, the specific metal film 235 blocks the incident light IL from entering the PD region 120 (and therefore the PD 20) with a high degree of certainty.

[0033] In FIG. 6, capacitance C2 is a parasitic capacitance formed between the multilayer filter 210 and the specific metal film 235. An insulator such as a silicon oxide film is interposed between the multilayer filter 210 and the specific metal film 235. Capacitance C3 is a parasitic capacitance formed between the specific metal film 235 and the PD region 120. An insulator such as a silicon oxide film is interposed between the specific metal film 235 and the PD region 120. More specifically, the parasitic capacitance C3 is formed between the specific metal film 235 and the semiconductor region 121 in the PD region 120. Therefore, the parasitic capacitance C3 can be considered equivalent to being formed between the specific metal film 235 and the anode of the PD 20 (see also FIG. 7). In FIG. 6, resistance R2 represents a portion of the resistance component of the multilayer filter 210. Resistance R2 has a value on the order of TΩ (teraohms). A series circuit of parasitic capacitance C4, resistance R2, parasitic capacitance C2, and parasitic capacitance C3 is interposed between the metal film 220 (and therefore the conductive end 51) and the semiconductor region 121 (the anode of the PD 20), as shown in FIG.

[0034] The insulator interposed between the multilayer filter 210 and the PD region 110, the insulator interposed between the multilayer filter 210 and the specific metal film 235, and the insulator interposed between the specific metal film 235 and the PD region 120 are made of the same material and are transparent to the incident light IL. The distance (shortest distance) between the multilayer filter 210 and the PD region 110 and the distance (shortest distance) between the multilayer filter 210 and the PD region 120 are equal to each other, and these distances are the same as the distance d between the multilayer filter 210 and the semiconductor substrate 100. A Therefore, the distance d between the multilayer filter 210 and the semiconductor substrate 100 A For the thickness Z of the specific metal film 235 235 If "d" is sufficiently small, the capacitance value of the parasitic capacitance C1 substantially matches the capacitance value of the combined capacitance of the parasitic capacitances C2 and C3. A >>Z 235 In this case, the capacitance value of the capacitor C1 substantially matches the capacitance value of the combined capacitance of the capacitors C2 and C3.

[0035] Specifically, for example, thickness Z 235 is the distance dA It is good that it is 1 / 10 or less of "1 / 100≦Z 235 / d A Thickness Z is within the range of ≦1 / 10”. 235 and distance d A However, the thickness Z 235 is the distance d A It may be smaller than 1 / 100 of the thickness Z. 235 is preferably set to 1 μm (micrometer) or less, and is preferably set as small as possible below 1 μm. The distance between the multilayer filter 210 and the specific metal film 235 is d A It is recommended to set it to 1 / 2 or less.

[0036] The illuminance detection circuit 2 is connected to ground and operates based on an internal power supply voltage with the ground potential as the reference. The internal power supply voltage is a positive DC voltage that is generated within the illuminance sensor LS based on a power supply voltage supplied to the illuminance sensor LS from a voltage source (not shown) provided external to the illuminance sensor LS. The power supply voltage supplied to the illuminance sensor LS from the voltage source may itself function as the internal power supply voltage. The conductive terminal 51 has ground potential or a potential that has a certain relationship with the ground potential. Therefore, the metal films 220 and 230 (non-specific light-shielding metal) connected to the conductive terminal 51 are not insulated from the semiconductor substrate 100 and are therefore not insulated from the illuminance detection circuit 2.

[0037] In contrast, the specific metal film 235 is in a floating state relative to the semiconductor substrate 100, and therefore is in a floating state relative to the illuminance detection circuit 2. In other words, the specific metal film 235 (specific light-shielding metal) is insulated from the semiconductor substrate 100 and the illuminance detection circuit 2. The specific metal film 235 is not connected to either the conductive terminal 51 or the ground, and has an indefinite potential when viewed from the ground.

[0038] The configuration and operation of the illuminance detection circuit 2 will be described with reference to FIG. 7. The cathode of PD10 is connected to the conductive terminal 52, and the anode of PD10 is connected to the node 53. The inverting input terminal of the operational amplifier 11a is connected to the node 53, and the non-inverting input terminal of the operational amplifier 11a is connected to the conductive terminal 51. One end of the capacitor 11b is connected to the inverting input terminal of the operational amplifier 11a, and the other end of the capacitor 11b is connected to the output terminal of the operational amplifier 11a. The signal at the output terminal of the operational amplifier 11a is referred to as the sense signal Sig1. The cathode of PD20 is connected to the conductive terminal 52, and the anode of PD20 is connected to the node 54. The inverting input terminal of the operational amplifier 21a is connected to the node 54, and the non-inverting input terminal of the operational amplifier 21a is connected to the conductive terminal 51. One end of the capacitor 21b is connected to the inverting input terminal of the operational amplifier 21a, and the other end of the capacitor 21b is connected to the output terminal of the operational amplifier 21a. The signal at the output terminal of the operational amplifier 21a is referred to as a sense signal Sig2.

[0039] A sense signal Sig1 is input to the AD conversion circuit 31. The sense signal Sig1 is an analog voltage signal. The AD conversion circuit 31 performs AD conversion processing to convert the sense signal Sig1 into a digital signal Sig3. The digital signal Sig3 has a signal value VAL_3 that is proportional to the voltage value of the sense signal Sig1. If the signal value of the sense signal Sig1 when the AD conversion processing is performed in the AD conversion circuit 31 is represented as "VAL_1", then "VAL_3 = k × Sig1". A sense signal Sig2 is input to the AD conversion circuit 32. The sense signal Sig2 is an analog voltage signal. The AD conversion circuit 32 performs AD conversion processing to convert the sense signal Sig2 into a digital signal Sig4. The digital signal Sig4 has a signal value VAL_4 that is directly proportional to the voltage value of the sense signal Sig2. If the signal value of the sense signal Sig2 when the AD conversion processing is performed in the AD conversion circuit 32 is represented as "VAL_2", then "VAL_4 = k × Sig2". k is a conversion coefficient set for the AD conversion circuits 31 and 32 .

[0040] Digital signals Sig3 and Sig4 are input to the differential calculation circuit 33. The differential calculation circuit 33 generates a differential signal Sig5 by executing a differential calculation process to find the absolute difference between the digital signals Sig3 and Sig4: "Sig5 = |Sig3 - Sig4|". In other words, the signal value of the differential signal Sig5 is the absolute value of the difference between the signal value (VAL_3) of the digital signal Sig3 and the signal value (VAL_4) of the digital signal Sig4.

[0041] The signal output circuit 34 outputs the illuminance detection signal S indicating the signal value of the difference signal Sig5. DET to the host device HOST (for example, the illuminance detection signal S DET (These are transmitted to the host device HOST in the form of serial signals.)

[0042] The control circuit 35 comprehensively controls the operation of the illuminance detection circuit 2. The control by the control circuit 35 includes setting of an integration period, which will be described later, control of the voltage supplied to the conductive terminals 51 and 52, control of the execution timing of AD conversion processing by the AD conversion circuits 31 and 32, control of the execution timing of difference calculation processing by the difference calculation circuit 33, and output of the illuminance detection signal S by the signal output circuit 34. DET This includes transmission control.

[0043] The illuminance sensor LS receives various commands from the host device HOST. The control circuit 35 sets the operation mode of the illuminance detection circuit 2 to a power-down mode or a normal mode in accordance with the mode setting command received from the host device HOST. Of the power-down mode and the normal mode, the illuminance detection circuit 2 is configured so that drive power (internal power supply voltage) is supplied to the integrating amplifier circuits 11 and 21, the AD conversion circuits 31 and 32, the difference calculation circuit 33, and the signal output circuit 34 only in the normal mode. In the power-down mode, the control circuit 35 fixes the voltages of the conductive terminals 51 and 52 to 0 V.

[0044] When the operation mode of the illuminance detection circuit 2 is the normal mode, the control circuit 35 sets an integration period. During the integration period, as shown in FIG. 10, the control circuit 35 applies a bias voltage V BIAS1and bias voltage V BIAS2 The bias voltage V BIAS1 and V BIAS2 is a positive DC voltage, and the bias voltage V BIAS2 The bias voltage V BIAS1 Therefore, during the integration period, a bias is applied to each of the PDs 10 and 20 to make the cathode side at a higher potential than the anode side. For example, a bias voltage V BIAS1 , V BIAS2 are 1.1 V and 1.4 V, respectively. At the start of the integration period, the voltage across capacitor 11b and the voltage across capacitor 21b are both 0 V.

[0045] During the integration period, the PD10 generates a photocurrent I10 corresponding to the amount of incident light. The photocurrent I10 is a current generated in the PD10 when incident light IL enters the PD10. The amount of incident light here refers to the amount of incident light IL on the illuminance sensor LS, or more precisely, the amount of light that enters the PD10 based on the incident light IL. In either case, during the integration period, a photocurrent I10 corresponding to the incident light IL is generated, and the magnitude of the photocurrent I10 increases as the amount of incident light IL increases. The photocurrent I10 flows from the cathode to the anode of the PD10 and toward the inverting input terminal of the operational amplifier 11a. Therefore, during the integration period, the sense signal Sig1 (the signal value of the sense signal Sig1) decreases over time due to the photocurrent I10 and the action of the integrating amplifier circuit 11.

[0046] On the other hand, since the incident light IL on the PD20 is blocked, no photocurrent corresponding to the incident light IL is generated in the PD20. However, when a bias is applied to the PD20, a leakage current called dark current is generated in the PD20. Dark current becomes more pronounced at high temperatures. Dark current also occurs in the PD10. The dark current of the PD10 is a current generated in the PD10 regardless of whether or not light is incident on the PD10, and the dark current of the PD20 is a current generated in the PD20 regardless of whether or not light is incident on the PD20. The dark current of the PD10, like the photocurrent I10, flows from the cathode to the anode of the PD10. The dark current of the PD20 flows from the cathode to the anode of the PD20.

[0047] The illuminance detection circuit 2 eliminates the influence of dark current by using the PDs 10 and 20. Fig. 11 shows the waveforms of the sense signals Sig1 and Sig2 during the integration period and before and after the integration period.

[0048] During the integration period, the sense signal Sig1 (signal value of the sense signal Sig1) decreases over time due to the photocurrent I10, the dark current of the PD 10, and the integration amplifier circuit 11. At the start of the integration period, the sense signal Sig1 is BIAS1 The sense signal Sig1 at the end of the integration period has a voltage value of V BIAS1 The integrating amplifier circuit 11 has a voltage value lower by a voltage ΔV1 than the photocurrent I10. The voltage ΔV1 is the total amount (integral amount) of the photocurrent I10 and the dark current of PD10 during the integration period, expressed as a voltage. In other words, the sense signal Sig1 at the end of the integration period is a first signal corresponding to the current (I10) generated by PD10 due to the incident light IL and the dark current of PD10, and the integrating amplifier circuit 11 functions as a first signal generating circuit for generating the first signal. The integrating amplifier circuit 11 converts the total amount (integral amount) of the photocurrent I10 and the dark current of PD10 during the integration period into a voltage, thereby generating the first signal (V BIAS1 -ΔV1).

[0049] During the integration period, the sense signal Sig2 (signal value of the sense signal Sig2) decreases over time due to the dark current of the PD 20 and the integration amplifier circuit 21. At the start of the integration period, the sense signal Sig2 is BIAS1 The sense signal Sig2 at the end of the integration period has a voltage value of V BIAS1 The voltage ΔV2 is a voltage value that is lower than the total amount (integral amount) of dark current of the PD 20 during the integration period. In other words, the sense signal Sig2 at the end of the integration period is a second signal corresponding to the dark current of the PD 20, and the integrating amplifier circuit 21 functions as a second signal generating circuit for generating the second signal. The integrating amplifier circuit 21 converts the total amount (integral amount) of dark current of the PD 20 during the integration period into a voltage to generate the second signal (V BIAS111, for convenience of illustration, the voltage ΔV2 is expressed as about 1 / 10 of the voltage ΔV1 (the same applies to FIG. 17 described later), but in reality, the voltage ΔV2 is often much smaller than the voltage ΔV1.

[0050] The PDs 10 and 20 have the same structure, and therefore the magnitude of the dark current in the PD 10 and the magnitude of the dark current in the PD 20 can be considered to be equal. BIAS1 -ΔV1) and the second signal (V BIAS1 -ΔV2) is calculated as the difference between the first signal (V BIAS1 The signal component of the dark current of PD10 can be removed from (-ΔV1), and as a result, the total amount (integral amount) of photocurrent I10 during the integration period can be accurately determined. The total amount of photocurrent I10 during the integration period is represented by the difference signal Sig5. Since the total amount of photocurrent I10 during the integration period is proportional to the illuminance of incident light IL, the illuminance detection signal S can be calculated from the difference signal Sig5. DET can be generated.

[0051] Here, a reference configuration different from the configuration of the illuminance sensor LS will be described. FIG. 12 shows the vertical structure of a semiconductor chip according to the reference configuration. FIG. 13 shows an illuminance detection circuit 2ref according to the reference configuration. In the reference configuration, the metal film 230 connected to the conductive terminal 51 is disposed not only above the circuit region 130 but also above the PD region 120, so that the metal film 230 blocks incident light IL from entering the PD region 120. As a result, in the reference configuration, the potential between the parasitic capacitances C2 and C3 is fixed at the potential of the conductive terminal 51, as shown in FIG.

[0052] Now, consider the case where noises NZ1 and NZ2 shown in FIG. 12 act on the illuminance sensor according to the reference configuration. The noises NZ1 and NZ2 are simultaneously generated by external disturbance noise (electrical noise) generated by communication or the like. Here, the noise NZ1 travels from the multilayer filter 210 toward the PD region 110 through the parasitic capacitance C1, while the noise NZ2 travels from the multilayer filter 210 toward the PD region 120 through the parasitic capacitance C2. The intensities of the noises NZ1 and NZ2 are assumed to be equal. In this case, in the reference configuration, the noise NZ1 enters the PD region 110, while the noise NZ2 does not enter the PD region 120 because the metal film 230 acts as an electromagnetic shield, and passes from the metal film 230 through the conductive end 51 to ground or the like. Therefore, in the reference configuration, the noise NZ1 acts on the integrating amplifier circuit 11, while the noise NZ2 does not act on the integrating amplifier circuit 21, as shown in FIG. 14. In other words, if noises NZ1 and NZ2 occur during the integration period in the reference configuration, noise NZ1 changes the charging voltage of capacitor 11b, while noise NZ2 does not change the charging voltage of capacitor 21b. As a result, the noise NZ1 component is mixed into differential signal Sig5 in the reference configuration.

[0053] To avoid this, in the illuminance sensor LS according to this embodiment, as described above (see FIG. 6 ), a specific metal film 235 is provided to shield the PD region 120 from the incident light IL, separate from the metal film 230 connected to the conductive terminal 51. The specific metal film 235 is set in a floating state relative to the semiconductor substrate 100 (and therefore in a floating state relative to the illuminance detection circuit 2). As a result, when noises NZ1 and NZ2 act on the illuminance sensor LS, as shown in FIG. 15 , the noises NZ1 and NZ2 have equal effects on the integrating amplifier circuits 11 and 21, and these effects are canceled out by differential calculation processing. Therefore, the effect of the noises (NZ1, NZ2) on the differential signal Sig5 is zero or sufficiently low. In other words, the configuration of FIG. 6 suppresses the effect of disturbance noise. The cancellation effect is maximized by making the parasitic capacitance C1 equal to the combined capacitance of the parasitic capacitances C2 and C3.

[0054] Below, several examples related to the ambient light sensor LS will be described. The matters described above in this embodiment apply to the following examples unless otherwise specified and unless contradicted (excluding matters related to the reference configuration). If there are any matters in each example that contradict the matters described above, the description in that example may take precedence. Furthermore, unless contradicted, matters described in any of the following examples can also be applied to any other example (that is, any two or more of the examples can be combined).

[0055] <<First Example>> A first embodiment will be described. BIAS1 -ΔV1) and the second signal (V BIAS1 In order to properly acquire the differential voltage (-ΔV2), as shown in FIG. 16, it is preferable to provide switches SW1 and SW2 in the sense circuit SNS1 and switches SW3 and SW4 in the sense circuit SNS2. The switches SW1 to SW4 are switches (bus switches) that can propagate analog signals. The switch SW1 is inserted in series between the anode (node ​​53) of the PD10 and the inverting input terminal of the operational amplifier 11a. Therefore, the anode of the PD10 and the inverting input terminal of the operational amplifier 11a are conductive when the switch SW1 is on, and are non-conductive when the switch SW1 is off. The switch SW2 is connected in parallel to the capacitor 11b. The switch SW3 is inserted in series between the anode (node ​​54) of the PD20 and the inverting input terminal of the operational amplifier 21a. Therefore, the anode of the PD 20 and the inverting input terminal of the operational amplifier 21a are connected electrically when the switch SW3 is on, and are not connected electrically when the switch SW3 is off. The switch SW4 is connected in parallel to the capacitor 21b. The states (on / off states) of the switches SW1 to SW4 are controlled by a control circuit 35. Each of the switches SW1 to SW4 can be configured as a switching element such as a field effect transistor.

[0056] 17, time t2 is the start time of the integration period, and time t3 is the end time of the integration period. In the normal mode, bias voltage VBIAS1 is supplied to the conductive terminal 52 and a bias voltage V BIAS2 In the normal mode, the control circuit 35 keeps all of the switches SW1 to SW4 on until just before time t2. Therefore, the voltage across the capacitor 11a and the voltage across the capacitor 11b are kept at 0V until just before time t2, and both the sense signals Sig1 and Sig2 are supplied with the bias voltage V BIAS1 has a voltage value of

[0057] At time t2, the control circuit 35 switches the switches SW2 and SW4 from the on state to the off state while keeping the switches SW1 and SW3 on. Thereafter, at time t3, the control circuit 35 switches the switches SW1 and SW3 from the on state to the off state while keeping the switches SW2 and SW4 off. Thereafter, the switches SW1 to SW4 remain in the off state for a period including time t4. Time t4 is a small time after time t3.

[0058] By controlling the states of the switches SW1 to SW4 as described above, the sense signal Sig1 at time t2 is BIAS1 The sense signal Sig1 at times t3 and t4 has a voltage value of V BIAS1 On the other hand, the sense signal Sig2 at time t2 has a voltage value lower than the bias voltage V BIAS1 The sense signal Sig2 at times t3 and t4 has a voltage value of V BIAS1 The voltage value of the sense signal Sig1 at time t4 is lower by ΔV2 than the voltage value of the sense signal Sig2 at time t4. The significance of the voltages ΔV1 and ΔV2 is as described above. The control circuit 35 controls the AD conversion circuit 31 to convert the sense signal Sig1 at time t4 into the digital signal Sig3, and controls the AD conversion circuit 32 to convert the sense signal Sig2 at time t4 into the digital signal Sig4. The length of the integration period may be fixed or may be variably set in response to a command from the host device HOST.

[0059] <<Second Example>> A second embodiment will now be described. A semiconductor substrate 100 may be provided with a plurality of PD regions 110 and a plurality of PD regions 120. FIG. 18 shows a configuration in which three PD regions 110, ie, PD regions 110a to 110c, and three PD regions 120, ie, PD regions 120a to 120c, are provided on the semiconductor substrate 100. The structure of each of the PD regions 110a to 110c is the same as the structure of the PD region 110 described above with reference to FIG. 2 and the like, and the structure of each of the PD regions 120a to 120c is the same as the structure of the PD region 120 described above with reference to FIG. 2 and the like. PD10 is formed by connecting three photodiodes formed by the PD regions 110a to 110c in parallel, and PD20 is formed by connecting three photodiodes formed by the PD regions 120a to 120c in parallel.

[0060] In the example of FIG. 18, PD regions 110a and 120a are arranged side by side in the X-axis direction, PD regions 120b and 110b are arranged side by side in the X-axis direction, and PD regions 110c and 120c are arranged side by side in the X-axis direction. Furthermore, in the example of FIG. 18, PD regions 110a, 120b, and 110c are arranged side by side in the Y-axis direction, while PD regions 120a, 110b, and 120c are arranged side by side in the Y-axis direction, with PD region 120b arranged between PD regions 110a and 110c, and PD region 110b arranged between PD regions 120a and 120c. This arrangement minimizes the effects of different placement positions between PDs 10 and 20. For ease of illustration, in FIG. 18, the circuit region 130 is represented by a hatched area filled with dots. In the two-dimensional region obtained by projecting the semiconductor substrate 100 onto the XY plane, the circuit region 130 is disposed in a position surrounding the PD regions 110a-110c and 120a-120c on all sides, and corresponds to the region (a square-shaped region) that remains when the fourth rectangular region is removed from the third rectangular region. The fourth rectangular region is a rectangular region located inside the outline of the third rectangular region, and the PD regions 110a-110c and 120a-120c are disposed within the fourth rectangular region.

[0061] 18 is employed, a first specific metal film disposed above the semiconductor substrate 100 in a position covering the PD region 120a, a second specific metal film disposed above the PD region 120b, and a third specific metal film disposed above the PD region 120c are provided between the multilayer filter 210 and the semiconductor substrate 100 in the stacked unit 200 (the first to third specific metal films are not shown). The first, second, and third specific metal films block incident light IL from entering the PD regions 120a, 120b, and 120c, respectively. The first, second, and third specific metal films correspond to the specific metal film 235 (see FIG. 6) for the PD regions 120a, 120b, and 120c. Therefore, the first, second, and third specific metal films are floating relative to the semiconductor substrate 100 and the illuminance detection circuit 2 (they are insulated from the semiconductor substrate 100 and the illuminance detection circuit 2).

[0062] <<Third Example>> A third embodiment will now be described. As shown in Fig. 19, a modification may be applied to the illuminance sensor LS in which the cathode of PD10 in sense circuit SNS1 is connected to node 53 and the cathode of PD20 in sense circuit SNS2 is connected to node 54. Node 53 is connected to the inverting input terminal of operational amplifier 11a (in this case, node 53 may be connected to the inverting input terminal of operational amplifier 11a via switch SW1). Node 54 is connected to the inverting input terminal of operational amplifier 21a (in this case, node 54 may be connected to the inverting input terminal of operational amplifier 21a via switch SW3).

[0063] When the modification according to the third embodiment is applied, the anodes of PDs 10 and 20 are connected to ground, and the photocurrent and dark current in PD 10 flow from node 53 to ground, while the dark current in PD 20 flows from node 54 to ground. Therefore, when the modification according to the third embodiment is applied, the change directions of the sense signals Sig1 and Sig2 during the integration period are opposite to those described above. That is, during the integration period, the sense signal Sig1 changes in response to the bias voltage V BIAS1 The sense signal Sig2 rises according to the photocurrent and dark current of the PD10, and the bias voltage VBIAS1 The sense signal generating circuit 30 operates in the same manner regardless of whether the sense signals Sig1 and Sig2 change downward or upward.

[0064] The illuminance detection circuit 2 may be provided with two separate pairs of integrating amplifier circuits 11 and 21 connected to PDs 10 and 20 in the manner shown in Fig. 7 and one pair of integrating amplifier circuits 11 and 21 connected to PDs 10 and 20 in the manner shown in Fig. 19. In this case, using the sense signals Sig1 and Sig2 of the former pair enables illuminance detection with peak sensitivity to the first wavelength, and using the sense signals Sig1 and Sig2 of the latter pair enables illuminance detection with peak sensitivity to the second wavelength. The first wavelength and the second wavelength differ from each other depending on the structures of the PD regions 110 and 120.

[0065] <<Additional Notes>> A supplementary note will be provided for the present disclosure, the specific configuration examples of which have been shown in the above-described embodiments.

[0066] An illuminance sensor (LS) according to one aspect of the present disclosure comprises an illuminance detection circuit (2) configured to detect the illuminance of incident light (IL) onto the illuminance sensor using a first photodiode (10) and a second photodiode (10), and a light-shielding metal (235) that blocks the incident light from entering the second photodiode. The illuminance detection circuit comprises a first sense circuit (SNS1) having the first photodiode and configured to generate a first signal (Sig1) corresponding to a photocurrent (I10) generated in the first photodiode when the incident light enters the first photodiode and a dark current of the first photodiode, and a second sense circuit (SNS2) having the second photodiode and configured to generate a second signal (Sig2) corresponding to the dark current of the second photodiode. The illuminance sensor (LS) detects the illuminance of the incident light based on the first signal and the second signal, and the light-shielding metal is insulated from the illuminance detection circuit (first configuration).

[0067] This makes it possible to suppress the difference in the influence of disturbance noise on the first and second photodiodes, thereby reducing the influence of disturbance noise on the detection of the illuminance of incident light based on the first and second signals.

[0068] In the illuminance sensor according to the first configuration, a filter (210) that selectively passes light components of a specific wavelength band of the incident light may be provided on the optical path of the incident light between a light source of the incident light and a semiconductor substrate (100) on which the illuminance detection circuit is formed, and the light-shielding metal may be disposed between the filter and a region (120) in the semiconductor substrate where the second photodiode is formed (second configuration).

[0069] In the illuminance sensor according to the second configuration, the distance (d A ) may be configured (third configuration) such that the distance between the filter and the region in the semiconductor substrate where the second photodiode is formed is equal to the distance therebetween.

[0070] This makes it possible to bring the difference between the parasitic capacitance between the formation region of the first photodiode and the filter and the parasitic capacitance between the formation region of the second photodiode and the filter closer to zero. By bringing this difference closer to zero, the difference in the influence of disturbance noise on the first and second photodiodes can be brought closer to zero.

[0071] In the illuminance sensor according to the third configuration, the thickness (Z 235 ) is the distance (d A ) or less (fourth configuration).

[0072] This makes it possible to bring the difference between the parasitic capacitance between the formation region of the first photodiode and the filter and the parasitic capacitance between the formation region of the second photodiode and the filter closer to zero. By bringing this difference closer to zero, the difference in the influence of disturbance noise on the first and second photodiodes can be brought closer to zero.

[0073] In the illuminance sensor according to any one of the second to fourth configurations, a configuration (fifth configuration) may be adopted in which the size of the light-shielding metal is equal to or larger than the size of the formation area of ​​the second photodiode in a direction parallel to a plane (XY plane) perpendicular to the direction in which the filter and the semiconductor substrate are arranged.

[0074] This makes it possible to effectively block incident light from entering the second photodiode.

[0075] In the illuminance sensor according to any of the second to fifth configurations, the first sense circuit comprises the first photodiode and a first signal generation circuit (11) configured to generate the first signal based on the photocurrent and a dark current of the first photodiode, the second sense circuit comprises the second photodiode and a second signal generation circuit (21) configured to generate the second signal based on the dark current of the second photodiode, and the illuminance detection circuit generates an illuminance detection signal (S ) indicating a detection result of the illuminance of the incident light based on the first signal and the second signal in addition to the first sense circuit and the second sense circuit. DET ), and the semiconductor substrate is provided with a formation region (110) of the first photodiode, a formation region (120) of the second photodiode, and another semiconductor region (130) in which the first signal generation circuit, the second signal generation circuit, and the detection signal generation circuit are formed, and the illuminance sensor is provided with, in addition to a specific shading metal (235) as the shading metal, non-specific shading metals (220, 230) that block the incident light from entering the other semiconductor regions, and the non-specific shading metals may be configured to be non-insulated from the illuminance detection circuit (sixth configuration).

[0076] In the illuminance sensor according to the sixth configuration, the first signal generation circuit may generate the first signal by converting the total amount of the photocurrent and the dark current of the first photodiode during an integration period into a voltage, the second signal generation circuit may generate the second signal by converting the total amount of the dark current of the second photodiode during the integration period into a voltage, and the detection signal generation circuit may generate the illuminance detection signal based on the difference between the first signal and the second signal (seventh configuration).

[0077] The embodiments of the present disclosure can be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The above-described embodiments are merely examples of the present disclosure, and the meanings of the terms of the present disclosure and each constituent element are not limited to those described in the above-described embodiments. The specific numerical values ​​shown in the above description are merely examples, and as a matter of course, they can be changed to various numerical values. [Explanation of symbols]

[0078] LS Light Sensor IL incident light CS chassis 1. Semiconductor chip P1 main surface P2 back side 10, 20 photodiodes 100 Semiconductor substrate 101 Board area 110, 120 Photodiode area 111, 112, 121, 122 Semiconductor area 210 Multilayer Filter 220, 230 Metal film 235 Specific metal film C1~C4 Parasitic capacitance R1 Resistor (resistance component) d A distance Z 235 Thickness HOST Host device 2. Illuminance detection circuit SNS1, SNS2 sense circuit 11, 21 Integrating amplifier circuit 11a, 21a operational amplifiers 11b, 21b capacitors 30 Detection signal generation circuit 31, 32 AD conversion circuit 33 Difference calculation circuit 34 Signal output circuit 35 Control circuit 51, 52 Conductive end 53, 54 nodes Sig1, Sig2 Sense signals Sig3, Sig4 digital signals Sig5 differential signal S DET Illuminance detection signal I10 Photocurrent V BIAS1 , V BIAS2 bias voltage NZ1, NZ2 noise SW1 to SW4 switches 110a to 110c, 120a to 120c Photodiode areas

Claims

1. an illuminance sensor comprising: an illuminance detection circuit configured to detect an illuminance of light incident on the illuminance sensor using a first photodiode and a second photodiode; and a light-shielding metal that blocks the incident light from reaching the second photodiode; the illuminance detection circuit includes a first sense circuit having the first photodiode and configured to generate a first signal corresponding to a photocurrent generated in the first photodiode when the incident light is incident on the first photodiode and a dark current of the first photodiode, and a second sense circuit having the second photodiode and configured to generate a second signal corresponding to the dark current of the second photodiode, and detects the illuminance of the incident light based on the first signal and the second signal; The light-shielding metal is insulated from the illuminance detection circuit. , illuminance sensor.

2. a filter that selectively passes light components of a specific wavelength band of the incident light is provided on the optical path of the incident light between a light source of the incident light and a semiconductor substrate on which the illuminance detection circuit is formed, The light-shielding metal is disposed between the filter and a region in the semiconductor substrate where the second photodiode is formed. The illuminance sensor according to claim 1 .

3. The distance between the first photodiode formation region and the filter in the semiconductor substrate is equal to the distance between the second photodiode formation region and the filter in the semiconductor substrate. The illuminance sensor according to claim 2 .

4. The thickness of the light-shielding metal in the direction in which the filter and the semiconductor substrate are arranged is 1 / 10 or less of the distance between the formation region of the first photodiode and the filter. The illuminance sensor according to claim 3 .

5. In a direction parallel to a plane perpendicular to the direction in which the filter and the semiconductor substrate are arranged, the size of the light-shielding metal is equal to or larger than the size of a region in which the second photodiode is formed.

5. The illuminance sensor according to claim 2.

6. the first sensing circuit comprises the first photodiode and a first signal generating circuit configured to generate the first signal based on the photocurrent and a dark current of the first photodiode; the second sensing circuit includes the second photodiode and a second signal generating circuit configured to generate the second signal based on a dark current of the second photodiode; the illuminance detection circuit includes, in addition to the first sense circuit and the second sense circuit, a detection signal generation circuit configured to generate an illuminance detection signal indicating a detection result of the illuminance of the incident light based on the first signal and the second signal; the semiconductor substrate is provided with a formation region of the first photodiode, a formation region of the second photodiode, and other semiconductor regions in which the first signal generation circuit, the second signal generation circuit, and the detection signal generation circuit are formed; In the illuminance sensor, in addition to the specific light-shielding metal as the light-shielding metal, a non-specific light-shielding metal that blocks the incident light from entering the other semiconductor regions is provided, The non-specific light-shielding metal is non-insulating with respect to the illuminance detection circuit. The illuminance sensor according to claim 2 .

7. the first signal generating circuit generates the first signal by converting a total amount of the photocurrent and a dark current of the first photodiode during an integration period into a voltage; the second signal generation circuit generates the second signal by converting a total amount of dark current of the second photodiode during the integration period into a voltage; The detection signal generating circuit generates the illuminance detection signal based on a difference between the first signal and the second signal. The illuminance sensor according to claim 6 .

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