Programmable gain amplifier with programmable resistance

Abstract

SOLUTION: A circuit includes an analog-to-digital converter (ADC), and also includes an analog front-end (AFE 310) having an AFE input and an AFE output, in which the AFE output is coupled to the input of the ADC. The AFE includes a programmable gain amplifier (PGA 115) having a first PGA input and a second PGA input. The PGA 115 includes a first operational amplifier (operational amplifier OP1) having first and second operational amplifier inputs. The AFE also includes a programmable resistance circuit (320) having a first programmable resistance circuit input and first and second programmable resistance circuit outputs. The first programmable resistance circuit input is coupled to the first and second PGA inputs. The programmable resistance circuit includes a resistor network having first and second balanced resistors. The first balanced resistor is coupled to the first and second operational amplifier inputs, and the second balanced resistor is coupled to the first and second operational amplifier inputs.SELECTED DRAWING: Figure 3

Description

[Background technology]

[0001] Analog-to-digital converters (ADCs) convert analog signals into digital representations of those analog signals. ADCs are used in a wide variety of applications. One of the characteristic parameters of an analog signal chain, such as one that includes an ADC, is the common mode rejection ratio (CMRR). CMRR is a measure of how well the signal chain suppresses common modes present at both input terminals of the signal chain. Some applications can benefit from a higher CMRR. Summary of the Invention

[0002] In one example, a circuit includes an analog-to-digital converter (ADC). The circuit also includes an analog front-end (AFE) having an AFE input and an AFE output. The AFE output is coupled to the input of the ADC. The AFE includes a programmable gain amplifier (PGA) having a first PGA input and a second PGA input. The PGA includes a first operational amplifier (opamp) having first and second opamp inputs. The AFE also includes a programmable resistance circuit having a first programmable resistance circuit input and first and second programmable resistance circuit outputs. The first programmable resistance circuit input is coupled to the first and second PGA inputs. The programmable resistance circuit includes a resistor network having first and second balanced resistors. The first balanced resistor is coupled to the first and second opamp inputs, and the second balanced resistor is coupled to the first and second opamp inputs. [Brief explanation of the drawings]

[0003] For a detailed description of various examples, reference will now be made to the accompanying drawings.

[0004] [Figure 1] 1 illustrates a circuit signal chain including an analog front end (AFE) having a programmable gain amplifier (PGA) coupled to an analog to digital converter (ADC).

[0005] [Figure 2] 2 illustrates the AFE of FIG. 1 with further details of the PGA.

[0006] [Figure 3] 1 illustrates an example AFE that includes a programmable resistor circuit used to compensate for resistor mismatch within the AFE.

[0007] [Figure 4] 1 illustrates an example implementation of a programmable resistance circuit that includes a resistor network having a pair of balanced resistors and also including a delta-sigma modulator (a hybrid R-2R network).

[0008] [Figure 5] An example of a programmable resistor circuit including a two-tap finite impulse response (FIR) filter for attenuating noise above the audio band is shown.

[0009] [Figure 6] 1 illustrates the use of two resistor networks with an AFE, where one resistor network is operated with an inverted input voltage compared to the other resistor network.

[0010] [Figure 7] 1 shows another example of an AFE that includes two resistor networks. DETAILED DESCRIPTION OF THE INVENTION

[0011] The signal chain described herein includes an analog front end (AFE) coupled to an ADC. The AFE receives an input analog signal. The AFE may include an amplifier, such as a programmable gain amplifier (PGA), to modify the magnitude of the input analog signal before it is provided to the ADC for conversion to a digital representation. The AFE described herein provides a relatively high CMRR.

[0012] 1 shows an example of a circuit 100 including an AFE 110 coupled to an ADC 150. The AFE 110 and ADC 150 in this example are formed on the same semiconductor die 105 and are therefore provided on the same chip. The output of the AFE 110 is coupled to the input of the ADC 150. The AFE 110 has inputs designated INP (Input Positive) and INM (Input Minus). The INP and INM inputs receive an analog input signal (e.g., a differential analog signal), which is processed by the AFE 110. The processed analog signal from the AFE 110 is converted to a digital representation (digital output 151) by the ADC 150.

[0013] In this example, the AFE 110 adjusts the magnitude of the input analog signal. The AFE 110 includes a programmable gain amplifier (PGA) 115 having a positive input 116, a negative input 117, a positive output (OUTP) 118, and a negative output (OUTM) 119. The OUTP 118 and OUTM 119 are coupled to corresponding inputs 153, 154 of the ADC 150. The AFE 110 also includes resistors R1P, R2P, R1M, and R2M. One terminal of R1P provides the INP input, and the other terminal of R1P is coupled to the positive input 116 of the PGA 115 and one terminal of R2P at node NP. The other terminal of R2P is coupled to a ground node 130 (or a supply voltage node). Similarly, one terminal of R1M provides the INM input, and the other terminal of R1M is coupled to the negative input 117 of PGA 115 and one terminal of R2M at node NM. The other terminal of R2M is coupled to ground node 131 (or another fixed voltage). Resistors R1P and R2P comprise a resistive voltage divider for attenuating the positive input signal INP before regulation (e.g., programmable attenuation) by PGA 115. The voltage on node NP is labeled ATTN_OUTP. Similarly, resistors R1M and R2M comprise a resistive voltage divider for attenuating the negative input signal INP before regulation by PGA 115. The voltage on node NM is labeled ATTN_OUTM. ADC 150 may include any suitable type of ADC. In one example, ADC 150 includes a third-order continuous-time delta-sigma ADC.

[0014] FIG. 2 shows the AFE 110 with additional example details for the PGA 115. The PGA 115 in this example includes operational amplifiers (opamps) OP1 and OP2 and resistors RINP, RINM, RCM1, RCM2, R3, R4, RFB1, and RFB2. OP1 has a positive input 201 (positive virtual ground, VGP), a negative input 202 (negative virtual ground, VGM), a positive output (OUTP) 118, and a negative output (OUTM) 119. OP2 has a negative input 203 and a positive input 204. RINP is coupled between R1P (the positive input 116 of the PGA 115) and the positive input 201 of OP1. RINM is coupled between R1M (the negative input 117 of the PGA 115) and the negative input 202 of OP2. RFB1 is coupled between the positive input 201 and OUTM 119, and RFB2 is coupled between the negative input 202 and OUTP 118. R4 is coupled between the positive input 201 of OP1 and the negative input 203 of OP2. R3 is coupled between the negative input 202 of OP1 and the negative input 203 of OP2. A common-mode voltage (VCM) is a reference voltage (e.g., generated by a bandgap reference) and is supplied to the positive input 204 of OP2. The VCM voltage is selected so that all nodes in the circuit remain within valid bias conditions throughout the input signal swing. The output of OP2 provides a signal labeled OP2_OUT and is coupled to RCM1 and RCM2. RCM1 is coupled to the positive input 201 of OP1, and RCM2 is coupled to the negative input 202 of OP1. PGA 115 has an input common mode suppression loop (CMSL) formed in part by RCM1, RCM12, OP2, R3, and R4 that ensures that the common mode of the virtual grounds VGP and VGM at the positive and negative inputs 201 and 202 of OP1 remains at the desired level of VCM.

[0015] The CMRR of the circuit 100 is determined, at least in part, by the CMRR of the AFE 110. The CMRR of the AFE 110 is determined by the degree of mismatch between the resistors on the positive side (i.e., R1P, R2P, RINP, and RCM1) and their corresponding resistors on the negative side (i.e., R1M, R2M, RINM, and RCM2). Due to their low cost, many semiconductor devices implement resistors as polysilicon resistors. However, polysilicon resistors are characterized by relatively poor matching. Therefore, achieving high CMRR using polysilicon to implement the resistors of the AFE 110 can be very difficult, if not impossible. Some applications may benefit from a CMRR of 80 dB, 90 dB, or even higher. For example, a CMRR of 90 dB may not be feasible using polysilicon for the resistors in the AFE architecture shown in FIG. 2.

[0016] FIG. 3 shows an example of an AFE 310 that achieves a higher CMRR (e.g., 90 dB) than the AFE 110 of FIGS. 1 and 2 while also using polysilicon resistors, but with a different architecture than that shown in FIG. 2. As with the architecture of the AFE 110 of FIG. 2, the AFE 310 in FIG. 3 includes OP1, OP2, and resistors RINP, RINM, RCM1, RCM2, R3, R4, RFB1, and RFB2 connected together in much the same manner as described above. The AFE 310 of FIG. 3 also includes a programmable resistance circuit 320 and resistors Rx1 and Rx2. Rx1 and Rx2 are connected in series between the positive and negative inputs 116 and 117 of the PGA, and thus between ATTN_OUTP and ATTN_OUTM. In some examples, the nominal resistance of Rx1 is equal to the nominal resistance of Rx2 (i.e., Rx1 = Rx2, ignoring resistor mismatch). A node 340 between Rx1 and Rx2 is coupled to the input terminal (VIN) of programmable resistance circuit 320. When Rx1 is equal to Rx2, the voltage at node 340 is halfway between ATTN_OUTM and ATTN_OUTP.

[0017] The output terminals of the programmable resistance circuit 320 include output 350 and output 351. Output 350 is coupled to the positive input 201 of OP1 at VGP, and output 351 is coupled to the negative input 202 of OP1 at VGM. The programmable resistance circuit 320 is trimmable to provide a programmed resistance coupled between the inputs 116, 117 of the PGA 115 and the inputs 201, 202 of OP1. The programmed resistance balances the AFE 310 against mismatches between the AFE's positive resistors (RINP, RINP, RCM1, and RFB1) and negative resistors (RINM, RINM, RCM2, and RFB2). All else being equal, the use of the programmable resistance circuit 320 results in a higher CMRR of the AFE 310 than would be possible for the AFE 110 of FIG. 2.

[0018] FIG. 4 shows an example implementation of a programmable resistance circuit 320. In this example, the programmable resistance circuit 320 includes a resistor network 410 coupled to a delta-sigma modulator 472. The programmable resistance circuit 320 also includes storage 490 (e.g., a memory device, a register, etc.). The resistor network 410 is a hybrid “R-2R” resistor network. A conventional R-2R network includes repeating cells (“legs”), each including a unit resistor (R) coupled to a 2R resistor, and also includes balancing resistors to help ensure the binary weighting of the various legs of the R-2R network. However, the resistor network 410 shown in FIG. 4 includes two balancing resistors (resistors 429 and 430) rather than just one as in a conventional R-2R network. Each balancing resistor 429, 430 may be implemented as a combination of one or more unit resistors (R). Each of balancing resistors 429 and 430 can also be referred to as a balancing resistor, recognizing that each balancing resistor 429, 430 can include multiple resistors. The additional balancing resistor 430 (in addition to balancing resistor 429) helps cover the residual error created by resistor network 410 using coarse CMRR trim code 470. The residual error created by resistor network 410 can be higher than the range of a single balancing resistor (due to mismatch in the resistors of resistor network 410). The two balancing resistors adequately address the residual error.

[0019] Resistor network 410 includes resistors 420-430 and 440-443. Each resistor includes one or more resistors having the nominal effective resistance shown. The resistors may include one or more unit resistances (R) combined together to form the resistances shown. Resistors 420, 422, 424, 426, 428-430, 440, 442, and 443 are each 2R resistors. Resistors 421, 423, and 425 are each R / 2 resistors (half a unit resistance). Resistor 441 is a 4R / 3 resistor.

[0020] A switch 450 selectively couples each 2R resistor 420, 422, 424, 426, and 428 to one of the nodes VGP, VCM, or VGM. A coarse CMRR trim code 470 controls the switch 450 to selectively allow current to flow to the VGP node, the VCM node, or the VGM node through the corresponding 2R resistor 420, 422, 424, 426, and 428. The coarse CMRR trim code 470 is stored in storage 490. In one example, the coarse CMRR trim code 470 is implemented in sign-magnitude form, but may be implemented in other forms such as two's complement. In the example of FIG. 4, five resistors (resistors 420, 422, 424, 426, and 428) are controlled by the coarse CMRR trim code 470. In the sign-magnitude form, one bit of the trim code is used to represent the direction of the correction, and the other bit is used to represent the magnitude. To control the five resistors, the coarse trim code 470 contains six bits. The most significant bit controls the direction of application, meaning whether the resistors (420-428) should be connected to VGP or VGM. The remaining five bits of the trim code control whether each respective resistor is connected to VCM (when the bit is 0) or VGP / VGM (when the bit is 1 and depending on the direction of the sign bit (MSB)). For example, if the coarse CMRR trim code 470 is "000000" or "100000," all resistors are connected to VCM. If the coarse trim code 470 is "011111," resistors 420-428 are connected to VGP. If the coarse trim code 470 is "111111," the resistors are connected to VGM.

[0021] The delta-sigma modulator 472 receives the fine CMRR trim code 471 (also stored in the storage 490). The delta-sigma modulator 472 may include a second-order delta-sigma modulator. The delta-sigma modulator generates an output bit sequence Q (and its complement QZ) to control the on / off states of switches SW1, SW2, SW3, and SW4. The use of a delta-sigma modulator helps ensure that relatively little noise in the audible frequency range is injected into the AFE 310. SW1 is coupled between resistor 430 and VGP. SW2 is coupled between resistor 430 and VGM. SW3 is coupled between resistor 429 and VGP. SW1 is coupled between resistor 429 and VGM. The Q signal controls SW1 and SW3, and QZ controls SW2 and SW4. In this manner, SW1 and SW2 are not both on at the same time, and similarly, SW3 and SW4 are not both on at the same time. The Q signal turns on SW1 and SW3 simultaneously (QZ turns off SW2 and SW4). The QZ signal turns on SW2 and SW4 simultaneously (Q turns off SW1 and SW3). While SW1 and SW3 are on (and SW2 and SW4 are off), current (i) flows to VGP through balancing resistors 429 and 430, respectively. And, while SW2 and SW4 are on (and SW1 and SW3 are off), current i flows to VGM through balancing resistors 429, 430, respectively.

[0022] When switches SW1-SW4 are operated with an average duty cycle of 50%, virtually zero differential current is applied to the input of OP1. However, by controlling the duty cycle to a value different from 50%, a sub-LSB (least significant bit) correction current is applied to the input of OP1. In this manner, by using dual balanced resistors 429, 430 and switching them between the VGP node and the VGM virtual ground node, the balanced portion of the resistor network helps to increase the resolution of resistor network 410, thereby allowing the resulting AFE 310 to have a higher CMRR.

[0023] Because two balancing resistors 429 and 430 are used (to increase the compensation range of the balancing stage of resistor network 410 to compensate for the full range of residual errors, as described above), current i flows through each of resistors 429 and 430, resulting in twice the current flowing through the combined balancing resistor of resistor network 410 than would flow through a conventional R-2R network based on a single balancing resistor. However, these additional balancing resistors degrade linearity performance compared to a conventional R-2R resistor network. To increase the compensation range of the balancing stage of resistor network 410 while preserving the linearity of the resistor network, an additional compensation resistor 440 (compared to a conventional R-2R network) is coupled in parallel across unit resistor 427. Resistors 441-443 are added (relative to a conventional R-2R network) to ensure that the binary weighting ratio of the resistor network is maintained. Figure 4 shows the relative current magnitudes through the various branches of the resistor network. Resistor 4R / 3 allows a current of 3i to flow through it, thereby maintaining a current of an integer power of 2 (e.g., 8i) through resistor 425. Resistor 442 is a 2R resistor that allows a 4i current to flow through it such that the current through resistor 423 is the next higher integer power of 2 compared to the current through resistor 425. That is, the current through resistor 423 is 16i. Resistor 443 is included for much the same reasons as resistor 442. Resistors 421, 423, and 425 comprise R / 2 resistors instead of unit resistor R, as in the R-2R ladder.

[0024] The delta-sigma modulator 472 is used to generate signals to control the switches SW1-SW4 in the example of FIG. 4. While a pulse-width modulated (PWM) clock can be used to control the switches SW1-SW4, using a clock can inject noise into the AFE 310 within the audible frequency range. However, the delta-sigma modulator 472 injects noise above the audible frequency range, while relatively little noise is injected into the audible frequency range. In one example, the delta-sigma modulator 472 includes a quantizer (noise injector) 489 coupled with integrators 481 and 482 (depending on the order of the modulator) to form a loop. The integrators 481 / 482 form the first stage of the loop, while the quantizer 489 forms the final stage. Because the integrators 481 / 482 have substantial gain at low frequencies, the noise injected by the quantizer 489 is filtered out at frequencies where the integrator gain is high (at low frequencies). At higher frequencies (where integrators 481 / 482 do not have high gain), the noise of quantizer 489 is not removed. In this way, the delta-sigma modulator adds low noise at low frequencies. Because the audio band is a relatively low frequency (e.g., 20 Hz to 20 KHz), delta-sigma modulator 472 advantageously adds low-level noise in the audio band. However, such higher-frequency noise (above the audio band) can still intermodulate with other high-frequency noise in the system, thereby introducing some additional noise into the audio band.

[0025] FIG. 5 is similar to FIG. 4 but shows an example of a resistor network including a finite impulse response (FIR) filter. The FIR filter includes a delay 520, dual switch balancing resistors 429 and 430, and corresponding switches SW1-SW4. Delay 520 delays the switch control signals Q and QZ for SW3 and SW4 relative to SW1 and SW2. The FIR filter in this example includes a two-tap FIR filter. The two-tap FIR filter is a notch filter, which advantageously attenuates noise at frequencies within the notch. The notch occurs at frequencies above the audio band.

[0026] To mitigate charge injection due to the switching of the two balancing resistors 429 and 430, in the example of FIG. 6 , the programmable resistance circuit is implemented as a pair of resistor networks 410P (for the P-side of the AFE 310) and 410M (for the M-side of the AFE 310). The VGP outputs of resistor networks 410P and 410M are tied together as shown, and the VGM outputs are also tied together. This circuit architecture ensures that the number of elements switching between VGP and VGM is the same regardless of the sequence. Thus, symmetry between VGP and VGM is maintained. However, to operate the M-side resistor network 410M, the input V to resistor network 410M should be the negative version of the common-mode input voltage to V of resistor network 410P. In one implementation, an inverting amplifier 610 can be included to invert the input voltage at node 340 to V of resistor network 410M.

[0027] FIG. 7 shows another example implementation of an AFE 710 similar to that described above. Two resistor networks 410P and 410M are shown, as is a delta-sigma modulator 472 (which may include a two-tap FIR filter, as described above). Rather than including an inverting amplifier (as in FIG. 6) to generate the input voltage (VIN) for resistor network 410M, the example AFE 710 of FIG. 7 includes a normalizer 718. The normalizer 718 has an input (IN) 719 and an output (OUT) 720. The normalizer input 719 is coupled to the output of OP2. The normalizer output 720 is coupled to the VIN of resistor network 410M. The normalizer 718 normalizes the output voltage from OP2 (OP2_OUT) to an appropriate level relative to the voltage on node 340 between Rx1 and Rx2. In one example, the normalizer 718 includes a resistive voltage divider. The signal on the output of OP2 (OP2_OUT) may be different from the voltage at node 340 between resistors Rx1 and Rx2. Normalizer 718 receives voltage OP2_OUT and outputs another voltage that is equal to or approximately equal to the voltage at node 340.

[0028] The term "couple" is used throughout this specification. This term may encompass a connection, communication, or signal path that enables a functional relationship consistent with the description of this disclosure. For example, in a first example, device A is coupled to device B when device A generates a signal to control device B to perform a certain action, or in a second example, device A is coupled to device B via an intervening component C such that device A controls device B via a control signal generated by device A, where intervening component C does not substantially change the functional association between device A and device B.

[0029] Variations are possible in the described embodiments.

Claims

1. A circuit comprising: an analog-to-digital converter (ADC) having an ADC input; an analog front end (AFE) having an AFE input and an AFE output, the AFE output coupled to the ADC input, the AFE including a programmable gain amplifier (PGA) having a first PGA input and a second PGA input, the PGA including a first operational amplifier (opamp) having a first opamp input and a second opamp input, the AFE further including a programmable resistor circuit; Including, the programmable resistance circuit having a first programmable resistance circuit input, a first programmable resistance circuit output, and a second programmable resistance circuit output, the first programmable resistance circuit input coupled to the first and second PGA inputs; the programmable resistance circuit includes a resistor network having first and second balancing resistors, the first balancing resistor coupled to the first and second operational amplifier inputs, and the second balancing resistor coupled to the first and second operational amplifier inputs.

2. 2. The circuit of claim 1, The circuit further includes a delta-sigma modulator coupled to the first and second balancing resistors.

3. 3. The circuit of claim 2, The circuit further includes a filter coupled to an output of the delta-sigma modulator.

4. 3. The circuit of claim 2, The circuit further includes a delay coupled between the delta-sigma modulator and one of the first and second balancing resistors.

5. 3. The circuit of claim 2, the programmable resistance circuit a first switch having a control input coupled between the first balancing resistor and the first operational amplifier input; a second switch having a control input coupled between the first balancing resistor and the second operational amplifier input; a third switch having a control input coupled between the second balancing resistor and the first operational amplifier input; a fourth switch having a control input coupled between the second balancing resistor and the second operational amplifier input; Including, The circuit wherein the delta-sigma modulator includes respective control outputs coupled to the control inputs of the first, second, third, and fourth switches.

6. 2. The circuit of claim 1, the programmable resistance circuit is a first programmable resistance circuit; a first programmable resistor circuit coupled to the first and second operational amplifier inputs, and a second programmable resistor circuit coupled to the first and second operational amplifier inputs;

7. 7. The circuit of claim 6, The circuit, wherein the AFE includes a second op-amp having a second op-amp output, and the second programmable resistance circuit includes a second programmable resistance input coupled to the second op-amp output.

8. 7. The circuit of claim 6, The circuit further includes a voltage level shifter circuit coupled between the second operational amplifier output and the second programmable resistor input.

9. A circuit comprising: a first operational amplifier (op amp) having a first op amp input and a second op amp input; a first resistor coupled to the first operational amplifier input, the first resistor providing a positive input; a second resistor coupled to the second op-amp input, the second resistor providing a negative input; and a programmable resistance circuit having a programmable resistance input, a first programmable resistance output, and a second programmable resistance output, the programmable resistance input coupled to the positive input and the negative input, the first programmable resistance output coupled to the first operational amplifier input, and the second programmable resistance output coupled to the second operational amplifier input; Including, the programmable resistance circuit includes a resistor network having first and second balancing resistors, the first balancing resistor coupled to the first and second operational amplifier inputs, and the second balancing resistor coupled to the first and second operational amplifier inputs.

10. 10. The circuit of claim 9, The circuit, wherein the first operational amplifier includes an output, and the circuit further includes an analog-to-digital converter (ADC) coupled to the output of the first operational amplifier.

11. 10. The circuit of claim 9, The circuit further includes a delta-sigma modulator coupled to the first and second balancing resistors.

12. 12. The circuit of claim 11, The circuit further includes a filter coupled to an output of the delta-sigma modulator.

13. 12. The circuit of claim 11, The circuit further includes a delay coupled between the delta-sigma modulator and one of the first and second balancing resistors.

14. 12. The circuit of claim 11, The circuit further includes a storage configured to store a trim code provided to the delta-sigma modulator.

15. 10. The circuit of claim 9, the programmable resistance circuit a first switch having a control input coupled between the first balancing resistor and the first operational amplifier input; a second switch having a control input coupled between the first balancing resistor and the second operational amplifier input; a third switch having a control input coupled between the second balancing resistor and the first operational amplifier input; a fourth switch having a control input coupled between the second balancing resistor and the second operational amplifier input; The circuit includes:

16. 10. The circuit of claim 9, the programmable resistance circuit is a first programmable resistance circuit; the circuit includes a second programmable resistance circuit, the second programmable resistance circuit including a resistor network having first and second balanced resistances, the first balanced resistance of the second programmable resistance circuit coupled to the first and second operational amplifier inputs, and the second balanced resistance of the second programmable resistance circuit coupled to the first and second operational amplifier inputs.

17. A circuit comprising: a first operational amplifier (op-amp) having a first op-amp input, a second op-amp input, and a first op-amp output; a second operational amplifier having a first operational amplifier input, a second operational amplifier input, and an operational amplifier output, the first operational amplifier input of the second operational amplifier being coupled to the first operational amplifier output of the first operational amplifier; a first resistor coupled to the first op-amp input of the first operational amplifier, the first resistor providing a positive input; a second resistor coupled to the second op-amp input of the first op-amp, the second resistor providing a negative input; a first programmable resistance circuit having a programmable resistance input, a first programmable resistance output, and a second programmable resistance output, wherein the programmable resistance input of the first programmable resistance circuit is coupled to the positive and negative inputs, the first programmable resistance output of the first programmable resistance circuit is coupled to the first opamp input of the first operational amplifier, and the first programmable resistance output of the first programmable resistance circuit is coupled to the second opamp input of the first operational amplifier; 1. A second programmable resistance circuit having a programmable resistance input, a first programmable resistance output, and a second programmable resistance output, wherein the programmable resistance input of the second programmable resistance circuit is coupled to the opamp output of the second operational amplifier, the first programmable resistance output of the second programmable resistance circuit is coupled to the first opamp input of the first operational amplifier, and the second programmable resistance output of the second programmable resistance circuit is coupled to the second opamp input of the first operational amplifier.

18. 18. The circuit of claim 17, a normalizer circuit coupled between the first operational amplifier output of the second operational amplifier and the programmable resistance input of the second programmable resistance circuit; The circuit, wherein the normalizer circuit is configured to adjust the voltage on the first op-amp output of the second op-amp to be supplied to the programmable resistance input of the second programmable resistance circuit.

19. 18. The circuit of claim 17, the first programmable resistance circuit includes a resistor network, and the second programmable resistance circuit includes a resistor network; The circuit further includes a delta-sigma modulator coupled to the first and second programmable resistance circuits.

20. 20. The circuit of claim 19, The circuit further includes a finite impulse response (FIR) filter coupled to the delta-sigma modulator.

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