Display device

Abstract

To provide a drive circuit that has a thin-film transistor whose threshold voltage is hard to control and which is normally on, minimizes erroneous activation in the circuit, and guarantees more highly reliable activation.SOLUTION: A display device includes a static shift register circuit that includes an inverter circuit having a first transistor and second transistor and a switch having a third transistor. Each of the first to third transistors has a semiconductor layer formed with an oxide semiconductor and is a depletion-type transistor. An amplitude voltage of a clock signal which drives the third transistor is larger than a supply voltage for use in driving the inverter circuit.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a driver circuit (also called a shift register circuit). The present invention relates to a display device having a driving circuit formed on a substrate. Regarding child devices. [Background technology]

[0002] With the spread of large display devices such as LCD TVs, there is a demand for higher value-added products. In particular, the channel region is made of amorphous semiconductor, especially oxide. Using thin film transistors (TFTs) made of semiconductors, the display is mounted on the same substrate as the pixel section. The technology for configuring driving circuits such as scan line driving circuits is being actively developed.

[0003] The configuration of the drive circuit is, for example, a static type described in Patent Document 1 (see Figure 2 etc.) There is a shift register circuit. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 64-89810 Summary of the Invention [Problem to be solved by the invention]

[0005] In a static shift register circuit, thin film transistors function as switches, and an inverter circuit (also called an inverting circuit). The use of an oxide semiconductor in the semiconductor layer of a transistor constituting an inverter circuit The advantage of using it is that it has excellent electrical properties such as high field effect mobility. On the other hand, oxide semiconductors have vacant spaces where oxygen has been removed, even without the addition of extrinsic impurities. Hole defects cause fluctuations in threshold voltage, and thin-film transistors using oxide semiconductors as semiconductor layers The transistor may also be of the depression type (also called normally-on).

[0006] In view of this, one embodiment of the present invention is to provide a channel formed of an oxide semiconductor, thereby preventing a normal - When an on-state thin film transistor is used in a unipolar drive circuit, malfunctions within the circuit are reduced. It is an object of the present invention to provide a driver circuit that can achieve this. [Means for solving the problem]

[0007] One aspect of the present invention is an inverter circuit having a first transistor and a second transistor. a static shift register circuit including a switch having a third transistor; the first to third transistors each include an oxide semiconductor. a depletion-type transistor having a semiconductor layer including the third transistor; The amplitude voltage of the clock signal that drives the inverter is It is a drive circuit with a larger voltage.

[0008] One aspect of the present invention is an inverter circuit having a first transistor and a second transistor. and a switch having a third transistor. and a demultiplexer circuit is provided at the output terminal of the shift register circuit, and the first transistor the first to third transistors each include a semiconductor layer containing an oxide semiconductor, and a depletion-mode transistor, and a clock that drives the first transistor; The amplitude voltage of the signal is greater than the power supply voltage for driving the inverter circuit, The output terminal of the multiplexer circuit is connected to a fourth transistor for fixing the potential of the output terminal. The starter is a drive circuit provided respectively.

[0009] In one aspect of the present invention, the clock signal comprises a first clock signal and a second clock signal. the second clock signal is an inverted signal of the first clock signal. It may also be a drive circuit.

[0010] In one embodiment of the present invention, the L / W ratio of the first transistor is The driving circuit may have a larger L / W ratio than the capacitor.

[0011] In one embodiment of the present invention, the thickness of the semiconductor layer of the first transistor is The driving circuit may have a thickness larger than that of the semiconductor layer of the transistor.

[0012] In one embodiment of the present invention, the L of the fifth transistor constituting the demultiplexer circuit The L / W ratio of the driving circuit may be smaller than the L / W ratio of the fourth transistor.

[0013] In one embodiment of the present invention, the fourth transistor has a gate to which a high power supply potential is supplied. the first terminal is electrically connected to a wiring to which a low power supply potential is supplied; The second terminal may be a driver circuit electrically connected to the output terminal of the demultiplexer circuit. good.

[0014] In one embodiment of the present invention, the first to fourth transistors are n-channel transistors. The driving circuit may be a transistor. [Effects of the Invention]

[0015] According to one embodiment of the present invention, the channel is formed of an oxide semiconductor, and thus the When a turned-on thin film transistor is used in a unipolar driver circuit, malfunctions within the circuit can be reduced. It is possible to provide a driving circuit that can [Brief explanation of the drawings]

[0016] [Figure 1] FIG. 2 is a diagram showing an example of a driver circuit. [Figure 2] FIG. 2 is a diagram showing an example of an inverter circuit, a switch, and waveforms of each signal. [Figure 3] FIG. 2 is a diagram showing an example of a top view of an inverter circuit. [Figure 4] FIG. 2 is a diagram showing an example of a driver circuit. [Figure 5] FIG. 2 is a diagram showing an example of a driver circuit. [Figure 6] FIG. 2 is a diagram showing an example of a timing chart of a driver circuit. [Figure 7] FIG. 2 is a diagram showing an example of a top view of an inverter circuit. [Figure 8] FIG. 1 is a diagram showing an example of a cross-sectional view of an inverter circuit. [Figure 9] FIG. 1 illustrates an example of a display device. [Figure 10] 1A and 1B are diagrams illustrating examples of electronic devices. [Figure 11] FIG. 2 is a diagram showing an example of a driver circuit. [Figure 12] FIG. 2 is a diagram showing an example of a timing chart of a driver circuit. DETAILED DESCRIPTION OF THE INVENTION

[0017] Hereinafter, embodiments of the present invention will be described with reference to the drawings. and the present invention may be practiced in various different ways without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various modifications can be made to the modes and details of the present invention. However, the present invention should not be construed as being limited to the description of the present embodiment. In the structure of the invention, reference numerals indicating the same objects are common among different drawings.

[0018] The size, thickness of layers, and regions of each component shown in the drawings of each embodiment are not clearly indicated. The figures may be exaggerated for clarity. It will not be done.

[0019] In this specification, the terms first, second, third, through Nth (N is a natural number of 2 or more) are used. is added to avoid confusion of components and does not limit the number The following is added.

[0020] (Embodiment 1) In this embodiment, first, a static shift register having a multi-stage pulse output circuit is used. The structure of a driver circuit, which is a transistor circuit, will be described with reference to the drawings. The driver circuit includes a thin film transistor that functions as a switch and an inverter circuit (inverter circuit). It is composed of several roads (also called paths).

[0021] The driver circuit 100 shown in this embodiment includes a circuit for supplying a first clock signal (CLK1). A line 101, a wiring 102 for supplying a second clock signal (CLK2), and a A pulse output circuit 103 receives a start pulse (SP, also referred to as a previous signal or an input signal). The driver circuit of this embodiment has a wiring 104 for supplying a current (hereinafter referred to as a "voltage") to the driver circuit. The following description will be given assuming that pulse signals for the out1 to outN columns are output. Alternatively, a scanning direction switching signal or the like may be input to switch the scanning direction. In this embodiment, the clock signals are a first clock signal (CLK1) and a second clock signal (CLK2). This example shows a clock signal driven by a two-phase clock signal (CLK1). The driving circuit may be driven by inputting a clock signal.

[0022] If the driving circuit shown in FIG. 1A is a gate line side driving circuit, for example, a buffer circuit or the like is The driver circuit shown in FIG. 1(A) is provided at each output terminal of the signal output circuit. In the case of a line side driving circuit, for example, a sampling switch for sampling a video signal is used. A latch circuit, a latch circuit, etc. are provided at each output terminal of the pulse output circuit.

[0023] The semiconductor layer of each transistor constituting the driver circuit 100 is preferably made of an oxide semiconductor. By using an oxide semiconductor for a semiconductor layer of a transistor, It is possible to increase the field effect mobility compared to silicon-based semiconductor materials such as ruthenium silicon. Examples of oxide semiconductors include zinc oxide (ZnO) and tin oxide (SnO2). Also, In, Ga, etc. can be added to ZnO.

[0024] In addition, InMO3(ZnO) is used as an oxide semiconductor. x Using a thin film expressed as (x>0) M can be gallium (Ga), iron (Fe), nickel (Ni), or manganese. It represents one or more metal elements selected from (Mn) and cobalt (Co). Examples: For example, M can be Ga, but there are also cases where M is other than Ga, such as Ga and Ni or Ga and Fe. The above metal elements may be contained. In addition to the metal elements, Fe, Ni and other transition metal elements may be present as impurity elements, or the transition metals For example, the oxide semiconductor layer contains In-Ga-Zn- An O-based non-single crystal film can be used.

[0025] Oxide semiconductor (InMO3(ZnO) x (x>0) film) as In-Ga-Zn-O based non- Instead of a single crystal film, InMO3(ZnO) where M is another metal element x (x>0) membrane In addition to the above, oxide semiconductors include In-Sn-Zn-O, In- Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Z nO series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-O series, Sn -O-based and Zn-O-based oxide semiconductors can be used.

[0026] A thin film transistor has at least a gate terminal, a drain terminal, and a source terminal. Both are elements with three terminals, and have a channel region between the drain region and the source region. and current can flow through the drain region, channel region, and source region. In this specification, the terminal connected to the wiring side for supplying the high power supply potential Vdd is called a driver. The drain terminal and the terminal connected to the side to which the low power supply potential Vss is supplied are referred to as the source terminal. In addition, the source terminal and the drain terminal are sometimes referred to as the first terminal and the second terminal. There is a match.

[0027] The structure of the thin film transistor can take various forms and is not limited to a specific structure. For example, a multi-gate structure having two or more gate electrodes can be applied.

[0028] Furthermore, a structure in which gate electrodes are arranged above and below the channel region can be applied. In addition, by arranging gate electrodes above and below the channel region, it is possible to It is also possible to configure the transistors in a parallel connection.

[0029] When it is explicitly stated that A and B are connected, it means that A and B are electrically connected. A and B are connected functionally, A and B are directly connected, Here, A and B are objects (e.g., devices, elements, circuits) Therefore, the predetermined connection relationship For example, the present invention is not limited to the connection relationships shown in the drawings or text, but may be applied to the connections shown in the drawings or text. This also includes things other than relationships.

[0030] Next, the configuration of the pulse output circuit 103 is shown in FIG. As an example, the first switch 11 connected to the terminal to which the start pulse SP is input is 1 and a first inverter 111 that inverts and outputs a signal input via the first switch 111. a second inverter circuit 112 that inverts the signal inverted by the first inverter circuit 112 and outputs the inverted signal; The first inverter circuit 113 and the second inverter circuit 113 are input. A second switch 114 connected to the terminal and a signal inverted by the first inverter circuit 112 are connected to the A third switch 115 is connected to a terminal from which a signal is output. a third inverter circuit 116 that inverts and outputs a signal input thereto; a fourth inverter circuit 117 that inverts and outputs the signal inverted by the circuit 116; A fourth switch 1 connected to a terminal to which a signal inverted by the inverter circuit 117 is input In the circuit diagram shown in Figure 1(B), the block indicated by the dotted line is The pulse output circuit 103 outputs pulse signals for each stage, and is the shift register shown in FIG. It is composed of N stages (N is a natural number greater than or equal to 2) of pulse output circuits. The output circuit outputs an output signal o from the output terminal of each of the third inverter circuits 116. ut1 to outN are output.

[0031] In the first switch 111 and the fourth switch 118 described above, The second switch is turned on (conducting) or off (non-conducting) by the clock signal CLK1. The third switch 114 and the third switch 115 are turned on or off by the second clock signal CLK2. The transistor is connected to the wiring 101 or the wiring 102 so that the transistor is controlled to be turned off.

[0032] Next, the first inverter circuit 112 to the fourth inverter circuit 11 used in FIG. An example of the circuit configuration of the 7 is shown in FIG. 2. By forming the semiconductor layer using an oxide semiconductor, As shown in Figure 2(A) and (B), an inverter consisting of unipolar thin film transistors is used. The inverter circuit 120 shown in FIG. 2A includes a first transistor 121, a second transistor 122, a The first transistor 121 is configured with a first terminal ( Here, the drain terminal) is connected to a wiring 122 that supplies a high power supply potential Vdd, and the second terminal ( Here, the source terminal is connected to the gate of the first transistor 121, and the terminal is connected to the The second transistor 123 is connected to the first terminal (here The drain terminal of the first transistor 121 is connected to the second terminal and gate of the second transistor 122. A terminal (here, a source terminal) is connected to a wiring 124 that supplies a low power supply potential Vss, and a gate The terminal serves as the input terminal of the inverter circuit 120.

[0033] Also, an inverter circuit with a different configuration from that shown in FIG. 2(A) is shown in FIG. 2(B). ) includes a first transistor 131 and a second transistor 132. 2. The first transistor 131 has a first terminal (here, a drain terminal) is connected to the wiring 122 that supplies the high power supply potential Vdd and the gate of the first transistor 131. The second terminal (here, the source terminal) serves as the output terminal of the inverter circuit 130. The second transistor 132 has a first terminal (here, a drain terminal) connected to the first transistor 131, and the second terminal (here, the source terminal) supplies the low power supply potential Vss. The gate of the inverter circuit 130 is connected to a wiring 124 that supplies a current to the inverter circuit 130 .

[0034] Note that a high power supply potential is a potential higher than the reference potential, and a low power supply potential is a potential lower than the reference potential. Note that both the high power supply potential and the low power supply potential are at which a transistor can operate. A potential of about 1000 V, i.e., a high power supply potential, is applied to the gate to create an ideal transistor ( When the threshold voltage is '0V', the transistor is turned on, and a low power supply potential is applied, resulting in an ideal transistor. It is desirable that the potential is such that the transistor is in an OFF state.

[0035] In addition, voltage often refers to the potential difference between a certain potential and a reference potential. The terms "voltage," "potential," and "potential difference" can be rephrased as "electric potential," "voltage," and "voltage difference," respectively.

[0036] Next, the circuit configuration of the first switch 111 to the fourth switch 118 used in FIG. As shown in FIG. 2C, the switch has a semiconductor layer made of an oxide semiconductor. The transistor 140 (sometimes referred to as the third transistor) is configured as follows. The transistor 140 functioning as a switch shown in FIG. 2C has a first terminal (source terminal The first terminal (either the source or drain terminal) is the input terminal IN of the switch, and the second terminal (either the source or drain terminal) is the The other of the drain terminals is the output terminal OUT of the switch, and the gate is connected to the wire 101 or The first clock signal CLK1 or the second clock signal C supplied from the wiring 102 LK2 (FIG. 2C shows the first clock signal CLK1 as an example) Off is controlled.

[0037] Next, the high power supply potential Vdd and the low power supply potential Vdd are input to the circuits shown in FIGS. FIG. 2 is a diagram showing a schematic diagram of the voltage amplitude of Vss and the first clock signal CLK1. In FIG. 2(D), the vertical axis represents the potential, and waveform 141 represents the first clock. 14 is shown for the clock signal CLK1, and waveform 142 is shown for the high power supply potential Vdd. Waveform 143 is shown for the low power supply potential Vss, and waveform 144 is shown for The start pulse SP is shown.

[0038] Also, in FIG. 2(E), instead of the amplitude of the voltage of the first clock signal CLK1, the amplitude of the voltage of the second clock signal CLK2 is FIG. 2(E) corresponds to a diagram showing the amplitude of the voltage of the clock signal CLK2. Similarly, the vertical axis represents potential, and waveform 145 represents the second clock signal CLK2. Waveform 142 is for the high power supply potential Vdd, and waveform 143 14 is for the low power supply potential Vss, and waveform 144 is for the start pulse SP. The second clock signal CLK2 is a clock signal having a period equal to the period of the first clock signal CLK1. This corresponds to the inverted signal of

[0039] As shown in FIGS. 2(D) and 2(E), the first clock signal CLK1 and the second clock signal The voltage amplitude of the signal CLK2 changes from a high level signal VH to a low level signal VL. The potential of the power supply potential Vdd, the potential of the low power supply potential Vss, and the voltage amplitude of the start pulse SP are The voltage Vss is larger than the low level signal VL, and the voltage Vdd is smaller than the high level signal VH.

[0040] The first inverter circuit 112 to the fourth inverter circuit 113 each have a semiconductor layer made of an oxide semiconductor. In the circuit 117, when each transistor is normally on, a large through current occurs. Therefore, the power consumption increases. By setting the amplitude voltage of the start pulse SP and the ss to a small value in advance, the power consumption can be reduced. On the other hand, the force can be reduced by the first switch 111 to the fourth switch 11 8, in order to reduce malfunctions, the ON or OFF state is reliably maintained. Therefore, the first clock signal CLK and the second clock signal By making the voltage amplitude of CLK2 larger than the power supply voltage of the inverter circuit, The on or off state of the first switch 111 to the fourth switch 118 can be more reliably maintained. It can be held.

[0041] Note that the first inverter circuit 112 to the fourth inverter circuit 111 described in FIG. 7, a first transistor 121 and a second transistor 123 are normally-on. In the case of the MOSFET, even if the voltage of the power supply potential supplied to the wiring 122 and the wiring 124 is reduced, the power consumption is reduced. Therefore, in a transistor using an oxide semiconductor for a semiconductor layer, When configuring the inverter circuit, the resistance value of the second transistor 123 is set to be equal to that of the first transistor. It is preferable to set the second transistor 121 higher than the first transistor 121. It is preferable that the L / W ratio of the first transistor 123 is larger than that of the first transistor 121. stomach.

[0042] Specifically, the L / W ratio of the second transistor 123 is set to the L / W ratio of the first transistor 121. A top view of the inverter circuit 120 with a larger ratio is shown in FIG. The circuit 120 includes a wiring 122 that supplies a high power supply potential Vdd, a wiring 123 that supplies a low power supply potential Vss, and a Line 124, first transistor 121, second transistor 123, first transistor 121, a gate wiring 201 of the second transistor 123, a gate wiring 202 of the first transistor The semiconductor layer 203 of the first transistor 121, the semiconductor layer 204 of the second transistor 123, The source terminal of the second transistor 121 and the drain terminal of the second transistor 123 are connected to each other. The connection of each wiring is the same as that in FIG. For example, the gate wiring 201 and the wiring 205 are connected via a contact hole. The gate wiring 202 serves as the input terminal IN of the inverter circuit 120, and the wiring 20 5 is the output terminal of the inverter circuit 120.

[0043] The thickness of the semiconductor layer of the second transistor 123 is set to be equal to that of the semiconductor layer of the first transistor 121. By adopting such a configuration, the resistance value can be reduced. The gate length L is the length of the gate of the transistor and the semiconductor. The gate width W is the length between the source and drain in the region where the semiconductor layers overlap. It corresponds to the width between the source and drain in the area where the gate and semiconductor layer overlap. The ratio corresponds to the ratio of gate length to gate width.

[0044] Note that in this embodiment, an example of a thin film transistor using an oxide semiconductor for a semiconductor layer will be described. However, the configuration disclosed in this embodiment is such that the thin film transistors constituting the driving circuit Therefore, for example, the amorphous silicon can be used Intentionally or unintentionally imparting n-type conductivity to semiconductor layers formed from silicon It is also used for transistors that operate as normally-on due to the inclusion of impurities. In addition, the semiconductor layer forming the channel region can be formed on the opposite side of the gate insulating film (backside). Charge accumulation on the gate (channel side) forms a parasitic channel, and The present invention is also applicable to transistors that operate as gates.

[0045] By adopting the configuration of this embodiment, transistors constituting a driver circuit of the same conductivity type are Even if the transistor is negatively on, it can be turned on or off. Even if the device is normally on, the driver circuit is highly accurate and can reduce malfunctions. This can be done.

[0046] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0047] (Embodiment 2) In this embodiment, in addition to the configuration of the driving circuit described in the first embodiment, a demultiplexer The configuration of the drive circuit provided at each output terminal of the pulse output circuit will be explained with reference to the drawings. The thin film transistor that functions as a switch, which is a configuration of the drive circuit of the first embodiment, The configuration described in this embodiment is applied to a driver circuit configured by a motor and an inverter circuit. By adding this, power consumption can be further reduced, which is preferable.

[0048] The driving circuit 400 of this embodiment shown in FIG. 4 supplies a first clock signal (CLK1). a wiring 401 for supplying a second clock signal (CLK2); a wiring 402 for supplying a second clock signal (CLK3); A pulse output circuit 403 provided by ) are supplied to the driver circuit 404. Each output terminal that outputs pulse signals for N trains has a demultiplexer circuit 405. Then, the demultiplexer circuit 405 outputs M (a natural number of 2 or more) signals with different timings. After generating the signal, pulse signals for N×M columns are output from the wiring 406 which corresponds to the output terminal. do.

[0049] That is, the number of stages of the pulse output circuit described in the first embodiment can be reduced from N to N / M. As a result, the frequency of the clock signal for driving the driving circuit can be reduced. Therefore, even if a transistor configured as a normally-on transistor is used, the consumption electrode can be It can be significantly reduced.

[0050] The demultiplexer circuit 405 receives the output signal out of the static shift register circuit. 1 to outN and the control signal of the demultiplexer circuit are ORed to form a wiring 406 A circuit for generating a plurality of pulse signals consisting of an H level signal VH and an L level signal VL at The demultiplexer circuit 405 shorts the wiring to the wiring to which the H-level signal is supplied. A state in which the L-level signal is shorted to the wiring that supplies the L-level signal, or an electrically floating state (floating Then, the demultiplexer circuit 405 is set to be a Even if the transistor is configured as a normally-on transistor, it is possible to create a circuit that can reduce malfunctions. This is a configuration that can be used.

[0051] A specific configuration of the demultiplexer circuit will be explained with reference to FIG. The demultiplexer circuit 405 generates multiple different signals from one input signal and multiple control signals. This is a circuit that generates timing signals (four in this case).

[0052] A specific example of the demultiplexer circuit 405 is a circuit including a first transistor 501, a second transistor 502, a the first transistor 502, the third transistor 503, the fourth transistor 504, and the fifth transistor A transistor 505, a sixth transistor 506, a seventh transistor 507, an eighth transistor transistor 508, ninth transistor 509, tenth transistor 510, eleventh The transistor 511, the twelfth transistor 512, the thirteenth transistor 513, the first 4, a wiring 515 and a wiring 517 for supplying a H level signal, The third transistor has a wiring 516 and a wiring 518 for supplying a level signal. The transistor 503 is turned on or off by applying a first control signal MUX1 to the gate. The fourth transistor 504 is controlled by applying a second control signal MUX2 to its gate. The fifth transistor 505 is controlled to be turned on or off by the third control signal MU The sixth transistor 506 is turned on or off by applying X3 to its gate. The fourth control signal MUX4 is applied to the gate to control whether the transistor is turned on or off. The transistor 507 of No. 7 is turned on when the first inverted control signal MUX1B is applied to the gate. The eighth transistor 508 is controlled to be on or off by the second inverted control signal MUX2. The ninth transistor 509 is turned on or off by applying B to the gate. , the third inverted control signal MUX3B is applied to the gate to control ON or OFF. The tenth transistor 510 is connected to the gate of which the fourth inverted control signal MUX4B is applied. The first terminal of the first transistor 501 is connected to a wiring 515. The gate of the second transistor 502 is connected to the output terminal of the driver circuit 400. The first terminal of the transistor 501 is connected to the wiring 516, and the gate of the transistor 501 is connected to the same driver circuit as the first transistor 501. The first terminal of the third transistor 503 is connected to the output terminal of the first transistor 400. The fourth transistor is connected to the second terminal of the transistor 501, and the second terminal is connected to the wiring G1. The first terminal of the first transistor 504 is connected to the second terminal of the first transistor 501, and the second terminal is The first terminal of the fifth transistor 505 is connected to the wiring G2. The sixth transistor 50 is connected to the second terminal of the sixth transistor 50. The sixth transistor 50 is connected to the second terminal of the sixth transistor 50. The first terminal of the first transistor 501 is connected to the second terminal of the first transistor 502, and the second terminal is connected to the wiring G4. The first terminal of the seventh transistor 507 is connected to the third terminal of the second transistor 502. The first terminal of the eighth transistor 508 is connected to the first terminal of the eighth transistor 508, and the second terminal is connected to the wiring G1. The terminal is connected to the second terminal of the second transistor 502, and the second terminal is connected to the wiring G2. The first terminal of the ninth transistor 509 is connected to the second terminal of the second transistor 502. The first terminal of the tenth transistor 510 is connected to the line G1, and the second terminal is connected to the line G3. , is connected to the second terminal of the second transistor 502, and the second terminal is connected to the wiring G4. A first terminal of the eleventh transistor 511 is connected to the wiring G1, and a gate of the eleventh transistor 511 is connected to the wiring 517. The first terminal of the twelfth transistor 512 is connected to the wiring 514, and the second terminal is connected to the wiring 518. The gate is connected to the wiring G2, the second terminal is connected to the wiring 517, and the second terminal is connected to the wiring 518. The first terminal of the thirteenth transistor 513 is connected to the wiring G3, and the gate is connected to the wiring 517. The first terminal of the fourteenth transistor 514 is connected to the wiring 518, and the second terminal is connected to the wiring 518. The first terminal is connected to the wire G4, the gate is connected to the wire 517, and the second terminal is connected to the wire 518. will be done.

[0053] In the demultiplexer circuit 405 of FIG. 5, the first transistor 501 to the tenth transistor 502 The L / W ratio of the transistor 510 is the same as that of the eleventh to fourteenth transistors 511 to 514. In other words, the first transistor 501 to the second transistor 514 are designed to be smaller than the first transistor 501 to the second transistor 514. The current supply capability of the tenth transistor 510 is The current supply capacity of the transistor 514 is designed to be higher than that of the transistor 514.

[0054] Specifically, a demultiplexer circuit is constructed using transistors that use an oxide semiconductor for a semiconductor layer. When forming the transistors 511 to 514, the resistance values ​​of the transistors 511 to 514 are set to , the first transistor 501 to the tenth transistor 510 are set to have a higher voltage than the first transistor 501 to the tenth transistor 510. That is, the eleventh transistor 511 to the fourteenth transistor 5 The L / W ratio of 14 is calculated by multiplying the L / W ratio of the first transistor 501 to the tenth transistor 510. It is preferable that the ratio is larger than the ratio of the eleventh to fourteenth transistors 511 to 514. The thickness of the semiconductor layer of the first transistor 501 to the tenth transistor 502 is set to The thickness of the semiconductor layer of the capacitor 510 may be smaller than that of the capacitor 510. This is preferable because the resistance values ​​can be made different.

[0055] In FIG. 5, wirings G1 to G4 are connected to the first to tenth transistors 501 to 505. When the signal VH is at a high level, the first transistor 501 The current supply capabilities of the first to tenth transistors 510 are By setting the current supply capacity of the wirings G1 to G4 higher than that of the transistor 514 of the fourth embodiment, The eleventh transistor 511 and the fourteenth transistor 512 can be set to a level signal VH. The transistor 514 is connected to the H-level signal VH during the period when the wirings G1 to G4 are floating. By applying this to the gate, the wirings G1 to G4 can be held at the L level signal VL. That is, the eleventh transistor 511 and the fourteenth transistor 514 are connected to the wiring G1 to G4 are for maintaining the potential of the L level signal during periods other than the potential of the H level signal VH. Note that each of the eleventh to fourteenth transistors 511 to 514 The transistors are a first transistor and a second transistor which constitute an inverter circuit of the driving circuit 400. 2 transistor, and the third transistor constituting the switch of the drive circuit 400, The first transistor 501 to the tenth transistor 502 are also referred to as the fourth transistor. The transistors of the transistor 510 are first transistors that form the inverter circuit of the driving circuit 400. The third transistor constitutes the switch of the driving circuit 400. This transistor is sometimes called the fifth transistor, following the fourth transistor mentioned above.

[0056] As described above, each transistor constituting the demultiplexer circuit 405 is also normally on. In this case, the potential of the L-level signal VL is maintained due to leakage current during the floating state. By using the circuit configuration of FIG. 5, the wirings G1 to G4 may not be able to maintain the same level. Even if there is a current, the potential of the L level signal can be maintained, reducing malfunctions. can be done.

[0057] Next, the operation of FIG. 5 will be explained with reference to the timing chart of FIG. 6. The signals are a first clock signal CLK1 and a second clock signal C LK2, the output signal out1, the output signal out2, and the output signal LK2 output from the drive circuit 400 out3, and output signal out4, as well as the first control signal MUX1, the second control signal MUX2, and the control signal MUX2, third control signal MUX3, fourth control signal MUX4, first inversion control signal MUX1B, a second inverted control signal MUX2B, a third inverted control signal MUX3B, a fourth the inverted control signal MUX4B, the output signal GOU output from the demultiplexer circuit 405, 1. The signals T1, GOUT2, and GOUT3 are shown.

[0058] As shown in FIG. 6, in response to the first clock signal CLK1 and the second clock signal CLK2, As a result, the output signals out1 to out4 are output in sequence as pulse signals. The pulse signal of t1 is a first control signal MUX1, a second control signal MUX2, a third control signal MUX3, and a By taking the logical OR of the fourth control signal MUX3 and the fourth control signal MUX4, pulses are output from the wirings G1 to G3. The first inversion control signal GOUT1, GOUT2, and GOUT3 are obtained in sequence. a first inverted control signal MUX1B, a second inverted control signal MUX2B, a third inverted control signal MUX3B, and a fourth inverted control signal MUX4B. The fourth inverted control signal MUX4B is a combination of the first control signal MUX1, the second control signal MUX2, and the third control signal MUX3. The third control signal MUX3 is a signal that has an opposite phase to the fourth control signal MUX4.

[0059] Also, the first inverted control signal MUX1B, the second inverted control signal MUX2B, and the third inverted control signal MUX3B are Instead of the fourth inverted control signal MUX3B and the fourth inverted control signal MUX4B, the inverted signal of the output signal out1 is used. The same output signal can be obtained from the wirings G1 to G4 by using the inverted output signal out1B corresponding to Figure 11 shows a specific example of the circuit configuration. Similar to FIG. 5, the multiplexer circuit 450 generates multiple signals from one input signal and multiple control signals. This is a circuit that generates a number of signals (four in this case) with different timings.

[0060] A specific example of the demultiplexer circuit 450 is a circuit including a first transistor 451, a second transistor 452, a the first transistor 452, the third transistor 453, the fourth transistor 454, the fifth transistor The transistor 455, the sixth transistor 456, the seventh transistor 457, the eighth transistor A wiring 459 for supplying an L-level signal VL to the transistor 458, an inverted output signal OU The first control signal MUX a wiring 461 for supplying the first control signal MUX1; a wiring 462 for supplying the second control signal MUX2; A wiring 463 for supplying the third control signal MUX3, a wiring 464 for supplying the fourth control signal MUX4 A first terminal of the first transistor 451 is connected to the wiring 461. The gate is connected to the output terminal of the driving circuit 400, and the second terminal is connected to the wiring G1. A first terminal of the second transistor 452 is connected to a wiring 462, and a gate of the second transistor 452 is connected to the driver circuit 40. The third transistor 453 has a first terminal connected to the output terminal of the first transistor 450 and a second terminal connected to the wiring G2. The first terminal of the transistor is connected to the wiring 463, the gate is connected to the output terminal of the driving circuit 400, and the third terminal of the transistor is connected to the wiring 463. The second terminal of the fourth transistor 454 is connected to the wiring G3. The gate is connected to the output terminal of the drive circuit 400, and the second terminal is connected to the wiring G4. The input terminal of the inverter circuit 460 is connected to the output terminal of the drive circuit 400. A first terminal of the fifth transistor 455 is connected to a wiring 459, and a gate of the fifth transistor 455 is connected to an inverter. The sixth transformer has a first terminal connected to the output terminal of the data circuit 460, and a second terminal connected to the wiring G1. The first terminal of the resistor 456 is connected to a wiring 459, and the gate is connected to the output of the inverter circuit 460. The first terminal of the seventh transistor 457 is connected to the terminal G1, and the second terminal is connected to the wiring G2. The terminal is connected to a wiring 459, the gate is connected to an output terminal of an inverter circuit 460, and the second The first terminal of the eighth transistor 458 is connected to the wiring G3. The gate is connected to the output terminal of the inverter circuit 460, and the second terminal is connected to the wiring G4. will be done.

[0061] 6, a timing chart of each signal in FIG. 11 is shown in FIG. 12. As shown in Figure 6, the same output signal can be obtained.

[0062] In the demultiplexer circuit 450 of FIG. 11, the first transistor 451 to the fourth transistor 452 The L / W ratio of the transistor 454 is In other words, the first transistor 451 to the fourth transistor 458 are designed to be smaller than the first transistor 451 to the fourth transistor 458. The current supply capacity of the fifth to eighth transistors 455 to 456 is It is designed to be higher than the current supply capacity of the stator 458.

[0063] Specifically, a demultiplexer circuit is constructed using transistors that use an oxide semiconductor for a semiconductor layer. When forming the transistors, the resistance values ​​of the fifth to eighth transistors 455 to 458 are set to The first to fourth transistors 451 to 454 are set to have a higher voltage than the first to fourth transistors 451 to 454. That is, the L / R of the fifth transistor 455 to the eighth transistor 458 is preferably The W ratio is set to be larger than the L / W ratios of the first to fourth transistors 501 to 454. It is preferable that the fifth to eighth transistors 455 to 458 The thickness of the semiconductor layer of the first transistor 451 to the semiconductor layer of the fourth transistor 454 is By adopting such a configuration, the resistance value can be changed. Note that the fifth to eighth transistors 455 to 458 are Each transistor of the register 458 is a first transistor that constitutes an inverter circuit of the driving circuit 400. a third transistor that constitutes a switch of the driving circuit 400; The first transistor 451 is also called the fourth transistor. The first to fourth transistors 454 are transistors that form inverter circuits in the driver circuit 400. The first and second transistors constitute the switches of the drive circuit 400. Following the third transistor and the fourth transistor mentioned above, we call this the fifth transistor. Sometimes it happens.

[0064] As shown in FIGS. 11 and 12, the inverted output signal out1B is input to a demultiplexer circuit 405. By using this, the number of input signals can be reduced. This reduces the wiring area, thereby saving space and enabling the miniaturization of the drive circuit. This allows for smaller size and lower power consumption.

[0065] By adopting the configuration of this embodiment, transistors constituting a driver circuit of the same conductivity type are Even if the transistor is negatively on, it can be turned on or off. Even if the device is normally on, the driver circuit is highly accurate and can reduce malfunctions. This can be done.

[0066] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0067] (Embodiment 3) In this embodiment, the manufacturing process of the driver circuit described in the above embodiment, particularly, the manufacturing process of the oxide semiconductor layer A top view and a cross-sectional view of a thin film transistor having a semiconductor layer will be described. The display device having the drive circuit described in the embodiment can be applied to a liquid crystal display device. Furthermore, the present invention can also be applied to a display device equipped with a light-emitting element such as an organic EL element. The driver circuit described in the above embodiment is also used for driving electronic paper having electrophoretic elements. It is possible to apply the present invention not only to the driving circuits of display devices but also to circuits for optical sensors. It is also applicable to other devices such as a drive circuit.

[0068] FIG. 7 shows the first transistor 121 and the second transistor 122 described in FIG. 3 of the first embodiment. 8 is a top view of the inverter circuit 120 configured with the first transistor 123. 8 is a cross-sectional view of the first transistor 121 and the second transistor 123. The cross-sectional view of the transistor 121 and the second transistor 123 is the same as that of the inverter circuit shown in FIG. These correspond to the lines A-A', B-B', and C-C' in the top view of 120. In this embodiment, the method of forming a thin film transistor when forming a semiconductor layer using an oxide semiconductor is particularly An example of the method will be described below.

[0069] First, a base film 902 is formed on a substrate 901. Next, a conductive film is formed on the base film 902. Thereafter, gate electrode layers 903A and 903B are formed by a photolithography process.

[0070] The resist mask may be formed by an ink-jet method. When the film is formed by the jet method, no photomask is used, and therefore the manufacturing cost can be reduced.

[0071] The conductive film forming the gate electrode layers 903A and 903B may be Al, Cr, Ta, Ti, An element selected from Mo, W, or an alloy containing the above elements, or a combination of the above elements Examples of such films include alloy films in which a metal oxide is combined with a metal oxide.

[0072] In addition, when a glass substrate is used as the substrate 901, if the temperature of the subsequent heat treatment is high, distortion may occur. It is advisable to use a glass substrate with a melting point of 730°C or higher. Glass materials such as borosilicate glass, aluminoborosilicate glass, and barium borosilicate glass Fees are used.

[0073] The base film 902 has a function of preventing the diffusion of impurity elements from the substrate 901, and is a silicon nitride film. , a silicon oxide film, a silicon nitride oxide film, or a silicon oxynitride film. It can be formed in a laminated structure.

[0074] Next, a gate insulating layer 904 is formed on the gate electrode layers 903A and 903B.

[0075] The gate insulating layer 904 is formed by depositing a silicon oxide layer by plasma CVD, sputtering, or the like. A silicon nitride layer, a silicon oxynitride layer, or a silicon nitride oxide layer may be formed as a single layer or a stacked layer. For example, the plasma CVD method can be performed using SiH4, oxygen, and nitrogen as the deposition gas. A silicon oxynitride layer may be formed.

[0076] Next, the gate insulating layer 904 is selectively etched by a photolithography process to form a gate insulating layer 904. A contact hole reaching the gate electrode layer 903B is formed.

[0077] Next, an oxide semiconductor film is formed over the gate insulating layer 904. After the oxide semiconductor film is formed The oxide semiconductor film is kept amorphous even when heat treatment for dehydration or dehydrogenation is performed. When using the film, it is preferable to make the film thickness thin, 50 nm or less.

[0078] The oxide semiconductor film is an In-Ga-Zn-O based non-single crystal film, an In-Sn-Zn-O based film, an In -Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al- Zn-O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-O series, S The oxide semiconductor film is formed by using a rare gas ( Typically, under an atmosphere of argon, oxygen, or a rare gas (typically argon) and oxygen. It can be formed by sputtering in a nitrogen atmosphere.

[0079] Here, an oxide semiconductor target containing In, Ga, and Zn (In2O3:Ga2O 3:ZnO=1:1:1[mol%], In:Ga:Zn=1:1:0.5[at%]) The distance between the substrate and the target was 100 mm, the pressure was 0.6 Pa, and the direct current (DC) The film is formed in an oxygen atmosphere (oxygen flow rate 100%) with a power supply of 0.5 kW. Use of a (DC) power supply is preferable because it reduces dust and makes the film thickness distribution uniform.

[0080] There are two types of sputtering methods: RF sputtering, which uses a high frequency power supply for the sputtering power source, and DC sputtering. There is also the pulsed DC sputtering method, which applies a pulsed bias. The DC sputtering method is mainly used to deposit insulating films, while the DC sputtering method is mainly used to deposit metal conductive films. It is used in such cases.

[0081] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The equipment can deposit layers of different materials in the same chamber, or multiple types of materials in the same chamber. It is also possible to simultaneously discharge and deposit the same materials.

[0082] Also, a sputtering apparatus using a magnetron sputtering method equipped with a magnet mechanism inside the chamber and ECR sputtering using plasma generated by microwaves without glow discharge. There are sputtering devices that use this method.

[0083] In addition, in the film formation method using the sputtering method, the target material and the sputtering gas component are mixed during film formation. Reactive sputtering is used to form thin films of these compounds by chemically reacting them with each other. There is also a bias sputtering method in which a voltage is also applied to the substrate.

[0084] Before forming the oxide semiconductor film by a sputtering method, argon gas was introduced to form a plasma. Reverse sputtering is performed to generate a mask, and dust adhering to the surface of the gate insulating layer 904 is removed. Reverse sputtering is a method in which a target is sputtered in an argon atmosphere without applying a voltage to the target. A voltage is applied to the substrate side using an RF power supply under atmospheric pressure to form plasma near the substrate and modify the surface. It is also possible to use nitrogen, helium, oxygen, etc. instead of the argon atmosphere. good.

[0085] Next, the oxide semiconductor film is subjected to a photolithography process to form an island-shaped oxide semiconductor layer 905A. , 905B. In addition, in order to form island-shaped oxide semiconductor layers 905A and 905B, The resist mask may be formed by an ink-jet method.

[0086] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the heat treatment is 400°C or higher and 750°C or lower, preferably 425°C or higher and lower than the strain point of the substrate. If the temperature is 425°C or higher, the heat treatment time can be 1 hour or less. If possible, the heat treatment time should be longer than 1 hour. The substrate is placed in an electric furnace, and the oxide semiconductor layer is subjected to a heat treatment in a nitrogen atmosphere. After the treatment, the oxide semiconductor layer is prevented from being exposed to the air, preventing water and hydrogen from re-entering the oxide semiconductor layer. In this embodiment, the oxide semiconductor layer is dehydrated or dehydrogenated. From the heating temperature T, use the same furnace to a temperature high enough to prevent water from entering again. The temperature is gradually cooled in a nitrogen atmosphere until it drops by 100°C or more below the temperature T. It is not dehydrated or dehydrogenated under rare gases (helium, neon, argon, etc.). Depending on the heating conditions, the crystallization rate of the oxide semiconductor may be 90% or more, or 80% or more. It may be above.

[0087] The heat treatment device is not limited to an electric furnace, and may be a heat treatment device using heat conduction or heat from a heat source such as a resistance heating element. A device for heating the object to be treated by radiation may be provided. For example, a GRTA (Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Anneal) equipment, etc. The LRTA device can be used with halogen lamps, metal halide lamps, etc. lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, high pressure A device that heats the workpiece by radiating light (electromagnetic waves) emitted from a lamp such as a mercury lamp. The GRTA device is a device that uses high-temperature gas for heat treatment. An inert gas that does not react with the material to be treated by heat treatment, such as a rare gas such as argon or nitrogen. Sexual gases are used.

[0088] Next, a conductive film is formed on the gate insulating layer 904 and the oxide semiconductor layers 905A and 905B. After that, a resist mask is formed by a photolithography process, and selective etching is performed. The electrode layer 906 is formed by the above process. The conductive film may be made of Ti, Mo, W, Al, Cr, Cu, Ta, or an alloy containing the above elements as components, or a combination of the above elements The conductive film is not limited to a single layer containing the above-mentioned elements, but may be a layer of two or more layers. Note that in FIG. 8, only the conductive film in contact with the oxide semiconductor layer is selected. Therefore, only the conductive film in contact with the oxide semiconductor layer is selectively removed. To achieve this, an alkaline etchant was used: ammonia hydrogen peroxide (31% by weight hydrogen peroxide solution: By using a mixture of 28% by weight of ammonia water and water (5:2:2), the conductive film can be selectively removed. The oxide semiconductor layer made of an In-Ga-Zn-O-based oxide semiconductor can be left. .

[0089] Next, an insulating layer is formed on the gate insulating layer 904, the oxide semiconductor layers 905A and 905B, and the electrode layer 906. The insulating layer 907 is formed to a thickness of at least 1 nm by sputtering. The oxide insulating film is formed by appropriately using a method that does not allow impurities such as water and hydrogen to be mixed into the oxide insulating film, such as a etching method. The insulating layer 907 formed in contact with the oxide semiconductor layers 905A and 905B can be Water, hydrogen ions, and OH - It does not contain impurities such as A blocking inorganic insulating film is used, typically a silicon oxide film, a silicon nitride oxide film, or an aluminum oxide film. Aluminum film, aluminum oxide nitride, or the like is used.

[0090] Through the above steps, the first transistor 121 and the second transistor 123 are manufactured. This can be done.

[0091] Note that the first transistor 121 and the second transistor 123 shown in FIG. 8 are made of oxide semiconductor. It is a bottom gate type TFT that uses a conductor as the semiconductor layer. A top gate type TFT may also be used.

[0092] By adopting the configuration of this embodiment, the transistors constituting the driver circuit are normally Even when the transistor is on, it can be in an on or off state. Even if the device is normally on, the driver circuit is highly accurate and can reduce malfunctions. This can be done.

[0093] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0094] (Fourth embodiment) In this embodiment, at least a part of the driver circuit and a thin film transistor disposed in the pixel portion are formed on the same substrate. An example of manufacturing a thin film transistor will be explained below. , may be formed in the same manner as in the third embodiment.

[0095] An example of a block diagram of an active matrix display device is shown in FIG. On the plate 5300, a pixel portion 5301, a first scanning line driving circuit 5302, a second scanning line driving circuit 5303, a The pixel portion 5301 has a plurality of signal lines. A plurality of scanning lines are arranged extending from the signal line driving circuit 5304, and the first scanning line driving circuit 5 302 and a scanning line driver circuit 5303. In the intersection area of ​​the lines 1 and 2, pixels each having a display element are arranged in a matrix. The display device substrate 5300 is an FPC (Flexible Printed Circuit) t) and other connections to a timing control circuit 5305 (also called a controller or control IC). It is connected to the

[0096] In FIG. 9A, a first scanning line driver circuit 5302, a second scanning line driver circuit 5303, a signal The line driver circuit 5304 is formed on the same substrate 5300 as the pixel portion 5301. The number of externally provided components such as drive circuits is reduced, which contributes to cost reduction. When a driving circuit is provided outside the substrate 5300, it becomes necessary to extend the wiring, and the connection between the wiring becomes difficult. If a driver circuit is mounted on the same board 5300, the number of connections between the wiring will be reduced. This can improve reliability or yield.

[0097] The timing control circuit 5305 controls the first scanning line driver circuit 5302 as follows: The first scanning line driving circuit start signal (GSP1), the scanning line driving circuit clock signal The timing control circuit 5305 also supplies the second scanning line driving circuit (GCLK1). For example, a start signal for the second scanning line driving circuit (GSP2) (S It supplies the clock signal (GCLK2) for the scanning line driver circuit. The signal line driver circuit 5304 receives a start signal (SSP) for the signal line driver circuit, Clock signal (SCLK), video signal data (DATA) (also simply called video signal) ), and latch signal (LAT). Each clock signal has a different period. It may be multiple clock signals, or may be provided together with an inverted clock signal (CLKB). The first scanning line driver circuit 5302 and the second scanning line driver circuit 5303 may be connected to each other. One of the circuits 5302 and 5303 can be omitted.

[0098] In FIG. 9B, circuits with low driving frequencies (for example, the first scanning line driving circuit 5302, the second scanning line driving circuit 5303, The scanning line driver circuit 5303 is formed on the same substrate 5300 as the pixel portion 5301, and the signal line driver This shows a structure in which the circuit 5304 is formed on a substrate different from that of the pixel portion 5301. The thin film transistor has a lower field-effect mobility than a transistor using a single-crystal semiconductor due to its structure. A driver circuit formed on the substrate 5300 can be configured using transistors. Therefore, it is possible to increase the size of the display device, reduce the number of processes, reduce costs, or improve yields. It is possible.

[0099] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiments. is.

[0100] (Embodiment 5) In this embodiment, an electronic device includes the display device described in the above embodiment as a display unit. An example of this will be described.

[0101] The contents (or even a part thereof) described in each of the drawings of the above embodiments can be applied to various electronic devices. Specifically, it can be applied to the display unit of an electronic device. The devices include video cameras, digital cameras, goggle displays, and navigation systems. Stems, sound reproduction devices (car audio, audio components, etc.), computers, games Equipment, personal digital assistants (mobile computers, mobile phones, portable game consoles, e-books, etc.) ), image reproducing devices equipped with recording media (specifically, Digital Versatile A device equipped with a display that can play recording media such as discs (DVDs) and display the images. equipment).

[0102] FIG. 10A shows a display, which includes a housing 1211, a support base 1212, and a display unit 1213. The display shown in FIG. 10(A) displays various information (still images, moving images, text images, etc.). The display shown in FIG. 10(A) has a function to display the information such as the The functions are not limited to these, and various functions can be provided.

[0103] FIG. 10(B) shows a camera, which includes a main body 1231, a display unit 1232, an image receiving unit 1233, and an operation key. 1234, an external connection port 1235, and a shutter button 1236. The camera shown in has a function to take still images and a function to take videos. The functions of the camera shown in FIG. 10(B) are not limited to these, and may have various functions. can.

[0104] FIG. 10(C) shows a computer, which includes a main body 1251, a housing 1252, a display unit 1253, and a keyboard. It includes a keyboard 1254, an external connection port 1255, and a pointing device 1256. The computer shown in Figure 10(C) displays various information (still images, videos, text images, etc.) The computer shown in FIG. 10C has the function of displaying the information on the display unit. The function is not limited to this and may have various functions.

[0105] By using the display device described in the above embodiment as the display unit of this embodiment, The transistors constituting the driver circuits shown in FIGS. 10A to 10C are normally-on. Even if the transistor is turned on, it can be turned off. Even in the case of marion, it is possible to make a drive circuit that is highly accurate and can reduce malfunctions. In addition, power consumption can be reduced by reducing the frequency of the clock signal of the driver circuit. It is also possible to

[0106] This embodiment mode can be implemented in appropriate combination with other embodiment modes. [Explanation of symbols]

[0107] 100 Drive circuit 101 Wiring 102 Wiring 103 Pulse output circuit 104 Wiring 111 First Switch 112 first inverter circuit 113 Second inverter circuit 114 Second Switch 115 The Third Switch 116 Third inverter circuit 117 Fourth Inverter Circuit 118 The Fourth Switch 120 Inverter circuit 121 First transistor 122 Wiring 123 Second Transistor 124 Wiring 130 Inverter circuit 131 First transistor 132 Second Transistor 140 transistors 141 Waveform 142 Waveform 143 Waveform 144 Waveform 145 Waveform 201 Gate wiring 202 Gate wiring 203 Semiconductor layer 204 Semiconductor layer 205 Wiring 400 drive circuit 401 Wiring 402 Wiring 403 Pulse output circuit 404 Wiring 405 Demultiplexer Circuit 406 Wiring 501 first transistor 502 second transistor 503 Third Transistor 504 Fourth Transistor 505 The fifth transistor 506 The 6th Transistor 507 The 7th Transistor 508 The 8th Transistor 509 The 9th Transistor 510 The 10th Transistor 511 11th Transistor 512 12th Transistor 513 The 13th Transistor 514 The 14th Transistor 515 Wiring 516 Wiring 517 Wiring 518 Wiring 901 Circuit Board 902 Base film 904 Gate insulating layer 906 Electrode layer 907 Insulation Layer 1211 Case 1212 Support stand 1213 Display section 1231 Main unit 1232 Display section 1233 Image receiving unit 1234 Operation Key 1235 External connection port 1236 Shutter button 1251 Main Unit 1252 Case 1253 Display section 1254 keyboard 1255 External connection port 1256 pointing device 5300 board 5301 Pixel unit 5302 Scanning line driver circuit 5303 Scanning line driver circuit 5304 Signal line driver circuit 5305 Timing control circuit 903A Gate electrode layer 903B gate electrode layer 905A Oxide semiconductor layer 450 Demultiplexer Circuit 451 First Transistor 452 Second Transistor 453 The third transistor 454 The fourth transistor 455 The fifth transistor 456 The 6th Transistor 457 The 7th Transistor 458 The 8th Transistor 459 Wiring 460 Inverter Circuit 461 Wiring 462 Wiring 463 Wiring 464 Wiring

Claims

[Claim 1] a first insulating layer on the substrate; a drive circuit having a first transistor and a second transistor on the first insulating layer; The first transistor is a first gate electrode layer; a second insulating layer on the first gate electrode layer; a first oxide semiconductor layer on the first insulating layer, the first oxide semiconductor layer having a region overlapping with the first gate electrode layer; a first electrode layer having a region in contact with an upper surface of the first oxide semiconductor layer; a second electrode layer having a region in contact with an upper surface of the first oxide semiconductor layer, The second transistor is a second gate electrode layer; the second insulating layer on the second gate electrode layer; a second oxide semiconductor layer on the second insulating layer, the second oxide semiconductor layer having a region overlapping with the second gate electrode layer; a third electrode layer having a region in contact with an upper surface of the second oxide semiconductor layer; the second electrode layer having a region in contact with an upper surface of the second oxide semiconductor layer, the second electrode layer is electrically connected to the first gate electrode layer; a channel length direction of the first transistor is along a first direction, a channel length direction of the second transistor is a direction along the first direction, the first electrode layer has a region extending in the first direction; The second electrode layer has a region extending in the first direction.

Images