Wiring board and semiconductor device

Abstract

To provide a wiring structure that is less likely to cause peel-off and cracks even in a case where an adhesion layer and a stress buffer layer do not affect electrical characteristics.SOLUTION: A wiring board includes: a substrate 11 that contains an inorganic insulation material on its surface; a first conductive layer 12 arranged on the inorganic insulation material so as to have a first region As1 and a second region As2 surrounding the first region; a second conductive layer 14 arranged on the first region of the first conductive layer, being thicker than the first conductive layer; and an organic insulation layer 22 arranged on the second region of the first conductive layer and on the inorganic insulation material.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a wiring substrate. [Background technology]

[0002] In a wiring board, where wiring is arranged on a substrate, the insulating material and the wiring arranged on this insulating material are formed. Various problems may arise depending on the relationship with the metal material that forms the insulating material. The difference in adhesion and thermal stress between the insulating material and the metal material can cause the wiring to peel off from the insulating material or the insulating material to break down. If peeling or cracks occur during manufacturing, it is a manufacturing defect. This reduces the yield, and if it occurs after the product is completed, it can lead to a decrease in reliability. In order to prevent such a decrease in yield or reliability, an adhesive layer is provided. For example, Patent Documents 1 and 2 disclose techniques for providing a stress buffer layer. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2017-5081 A [Patent Document 2] Japanese Patent Application Publication No. 2018-107423 Summary of the Invention [Problem to be solved by the invention]

[0004] By providing an adhesion layer or stress buffer layer as described above, various manufacturing defects can be eliminated. On the other hand, it is possible to improve peeling and cracks by using only such a layer. In this case, the presence of this layer may affect the electrical characteristics. When the wiring is viewed from the surface of the board, Stress is concentrated at the boundary between the wiring and the adhesive layer or the stress buffer layer. Therefore, it is important to ensure that the adhesive layer and the stress buffer layer are electrically Even if it does not affect the electrical characteristics, it is necessary to develop a wiring structure that is less susceptible to peeling and cracking. It is preferable to devise and adopt such measures in order to reduce product defects.

[0005] One of the purposes of the present disclosure is to prevent manufacturing defects occurring in wiring boards by a method different from the conventional method. The purpose is to restrain. [Means for solving the problem]

[0006] According to the present disclosure, a substrate including an inorganic insulating material on a surface thereof, and a metal oxide film disposed on the inorganic insulating material, a first conductive layer having a first region and a second region surrounding the first region; a second conductive layer disposed on the first region and having a thickness greater than that of the first conductive layer; an organic insulating layer disposed on the second region and on the inorganic insulating material. will be done.

[0007] The second conductive layer may further include a third conductive layer connected to the second conductive layer. a contact portion with the conductive layer and an extension portion extending outward from the contact portion, The distance from the outer edge of the second region to the outer edge of the contact portion is The distance may be less than or equal to the distance to the

[0008] The thickness of the first conductive layer is greater than the distance from the outer edge of the first region to the outer edge of the second region. It can be small.

[0009] The substrate has a through hole formed therein that penetrates the first surface and the second surface, and the through hole has an inner surface on which: The first conductive layer is disposed on the first surface and the second surface, and the second region is It may be present on one surface and on said second surface.

[0010] The substrate has a through hole formed therein that penetrates the first surface and the second surface, and a metal layer is formed on the inner surface of the through hole. The first conductive layer may be disposed, and the second region may be present on an inner surface of the through hole.

[0011] The first conductive layer and the second conductive layer may have different physical properties.

[0012] The first conductive layer and the second conductive layer may be made of different materials.

[0013] According to the present disclosure, there is also provided a semiconductor device including the above-described wiring board and a semiconductor electrically connected to the wiring board. A semiconductor device including a chip is provided. [Effects of the Invention]

[0014] According to the present disclosure, manufacturing defects occurring in wiring boards are suppressed by a method different from conventional methods. It is possible. [Brief explanation of the drawings]

[0015] [Figure 1] 1 is a schematic plan view showing a wiring substrate according to a first embodiment of the present disclosure. [Figure 2] 1 is a schematic cross-sectional view (cross-sectional view taken along line A1-A2 in FIG. 1) illustrating a wiring board according to a first embodiment of the present disclosure. [Figure 3] 3 is an enlarged view of the wiring according to the first embodiment of the present disclosure (an enlarged view of the vicinity of an area AX in FIG. 2). FIG. [Figure 4] FIG. 2 is a diagram illustrating the relationship between a first conductive layer and a second conductive layer according to the first embodiment of the present disclosure. [Figure 5]3A to 3C are diagrams illustrating a method for manufacturing a wiring substrate according to the first embodiment of the present disclosure. [Figure 6] 3A to 3C are diagrams illustrating a method for manufacturing a wiring substrate according to the first embodiment of the present disclosure. [Figure 7] 3A to 3C are diagrams illustrating a method for manufacturing a wiring substrate according to the first embodiment of the present disclosure. [Figure 8] 2A to 2C are diagrams illustrating a method for manufacturing a wiring substrate according to the first embodiment of the present disclosure. [Figure 9] 3A to 3C are diagrams illustrating a method for manufacturing a wiring substrate according to the first embodiment of the present disclosure. [Figure 10] 5A to 5C are diagrams illustrating a method for manufacturing a wiring according to a second embodiment of the present disclosure. [Figure 11] 5A to 5C are diagrams illustrating a method for manufacturing a wiring according to a second embodiment of the present disclosure. [Figure 12] FIG. 10 is a schematic cross-sectional view showing details of the structure of a wiring according to a third embodiment of the present disclosure. [Figure 13] 10A to 10C are diagrams illustrating a method for manufacturing a wiring substrate according to a third embodiment of the present disclosure. [Figure 14] 10A to 10C are diagrams illustrating a method for manufacturing a wiring substrate according to a third embodiment of the present disclosure. [Figure 15] 10A to 10C are diagrams illustrating a method for manufacturing a wiring substrate according to a third embodiment of the present disclosure. [Figure 16] FIG. 10 is a schematic cross-sectional view showing details of the structure of a wiring according to a fourth embodiment of the present disclosure. [Figure 17] 10A to 10C are diagrams illustrating a method for manufacturing a wiring board according to a fourth embodiment of the present disclosure. [Figure 18] 10A to 10C are diagrams illustrating a method for manufacturing a wiring board according to a fourth embodiment of the present disclosure. [Figure 19] 10A to 10C are diagrams illustrating a method for manufacturing a wiring board according to a fourth embodiment of the present disclosure. [Figure 20] 10A to 10C are diagrams illustrating a method for manufacturing a wiring board according to a fifth embodiment of the present disclosure. [Figure 21] 10A to 10C are diagrams illustrating a method for manufacturing a wiring board according to a fifth embodiment of the present disclosure. [Figure 22]10A to 10C are diagrams illustrating a method for manufacturing a wiring board according to a fifth embodiment of the present disclosure. [Figure 23] 10A to 10C are diagrams illustrating a method for manufacturing a wiring board according to a fifth embodiment of the present disclosure. [Figure 24] 10A to 10C are diagrams illustrating a method for manufacturing a wiring according to a sixth embodiment of the present disclosure. [Figure 25] 10A to 10C are diagrams illustrating a method for manufacturing a wiring according to a sixth embodiment of the present disclosure. [Figure 26] FIG. 10 is a diagram showing a simulation result of the operating frequency dependency of the reflection characteristic (S11). [Figure 27] FIG. 10 is a diagram showing the simulation results of the operating frequency dependency of the pass characteristic (S21). DETAILED DESCRIPTION OF THE INVENTION

[0016] Hereinafter, an embodiment of the present disclosure will be described with reference to the drawings. The embodiments are merely examples, and the present disclosure is not to be construed as being limited to these embodiments. In the drawings referred to in this embodiment, the same parts or parts having similar functions are designated by the same reference numerals. A symbol or similar symbol (a symbol consisting of a number followed by A, B, etc.) is added, and the symbol is repeated. In addition, the dimensional ratios in the drawings may differ from the actual ratios for the sake of convenience. In some cases, the drawings may not include all the details, and some of the components may be omitted. In order to facilitate illustration and understanding, the scale and aspect ratio of the actual product are used. The drawings may be modified and exaggerated, or some components may be omitted from the drawings.

[0017] First Embodiment [1. Overall structure] The wiring board according to the embodiment of the present disclosure includes a through hole and a wiring. The wiring board having such wiring is formed on the inorganic insulating material. In this example, the wiring board is an interposer having a through hole. The wiring board may not have a through hole.

[0018] FIG. 1 is a schematic plan view showing a wiring substrate 10 according to a first embodiment of the present disclosure. 1 is a schematic cross-sectional view showing a wiring board 10 according to a first embodiment of the present disclosure (a cross-sectional view taken along line AA in FIG. 1); In FIG. 1, the positions of the substrate 11, the first conductive layer 12, and the second conductive layer 14 are Some configurations have been omitted to make the relationships easier to understand.

[0019] The wiring board 10 includes a substrate 11, a first conductive layer 12, and a second conductive layer 14. The substrate 11 has a first surface 11a and a second surface 11b opposite to the first surface 11a. The substrate 11 has an insulating surface, and in this example, is made of alkali-free glass. The thickness may be appropriately designed depending on the application of the wiring board 10. For example, if the substrate 11 is made thicker, It is possible to prevent bending due to external force, and by making the substrate 11 thin, it is possible to follow and bend due to external force. However, the substrate 11 can be formed to such an extent that the through-hole 15 having the desired opening width can be formed. Specifically, the thinner the substrate 11, the easier it is to set the thickness of the through hole with a smaller opening width. Therefore, the thickness of the substrate 11 is set to 30 μm or more and 1000 μm or less. It is preferable that the thickness is 400 μm in this example.

[0020] The substrate 11 may be made of an inorganic insulating material other than glass, or may be made of an organic material. For example, when a silicon substrate is used as an interposer, To achieve this, the substrate surface is covered with an inorganic insulating material such as a silicon oxide film or a silicon nitride film. Silicon is a material with excellent rigidity, but it is also conductive. In addition, the sidewall of the through hole is covered with an inorganic insulating material such as a silicon oxide film or a silicon nitride film. By forming the through hole in a small diameter, it is possible to form a through electrode with a high aspect ratio. On the other hand, glass, especially non-alkali glass and quartz, is insulating. Therefore, unless there is a specific reason, there is no need to cover the surface with another material to obtain insulation. Therefore, when considering electrical properties, it can be considered as a uniform material, and the characteristics Simulation and wiring structure design are easier. In the case of materials that have high insulating properties but are less insulating than alkali-free glass, If necessary, it may be coated with an inorganic insulating material in the same manner as in the case of a silicon substrate.

[0021] The wiring 100 has a structure in which a plurality of conductive layers (two conductive layers in this example) are stacked, and the wiring 100 is A first conductive layer 12 is disposed on the surface of the first conductive layer 11, and a second conductive layer 13 is laminated on a part of the first conductive layer 12. The first conductive layer 12 includes a region near the edge where the second conductive layer 14 is not disposed. In the plan view shown in FIG. 1, the edge of the first conductive layer 12 is in contact with the edge of the second conductive layer 14. The second conductive layer 14 of the first conductive layer 12 is disposed on the outer side of the first conductive layer 12. The region is referred to as a first region As1, and the other region, that is, the region where the second conductive layer 14 is disposed, is referred to as a second region As2. The area without the ion beam is called the second area As2 (see Figure 3). According to this definition, the first area As1 is It can also be said that it is surrounded by the second region As2.

[0022] The first conductive layer 12 is directly attached to the surface (first surface 11a or second surface 11b) of the substrate 11. Alternatively, the substrate 11 may be provided with at least one conductive or insulating layer interposed therebetween. Alternatively, the insulating layer 10 may be disposed on an inorganic insulating material different from the inorganic insulating material on the surface of the insulating layer 10 .

[0023] The first conductive layer 12 corresponds to a portion of the seed layer. The seed layer is formed by electrolytically depositing the second conductive layer 14. The first conductive layer 12 is a conductive layer that functions as an electrode when the first conductive layer 12 is formed by plating. , copper (Cu) film, but chromium (Cr), titanium (Ti), nickel (Ni), The film may be made of other materials such as talc (Ta) or molybdenum (Mo), or may be made of multiple films. The thickness of the first conductive layer 12 is preferably 0.05 μm or more and 2 μm or less. , more preferably 0.05 μm or more and 1 μm or less, and in this example it is 0.2 μm.

[0024] In this example, the first conductive layer 12 is formed by electroless plating, but it may be formed by other methods such as sputtering. When the electroless plating method is used, the through hole 1 may be formed by the method. Even if the aspect ratio of the through hole 15 is large, the first conductive layer 12 is formed on the inner surface 15a of the through hole 15. On the other hand, the first conductive layer 12 formed by electroless plating is easily formed on the substrate 11. In such cases, the adhesion to the substrate tends to be weaker than when the substrate is formed by sputtering. However, by adopting the structure of the wiring 100 according to the present disclosure, the wiring can be When the second conductive layer 14 is pressed against the first conductive layer 12, the stress concentrated at the end of the second conductive layer 14 can be dispersed by the first conductive layer 12. Furthermore, since the contact area of ​​the first conductive layer 12 with the substrate 11 increases, the wiring 100 In addition, when it is desired to further suppress peeling, An adhesive layer may be used in combination. Conversely, if cracks are to be suppressed, a stress buffer layer may be used in combination. You can do that.

[0025] The second conductive layer 14 is formed by electrolytic plating using the first conductive layer 12 as a seed layer. In this example, the second conductive layer 14 is a Cu film, but it may be a film of another conductive material. The thickness of the second conductive layer 14 increases as the thickness increases. The stress caused by thermal changes increases as the thickness increases, so a thinner thickness is preferable to prevent peeling and cracking. However, in order to reduce the wiring resistance, it is preferable that the second conductive layer 14 is thicker. The thickness is designed to balance these factors, and in this example, it is 0.5 μm or 40 μm. It is preferable that the thickness is 5 μm or less, and more preferably 5 μm or more and 30 μm or less. The thickness of the first conductive layer 12 and the second conductive layer 14 is 20 μm. The first conductive layer 12 and the second conductive layer 13 may be made of the same material. Even if the two are made of the same material, they may be made of different materials such as different film qualities. It may have a property.

[0026] The substrate 11 has a through-hole 15 that penetrates from the first surface 11a to the second surface 11b. The first conductive layer 12 and the second conductive layer 14 are also disposed inside the through hole 1. The first conductive layer 12 and the second conductive layer 14 disposed inside the first surface 1 of the substrate 11 are The through holes 15 extend from the first surface 11a to the second surface 11b, thereby forming through electrodes. In this example, a conductive layer is disposed along the inner surface 15a of the through hole 15, and the central axis portion An insulating layer 22 is disposed on the portion, but may be covered by a conductive layer.

[0027] To suppress transmission loss, it is necessary to reduce the wiring resistance including the through electrodes. If the through holes 15 are made larger, the wiring pitch cannot be made smaller, making integration difficult. Therefore, the opening width of the through hole 15 must be at least twice the thickness of the second conductive layer 14. Taking into consideration the processing accuracy, it is preferable that the thickness is 150 μm or less. Here, the opening width of the through-hole 15 is the width between the first surface 11a and the second surface 11b. The figure formed by the cross section of the through hole 15 along these planes is defined, and any of the outer edges of the figure is The maximum value that can be taken as the distance between any two points. In this case, the width mentioned above refers to the diameter of the circle. Therefore, the opening width may be different between the first surface 11a and the second surface 11b. The opening width of the through-hole 15 is set to 150 μm or less. 10 shows the narrower opening width of the two.

[0028] For example, when the thickness of the second conductive layer 14 is 20 μm, after the second conductive layer 14 is formed, In order to provide an opening between the first surface 11a and the second surface 11b in the through hole 15, the opening width The lower limit of the thickness must be twice the thickness of the second conductive layer 14, that is, 40 μm or more. By providing an opening in the through-hole 15, gas and and liquid flow can be generated.

[0029] On the other hand, it is also possible to close the through-holes 15 at the same time as forming the second conductive layer 14. Therefore, the opening width must be smaller than twice the thickness of the second conductive layer 14, that is, 40 μm. In this case, in order to close the through hole 15 and prevent a cavity from being formed inside the through hole 15, It is preferable to make only one of the first surface 11a and the second surface 11b of the through-hole 15 smaller than 40 μm. By closing the through-hole 15 in this way, it is possible to provide, for example, a via in the closed portion. In addition, it is possible to stack wirings by using the insulating film, and it is possible to form a gap between the first surface 11a and the second surface 11b. This can prevent the flow of liquid.

[0030] However, as mentioned above, if the thickness of the substrate 11 is, for example, 1000 μm, the substrate 11 is not sufficiently Since the thickness of the through hole 15 is so large, it is difficult to reduce the opening width of the through hole 15. It is necessary to adjust the thickness appropriately depending on the thickness of the substrate 11. In this embodiment, the thickness is 400 μm. Since the substrate 11 is made of a material having a thickness of 1000 Å, the opening width of the through-hole 15 is set to 40 μm or less in consideration of processability. When the opening width of the through-hole 15 is small, it is necessary to consider the method of forming the seed layer. For example, when a physical film formation method such as sputtering or vapor deposition is used, the through-hole 1 In some cases, the seed layer cannot be formed deep inside the hole 5 (the central part between the first surface 11a and the second surface 11b). However, by using electroless plating, it is easy to form a seed layer deep inside the through-hole 15. On the other hand, the adhesion to the substrate 11 is lower in electroless plating, and is higher in physical film formation. Sex is high.

[0031] As shown in the figure, the through-hole 15 has an opening width of 1 / 2 mm between the first surface 11a and the second surface 11b. However, other shapes may be used. For example, the first surface 11a and The size of the opening width may vary between the first surface 11b and the second surface 11c, and may have a minimum value, for example. However, it may have a maximum value, or may have a minimum value and a maximum value. The thickness may gradually increase or decrease from the surface 11a to the second surface 11b. good.

[0032] An insulating layer 22 is formed on the first surface 11a side and the second surface 11b side of the substrate 11. In this example, the insulating layer 22 is a layer containing a resin, which is an organic material. For example, the insulating layer 22 is made of polyimide or acrylic. A third conductive layer 24 is disposed in each of the via holes 23. The layer 24 is electrically connected to the second conductive layer 14 disposed at the bottom of the via hole 23. In addition, the structure in which insulating layers and conductive layers are repeatedly stacked can be used to form a multi-layer structure having even more layers. A multi-layer wiring structure may be realized.

[0033] The wiring substrate 10 is electrically connected to the semiconductor chip 90 via the third conductive layer 24. The wiring board 10 is connected to the circuit board 8 via the solder balls 25 and the third conductive layer 24. 0. The semiconductor chip 90 is also connected to the third conductive In this configuration, the wiring board 10 and the first surface 11 of the substrate 11 may be connected to the layer 24. a semiconductor chip 90 disposed on the a side and electrically connected to the second conductive layer 14, and the and a circuit board 80 disposed on the second surface 11b side and electrically connected to the second conductive layer 14. According to the wiring board 10 of this embodiment, a semiconductor chip with a narrow terminal pitch can be mounted. This simplifies mounting the chip 90 on a large circuit board 80. The circuit board 80 may be, for example, , motherboards, etc.

[0034] In this way, a wiring board such as the wiring board 10 can be electrically connected to other elements such as the semiconductor chip 90. The semiconductor chip 90 is connected to the semiconductor device. For example, memory, processor, acceleration sensor, magnetic sensor, filter, amplifier, etc. The semiconductor device may include various functions such as a mobile terminal, an information processing device, and a home appliance. It is installed in various electronic devices.

[0035] [2. Wiring structure] Next, the detailed structure of the wiring 100 will be explained using an enlarged view of the vicinity of the area AX in FIG. do.

[0036] FIG. 3 is an enlarged view of the wiring according to the first embodiment of the present disclosure (an enlarged view of the vicinity of the region AX in FIG. 2). 4 shows the relationship between the first conductive layer and the second conductive layer according to the first embodiment of the present disclosure. The thickness of the first conductive layer 12 is referred to as thickness t1, and the thickness of the second conductive layer 14 is referred to as thickness t2. As described above, the region of the first conductive layer 12 where the second conductive layer 14 is disposed is called the first conductive layer 12. The side surface of the second conductive layer 14 is referred to as a region As1, and the remaining region is referred to as a second region As2. The width of the second conductive layer 14 is inclined so that it widens or narrows as it moves away from the first conductive layer 12. In this case, the first region As1 is a region of the first conductive layer 12 that is in contact with the second conductive layer 14. It is defined as the area where

[0037] The distance from the outer edge of the first region As1 to the outer edge of the second region As2 is referred to as distance d1. The portion where the second conductive layer 14 and the third conductive layer 24 contact each other is called a contact portion CA. The part of the contact area CA that extends outward is called the extension area EA. The distance from the edge to the outer edge of the extension part EA is called distance d2.

[0038] As shown in FIG. 3, the second region As2 of the first conductive layer 12 is formed by the substrate 11 and the insulating layer 22. The substrate 11 and the insulating layer 22 are sandwiched between the second region As2 and the insulating layer 22 in adjacent regions outside the second region As2. Generally, to improve adhesion with organic insulating materials, However, the surface roughness of the first conductive layer 12 and the second conductive layer 13 is preferably large. It is not preferable to increase the surface roughness of the conductive layer 14 because the signals transmitted through the wiring In the case of high frequency signals, the signals are transmitted along the surface of the wiring, so the greater the surface roughness, the more the signal is transmitted. This is because transmission loss is likely to occur. In addition, it is easier to increase the roughness of inorganic insulating materials. It is easy to maintain a low level of chemical bonding with organic insulating materials. On the other hand, the metal that is the conductive layer has a natural oxide film formed on the surface, Since there is a concern that the surface condition may change during the process, careful consideration is required. Keeping the surface clean, controlling the oxide film, or forming an adhesive layer with organic insulating materials to cover the surface It is preferable to provide the second conductive layer at the end of the wiring 100. The first conductive layer 12 is formed without the wiring 14. 0, the stress of the second conductive layer 14 is applied to the second region As2 of the first conductive layer 12. The second region As2 is covered with the insulating layer 22, and the second region As2 is dispersed in the insulating layer 22. The substrate 11 is fixed from the side. The wiring 100 is prevented from peeling off from the substrate 11, and cracks are prevented from occurring in the substrate 11. This can be suppressed.

[0039] At this time, by adopting a structure for the wiring 100 that satisfies at least one of the following conditions: This prevents peeling or cracking, while also improving the electrical integrity of the wiring board 10 as a whole. For example, if the distance d1 is too large, the distance between adjacent wirings Therefore, the second conductive layer 14 may need to be narrowed or may act as a stub structure. The structure of the wiring 100 must satisfy these conditions. The conditions may be satisfied in duplicate, or some of the conditions may not be satisfied. (Condition 1) The distance d1 is equal to or less than the distance d2. (Condition 2) The thickness t1 is smaller than the distance d1. (Condition 3) The thickness t2 is greater than the distance d1.

[0040] The above-described wiring 100 is arranged only on the first surface 11a or the second surface 11b. The present invention is not limited to the case where the present invention is applied only to the wiring 100 having the through electrode, but also to the first conductive layer 12 and The same applies to the second conductive layer 14.

[0041] [3. Method of manufacturing wiring board] Next, a method for manufacturing the wiring board 10 will be described.

[0042] 5 to 9 are diagrams illustrating a method for manufacturing a wiring board according to the first embodiment of the present disclosure. 5 to 9 are cross-sectional views of the part corresponding to FIG. 2 (A1-A2 line cross-section in FIG. 1). First, the first surface 11a and the second surface 11b are shown. The substrate 11 is provided with a through-hole 15 penetrating the first surface 11b and the second surface 11b. For 11, etching processing, laser processing, and a combination of laser processing and etching processing It is formed by machining using abrasives, sandblasting, electrical discharge machining, drilling, etc. As shown in FIG. 5, the first surface 11a, the second surface 11b, and the inside of the through-hole 15 of the substrate 11 are A seed layer 1210 is formed on the side surface 15a by electroless plating.

[0043] As shown in FIG. 6, a resist mask RM is formed on a part of the seed layer 1210. By plating, the portion of the seed layer 1210 exposed from the resist mask RM is introduced. This forms the second conductive layer 14. Thereafter, a resist mask R Remove M.

[0044] As shown in FIG. 7, the second conductive layer 11a is formed on the first surface 11a side and the second surface 11b side of the substrate 11. A resist mask RM is formed to cover the second conductive layer 14. The edge of the resist mask RM is disposed on the outside. The distance to the edge of the block RM corresponds approximately to the distance d1 described above.

[0045] As shown in FIG. 8, the seed layer 1210 exposed from the resist mask RM is etched. After that, the resist mask RM is removed. This separates the individual conductive layers. A wiring 100 having a laminated structure of a first conductive layer 12 and a second conductive layer 14 is formed on a substrate 11. Next, as shown in FIG. 9, insulating layer 2 is applied from the first surface 11a side and the second surface 11b side. At this time, a via hole 23 is formed in the insulating layer 22. The third conductive layer 24 is formed so as to fill the hole 23, thereby forming the structure shown in FIG. It will be realized.

[0046] Second Embodiment The method for manufacturing the wiring 100 is not limited to the above-described method. Explain the law.

[0047] 10 and 11 are diagrams illustrating a method for manufacturing a wiring according to the second embodiment of the present disclosure. FIG. 10 shows a state in which the resist mask RM is removed from the structure shown in FIG. 6 according to the first embodiment. Then, the plating layer 1410 (corresponding to the second conductive layer 14 shown in FIG. 6) is exposed. 12 is a diagram of the vicinity of the wiring 100 when the seed layer 1210 is etched. The etched and separated seed layers 1210 are deposited on the substrate 11 as the first conductive layer 12. In this example, the first conductive layer 12 (seed layer 1210) and the plating layer 1410 are The materials are formed from different materials. The combination of materials is determined by the following criteria for a given etching solution: The etching rate of the plating layer 1410 is higher than the etching rate of the first conductive layer 12. The material combinations used are:

[0048] Next, as shown in FIG. 11, the plating layer 1410 is etched with the etching solution. A part of the exposed portion of the plating layer 1410 is etched by wet etching. Here, the plating layer 1410 has an upper surface and a side surface that are not in contact with the first conductive layer 12. Therefore, the plating layer 1410 is etched from the top and sides. At this time, the first conductive layer 12 is almost As shown in FIG. 11, a part of the first conductive layer 12 is etched away from the second conductive layer 14. The second region As2 of the wiring 100 in the first embodiment is formed. According to this example, unlike the first embodiment, the film thickness of the second conductive layer 14 is slightly On the other hand, the size of the second region As2 is reduced by the resist mask RM It can be controlled by wet etching time, regardless of alignment accuracy during formation. As a result, the size of the second region As2 can be controlled with high precision.

[0049] <Third embodiment> In the third embodiment, a structure similar to that of the first embodiment is adopted in the through electrode portion. On the other hand, an example will be described in which wiring is arranged not on the substrate 11 but on a structure corresponding to the insulating layer 22. .

[0050] FIG. 12 is a schematic cross-sectional view showing details of the structure of the wiring according to the third embodiment of the present disclosure. In the first conductive layer 12A constituting the conductive electrode, the first region As1 is a, the first surface 11a and the second surface 11b are disposed across the second region As2, and the second region As3 is disposed across the first surface 11a and the second surface 11b. The second surface 11a and the second surface 11b are arranged in the same configuration as in the first embodiment. The insulating layer 22A covering the region As2 is made of an organic insulating material and has an opening with a diameter larger than that of the through-hole 15. In the portion where the opening 225A is arranged, the first conductive layer 12A is The second conductive layer 14A is formed on the exposed portion of the first conductive layer 12A. Therefore, this portion corresponds to the first region As1.

[0051] The fourth conductive layer 16A is disposed between the second conductive layer 14A and the insulating layer 22A. The fourth conductive layer 16A corresponds to a seed layer when the second conductive layer 14A is formed by electrolytic plating. In this example, a fourth conductive layer 16A is provided between the first conductive layer 12A and the second conductive layer 14A. is not arranged, but may be arranged.

[0052] As in the first embodiment, the insulating layer 22 in the first embodiment is further formed on the second conductive layer 14A. and a third conductive layer 14A connected to the second conductive layer 14B through a via hole 23 formed in the insulating layer 22. 3. A conductive layer 24 is disposed thereon.

[0053] With this structure, the through electrode portion is formed by the substrate 11, the first conductive layer 12A, the second conductive layer The positional relationship between the insulating layer 14A and the insulating layer 22A is the same as that in the first embodiment. The lines are arranged on the insulating layer 22A. When a pattern with short wiring intervals is adopted, In this case, since it is not desirable to provide the second region As2, the insulating layer 22A is used as a stress buffer. By using it as a shock absorber, it is possible to use wiring without the second region As2. For example, when wiring is provided on the surface of the substrate to connect with the through electrodes, the first wiring between adjacent wirings is When a pattern with a short distance between the wiring that connects the two areas As2 and may cause a short circuit is used, Therefore, it is not desirable to provide the second region As2 on the insulating layer 22A. By forming the second region As2, the second region As3 can be used as a stress buffer layer. Lines can also be used.

[0054] In addition, in the through electrode portion, the expansion or contraction of the substrate 11 due to the difference in the thermal expansion coefficient Since this occurs not only in the surface direction of the through electrode 11 but also in the thickness direction, stress is likely to occur. In the case of a laminated structure, peeling and cracking are likely to occur, but by adopting this structure, peeling and cracking can be prevented. It is also possible to suppress the occurrence of cracks.

[0055] 13 to 15 are diagrams illustrating a method for manufacturing a wiring board according to the third embodiment of the present disclosure. 13 to 15 show the cross-sectional shapes of the parts corresponding to FIG. First, a metal plate having a first surface 11a and a second surface 11b is formed. As shown in FIG. 13, a substrate 11 having a through hole 15 is prepared. a, the second surface 11b, and the inner surface 15a of the through hole 15 by electroless plating. A conductive layer is formed and processed into a desired pattern to form the first conductive layer 12A.

[0056] Next, as shown in FIG. 14, on the first surface 11a side and the second surface 11b side of the substrate 11, Then, an organic insulating material is applied to cover the end portion (corresponding to the second region As2) of the first conductive layer 12A. At this time, the insulating layer 22A is provided with a hole having a diameter larger than that of the through hole 15. An opening 225A is formed.

[0057] Next, as shown in Figure 15, the film is formed by sputtering, vapor deposition, electroless plating, etc. A seed layer 1610A is formed by this, and then a resist mask RM is formed. A seed layer 1610A is formed on the surface of the edge layer 22A. Then, as in the first embodiment, The second conductive layer 14A is formed by electrolytic plating, and the resist mask RM is removed. After removing the seed layer 1610A, forming the insulating layer 22, and forming the third conductive layer 24, , the configuration shown in FIG. 12 is realized.

[0058] <Fourth embodiment> In the fourth embodiment, the second region As2 in the third embodiment is formed on the inner surface 15a of the through hole 15. An example of the arrangement above will be described.

[0059] FIG. 16 is a schematic cross-sectional view showing details of the structure of the wiring according to the fourth embodiment of the present disclosure. The first conductive layer 12B constituting the conductive electrode is arranged in a strip shape around the inside of the through hole 15. In the first conductive layer 12B, the first region As1 and the second region As2 are formed by the through-hole 1. 5 and does not extend to the first surface 11a and the second surface 11b. The insulating layer 22B covering the second region As2 is made of an organic insulating material. , are arranged to cover the ends of the second regions As2 of the first conductive layer 12B, and the two second regions As A strip-shaped opening 225B is arranged around the inside of the through hole 15 between the two. In the portion where the opening 225B is arranged, the first conductive layer 12B is exposed. Since the second conductive layer 14B is formed on the exposed portion of the first conductive layer 12B, that portion It should be noted that even with this configuration, the first region As1 corresponds to the second region As2. In other words, the edge of the first conductive layer 12B is surrounded by the region As2. The first area As1 is not arranged in the portion.

[0060] The fourth conductive layer 16B is disposed between the second conductive layer 14B and the insulating layer 22B. The fourth conductive layer 16B corresponds to a seed layer when the second conductive layer 14B is formed by electrolytic plating. In this example, a fourth conductive layer 16B is provided between the first conductive layer 12B and the second conductive layer 14B. is not arranged, but may be arranged.

[0061] As in the first embodiment, the insulating layer 22 in the first embodiment is further formed on the second conductive layer 14B. and a third conductive layer 14B connected to the second conductive layer 14B through a via hole 23 formed in the insulating layer 22. 3. A conductive layer 24 is disposed thereon.

[0062] With this structure, the through electrode portion is formed by the substrate 11, the first conductive layer 12B, the second conductive layer Even if the positional relationship between the insulating layer 14B and the insulating layer 22B is inside the through-hole 15, the same as in the first embodiment is true. The other wirings are arranged on the insulating layer 22B. When a pattern is used, it is not desirable to provide the second region As2. By using such an insulating layer 22B as a stress buffer layer, it is possible to form a wiring without providing the second region As2. For example, when wiring is provided on the surface of the substrate to connect with the through electrodes, In addition, the second area As2 of adjacent wirings is connected to each other, and there is a risk of short circuiting. When a turn is used, it is not desirable to provide the second region As2. By forming wiring on the insulating layer 22B, the insulating layer 22B can be used as a stress buffer layer. It is also possible to use wiring that does not have the two regions As2.

[0063] In addition, in the through electrode portion, the expansion or contraction of the substrate 11 due to the difference in the thermal expansion coefficient Since this occurs not only in the surface direction of the through electrode 11 but also in the thickness direction, stress is likely to occur. In the case of a laminated structure, peeling and cracking are likely to occur, but by adopting this structure, peeling and cracking can be prevented. It is also possible to suppress the occurrence of cracks.

[0064] 17 to 19 are diagrams illustrating a method for manufacturing a wiring board according to a fourth embodiment of the present disclosure. 17 to 19 each show a cross-sectional shape of a portion corresponding to FIG. First, a metal plate having a first surface 11a and a second surface 11b is formed. As shown in FIG. 17, a substrate 11 having a through hole 15 is prepared. A resist mask RM is formed on the a side and the second surface 11b side. The resist mask RM is formed so as to penetrate into a part of the inside. The amount of input is determined by the size of the opening diameter of the portion of the resist mask RM corresponding to the through hole 15, the resist The center of the inner surface 15a of the through-hole 15 is Not covered by the rhist mask RM.

[0065] Next, a first conductive layer 12B, which serves as a seed layer, is formed by electroless plating. The electroless plating process uses conditions that make it easier to form a layer on an inorganic material than on an organic material. As a result, as shown in FIG. 18, the portion of the inner surface 15a exposed from the resist mask RM After that, the resist mask RM is removed, and the first conductive layer 12B is formed as shown in FIG. As shown in the figure, inside the through-hole 15, the end of the first conductive layer 12B (relative to the second region As2) An insulating layer 22B made of an organic insulating material is formed so as to cover the insulating layer 22B. The processing conditions are set so that the penetration amount into 15 is greater than when forming the resist mask RM. This allows for such a structure to be realized.

[0066] The subsequent steps are the same as those described in the third embodiment with reference to FIG. That is, the insulating layer is formed by electroless plating under conditions that make it easier to form on organic materials than on inorganic materials. A seed layer is formed on the edge layer 22B, and then a resist mask RM is formed. The second conductive layer 14B is formed by plating, and the resist mask RM is removed. After removing the seed layer, forming the insulating layer 22, and forming the third conductive layer 24, the structure shown in FIG. The configuration is realized.

[0067] Fifth Embodiment In the fifth embodiment, an example in which a structure similar to that of the fourth embodiment is manufactured by a different method will be described. I will explain.

[0068] 20 to 23 are diagrams illustrating a method for manufacturing a wiring board according to the fifth embodiment of the present disclosure. 20 to 23 show the cross-sectional shapes of the parts corresponding to FIG. First, a metal plate having a first surface 11a and a second surface 11b is formed. As shown in FIG. 20, a substrate 11 having a through hole 15 is prepared. A resist layer 1210B is formed on the first surface 11a side and the second surface 11b side of the substrate 11. The resist mask RM is formed in the same manner as in the fourth embodiment. The fifth embodiment differs from the fourth embodiment in that a seed layer 1210B is formed before that.

[0069] Next, as shown in FIG. 21, the resist layer of the seed layer 1210B is removed by electrolytic plating. A plating layer 1215B is formed on the portion exposed from the photomask RM. As shown in the figure, the resist mask RM is removed, and the seed layer 1215B is formed using the plating layer 1215B as a mask. 210B is etched to form a seed layer 1210B, as shown in FIG. The first conductive layer 12B is formed by laminating the first conductive layer 1215B and the second conductive layer 1215B. This is the same as the process from FIG. 19 onwards in the fourth embodiment.

[0070] Sixth Embodiment In the above-described embodiment, the wiring 100 is formed by laminating the first conductive layer 12 and the second conductive layer 14. In the sixth embodiment, a structure similar to the wiring 100 is realized by using an integral layer. An example will be explained.

[0071] 24 and 25 are diagrams illustrating a method for manufacturing a wiring according to a sixth embodiment of the present disclosure. First, as shown in FIG. 24, a conductive layer 1010C is formed on the substrate 11, and then a resist is formed on the conductive layer 1010C. A resist mask RM is formed to cover a part of the conductive layer 1010C. The part corresponding to the first region As1 corresponds to the second region As2. Then, the portion of the conductive layer 1010C exposed from the resist mask RM is etched. At this time, it is preferable to use highly anisotropic etching. In this way, the portion corresponding to the first region As1 and the second region As2 that is thinner than the first region As1 is At this time, the wiring 100C having the length relationship shown in FIGS. In this way, even if the wiring is formed in one layer, it is possible to form it in two layers. By adopting a structure similar to that in the first embodiment, the same effect as the wiring structure in the first embodiment can be obtained. can be obtained.

[0072] <Modification> The present disclosure is not limited to the above-described embodiments, and includes various other modified examples. For example, the above-described embodiments have been described in detail to clearly explain the present disclosure. The present invention is not limited to those having all the configurations described above. A part of the configuration of an embodiment may be replaced with a configuration of another embodiment. It is also possible to add the configuration of another embodiment to the configuration of the embodiment. It is possible to add, remove, or replace other components in the parts. The modified example of the first embodiment will be explained below. This can also be applied as an example.

[0073] (1) The material of the second conductive layer 14 is not limited to Cu, but may be gold (Au), silver (Ag), copper (Cu), Iron (Fe), Nickel (Ni), Platinum (Pt), Palladium (Pd), Ruthenium (Ru The conductive material may include tungsten (W) or other conductive materials.

[0074] (2) Various methods can be used to form patterns of the conductive layers such as the third conductive layer 24. For example, The forming methods include semi-additive, full-additive, subtractive, and clumping. A thin method or a dual damascene method may also be employed.

[0075] (3) The above-described substrate 11 has a structure in which at least the inorganic insulating material is exposed on the surface. However, the insulating material may have a structure in which the organic insulating material is exposed on the surface. The structure of the first embodiment is adopted for the wiring arranged on the substrate, which improves adhesion. On the other hand, in wiring arranged on organic insulating materials, inorganic insulating materials are Although problems such as adhesion are less likely to occur than with wiring arranged on a substrate, the same structure as the first embodiment is used. Therefore, if this structure is not adopted, the contact area will increase. This means that the adhesion is improved compared to

[0076] [Example (simulation results)] In order to verify the effect of the structure of the wiring 100 of the present disclosure, a transmission The transmission characteristics were confirmed. The wiring structure was a microstrip structure, and the wiring length was 1.0 m. The wiring width corresponding to the first region As1 was set to 20 μm.

[0077] Considering the characteristics of the wiring 100 of the present disclosure, the thickness t1 must be smaller than the distance d1. Therefore, the thickness of the wiring is set to 0.5 μm for the first layer (corresponding to the first conductive layer 12) and 0.5 μm for the second layer (corresponding to the second conductive layer 13). The distance d1 was used as a variable and four values ​​were substituted. The S-parameters (S11, S21) were compared with the distance d1 (four values). The values ​​to be substituted are 0.0 μm, 1.0 μm, 2.0 μm, and 5.0 μm, and 1.0 μ m, 2.0 μm, and 5.0 μm correspond to the results of the present invention, and 0.0 μm corresponds to the results of the prior art.

[0078] The transmission characteristics to be simulated are S parameters, and here, S11 (terminal 1 reflection loss: reflection characteristics) and S21 (insertion loss from terminal 1 to terminal 2: transmission characteristics) Here, these characteristics were compared using the operating frequency as a variable. When giving representative examples, we compared the characteristics at an operating frequency of 20 GHz.

[0079] Briefly, the embodiments disclosed herein assume a microstrip structure, The distance d1 and the operating frequency are applied as two variables, and the S parameter S11 at this time is This is the result of comparing S21. The analysis results based on the above are shown below.

[0080] Figure 26 shows the results of a simulation of the operating frequency dependency of the reflection characteristic (S11). As shown in FIG. 26, S11 is roughly consistent regardless of the value of the distance d1. , S11 is almost independent of the distance d1.

[0081] Figure 27 shows the simulation results of the operating frequency dependency of the passband characteristic (S21). In S21, compared to S11, it seems that there is a difference depending on the value of the distance d1. Therefore, the results of the prior art and the present invention were compared more closely. First, the operating frequency was 20 GHz. The characteristic value (dB) at the input is converted to gain, which is the ratio of input to output. When the distance d1 is 0.0 μm, the gain is 1.00. The ratio was calculated for distances d1 of 0.1 μm, 0.2 μm, and 0.5 μm. For 2 μm and 0.5 μm, the ratios are 0.995, 0.990, and 0.988, respectively. As described above, the gain does not change significantly depending on the structure of the wiring 100 according to the present disclosure. As described above, even if the structure of the wiring 100 described in the present disclosure is adopted, the distance d1=0 It has been found that the effect on transmission characteristics at high frequencies is minor compared to the conventional 0.0μm structure. Light. [Explanation of symbols]

[0082] 10...Wiring board, 11...Board, 11a...First side, 11b...Second side, 12,12A,12B ...First conductive layer, 14,14A,14B...Second conductive layer, 15...Through hole, 15a...Inner surface, 1 6, 16A, 16B... fourth conductive layer; 22, 22A, 22B... insulating layer; 23... via hole; 24... third conductive layer, 25... solder ball, 80... circuit board, 90... semiconductor chip, 100 ,100C...Wiring, 225,225A,225B...Opening, 1010C...Conductive layer, 121 0...seed layer, 1215B...plating layer, 1410...plating layer, 1610A...seed layer

Claims

1. a substrate including an inorganic insulating material on its surface; a first conductive layer disposed on the inorganic insulating material and having a first region and a second region surrounding the first region; a second conductive layer disposed on the first region of the first conductive layer and having a thickness greater than that of the first conductive layer; an organic insulating layer disposed on the second region of the first conductive layer and on the inorganic insulating material; Including, The wiring substrate, wherein the outer edge of the first region is formed along the outer edge of the second region.

2. The wiring board according to claim 1 , wherein the thickness of the first conductive layer is smaller than the distance from the outer edge of the first region to the outer edge of the second region.

3. 3. The wiring board according to claim 1, wherein the thickness of the second conductive layer is greater than the distance from the outer edge of the first region to the outer edge of the second region.

4. the substrate has a through hole formed therein that penetrates from a first surface to a second surface; the first conductive layer is disposed on an inner surface of the through hole, on the first surface, and on the second surface; 4. The wiring board according to claim 1, wherein the second region is present on both the first surface and the second surface.

5. the substrate has a through hole formed therein that penetrates from a first surface to a second surface; the first conductive layer is disposed on an inner surface of the through hole; The wiring board according to claim 1 , wherein the second region is present on an inner side surface of the through hole.

6. 6. The wiring board according to claim 1, wherein the first conductive layer and the second conductive layer have different physical properties.

7. 7. The wiring board according to claim 1, wherein the first conductive layer and the second conductive layer are made of different materials.

8. A wiring board according to any one of claims 1 to 7; a semiconductor chip electrically connected to the wiring substrate; A semiconductor device comprising:

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