Semiconductor device

Abstract

To provide a semiconductor device in which wire bonding to a gate electrode can be easily performed.SOLUTION: A semiconductor device 20 includes a semiconductor device 1, and further includes an emitter electrode (aluminum electrode 2E) and a gate electrode (aluminum electrode 2G) on the semiconductor device 1. The emitter electrode has a plated portion (Ni plating layer 3E) formed to cover the emitter electrode, and the gate electrode is formed as a non-plated portion made of a sputtered film. The non-plated portion is rectangular in plan view, with three corners of the rectangle being right angles. The plated portion facing the non-plated portion has an R-shape in plan view.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] In power conversion equipment and the like, double-sided cooling modules are used to improve heat dissipation. However, because copper plates or the like are soldered to both sides of the IGBT (Insulated Gate Bipolar Transistor) chips used, the surface of the IGBT also needs to be nickel-plated for soldering.

[0003] Patent Document 1 discloses that "an emitter electrode and a gate electrode are disposed at a distance from each other on the upper surface of a power semiconductor element. The emitter electrode and the gate electrode have a three-layer structure consisting of a 5 μm thick film made primarily of aluminum (Al) deposited by sputtering, for example, a 10 μm thick film made primarily of nickel (Ni) deposited thereon by electroless plating, and a 0.05 μm thick film made primarily of gold (Au) deposited thereon by flash plating. Such emitter electrodes and gate electrodes can provide good bonding with metal sintered bodies." [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2020-43154 A (see paragraph 0013) Summary of the Invention [Problem to be solved by the invention]

[0005] In Patent Document 1, as described above, a film containing nickel (Ni) as a main material is formed on the emitter region and the gate electrode by electroless plating.

[0006] On the other hand, on the surface of the IGBT, bonding of Cu plates etc. is only done in the large emitter region, and the gate region is often bonded by conventional wire bonding. When plating is applied to the gate region (gate electrode), differences in plating film quality (surface gloss, etc.) require new wire bonding conditions to be established and the associated reliability to be confirmed.

[0007] The present invention has been made to solve the above-mentioned problems, and has as its object to provide a semiconductor device in which wire bonding to, for example, a gate electrode can be easily performed. [Means for solving the problem]

[0008] To achieve the above object, the present invention provides a semiconductor device comprising a semiconductor device, and further comprising an emitter electrode and a gate electrode on the semiconductor device, the emitter electrode having a plated portion formed thereon so as to cover the emitter electrode, and the gate electrode having a non-plated portion formed of a sputtered film. Other aspects of the present invention will be described in the embodiments below. [Effects of the Invention]

[0009] According to the present invention, for example, wire bonding can be easily performed in the gate region. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 2 is a top view showing a plated product of the semiconductor device according to the embodiment. [Figure 2] FIG. 2 is a view showing a cross section taken along the line BB′ in FIG. 1 according to the embodiment. [Figure 3] 1 is a cross-sectional view showing the configuration of a double-sided cooling power module according to an embodiment. [Figure 4] FIG. 10 is a top view showing a plated product of a semiconductor device according to a comparative example. [Figure 5] FIG. 5 is a cross-sectional view of a comparative example taken along line AA' in FIG. [Figure 6]FIG. 10 is a cross-sectional view showing the configuration of a double-sided cooled power module of a comparative example. [Figure 7A] FIG. 2 is a diagram showing a state before plating according to the embodiment. [Figure 7B] 10A and 10B are diagrams illustrating a resist-protected state of a gate pad according to an embodiment. [Figure 7C] FIG. 2 is a diagram showing the state after electroless Ni—P plating according to the embodiment. [Figure 7D] FIG. 10 is a diagram showing a state after resist removal according to the embodiment. [Figure 8A] FIG. 10 is a top view showing another plated product of the semiconductor device according to the embodiment. [Figure 8B] 10A and 10B are top views showing other plated products of the semiconductor device according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, modes for carrying out the present invention (hereinafter referred to as "embodiments") will be described with reference to the drawings as appropriate. The following description shows specific examples of the contents of the present invention, and the present invention is not limited to these descriptions. Various changes and modifications can be made by those skilled in the art within the scope of the technical ideas disclosed in this specification. Furthermore, in all drawings used to explain the present invention, parts having the same function are given the same reference numerals, and repeated explanations may be omitted. Note that the following embodiments will be described using an IGBT semiconductor device having a gate function.

[0012] FIG. 1 is a top view showing a plated product of a semiconductor device 20 according to an embodiment. FIG. 2 is a view showing a cross section taken along line B-B' in FIG. 1 according to an embodiment. FIG. 3 is a cross section showing the configuration of a double-sided cooled power module 20M according to an embodiment. To clarify the features of this embodiment, FIG. 4 is a top view showing a plated product of a semiconductor device 30 according to a comparative example. FIG. 5 is a cross section taken along line A-A' in FIG. 4 according to a comparative example. FIG. 6 is a cross section showing the configuration of a double-sided cooled power module 30M according to a comparative example.

[0013] 1 and 2, the top surface of the plated semiconductor device 20 has a Ni plating layer 3E, an aluminum electrode 2G (non-plated portion) that is a gate pad that supplies power to the gate common wiring, and a protective film 7. The surface of the Ni plating layer 3E is an active region where multiple switching elements are formed, and is a region that has a gate common wiring commonly connected to the gates of the multiple switching elements. The periphery of the active region is a termination region, which is protected by the protective film 7.

[0014] The active area (Ni plating layer 3E) is roughly a square with four curvatures at the corners. In the case of FIG. 1, the gate pad is located at the bottom right, so the active area (Ni plating layer 3E) has a recessed shape, and an unplated aluminum electrode 2G is located in that recess. A feature of this embodiment is that the surface of the aluminum electrode 2G (unplated portion) is not Ni-plated.

[0015] The semiconductor device 20 includes a semiconductor device and an emitter electrode (aluminum electrode 2E) and a gate electrode (aluminum electrode 2G) on the semiconductor device. The emitter electrode has a plated portion (Ni plating layer 3E) formed to cover the emitter electrode, and the gate electrode is formed as a non-plated portion made of a sputtered film. That is, the non-plated portion is made of a sputtered film formed by sputtering. The non-plated portion of the aluminum electrode 2G is rectangular in plan view, and three corners of the rectangle are right-angled.

[0016] 1, the upper left, upper right, and lower left corners of the Ni plating layer 3E are configured as curved portions R having a predetermined curvature. In addition, the Ni plating layer 3E also has a curved portion R in the portion (lower right portion) that contacts the aluminum electrode 2G.

[0017] When the semiconductor device 20 is viewed from above, the corners of the Ni plating layer 3 (Ni plating layer 3E) have a radius of curvature (R-shape) in order to reduce the incidence of cracks. Furthermore, the plated portion facing the non-plated portion also has a R-shape when viewed from above. In other words, since the aluminum electrode 2G does not have a Ni plating layer, it is not necessary to provide the corners with a curved portion R having an appropriate radius of curvature. Modifications will be described with reference to FIGS. 8A and 8B.

[0018] Additionally, as mentioned above, the reason for providing the curvature R at each corner of the Ni plating layer 3E is to prevent cracks in the Ni plating layer 3E. Meanwhile, in FIG. 1, the aluminum electrode 2G (non-plated portion) is rectangular (approximately rectangular), and each of the upper right, lower left, and lower right corners, excluding the upper left corner, is configured as a right-angled portion C. This is because, since the aluminum electrode 2G is a non-plated portion, there is no need to worry about plating cracks. By configuring the corners as right-angled portions C in this way, there is an advantage that the area of ​​the aluminum electrode 2G can be increased compared to when the corners are curved (when the corners are chamfered). It should be noted that the term "rectangle" includes rectangles and squares.

[0019] FIG. 2 shows a cross section taken along the line B-B' in FIG. 1. The semiconductor device 20 includes a semiconductor substrate 1 (semiconductor device) made of Si. The semiconductor substrate 1 has, on its front surface (upper layer side in FIG. 2), an aluminum electrode 2E (emitter electrode) and an aluminum electrode 2G (gate electrode), which are films primarily made of aluminum (Al) and formed by, for example, a sputtering method. The aluminum electrode 2E also has, on its front surface, a Ni plating layer 3E formed by electroless plating. The aluminum electrodes 2E and 2G are insulated from each other by an oxide film 6, which is covered with a protective film 7 made of polyimide or the like. The protective film 7 protects the ends of the aluminum electrode 2E, the Ni plating layer 3E, and the aluminum electrode 2G.

[0020] The semiconductor substrate 1 has an aluminum electrode 11 (collector electrode) formed by sputtering, for example, on the surface opposite to the front surface, and a Ni plating layer 12 formed by electroless plating below the aluminum electrode 11.

[0021] Here, Ni plating includes Ni-P (nickel-phosphorus) plating, Ni-P / Pd / Au plating, Ni-P / Au plating, etc. Aluminum, Ti-Al, etc. are used to produce aluminum electrodes.

[0022] Figure 3 shows the configuration of a double-sided cooled power module 20M using the semiconductor device 20 of Figure 2. In the double-sided cooled power module 20M, a lead frame 9 is provided on a Ni plating layer 3E via solder 8. Furthermore, a bonding wire 10 is attached to an aluminum electrode 2G by ultrasonic bonding or wedge bonding, which is a method of bonding by ultrasonic bonding. Furthermore, a terminal plate (not shown) is attached below the Ni plating layer 12 via solder 13. The semiconductor device 20 is double-sided cooled via the lead frame 9 and the terminal plate.

[0023] When the lead frame 9 is used for a power device, the lead frame 9 is required to have not only electrical connection for a power package used under high power but also high heat dissipation properties.

[0024] (Comparative Example) A semiconductor device 30 of the comparative example will be described with reference to Figures 4 to 6. Descriptions of components similar to those in Figures 1 to 3 will be omitted.

[0025] Fig. 4 shows a top view of a plated product of a semiconductor device 300 of a comparative example. As shown in Fig. 4, the top surface of the plated product of the semiconductor device 30 has a Ni plating layer 3E, a Ni plating layer 3G, and a protective film 7. In Fig. 4, compared to Fig. 1, the gate pad portion is made of Ni plating layer 3E. Furthermore, the shape of Ni plating layer 3E is circular to prevent cracks.

[0026] Cracks are likely to occur depending on the type of electroless Ni plating bath and the heat treatment conditions after plating. If cracks occur in the electroless Ni plating film, they can propagate due to changes in temperature and stress, potentially resulting in poor characteristics. Furthermore, if cracks exist in the electroless Ni plating layer of a semiconductor device, when an electrical connection is made to a connection terminal using a bonding layer made of a copper sintered layer, copper can diffuse from the bonding layer to the power semiconductor chip, potentially increasing the element leakage current, degrading the element's withstand voltage, and causing fluctuations in element characteristics.

[0027] 5 shows the A-A' cross section of FIG. 4. The semiconductor device 30 includes a semiconductor substrate 1 made of Si. The semiconductor substrate 1 has, on its front surface (upper layer side in FIG. 2), an aluminum electrode 2E (emitter electrode) and an aluminum electrode 2G (gate electrode) that are films primarily made of aluminum (Al) and formed by, for example, a sputtering method. Furthermore, Ni plating layers 3E and 3G are formed on the aluminum electrodes 2E and 2G by electroless plating.

[0028] Fig. 6 shows the configuration of a double-sided cooled power module 20M using the semiconductor device 30 of Fig. 5. In the double-sided cooled power module 30M, a lead frame 9 is provided on a Ni plating layer 3E via solder 8. In addition, a bonding wire 10 is attached on the Ni plating layer 3G by ultrasonic bonding or wedge bonding, which is a method of bonding by ultrasonic bonding.

[0029] For this reason, as mentioned above, when plating is applied up to the gate region, differences in the plating film quality (surface gloss, etc.) require new wire bonding conditions to be established and the associated reliability to be confirmed. In this embodiment, the problem shown in Figure 6 is solved by Figure 3. In Figure 3, the aluminum electrode 2G in the gate region is formed of a sputtered film as in the conventional case, making it easy to establish wire bonding conditions.

[0030] (Process Flow) The process flow of the semiconductor device 20 will be described with reference to FIGS. 7A to 7D. Fig. 7A is a diagram showing a state before plating according to an embodiment. Fig. 7B is a diagram showing a resist-protected state of a gate pad according to an embodiment. Fig. 7C is a diagram showing a state after electroless Ni-P plating according to an embodiment. Fig. 7D is a diagram showing a state after resist removal according to an embodiment. Figs. 7A to 7D show the areas around the aluminum electrode 2E (emitter electrode) and aluminum electrode 2G (gate electrode) in Fig. 2.

[0031] Step S1: Figure 7A shows the state before plating, in which an aluminum electrode 2E (emitter electrode) and an aluminum electrode 2G (gate electrode) have been formed, which are films made primarily of aluminum (Al) by sputtering. Step S2: FIG. 7B is a diagram showing the resist protection state of the gate pad, where resist 15 is placed on the aluminum electrode 2G to prevent plating from occurring on the aluminum electrode 2G. Step S3: FIG. 7C shows the state after electroless Ni-P plating, in which a Ni plating layer 3E is formed on the aluminum electrode 2E. Step S4: FIG. 7D shows the state after the resist has been removed, and the aluminum electrode 2G appears on the surface due to the removal of the resist 15 in FIG. 7B. Through the above process, the semiconductor device 20 shown in FIG. 1 can be formed.

[0032] The shape of the aluminum electrode 2G (the shape of the non-plated portion) is rectangular in plan view in FIG. 1, and three corners of the rectangle are right angles, but this is not limited to this.

[0033] Fig. 8A is a top view showing another plated product of the semiconductor device 20 according to the embodiment. Fig. 8B is a top view showing another plated product of the semiconductor device 20 according to the embodiment. Figs. 8A and 8B differ from Fig. 1 in the shape of the aluminum electrode 2G.

[0034] In the case of FIG. 8A, the aluminum electrode 2G1 has a rectangular shape in plan view, and three corners of the rectangle are right angles, but one corner is cut off. In the case of FIG. 8B, the aluminum electrode 2G2 has a quadrangular shape in plan view. Even in the case of aluminum electrodes 2G1 and 2G2, the surfaces are non-plated portions, so there is no need to worry about cracks occurring, as there is in plated portions.

[0035] Although this embodiment has been described using an IGBT semiconductor device having a gate function, the present invention can also be applied to other specific devices such as MOSFETs and bipolar transistors. [Explanation of symbols]

[0036] 1. Semiconductor substrate (semiconductor device) 2E Aluminum electrode (emitter electrode) 2G Aluminum electrode (gate electrode, non-plated area, sputtered film) 3E Ni plating layer (emitter electrode) 3G Ni plating layer (gate electrode) 6. Oxide film 7 Protective film 8 Solder 9 Lead Frame 10 Bonding Wire 11 Aluminum electrode (collector electrode) 12 Ni plating layer 13 Solder 15 Resist 20 Semiconductor Devices 30 Semiconductor device (comparison example) C Right angle part (right angle shape) R curvature part (R shape)

Claims

1. A semiconductor device is provided, an emitter electrode and a gate electrode on the semiconductor device; the emitter electrode has a plating portion formed thereon so as to cover the emitter electrode; The gate electrode is formed as a non-plated portion made of a sputtered film. A semiconductor device characterized by:

2. The non-plated portion has a rectangular shape in a plan view, and three corners of the rectangle are right angles.

2. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

3. The non-plated portion is rectangular in plan view.

2. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

4. The plated portion facing the non-plated portion has an R-shape in plan view.

2. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device having a first insulating layer.

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