Semiconductor storage device and control method for semiconductor storage device

Abstract

To provide a semiconductor storage device and a control method for a semiconductor storage device to reduce cycle time when accessing memory cells containing ferroelectric capacitors.SOLUTION: A semiconductor storage device includes: a first memory cell and a second memory cell having ferroelectric capacitors for storing data; a first bit line and a first plate line connected to the first memory cell; a second bit line and a second plate line connected to the second memory cell; a sense amplifier that differentially amplifies data read from the first memory cell to the first bit line by driving the first plate line and data read from the second memory cell to the second bit line by driving the second plate line; a first restore circuit that outputs a level that inverts the logic of the data of the first bit line that is differentially amplified by the sense amplifier to the first plate line; and a second restore circuit that outputs a level that inverts the logic of the data of the second bit line that is differentially amplified by the sense amplifier to the second plate line.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a semiconductor memory device and a method for controlling the semiconductor memory device. [Background technology]

[0002] A semiconductor memory device is known that has a memory cell including a ferroelectric capacitor that functions as a variable capacitance element and can retain data according to the remanent polarization of the ferroelectric capacitor. This type of semiconductor memory device has a bit line pair connected to the memory cell and a dummy cell capacitor, and a sense amplifier that compares and amplifies the voltage appearing on the bit line pair. Connecting a correction capacitor to the bit line pair to correct the reference potential read from the dummy cell capacitor to the bit line improves the data read margin from the memory cell (see, for example, Patent Document 1). Furthermore, when a ferroelectric dummy cell capacitor is used, applying a voltage opposite to the voltage applied during read to the dummy cell capacitor during times other than read can mitigate the imprint effect of the dummy cell capacitor (see, for example, Patent Document 2). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-102793 [Patent Document 2] Japanese Patent Application Laid-Open No. 2011-134383 Summary of the Invention [Problem to be solved by the invention]

[0004] When reading data from a memory cell containing a ferroelectric capacitor, either the data "0" or the data "1" is destroyed by the read operation, and the data before the destruction is restored to the memory cell after the data is read. This causes a problem in that the cycle time when accessing the memory cell is lengthened by the time required for the restore.

[0005] In one aspect, the present invention aims to reduce the cycle time when accessing a memory cell including a ferroelectric capacitor. [Means for solving the problem]

[0006] According to one aspect, a semiconductor memory device includes a first memory cell and a second memory cell each having a ferroelectric capacitor for holding data, a first bit line and a first plate line connected to the first memory cell, a second bit line and a second plate line connected to the second memory cell, a sense amplifier that differentially amplifies data read from the first memory cell to the first bit line by driving the first plate line and data read from the second memory cell to the second bit line by driving the second plate line, a first restore circuit that outputs to the first plate line an inverted level of the logic of the data on the first bit line differentially amplified by the sense amplifier, and a second restore circuit that outputs to the second plate line an inverted level of the logic of the data on the second bit line differentially amplified by the sense amplifier. [Effects of the Invention]

[0007] The cycle time when accessing a memory cell including a ferroelectric capacitor can be shortened. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a block diagram illustrating an example of a semiconductor memory device according to an embodiment. [Figure 2] FIG. 2 is a block diagram showing an example of two circuits of the subarrays of FIG. [Figure 3] 3 is a circuit diagram showing an example of a main part of the sub-array of FIG. 2. FIG. [Figure 4] FIG. 10 is a block diagram showing an example of circuits for two subarrays of another semiconductor memory device. [Figure 5]2A to 2C are explanatory diagrams showing examples of write and read operations of the ferroelectric capacitor of FIG. [Figure 6] 2 is a timing chart showing an example of an access operation of the semiconductor memory device of FIG. 1. [Figure 7] 5 is a timing chart showing a comparison of the access operations of the semiconductor memory devices of FIG. 1 and FIG. 4. [Figure 8] 1. FIG. 4 is a timing chart showing another example of an access operation of the semiconductor memory device of FIG. [Figure 9] FIG. 10 is a block diagram showing an example of a main part of yet another semiconductor memory device. [Figure 10] FIG. 10 is a block diagram showing an example of circuits for two sub-arrays of a semiconductor memory device according to another embodiment. [Figure 11] 11 is a timing chart showing an example of an access operation of the semiconductor memory device having the subarray of FIG. 10. [Figure 12] 11 is an explanatory diagram showing an example of time-dependent changes in the remanent polarization values ​​of the reference cell and the memory cell in FIG. 10. FIG. [Figure 13] 11 is a timing chart showing another example of an access operation of the semiconductor memory device having the subarray of FIG. 10. [Figure 14] FIG. 10 is a block diagram showing an example of circuits for two sub-arrays of a semiconductor memory device according to another embodiment. [Figure 15] FIG. 15 is a block diagram showing an example of elements arranged on the left side of the subarray of FIG. 14. [Figure 16] 15 is a circuit diagram showing an example of a main part on the left side of the subarray in FIG. 14. FIG. [Figure 17] 15 is a circuit diagram showing an example of a main part on the right side of the subarray in FIG. 14. FIG. [Figure 18] 15 is an explanatory diagram showing an example of positions of memory cells and reference cells to be accessed when access operations are successively performed in the semiconductor memory device of FIG. 14. FIG. [Figure 19] 15 is a timing chart showing an example of an access operation of the semiconductor memory device having the subarray of FIG. 14. [Figure 20]FIG. 20 is a timing diagram illustrating an example of various signals used to generate the waveforms shown in FIG. 19. [Figure 21] FIG. 10 is a block diagram showing an example of circuits for two sub-arrays of a semiconductor memory device according to yet another embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments will be described with reference to the drawings.

[0010] FIG. 1 illustrates an example of a semiconductor memory device according to an embodiment. The semiconductor memory device 100 illustrated in FIG. 1 is, for example, a ferroelectric random access memory (FeRAM). The semiconductor memory device 100 is installed as a single memory device in various electronic devices. The semiconductor memory device 100 includes a plurality of subarrays SARY arranged in a matrix along the X and Y directions, a control circuit CNTL, a row decoder RDEC, a read amplifier RA, and a write amplifier WA. For example, each of the plurality of subarrays SARY corresponds to one of 32 data input / output terminals I / O0-I / O31.

[0011] That is, the semiconductor memory device 100 is a parallel memory that outputs data read from 32 sub-arrays SARY from 32 data input / output terminals I / O and writes data received at the 32 data input / output terminals I / O to the 32 sub-arrays SARY.

[0012] The semiconductor memory device 100 may be a serial memory that sequentially outputs data read from 32 sub-arrays SARY from one data input / output terminal I / O and writes 32 pieces of data sequentially received at one data input / output terminal I / O to the 32 sub-arrays SARY. The number of sub-arrays SARY is not limited to 32. The number of data input / output terminals I / O of the semiconductor memory device 100 operating as a parallel memory is not limited to 32.

[0013] Each subarray SARY has a sense amplifier SA and a pair of memory cell arrays MCA arranged on both sides of the sense amplifier SA. Each subarray SARY also has bit line switches BLSW (BLSWL, BLSWR), plate line switches PLSW (PLSWL, PLSWR), and plate line control circuits PLeCNT, PLoCNT. The bit line switches BLSWL, BLSWR, plate line switches PLSWL, PLSWR, and plate line control circuits PLeCNT, PLoCNT will be described in Figure 2 and subsequent figures.

[0014] Each memory cell array MCA has a plurality of memory cells MC connected to word lines WL, bit lines BL, and plate lines PL, respectively. Each memory cell MC has a cell transistor CT and a ferroelectric capacitor FC. For example, the cell transistor CT is an nMOS (Metal Oxide Semiconductor) transistor.

[0015] The gate of the cell transistor CT is connected to a word line WL. One of the source and drain of the cell transistor CT is connected to a bit line BL. The other of the source and drain of the cell transistor CT is connected to a bottom electrode BEL, which is one end of the ferroelectric capacitor FC. The other end of the ferroelectric capacitor FC, the top electrode TEL, is connected to a plate line PL.

[0016] The control circuit CNTL receives an address signal AD and a command signal CMD from outside the semiconductor memory device 100 and controls the overall operation of the semiconductor memory device 100. For example, the command signal CMD includes a chip enable signal / CE, a write enable signal / WE, and an output enable signal / OE. The row decoder RDEC decodes the address signal AD received via the control circuit CNTL and drives the word line WL and plate line PL corresponding to the value of the address signal AD at a predetermined timing.

[0017] When the control circuit CNTL receives a low-level chip enable signal / CE, a high-level write enable signal / WE, and a low-level output enable signal / OE, it recognizes a read command and executes a read operation. In the read operation, data is read from a memory cell MC selected by an address signal AD, amplified by a sense amplifier SA, and output to a data input / output terminal I / O via a read amplifier RA.

[0018] When the control circuit CNTL receives a low-level chip enable signal / CE, a low-level write enable signal / WE, and a high-level output enable signal / OE, it recognizes a write command and executes a write operation. In a write operation, data received at the data input / output terminal I / O is supplied to the sense amplifier SA via the write amplifier WA and written to the memory cell MC selected by the address signal AD. In a write operation, as in a read operation, data is read from the memory cell MC selected by the address signal AD and amplified by the sense amplifier SA. The amplified data is rewritten as write data and written to the memory cell MC.

[0019] For example, the semiconductor memory device 100 is a so-called 2T2C type that stores one bit of data using two memory cells MC. The memory cells MC store data with a logical value of "0" or "1" depending on the polarization state (residual polarization value) of the ferroelectric capacitor FC. The polarization state of the ferroelectric capacitor FC changes depending on the logical value of the write data. The ferroelectric capacitor FC operates as a variable capacitor whose capacitance changes depending on the electrically rewritable polarization state.

[0020] FIG. 2 shows an example of a circuit for two of the subarrays SARY in FIG. 1. The sense amplifier SA, located approximately in the center of each subarray SARY, operates during the activation period of the latch enable signals LEZ and LEX, and differentially amplifies the voltages appearing on the complementary bit lines BL and / BL. Each plate line control circuit PLeCNT has a NAND gate. While the write enable signal WREZe is at a high level, the plate line control circuit PLeCNT inverts the logic level of the bit line BL differentially amplified by the sense amplifier SA and outputs it to the plate line PLe. While the write enable signal WREZe is at a low level, the plate line control circuit PLeCNT outputs a high level to the plate line PLe. The plate line control circuit PLeCNT is an example of either a first restore circuit or a second restore circuit.

[0021] The plate line control circuit PLoCNT inverts the logic level of the bit line / BL differentially amplified by the sense amplifier SA and outputs it to the plate line PLo while the write enable signal WREZo is at a high level. The plate line control circuit PLoCNT outputs a high level to the plate line PLo while the write enable signal WREZo is at a low level. The plate line control circuit PLoCNT is an example of the other of the first restore circuit and the second restore circuit.

[0022] The write enable signals WREZe and WREZo are set to a high level during the period in which data is restored (rewritten) to the memory cells MC during an access operation of the memory cells MC. Note that the memory cells MC, bit line switches BLSW, and plate line switches PLSWL indicated by bold frames represent circuits that operate during the read operation shown in Figure 6. In other subarrays SARY, memory cells MC, bit line switches BLSWL and BLSWR, and plate line switches PLSWL and PLSWR at the same positions as those indicated by bold frames are selected and operate.

[0023] One end of a bit line BL extending in the X direction is connected to a plurality of bit lines BLL (BLL0-BLL3) via a plurality of bit line switches BLSWL. The other end of the bit line BL is connected to a plurality of bit lines BLR (BLR0-BLR3) via a plurality of bit line switches BLSWR. Similarly, one end of a bit line / BL extending in the X direction is connected to a plurality of bit lines / BLL ( / BLL0- / BLL3) via a plurality of bit line switches BLSWL. The other end of the bit line / BL is connected to a plurality of bit lines / BLR ( / BLR0- / BLR3) via a plurality of bit line switches BLSWR. The bit line switch BLSWL is an example of either a first bit line switch or a second bit line switch. The bit line switch BLSWR is an example of the other of the first bit line switch or the second bit line switch.

[0024] One end of the plate line PLe extending in the X direction is connected to a plurality of plate lines PLLe (PLLe0-PLLe3) via a plurality of plate line switches PLSWL. The other end of the plate line PLe is connected to a plurality of plate lines PLRe (PLRe0-PLRe3) via a plurality of plate line switches PLSWR. Similarly, one end of the plate line PLo extending in the X direction is connected to a plurality of plate lines PLLo (PLLo0-PLLo3) via a plurality of plate line switches PLSWL. The other end of the plate line PLo is connected to a plurality of plate lines PLRo (PLRo0-PLRo3) via a plurality of plate line switches PLSWR. The plate line switch PLSWL is an example of either a first plate line switch or a second plate line switch. The plate line switch PLSWR is an example of the other of the first plate line switch or the second plate line switch.

[0025] Here, each plate line PLLe corresponding to each bit line BLL is wired in parallel to each bit line BLL. Each plate line PLLo corresponding to each bit line / BLL is wired in parallel to each bit line / BLL. Each plate line PLRe corresponding to each bit line BLR is wired in parallel to each bit line BLR. Each plate line PLRo corresponding to each bit line / BLR is wired in parallel to each bit line / BLR.

[0026] By wiring the plate lines PLLe, PLLo in parallel to the bit lines BLL, / BLL corresponding to the bit lines BLL, / BLL, data can be restored for each memory cell MC connected to the bit lines BLL, / BLL. Similarly, by wiring the plate lines PLRe, PLRo in parallel to the bit lines BLR, / BLR corresponding to the bit lines BLR, / BLR, data can be restored for each memory cell MC connected to the bit lines BLR, / BLR.

[0027] The bit line switches BLSWL are turned on or off in response to a pair of corresponding bit line selection signals BLSZL (BLSZL0-BLSZL3) and BLSXL (BLSXL0-BLSXL3). The bit line switches BLSWR are turned on or off in response to a pair of corresponding bit line selection signals BLSZR (BLSZR0-BLSZR3) and BLSXR (BLSXR0-BLSXR3).

[0028] For example, two bit line switches BLSW connected to bit lines BLL0 and / BLL0 respectively operate in response to bit line selection signals BLSZL0 and BLSXL0. Two bit line switches BLSW connected to bit lines BLR2 and / BLR2 respectively operate in response to bit line selection signals BLSZR2 and BLSXR2. The bit line selection signals BLSZL, BLSXL, BLSZR, and BLSXR are commonly wired to the subarrays SARY arranged in the Y direction.

[0029] The plate line switches PLSWL are turned on or off in response to a pair of corresponding plate line selection signals PLSZL (PLSZL0-PLSZL3) and PLSXL (PLSXL0-PLSXL3). The plate line switches PLSWR are turned on or off in response to a pair of corresponding plate line selection signals PLSZR (PLSZR0-PLSZR3) and PLSXR (PLSXR0-PLSXR3).

[0030] For example, two plate line switches PLSWL connected to plate lines PLLe0 and PLLo0 operate in response to plate line selection signals PLSZL0 and PLSXL0. Two plate line switches PLSWR connected to plate lines PLRe2 and PLRo2 operate in response to plate line selection signals PLSZR2 and PLSXR2. The plate line selection signals PLSZL, PLSXL, PLSZR, and PLSXR are commonly wired to the subarrays SARY arranged in the Y direction.

[0031] 2, four memory cells MC arranged in the X direction are connected to each pair of adjacently wired bit lines BLL and plate lines PLLe. Four memory cells MC arranged in the X direction are connected to each pair of adjacently wired bit lines / BLL and plate lines PLLo. Four memory cells MC arranged in the X direction are connected to each pair of adjacently wired bit lines BLR and plate lines PLRe. Four memory cells MC arranged in the X direction are connected to each pair of adjacently wired bit lines / BLR and plate lines PLRo.

[0032] The number of memory cells MC arranged on both sides in the X direction is not limited to four. The number of pairs of adjacently wired bit lines BLL ( / BLL) and plate lines PLLe (PLLo) is not limited to four. The number of pairs of adjacently wired bit lines BLR ( / BLR) and plate lines PLRe (PLRo) is not limited to four.

[0033] The memory cells MC arranged in the Y direction are connected to either word lines WLL (WLL0-WLL3) or word lines WLR (WLR0-WLR3) extending in the Y direction. Each word line WLL, WLR is commonly wired to the subarrays SARY arranged in the Y direction. The number of word lines WLL, WLR wired on both sides in the X direction is not limited to four.

[0034] The bit line switches BLSWL connected to the bit lines BLL and / BLL and the bit line switches BLSWR connected to the bit lines BLR and / BLR are turned on exclusively. The plate line switches PLSWL connected to the plate lines PLLe and PLLo and the plate line switches PLSWR connected to the plate lines PLRe and PLRo are turned on exclusively. In addition, the on periods of the bit line switches BLSWL and the plate line switches PLSWL overlap each other, and the on periods of the bit line switches BLSWR and the plate line switches PLSWR overlap each other. This allows data to be read or written by selecting a pair of memory cells MC on one end or the other end in the X direction.

[0035] 2, a memory cell MC connected to a word line WLL0, a bit line BLL0, and a plate line PLLe0 is connected to a bit line BL and a plate line PLe via a bit line switch BLSWL and a plate line switch PLSWL. Similarly, a memory cell MC connected to a word line WLL0, a bit line / BLL0, and a plate line PLLo0 is connected to a bit line / BL and a plate line PLo via a bit line switch BLSWL and a plate line switch PLSWL. Then, complementary data stored in two memory cells MC connected to a sense amplifier SA is differentially amplified by the sense amplifier SA.

[0036] Of the eight memory cells MC connected to each word line WLL, one piece of data is read from two memory cells MC selected by the bit line switch BLSWL and the plate line switch PLSWL (four columns).Furthermore, the sense amplifier SA reads one piece of data from two memory cells MC selected by the bit line switch BLSWR and the plate line switch PLSWR (four columns) of the eight memory cells MC connected to each word line WLR.

[0037] The sense amplifiers SA and the plate line control circuits PLeCNT and PLoCNT are provided in common to a plurality of bit lines BLL and BLR, which reduces the number of sense amplifiers SA and plate line control circuits PLeCNT and PLoCNT mounted in the subarray SARY and prevents an increase in the layout size of the subarray SARY.

[0038] Fig. 3 shows an example of a main part of the subarray SARY in Fig. 2. Explanation of the elements explained in Fig. 2 will be omitted. Fig. 3 shows an area including the bit lines BLL0-BLL3, plate lines PLLe0-PLLe3, word lines WLL0-WLL2, and sense amplifiers SA in Fig. 2.

[0039] The sense amplifier SA has a CMOS (Complementary Metal Oxide Semiconductor) inverter whose input is connected to the bit line BL and whose output is connected to the bit line / BL, and a CMOS inverter whose input is connected to the bit line / BL and whose output is connected to the bit line BL. The source of the p-channel MOS (Metal Oxide Semiconductor) transistor of each CMOS inverter is connected to the power supply line VDD via a p-channel MOS transistor whose gate receives the latch enable signal LEX. The source of the n-channel MOS transistor of each CMOS inverter is connected to the ground line VSS via an n-channel MOS transistor whose gate receives the latch enable signal LEZ.

[0040] In the sense amplifier SA, the node of the bit line BL connected to the input of the plate line control circuit PLeCNT is an example of either the first node or the second node. In the sense amplifier SA, the node of the bit line / BL connected to the input of the plate line control circuit PLoCNT is an example of the other of the first node or the second node. By transmitting the logic level of the data differentially amplified by the sense amplifier SA to the plate line control circuits PLeCNT and PLoCNT without passing through other circuits, it is possible to prevent the period required to restore data to the memory cell MC from becoming long.

[0041] The bit line switch BLSWL has a CMOS transmission gate TG and an n-channel MOS transistor NM arranged between each bit line BLL and bit line BL. The circuit configuration of the plate line switch PLSWL and the bit line switches BLSWR and PLSWLR shown in FIG. 2 is the same as the circuit configuration of the bit line switch BLSWL.

[0042] The CMOS transmission gate TG of the bit line switch BLSWL is turned on when the bit line selection signals BLSZL and BLSXL are at a high level and a low level, respectively, and is turned off when the bit line selection signals BLSZL and BLSXL are at a low level and a high level, respectively. The n-channel MOS transistor NM of the bit line switch BLSWL receives the bit line selection signal BLSXL at its gate, has a drain connected to the bit line BLL, and has a source connected to the ground line VSS. The n-channel MOS transistor NM of the bit line switch BLSWL is turned on when the bit line selection signal BLSXL is at a high level, and is turned off when the bit line selection signal BLSXL is at a low level.

[0043] The CMOS transmission gate TG of the plate line switch PLSWL is turned on when the plate line selection signals PLSZL and PLSXL are at high and low levels, respectively, and is turned off when the plate line selection signals PLSZL and PLSXL are at low and high levels, respectively. The n-channel MOS transistor NM of the plate line switch PLSWL receives the plate line selection signal PLSXL at its gate, has its drain connected to the plate line PLLe, and its source connected to the ground line VSS. The n-channel MOS transistor NM of the plate line switch PLSWL is turned on when the plate line selection signal PLSXL is at high level, and is turned off when the plate line selection signal PLSXL is at low level.

[0044] FIG. 4 shows an example of a circuit for two subarrays of another semiconductor memory device. The semiconductor memory device 200 shown in FIG. 4 is a 2T2C type. Each subarray SARY corresponds to four data input / output terminals I / O0-I / O3 and is assigned one column. Since four data corresponding to the four data input / output terminals I / O are read / written in each subarray SARY, each subarray SARY has four sense amplifiers SA. The four sense amplifiers SA are connected to corresponding bit line pairs BL (BL0-BL3), / BL ( / BL0- / BL3).

[0045] Each bit line BL, / BL is connected to a corresponding bit line BLL (BLL0-BLL3), / BLL ( / BLL0- / BLL3) via a bit line switch BLSWL. Also, each bit line BL, / BL is connected to a corresponding bit line BLR (BLR0-BLR3), / BLR ( / BLR0- / BLR3) via a bit line switch BLSWR. Note that the memory cells MC and bit line switches BLSWL enclosed in bold frames represent circuits that operate during the read operation of the semiconductor memory device 200 shown in FIG. 7.

[0046] Figure 5 shows an example of the write operation and read operation of the ferroelectric capacitor FC of Figure 1. In the "0" write operation of the ferroelectric capacitor FC, the word line WL is set to a high level SH higher than the power supply voltage VDD, the plate line PL is set to a high level H (=VDD), and the bit line BL is set to a low level L (VSS).

[0047] As a result, the remanent polarization value of the ferroelectric capacitor FC when no voltage is applied between the upper electrode TEL and the lower electrode BEL after the "0" write operation is set to a higher state than when "1" is stored, and the ferroelectric capacitor FC stores "0." Note that in the "0" write operation of the ferroelectric capacitor FC, the low level of the bit line BL only needs to be transmitted to the lower electrode BEL, so the word line WL may be set to the power supply voltage VDD.

[0048] In a "1" write operation for the ferroelectric capacitor FC, the word line WL is set to a high level SH higher than the power supply voltage VDD, the plate line PL is set to a low level L (=VSS), and the bit line BL is set to a high level H (VDD). As a result, the remanent polarization value of the ferroelectric capacitor FC when no voltage is applied between the upper electrode TEL and the lower electrode BEL after the "1" write operation is set to a lower state than when "0" was stored, and the ferroelectric capacitor FC stores "1".

[0049] In a read operation of the ferroelectric capacitor FC, the word line WL is set to a high level (VDD), the bit line BL is set to a floating state, and the plate line PL is set to a high level L (=VDD). A voltage corresponding to the remanent polarization value of the ferroelectric capacitor FC is generated on the bit line BL.

[0050] In a 2T2C type ferroelectric memory, a "0" or a "1" is read out by using a sense amplifier SA to amplify the difference between the voltage of the bit line BL connected to a memory cell MC in which a "0" is stored and the voltage of the bit line BL connected to a memory cell MC in which a "1" is stored. In a 1T1C type ferroelectric memory, a "0" or a "1" is read out by using a sense amplifier SA to amplify the difference between the voltage of the bit line BL connected to a memory cell MC in which a "0" or a "1" is stored and the voltage of the bit line BL connected to a reference cell. A remanent polarization value intermediate between the remanent polarization value corresponding to a "0" and the remanent polarization value corresponding to a "1" is pre-stored in the reference cell.

[0051] Fig. 6 shows an example of an access operation of the semiconductor memory device 100 of Fig. 1. In Fig. 6, a predetermined address signal AD (not shown) is supplied, and a read operation is started when the chip enable signal / CE changes to low level while the write enable signal / WE is at high level H (Fig. 6(a)).

[0052] The address signal AD (not shown) is decoded, the bit line selection signal BLSZL0 corresponding to the address signal AD is set to a high level, and the word line WLL2 corresponding to the address signal AD is set to a high level (=VDD) (FIGS. 6(b) and 6(c)). The bit line selection signal BLSXL0 is set to a level opposite to that of the bit line selection signal BLSZL0. Note that while the write enable signals WREZe and WREZo are at a low level, the plate lines PLe and PLo are set to a high level (=VDD) due to the high level output from the plate line control circuits PLeCNT and PLoCNT (FIG. 6(d)).

[0053] Next, the plate line selection signal PLSZL0 corresponding to the address signal AD is set to a high level, and the corresponding plate line switch PLSWL is turned on (FIG. 6(e)). The high levels of the plate lines PLe and PLo are transmitted to the plate lines PLLe0 and PLLo0 via the plate line switches PLSWL that have been turned on, respectively, and the plate lines PLLe0 and PLLo0 are set to a high level (=VDD) (FIG. 6(f)). The plate line selection signal PLSXL0 is set to the opposite level to the plate line selection signal PLSZL0.

[0054] When the plate lines PLLe and PLLo are set to high level, data is read from a pair of memory cells MC to bit lines BLL0 and / BLL0. Then, the voltages of the bit lines BLL0 and / BLL0 rise depending on whether the data stored in the memory cells MC is "1" (solid line) or "0" (dotted line) (FIG. 6(g)). The voltages of the bit lines BLL0 and / BLL0 are transmitted to the bit lines BL and / BL, respectively, via the bit line switches BLSWL that are turned on.

[0055] In the following, for simplicity of explanation, it is assumed that data "0" is stored in the memory cell MC connected to bit line BLL0 and plate line PLLe0, and data "1" is stored in the memory cell MC connected to bit line / BLL0 and plate line PLLo0.

[0056] Next, the latch enable signals LEZ and LEX are activated to high and low levels, respectively, and the sense amplifier SA starts operating (Fig. 6(h)). The sense amplifier SA amplifies the voltage difference between the bit lines BL and / BL, and sets the bit line BL to high level ("1") and the bit line / BL to low level ("0") (Fig. 6(i)).

[0057] Next, the word line WLL2 is set to a voltage higher than the power supply voltage VDD (FIG. 6(j)). In addition, the write enable signals WREZe and WREZo are set to a high level, and the plate line control circuits PLeCNT and PLoCNT are activated (FIG. 6(k)). As a result, the plate lines PLe (PLLe) and PLo (PLLo) are set to a voltage level that is the inverse of the voltage levels of the bit lines BLL (BLL0) and / BL ( / BLL0) (FIGS. 6(l) and (m)). For example, the plate line PLLe0 is set to "1" (solid line), and the plate line PLLo0 is set to "0" (dotted line).

[0058] As a result, the bit line BLL0 and plate line PLLe0 connected to the memory cell MC storing data "0" are set to low level ("0") and high level ("1"), respectively, and data "0" is restored to the memory cell MC. If data "1" is stored in the memory cell MC, the bit line / BLL0 and plate line PLLo0 are set to high level ("1") and low level ("0"), respectively, and data "1" is restored to the memory cell MC. As a result, complementary data stored in a pair of memory cells MC can be restored at the same time. This makes it possible to shorten the cycle time during memory access and perform random access at high speed.

[0059] After this, the bit line selection signal BLSZL0 and the bit line selection signal BLSXL0 (not shown) are set to low and high levels, respectively, and the n-channel MOS transistor NM of the bit line switch BLSWL is turned on (FIG. 6(o)). As a result, the bit lines BLL0 and / BLL0 are set to low levels (FIG. 6(p)). Also, the plate line selection signal PLSZL0 and the plate line selection signal PLSXL0 (not shown) are set to low and high levels, respectively, and the n-channel MOS transistor NM of the plate line switch PLSWL is turned on (FIG. 6(q)). As a result, the plate lines PLLe0 and PLLo0 are set to low levels (FIG. 6(r)).

[0060] Then, the word line WLL2 is set to a low level, and the write enable signals WREZe and WREZo are set to a low level (FIGS. 6(s) and (t)). The low level of the write enable signals WREZe and WREZo sets the plate lines PLLe and PLLo to a high level (=VDD) (FIG. 6(u)). The read operation is then completed. The write operation of the semiconductor memory device 100 is similar to the read operation except that a voltage level corresponding to the write data received at the data input / output terminal I / O and its inverted level are applied to the bit lines BL and / BL, respectively. The voltage level corresponding to the write data and its inverted level are applied to the bit lines BL and / BL, respectively, during the "write 0 & write 1" period in which data is restored to the memory cell MC.

[0061] 7 shows a comparison of the access operations of the semiconductor memory devices of FIG. 1 and FIG. 4. In FIG. 7, a read operation is performed in the same manner as in FIG. 6. The read operation of the semiconductor memory device 100 is the same as in FIG. 6. However, the waveform of the plate line PL of the semiconductor memory device 100 shows the waveform of the plate line (e.g., PLLe0) connected to the memory cell MC.

[0062] 7, the symbol STB indicates a standby period, the symbol CRD indicates a cell read period for reading data from the memory cell MC, the symbol SNS indicates a sense period of the sense amplifier SA, the symbol D0-RSTR indicates a restore period for data "0", and the symbol D1-RSTR indicates a restore period for data "1", and the symbol RST indicates a reset period.

[0063] In the semiconductor memory device 100, the restore period D1-RSTR overlaps with the restore period D0-RSTR, whereas in the read operation of the semiconductor memory device 200, the restore period D1-RSTR is performed after the restore period D0-RSTR. Therefore, the cycle time of the read operation of the semiconductor memory device 100 can be shortened by the restore period D1-RSTR compared to the cycle time of the read operation of the semiconductor memory device 200. Note that, similar to the read operation, the cycle time of the write operation of the semiconductor memory device 100 can also be shortened by the restore period D1-RSTR compared to the cycle time of the write operation of the semiconductor memory device 200.

[0064] 8 shows another example of an access operation of the semiconductor memory device 100 of FIG. 1. A read operation is also performed in FIG. 8. However, in FIG. 8, the bit line selection signal BLSZL0, which was activated before the data was amplified by the sense amplifier SA, is temporarily inactivated, the bit line switch BLSWL is turned off, and the bit lines BLL0 and / BLL0 are set to a low level (FIGS. 8(a) and 8(b)). Then, the sense amplifier SA performs an amplification operation with the bit lines BLL0 and / BLL0 disconnected from the sense amplifier SA, thereby performing a read operation (confined sense method).

[0065] In the confined sensing method, the capacitance of the bit lines BLL0, / BLL0 is not visible to the sense amplifier SA, so the amplification operation of the sense amplifier SA can be performed at a higher speed than when the confined sensing method is not adopted.

[0066] 8, the plate line selection signal PLSZL0 is temporarily deactivated to turn off the plate line switch PLSWL, so that the plate lines PLLe0 and PLLo0 are set to a low level during the confinement sensing (FIGS. 8(c) and 8(d)). That is, by the confinement sensing method, both the bit lines BLL0 and / BLL0 and the plate lines PLLe0 and PLLo0 are set to a low level before restoring the data.

[0067] This allows only one of the upper electrode TEL or the lower electrode BEL of the ferroelectric capacitor FC (i.e., only one of the plate line PLL or the bit line BLL) to be changed from low to high when restoring data to the memory cell MC, thereby shortening the restore period compared to when the voltages of both the upper electrode TEL and the lower electrode BEL are changed.

[0068] As described above, in this embodiment, the plate line control circuits PLeCNT and PLoCNT supply the inverted levels of the bit lines BL and / BL to the plate lines PLe and PLo, respectively. This allows the "1" write and "0" write during restore of the memory cell MC to be performed at the same time. As a result, the cycle time during memory access can be shortened, and random access can be performed at high speed.

[0069] By turning off the bit line switch BLSWL before the sense amplifier SA amplifies the data, the capacitance of the bit lines BLL0 and / BLL0 can be made invisible to the sense amplifier SA during amplification by the sense amplifier SA, allowing the amplification operation to be performed at high speed. Furthermore, by turning off the plate line switch PLSWL in synchronization with the turning off of the bit line switch BLSWL, only one of the upper electrode TEL or the lower electrode BEL of the ferroelectric capacitor FC can be changed from low to high during data restore. Therefore, the restore period can be shortened compared to when the voltages of both the upper electrode TEL and the lower electrode BEL are changed.

[0070] By transmitting the logical level of the data differentially amplified by the sense amplifier SA to the plate line control circuits PLeCNT, PLoCNT without passing through other circuits, it is possible to prevent the period for restoring data to the memory cells MC from becoming long. By wiring each of the bit lines BLL, / BLL, BLR, / BLR and each of the plate lines PLLe, PLLo, PLRe, PLRo in parallel, it is possible to restore data for each memory cell MC.

[0071] By providing the sense amplifiers SA and plate line control circuits PLeCNT, PLoCNT in common to multiple bit lines BLL, BLR, the number of sense amplifiers SA and plate line control circuits PLeCNT, PLoCNT mounted in the subarray SARY can be reduced, which in turn prevents the layout size of the subarray SARY from increasing.

[0072] Fig. 9 shows an example of a main part of yet another semiconductor memory device. The semiconductor memory device 300 shown in Fig. 9 is a so-called 1T1C type in which one bit of data is stored in one memory cell MC and a reference cell RMC is used to read data from the memory cell MC. In the following description, it is assumed that the elements shown in Fig. 9 are included in one sub-array SARY.

[0073] The subarray SARY has the same number of memory cells MC as the memory cells MC included in the subarray SARY of Figure 4, and the same number of reference cells RMC as the memory cells MC. By providing the same number of reference cells RMC as the memory cells MC, the number of accesses to each reference cell RMC can be made equal to the number of accesses to the corresponding memory cell MC. This makes it possible to reduce the difference in characteristic fluctuations of the reference cells RMC and the memory cells MC due to the number of accesses.

[0074] The size of the ferroelectric capacitor FC of each reference cell RMC is set larger than the size of the ferroelectric capacitor FC of each memory cell MC. Each reference cell RMC always holds data "0". This allows the remanent polarization value of the ferroelectric capacitor FC of each reference cell RMC to be set midway between the remanent polarization value FC of data "0" of each memory cell MC and the remanent polarization value of data "1".

[0075] 9 is connected to one of the bit lines BLL (BLL0-BLL7), one of the word lines WLL (WLL0-WLL3), and the plate line PLL0. The reference cell RMC arranged on the left side of Fig. 9 is connected to one of the reference bit lines rBLL (rBLL0-rBLL7), one of the word lines WLL (WLL0-WLL3), and the plate line PLL0.

[0076] 9 is connected to one of the bit lines BLR (BLR0-BLR7), one of the word lines WLR (WLR0-WLR3), and the plate line PLR0. The reference cell RMC arranged on the right side of Fig. 9 is connected to one of the reference bit lines rBLR (rBLR0-rBLR7), one of the word lines WLR (WLR0-WLR3), and the plate line PLR0.

[0077] Each bit line BLL is connected to a bit line BL via a bit line switch BLSWL. Each bit line BLR is connected to a bit line BL via a bit line switch BLSWR. The sense amplifier SA is a circuit similar to the sense amplifier SA shown in FIG. 3. The sense amplifier SA is connected to the bit line BL and a reference node rND1. The sense amplifier SA determines the data stored in the memory cell MC to be accessed by amplifying the difference in voltage between the bit line BL and the reference node rND1.

[0078] The reference node rND1 is connected to a reference generation circuit FEFGEN. The reference generation circuit FEFGEN has, for example, a p-channel MOS transistor WP and a resistance element R1 connected in series between a power supply line VDD and a ground line VSS. The p-channel MOS transistor WP has a gate connected to a common gate line CGT, a source connected to the power supply line VDD, and a drain connected to the sense amplifier SA via the reference node rND1.

[0079] Each reference bit line rBLL is connected to a reference bit line rBL via a bit line switch BLSWL. Each reference bit line rBLR is connected to a reference bit line rBL via a bit line switch BLSWR. The reference bit line rBL is connected to a reference copy circuit REFCPY.

[0080] The reference copy circuit REFCPY includes, for example, a p-channel MOS transistor rWP, a resistor element R0, and a preamplifier AMP connected in series between a power supply line VDD and a ground line VSS. The p-channel MOS transistor rWP has a gate connected to a common gate line CGT and the output of the preamplifier AMP, a source connected to the power supply line VDD, and a drain connected to the + input of the preamplifier AMP via a reference node rND0.

[0081] The preamplifier AMP outputs a control voltage to the common gate line CGT and the gate of the p-channel MOS transistor rWP according to the difference between the voltage of the reference bit line rBL received at its - input and the voltage of the reference node rND0. The p-channel MOS transistors WP and rWP, whose gates are connected to the common gate line CGT, and the resistive elements R1 and R0 function as a current mirror circuit, copying the current i flowing through the resistive element R0 to the current i flowing through the resistive element R1. This allows the reference voltage read from one of the multiple reference cells RMC onto the reference bit line rBL to be copied to the reference node rND1. The sense amplifier SA can then determine the logical value of the data stored in the memory cell MC by amplifying the difference between the voltage value of the data read from the memory cell MC onto the bit line BL and the voltage value (reference level) of the reference node rND1.

[0082] 9, in order to increase the accuracy of the reference level generation, the preamplifier AMP must be designed with high precision, and feedback control by the preamplifier AMP is necessary. This makes it time-consuming to generate the reference level, which hinders the speed-up of random access of the semiconductor memory device 300. Furthermore, if the semiconductor memory device 300 is equipped with the same number of reference cells RMC as memory cells MC, the chip area of ​​the semiconductor memory device 300 increases, which increases costs.

[0083] 10 shows an example of a circuit for two subarrays of a semiconductor memory device according to another embodiment. Detailed descriptions of elements similar to those in FIGS. 2 and 3 will be omitted. For example, the semiconductor memory device 102 shown in FIG. 10 includes multiple subarrays SARY, a control circuit CNTL, a row decoder RDEC, a read amplifier RA, and a write amplifier WA, similar to the semiconductor memory device 100 shown in FIG. 1. The semiconductor memory device 102 is mounted as a single memory device in various electronic devices.

[0084] The semiconductor memory device 102 shown in FIG. 10 is a 1T1C type. The semiconductor memory device 102 has reference cells RMC arranged in a row along the Y direction on the sense amplifier SA side of the memory cell MC regions arranged on both the left and right sides of FIG. 10. As in FIG. 9, each reference cell RMC always holds data "0." In the 1T1C type semiconductor memory device 102, each subarray SARY is assigned a single bit line BLL (BLL0-BLL7) and a single bit line BLR (BLR0-BLR7) instead of complementary bit lines. Furthermore, each subarray SARY is assigned a single plate line PLL (PLL0-PLL7) and a single plate line PLR ​​(PLR0-PLR7) instead of a pair of plate lines.

[0085] In the 1T1C type, when a memory cell MC is accessed, one memory cell MC and one reference cell RMC are selected for each subarray SARY. Therefore, the eight bit line switches BLSWL on the left side of the sense amplifier SA operate individually in response to eight pairs of bit line selection signals BLSZL0-BLSZL7 and BLSXL0-BLSXL7. The eight bit line switches BLSWR on the right side of the sense amplifier SA operate individually in response to eight pairs of bit line selection signals BLSZR0-BLSZR7 and BLSXR0-BLSXR7.

[0086] For example, when a memory cell MC indicated by a bold frame on the left side of Fig. 10 is accessed, a reference cell RMC indicated by a bold frame on the right side of Fig. 10 is selected. That is, when a certain memory cell MC is accessed, a reference cell RMC located on the opposite side of the sense amplifier SA from the memory cell MC to be accessed is selected.

[0087] The bit line BLL0 connected to the memory cell MC to be accessed is connected to the bit line BL via a bit line switch BLSWL (bold frame) that is turned on by activation of the bit line selection signals BLSZL0 and BLSXL0. The plate line PLL0 connected to the memory cell MC to be accessed is connected to the plate line PLe via a plate line switch PLSWL (bold frame) that is turned on by activation of the plate line selection signals PLSZL0 and PLSXL0.

[0088] The bit line BLR4 connected to the reference cell RMC to be accessed is connected to the bit line / BL via a bit line switch BLSWR (bold frame) that is turned on by activation of bit line selection signals BLSZR4, BLSXR4. The plate line PLR4 connected to the reference cell RMC to be accessed is connected to the plate line PLo via a plate line switch PLSWR (bold frame) that is turned on by activation of plate line selection signals PLSZR4, PLSXR4. In other subarrays SARY, memory cells MC, reference cells RMC, bit line switches BLSWL, BLSWR, and plate line switches PLSWL, PLSWR at positions corresponding to those indicated by bold frames are selected and operated.

[0089] The circuit configurations of the sense amplifier SA and the plate line control circuits PLeCNT, PLoCNT are the same as those of the sense amplifier SA and the plate line control circuits PLeCNT, PLoCNT of the 2T2C type semiconductor memory device 100 shown in Figures 2 and 3. Therefore, in the semiconductor memory device 102, the sense amplifier SA can be operated at a higher speed than when the reference copy circuit REFCPY and the reference generation circuit FEFGEN shown in Figure 9 are used. Furthermore, since the same circuits as those of the semiconductor memory device 100 of Figure 2 can be used, design assets can be reused, and an increase in development costs for the semiconductor memory device 102 can be suppressed.

[0090] In addition, a pair of memory cells MC may be connected to the bit lines BL, / BL and the plate lines PLe, PLo by simultaneously selecting one pair of plate line selection signals PLSZL<0-3>, PLSXL<0-3> and one pair of corresponding bit line selection signals BLSZL<0-3>, BLSXL<0-3>, and one pair of plate line selection signals PLSZL<4-7>, PLSXL<4-7> and one pair of corresponding bit line selection signals BLSZL<4-7>, BLSXL<4-7>. Alternatively, one pair of plate line selection signals PLSZR<0-3>, PLSXR<0-3> and one pair of corresponding bit line selection signals BLSZR<0-3>, BLSXR<0-3>, and one pair of plate line selection signals PLSZR<4-7>, PLSXR<4-7> and one pair of corresponding bit line selection signals BLSZR<4-7>, BLSXR<4-7> may be simultaneously selected to connect a pair of memory cells MC to the bit lines BL, / BL and the plate lines PLe, PLo. This allows the semiconductor memory device 102 to operate as a 2T2C type, similar to the sub-array SARY shown in FIG.

[0091] Fig. 11 shows an example of an access operation of the semiconductor memory device 102 of Fig. 10. A detailed description of operations similar to those in Fig. 8 will be omitted. Since a read operation is also performed in Fig. 11, the waveforms of the chip enable signal / CE and the latch enable signals LEZ and LEX are similar to those in Fig. 8. In a read operation, the write enable signal / WE is always set to high level "H".

[0092] The waveforms of the bit line selection signal BLSZL0 and the plate line selection signal PLSZL0 are the same as those in Fig. 8. That is, the semiconductor memory device 102 employs a confined sense scheme in which the sense amplifier SA performs an amplification operation while the bit lines BLL and BLR connected to the memory cell MC and the reference cell RMC are disconnected from the sense amplifier SA.

[0093] The waveform of the write enable signal WREZe corresponding to the plate line PLe connected to the memory cell MC to be accessed and the waveform of the plate line PLe are the same as those in Figure 8 (Figures 11(a) and (b)). The write enable signal WREZo corresponding to the plate line PLo connected to the reference cell RMC to be accessed is set to low level "L" (Figure 11(c)).

[0094] When the write enable signal WREZo is at low level, the plate line PLo corresponding to the reference cell RMC to be accessed is set to high level "H" (FIG. 11(d)). This prevents the reference cell RMC to be accessed from being rewritten to "1".

[0095] When the memory cell MC corresponding to the bit line / BL is accessed, the write enable signal WREZe is set to low level "L", and the write enable signal WREZo has the same waveform as the write enable signal WREZe in FIG.

[0096] The bit line selection signal BLSZR4 corresponding to the reference cell RMC to be accessed is set to a high level during the period when data is read from the reference cell RMC to the bit line / BL, and then set to a low level (FIG. 11(e)). The plate line selection signal PLSZR4 corresponding to the reference cell RMC to be accessed is set to a high level from the rising edge of the plate line selection signal PLSZL0 corresponding to the memory cell MC to be accessed until the end of the restore period (FIG. 11(f)).

[0097] The waveforms of the word line WLL2, bit line BLL0, and plate line PLLE0 connected to the memory cell MC to be accessed are the same as those in Figure 8. The waveform of the word line RWLR connected to the reference cell RMC to be accessed is the same as that of the word line WLL2, except that it is set to the power supply voltage VDD during the data rewrite period (Figure 11(g)). Since data "0" is always rewritten to the reference cell RMC, the high-level voltage of the word line RWLR during the rewrite period can be the power supply voltage VDD, which is lower than the high-level voltage of the word line WLL2.

[0098] The voltage of the bit line BLR4 connected to the reference cell RMC to be accessed becomes an intermediate value between the voltage of the bit line BLL0 for data "1" and the voltage of the bit line BLL0 for data "0" during the high level period of the bit line selection signal BLSZR4 (FIG. 11(h)). The voltage of the bit line BLR4 is set to a low level by the bit line selection signal BLSXR4 (not shown) which changes to a high level in response to the low level of the bit line selection signal BLSZR4 during the rewrite period (FIG. 11(i)).

[0099] The read operation shown in Figure 11 is similar to that shown in Figure 8, except that the sense amplifier SA differentially amplifies the data read from the memory cell MC onto the bit line BL and the data read from the reference cell RMC onto the bit line / BL. This allows the "1" write and "0" write during restore of the memory cell MC to be performed at the same time, shortening the cycle time during memory access and enabling high-speed random access. However, to prevent the reference cell RMC being accessed from being rewritten to "1," the plate lines PLo and PLR4 connected to the reference cell RMC are set to high level "H" (VDD) during the read operation.

[0100] In the semiconductor memory device 102 in which one reference cell RMC is assigned to multiple memory cells MC, the access frequency of the reference cell RMC during random access is higher than the access frequency of the memory cells MC. This may cause differences in the fluctuations of the remanent polarization values ​​of the memory cells MC and the reference cells RMC, reducing the data read margin. In contrast, in the semiconductor memory device 300 in which the number of memory cells MC and the number of reference cells RMC are the same, the access frequency of the reference cells RMC is the same as the access frequency of the memory cells MC.

[0101] 12 shows an example of the change over time in the remanent polarization value of the reference cell RMC and the memory cell MC. In FIG. 12, the WR-RD interval indicates the time from when data is written to the reference cell RMC or the memory cell MC to when the data is read, for example, the time from when the data is rewritten to when the data is read by the next access.

[0102] For example, the remanent polarization value of the reference cell RMC storing data "0" (U-term) increases as the WR-RD interval becomes longer. As the remanent polarization value increases, the amount of signal read from the reference cell RMC to the bit line during a read operation decreases.

[0103] 12, the remanent polarization value of the memory cell MC storing data "0" (U-term) also increases as the WR-RD interval becomes longer. The remanent polarization value of the memory cell MC storing data "1" (P-term) decreases as the WR-RD interval becomes longer.

[0104] The read margin is expressed by the difference in the remanent polarization value between the memory cell MC in the P-term and the reference cell RMC in the U-term, and the difference in the remanent polarization value between the memory cell MC in the U-term and the reference cell RMC in the U-term. Therefore, if the access frequency of the reference cell RMC and the memory cell MC differs due to random access, the worst read margin decreases.

[0105] The worst read margin for the P-term memory cell MC occurs when both the WR-RD intervals of the memory cell MC and the reference cell RMC are long. The worst read margin for the U-term memory cell MC occurs when the WR-RD interval of the U-term memory cell MC is long and the WR-RD interval of the reference cell RMC is short.

[0106] Therefore, by writing "0" to the reference cell RMC in advance when accessing the memory cell MC, the WR-RD interval of the reference cell RMC is always kept short. Furthermore, the area of ​​the ferroelectric capacitor FC of the reference cell RMC is set so that the remanent polarization value of the reference cell RMC when "0" is written is an intermediate value between the remanent polarization value of the P-term memory cell MC and the remanent polarization value of the U-term memory cell MC. This makes it possible to suppress changes in the remanent polarization value of the reference cell RMC, as shown in the lower right of FIG. 12. As a result, even when the access frequencies of the reference cell RMC and the memory cell MC differ, it is possible to suppress a decrease in the read margin of the P-term and U-term memory cells MC.

[0107] 13 shows another example of an access operation of the semiconductor memory device 102 having the sub-array SARY of FIG. 10. The read operation performed in FIG. 13 is the read operation shown in FIG. 11 with the addition of a prior "0" restore to the reference cell RMC (FIG. 13(a)). That is, a restore period RMC-RSTR of the reference cell RMC and a WR-RD interval period RMC-INTVL of the reference cell RMC are added before the read period CRD of the memory cell MC (FIGS. 13(b) and 13(c)). The operation after the prior "0" restore is the same as that shown in FIG. 11. FIG. 13 shows only the main waveforms among those shown in FIG. 12.

[0108] The introduction of the pre-"0" restore eliminates the need for the reference cell RMC "0" restore that is performed when reading data from the memory cell MC. Therefore, the waveform of the word line RWLR connected to the reference cell RMC is set to a high level during the read period CRD and the sense period SNS, and then set to a low level (Figure 13(d)). Similarly, the waveform of the plate line PLR4 connected to the reference cell RMC is set to a high level during the read period CRD and the sense period SNS, and then set to a low level (Figure 13(e)).

[0109] This allows the WR-RD interval of the reference cell RMC to be a short, constant period regardless of the access frequency of the reference cell RMC.As a result, even if the access frequencies of the reference cell RMC and the memory cell MC differ, it is possible to suppress a decrease in the read margin of the memory cell MC.

[0110] As described above, the embodiments shown in Figures 10 to 13 can also achieve the same effects as the embodiments shown in Figures 1 to 9. For example, when restoring a memory cell MC, writing "1" and writing "0" can be performed at the same timing, which can shorten the cycle time when accessing the memory, and enables high-speed random access.

[0111] Furthermore, in this embodiment, when accessing a memory cell MC, the plate line PLo (or PLe) connected to the reference cell RMC can be set to a high level "H" to prevent the reference cell RMC from being rewritten to "1".

[0112] By performing a pre-restoration of "0" on the reference cell RMC when accessing the memory cell MC, the WR-RD interval of the reference cell RMC can be set to a short, constant period regardless of the access frequency of the reference cell RMC. As a result, even if the access frequencies of the reference cell RMC and the memory cell MC differ, a decrease in the read margin of the memory cell MC can be suppressed.

[0113] Figure 14 shows an example of a circuit for two subarrays of a semiconductor memory device according to another embodiment. Detailed descriptions of elements similar to those in Figure 10 will be omitted. For example, the semiconductor memory device 103 shown in Figure 14 includes multiple subarrays SARY, a control circuit CNTL, a row decoder RDEC, a read amplifier RA, and a write amplifier WA, similar to the semiconductor memory device 100 shown in Figure 1. The semiconductor memory device 104 is mounted as a single memory device in various electronic devices.

[0114] The semiconductor memory device 104 shown in FIG. 14 is a 1T1C type. The semiconductor memory device 104 has reference cells RMC arranged in a row along the Y direction on the opposite side of the sense amplifiers SA with respect to the regions of the memory cells MC arranged on both the left and right sides of the subarray SARY in FIG. 14. The circuits arranged inside the reference cells RMC arranged on both the left and right sides are the same as those in FIG. 10. Note that the plate line control circuits PLeCNT and the write enable signals WREZe and WREZo that control PLoCNT are not shown. The circuits outside the reference cells RMC will be described in FIGS. 15 and 16.

[0115] FIG. 15 shows an example of a circuit arranged on the left side of the subarray SARY in FIG. 14. The memory cells MC, bit line switches BLSWL, and plate line switches PLSWL shown in bold frames in FIG. 15 represent circuits that operate in the first access of FIG. 18, which will be described later. FIG. 16 shows an example of a main part on the left side of the subarray in FIG. 14. FIG. 17 shows an example of a main part on the right side of the subarray in FIG. 14. The circuit shown in FIG. 17 is symmetrical to the circuit shown in FIG. 16, and is the same as FIG. 16 except that the suffixes of some signal names are changed from "L" to "R," so a description thereof will be omitted. The circuits shown in FIGS. 15 and 16 will be described below.

[0116] In this embodiment, the plate lines are separated between the memory cells MC and the reference cells RMC. The plate lines rPLL (rPLL0-rPLL7) connected to each reference cell RMC are connected to the plate line rPL (rPLe or rPLo) via plate line switches rPLSWL. The plate line rPLL is connected to the output of an inverter IVL (IVLe or IVLo) that receives the plate drive signal rPLEXL at its input.

[0117] Each inverter IVL outputs a signal obtained by inverting the logic level of the plate line drive signal rPLEXL to the plate lines rPLLe and rPLLo. The inverted signal of the plate line drive signal rPLEXL is then output to the plate line rPLL connected to the reference cell RMC to be accessed via the plate line switch rPLSWL that is turned on.

[0118] As shown in Fig. 16, the plate line switch rPLSWL has the same circuit configuration as the plate line switch PLSWL shown in Fig. 3. The plate line switch rPLSWL is turned on or off according to the corresponding plate line selection signal rPLSZL (one of rPLSZL0-rPLSZL7) or rPLSXL (one of rPLSXL0-rPLSXL7). In addition, the plate line switch rPLSWL connects the corresponding plate line rPLL to the ground line VSS while the corresponding plate line selection signal rPLSXL is at a high level (the off period of the plate line switch rPLSWL).

[0119] 16, the reset switch RSTSWL has an n-channel MOS transistor whose gate is connected to a reset signal line RSTRWLL, whose drain is connected to the bottom electrode BEL of the reference cell RMC, and whose source is connected to the ground line VSS. The reset switch RSTSWL is turned on while the reset signal RSTRWLL is at a high level, and sets the bottom electrode BEL of the reference cell RMC to "0."

[0120] By arranging the reference cells RMC on both the left and right sides of the sub-array SARY, it is possible to easily arrange the reset switches RSTSWL, which allows the reference cells RMC to be easily connected to a plate line rPLL separate from the plate line PLL. It is also possible to easily arrange the inverters IVL and plate line switches rPLSWL that control the voltage of the plate line rPLL.

[0121] 12 and 13, the semiconductor memory device 104 can perform the pre-restoration of the reference cell RMC to "0" separately from the access of the memory cell MC by using the inverter IVL, the plate line switch rPLSWL, and the reset switch RSTSWL. As a result, when read operations are performed consecutively, as will be described in FIG. 19, the pre-restoration of the "0" can be overlapped with the restore period of the previous read operation.

[0122] 18 shows an example of the positions of memory cells MC and reference cells RMC to be accessed when successive access operations are performed on the semiconductor memory device 104 of FIG. 14. The positions of the memory cells MC and reference cells RMC to be accessed are indicated by shading. Hereinafter, in the successive access operations, the first access operation is referred to as the 1st access, and the next access operation is referred to as the 2nd access.

[0123] For example, in the first access, the memory cell MC connected to the word line WLL2 and the bit line BLL0 and the reference cell RMC connected to the bit line BLR4 are accessed. In the second access, the memory cell MC connected to the word line WLR2 and the bit line BLR4 and the reference cell RMC connected to the bit line BLL0 are accessed. Then, while the memory cell MC is being accessed in the first access, the reference cell RMC is pre-restored to "0" in the second access.

[0124] FIG. 19 shows an example of an access operation of the semiconductor memory device 104 having the subarray SARY of FIG. 14. FIG. 20 shows examples of various signals used to generate the waveforms shown in FIG. 19. In FIG. 19, the word lines WLL, WLR, reference word lines RWLL, RWLR, plate lines PLL, PLR, reference plate lines rPLL, rPLR, and bit lines BLL, BLR are indicated by the symbols WL, RWL, PL, and BL. The waveforms of the signal lines shown will be explained with reference to FIG. 20. In FIG. 19, a write operation is performed as the first access, and a read operation is performed as the second access. In the first and second accesses, the memory cells MC and reference cells RMC shown shaded in FIG. 18 are accessed.

[0125] First, a write operation is initiated when the chip enable signal / CE and the write enable signal / WE go low while a predetermined address signal AD is being supplied (FIG. 19(a)). In the write operation, a pre-restore to "0" is performed as in FIG. 13 (FIG. 19(b)).

[0126] As shown in FIG. 20, in the pre-"0" restore, the plate line drive signal rPLEXR is set to a low level, and the reference plate line rPLRo is set to a high level via the inverter IVRo (FIG. 20(a) and (b)). The high level of the reference plate line rPLRo is transmitted to the reference plate line rPLR4 via the plate line switch rPLSWR (FIG. 20(c)). In addition, the bottom electrode BEL of the reference cell RMC is set to a low level by the reset switch RSTSWR that receives a high-level reset signal RSTRWLR (FIG. 20(d)). As a result, data "0" is restored to the reference cell RMC to be accessed (pre-"0" restore).

[0127] After that, as shown in Figure 19, the word line WL, reference word line RWL, and plate line PL are set to high level (Figure 19(c)), similarly to Figure 13. Then, data is read from the memory cell MC and reference cell RMC to the bit lines BL and / BL (Figure 19(d)). After the data on the bit lines BL and / BL is differentially amplified by the sense amplifier SA, write data is supplied to the bit lines BL and / BL (Figure 19(e)).

[0128] Specifically, as shown in Figure 20, the word line WLL2 and the plate line PLL0 are sequentially set to high level, and data is read from the memory cell MC to the bit line BLL0 (Figure 20(e), (f), (g)). At the same time, the reference word line RWLR and the reference plate line rPLR4 are set to high level, and data is read from the reference cell RMC to the bit line BLR4 (Figure 20(h), (i), (j)).

[0129] The data on the bit line BLL0 is transmitted to the bit line BL via the bit line switch BLSWL, which is turned on by the high-level bit line selection signal BLSZL0 (FIG. 20(k)). The data on the bit line BLR4 is transmitted to the bit line / BL via the bit line switch BLSWR, which is turned on by the high-level bit line selection signal BLSZR4 (FIG. 20(l)).

[0130] Then, the data on the bit lines BL and / BL is amplified by the sense amplifier SA, and the logical value of the data stored in the memory cell MC is determined (FIG. 20(m)). After this, the data on the bit lines BL and / BL is rewritten with the write data (FIG. 20(n)). The restore operation to the memory cell MC in the subsequent first access is the same as the restore operation in FIG. 13.

[0131] As shown in FIG. 19, the second access starts at the end of the restore period RSTR in the first access and during the overlapping period with the reset period RSTR, and a pre-“0” restore for the second access is performed (FIG. 19(f)). Specifically, as shown in FIG. 20, in the pre-“0” restore for the second access, the plate line drive signal rPLEXL is set to a low level, and the reference plate line rPLLe is set to a high level (FIG. 20(o) and (p)). The high level of the reference plate line rPLLe is transmitted to the reference plate line rPLL0 via the plate line switch rPLSWL (FIG. 20(q)). In addition, the reset switch RSTSWL, which receives a high-level reset signal RSTRWLL, sets the bottom electrode BEL of the reference cell RMC connected to the bit line BLL0 to a low level (FIG. 20(r)). As a result, data “0” is restored in the reference cell RMC to be accessed (pre-“0” restore).

[0132] After this, similar to FIG. 13, the word line WLR2 and the plate line PLR4 are sequentially set to high level, and data is read from the memory cell MC to the bit line BLR4 (FIG. 20(s), (t), (u)). At the same time, the reference word line RWLL and the reference plate line rPLL0 are set to high level, and data is read from the reference cell RMC to the bit line BLL0 (FIG. 20(v), (w), (x)). Then, the data on the bit lines BL and / BL is amplified by the sense amplifier SA, and the logical value of the data stored in the memory cell MC is determined (FIG. 20(y)).

[0133] As described above, in this embodiment, the period of the prior "0" restore overlaps with part of the list period and reset period of the access operation performed immediately before. This makes it possible to shorten the cycle time seen from outside the semiconductor memory device 104 compared to the internal cycle time of the semiconductor memory device 104, enabling high-speed random access. Furthermore, when accessing the memory cell MC, the plate line PLo (or PLe) connected to the reference cell RMC is set to high level "H," thereby preventing the reference cell RMC from being rewritten to "1."

[0134] As described above, the embodiments shown in Figures 14 to 20 can also achieve the same effects as the embodiments shown in Figures 1 to 13. For example, when restoring a memory cell MC, writing "1" and writing "0" can be performed at the same timing, which can shorten the cycle time when accessing memory, and enables high-speed random access.

[0135] Furthermore, in this embodiment, by overlapping the period of the pre-restore "0" of the next access operation with the latter half of the access operation, the cycle time seen from outside the semiconductor memory device 104 can be made shorter than the internal cycle time of the semiconductor memory device 104. As a result, random access can be performed at even higher speeds.

[0136] By placing the reference cells RMC on both the left and right sides of the subarray SARY, the reset switches RSTSWL and RSTSWR can be easily placed. The reference cells RMC can be easily connected to plate lines rPLL and rPLR, which are separate from the plate lines PLL and PLR. In addition, the inverters IVL and IVR, which control the voltages of the plate lines rPLL and rPLR, and the plate line switches rPLSWL and rPLSWR can be easily placed.

[0137] Figure 21 shows an example of circuits for two subarrays of a semiconductor memory device according to yet another embodiment. Detailed descriptions of elements that are the same as those shown in Figures 14 to 17 will be omitted. For example, the semiconductor memory device 106 shown in Figure 21 includes multiple subarrays SARY, a control circuit CNTL, a row decoder RDEC, a read amplifier RA, and a write amplifier WA, similar to the semiconductor memory device 100 shown in Figure 1. The semiconductor memory device 106 is mounted as a single memory device in various electronic devices.

[0138] The subarray SARY has reference cells RMC of multiple sizes. For example, the reference cells RMC may be medium, extra-medium, large, or extra-large. For example, the semiconductor memory device 106 may be realized by changing the sizes of the reference cells RMC arranged in the Y direction in the semiconductor memory device 104 shown in FIG. 14.

[0139] Then, among the four sizes of reference cells RMC, a reference cell RMC of the same size is always used to read data from the memory cell MC. For this purpose, the control circuit CNTL (FIG. 1) always selects a reference cell RMC of the same size and connects it to the bit line BLe (or BLo) regardless of which memory cell MC is accessed. The control circuit CNTL may also always perform a pre-restoration to the reference cell RMC of the same size. The control circuit CNTL that selects the reference cell RMC is an example of a reference selection control unit.

[0140] For example, a pair of reference cells RMC of the same size connected to one end of the bit line BLe and the other end of the bit line BLo, respectively, is an example of a first reference cell and a second reference cell. When reading data from a memory cell MC connected to the other end of the bit line BLo, the first reference cell is connected to the bit line BLe and the plate line PLe. When reading data from a memory cell MC connected to one end of the bit line BLe, the second reference cell is connected to the bit line BLo and the plate line PLo.

[0141] Which of the reference cells RMC to use is determined in advance before shipping the semiconductor memory device 106. For example, the semiconductor memory device 106 has a program circuit in which information indicating the reference cell RMC to be selected is programmed. The control circuit CNTL selects the reference cell RMC to be used in the access operation based on information programmed in the program circuit during the manufacturing process (e.g., the test process). The program circuit may have a ferroelectric capacitor FC provided in an area separate from the sub-array SARY, or may have a fuse.

[0142] For example, if it is found that the read margin is small in the test process of the semiconductor memory device 106 due to fluctuations in the manufacturing conditions of the semiconductor memory device 106 in the semiconductor manufacturing process, it is determined to use an appropriate reference cell RMC that can ensure a predetermined read margin.

[0143] 21 also provides the same effects as those of the above-described embodiments. Furthermore, in this embodiment, by providing reference cells RMC of different sizes and enabling selective use, it is possible to use an appropriate reference cell RMC in accordance with the characteristics of the manufactured semiconductor memory device 106. This makes it possible to suppress a decrease in the read margin of the semiconductor memory device 106.

[0144] 10, 14, and 21, which have reference cells RMC, can be used not only as 1T1C types but also as 2T2C types. This is because the circuit configuration of the memory cells MC, bit lines (BL, etc.), plate lines (PLe, etc.), sense amplifiers SA, and plate line control circuits PLeCNT and PLoCNT is similar to the circuit configuration of the 2T2C type subarray SARY shown in Fig. 2. When used as a 2T2C type, the reference cells RMC are not used, and complementary data is stored in a pair of memory cells MC, and is differentially amplified by the sense amplifier SA when the data is read.

[0145] In this case, the functions of the control circuit CNTL, row decoder RDEC, etc. shown in Fig. 1 can be switched between the 2T2C type and the 1T1C type. This makes it possible to operate as the 2T2C type immediately after mass production when the manufacturing conditions and yield are not stable, and as the 1T1C type when the manufacturing conditions and yield are stable.

[0146] The features and advantages of the embodiments will be apparent from the above detailed description. It is intended that the claims encompass the features and advantages of the above-described embodiments without departing from the spirit and scope of the claims. Furthermore, any improvements and modifications will be readily apparent to those skilled in the art. Therefore, it is not intended that the scope of the inventive embodiments be limited to the above-described embodiments, and appropriate improvements and equivalents within the scope of the disclosed embodiments may be utilized. [Explanation of symbols]

[0147] 100, 102, 104, 106 Semiconductor memory device BEL bottom electrode BL, / BL bit lines BLL, / BLL bit lines BLR, / BLR bit lines BLSW (BLSWL, BLSWR) Bit Line Switch BLSZL, BLSXL, BLSZR, BLSXR Bit line select signals / CE Chip enable signal CMD Command signal CNTL control circuit CT cell transistor FC Ferroelectric Capacitor IVLe, IVLo, IVRe, IVRo inverters I / O Data input / output terminal LEZ, LEX Latch enable signal MC memory cell MCA Memory Cell Array / OE Output enable signal PL, PLe, PLo plate lines PLLe, PLLo, PLRe, PLRo plate wire PLeCNT, PLoCNT plate line control circuit PLSW (PLSWL, PLSWR) Plate line switch PLSZL, PLSXL, PLSZR, PLSXR Plate line selection signals RDEC Row Decoder RA Read Amplifier RMC Reference Cell rPLEXL, rPLEXR plate drive signal rPLL (rPLL0-rPLL7), rPLLe, rPLLo plate lines rPLR (rPLL0-rPLL7), rPLRe, rPLRo plate lines rPLSWL, rPLSWR Plate line switch rPLSZL (rPLSZL0-rPLSZL7) Plate line selection signal rPLSXL (rPLSXL0-rPLSXL7) Plate line selection signal rPLSZR(rPLSZR0-rPLSZR7) Plate line selection signal rPLSXR (rPLSXR0-rPLSXR7) Plate line selection signal RSTSWL, RSTSWR Reset switch RSTRWLL, RSTRWLR Reset signal lines SA Sense Amplifier SARY Sub-array TEL upper electrode WA Light Amplifier / WE Write enable signal WL, WLL, WLR word lines WREZe, WREZo Write enable signals

Claims

1. a first memory cell and a second memory cell each having a ferroelectric capacitor for retaining data; a first bit line and a first plate line connected to the first memory cell; a second bit line and a second plate line connected to the second memory cell; a sense amplifier that differentially amplifies data read from the first memory cell to the first bit line by driving the first plate line and data read from the second memory cell to the second bit line by driving the second plate line; a first restore circuit that outputs to the first plate line a level obtained by inverting the logic of the data on the first bit line that has been differentially amplified by the sense amplifier; a second restore circuit that outputs to the second plate line a level obtained by inverting the logic of the data on the second bit line that has been differentially amplified by the sense amplifier; A semiconductor memory device having:

2. an input of the first restore circuit is connected to a first node in the sense amplifier connected to the first bit line; The input of the second restore circuit is connected to a second node in the sense amplifier that is connected to the second bit line.

2. The semiconductor memory device according to claim 1.

3. The first plate line and the second plate line are wired in parallel to the first bit line and the second bit line.

2. The semiconductor memory device according to claim 1.

4. a plurality of first bit line switches respectively connecting the plurality of first memory cells to the first bit lines; a plurality of first plate line switches respectively connecting the plurality of first memory cells to the first plate lines; a plurality of second bit line switches respectively connecting the plurality of second memory cells to the second bit lines; a plurality of second plate line switches respectively connecting the plurality of second memory cells to the second plate lines; The sense amplifier, the first restore circuit, and the second restore circuit are provided in common to the plurality of first memory cells and the plurality of second memory cells.

2. The semiconductor memory device according to claim 1.

5. a first reference cell connected to the first bit line and the first plate line exclusively with respect to the first memory cell, the first reference cell having a ferroelectric capacitor for holding data; a second reference cell connected to the second bit line and the second plate line exclusively with respect to the second memory cell, the second reference cell having a ferroelectric capacitor for holding data; the sense amplifier differentially amplifies the data stored in the first memory cell and the reference data stored in the second reference cell, or differentially amplifies the data stored in the second memory cell and the reference data stored in the first reference cell; The first restore circuit or the second restore circuit, which receives the reference data differentially amplified by the sense amplifier, outputs a level to the corresponding first plate line or the corresponding second plate line that inhibits rewriting of the data stored in the first reference cell and the second reference cell, regardless of the logic of the reference data.

2. The semiconductor memory device according to claim 1.

6. The first reference cell and the second reference cell store data "0" corresponding to an intermediate value between data "0" and data "1" stored in the first memory cell and the second memory cell, In a read cycle for reading data stored in the first memory cell or the second memory cell, data "0" is restored to the second reference cell or the first reference cell before data is read from the first memory cell or the second memory cell to the first bit line or the second bit line.

6. The semiconductor memory device according to claim 5.

7. a first memory cell and a second memory cell each having a ferroelectric capacitor for retaining data; a first bit line and a first plate line connected to the first memory cell; a second bit line and a second plate line connected to the second memory cell; a first reference cell connected to the first bit line and the first plate line exclusively with respect to the first memory cell, the first reference cell having a ferroelectric capacitor for holding data; a second reference cell connected to the second bit line and the second plate line exclusively with respect to the second memory cell, the second reference cell having a ferroelectric capacitor for holding data; a third plate line connected to the first reference cell; a fourth plate line connected to the second reference cell; a first reset switch that resets the first bit line to a low level; a second reset switch that resets the second bit line to a low level; a sense amplifier that differentially amplifies data read from the first memory cell to the first bit line by driving the first plate line and reference data read from the second reference cell to the second bit line by driving the second plate line, or that differentially amplifies data read from the second memory cell to the second bit line by driving the second plate line and reference data read from the first reference cell to the first bit line by driving the first plate line; a first restore circuit that outputs to the first plate line a level obtained by inverting the logic of the data on the first bit line that has been differentially amplified by the sense amplifier; a second restore circuit that outputs to the second plate line a level that is an inverted version of the logic of the data on the second bit line that has been differentially amplified by the sense amplifier; In a read cycle for reading data stored in the first memory cell or the second memory cell, before reading data from the first memory cell to the first bit line, the fourth plate line is set to a high level and the second reset switch is turned on to restore data "0" to the second reference cell, or before reading data from the second memory cell to the second bit line, the third plate line is set to a high level and the first reset switch is turned on to restore data "0" to the first reference cell. Semiconductor memory device.

8. The first reference cell and the second reference cell are arranged at the ends of the first bit line and the second bit line that are farther from the sense amplifier.

8. The semiconductor memory device according to claim 7.

9. a reference selection control unit that selects a pair of the first reference cell and the second reference cell having the same size from among the plurality of first reference cells and the plurality of second reference cells, connects the selected first reference cell to the first bit line, the first plate line, and the third plate line, and connects the selected second reference cell to the second bit line, the second plate line, and the fourth plate line.

8. The semiconductor memory device according to claim 7.

10. Complementary data is stored in the first memory cell and the second memory cell without using the first reference cell and the second reference cell, and the complementary data read from the first memory cell and the second memory cell to the first bit line and the second bit line is differentially amplified by the sense amplifier.

10. The semiconductor memory device according to claim 5.

11. A method for controlling a semiconductor memory device having first and second memory cells each having a ferroelectric capacitor for retaining data, a first bit line and a first plate line connected to the first memory cell, and a second bit line and a second plate line connected to the second memory cell, the method comprising: differentially amplifying data read from the first memory cell to the first bit line by driving the first plate line and data read from the second memory cell to the second bit line by driving the second plate line; outputting a level obtained by inverting the logic of the differentially amplified data of the first bit line to the first plate line; The logic level of the differentially amplified data of the second bit line is inverted and output to the second plate line. A method for controlling a semiconductor memory device.

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