Manufacturing method for semiconductor device

Abstract

To improve the reliability of a semiconductor device.SOLUTION: In a region 1A, a laminate structure (LM1) and a side wall spacer (SW1) are formed. In a region 2A, a laminate structure (LM2) including a metal film MF is formed. In the region 1A, an epitaxial layer EP is formed on a semiconductor layer SL. The side wall spacer (SW1) is removed. On a surface of the epitaxial layer EP exposed from an insulating film IF1, a silicon oxide film OX1 is formed. By cleaning the insulating film IF1 and the silicon oxide film OX1 using an aqueous solution including ammonia and an activator, the thickness of each of the insulating film IF1 and the silicon oxide film OX1 is reduced. By injecting ions through the insulating film IF1 and the silicon oxide film OX1, an extension region EX1 is formed in the semiconductor layer SL and the epitaxial layer EP.SELECTED DRAWING: Figure 16

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a semiconductor device, for example, a method for manufacturing a semiconductor device including an SOI substrate. [Background technology]

[0002] One technology for low-power semiconductor devices is to form a metal-insulator semiconductor field-effect transistor (MISFET) on a silicon-on-insulator (SOI) substrate, which has a semiconductor substrate, an insulating layer formed on the semiconductor substrate, and a semiconductor layer formed on the insulating layer. The MISFET formed on this SOI substrate can reduce the parasitic capacitance caused by the diffusion region formed in the semiconductor layer. This can improve the operating speed of the MISFET and reduce power consumption.

[0003] For example, Patent Document 1 discloses a method for manufacturing a semiconductor device using an SOI substrate. First, a gate electrode is formed on a semiconductor layer. Next, a silicon oxide film is formed on the semiconductor layer so as to cover the gate electrode. Next, dummy sidewall spacers are formed on the side surfaces of the gate electrode and on the semiconductor layer via the silicon oxide film. Next, an epitaxial layer is formed on the dummy sidewall spacers and on the semiconductor layer exposed from the silicon oxide film. Next, the dummy sidewall spacers are removed.

[0004] Next, ion implantation is performed through the silicon oxide film located on the semiconductor layer to form extension regions in the semiconductor layer. Next, sidewall spacers are formed again on the sides of the gate electrode. Next, ion implantation is performed to form diffusion regions in the epitaxial layer exposed by the sidewall spacers. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-219181 Summary of the Invention [Problem to be solved by the invention]

[0006] As described above, when forming the extension region, ions are implanted so as to penetrate the silicon oxide film. However, if the silicon oxide film is too thick, it may be difficult to implant ions into the semiconductor layer. Therefore, the inventors investigated adjusting the thickness of the silicon oxide film by a cleaning process before forming the extension region. In addition, in recent years, MISFETs have been developed in which a metal film, such as a titanium nitride film, functions as part of the gate electrode.

[0007] The inventors of the present invention have investigated the incorporation of a MISFET containing a metal film into a semiconductor device using an SOI substrate, and in the process have found that the metal film may be etched by the aqueous solution used in the cleaning process to adjust the thickness of the silicon oxide film.

[0008] On the other hand, after the epitaxial layer is formed, the dummy sidewall spacers are removed, but the epitaxial layer covered with the dummy sidewall spacers is exposed during the cleaning process. Depending on the aqueous solution used in the cleaning process, the metal film may be difficult to etch, but the exposed epitaxial layer may be easily etched.

[0009] Therefore, there is a need for a technology that prevents both the metal film and the epitaxial layer from being etched even when a MISFET including a metal film is mounted on a semiconductor device using an SOI substrate, thereby improving the reliability of the semiconductor device.

[0010] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0011] A method for manufacturing a semiconductor device in one embodiment is a method for manufacturing a semiconductor device having a first region in which a first MISFET is formed and a second region in which a second MISFET is formed. a step of forming an epitaxial layer on the semiconductor layer exposed from the first insulating film and the first sidewall spacer in the first region; a step of removing the first sidewall spacer in the first region and the second insulating film in the second region; a step of forming a first silicon oxide film on the surface of the epitaxial layer exposed from the first insulating film in the first region; a step of cleaning the first insulating film and the first silicon oxide film with an aqueous solution containing ammonia and an activator to reduce the thickness of each of the first insulating film and the first silicon oxide film; and a step of forming first impurity regions in the semiconductor layer and the epitaxial layer in the first region by implanting ions so as to penetrate the first insulating film and the first silicon oxide film.

[0012] In one embodiment, a method for manufacturing a semiconductor device includes the steps of forming a first stacked structure including a metal film on a semiconductor layer, forming an epitaxial layer on the semiconductor layer, forming a first silicon oxide film on a surface of the epitaxial layer exposed from a first insulating film, performing a cleaning process on the first insulating film and the first silicon oxide film using an aqueous solution including ammonia and an activator to reduce the thickness of each of the first insulating film and the first silicon oxide film, and forming a first impurity region in the semiconductor layer and the epitaxial layer by implanting ions so that the ions penetrate the first insulating film and the first silicon oxide film. [Effects of the Invention]

[0013] According to one embodiment, the reliability of the semiconductor device can be improved. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 1 is a cross-sectional view showing a semiconductor device according to the first embodiment. [Figure 2] 2A to 2C are cross-sectional views showing a manufacturing process of the semiconductor device according to the first embodiment. [Figure 3] FIG. 3 is a cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 4] FIG. 4 is a cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 5] FIG. 5 is a cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 6] FIG. 6 is a cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 7] FIG. 7 is a cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 8] FIG. 8 is a cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 9] FIG. 9 is a cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 10] FIG. 10 is a cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 11] FIG. 11 is a cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 12] FIG. 12 is a cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 13] FIG. 13 is a cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 14] FIG. 14 is a cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 15] FIG. 15 is a cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 16] FIG. 16 is a cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 17] FIG. 17 is a cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 18]18A to 18C are cross-sectional views showing a manufacturing process of a semiconductor device according to a modified example. [Figure 19] FIG. 19 is a cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 20] FIG. 20 is a cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 21] FIG. 21 is a cross-sectional view showing a manufacturing process subsequent to FIG. [Figure 22] FIG. 22 is a cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 23] FIG. 23 is a cross-sectional view showing a semiconductor device according to the second embodiment. [Figure 24] FIG. 24 is a cross-sectional view showing a manufacturing process of the semiconductor device according to the second embodiment. [Figure 25] FIG. 25 is a cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 26] FIG. 26 is a cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 27] FIG. 27 is a cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 28] FIG. 28 is a cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 29] FIG. 29 is a cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 30] FIG. 30 is a cross-sectional view showing a manufacturing step subsequent to FIG. [Figure 31] FIG. 31 is a cross-sectional view showing a manufacturing process of a semiconductor device in the study example. DETAILED DESCRIPTION OF THE INVENTION

[0015] Hereinafter, embodiments will be described in detail with reference to the drawings. In all drawings for explaining the embodiments, components having the same functions are designated by the same reference numerals, and repeated explanations thereof will be omitted. In the following embodiments, explanations of the same or similar parts will not be repeated unless particularly necessary.

[0016] (Embodiment 1) First, a portion of the structure of the semiconductor device in the first embodiment will be described with reference to Figure 1. As shown in Figure 1, the semiconductor device includes an SOI substrate 10. The SOI substrate 10 has a semiconductor substrate SUB, an insulating layer BOX formed on the semiconductor substrate SUB, and a semiconductor layer SL formed on the insulating layer BOX. The semiconductor device also has a region 1A and a region 2A located around the region 1A.

[0017] Region 1A is an SOI region where the insulating layer BOX and the semiconductor layer SL remain. A MISFET 1Q is formed in region 1A. The MISFET 1Q is a low-breakdown-voltage MISFET that constitutes a logic circuit, an SRAM circuit, etc. FIG. 1 illustrates a case where the MISFET 1Q is an n-type low-breakdown-voltage MISFET.

[0018] Region 2A is a bulk region from which the insulating layer BOX and the semiconductor layer SL have been removed. A ferroelectric memory transistor MQ is formed in region 2A as an n-type MISFET. Although not shown, a bulk region such as region 2A also includes a high-voltage MISFET that constitutes an I / O circuit and has a higher breakdown voltage than the low-voltage MISFET in region 1A.

[0019] The ferroelectric memory transistor MQ is an electrically rewritable nonvolatile memory cell. The ferroelectric memory transistor MQ has a ferroelectric film FE, and can change between a written state and an erased state by controlling the direction of polarization of the ferroelectric film FE.

[0020] The ferroelectric memory transistor MQ also has a metal film MF and a gate electrode GE2. The metal film MF applies stress to the ferroelectric film FE during the manufacturing process and controls the crystal orientation of the ferroelectric film FE. In other words, the metal film MF has the function of orthorhombic-orienting the crystal phase of the ferroelectric film FE. The metal film MF also functions as a part of the gate electrode GE2.

[0021] <Method of manufacturing a semiconductor device> Each manufacturing step included in the method for manufacturing the semiconductor device according to the first embodiment will be described below with reference to FIGS.

[0022] First, as shown in FIG. 2, an SOI substrate 10 is prepared, which has a semiconductor substrate SUB, an insulating layer BOX formed on the semiconductor substrate SUB, and a semiconductor layer SL formed on the insulating layer BOX.

[0023] The semiconductor substrate SUB is made of, for example, p-type single crystal silicon. The insulating layer BOX is made of, for example, silicon oxide and has a thickness of, for example, 10 nm or more and 20 nm or less. The semiconductor layer SL is made of single crystal silicon and has a thickness of, for example, 10 nm or more and 20 nm or less. The semiconductor layer SL is an intrinsic semiconductor layer into which no n-type or p-type impurities have been introduced by ion implantation or the like. Even if p-type impurities have been introduced into the semiconductor layer SL, the impurity concentration is 1×10 13 / cm 3 The following is the result.

[0024] Such an SOI substrate 10 is formed, for example, by a bonding method. In the bonding method, for example, the surface of a first semiconductor substrate made of silicon is oxidized to form an insulating layer BOX, and then a second semiconductor substrate made of silicon is pressure-bonded onto the insulating layer BOX at high temperature. The second semiconductor substrate is then thinned. The thin film of the second semiconductor substrate remaining on the insulating layer BOX is formed as the semiconductor layer SL, and the first semiconductor substrate below the insulating layer BOX is formed as the semiconductor substrate SUB.

[0025] As shown in FIG. 3, an element isolation portion STI, an n-type well region DNW, a p-type well region PW1, and a p-type well region PW2 are formed.

[0026] First, a trench is formed in the SOI substrate 10 by photolithography and etching, reaching the semiconductor substrate SUB. Next, an insulating film is formed to fill the interior of the trench by a film formation process using, for example, a CVD (Chemical Vapor Deposition) method. Next, the insulating film located outside the trench is removed by a polishing process using a CMP (Chemical Mechanical Polishing) method. As a result, an element isolation portion STI including the trench and the insulating film is formed. The depth of the element isolation portion STI is, for example, 300 nm or more and 400 nm or less.

[0027] Next, a well region (impurity region) DNW is formed in the semiconductor substrate SUB by photolithography and ion implantation. Next, a well region (impurity region) PW1 is formed in the well region DNW of region 1A by photolithography and ion implantation, and a well region (impurity region) PW2 is formed in the well region DNW of region 2A by photolithography and ion implantation.

[0028] As shown in FIG. 4, the semiconductor layer SL and the insulating layer BOX located in the region 2A are selectively removed, and a gate insulating film GI1 and a protective film PVF are formed on the semiconductor layer SL located in the region 1A.

[0029] First, the semiconductor layer SL and insulating layer BOX located in region 2A are selectively removed using photolithography and etching so as to leave the semiconductor layer SL and insulating layer BOX located in region 1A, thereby exposing the semiconductor substrate SUB located in region 2A.

[0030] Next, a gate insulating film GI1 is formed by thermal oxidation on the semiconductor layer SL located in region 1A and on the semiconductor substrate SUB located in region 2A. The gate insulating film GI1 is, for example, a silicon oxide film and has a thickness of, for example, 2 nm or more and 5 nm or less. Next, using photolithography and etching, the gate insulating film GI1 located in region 2A is selectively removed so that the gate insulating film GI1 located in region 1A remains.

[0031] Next, a protective film PVF is formed on the gate insulating film GI1 located in region 1A and on the semiconductor substrate SUB located in region 2A by a film formation process using, for example, a CVD method. The protective film PVF is, for example, a silicon nitride film, a silicon oxynitride film, or a polycrystalline silicon film. Next, the protective film PVF located in region 2A is selectively removed using photolithography and etching so that the protective film PVF located in region 1A remains. This exposes the semiconductor substrate SUB located in region 2A.

[0032] As shown in FIG. 5, a gate insulating film GI2, a ferroelectric film FE, and a metal film MF are formed.

[0033] First, a gate insulating film GI2 is formed on the semiconductor substrate SUB located in the region 2A by thermal oxidation treatment using an ISSG (In Situ Steam Generation) oxidation method. The gate insulating film GI2 is, for example, a silicon oxide film and has a thickness of, for example, 1 nm or more and 5 nm or less.

[0034] Next, a ferroelectric film FE is formed on the protective film PVF located in the region 1A and on the gate insulating film GI2 located in the region 2A by a film formation process using, for example, an ALD (Atomic Layer Deposition) method. At this point, the ferroelectric film FE is in an amorphous state.

[0035] The ferroelectric film FE is a HfO2 film or a HfO2 film to which at least one of zirconium (Zr), silicon (Si), nitrogen (N), carbon (C), and aluminum (Al) is added. The thickness of the ferroelectric film FE is, for example, 4 nm or more and 20 nm or less.

[0036] Next, a metal film MF is formed on the ferroelectric film FE located in the region 1A and the region 2A by a film formation process using, for example, a CVD method or a sputtering method. The metal film MF is, for example, a titanium nitride film. The thickness of the metal film MF is, for example, 10 nm or more and 20 nm or less.

[0037] Next, the ferroelectric film FE is crystallized by heat treatment to form an orthorhombic ferroelectric film FE. This heat treatment is performed within a temperature range of 400°C or higher and 600°C or lower. Here, the metal film MF applies stress to the ferroelectric film FE during the heat treatment and controls the crystal orientation of the ferroelectric film FE. In other words, the metal film MF has the function of orienting the crystalline phase of the ferroelectric film FE to an orthorhombic crystal.

[0038] As shown in FIG. 6, the metal film MF and the ferroelectric film FE located in the region 1A are selectively removed.

[0039] First, a resist pattern RP1 is formed on the metal film MF, opening the region 1A and covering the region 2A. Next, an anisotropic etching process is performed using the resist pattern RP1 as a mask to remove the metal film MF and ferroelectric film FE exposed from the resist pattern RP1. Next, the resist pattern RP1 is removed by ashing.

[0040] In the anisotropic etching process, over-etching is performed so as to reliably remove the metal film MF and the ferroelectric film FE located in the region 1 A. The protective film PVF protects the gate insulating film GI1 from this over-etching.

[0041] As shown in FIG. 7, the protective film PVF is removed, and a conductive film CF1, a cap film CP1, and a cap film CP2 are formed.

[0042] First, an etching process is performed using the metal film MF and the ferroelectric film FE as a mask to remove the protective film PVF located in region 1A. Next, a conductive film CF1, a cap film CP1, and a cap film CP2 are sequentially formed on the gate insulating film GI1 located in region 1A and on the metal film MF located in region 2A by a film formation process using, for example, a CVD method.

[0043] The conductive film CF1 is, for example, an n-type polycrystalline silicon film having a thickness of, for example, 60 nm to 100 nm. The cap film CP1 is, for example, an insulating film such as a silicon oxide film having a thickness of, for example, 5 nm to 10 nm. The cap film CP2 is, for example, an insulating film such as a silicon nitride film having a thickness of, for example, 10 nm to 20 nm.

[0044] As shown in FIG. 8, the conductive film CF1, the cap film CP1 and the cap film CP2 are patterned.

[0045] First, a resist pattern RP2 is formed in region 1A and region 2A so as to cover a portion of the cap film CP2. Next, an anisotropic etching process is performed using the resist pattern RP2 as a mask to remove the cap film CP2, the cap film CP1, and the conductive film CF1 exposed from the resist pattern RP2. Next, the resist pattern RP2 is removed by ashing.

[0046] The patterned conductive film CF1 is formed as a gate electrode GE1 in the region 1 A, and as a gate electrode GE2 in the region 2 A. Next, the gate insulating film GI1 exposed from the gate electrode GE1 in the region 1 A may be removed by performing an isotropic etching process using an aqueous solution containing hydrofluoric acid.

[0047] In this manner, a stacked structure LM1 including the gate insulating film GI1, the gate electrode GE1, the cap film CP1, and the cap film CP2 is formed on the semiconductor layer SL located in the region 1A.

[0048] 9, an anisotropic etching process is performed using the cap film CP2 as a mask to remove the metal film MF and the ferroelectric film FE exposed from the cap film CP2 in the region 2A. Next, an isotropic etching process may be performed using an aqueous solution containing hydrofluoric acid to remove the gate insulating film GI2 exposed from the ferroelectric film FE in the region 2A.

[0049] In this way, a stacked structure LM2 including a gate insulating film GI2, a ferroelectric film FE, a metal film MF, a gate electrode GE2, a cap film CP1, and a cap film CP2 is formed on the semiconductor substrate SUB located in the region 2A.

[0050] As shown in FIG. 10, an offset spacer OS1, an extension region EX2, an insulating film IF1, and an insulating film IF2 are formed.

[0051] First, a silicon nitride film is formed by a film formation process using, for example, a CVD method so as to cover the stacked structures LM1 and LM2. Next, the silicon nitride film is processed by an anisotropic etching process to form offset spacers OS1 on each side surface of the stacked structures LM1 and LM2.

[0052] Next, in the region 2A, an n-type extension region (impurity region) EX2 is selectively formed in the well region PW2 (in the semiconductor substrate SUB) by photolithography and ion implantation.

[0053] Next, an insulating film IF1 is formed by a film formation process using, for example, a CVD method so as to cover the stacked structures LM1 and LM2. Next, in the region 1A and the region 2A, an insulating film IF2 is formed on the insulating film IF1 by a film formation process using, for example, a CVD method.

[0054] The insulating film IF1 is, for example, a silicon oxide film having a thickness of, for example, 5 nm to 10 nm, and the insulating film IF2 is, for example, a silicon nitride film having a thickness of, for example, 30 nm to 50 nm.

[0055] As shown in FIG. 11, in the region 1A, a sidewall spacer SW1 is formed from an insulating film IF2.

[0056] First, a resist pattern RP3 is formed to cover the insulating film IF2 located in region 2A and to leave an opening in the insulating film IF2 located in region 1A. Next, using the resist pattern RP3 as a mask, an anisotropic etching process is performed on the insulating film IF2 located in region 1A. By selectively processing the insulating film IF2 in region 1A, sidewall spacers SW1 are formed on the side surfaces of the stacked structure LM1 via the offset spacers OS1 and the insulating film IF1. Next, the resist pattern RP3 is removed by an ashing process. Next, an isotropic etching process is performed using an aqueous solution containing hydrofluoric acid to remove the insulating film IF1 exposed from the sidewall spacers SW1 in region 1A.

[0057] 12, by a film formation process using an epitaxial growth method, an epitaxial layer (semiconductor layer) EP is formed on the semiconductor layer SL exposed from the stacked structure LM1, the insulating film IF1, and the sidewall spacer SW1 in the region 1A. At this time, the gate electrode GE1 in the region 1A is covered with the cap film CP2, and the entire region 2A is covered with the insulating film IF2, so the epitaxial layer EP is not formed in these places.

[0058] The epitaxial layer EP is made of, for example, single crystal silicon, and is the same material as the semiconductor layer SL, so they are integrated together. However, to make it easier to understand the invention, the boundary between the epitaxial layer EP and the semiconductor layer SL is shown by a dashed line in the following drawings.

[0059] 13, a silicon oxide film OX2 is formed by thermal oxidation on the surface of the epitaxial layer EP exposed from the sidewall spacer SW1 in the region 1A. The thickness of the silicon oxide film OX2 is, for example, not less than 3 nm and not more than 10 nm.

[0060] As shown in FIG. 14, in the region 2A, a sidewall spacer SW1 is formed from an insulating film IF2.

[0061] First, a resist pattern RP4 is formed to cover the region 1A and to expose the insulating film IF2 located in the region 2A. Next, using the resist pattern RP4 as a mask, the insulating film IF2 located in the region 2A is anisotropically etched. In the region 2A, the insulating film IF2 is selectively processed to form sidewall spacers SW1 on the side surfaces of the stacked structure LM2 via the offset spacers OS1 and the insulating film IF1. Next, the resist pattern RP4 is removed by ashing.

[0062] As shown in FIG. 15, the sidewall spacer SW1 made of the insulating film IF2 is removed, and a silicon oxide film OX1 is formed on the surface of the epitaxial layer EP.

[0063] First, the sidewall spacers SW1 are removed in the regions 1A and 2A by performing an anisotropic etching process under conditions that allow a silicon nitride film to be etched more easily than a silicon oxide film. At this time, the cap films CP2 of the stacked structures LM1 and LM2 are also removed. By removing the sidewall spacers SW1, a portion of the surface of the epitaxial layer EP that was in contact with the sidewall spacers SW1 is exposed.

[0064] Next, in the region 1A, a silicon oxide film OX1 is formed on the surface of the epitaxial layer EP exposed from the insulating film IF1 and the silicon oxide film OX2. The silicon oxide film OX1 can be formed, for example, by ashing. When ashing is used, the thickness of the silicon oxide film OX1 is, for example, 1 nm or more and 2 nm or less. As another example, the silicon oxide film OX1 can be formed, for example, by thermal oxidation. When thermal oxidation is used, the thickness of the silicon oxide film OX1 is, for example, 3 nm or more and 10 nm or less.

[0065] As shown in FIG. 16, after the thickness of the insulating film IF1 that functions as a through film during ion implantation is adjusted by a cleaning process, extension regions (impurity regions) EX1 are formed by ion implantation.

[0066] When forming the extension regions EX1 in the semiconductor layer SL, ions are implanted so that they penetrate the insulating film IF1 (silicon oxide film). However, if the thickness of the insulating film IF1 is too thick, it may be difficult to implant ions into the semiconductor layer SL. Therefore, before forming the extension regions EX1, a cleaning process is performed to adjust the thickness of the insulating film IF1.

[0067] <Problems in the study example and main features of the first embodiment> The manufacturing process of the example studied by the present inventors will be described below with reference to Fig. 31. Fig. 31 shows the state before and after the above-mentioned cleaning process.

[0068] First, the inventors of the present application investigated the use of an aqueous solution containing ammonia water and hydrogen peroxide (APM cleaning solution) and an aqueous solution containing hydrofluoric acid and hydrogen peroxide (HPM cleaning solution) as the aqueous solution used for the cleaning process. The thickness of the insulating film IF1 can be adjusted by the APM cleaning solution and the HPM cleaning solution.

[0069] However, the inventors of the present application have discovered that when a MISFET (ferroelectric memory transistor MQ) having a metal film MF is present in addition to MISFET 1Q, as in embodiment 1, a problem occurs in which part of the metal film MF is dissolved by the APM cleaning solution and HPM cleaning solution.

[0070] As shown in FIG. 15, the cause of this problem is that the side surfaces of the metal film MF are covered by the offset spacer OS1 and the insulating film IF1, but pinholes (defects) may be locally formed in the offset spacer OS1 and the insulating film IF1. Pinholes are likely to be formed when the offset spacer OS1 and the insulating film IF1 are formed by a film formation process using a CVD method. This causes the APM cleaning solution and the HPM cleaning solution to reach the metal film MF through the pinholes, resulting in the problem of dissolving part of the metal film MF. In particular, the hydrogen peroxide solution contained in the APM cleaning solution and the HPM cleaning solution has the property of easily dissolving the metal film MF.

[0071] Therefore, the inventors of the present application investigated the use of an aqueous solution containing ammonia water and an activator instead of the APM cleaning solution and the HPM cleaning solution. This aqueous solution does not contain hydrogen peroxide. This aqueous solution can solve the problem of partial dissolution of the metal film MF even when pinholes are formed in the offset spacer OS1 and the insulating film IF1. This aqueous solution can adjust the thickness of a silicon oxide film such as the insulating film IF1, and has a constant etching rate for silicon.

[0072] As shown in "Before Cleaning" in Fig. 31, when the sidewall spacer SW1 is removed, a part of the surface of the epitaxial layer EP that was in contact with the sidewall spacer SW1 is exposed. In Fig. 31, the exposed part of the epitaxial layer EP is illustrated as a concern part 20. Here, in the study example, unlike the first embodiment, the silicon oxide film OX1 is not formed.

[0073] 31, when cleaning is performed using an aqueous solution containing ammonia water and an activator, etching of silicon progresses from the concern area 20, removing part of the epitaxial layer EP and part of the semiconductor layer SL. As a result, a problem occurs in which the on-current of the MISFET 1Q decreases.

[0074] Furthermore, the upper portions of the offset spacer OS1 and the insulating film IF1 formed on the side surface of the stacked structure LM1 may be recessed by the isotropic etching process of the insulating film IF1 in FIG. 11 and the process of removing the sidewall spacer SW1 in FIG. 15. In this case, the upper portion of the gate electrode GE1 is exposed. In FIG. 31, the portion where the upper portion of the gate electrode GE1 is exposed is illustrated as a concern portion 21.

[0075] In this state, if a cleaning process is performed using an aqueous solution containing ammonia water and an activator, etching of silicon will proceed from the concern portion 21, causing a problem that part of the gate electrode GE1 will be removed.

[0076] In the first embodiment, the silicon oxide film OX1 is formed on the surface of the epitaxial layer EP exposed from the insulating film IF1 and the silicon oxide film OX2, as described in Fig. 15. Note that even if the concern portion 21 in Fig. 31 occurs, the silicon oxide film OX1 is also formed on the exposed upper part of the gate electrode GE1.

[0077] That is, by forming the silicon oxide film OX1, there are no exposed portions of silicon during the cleaning process. Therefore, in the first embodiment, the problem of the metal film MF being dissolved can be solved, and the problem of the epitaxial layer EP, the semiconductor layer SL, and the gate electrode GE1 being partially removed can also be solved. This improves the reliability of the semiconductor device.

[0078] Note that, when the thickness is adjusted by a cleaning process using an aqueous solution containing ammonia water and an activator, the thicknesses of the insulating film IF1, the silicon oxide film OX1, and the silicon oxide film OX2 become thinner. When the silicon oxide film OX1 is formed by an ashing process, it is more difficult to form the silicon oxide film OX1 thick than when the silicon oxide film OX1 is formed by a thermal oxidation process. Therefore, the silicon oxide film OX1 may be completely removed during the cleaning process. In such a case, the ashing process is performed again to increase the thickness of the silicon oxide film OX1, and the cleaning process is performed again. That is, when the silicon oxide film OX1 is formed by an ashing process, the formation of the silicon oxide film OX1 by the ashing process and the cleaning process may be repeated multiple times.

[0079] When the silicon oxide film OX1 is formed by thermal oxidation, it is easier to form a thick silicon oxide film OX1 than when the silicon oxide film OX1 is formed by ashing, and therefore it is not necessary to repeat the formation of the silicon oxide film OX1 and the cleaning process multiple times, which simplifies the manufacturing process.

[0080] On the other hand, when the silicon oxide film OX1 is formed by thermal oxidation, the thermal load history increases. In the manufacturing process of a semiconductor device, if the thermal load history is very large, problems such as fluctuations in the impurity profile of the impurity region or distortion of the semiconductor substrate occur, so it is preferable to keep the thermal load history as small as possible. When the silicon oxide film OX1 is formed by ashing, the thermal load history hardly increases. Therefore, from the viewpoint of such thermal load history, ashing is superior to thermal oxidation.

[0081] After the formation and cleaning of the silicon oxide film OX1 as described above, as shown in FIG. 16, ions are implanted in the region 1A by photolithography and ion implantation so as to penetrate the insulating film IF1, the silicon oxide film OX1, and the silicon oxide film OX2, thereby selectively forming n-type extension regions EX1 in the semiconductor layer SL and the epitaxial layer EP.

[0082] As shown in FIG. 17, sidewall spacers SW2 and diffusion regions (impurity regions) ND are formed, and the silicon oxide film OX2 and cap film CP1 are removed.

[0083] First, in region 1A and region 2A, for example, a silicon nitride film is formed by, for example, a CVD method. Anisotropic etching is performed on the silicon nitride film to form sidewall spacers SW2 on the side surfaces of gate electrode GE1 and gate electrode GE2, with offset spacers OS1 and insulating films IF1 interposed therebetween. The sidewall spacers SW2 are formed so as to cover a portion of epitaxial layer EP. Alternatively, the sidewall spacers SW2 may be a stacked film of a silicon oxide film and the silicon nitride film formed on the silicon oxide film.

[0084] Next, using photolithography and ion implantation, n-type diffusion regions ND are formed in the epitaxial layer EP and semiconductor layer SL located in region 1A, and in the semiconductor substrate SUB located in region 2A. Next, a heat treatment is performed in an inert gas atmosphere to activate the impurities contained in each impurity region, such as the diffusion region ND.

[0085] In the region 1A, the extension region EX1 and the diffusion region ND form the source or drain region of the MISFET 1Q. In the region 2A, the extension region EX2 and the diffusion region ND form the source or drain region of the ferroelectric memory transistor MQ.

[0086] Next, an isotropic etching process is performed using an aqueous solution containing hydrofluoric acid to remove the silicon oxide film OX2 and the cap film CP1 in the region 1A, and to remove the insulating film IF1 exposed from the sidewall spacer SW2 and the cap film CP1 in the region 2A.

[0087] Thereafter, a silicide film SI is formed on the upper surfaces of the diffusion region ND, the gate electrode GE1, and the gate electrode GE2 by salicide technology. The silicide film SI is made of, for example, cobalt silicide (CoSi2), nickel silicide (NiSi), or nickel platinum silicide (NiPtSi). Through the above manufacturing steps, the MISFET 1Q and ferroelectric memory transistor MQ shown in FIG. 1 are manufactured.

[0088] (Variation) A modification of the first embodiment will be described below with reference to Figures 18 to 22. In the first embodiment, the protective film PVF is removed, but in the modification, the protective film PVF remains as a part of the gate electrode GE1.

[0089] Fig. 18 shows a manufacturing process following Fig. 3. As shown in Fig. 18, first, the semiconductor layer SL and insulating layer BOX located in region 2A are selectively removed using photolithography and etching so that the semiconductor layer SL and insulating layer BOX located in region 1A remain. This exposes the semiconductor substrate SUB located in region 2A.

[0090] Next, a gate insulating film GI1 is formed by thermal oxidation on the semiconductor layer SL located in region 1A and on the semiconductor substrate SUB located in region 2A. Next, a protective film PVF is formed on the gate insulating film GI1 located in region 1A and region 2A by film formation using, for example, a CVD method. The protective film PVF is an n-type polycrystalline silicon film.

[0091] As shown in FIG. 19, the protective film PVF and the gate insulating film GI1 located in the region 2A are selectively removed.

[0092] First, a resist pattern RP5 is formed on the protective film PVF, opening the region 2A and covering the region 1A. Next, an anisotropic etching process is performed using the resist pattern RP5 as a mask to remove the protective film PVF exposed from the resist pattern RP5. Next, an isotropic etching process is performed using the resist pattern RP5 as a mask to remove the gate insulating film GI1 exposed from the resist pattern RP5. This exposes the semiconductor substrate SUB located in the region 2A. Next, the resist pattern RP5 is removed by ashing.

[0093] 20, first, a gate insulating film GI2, a ferroelectric film FE, and a metal film MF are formed using a technique similar to that shown in FIGS. 5 and 6 of Embodiment 1. In the modification, the metal film MF and ferroelectric film FE located in the region 1A are selectively removed, but the protective film PVF located in the region 1A is left unremoved.

[0094] Next, using a technique similar to that shown in FIG. 7 of the first embodiment, a conductive film CF1, a cap film CP1, and a cap film CP2 are sequentially formed on the protective film PVF located in the region 1A and on the metal film MF located in the region 2A.

[0095] As shown in FIG. 21, the protective film PVF, the conductive film CF1, the cap film CP1 and the cap film CP2 are patterned.

[0096] First, a resist pattern RP2 is formed in region 1A and region 2A so as to cover a portion of the cap film CP2. Next, an anisotropic etching process is performed using the resist pattern RP2 as a mask to remove the cap film CP2, cap film CP1, conductive film CF1, and protective film PVF exposed from the resist pattern RP2 in region 1A, and to remove the cap film CP2, cap film CP1, and conductive film CF1 exposed from the resist pattern RP2 in region 2A. Next, the resist pattern RP2 is removed by ashing.

[0097] The conductive film CF1 and the protective film PVF patterned in the region 1A are formed as the gate electrode GE1, and the conductive film CF1 patterned in the region 2A is formed as the gate electrode GE2. Next, the gate insulating film GI1 exposed from the gate electrode GE1 in the region 1A may be removed by performing an isotropic etching process using an aqueous solution containing hydrofluoric acid.

[0098] In this manner, a stacked structure LM1 including the gate insulating film GI1, the gate electrode GE1, the cap film CP1, and the cap film CP2 is formed on the semiconductor layer SL located in the region 1A.

[0099] Thereafter, through the same manufacturing steps as those shown in FIGS. 10 to 17 of the first embodiment, the MISFET 1Q and ferroelectric memory transistor MQ shown in FIG. 22 are manufactured.

[0100] (Embodiment 2) A part of the structure of the semiconductor device in the second embodiment will be described below with reference to Fig. 23. Also, each manufacturing step included in the method for manufacturing the semiconductor device in the second embodiment will be described with reference to Fig. 24 to Fig. 31. In the following explanation, differences from the first embodiment will be mainly described, and explanation of points that overlap with the first embodiment will be omitted.

[0101] 23, in the second embodiment, a MISFET 2Q is formed in the region 1A. Like the MISFET 1Q, the MISFET 2Q is a low-breakdown-voltage MISFET that forms logic circuits, SRAM circuits, etc. The MISFET 2Q has the same configuration as the MISFET 1Q, except that the configurations of the gate insulating film GI3 and the gate electrode GE3 are different from the configurations of the gate insulating film GI1 and the gate electrode GE1.

[0102] The MISFET 2Q has a gate insulating film GI3 and a gate electrode GE3. The gate insulating film GI3 includes a silicon oxide film and a high-dielectric-constant film HK. The high-dielectric-constant film HK is made of an insulating film having a higher dielectric constant than silicon nitride. The gate electrode GE3 includes a metal film MF and a conductive film CF2 made of an n-type polycrystalline silicon film.

[0103] In the second embodiment, there is also a risk of problems occurring at the concern points 20 and 21 as in the example of FIG. 31, but such problems can be eliminated by forming a silicon oxide film OX1 and performing a cleaning process using an aqueous solution containing ammonia water and an activator.

[0104] The following describes each manufacturing step included in the method for manufacturing a semiconductor device according to the second embodiment. Figure 24 shows the manufacturing step following Figure 3.

[0105] As shown in FIG. 24, a gate insulating film GI3, a metal film MF, a conductive film CF2, a cap film CP1, and a cap film CP2 are formed.

[0106] First, a gate insulating film GI3 is formed on the semiconductor layer SL located in region 1A. To form the gate insulating film GI3, a silicon oxide film is first formed on the semiconductor layer SL by thermal oxidation treatment using, for example, the ISSG oxidation method. This silicon oxide film is formed for the purpose of stabilizing the interface state between the semiconductor layer SL and the gate insulating film GI3, and has a thickness of, for example, 1 nm or more and 2 nm or less.

[0107] Next, a high-dielectric-constant film HK is formed on the silicon oxide film by a film formation process using, for example, the ALD method. The thickness of the high-dielectric-constant film HK is, for example, 4 nm or more and 10 nm or less. The high-dielectric-constant film HK is, for example, a hafnium oxide film (HfO2 film), a hafnium silicate film (HfSiO film), an aluminum oxide film (Al2O3 film), or a hafnium aluminate film (HfAlO2 film), or a laminate film of these.

[0108] Next, a metal film MF is formed on the gate insulating film GI3 by a film formation process using, for example, a CVD method or a sputtering method. The metal film MF of the second embodiment may be made of the same material as the metal film MF of the first embodiment, or may be made of a material different from that of the metal film MF of the first embodiment. The metal film MF of the second embodiment is, for example, a titanium nitride film, a titanium film, a tantalum nitride film, a tantalum film, a tungsten nitride film, a tungsten film, or an aluminum film, or a laminate film of these.

[0109] Next, a conductive film CF2, a cap film CP1, and a cap film CP2 are sequentially formed on the metal film MF by a film formation process using, for example, a CVD method. The conductive film CF2 is, for example, an n-type polycrystalline silicon film.

[0110] 25, a resist pattern RP6 is formed to cover a portion of the cap film CP2. Next, an anisotropic etching process is performed using the resist pattern RP6 as a mask to remove the cap film CP2, cap film CP1, conductive film CF2, metal film MF, and gate insulating film GI3 exposed from the resist pattern RP6. Next, the resist pattern RP6 is removed by ashing.

[0111] In this manner, a stacked structure LM3 including the gate insulating film GI3, the gate electrode GE3 including the conductive film CF2 and the metal film MF, the cap film CP1, and the cap film CP2 is formed on the semiconductor layer SL.

[0112] Next, as shown in FIG. 26, offset spacers OS1, insulating films IF1, and sidewall spacers SW1 are formed on the side surfaces of the multilayer structure LM3 using a technique similar to that of the first embodiment.

[0113] 27, an epitaxial layer EP is formed on the stacked structure LM3, the insulating film IF1, and the semiconductor layer SL exposed from the sidewall spacer SW1 using a technique similar to that of Embodiment 1. Next, a silicon oxide film OX2 is formed on the surface of the epitaxial layer EP exposed from the sidewall spacer SW1 using a technique similar to that of Embodiment 1.

[0114] 28, the sidewall spacers SW1 and the cap film CP2 of the stacked structure LM3 are removed by anisotropic etching, at which time a part of the surface of the epitaxial layer EP that was in contact with the sidewall spacers SW1 is exposed.

[0115] Next, a silicon oxide film OX1 is formed on the surface of the epitaxial layer EP exposed from the insulating film IF1 and the silicon oxide film OX2. The method for forming the silicon oxide film OX1 is the same as in the first embodiment, such as an ashing process or a thermal oxidation process.

[0116] 29, the insulating film IF1, the silicon oxide film OX1, and the silicon oxide film OX2 are subjected to a cleaning process similar to that of Embodiment 1. Next, ion implantation is performed so as to penetrate the insulating film IF1, the silicon oxide film OX1, and the silicon oxide film OX2, thereby forming n-type extension regions EX1 in the semiconductor layer SL and the epitaxial layer EP.

[0117] In the second embodiment, similarly to the first embodiment, the problem of the metal film MF being dissolved can be solved, and the problem of the epitaxial layer EP, the semiconductor layer SL, and the gate electrode GE3 being partially removed can also be solved, thereby improving the reliability of the semiconductor device.

[0118] Next, as shown in FIG. 30, by using a technique similar to that of the first embodiment, sidewall spacers SW2 and diffusion regions ND are formed, and the silicon oxide film OX2 and cap film CP1 are removed.

[0119] Thereafter, the silicide film SI is formed using the same technique as in the embodiment 1. Through the above manufacturing steps, the MISFET 2Q shown in FIG.

[0120] The present invention has been specifically described above based on the above embodiment, but the present invention is not limited to the above embodiment and can be modified in various ways without departing from the spirit of the present invention.

[0121] For example, although the above embodiment has been described with reference to n-type MISFET1Q and n-type MISFET2Q, the present invention can also be applied to cases where MISFET1Q and MISFET2Q are p-type. In such a case, the conductivity types of the components included in MISFET1Q and MISFET2Q are reversed, for example, the extension region EX1 is a p-type impurity region. [Explanation of symbols]

[0122] 10 SOI substrate 20, 21 Areas of concern 1Q, 2Q MISFET BOX insulation layer CF1, CF2 conductive film CP1, CP2 cap membrane DNW well region (impurity region) EP epitaxial layer EX1, EX2 extension regions (impurity regions) FE ferroelectric film GE1, GE2, GE3 gate electrodes GI1, GI2, GI3 gate insulating film HK high dielectric constant film IF1, IF2 insulating film LM1, LM2, LM3 laminated structure MF metal film MQ ferroelectric memory transistor ND Diffusion region (impurity region) OS1 offset spacer OX1, OX2 silicon oxide film PVF protective film PW1, PW2 Well region (impurity region) RP1, RP2, RP3, RP4, RP5, RP6 resist patterns SI silicide film SL Semiconductor layer STI element isolation section SUB Semiconductor substrate SW1, SW2 sidewall spacers

Claims

1. 1. A method for manufacturing a semiconductor device having a first region in which a first MISFET is formed and a second region in which a second MISFET is formed, comprising: (a) preparing an SOI substrate having a semiconductor substrate, an insulating layer formed on the semiconductor substrate, and a semiconductor layer formed on the insulating layer; (b) after the step (a), forming a first stacked structure in the first region, the first stacked structure including a first gate insulating film, a first gate electrode formed on the first gate insulating film, and a first cap film formed on the first gate electrode; (c) after the step (a), forming a second stacked structure in the second region, the second stacked structure including a second gate insulating film, a metal film formed on the second gate insulating film, a second gate electrode formed on the metal film, and a second cap film formed on the second gate electrode; (d) forming the first insulating film so as to cover the first stacked structure and the second stacked structure after the steps (b) and (c); (e) after the step (d), forming a second insulating film on the first insulating film in the first region and the second region; (f) after the step (e), selectively processing the second insulating film in the first region to form first sidewall spacers on the side surfaces of the first stacked structure via the first insulating film, and removing the first insulating film exposed from the first sidewall spacers; (g) after the step (f), forming an epitaxial layer on the first stacked structure, the first insulating film, and the semiconductor layer exposed from the first sidewall spacer in the first region; (h) after the step (g), removing the first sidewall spacer in the first region and removing the second insulating film in the second region; (i) after the step (h), forming a first silicon oxide film on a surface of the epitaxial layer exposed from the first insulating film in the first region; (j) after the step (i), performing a cleaning process on the first insulating film and the first silicon oxide film using an aqueous solution containing ammonia and an activator, thereby reducing the thickness of each of the first insulating film and the first silicon oxide film; (k) after the step (j), performing ion implantation in the first region so as to penetrate the first insulating film and the first silicon oxide film, thereby forming a first impurity region in the semiconductor layer and the epitaxial layer; A method for manufacturing a semiconductor device, comprising:

2. 2. The method for manufacturing a semiconductor device according to claim 1, The method for manufacturing a semiconductor device, wherein the aqueous solution used in the step (j) does not contain hydrogen peroxide water.

3. 2. The method for manufacturing a semiconductor device according to claim 1, In the step (i), the first silicon oxide film is formed by performing an ashing process.

4. 4. The method for manufacturing a semiconductor device according to claim 3, A method for manufacturing a semiconductor device, wherein the step (i) and the step (j) are repeated a plurality of times, and then the step (k) is performed.

5. 2. The method for manufacturing a semiconductor device according to claim 1, In the step (i), the first silicon oxide film is formed by performing a thermal oxidation treatment.

6. 2. The method for manufacturing a semiconductor device according to claim 1, In the step (d), the first insulating film is formed by a film formation process using a CVD method.

7. 2. The method for manufacturing a semiconductor device according to claim 1, (l) between the step (g) and the step (h), forming a second silicon oxide film on the surface of the epitaxial layer exposed from the first sidewall spacer; Further provided with In the step (i), the first silicon oxide film is formed on the surface of the epitaxial layer exposed from the first insulating film and the second silicon oxide film in the first region; In the step (j), the thickness of the second silicon oxide film is also reduced by the cleaning treatment, In the step (k), the ion implantation is performed so as to penetrate the second silicon oxide film.

8. 2. The method for manufacturing a semiconductor device according to claim 1, (m) selectively removing the semiconductor layer and the insulating layer in the second region after the step (a) and before the steps (b) and (c); Further provided with In the step (b), the first stacked structure is formed on the semiconductor layer located in the first region, In the step (c), the second stacked structure is formed on the semiconductor substrate located in the second region.

9. 2. The method for manufacturing a semiconductor device according to claim 1, The method for manufacturing a semiconductor device, wherein the metal film is a titanium nitride film.

10. 2. The method for manufacturing a semiconductor device according to claim 1, the second stacked structure includes a ferroelectric film formed on the second gate insulating film, the metal film is formed on the ferroelectric film and functions as a part of the second gate electrode; The second MISFET is a ferroelectric memory transistor.

11. (a) preparing an SOI substrate having a semiconductor substrate, an insulating layer formed on the semiconductor substrate, and a semiconductor layer formed on the insulating layer; (b) after the step (a), forming a first stacked structure on the semiconductor layer, the first stacked structure including a first gate insulating film, a first gate electrode including a metal film formed on the first gate insulating film, and a first cap film formed on the first gate electrode; (c) after the step (b), forming the first insulating film so as to cover the first stacked structure; (d) after the step (c), forming a second insulating film on the first insulating film; (e) after the step (d), processing the second insulating film to form first sidewall spacers on the side surfaces of the first stacked structure via the first insulating film, and removing the first insulating film exposed from the first sidewall spacers; (f) after the step (e), forming an epitaxial layer on the first stacked structure, the first insulating film, and the semiconductor layer exposed from the first sidewall spacer; (g) after step (f), removing the first sidewall spacer; (h) after the step (g), forming a first silicon oxide film on the surface of the epitaxial layer exposed from the first insulating film; (i) after the step (h), performing a cleaning process on the first insulating film and the first silicon oxide film using an aqueous solution containing ammonia and an activator, thereby reducing the thickness of each of the first insulating film and the first silicon oxide film; (j) after the step (i), performing ion implantation so as to penetrate the first insulating film and the first silicon oxide film, thereby forming a first impurity region in the semiconductor layer and the epitaxial layer; A method for manufacturing a semiconductor device, comprising:

12. 12. The method for manufacturing a semiconductor device according to claim 11, The method for manufacturing a semiconductor device, wherein the aqueous solution used in the step (i) does not contain hydrogen peroxide water.

13. 13. The method for manufacturing a semiconductor device according to claim 12, In the step (h), the first silicon oxide film is formed by performing an ashing process.

14. 14. The method for manufacturing a semiconductor device according to claim 13, The method for manufacturing a semiconductor device, wherein the step (h) and the step (i) are repeated a plurality of times, and then the step (j) is performed.

15. 12. The method for manufacturing a semiconductor device according to claim 11, In the step (h), the first silicon oxide film is formed by performing a thermal oxidation treatment.

16. 12. The method for manufacturing a semiconductor device according to claim 11, In the step (c), the first insulating film is formed by a film formation process using a CVD method.

17. 12. The method for manufacturing a semiconductor device according to claim 11, (k) forming a second silicon oxide film on the surface of the epitaxial layer exposed from the first sidewall spacer between the steps (f) and (g); Further provided with In the step (h), the first silicon oxide film is formed on the surface of the epitaxial layer exposed from the first insulating film and the second silicon oxide film; In the step (i), the thickness of the second silicon oxide film is also reduced by the cleaning treatment, In the step (j), the ion implantation is performed so as to penetrate the second silicon oxide film.

18. 12. The method for manufacturing a semiconductor device according to claim 11, The method for manufacturing a semiconductor device, wherein the metal film is a titanium nitride film, a titanium film, a tantalum nitride film, a tantalum film, a tungsten nitride film, a tungsten film, or an aluminum film, or a laminate film thereof.

19. 12. The method for manufacturing a semiconductor device according to claim 11, The first gate insulating film includes a high dielectric constant film made of an insulating film having a higher dielectric constant than silicon nitride.

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