Integrated circuit device and oscillator

Abstract

To provide an integrated circuit device capable of reducing the risk of interference between a reference clock signal to be inputted and an output clock signal through a terminal.SOLUTION: An integrated circuit device includes: a clock input terminal which is arranged along a first side, and to which a reference clock signal is inputted; a first power supply voltage input terminal which is arranged along the first side, and to which a first power supply voltage is inputted; a clock output terminal which is arranged along a second side, and from which an output clock signal having a frequency different from the reference clock signal is output; a second power supply voltage input terminal which is arranged along the second side, and to which a second power supply voltage is inputted; a first ground terminal which is arranged along the first side and between the clock input terminal and the first power supply voltage input terminal; and a second ground terminal which is arranged along the second side and between the clock output terminal and the second power supply voltage input terminal.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present invention relates to an integrated circuit device and an oscillator. [Background technology]

[0002] Patent Document 1 describes an integrated circuit in which, in a decimal point division PLL circuit, power supply pads that supply power supply voltage to the integer division circuit, decimal division circuit, phase comparator, and charge pump are provided separately, thereby preventing frequency components that cause spurious emissions from coupling via the power supply lines. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-124630 Summary of the Invention [Problem to be solved by the invention]

[0004] The integrated circuit described in Patent Document 1 can suppress interference noise propagating inside the PLL circuit, but cannot be expected to be effective in suppressing interference via terminals. [Means for solving the problem]

[0005] One aspect of the integrated circuit device according to the present invention is In a plan view, the substrate has a first side and a second side opposite to the first side, a clock input terminal disposed along the first side and receiving a reference clock signal; a first power supply voltage input terminal disposed along the first side and adapted to receive a first power supply voltage that is a source of a power supply voltage supplied to a first circuit that operates at the frequency of the reference clock signal; a clock output terminal disposed along the second side and outputting an output clock signal having a frequency different from that of the reference clock signal; a second power supply voltage input terminal disposed along the second side and receiving a second power supply voltage that is a source of a power supply voltage supplied to a second circuit that operates at the frequency of the output clock signal; a first ground terminal disposed along the first side between the clock input terminal and the first power supply voltage input terminal; and a second ground terminal disposed along the second side between the clock output terminal and the second power supply voltage input terminal.

[0006] One aspect of the oscillator according to the present invention is The present invention includes one aspect of the integrated circuit device. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 2 is a cross-sectional view of the oscillator of the present embodiment. [Figure 2] FIG. 2 is a plan view of the oscillator of the present embodiment. [Figure 3] FIG. 2 is a cross-sectional view showing an inner package and its interior of the oscillator. [Figure 4] FIG. 2 is a cross-sectional view showing a vibrator included in the oscillator. [Figure 5] FIG. 2 is a functional block diagram of the oscillator according to the first embodiment. [Figure 6] FIG. 1 is a diagram showing an example of the configuration of a fractional N-PLL circuit. [Figure 7] FIG. 2 is a diagram showing an example of the configuration of a PLL circuit. [Figure 8] FIG. 2 is a diagram showing the layout configuration of a control IC according to the first embodiment. [Figure 9] FIG. 1 is an explanatory diagram of electromagnetic field coupling. [Figure 10] FIG. 3 is an explanatory diagram of capacitive coupling in the first embodiment. [Figure 11] FIG. 10 is a diagram showing the layout configuration of a control IC according to a second embodiment. [Figure 12] FIG. 10 is an explanatory diagram of capacitive coupling in the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Note that the embodiments described below do not unduly limit the content of the present invention as defined in the claims. Furthermore, not all of the configurations described below are necessarily essential components of the present invention.

[0009] 1. First embodiment 1-1. Oscillator structure Fig. 1 is a cross-sectional view showing an oscillator of this embodiment. Fig. 2 is a plan view of the oscillator seen from above. Fig. 3 is a cross-sectional view showing an inner package and its interior of the oscillator. Fig. 4 is a cross-sectional view showing a resonator of the oscillator.

[0010] 1 and 2 is an oven-controlled crystal oscillator, and includes an outer package 2, an inner package 3, a control IC 4, and a resonator 5. The inner package 3, the control IC 4, and the resonator 5 are housed in the outer package 2.

[0011] 1, the outer package 2 has an outer base 21 and an outer lid 22. The outer base 21 has a substrate 27, a frame-shaped wall portion 28 standing upward from the edge of the upper surface of the substrate 27, and frame-shaped leg portions 29 standing downward from the edge of the lower surface of the substrate 27. The upper surface of the substrate 27 and the wall portion 28 form an upper recess 211 that opens to the upper surface 21a of the outer base 21, and the lower surface of the substrate 27 and the leg portions 29 form a lower recess 212 that opens to the lower surface 21b of the outer base 21. Therefore, the outer base 21 is approximately H-shaped in cross section.

[0012] The upper recess 211 has a first upper recess 211a that opens to the top surface 21a, a second upper recess 211b that opens to the bottom surface of the first upper recess 211a and has a smaller opening than the first upper recess 211a, and a third upper recess 211c that opens to the bottom surface of the second upper recess 211b and has a smaller opening than the second upper recess 211b. The control IC 4 is disposed on the bottom surface of the first upper recess 211a, and the inner package 3 is disposed on the bottom surface of the third upper recess 211c.

[0013] The outer lid 22 is bonded to the upper surface 21a of the outer base 21 via a sealing member 23 such as a seal ring or low-melting-point glass so as to close the opening of the upper recess 211. This hermetically seals the upper recess 211, forming an outer accommodating space S2 as an accommodating space within the outer package 2. On the other hand, the opening of the lower recess 212 is not sealed and faces the outside of the outer package 2. The inner package 3 and the control IC 4 are housed in the outer accommodating space S2, and the vibrator 5 is disposed in the lower recess 212.

[0014] The outer base 21 is provided with a plurality of internal terminals 241 arranged on the bottom surface of the first upper recess 211a, a plurality of internal terminals 242 arranged on the bottom surface of the second upper recess 211b, a plurality of internal terminals 243 arranged on the bottom surface of the lower recess 212, and a plurality of external terminals 244 arranged on the bottom surface 21b, i.e., the top surfaces of the legs 29. Each internal terminal 241 is electrically connected to the control IC 4 via a bonding wire BW1, each internal terminal 242 is electrically connected to the inner package 3 via a bonding wire BW2, and each internal terminal 243 is electrically connected to the vibrator 5 via a conductive bonding member B1.

[0015] These terminals 241, 242, 243, and 244 are electrically connected as appropriate via internal wiring 25 formed within the outer base 21, electrically connecting the control IC 4, the inner package 3, the vibrator 5, and the external terminal 244. The internal wiring 25 passes through the inside of the leg 29 and is connected to the external terminal 244. The external terminal 244 is then connected to an external device (not shown). Side terminals 245 connected to the external terminal 244 are disposed on the side surfaces of the leg 29. The side terminals 245 are castellated. Therefore, the solder H wets and spreads on the side terminals 245, forming fillets, thereby strengthening the mechanical and electrical connection with the external device. However, this is not limited thereto, and for example, the side terminals 245 may be omitted.

[0016] 3, the inner package 3 has an inner base 31 and an inner lid 32. The inner base 31 has a recess 311 that opens to a lower surface 31b.

[0017] The recess 311 has a first recess 311a that opens to the lower surface 31b, a second recess 311b that opens to the bottom surface of the first recess 311a and has a smaller opening than the first recess 311a, and a third recess 311c that opens to the bottom surface of the second recess 311b and has a smaller opening than the second recess 311b. The vibration element 6 is disposed on the bottom surface of the first recess 311a, and the heat-generating IC 7 and the oscillation IC 8 are disposed on the bottom surface of the third recess 311c, aligned in the X-axis direction.

[0018] The inner lid 32 is bonded to the lower surface 31b of the inner base 31 via a sealing member 33 such as a seal ring or low-melting-point glass so as to close the opening of the recess 311. This hermetically seals the recess 311, and forms an inner accommodating space S3 within the inner package 3. The resonator element 6, the heat-generating IC 7, and the oscillation IC 8 are accommodated in the inner accommodating space S3.

[0019] Such an inner accommodating space S3 is airtight and in a reduced pressure state, preferably a state closer to a vacuum, thereby reducing the viscous resistance of the inner accommodating space S3 and improving the vibration characteristics of the vibration element 6. However, the atmosphere of the inner accommodating space S3 is not particularly limited.

[0020] The inner base 31 is provided with a plurality of internal terminals 341 arranged on the bottom surface of the first recess 311a, a plurality of internal terminals 342 and 343 arranged on the bottom surface of the second recess 311b, and a plurality of external terminals 344 arranged on the upper surface 31a of the inner base 31. Each internal terminal 341 is electrically connected to the vibration element 6 via a conductive bonding member B2 and a bonding wire BW3, each internal terminal 342 is electrically connected to the heat-generating IC 7 via a bonding wire BW4, and each internal terminal 343 is electrically connected to the oscillation IC 8 via a bonding wire BW5.

[0021] These terminals 341, 342, 343, and 344 are electrically connected as appropriate via internal wiring (not shown) formed within the inner package 3, and electrically connect the vibrating element 6, the heat-generating IC 7, the oscillation IC 8, and the external terminal 344. In such an inner package 3, the inside and outside are electrically connected via the external terminal 344.

[0022] The inner package 3 as described above is fixed at the inner lid 32 to the bottom surface of the third upper recess 211c via a joining member B3 having a sufficiently low thermal conductivity.

[0023] 3, the heat-generating IC 7 is placed on the bottom surface of the third recess 311c with its active surface facing downward (toward the inner lid 32) and is electrically connected to multiple internal terminals 342 via bonding wires BW4. The oscillation IC 8 is placed on the bottom surface of the third recess 311c with its active surface facing downward (toward the inner lid 32) and is electrically connected to multiple internal terminals 343 via bonding wires BW5.

[0024] As shown in FIG. 4, the vibrator 5 has a package 51 and a vibrating element 55 housed in the package 51.

[0025] The package 51 has a base 52 and a lid 53. The base 52 has a recess 521 that opens to a lower surface 52b. The vibration element 55 is disposed on the bottom surface of the recess 521.

[0026] The lid 53 is bonded to the lower surface 52b of the base 52 via a sealing member 54 such as a seal ring or low-melting-point glass so as to close the opening of the recess 521. This hermetically seals the recess 521, forming an accommodation space S5 within the package 51. The vibration element 55 is accommodated in the accommodation space S5. The accommodation space S5 is airtight and in a reduced pressure state, preferably closer to a vacuum. This reduces the viscous resistance of the accommodation space S5, improving the vibration characteristics of the vibration element 55. However, the atmosphere of the accommodation space S5 is not particularly limited.

[0027] The base 52 is provided with a plurality of internal terminals 561 arranged on the bottom surface of the recess 521 and a plurality of external terminals 564 arranged on the upper surface 52a of the base 52. Each internal terminal 561 is electrically connected to the vibration element 55 via a conductive bonding member B4. These terminals 561, 564 are electrically connected as appropriate via internal wiring (not shown) formed within the base 52, electrically connecting the vibration element 55 and the external terminals 564. In such a package 51, the inside and outside are electrically connected via the external terminals 564.

[0028] The vibration element 55 is an AT-cut quartz crystal vibration element. However, the vibration element 55 does not have to be an AT-cut quartz crystal vibration element, and may be, for example, an SC-cut quartz crystal vibration element, a BT-cut quartz crystal vibration element, a tuning fork-type quartz crystal vibration element, a surface acoustic wave resonator, other piezoelectric vibration elements, a MEMS resonator, or the like.

[0029] 4, the vibrator 5 is fixed to the bottom surface of the lower recess 212 via a conductive bonding member B1. Furthermore, the external terminal 564 and the internal terminal 243 are electrically connected via the bonding member B1.

[0030] 1-2. Functional configuration of the oscillator Fig. 5 is a functional block diagram of the oscillator 1 of the first embodiment. In Fig. 5, the same components as those shown in Figs. 1 to 4 are denoted by the same reference numerals. As shown in Fig. 5, the oscillator 1 of the first embodiment includes a control IC 4, a vibrator 5, a vibrating element 6, a heat-generating IC 7, and an oscillation IC 8.

[0031] The oscillation IC 8 includes an oscillation circuit 81 and a temperature sensor 82, and operates by receiving a power supply voltage VOSC from the control IC 4. The oscillation circuit 81 is electrically connected to both ends of the vibration element 6, and is a circuit that oscillates the vibration element 6 by amplifying the output signal of the vibration element 6 and feeding it back to the vibration element 6, and outputs a reference clock signal CLKIN, which is a clock signal based on the oscillation signal. In other words, the oscillation circuit 81 oscillates the frequency f of the reference clock signal CLKIN. CLKINThe oscillator circuit 81 is a circuit that operates in accordance with the above-described principle. For example, the oscillator circuit 81 may be an oscillator circuit that uses an inverter as an amplifying element, or an oscillator circuit that uses a bipolar transistor as an amplifying element. The reference clock signal CLKIN output from the oscillator circuit 81 is input to the control IC 4.

[0032] The temperature sensor 82 is a thermosensitive element that detects temperature and outputs a temperature detection signal TS1 having a voltage level corresponding to the detected temperature. The temperature sensor 82 is built into the oscillator IC 8 and detects the temperature of the oscillator IC 8. The temperature detection signal TS1 output from the temperature sensor 82 is input to the control IC 4. The temperature sensor 82 may be, for example, a sensor that utilizes the temperature dependency of the forward voltage of a PN junction of a diode.

[0033] The heat-generating IC 7 includes a temperature control element 71 and a temperature sensor 72. The temperature control element 71 is an element that controls the temperature of the vibration element 6 based on a temperature control signal OVC output from the control IC 4, and may be a heat-generating element. For example, the temperature control element 71 is a CMOS transistor, and the amount of heat generated varies depending on the voltage of the temperature control signal OVC input to its gate. The greater the amount of heat generated by the temperature control element 71, the higher the temperature of the vibration element 6. The control IC 4 controls the amount of heat generated by the temperature control element 71 so that the temperature of the vibration element 6 remains constant at a target set temperature. For example, the set temperature may be a fixed value such as 80°C, or may be freely settable within a predetermined range, such as a range of 70°C to 125°C.

[0034] The temperature sensor 72 is a thermosensitive element that detects temperature and outputs a temperature detection signal TS2 having a voltage level corresponding to the detected temperature. The temperature sensor 72 is built into the heat-generating IC 7 and detects the temperature of the heat-generating IC 7. Because the heat-generating IC 7 also has a built-in temperature control element 71, the temperature sensor 72 detects the temperature of the temperature control element 71. The temperature detection signal TS2 output from the temperature sensor 72 is input to the control IC 4. The temperature sensor 72 may be, for example, a sensor that utilizes the temperature dependency of the forward voltage of a PN junction of a diode.

[0035] As shown in FIG. 3 , the resonator element 6, the heat-generating IC 7, and the oscillation IC 8 are housed in an inner package 3, and the control IC 4 controls the heat generation of the heat-generating IC 7 so that the temperature of the resonator element 6 remains constant. The heat-generating IC 7 is a heat source, and radiant heat from the heat-generating IC 7 is transmitted to the resonator element 6 and the oscillation IC 8, resulting in a difference between the temperatures of the resonator element 6 and the oscillation IC 8 and the heat-generating IC 7. In contrast, the resonator element 6 and the oscillation IC 8 are spaced apart from the heat-generating IC 7. If the thermal distance between the heat-generating IC 7 and the resonator element 6 is considered to be approximately the same as the thermal distance between the heat-generating IC 7 and the oscillation IC 8, the temperature of the oscillation IC 8 can be said to be closer to the temperature of the resonator element 6. In other words, the temperature detected by the temperature sensor 82 built into the oscillation IC 8 is closer to the temperature of the resonator element 6 than the temperature detected by the temperature sensor 72 built into the heat-generating IC 7. Therefore, as described below, the control IC 4 controls the heat generation of the heat-generating IC 7 based on a temperature detection signal TS1 output from the temperature sensor 82. However, depending on the arrangement of the vibration element 6, the heat-generating IC 7, and the oscillation IC 8, the temperature of the heat-generating IC 7 may be closer to the temperature of the vibration element 6 than the temperature of the oscillation IC 8. In such a case, the control IC 4 may control the heat generation of the heat-generating IC 7 based on the temperature detection signal TS2 output from the temperature sensor 72.

[0036] The control IC 4 operates by receiving a first power supply voltage VDD1, a second power supply voltage VDD2, and a ground voltage VSS from an external device. The control IC 4 includes a microcontroller 40, a selector 41, a temperature sensor 42, an A / D conversion circuit 43, a D / A conversion circuit 44, a fractional N-PLL circuit 45, a PLL circuit 46, a switch circuit 47, an interface circuit 49, LDO regulators 61 to 67, a memory 90, and a register 94. PLL stands for Phase Locked Loop. LDO stands for Low Drop Out.

[0037] The LDO regulator 61 is a power supply circuit that generates a power supply voltage VOSC, which is a constant voltage lower than the first power supply voltage VDD1, based on the first power supply voltage VDD1 supplied from outside the oscillator 1. The power supply voltage VOSC is supplied to an oscillation circuit 81 of the oscillation IC 8.

[0038] The LDO regulator 62 is a power supply circuit that generates a power supply voltage VPFD, which is a constant voltage lower than the first power supply voltage VDD1, based on the first power supply voltage VDD1. The power supply voltage VPFD ​​is supplied to the fractional N-PLL circuit 45.

[0039] The LDO regulator 63 is a power supply circuit that generates a power supply voltage VCP, which is a constant voltage lower than the second power supply voltage VDD2, based on the second power supply voltage VDD2 supplied from outside the oscillator 1. The power supply voltage VCP is supplied to the fractional N-PLL circuit 45.

[0040] The LDO regulator 64 is a power supply circuit that generates a power supply voltage VBUF, which is a constant voltage lower than the second power supply voltage VDD2, based on the second power supply voltage VDD2. The power supply voltage VBUF is supplied to the fractional N-PLL circuit 45.

[0041] The LDO regulator 65 is a power supply circuit that generates a power supply voltage VDIV, which is a constant voltage lower than the second power supply voltage VDD2, based on the second power supply voltage VDD2. The power supply voltage VDIV is supplied to the fractional N-PLL circuit 45.

[0042] The LDO regulator 66 is a power supply circuit that generates a power supply voltage VVCO, which is a constant voltage lower than the second power supply voltage VDD2, based on the second power supply voltage VDD2. The power supply voltage VVCO is supplied to the PLL circuit 46.

[0043] The LDO regulator 67 is a power supply circuit that generates a power supply voltage VPLL, which is a constant voltage lower than the second power supply voltage VDD2, based on the second power supply voltage VDD2. The power supply voltage VPLL is supplied to the PLL circuit 46.

[0044] The fractional N-PLL circuit 45 receives the reference clock signal CLKIN output from the oscillation IC 8 and converts the frequency of the reference clock signal CLKIN to a frequency f CLKIN is divided by the frequency f according to the division ratio indicated by the division ratio control signal DIVC. CK1 The clock signal CK1 converted into the above is generated and output.

[0045] Fig. 6 is a diagram showing an example of the configuration of the fractional N-PLL circuit 45. As shown in Fig. 6, the fractional N-PLL circuit 45 includes a phase comparator 111, a charge pump 112, a low-pass filter 113, a voltage-controlled oscillator circuit 114, a buffer circuit 115, and a frequency divider circuit 116.

[0046] The phase comparator 111 operates by receiving a power supply voltage VPFD, and the charge pump 112 operates by receiving a power supply voltage VCP. The low-pass filter 113, voltage-controlled oscillator circuit 114, and buffer circuit 115 operate by receiving a power supply voltage VBUF. The frequency divider circuit 116 operates by receiving a power supply voltage VDIV.

[0047] The phase comparator 111 compares the phase of the reference clock signal CLKIN with that of the clock signal FBCLK output by the frequency divider circuit 116, and outputs the comparison result as a pulse voltage.

[0048] The charge pump 112 converts the pulse voltage output by the phase comparator 111 into a current, and the low-pass filter 113 smoothes and voltage-converts the current output by the charge pump 112 .

[0049] The voltage controlled oscillator circuit 114 outputs an oscillation signal whose frequency changes according to the output voltage of the low pass filter 113. The voltage controlled oscillator circuit 114 can be realized as various types of oscillation circuits, such as an LC oscillation circuit configured using an inductance element such as a coil and a capacitance element such as a capacitor, or an oscillation circuit using a piezoelectric oscillator such as a quartz oscillator.

[0050] The buffer circuit 115 buffers the oscillation signal output from the voltage controlled oscillation circuit 114 and outputs the clock signal CK1.

[0051] The frequency divider circuit 116 outputs a clock signal FBCLK obtained by dividing the clock signal CK1 output by the buffer circuit 115 using the value of the frequency division ratio control signal DIVC as the frequency division ratio.

[0052] The fractional N-PLL circuit 45 configured in this way generates the clock signal CK1 by performing feedback control so that the phase of the reference clock signal CLKIN coincides with the phase of the signal obtained by dividing the clock signal CK1 by the division ratio specified by the division ratio control signal DIVC. The division ratio control signal DIVC is delta-sigma modulated, and the division ratio specified by the division ratio control signal DIVC switches between multiple integer division ratios, and becomes a fractional division ratio when averaged. Therefore, the frequency f CK1 is the frequency f CLKIN The fractional N-PLL circuit 45 controls the frequency f CLKIN Unlike the frequency f CK1 Alternatively, the clock signal CK1 may be output.

[0053] Returning to the explanation of FIG. 5, the PLL circuit 46 receives the clock signal CK1 output from the fractional N-PLL circuit 45 and converts the frequency of the clock signal CK1 to a frequency f CK1 The frequency f is the same as CK2 The clock signal CK2 is generated and output.

[0054] 7 is a diagram showing an example of the configuration of the PLL circuit 46. As shown in FIG. 7, the PLL circuit 46 includes a phase comparator 121, a charge pump 122, a low-pass filter 123, an oscillation circuit 124, and a buffer circuit 125.

[0055] The phase comparator 121, the charge pump 122, the low-pass filter 123, and the buffer circuit 125 are supplied with a power supply voltage VPLL to operate, while the oscillator circuit 124 is supplied with a power supply voltage VVCO to operate.

[0056] The phase comparator 121 compares the phase of the clock signal CK1 with that of the clock signal CK2 output by the buffer circuit 125, and outputs the comparison result as a pulse voltage.

[0057] The charge pump 122 converts the pulse voltage output by the phase comparator 121 into a current, and the low-pass filter 123 smoothes and voltage-converts the current output by the charge pump 122.

[0058] The oscillator circuit 124 generates a frequency f CK2 Specifically, the oscillation circuit 124 is connected to the vibrator 5, and causes the vibrator 5 to oscillate, thereby generating an oscillation signal VO_XI having a frequency corresponding to the output voltage of the low-pass filter 123. That is, the oscillation circuit 124 amplifies the oscillation signal VO_XI output from the vibrator 5 to output the amplified oscillation signal VO_XO to the vibrator 5, causing the vibrator 5 to continue oscillating.

[0059] The buffer circuit 125 buffers the oscillation signal VO_XI generated by the oscillation circuit 124 to generate a signal having a frequency f CK2 As will be described later, during normal operation of the oscillator 1, the clock signal CK2 is selected as the output clock signal OUT, and therefore the buffer circuit 125 outputs the output clock signal OUT.

[0060] In this way, the vibrator 5 and the oscillation circuit 124 constitute a voltage-controlled oscillator 9 whose oscillation frequency changes in accordance with the output voltage of the low-pass filter 123 .

[0061] The PLL circuit 46 configured in this manner receives the clock signal CK1 output from the fractional N-PLL circuit 45 and synchronizes the phase of the clock signal CK2 with the clock signal CK1. That is, the PLL circuit 46 feedback-controls the output voltage of the low-pass filter 123 so that the phases of the clock signals CK1 and CK2 coincide with each other, thereby synchronizing the frequency f of the clock signal CK1. CK1 The frequency f is the same as CK2 The clock signal CK2 is generated and output.

[0062] Returning to the explanation of FIG. 5, the clock signal CK1 output from the fractional N-PLL circuit 45 has a frequency f CK1 is the frequency f of the reference clock signal CLKIN CLKIN On the other hand, the clock signal CK2 output from the PLL circuit 46 has a frequency f CK2 is the frequency f of the clock signal CK1 CK1 Since the clock signal CK1 is generated by oscillating the oscillator 5, which has high frequency stability, it has smaller jitter than the clock signal CK1.

[0063] The switch circuit 47 selects either the clock signal CK1 or the clock signal CK2 and outputs the output clock signal OUT in accordance with the logic level of the switch control signal SWC output from the register 94. The output clock signal OUT is output to the outside of the oscillator 1. The output clock signal OUT may be supplied to an external device 100, or may be supplied to a device different from the external device 100. For example, during normal operation of the oscillator 1, the clock signal CK2 with small jitter may be selected as the output clock signal OUT, and when inspecting the clock signal CK1, the clock signal CK1 may be selected as the output clock signal OUT.

[0064] The temperature sensor 42 is a thermosensor that detects temperature and outputs a temperature detection signal TS3 having a voltage level corresponding to the detected temperature. The temperature sensor 42 is built into the control IC 4 and detects the temperature of the control IC 4. As shown in FIG. 1, the control IC 4 is located close to the outer lid 22. The distance between the vibration element 6 and the temperature sensor 42 is greater than the distance between the vibration element 6 and the temperature sensor 82 included in the oscillation IC 8. Therefore, the temperature of the control IC 4 is easily affected by the ambient temperature of the oscillator 1. Therefore, assuming that the amount of heat generated by the control IC 4 is approximately constant, the temperature sensor 42 can detect changes in the ambient temperature of the oscillator 1. The temperature detection signal TS2 output from the temperature sensor 72 is input to the control IC 4. The temperature sensor 72 may be, for example, a sensor that utilizes the temperature dependence of the forward voltage of a PN junction of a diode.

[0065] The selector 41 selects and outputs one of the temperature detection signal TS1 output from the oscillation IC 8, the temperature detection signal TS2 output from the heat generation IC 7, and the temperature detection signal TS3 output from the temperature sensor 42. In this embodiment, the selector 41 selects and periodically outputs the temperature detection signals TS1, TS2, and TS3 in a time-division manner.

[0066] The A / D conversion circuit 43 converts the voltages of the temperature detection signals TS1, TS2, and TS3, which are analog signals output in a time-division manner from the selector 41, into temperature codes DTS1, DTS2, and DTS3, which are digital signals. The A / D conversion circuit 43 may convert the voltage levels of the temperature detection signals TS1, TS2, and TS3 using resistor voltage division or the like, and then convert them into the temperature codes DTS1, DTS2, and DTS3.

[0067] The microcontroller 40 includes a CPU 10 and a memory 15. CPU stands for Central Processing Unit. Temperature control data 91 and temperature compensation data 92 are stored in a non-volatile memory 90, and are transferred to the memory 15 when the oscillator 1 is started. The non-volatile memory 90 also stores a temperature control program and a temperature compensation program (not shown), and are transferred to the memory 15 when the oscillator 1 is started.

[0068] The CPU 10 functions as a temperature control circuit 11 by executing a temperature control program transferred to the memory 15. The temperature control circuit 11 controls the operation of the temperature control element 71 built into the heat-generating IC 7. Specifically, the temperature control circuit 11 outputs a temperature control code DOVC for controlling the heat generation amount of the temperature control element 71 based on the temperature code DTS1 and temperature control data 91 transferred to the memory 15 and stored therein. For example, the temperature control data 91 may include information on a set temperature that is a target temperature for the vibration element 6 and information on a gain for controlling the heat generation amount of the temperature control element 71. Alternatively, if the set temperature that is a target temperature for the vibration element 6 varies depending on the outside air temperature, the temperature control data 91 may include information indicating the relationship between the temperature code DTS3 and the set temperature. In this case, the temperature control circuit 11 outputs the temperature control code DOVC based on the temperature codes DTS1 and DTS3 and the temperature control data 91.

[0069] The CPU 10 functions as a temperature compensation circuit 12 by executing a temperature compensation program transferred to the memory 15. The temperature compensation circuit 12 temperature-compensates the frequency of the reference clock signal CLKIN, which is generated by the oscillation circuit 81 built into the oscillation IC 8 causing the vibration element 6 to oscillate. Specifically, the temperature compensation circuit 12 outputs a division ratio control signal DIVC to the fractional N-PLL circuit 45, causing the fractional N-PLL circuit 45 to output a clock signal CK1 whose frequency remains constant regardless of temperature, based on the temperature code DTS3 and temperature compensation data 92 transferred to the memory 15. For example, the temperature compensation data 92 may be table information indicating the relationship between the temperature code DTS3 and the frequency of the reference clock signal CLKIN, or may be information on coefficient values ​​of each order of a mathematical equation indicating this relationship. Alternatively, the temperature compensation data 92 may be information indicating the relationship between the temperature code DTS3 and the fractional division ratio of the fractional N-PLL circuit 45, calculated from the relationship between the temperature code DTS3 and the frequency of the reference clock signal CLKIN.

[0070] The D / A conversion circuit 44 converts the temperature control code DOVC, which is a digital signal output from the temperature control circuit 11, into a temperature control signal OVC, which is an analog signal. The temperature control signal OVC is supplied to the temperature control element 71 of the heat generation IC 7.

[0071] The interface circuit 49 is a circuit for performing data communication between the oscillator 1 and an external device 100 connected thereto. Specifically, the interface circuit 49 writes and reads data to and from the memory 90, the register 94, or the memory 15 of the microcontroller 40 in response to a request from the external device 100. The interface circuit 49 is, for example, 2 It may be an interface circuit compatible with the C bus or an interface circuit compatible with the SPI bus. 2 C stands for Inter-Integrated Circuit, and SPI stands for Serial Peripheral Interface.

[0072] In an inspection process during manufacturing of oscillator 1, the inspection device, which is external device 100, may set a switch control signal SWC via interface circuit 49 to cause switch circuit 47 to select clock signal CK1, and inspect clock signal CK1. The inspection device, which is external device 100, may also write temperature control data 91 and temperature compensation data 92, and further write a temperature control program and a temperature compensation program, to memory 90 via interface circuit 49. The temperature control data 91 and temperature compensation data 92 may also be set in register 94 by external device 100 when oscillator 1 is started.

[0073] 1-3.Control IC layout configuration As mentioned above, the frequency of the clock signal CK1 is f CK1 is the frequency of the reference clock signal CLKIN CLKIN is a non-integer multiple of the frequency f of the clock signal CK2. CK2 is the frequency f of the clock signal CK1 CK1 During normal operation, the clock signal CK2 is selected as the output clock signal OUT, so that the frequency f of the reference clock signal CLKIN input to the control IC 4 is CLKIN and the frequency f of the output clock signal OUT from control IC4 CK2 Therefore, the frequency f CLKIN signal and frequency f CK2 Interference occurs between the signal at frequency f CLKIN and frequency f CK2 Therefore, in this embodiment, the layout configuration of the control IC 4 is devised to reduce this spurious noise.

[0074] FIG. 8 is a diagram showing the layout configuration of the control IC 4 in the first embodiment. FIG. 8 shows only the arrangement of some pads and the like necessary for explanation. As shown in FIG. 8, the control IC 4 includes a semiconductor substrate 400. In a plan view, the semiconductor substrate 400 has a first side 401, a second side 402 opposite the first side 401, a third side 403 intersecting the first side 401 and the second side 402, and a fourth side 404 opposite the third side 403. The control IC 4 and the semiconductor substrate 400 have substantially the same outline in a plan view. Therefore, it can be said that the control IC 4 has the first side 401, the second side 402, the third side 403, and the fourth side 404 in a plan view.

[0075] Pads P1, P2, P3, P4, and P5 are arranged on the semiconductor substrate 400 along a first side 401. The pad P1 is a clock input terminal to which a reference clock signal CLKIN is input. The pad P2 is a ground terminal to which a ground voltage VSS is supplied. The pad P3 is a power supply voltage input terminal to which a first power supply voltage VDD1, which is the source of the power supply voltage VOSC supplied to the oscillation circuit 81, is input. The pad P4 is a ground terminal to which the ground voltage VSS is supplied. The pad P5 is a power supply voltage output terminal that outputs the power supply voltage VOSC. The pads P1, P2, P3, P4, and P5 are arranged in this order along the first side 401.

[0076] Additionally, pads P6, P7, P8, P9, P10, and P11 are arranged on the semiconductor substrate 400 along the second side 402. The pad P6 is a power supply voltage input terminal to which a second power supply voltage VDD2, which is the source of the power supply voltages VVCO and VPLL supplied to the PLL circuit 46, is input. The pad P7 is a ground terminal to which a ground voltage VSS is supplied. The pad P8 is a clock output terminal to which an output clock signal OUT having a frequency different from that of the reference clock signal CLKIN is output. The pad P9 is a ground terminal to which a ground voltage VSS is supplied. The pad P10 is a first oscillator terminal connected to the oscillator 5, the oscillation circuit 124, and the buffer circuit 125. The pad P11 is a second oscillator terminal connected to the oscillator 5 and the oscillation circuit 124. That is, the oscillation signal VO_XI output from the vibrator 5 is input to the oscillation circuit 124 and the buffer circuit 125 via the pad P10, which is the first vibrator terminal, and the oscillation signal VO_XO amplified by the oscillation circuit 124 is input to the vibrator 5 via the pad P11, which is the second vibrator terminal. Then, along the second side 402, the pads P6, P7, P8, P9, P10, and P11 are arranged in this order.

[0077] Thus, the frequency f CLKIN Pad P1 to which a reference clock signal CLKIN of frequency f CK2 The pad P8 from which the output clock signal OUT of the frequency f CLKIN The fractional N-PLL circuit 45 to which the reference clock signal CLKIN of frequency f is input is provided at a position closer to the first side 401 than to the second side 402. CK2 The PLL circuit 46 that outputs the clock signal CK2 of frequency f is provided closer to the second side 402 than to the first side 401. CLKIN A first power supply voltage VDD1 is the source of a power supply voltage VOSC supplied to an oscillator circuit 81 operating at a frequency f CK2The second power supply voltage VDD2, which is the source of the power supply voltages VVCO and VPLL supplied to the PLL circuit 46 operating at a frequency f, is input from two different pads P2 and P5, respectively, and the pads P2 and P5 are located at separate positions. CLKIN The layout area of ​​the circuit that operates at frequency f CK2 Since the placement area of ​​the circuit operating at frequency f is separated as much as possible, CLKIN signal and frequency f CK2 This reduces spurious noise caused by interference with other signals.

[0078] Furthermore, along the first side 401, pad P2, which is a ground terminal, is disposed between pad P1, which is a clock input terminal, and pad P3, which is a power supply voltage input terminal. That is, since pad P2, which is a ground terminal, is disposed next to pad P1, which is a clock input terminal, as shown in FIG. 9, the magnetic field generated by current I1 due to charging and discharging when the reference clock signal CLKIN is input to pad P1 is weakened by the magnetic field generated by current I2 flowing to ground via pad P2. This reduces the electromagnetic field coupling between the node to which the reference clock signal CLKIN is input and the node of the first power supply voltage VDD1, and the induced current I3 flowing to the node of the first power supply voltage VDD1 due to electromagnetic induction based on this magnetic field is reduced, thereby reducing the fluctuation of the first power supply voltage VDD1. Furthermore, pad P2, which is a ground terminal, reduces the capacitive coupling between pad P1 and pad P3, so that the frequency f based on the reference clock signal CLKIN is reduced to the first power supply voltage VDD1. CLKIN This makes it difficult for noise to be superimposed.

[0079] Additionally, along the first side 401, pads P2 and P4, which are ground terminals, are arranged between pad P5, which is the power supply voltage output terminal, and pad P1, which is the clock input terminal. Therefore, the magnetic field generated by the current due to charging and discharging when the reference clock signal CLKIN is input to pad P1 is weakened by the magnetic field generated by the current flowing to ground via pads P2 and P4. This reduces the electromagnetic field coupling between the node to which the reference clock signal CLKIN is input and the node of the power supply voltage VOSC, and the induced current flowing to the node of the power supply voltage VOSC due to electromagnetic induction based on this magnetic field is reduced, thereby reducing the fluctuation of the power supply voltage VOSC.

[0080] Additionally, along the first side 401, pad P4, which is a ground terminal, is disposed between pad P5, which is a power supply voltage output terminal, and pad P3, which is a power supply voltage input terminal. Therefore, the magnetic field generated by the current based on the fluctuations in the power supply voltage VOSC and the magnetic field generated by the current based on the fluctuations in the first power supply voltage VDD1 are weakened by the magnetic field generated by the current flowing to ground. This reduces the electromagnetic field coupling between the node of the first power supply voltage VDD1 and the node of the power supply voltage VOSC, and the induced current flowing through the node of the first power supply voltage VDD1 and the node of the power supply voltage VOSC due to electromagnetic induction based on the magnetic field is reduced, thereby reducing the fluctuations in the power supply voltage VOSC and the first power supply voltage VDD1.

[0081] Furthermore, since pads P2 and P4, which are ground terminals, are arranged on both sides of pad P3, which is a power supply voltage input terminal, along first side 401, the magnetic field generated by the current based on fluctuations in the first power supply voltage VDD1 is weakened by the magnetic field generated by the current flowing to ground. As a result, the electromagnetic field coupling between the node of the first power supply voltage VDD1 and each node inside control IC4 is reduced, and the fluctuations of each node are reduced.

[0082] Furthermore, along the second side 402, pad P7, which is a ground terminal, is arranged between pad P8, which is a clock output terminal, and pad P6, which is a second power supply voltage input terminal. In other words, because pad P7, which is a ground terminal, is arranged next to pad P8, which is a clock output terminal, the magnetic field generated by the current due to charging and discharging when the output clock signal OUT is output from pad P8 is weakened by the magnetic field generated by the current flowing to ground via pad P7. As a result, the electromagnetic field coupling between the node from which the output clock signal OUT is output and the node of the second power supply voltage VDD2 is reduced, and the induced current flowing to the node of the second power supply voltage VDD2 due to electromagnetic induction based on the magnetic field is reduced, and the frequency f superimposed on the second power supply voltage VDD2 is reduced. CK2 Furthermore, since the pad P7, which is a ground terminal, reduces the capacitive coupling between the pads P6 and P8, the frequency f based on the output clock signal OUT is applied to the second power supply voltage VDD2. CK2 This makes it difficult for noise to be superimposed.

[0083] Additionally, pad P9, which is a ground terminal, is disposed between pad P10, which is a first oscillator terminal, and pad P8, which is a clock output terminal, along second side 402. Therefore, the magnetic field generated by the current due to charging and discharging when the output clock signal OUT is output from pad P8 is weakened by the magnetic field generated by the current flowing to ground via pad P9. This reduces the electromagnetic field coupling between the node from which the output clock signal OUT is output and the node to which the oscillation signal VO_XI is input, and the induced current flowing to the node to which VO_XI is input due to electromagnetic induction based on the magnetic field is reduced, thereby reducing the fluctuation of the oscillation signal VO_XI.

[0084] Additionally, along the second side 402, pads P7 and P9, which are ground terminals, are disposed between pad P10, which is the first vibrator terminal, and pad P6, which is the power supply voltage input terminal. Therefore, the magnetic field generated by the current based on the fluctuations of the oscillation signal VO_XI and the magnetic field generated by the current based on the fluctuations of the second power supply voltage VDD2 are weakened by the magnetic field generated by the current flowing to ground. This reduces the electromagnetic field coupling between the node of the second power supply voltage VDD2 and the node to which the oscillation signal VO_XI is input, and electromagnetic induction based on this magnetic field reduces the induced current flowing to the node of the second power supply voltage VDD2 and the node to which the oscillation signal VO_XI is input, thereby reducing the fluctuations of the oscillation signal VO_XI and the second power supply voltage VDD2.

[0085] Additionally, since pad P7, which is a ground terminal, is located next to pad P6, which is a power supply voltage input terminal, along second side 402, the magnetic field generated by the current due to fluctuations in second power supply voltage VDD2 is weakened by the magnetic field generated by the current flowing to ground. As a result, the electromagnetic field coupling between the node of second power supply voltage VDD2 and each node inside control IC 4 is reduced, and the fluctuations of each node are reduced.

[0086] 8, the LDO regulator 61 that outputs the power supply voltage VOSC is located close to the pad P5. Therefore, the wiring 411 from the output of the LDO regulator 61 to the pad P5 is short, reducing its impedance, and the inverse PSNR characteristics of the LDO regulator 61 reduce noise propagating from the node of the first power supply voltage VDD1 to the node of the power supply voltage VOSC.

[0087] Furthermore, LDO regulator 62 that outputs power supply voltage VPFD, LDO regulator 63 that outputs power supply voltage VCP, LDO regulator 64 that outputs power supply voltage VBUF, and LDO regulator 65 that outputs power supply voltage VDIV are provided in positions close to fractional N-PLL circuit 45. Therefore, the wiring from each output of LDO regulators 62, 63, 64, and 65 to fractional N-PLL circuit 45 is short, reducing the impedance, and the inverse PSNR characteristics of LDO regulators 62, 63, 64, and 65 reduce noise propagating from the node of first power supply voltage VDD1 to each node of power supply voltage VPFD, power supply voltage VCP, power supply voltage VBUF, and power supply voltage VDIV.

[0088] Furthermore, the LDO regulator 66 that outputs the power supply voltage VVCO and the LDO regulator 67 that outputs the power supply voltage VPLL are provided in positions close to the PLL circuit 46. Therefore, the wiring from each output of the LDO regulators 66, 67 to the PLL circuit 46 is short, reducing the impedance, and the inverse PSNR characteristics of the LDO regulators 66, 67 reduce noise propagating from the node of the second power supply voltage VDD2 to each node of the power supply voltage VVCO and the power supply voltage VPLL.

[0089] 8, a first power supply wiring 410 is provided on the semiconductor substrate 400. The first power supply wiring 410 is connected to the pad P3 and the LDO regulators 61 and 62, and a first power supply voltage VDD1 is supplied from the pad P3 to the LDO regulators 61 and 62 via the first power supply wiring 410. The first power supply wiring 410 further extends along part of the outer edge of the arrangement area of ​​the fractional N-PLL circuit 45.

[0090] Further, a second power supply wiring 420 is provided on the semiconductor substrate 400. The second power supply wiring 420 is connected to the pad P6 and the LDO regulators 63, 64, 65, 66, and 67, and a second power supply voltage VDD2 is supplied from the pad P6 to the LDO regulators 63, 64, 65, 66, and 67 via the second power supply wiring 420. The second power supply wiring 420 is provided along part of the outer edge of the arrangement region of the PLL circuit 46 and part of the outer edge of the arrangement region of the fractional N-PLL circuit 45.

[0091] 8, a portion of the first power supply wiring 410 and a portion of the second power supply wiring 420 are parallel to each other, and fluctuations in the first power supply voltage VDD1 and the second power supply voltage VDD2 tend to interfere with each other due to capacitive coupling between the first power supply wiring 410 and the second power supply wiring 420. Therefore, a shield wiring 430 is provided between the first power supply wiring 410 and the second power supply wiring 420. For example, by providing the first power supply wiring 410, the second power supply wiring 420, and the shield wiring 430 in the same wiring layer, the capacitive coupling between the first power supply wiring 410 and the second power supply wiring 420 is effectively suppressed. Furthermore, the first power supply wiring 410 and the second power supply wiring 420 are not loop-shaped, and are arranged so as not to be close to each other except for the portions sandwiching the shield wiring 430, so as to reduce the capacitive coupling between the first power supply wiring 410 and the second power supply wiring 420.

[0092] The pads P10 and P11 are pads connected to the oscillator 5, and the nodes connected to the pads P10 and P11 are high-impedance nodes, which are prone to noise superposition. In particular, the pad P10 is a pad to which the oscillation signal VO_XI output from the oscillator 5 is input, and noise superposed on the node of the pad P10 is amplified by the oscillation circuit 124. For this reason, the first power supply wiring 410 and the second power supply wiring 420 are arranged so as to be away from the pads P10 and P11. As a result, the shortest distance between the pad P10 and the second power supply wiring 420 is longer than the shortest distance between the pad P8, which is the clock output terminal, and the second power supply wiring 420.

[0093] The control IC 4 is an example of an "integrated circuit device," and the oscillator IC 8 is an example of a "second integrated circuit device." The oscillator circuit 81 is an example of a "first circuit," and the PLL circuit 46 is an example of a "second circuit." Furthermore, the pad P2 is an example of a "first ground terminal," the pad P7 is an example of a "second ground terminal," the pad P4 is an example of a "third ground terminal," and the pad P9 is an example of a "fourth ground terminal." Furthermore, the pad P3 is an example of a "first power supply voltage input terminal," and the pad P6 is an example of a "second power supply voltage input terminal."

[0094] 1-4.Effects As described above, in the oscillator 1 of the first embodiment, the control IC 4 has the layout configuration shown in Fig. 8, which reduces electromagnetic field coupling and capacitive coupling between nodes and reduces spurious noise superimposed on the output clock signal OUT. Therefore, the oscillator 1 of the first embodiment can output an output clock signal OUT with a high S / N ratio. Furthermore, the multiple wirings external to the control IC 4 that are connected to the pads P1 to P11, respectively, are arranged in the same manner as the pads P1 to P11, so the above-mentioned effects can also be obtained outside the control IC 4.

[0095] 2. Second embodiment In the following, in the second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and explanations of the same components as those in the first embodiment are omitted or simplified, and differences from the first embodiment will be mainly described.

[0096] The structure of the oscillator 1 of the second embodiment is the same as that shown in FIGS. 1 to 4, and therefore its illustration and description will be omitted.

[0097] In the oscillator 1 of the first embodiment, in the control IC 4, the pad P4, which is a ground terminal, is located next to the pad P1 to which the reference clock signal CLKIN is input, and the pads P7 and P9, which are also ground terminals, are located on both sides of the pad P8 to which the output clock signal OUT is output. Therefore, as shown in Fig. 10, when the ground impedance is relatively high, there is a risk that slight spurious noise will be superimposed on the output clock signal OUT due to the capacitive coupling between the pad P1 and the ground and the capacitive coupling between the ground and the pad P8.

[0098] Therefore, in the oscillator 1 of the second embodiment, the pad P2 of the control IC 4 is connected to a first ground external to the control IC 4, and the pads P7 and P9 are connected to a second ground external to the control IC 4 that is different from the first ground. Figure 11 is a diagram showing the layout configuration of the control IC 4 of the second embodiment. In Figure 11, the same components as in Figure 8 are assigned the same reference numerals.

[0099] The layout shown in FIG. 11 differs from the layout shown in FIG. 8 in that a first ground voltage VSS1 is supplied to pads P2 and P4, and a second ground voltage VSS2 is supplied to pads P7 and P9. The pads P2 and P4 are connected to a first ground, and the pads P7 and P9 are connected to a second ground different from the first ground. The first ground voltage VSS1 is the voltage of the first ground, and the second ground voltage VSS2 is the voltage of the second ground. Therefore, as shown in FIG. 12, capacitive coupling occurs between pad P1 and the first ground connected to the adjacent pad P2, and between pad P8 and the second grounds connected to the adjacent pads P7 and P9. However, because the first ground and the second ground are separated, spurious noise is not superimposed on the output clock signal OUT due to this capacitive coupling.

[0100] The functional block diagram of the oscillator 1 of the second embodiment is the same as that of FIG. 5 except that a first ground voltage VSS1 and a second ground voltage VSS2 are supplied, and therefore illustration and description thereof will be omitted.

[0101] As described above, according to the oscillator 1 of the second embodiment, as with the oscillator 1 of the first embodiment, electromagnetic field coupling and capacitive coupling between nodes are reduced, thereby reducing spurious noise superimposed on the output clock signal OUT. Furthermore, because the first ground connected to pad P2 and the second ground connected to pads P7 and P9 are separated, interference between the reference clock signal CLKIN input to pad P1 and the output clock signal OUT output from pad P8 is reduced, further reducing spurious noise superimposed on the output clock signal OUT. Therefore, according to the oscillator 1 of the first embodiment, it is possible to output an output clock signal OUT with a high S / N ratio. Furthermore, because the multiple wirings external to the control IC 4 connected to the pads P1 to P11, respectively, are arranged in the same manner as the pads P1 to P11, the above-mentioned effect is also achieved outside the control IC 4.

[0102] 3. Variations The present invention is not limited to the present embodiment, and various modifications are possible within the scope of the present invention.

[0103] In each of the above embodiments, the temperature control element 71 and the temperature sensor 72 are built into the heat generating IC 7, but the temperature control element 71 and the temperature sensor 72 may be provided separately. Also, in each of the above embodiments, the temperature sensor 82 is built into the oscillator IC 8, but the temperature sensor 82 and the oscillator IC 8 may be provided separately. Also, in each of the above embodiments, the temperature sensor 42 is built into the control IC 4, but the temperature sensor 42 and the control IC 4 may be provided separately. In these cases, for example, the temperature sensors 72, 82, and 42 may be thermistors or platinum resistors.

[0104] Furthermore, in each of the above embodiments, the control IC 4 includes one temperature sensor 42, but it may also include multiple temperature sensors. In this case, for example, the A / D conversion circuit 43 may convert multiple temperature detection signals output from the multiple temperature sensors into multiple temperature codes, and the microcontroller 40 may perform temperature control or temperature compensation based on the multiple temperature codes. For example, the microcontroller 40 may perform temperature control or temperature compensation using an average value of the multiple temperature codes as the temperature code DTS3.

[0105] Furthermore, in each of the above embodiments, one A / D conversion circuit 43 converts the voltages of the temperature detection signals TS1, TS2, TS3 into temperature codes DTS1, DTS2, DTS3, respectively, in a time-division manner, but for example, the control IC 4 may be provided with multiple A / D conversion circuits, and the multiple A / D conversion circuits may convert the voltages of the temperature detection signals TS1, TS2, TS3 into temperature codes DTS1, DTS2, DTS3, respectively.

[0106] Furthermore, in each of the above embodiments, the temperature control element 71 is a heat generating element such as a CMOS transistor, but the temperature control element 71 may be any element capable of controlling the temperature of the vibration element 6, and may also be a heat absorbing element such as a Peltier element depending on the relationship between the set temperature that is the target temperature of the vibration element 6 and the outside air temperature.

[0107] The above-described embodiment and modifications are merely examples, and the present invention is not limited to these. For example, the embodiments and modifications can be combined as appropriate.

[0108] The present invention includes configurations that are substantially the same as the configurations described in the embodiments, for example, configurations with the same functions, methods, and results, or configurations with the same purpose and effects. The present invention also includes configurations that replace non-essential parts of the configurations described in the embodiments. The present invention also includes configurations that achieve the same effects or purposes as the configurations described in the embodiments. The present invention also includes configurations that add publicly known technology to the configurations described in the embodiments.

[0109] The following can be derived from the above-described embodiment and modifications.

[0110] One aspect of the integrated circuit device is In a plan view, the substrate has a first side and a second side opposite to the first side, a clock input terminal disposed along the first side and receiving a reference clock signal; a first power supply voltage input terminal disposed along the first side and adapted to receive a first power supply voltage that is a source of a power supply voltage supplied to a first circuit that operates at the frequency of the reference clock signal; a clock output terminal disposed along the second side and outputting an output clock signal having a frequency different from that of the reference clock signal; a second power supply voltage input terminal disposed along the second side and receiving a second power supply voltage that is a source of a power supply voltage supplied to a second circuit that operates at the frequency of the output clock signal; a first ground terminal disposed along the first side between the clock input terminal and the first power supply voltage input terminal; and a second ground terminal disposed along the second side between the clock output terminal and the second power supply voltage input terminal.

[0111] In this integrated circuit device, the magnetic field generated by the current due to charging and discharging when a reference clock signal is input to the clock input terminal is weakened by the magnetic field generated by the current flowing to ground via the first ground terminal. As a result, the electromagnetic field coupling between the node to which the reference clock signal is input and the node of the first power supply voltage is reduced, and the induced current flowing in the node of the first power supply voltage due to electromagnetic induction based on the magnetic field is reduced, thereby reducing fluctuations in the first power supply voltage. In addition, the first ground terminal reduces the capacitive coupling between the clock input terminal and the first power supply voltage input terminal, making it less likely that noise due to the reference clock signal will be superimposed on the first power supply voltage.

[0112] Furthermore, in this integrated circuit device, the magnetic field generated by the current due to charging and discharging when the output clock signal is output from the clock output terminal is weakened by the magnetic field generated by the current flowing to ground via the second ground terminal. As a result, the electromagnetic field coupling between the node from which the output clock signal is output and the node of the second power supply voltage is reduced, and the induced current flowing in the node of the second power supply voltage due to electromagnetic induction based on the magnetic field is reduced, thereby reducing noise superimposed on the second power supply voltage. Furthermore, the second ground terminal reduces the capacitive coupling between the clock output terminal and the second power supply voltage input terminal, making it less likely that noise due to the output clock signal will be superimposed on the second power supply voltage.

[0113] In this way, with this integrated circuit device, electromagnetic field coupling and capacitive coupling between nodes via terminals are reduced, and spurious noise superimposed on the output clock signal is reduced, making it possible to output an output clock signal with a high S / N ratio.

[0114] One aspect of the integrated circuit device is a power supply circuit that generates the power supply voltage to be supplied to the first circuit based on the first power supply voltage; a power supply voltage output terminal arranged along the first side and configured to output the power supply voltage to be supplied to the first circuit; The power supply circuit may further include a third ground terminal disposed between the power supply voltage output terminal and the first power supply voltage input terminal, or between the power supply voltage output terminal and the clock input terminal.

[0115] In this integrated circuit device, a magnetic field generated by a current due to charging and discharging when a reference clock signal is input to the clock input terminal is weakened by a magnetic field generated by a current flowing to ground via the third ground terminal. This reduces the electromagnetic field coupling between the node to which the reference clock signal is input and the node of the power supply voltage supplied to the first circuit, and electromagnetic induction based on this magnetic field reduces the induced current flowing in the node of the power supply voltage, thereby reducing fluctuations in the power supply voltage. Furthermore, the magnetic field generated by the current due to fluctuations in the power supply voltage and the magnetic field generated by the current due to fluctuations in the first power supply voltage are weakened by a magnetic field generated by the current flowing to ground via the third ground terminal. This reduces the electromagnetic field coupling between the node of the first power supply voltage and the node of the power supply voltage supplied to the first circuit, and electromagnetic induction based on this magnetic field reduces the induced current flowing in the node of the first power supply voltage and the node of the power supply voltage, thereby reducing fluctuations in the power supply voltage and the first power supply voltage. This integrated circuit device therefore reduces electromagnetic field coupling and capacitive coupling between nodes via the terminals, enabling it to output an output clock signal with a high signal-to-noise ratio.

[0116] In one aspect of the integrated circuit device, The clock input terminal, the first ground terminal, the first power supply voltage input terminal, the third ground terminal, and the power supply voltage output terminal may be arranged in this order along the first side.

[0117] According to this integrated circuit device, electromagnetic field coupling and capacitive coupling between nodes via terminals are reduced, and an output clock signal with a high S / N ratio can be output.

[0118] One aspect of the integrated circuit device is an oscillation circuit that oscillates an oscillator to generate an oscillation signal; a buffer circuit that buffers the oscillation signal and outputs the output clock signal; a first vibrator terminal connected to the vibrator and the buffer circuit; The circuit may further include a fourth ground terminal arranged along the second side between the first oscillator terminal and the clock output terminal or between the first oscillator terminal and the second power supply voltage input terminal.

[0119] According to this integrated circuit device, a magnetic field generated by a current due to charging and discharging when an output clock signal is output from the clock output terminal is weakened by a magnetic field generated by a current flowing to ground via the fourth ground terminal. This reduces electromagnetic field coupling between the node from which the output clock signal is output and the node connected to the first oscillator terminal, and electromagnetic induction based on this magnetic field reduces the induced current flowing to the node connected to the first oscillator terminal, thereby reducing fluctuations in the oscillation signal due to oscillator oscillation. Furthermore, a magnetic field generated by a current due to fluctuations in the oscillation signal and a magnetic field generated by a current due to fluctuations in the second power supply voltage are weakened by a magnetic field generated by a current flowing to ground via the fourth ground terminal. This reduces electromagnetic field coupling between the node of the second power supply voltage and the node connected to the first oscillator terminal, and electromagnetic induction based on this magnetic field reduces the induced current flowing to the node of the second power supply voltage and the node connected to the first oscillator terminal, thereby reducing fluctuations in the oscillation signal due to oscillator oscillation and fluctuations in the second power supply voltage. This integrated circuit device therefore reduces electromagnetic field coupling and capacitive coupling between nodes via the terminals, enabling the output clock signal to have a high signal-to-noise ratio.

[0120] In one aspect of the integrated circuit device, The second power supply voltage input terminal, the second ground terminal, the clock output terminal, the fourth ground terminal, and the first oscillator terminal may be arranged in this order along the second side.

[0121] According to this integrated circuit device, electromagnetic field coupling and capacitive coupling between nodes via terminals are reduced, and an output clock signal with a high S / N ratio can be output.

[0122] One aspect of the integrated circuit device is a power supply wiring connected to the second power supply voltage input terminal; The shortest distance between the first oscillator terminal and the power supply wiring may be longer than the shortest distance between the clock output terminal and the power supply wiring.

[0123] According to this integrated circuit device, the node connected to the first oscillator terminal is a high impedance node and is prone to noise superposition, but the power supply wiring to which the second power supply voltage is supplied is arranged away from the first oscillator terminal, thereby reducing the noise superposed on the oscillation signal based on the oscillator oscillation and enabling the output of an output clock signal with a high signal-to-noise ratio.

[0124] One aspect of the integrated circuit device is a first power supply wiring connected to the first power supply voltage input terminal; a second power supply wiring connected to the second power supply voltage input terminal; The semiconductor device may further include a shield wiring provided between the first power supply wiring and the second power supply wiring.

[0125] According to this integrated circuit device, the shielding wiring effectively suppresses capacitive coupling between the first power supply wiring and the second power supply wiring, thereby reducing the risk of fluctuations in the first power supply voltage and fluctuations in the second power supply voltage interfering with each other, and making it possible to output an output clock signal with a high S / N ratio.

[0126] In one aspect of the integrated circuit device, the first ground terminal is connected to an external first ground; The second ground terminal may be connected to an external second ground different from the first ground.

[0127] According to this integrated circuit device, the first ground connected to the first ground terminal and the second ground connected to the second ground terminal are separated, thereby reducing interference between the reference clock signal input to the clock input terminal and the output clock signal output from the clock output terminal, and further reducing spurious noise superimposed on the output clock signal.

[0128] One aspect of the oscillator is The present invention includes one aspect of the integrated circuit device.

[0129] One aspect of the oscillator is A vibration element; The oscillator may further include a second integrated circuit device that oscillates the vibration element and outputs the reference clock signal.

[0130] One aspect of the oscillator is A temperature control element for controlling the temperature of the vibration element may be provided. [Explanation of symbols]

[0131] 1... oscillator, 2... outer package, 3... inner package, 4... control IC, 5... resonator, 6... vibration element, 7... heat-generating IC, 8... oscillation IC, 9... voltage-controlled oscillator, 10... CPU, 11... temperature control circuit, 12... temperature compensation circuit, 13... fault detection circuit, 14... filter circuit, 15... memory, 21... outer base, 21a... upper surface, 21b... lower surface, 22... outer lid, 23... sealing member, 25... internal wiring, 27... board, 28... wall portion, 29... legs, 31... inner base, 31a... upper surface, 31b... lower surface, 32... inner lid, 33... sealing member, 40... microcontroller , 41...Selector, 42...Temperature sensor, 43...A / D conversion circuit, 44...D / A conversion circuit, 45...Fractional N-PLL circuit, 46...PLL circuit, 47...Switch circuit, 48...Power supply circuit, 49...Interface circuit, 51...Package, 52...Base, 52a...Top surface, 52b...Bottom surface, 53...Lid, 54...Sealing member, 55...Vibration element, 61-67...LDO regulator, 71...Temperature control element, 72...Temperature sensor, 81...Oscillator circuit, 82...Temperature sensor, 90...Memory, 91...Temperature control data, 92...Temperature compensation data, 94...Register , 100...external device, 111...phase comparator, 112...charge pump, 113...low-pass filter, 114...voltage controlled oscillator circuit, 115...buffer circuit, 116...frequency divider circuit, 120...frequency controlled voltage generation circuit, 121...phase comparator, 122...charge pump, 123...low-pass filter, 124...oscillation circuit, 125...buffer circuit, 211...upper recess, 211a...first upper recess, 211b...second upper recess, 211c...third upper recess, 212...lower recess, 241...internal terminal, 242...internal terminal, 243...internal terminal, 244...external terminal, 245... Side terminal, 311...recess, 311a...first recess, 311b...second recess, 311c...third recess, 341...internal terminal, 342...internal terminal, 343...internal terminal, 344...external terminal, 400...semiconductor substrate, 401...first side, 402...second side, 403...third side, 404...fourth side, 410...first power supply wiring, 411...wiring, 420...second power supply wiring, 430...shield wiring, 521...recess, 561...internal terminal, 564...external terminal, B1...bonding member, B2...bonding member, B3...bonding member, B4...bonding member, BW1...bonding wire, BW2...bonding wire,BW3...bonding wire, BW4...bonding wire, BW5...bonding wire, H...solder, S2...outer accommodating space, S3...inner accommodating space, S5...accommodating space,

Claims

1. In a plan view, the insulating film has a first side and a second side opposite to the first side, a clock input terminal disposed along the first side and receiving a reference clock signal; a first power supply voltage input terminal disposed along the first side and adapted to receive a first power supply voltage that is a source of a power supply voltage supplied to a first circuit that operates at the frequency of the reference clock signal; a clock output terminal disposed along the second side and configured to output an output clock signal having a frequency different from that of the reference clock signal; a second power supply voltage input terminal disposed along the second side and receiving a second power supply voltage that is a source of a power supply voltage supplied to a second circuit that operates at the frequency of the output clock signal; a first ground terminal disposed along the first side between the clock input terminal and the first power supply voltage input terminal; a second ground terminal disposed along the second side between the clock output terminal and the second power supply voltage input terminal.

2. In claim 1, a power supply circuit that generates the power supply voltage to be supplied to the first circuit based on the first power supply voltage; a power supply voltage output terminal arranged along the first side and configured to output the power supply voltage to be supplied to the first circuit; a third ground terminal disposed between the power supply voltage output terminal and the first power supply voltage input terminal or between the power supply voltage output terminal and the clock input terminal.

3. In claim 2, An integrated circuit device, wherein the clock input terminal, the first ground terminal, the first power supply voltage input terminal, the third ground terminal, and the power supply voltage output terminal are arranged in this order along the first side.

4. In claim 1, an oscillation circuit that oscillates an oscillator to generate an oscillation signal; a buffer circuit that buffers the oscillation signal and outputs the output clock signal; a first vibrator terminal connected to the vibrator and the buffer circuit; a fourth ground terminal arranged along the second side between the first oscillator terminal and the clock output terminal or between the first oscillator terminal and the second power supply voltage input terminal.

5. In claim 4, An integrated circuit device, wherein the second power supply voltage input terminal, the second ground terminal, the clock output terminal, the fourth ground terminal, and the first oscillator terminal are arranged in this order along the second side.

6. In claim 4, a power supply wiring connected to the second power supply voltage input terminal; an integrated circuit device, wherein the shortest distance between the first oscillator terminal and the power supply wiring is longer than the shortest distance between the clock output terminal and the power supply wiring.

7. In claim 1, a first power supply wiring connected to the first power supply voltage input terminal; a second power supply wiring connected to the second power supply voltage input terminal; a shield wiring provided between the first power supply wiring and the second power supply wiring.

8. In claim 1, the first ground terminal is connected to an external first ground; The second ground terminal is connected to an external second ground different from the first ground.

9. An oscillator comprising the integrated circuit device according to any one of claims 1 to 8.

10. In claim 9, A vibration element; a second integrated circuit device that causes the vibration element to oscillate and outputs the reference clock signal.

11. In claim 10, An oscillator comprising a temperature control element that controls the temperature of the vibration element.

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