Display device and electronic appliance

Abstract

To provide a display device in which the area size is reduced by simplifying a circuit to drive a pixel circuit.SOLUTION: A display device includes a pixel circuit including first to fourth transistors and a light-emitting element, and a data potential generation circuit that generates a data potential. In a first period, the second transistor is turned on; the third transistor and the fourth transistor are turned off; and a first potential is supplied to a gate of the first transistor through a data line. In a second period, the second transistor and the third transistor are turned on; the fourth transistor is turned off; and the data line and a gate and a drain of the first transistor are electrically connected. In a third period, the second transistor is turned on; the third transistor and the fourth transistor are turned off; and the data potential is supplied to the gate of the first transistor through the data line and the second transistor.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a display device and an electronic device. [Background technology]

[0002] Display devices that have light-emitting elements such as organic electroluminescence (EL) elements are known. In these display devices, a large number of pixel circuits, each of which has a light-emitting element and a plurality of transistors used to drive the light-emitting element and control the light-emitting timing, are connected to a single data line.

[0003] For example, Patent Document 1 discloses a display device in which the threshold voltage of a driving transistor of a light-emitting element is held at one end of a coupling capacitance provided between a data line and a pixel circuit, and then data is written to the pixel circuit from the other end of the coupling capacitance by changing the voltage according to gradation data. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2021-96418 Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the display device described in Patent Document 1, when the load capacitance of the data lines increases due to an increase in the number of pixels and an increase in screen size as a result of higher resolution display images, the capacitance value of the coupling capacitance needs to be increased in proportion to the increase in the load capacitance of the data lines, which results in an increase in the area size of the display device. [Means for solving the problem]

[0006] One aspect of the display device according to the present invention is The scan line and The data line and pixel circuits provided corresponding to the scanning lines and the data lines; a data potential generating circuit that generates a data potential; the pixel circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a light emitting element; the first transistor supplies a current to the light emitting element according to a voltage between a gate and a source; the second transistor controls an electrical connection between the data line and the gate of the first transistor in response to a potential of the scan line; the third transistor controls an electrical connection between the data line and the drain of the first transistor; the fourth transistor controls an electrical connection between the light emitting element and the drain of the first transistor; In the first period, the second transistor is turned on, the third transistor and the fourth transistor are turned off, and a predetermined first potential is supplied to the gate of the first transistor via the data line; In a second period after the first period, the second transistor and the third transistor are turned on, the fourth transistor is turned off, and the data line is electrically connected to the gate and the drain of the first transistor; In a third period after the second period, The second transistor is turned on, the third transistor and the fourth transistor are turned off, and the data potential is supplied to the gate of the first transistor via the data line and the second transistor.

[0007] One aspect of the electronic device according to the present invention is The display device has one aspect of the above. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view schematically showing a display device according to an embodiment of the present invention. [Figure 2] FIG. 2 is a plan view schematically showing a display panel of the display device. [Figure 3] FIG. 2 is a block diagram showing the electrical configuration of the display device. [Figure 4] FIG. 2 is a diagram showing the configuration of a pixel circuit and a data line driving circuit according to the first embodiment. [Figure 5] FIG. 3 is a timing chart showing an example of waveforms of various signals in the display device of the first embodiment. [Figure 6] FIG. 2 is a diagram for explaining the operation of the display device according to the first embodiment. [Figure 7] FIG. 2 is a diagram for explaining the operation of the display device according to the first embodiment. [Figure 8] FIG. 2 is a diagram for explaining the operation of the display device according to the first embodiment. [Figure 9] FIG. 2 is a diagram for explaining the operation of the display device according to the first embodiment. [Figure 10] FIG. 2 is a diagram for explaining the operation of the display device according to the first embodiment. [Figure 11] FIG. 2 is a diagram for explaining the operation of the display device according to the first embodiment. [Figure 12] FIG. 10 is a diagram showing the configuration of a pixel circuit and a data line driving circuit according to a second embodiment. [Figure 13] FIG. 10 is a timing chart showing an example of waveforms of various signals in the display device according to the second embodiment. [Figure 14] FIG. 10 is a diagram for explaining the operation of the display device according to the second embodiment. [Figure 15] FIG. 10 is a diagram for explaining the operation of the display device according to the second embodiment. [Figure 16] FIG. 10 is a diagram for explaining the operation of the display device according to the second embodiment. [Figure 17] FIG. 10 is a diagram for explaining the operation of the display device according to the second embodiment. [Figure 18] FIG. 10 is a diagram for explaining the operation of the display device according to the second embodiment. [Figure 19] FIG. 10 is a diagram for explaining the operation of the display device according to the second embodiment. [Figure 20] FIG. 1 is a perspective view schematically showing a head-mounted display according to an embodiment of the present invention. [Figure 21] FIG. 2 is a diagram schematically illustrating an image forming device and a light guiding device of the head-mounted display according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Preferred embodiments of the present invention will be described in detail below with reference to the drawings. Note that the embodiments described below do not unduly limit the content of the present invention as defined in the claims. Furthermore, not all of the configurations described below are necessarily essential components of the present invention.

[0010] 1.Display device 1-1. First embodiment 1-1-1. Overall configuration of the display device Fig. 1 is a perspective view schematically showing a display device 1 of this embodiment. Fig. 2 is a plan view schematically showing a display panel 2 of the display device 1 of this embodiment. Note that Figs. 1 and 2 show an X-axis, a Y-axis, and a Z-axis as three mutually orthogonal axes.

[0011] The display device 1 is, for example, a micro display that displays color images in an HMD, etc. HMD is an abbreviation for Head Mount Display.

[0012] 1, the display device 1 includes a display panel 2, an FPC board 120, and a case 130. FPC is an abbreviation for Flexible Printed Circuits.

[0013] The display panel 2 includes a plurality of pixel circuits and a drive circuit for driving the pixel circuits. In this embodiment, the plurality of pixel circuits and the drive circuit included in the display panel 2 are formed on a silicon substrate, and the pixel circuits use OLEDs, which are light-emitting elements. OLED is an abbreviation for Organic Light Emitting Diode.

[0014] As shown in FIG. 2, the display panel 2 has a display area 112. In the illustrated example, the display area 112 is a rectangle with long sides parallel to the X axis. In the display area 112, a plurality of pixels P as display units are displayed in a matrix at a predetermined arrangement pitch. In the illustrated example, the plurality of pixels P are displayed in a matrix in the X-axis direction and the Y-axis direction. The pixels P have luminance information and may also have color information. When the pixels P have luminance information but no color information, a black and white image is displayed in the display area 112. On the other hand, when the pixels P have both luminance information and color information, a color image is displayed in the display area 112. In the following description, it is assumed that the pixels P have luminance information and color information.

[0015] As shown in FIG. 1, the display panel 2 is housed and fixed in a frame-shaped case 130 that opens in the display area 112, and one end of an FPC board 120 is connected to the case. The other end of the FPC board 120 is provided with a plurality of external connection terminals 124, which are connected to an external circuit (not shown). A control circuit 3, which is a semiconductor chip, is mounted on the FPC board 120 using COF technology, and image data synchronized with a synchronization signal is supplied from the external circuit via the plurality of external connection terminals 124. COF is an abbreviation for Chip On Film. The synchronization signal includes a vertical synchronization signal that instructs the start of vertical scanning of image data, a horizontal synchronization signal that instructs the start of horizontal scanning of image data, and a dot clock signal that indicates the timing of one pixel of image data.

[0016] The control circuit 3 supplies various control signals and various potentials generated in accordance with the synchronization signal to the display panel 2, and also supplies data corresponding to each pixel P included in the image data to the display panel 2 in a time-division manner.

[0017] 1-1-2. Functional configuration of the display device Fig. 3 is a block diagram showing the electrical configuration of the display device 1. As shown in Fig. 3, the display device 1 includes a control circuit 3, a plurality of pixel circuits 20, a scanning line driving circuit 21, a plurality of data line driving circuits 22, and a plurality of data potential generating circuits 23. The plurality of pixel circuits 20, the scanning line driving circuit 21, the plurality of data line driving circuits 22, and the plurality of data potential generating circuits 23 are provided in the display panel 2. As described above, the control circuit 3 is mounted on the FPC board 120, but may also be provided in the display panel 2.

[0018] The display panel 2 has m scanning lines 11 arranged in the horizontal direction in the figure, and 3n data lines 12 arranged in the vertical direction in the figure. In Figure 3, the horizontal direction corresponds to the X-axis direction in Figures 1 and 2, and the vertical direction corresponds to the Y-axis direction in Figures 1 and 2. Note that m and n are integers of 2 or greater. m x 3n pixel circuits 20 are provided corresponding to the m scanning lines 11 and the 3n data lines 12. That is, one pixel circuit 20 is provided corresponding to one scanning line 11 and one data line 12, and the m x 3n pixel circuits 20 are arranged in a matrix of m rows in the vertical direction and 3n columns in the horizontal direction.

[0019] The 3n data lines 12 are divided into n groups, each consisting of three data lines. Of these n groups, the j-th group from the left includes the data line 12 in the 3j-2 column, the data line 12 in the 3j-1 column, and the data line 12 in the 3j-2 column. Here, j is an integer between 1 and n. The data line 12 in the 3j-2 column is connected to n pixel circuits 20 that emit red light, the data line 12 in the 3j-1 column is connected to n pixel circuits 20 that emit blue light, and the data line 12 in the 3j-1 column is connected to n pixel circuits 20 that emit green light. In FIG. 3, the pixel circuits 20 that emit red light are marked with "R," the pixel circuits 20 that emit blue light are marked with "B," and the pixel circuits 20 that emit green light are marked with "G."

[0020] The three pixel circuits 20 connected to the i-th scanning line 11 and each connected to three data lines 12 included in the j-th group correspond to the red, blue, and green pixels that make up the pixel P in the i-th row and j-th column, respectively. That is, the color of pixel P is expressed by additive color mixture using the three pixel circuits 20 corresponding to the red, blue, and green pixels, where i is an integer between 1 and m.

[0021] The display panel 2 is also provided with 3n power supply lines 15 arranged in the vertical direction. m pixel circuits 20 corresponding to red pixels are connected to the power supply line 15 in the 3j-2 column, m pixel circuits 20 corresponding to blue pixels are connected to the power supply line 15 in the 3j-1 column, and m pixel circuits 20 corresponding to green pixels are connected to the power supply line 15 in the 3j-1 column. A potential V0 is commonly supplied to the 3n power supply lines 15 from the control circuit 3. The potential V0 is, for example, a ground potential VSS, which is a reference for zero potential, or a potential close to the ground potential VSS. Specifically, the potential V0 is a potential such that, when applied to a light-emitting element included in each pixel circuit 20, no current flows through the light-emitting element.

[0022] The control circuit 3 controls each component based on image data VID, a vertical synchronization signal VSYNC, a horizontal synchronization signal HSYNC, and a dot clock signal DCLK supplied from an external circuit. The image data VID is data that specifies the gradation level of each pixel P of an image to be displayed in the display area 112, for example, by 8 bits for each RGB. In other words, the image data VID is data that switches between 24-bit RGB data corresponding to the luminance information and color information of each pixel P for each cycle of the dot clock signal DCLK.

[0023] Here, because the brightness characteristics indicated by the gradation level do not match the luminance characteristics of the light-emitting elements included in the pixel circuit 20, the control circuit 3 converts the image data VID that specifies the gradation level of the pixel P into image data VIDX that specifies the luminance corresponding to that gradation level. That is, the control circuit 3 up-converts each of the 8 bits of R data, G data, and B data of each pixel P included in the image data VID into, for example, 10-bit R data, G data, and B data that specify the luminance of the corresponding light-emitting element, thereby generating the image data VIDX. For such up-conversion, a look-up table that pre-stores the correspondence between each of the 8-bit R data, G data, and B data and each of the 10-bit R data, G data, and B data is used.

[0024] The scanning line driving circuit 21 is a circuit for driving the pixel circuits 20 arranged in m rows and 3n columns, row by row, under the control of the control circuit 3, and outputs various signals. For example, the scanning line driving circuit 21 supplies scanning signals XGWR[1] to XGWR[m] to the 1st to mth scanning lines 11 in order. That is, the scanning signal XGWR[i] is supplied to the i-th scanning line 11.

[0025] One data line driving circuit 22 and one data potential generating circuit 23 are provided for three data lines 12 included in the same group. As described above, the 3n data lines 12 are divided into n groups, so the display panel 2 has n data line driving circuits 22 and n data potential generating circuits 23.

[0026] The j-th data potential generating circuit 23 from the left generates data potentials VDATA[j] to be supplied to the data lines 12 in the 3j-2th, 3j-1st, and 3jth columns, respectively, based on image data VIDX supplied from the control circuit 3, in accordance with control by the control circuit 3. Specifically, the j-th data potential generating circuit 23 includes a D / A conversion circuit and an amplifier circuit, and the D / A conversion circuit acquires R data, B data, and G data of m pixels P in the jth column, included in the image data VIDX output from the control circuit 3, at timings specified by the control circuit 3, and performs D / A conversion on the data in a time-division manner. Furthermore, the amplifier circuit amplifies the potential after D / A conversion and outputs the data potential VDATA[j]. That is, the data potential VDATA[j] switches in a time-division manner at the timings at which R data, B data, or G data is written to 3m pixel circuits 20 corresponding to the m pixels P in the jth column.

[0027] The j-th data line driving circuit 22 from the left is connected to three data lines 12 in the 3j-2, 3j-1, and 3j columns. In accordance with control by the control circuit 3, the j-th data line driving circuit 22 outputs the R data, B data, and G data included in the time-division data potential VDATA[j] output from the j-th data potential generating circuit 23 to the 3j-2, 3j-1, and 3j column data lines 12 at the timing when RGB data is written to three pixel circuits corresponding to the pixel P in the i-th row and j-th column.

[0028] The control circuit 3 supplies various control signals and various potentials to the display panel 2, but only some of them are shown in FIG.

[0029] 1-1-3. Configuration of pixel circuit and data line driving circuit 4 is a diagram showing the configuration of three pixel circuits 20 corresponding to pixel P on the ith row and jth column, and the jth data line drive circuit 22. For ease of explanation, in FIG. 4, the three pixel circuits 20 corresponding to pixel P on the ith row and jth column are distinguished as pixel circuits 20-1, 20-2, and 20-3, respectively, but the three pixel circuits 20 have the same configuration, and the same components are assigned the same reference numerals. Pixel circuit 20-1 is the pixel circuit 20 corresponding to the red pixel of pixel P, pixel circuit 20-2 is the pixel circuit 20 corresponding to the blue pixel of pixel P, and pixel circuit 20-3 is the pixel circuit 20 corresponding to the green pixel of pixel P.

[0030] 4, the pixel circuit 20 includes a capacitive element 201, P-channel MOSFETs 202 to 206, and a light-emitting element 207. MOS is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor.

[0031] The light-emitting element 207 is an OLED and has a structure in which a light-emitting functional layer is sandwiched between a pixel electrode and a common electrode (not shown). The pixel electrode functions as an anode, and the common electrode, which is optically transparent, functions as a cathode. When a current flows from the anode to the cathode in the light-emitting element 207, holes injected from the anode and electrons injected from the cathode recombine in the light-emitting functional layer to generate excitons, thereby generating white light. The generated white light then resonates in an optical resonator composed of a reflective layer and a semi-reflective / semi-transmissive layer (not shown) and is emitted at a resonant wavelength set corresponding to one of red, green, or blue. A color filter corresponding to the corresponding color is provided on the light exit side of the optical resonator. Therefore, the light emitted from the light-emitting element 207 is visually recognized by the viewer after being colored by the optical resonator and color filter. Note that the color filter is omitted when displaying a black-and-white image in the display area 112.

[0032] A potential VEL is supplied to one end of the capacitance element 201 from the control circuit 3, and the other end of the capacitance element 201 is connected to the gate of the MOSFET 202 and the drain of the MOSFET 203. A potential VEL is supplied to the source of the MOSFET 202, and the drain of the MOSFET 202 is connected to the drain of the MOSFET 204 and the source of the MOSFET 205. The drain of the MOSFET 205 is connected to the drain of the MOSFET 206 and the anode of the light-emitting element 207. A potential VCT is supplied to the cathode of the light-emitting element 207 from the control circuit 3.

[0033] The source of the MOSFET 203 and the source of the MOSFET 204 are connected to the data line 12. The source of the MOSFET 206 is connected to the power supply line 15, and is supplied with a potential V0 from the control circuit 3.

[0034] The gate of the MOSFET 203 receives a scanning signal XGWR[i] from the scanning line driving circuit 21. The gate of the MOSFET 204 receives a control signal XGCMP[i] from the scanning line driving circuit 21. The gate of the MOSFET 205 receives a control signal XGEL[i] from the scanning line driving circuit 21. The gate of the MOSFET 206 receives a control signal XGOR[i] from the scanning line driving circuit 21.

[0035] The MOSFET 202 supplies a current according to the voltage between the gate and source to the light emitting element 207. Specifically, the higher the voltage between the gate and source of the MOSFET 202, the larger the current flowing through the light emitting element 207, and the greater the amount of light emitted by the light emitting element 207.

[0036] The MOSFET 203 controls the electrical connection between the data line 12 and the gate of the MOSFET 202 according to the potential of the scanning line 11. Specifically, when the scanning signal XGWR[i] supplied to the scanning line 11 is at L level, the MOSFET 203 is turned on, electrically connecting the data line 12 and the gate of the MOSFET 202, and when the scanning signal XGWR[i] is at H level, the MOSFET 203 is turned off, electrically disconnecting the data line 12 and the gate of the MOSFET 202.

[0037] The MOSFET 204 controls the electrical connection between the data line 12 and the drain of the MOSFET 202. Specifically, when the control signal XGCMP[i] is at an L level, the MOSFET 204 is turned on, electrically connecting the data line 12 and the drain of the MOSFET 202, and when the control signal XGCMP[i] is at an H level, the MOSFET 204 is turned off, electrically disconnecting the data line 12 and the drain of the MOSFET 202.

[0038] The MOSFET 205 controls the electrical connection between the light emitting element 207 and the drain of the MOSFET 202. Specifically, when the control signal XGEL[i] is at an L level, the MOSFET 205 is turned on, electrically connecting the anode of the light emitting element 207 and the drain of the MOSFET 202, and when the control signal XGEL[i] is at an H level, the MOSFET 205 is turned off, electrically disconnecting the anode of the light emitting element 207 and the drain of the MOSFET 202.

[0039] The MOSFET 206 controls the electrical connection between the power supply line 15 and the light-emitting element 207. Specifically, when the control signal XGOR[i] is at an L level, the MOSFET 206 is turned on, electrically connecting the power supply line 15 and the anode of the light-emitting element 207, and when the control signal XGOR[i] is at an H level, the MOSFET 206 is turned off, electrically disconnecting the power supply line 15 and the anode of the light-emitting element 207.

[0040] 4, a capacitance 25 is provided between the data line 12 connected to the pixel circuit 20 and the power supply line 15. The capacitance 25 may be a parasitic capacitance between the data line 12 and the power supply line 15, or may be a capacitance formed by sandwiching an insulating layer between different conductive layers on a silicon substrate.

[0041] As shown in FIG. 4, the data line driving circuit 22 includes P-channel MOSFETs 221-1, 221-2, 221-3, 222-1, 222-2, and 222-3, switch circuits 223-1, 223-2, 223-3, 224-1, 224-2, and 224-3, and capacitance elements 225-1, 225-2, and 225-3.

[0042] Switch circuits 223-1, 223-2, 223-3, 224-1, 224-2, and 224-3 are transmission gates in which the sources and drains of an N-channel MOSFET and a P-channel MOSFET are connected to each other. Hereinafter, in each of switch circuits 223-1, 223-2, 223-3, 224-1, 224-2, and 224-3, the gate of the N-channel MOSFET is referred to as a "first control terminal," the gate of the P-channel MOSFET is referred to as a "second control terminal," the connection node between the source of the N-channel MOSFET and the source of the P-channel MOSFET is referred to as an "input terminal," and the connection node between the drain of the N-channel MOSFET and the drain of the P-channel MOSFET is referred to as an "output terminal."

[0043] A potential VINI is supplied to the source of the MOSFET 221-1 from the control circuit 3, and the drain of the MOSFET 221-1 is connected to the data line 12 connected to the pixel circuit 20-1. A potential VREF is supplied to the source of the MOSFET 222-1 from the control circuit 3, and the drain of the MOSFET 222-1 is connected to the data transfer line 17-1. An input terminal of the switch circuit 223-1 is connected to the data transfer line 17-1, and an output terminal of the switch circuit 223-1 is connected to the data line 12 connected to the pixel circuit 20-1. An input terminal of the switch circuit 224-1 is connected to the data supply line 18, and an output terminal of the switch circuit 224-1 is connected to the data transfer line 17-1. One end of the capacitance element 225-1 is connected to the data transfer line 17-1, and the other end of the capacitance element 225-1 is supplied with a ground potential VSS.

[0044] Similarly, a potential VINI is supplied from the control circuit 3 to the source of the MOSFET 221-2, and the drain of the MOSFET 221-2 is connected to the data line 12 connected to the pixel circuit 20-2. A potential VREF is supplied from the control circuit 3 to the source of the MOSFET 222-2, and the drain of the MOSFET 222-2 is connected to the data transfer line 17-2. An input terminal of the switch circuit 223-2 is connected to the data transfer line 17-2, and an output terminal of the switch circuit 223-2 is connected to the data line 12 connected to the pixel circuit 20-2. An input terminal of the switch circuit 224-2 is connected to the data supply line 18, and an output terminal of the switch circuit 224-2 is connected to the data transfer line 17-2. One end of the capacitance element 225-2 is connected to the data transfer line 17-2, and the other end of the capacitance element 225-2 is supplied with a ground potential VSS.

[0045] Similarly, a potential VINI is supplied from the control circuit 3 to the source of the MOSFET 221-3, and the drain of the MOSFET 221-3 is connected to the data line 12 connected to the pixel circuit 20-3. A potential VREF is supplied from the control circuit 3 to the source of the MOSFET 222-3, and the drain of the MOSFET 222-3 is connected to the data transfer line 17-3. An input terminal of the switch circuit 223-3 is connected to the data transfer line 17-3, and an output terminal of the switch circuit 223-3 is connected to the data line 12 connected to the pixel circuit 20-3. An input terminal of the switch circuit 224-3 is connected to the data supply line 18, and an output terminal of the switch circuit 224-3 is connected to the data transfer line 17-3. One end of the capacitance element 225-3 is connected to the data transfer line 17-3, and the other end of the capacitance element 225-3 is supplied with a ground potential VSS.

[0046] The data supply line 18 is supplied with the data potential VDATA[j] generated by the j-th data potential generating circuit 23 .

[0047] A control signal XGINI is input to each gate of the MOSFETs 221-1, 221-2, and 221-3 from the control circuit 3. A control signal XGREF is input to each gate of the MOSFETs 222-1, 222-2, and 222-3 from the control circuit 3.

[0048] A control signal GCPL is input to each first control terminal of the switch circuits 223-1, 223-2, and 223-3 from the control circuit 3, and a control signal XGCPL is input to each second control terminal of the switch circuits 223-1, 223-2, and 223-3 from the control circuit 3. The control signal GCPL and the control signal XGCPL are digital signals whose logical levels are inverted from each other.

[0049] A control signal SEL1 is input to a first control terminal of the switch circuit 224-1 from the control circuit 3, and a control signal XSEL1 is input to a second control terminal of the switch circuit 224-1 from the control circuit 3. The control signal SEL1 and the control signal XSEL1 are digital signals whose logical levels are inverted from each other.

[0050] A control signal SEL2 is input to a first control terminal of the switch circuit 224-2 from the control circuit 3, and a control signal XSEL2 is input to a second control terminal of the switch circuit 224-2 from the control circuit 3. The control signal SEL2 and the control signal XSEL2 are digital signals whose logical levels are inverted from each other.

[0051] A control signal SEL3 is input to a first control terminal of the switch circuit 224-3 from the control circuit 3, and a control signal XSEL3 is input to a second control terminal of the switch circuit 224-3 from the control circuit 3. The control signal SEL3 and the control signal XSEL3 are digital signals whose logical levels are inverted from each other.

[0052] MOSFET 221-1 controls the supply of potential VINI to data line 12 connected to pixel circuit 20-1. MOSFET 221-2 controls the supply of potential VINI to data line 12 connected to pixel circuit 20-2. MOSFET 221-3 controls the supply of potential VINI to data line 12 connected to pixel circuit 20-3. Specifically, when the control signal XGINI is at L level, MOSFET 221-1 is turned on to supply potential VINI to data line 12 connected to pixel circuit 20-1, MOSFET 221-2 is turned on to supply potential VINI to data line 12 connected to pixel circuit 20-2, and MOSFET 221-3 is turned on to supply potential VINI to data line 12 connected to pixel circuit 20-3. Furthermore, when the control signal XGINI is at an H level, MOSFET 221-1 is turned off and no potential VINI is supplied to the data line 12 connected to pixel circuit 20-1, MOSFET 221-2 is turned off and no potential VINI is supplied to the data line 12 connected to pixel circuit 20-2, and MOSFET 221-3 is turned off and no potential VINI is supplied to the data line 12 connected to pixel circuit 20-3.

[0053] The MOSFET 222-1 controls the supply of the potential VREF to the data transfer line 17-1. The MOSFET 222-2 controls the supply of the potential VREF to the data transfer line 17-2. The MOSFET 222-3 controls the supply of the potential VREF to the data transfer line 17-3. Specifically, when the control signal XGREF is at an L level, the MOSFET 222-1 turns on and the potential VREF is supplied to the data transfer line 17-1, the MOSFET 222-2 turns on and the potential VREF is supplied to the data transfer line 17-2, and the MOSFET 222-3 turns on and the potential VREF is supplied to the data transfer line 17-3. On the other hand, when the control signal XGREF is at an H level, the MOSFET 222-1 turns off and the potential VREF is not supplied to the data transfer line 17-1, the MOSFET 222-2 turns off and the potential VREF is not supplied to the data transfer line 17-2, and the MOSFET 222-3 turns off and the potential VREF is not supplied to the data transfer line 17-3.

[0054] The switch circuit 223-1 controls the electrical connection between the data line 12 connected to the pixel circuit 20-1 and the data transfer line 17-1. The switch circuit 223-2 controls the electrical connection between the data line 12 connected to the pixel circuit 20-2 and the data transfer line 17-2. The switch circuit 223-3 controls the electrical connection between the data line 12 connected to the pixel circuit 20-3 and the data transfer line 17-3. Specifically, when the control signals GCPL and XGCPL are at H level and L level, respectively, the switch circuit 223-1 turns on, electrically connecting the data line 12 connected to the pixel circuit 20-1 and the data transfer line 17-1, the switch circuit 223-2 turns on, electrically connecting the data line 12 connected to the pixel circuit 20-2 and the data transfer line 17-2, and the switch circuit 223-3 turns on, electrically connecting the data line 12 connected to the pixel circuit 20-3 and the data transfer line 17-3. Furthermore, when the control signals GCPL and XGCPL are at L level and H level, respectively, the switch circuit 223-1 is turned off, electrically disconnecting the data line 12 connected to the pixel circuit 20-1 from the data transfer line 17-1, the switch circuit 223-2 is turned off, electrically disconnecting the data line 12 connected to the pixel circuit 20-2 from the data transfer line 17-2, and the switch circuit 223-3 is turned off, electrically disconnecting the data line 12 connected to the pixel circuit 20-3 from the data transfer line 17-3.

[0055] The switch circuit 224-1 controls the electrical connection between the data transfer line 17-1 and the data supply line 18. The switch circuit 224-2 controls the electrical connection between the data transfer line 17-2 and the data supply line 18. The switch circuit 224-3 controls the electrical connection between the data transfer line 17-3 and the data supply line 18. Specifically, when the control signals SEL1 and XSEL1 are at H level and L level, respectively, the switch circuit 224-1 turns on and the data transfer line 17-1 and the data supply line 18 are electrically connected, and when the control signals SEL1 and XSEL1 are at L level and H level, respectively, the switch circuit 224-1 turns off and the data transfer line 17-1 and the data supply line 18 are electrically disconnected. Furthermore, when the control signals SEL2 and XSEL2 are at H level and L level, respectively, the switch circuit 224-2 turns on, electrically connecting the data transfer line 17-2 and the data supply line 18, and when the control signals SEL2 and XSEL2 are at L level and H level, respectively, the switch circuit 224-2 turns off, electrically disconnecting the data transfer line 17-2 and the data supply line 18. Furthermore, when the control signals SEL3 and XSEL3 are at H level and L level, respectively, the switch circuit 224-3 turns on, electrically connecting the data transfer line 17-3 and the data supply line 18, and when the control signals SEL3 and XSEL3 are at L level and H level, respectively, the switch circuit 224-3 turns off, electrically disconnecting the data transfer line 17-3 and the data supply line 18.

[0056] When the data transfer line 17-1 and the data supply line 18 are electrically connected by the switch circuit 224-1, the data potential VDATA[j] is transferred from the data supply line 18 to the data transfer line 17-1. Similarly, when the data transfer line 17-2 and the data supply line 18 are electrically connected by the switch circuit 224-2, the data potential VDATA[j] is transferred from the data supply line 18 to the data transfer line 17-1. Similarly, when the data transfer line 17-3 and the data supply line 18 are electrically connected by the switch circuit 224-3, the data potential VDATA[j] is transferred from the data supply line 18 to the data transfer line 17-1.

[0057] The control signals XGINI, XGREF, GCPL, XGCPL, SEL1, XSEL1, SEL2, XSEL2, SEL3, and XSEL3 are input in common to the n data line driving circuits 22.

[0058] 1-1-4. Display device operation The operation of the display device 1 will be described with reference to Fig. 5 to Fig. 11. Fig. 5 is a timing chart showing an example of waveforms of various signals in the display device 1. Fig. 6 to Fig. 11 are diagrams in which the on / off states of the MOSFET and switch circuit and the supply paths of various potentials in each period are added to Fig. 4.

[0059] As shown in FIG. 5, a horizontal scanning period 1H corresponds to one cycle from the timing when a horizontal synchronization signal HSYNC input from an external circuit of the display device 1 transitions from H level to L level to the timing when the horizontal synchronization signal HSYNC next transitions from H level to L level. During each horizontal scanning period 1H, data is written to 3n pixel circuits 20 corresponding to n pixels P in each row. During each horizontal scanning period 1H, the scanning line driving circuit 21 commonly outputs control signals XGEL[i], XGOR[i], XGCMP[i] and a scanning signal XGWR[i] to the 3n pixel circuits 20 corresponding to n pixels P in the i-th row. In addition, the control circuit 3 commonly outputs control signals XGINI, XGREF, GCPL, XGCPL, SEL1, XSEL1, SEL2, XSEL2, SEL3, and XSEL3 to the n data line driving circuits 22. FIG. 5 is a timing chart focusing on a horizontal scanning period 1H of the i-th row after the horizontal scanning periods 1H of the 1st to (i-1)th rows have ended.

[0060] As shown in FIG. 5, the horizontal scanning period 1H for the i-th row includes an initialization period a, a compensation period b following the initialization period a, and a writing period d following the compensation period b. Furthermore, the horizontal scanning period 1H for the i-th row includes a first transfer period c1, a second transfer period c2 following the first transfer period c1, and a third transfer period c3 following the second transfer period c2, which overlap with part of the compensation period b. After the writing period d, there is a light-emitting period e, and after one frame period, the horizontal scanning period 1H for the i-th row resumes. Note that one frame period corresponds to one cycle of the vertical synchronization signal VSYNC and is the time required to display one frame of the image specified by the image data VID. For example, if the frequency of the vertical synchronization signal VSYNC is 60 Hz, the period of one frame is approximately 16.7 milliseconds.

[0061] As shown in FIG. 5, in the horizontal scanning period 1H of the i-th row, during the initialization period a, the scanning signal XGWR[i] is at the L level. Also, the control signal XGOR[i] is at the L level, and the control signals XGEL[i] and XGCMP[i] are at the H level. Also, the control signals XGREF and XGINI are at the L level. Also, the control signals SEL1, SEL2, SEL3, and GCPL are at the L level, and the control signals XSEL1, XSEL2, XSEL3, and XGCPL are at the H level. Therefore, as shown in FIG. 6, during the initialization period a, in the pixel circuits 20-1, 20-2, and 20-3, the MOSFETs 203 and 206 are turned on, and the MOSFETs 204 and 205 are turned off. Furthermore, in data line drive circuit 22, MOSFETs 221-1, 221-2, 221-3, 222-1, 222-2, and 222-3 are turned on, and switch circuits 223-1, 223-2, 223-3, 224-1, 224-2, and 224-3 are turned off. Therefore, in pixel circuits 20-1, 20-2, and 20-3, a predetermined potential VINI is supplied to the gate of MOSFET 202 and the other end of capacitive element 201 via data line 12. Furthermore, potential V0 is supplied to the anode of light-emitting element 207 via power supply line 15. That is, the potentials of data line 12, the gate of MOSFET 202, and the other end of capacitive element 201 are initialized to potential VINI, and the potential of the anode of light-emitting element 207 is initialized to potential V0. In the data line driving circuit 22, the potential VREF is supplied to the data transfer lines 17-1, 17-2, and 17-3, and the voltages across the capacitive elements 225-1, 225-2, and 225-3 are initialized to the difference between the potential VREF and the ground potential VSS.

[0062] As shown in FIG. 5, in the horizontal scanning period 1H of the i-th row, the scanning signal XGWR[i] is at an L level during the compensation period b. The control signals XGOR[i] and XGCMP[i] are at an L level, and the control signal XGEL[i] is at an H level. The control signals XGREF and XGINI are at an H level. The control signal GCPL is at an H level, and the control signal XGCPL is at an L level. Therefore, as shown in FIGS. 7, 8, and 9, in the pixel circuits 20-1, 20-2, and 20-3, the MOSFETs 203, 204, and 206 are turned on, and the MOSFET 205 is turned off during the compensation period b. In the data line driving circuit 22, the MOSFETs 221-1, 221-2, 221-3, 222-1, 222-2, and 222-3 are turned off, and the switch circuits 223-1, 223-2, and 223-3 are turned off. Therefore, in pixel circuits 20-1, 20-2, and 20-3, a current flows from the power supply line carrying potential VEL to the gate of MOSFET 202 via MOSFETs 202, 204, and 205, causing the potentials of data line 12, the gate of MOSFET 202, and the other end of capacitive element 201 to rise from potential VINI. At this time, MOSFET 202 is in a state where its gate and drain are connected, i.e., a diode-connected state, so that the voltage between the gate and source of MOSFET 202 converges to the threshold voltage Vth of MOSFET 202. Since MOSFET 202 is a P-channel type, the threshold voltage Vth is a negative voltage. Because potential VEL is supplied to the source of MOSFET 202, the potentials of data line 12, the gate of MOSFET 202, and the other end of capacitive element 201 converge to potential (VEL-|Vth|). In addition, the potential of the anode of light-emitting element 207 remains at potential V0.

[0063] 7, during the first transfer period c1 that overlaps with part of the compensation period b, in the data line driving circuit 22, the switch circuit 224-1 is turned on, and the switch circuits 223-1, 223-2, 223-3, 224-2, and 224-3 are turned off. Therefore, in the data line driving circuit 22, a current flows from the data supply line 18 to the capacitive element 225-1 via the switch circuit 224-1 and the data transfer line 17-1, and the voltage across the capacitive element 225-1 becomes the voltage difference between the data potential VDATA[j] and the ground potential VSS. That is, the data potential VDATA[j] for the pixel circuit 20-1 is held in the capacitive element 225-1.

[0064] 8, during the second transfer period c2 that overlaps with part of the compensation period b, in the data line driving circuit 22, the switch circuit 224-2 is turned on, and the switch circuits 223-1, 223-2, 223-3, 224-1, and 224-3 are turned off. Therefore, in the data line driving circuit 22, a current flows from the data supply line 18 to the capacitive element 225-2 via the switch circuit 224-2 and the data transfer line 17-2, and the voltage across the capacitive element 225-2 becomes the voltage difference between the data potential VDATA[j] and the ground potential VSS. That is, the data potential VDATA[j] for the pixel circuit 20-2 is held in the capacitive element 225-2.

[0065] 9, during the third transfer period c3 that overlaps with part of the compensation period b, in the data line driving circuit 22, the switch circuit 224-3 is turned on, and the switch circuits 223-1, 223-2, 223-3, 224-1, and 224-2 are turned off. Therefore, in the data line driving circuit 22, a current flows from the data supply line 18 to the capacitive element 225-3 via the switch circuit 224-3 and the data transfer line 17-3, and the voltage across the capacitive element 225-3 becomes the voltage difference between the data potential VDATA[j] and the ground potential VSS. That is, the data potential VDATA[j] for the pixel circuit 20-3 is held in the capacitive element 225-3.

[0066] In this way, the first transfer period c1, the second transfer period c2, and the third transfer period c3 overlap with part of the compensation period b. In other words, during the compensation period b, the data potential VDATA[j] output from the data potential generating circuit 23 is transferred in order from the data supply line 18 to the data transfer lines 17-1, 17-2, and 17-3, and the data potential VDATA[j] transferred to the data transfer lines 17-1, 17-2, and 17-3, respectively, are held in the capacitive elements 225-1, 225-2, and 225-3, respectively.

[0067] As shown in FIG. 5, in the horizontal scanning period 1H of the i-th row, during the writing period d, the scanning signal XGWR[i] is at the L level. Also, the control signal XGOR[i] is at the L level, and the control signals XGCMP[i] and XGEL[i] are at the H level. Also, the control signals XGREF and XGINI are at the H level. Also, the control signals SEL1, SEL2, SEL3, and XGCPL are at the H level, and the control signals XSEL1, XSEL2, XSEL3, and GCPL are at the L level. Therefore, as shown in FIG. 10, during the writing period d, in the pixel circuits 20-1, 20-2, and 20-3, the MOSFETs 203 and 206 are turned on, and the MOSFETs 204 and 205 are turned off. Furthermore, in the data line driving circuit 22, the MOSFETs 221-1, 221-2, 221-3, 222-1, 222-2, and 222-3 are turned off, the switch circuits 223-1, 223-2, and 223-3 are turned on, and the switch circuits 224-1, 224-2, and 224-3 are turned off. Therefore, in the pixel circuit 20-1, the data potential VDATA[j] held in the capacitive element 225-1 is supplied to the other end of the capacitive element 201 and the gate of the MOSFET 202 via the data transfer line 17-1, the switch circuit 223-1, the data line 12, and the MOSFET 203. Similarly, in the pixel circuit 20-2, the data potential VDATA[j] held in the capacitive element 225-2 is supplied to the other end of the capacitive element 201 and the gate of the MOSFET 202 via the data transfer line 17-2, the switch circuit 223-2, the data line 12, and the MOSFET 203. Similarly, in the pixel circuit 20-3, the data potential VDATA[j] held in the capacitive element 225-3 is supplied to the other end of the capacitive element 201 and the gate of the MOSFET 203 via the data transfer line 17-3, the switch circuit 223-3, the data line 12, and the MOSFET 203.

[0068] Here, just before the MOSFET 203 and switch circuit 223-1 of the pixel circuit 20-1 are both turned on, the potential of the data line 12 is the potential (VEL-|Vth|), and the potential of the data transfer line 17-1 is the data potential VDATA[j]. Therefore, when the MOSFET 203 and switch circuit 223-1 are both turned on, the potential of the data line 12 becomes the potential ((Cd·(VEL-|Vth|)+Cst·VDATA[j]) / (Cd+Cst)) due to the capacitive coupling between the capacitor 25 and the capacitive element 225-1. Here, Cd is the capacitance value of the capacitor 25, and Cst is the capacitance value of the capacitive element 225-1. The same applies to the potentials of the data lines 12 connected to the pixel circuits 20-2 and 20-3. Thereafter, when the scanning signal XGWR[j] goes low, the MOSFETs 203 are turned off in the pixel circuits 20-1, 20-2, and 20-3, and the potential of the gate of the MOSFET 202 is fixed at the potential ((Cd·(VEL−|Vth|)+Cst·VDATA[j]) / (Cd+Cst)).

[0069] As shown in Fig. 5, in the horizontal scanning period 1H of the i-th row, the scanning signal XGWR[i] is at H level during the light emission period e. Also, the control signal XGEL[i] is at L level, and the control signals XGCMP[i] and XGOR[i] are at H level. Therefore, as shown in Fig. 11, in the light emission period e, in the pixel circuits 20-1, 20-2, and 20-3, the MOSFET 205 is turned on, and the MOSFETs 203, 204, and 206 are turned off. Therefore, the current flowing from the source to the drain of the MOSFET 202 is supplied to the light emitting element 207 via the MOSFET 205, causing the light emitting element 207 to emit light. The potential of the source of MOSFET 202 is potential VEL, and the potential of the gate of MOSFET 202 is potential ((Cd·(VEL−|Vth|)+Cst·VDATA[j]) / (Cd+Cst)), so that a current according to the data potential VDATA[j] is supplied to light-emitting element 207 while compensating for the threshold voltage Vth of MOSFET 202.

[0070] As shown in Figure 5, in the horizontal scanning period 1H of the i+1th row following the horizontal scanning period 1H of the i-th row, the control signals XGEL[i+1], XGOR[i+1], XGCMP[i+1] and the scanning signal XGWR[i+1] have waveforms that are shifted by a time equivalent to the cycle of the horizontal scanning period 1H from the control signals XGEL[i], XGOR[i], XGCMP[i] and the scanning signal XGWR[i].

[0071] In the first embodiment, the MOSFET 202 is an example of a "first transistor," the MOSFET 203 is an example of a "second transistor," the MOSFET 204 is an example of a "third transistor," and the MOSFET 205 is an example of a "fourth transistor." Each of the switch circuits 223-1, 223-2, and 223-3 is an example of a "first switch circuit," and each of the switch circuits 224-1, 224-2, and 224-3 is an example of a "second switch circuit." The potential VINI is an example of a "first potential." The initialization period a is an example of a "first period," the compensation period b is an example of a "second period," the writing period d is an example of a "third period," and the light-emitting period e is an example of a "fourth period."

[0072] 1-1-5.Effects As described above, in the display device 1 of the first embodiment, in the initialization period a, the potential of the gate of the MOSFET 202 is initialized to the potential VINI, and in the writing period d, the data potential VDATA[j] is supplied to the gate of the MOSFET 202. Then, in the compensation period b between the initialization period a and the writing period d, the voltage between the gate and source of the MOSFET 202 is set to the threshold voltage Vth, and therefore, in the writing period d, the gate of the MOSFET 202 is held at a potential obtained by compensating for the threshold voltage Vth. Specifically, during the first transfer period c1, second transfer period c2, and third transfer period c3, which overlap with part of the compensation period b, the data potential VDATA[j] transferred from the data supply line 18 to the data transfer lines 17-1, 17-2, and 17-3 is held in the capacitive elements 225-1, 225-2, and 225-3, respectively. During the write period d, the gate of the MOSFET 202 is held at a potential at which the threshold voltage Vth is compensated due to coupling between each of the capacitive elements 225-1, 225-2, and 225-3 and the capacitance 25 of the data line 12. Therefore, during the light-emission period e, the light-emitting element 207 is supplied with a current corresponding to the data potential VDATA[j] while compensating for the threshold voltage Vth of the MOSFET 202, thereby enabling accurate light emission. Therefore, according to the display device 1 of the first embodiment, there is no need to provide a coupling capacitance between the data line 12 and the pixel circuit 20, and the data line driving circuit 22 can be simplified and its area reduced.

[0073] Furthermore, according to the display device 1 of the first embodiment, the first transfer period c1, the second transfer period c2, and the third transfer period c3 each overlap with a portion of the compensation period b, thereby shortening the time required to write data to the pixel circuit 20.

[0074] 1-2. Second embodiment Hereinafter, for the display device 1 of the second embodiment, the same symbols will be used for configurations similar to those of the first embodiment, and explanations similar to those of the first embodiment will be omitted or simplified, with the main focus being on the differences from the first embodiment.

[0075] The perspective view of the display device 1 of the second embodiment is the same as that of FIG. 1, and the plan view of the display panel 2 of the second embodiment is the same as that of FIG. 2, so illustration and description thereof will be omitted. Furthermore, the block diagram showing the electrical configuration of the display device 1 of the second embodiment is the same as that of FIG. 3, so illustration and description thereof will be omitted. However, the display device 1 of the second embodiment differs from the first embodiment in that the data potential generating circuit 23 includes a capacitive DAC that outputs the data potential VDATA[j]. DAC is an abbreviation for Digital to Analog Converter. Furthermore, since the data potential generating circuit 23 includes a capacitive DAC, the configuration of the data line driving circuit 22 also differs from that of the first embodiment.

[0076] 12 is a diagram showing the configuration of three pixel circuits 20 corresponding to the pixel P in the ith row and jth column, the jth data line driving circuit 22, and the data potential generating circuit 23 in the display device 1 of the second embodiment. In FIG. 12, the same components as those in FIG. 4 are assigned the same reference numerals. The configuration of the pixel circuit 20 is the same as that in FIG. 4, so its description will be omitted.

[0077] 12, the data line driving circuit 22 in the second embodiment includes P-channel MOSFETs 221-1, 221-2, and 221-3 and switch circuits 224-1, 224-2, and 224-3, as in the first embodiment, but does not include switch circuits 223-1, 223-2, and 223-3 and capacitive elements 225-1, 225-2, and 225-3, unlike the first embodiment. Moreover, the data line driving circuit 22 in the second embodiment includes a P-channel MOSFET 222 instead of the P-channel MOSFETs 222-1, 222-2, and 222-3.

[0078] A potential VINI is supplied to the source of the MOSFET 221-1 from the control circuit 3, and the drain of the MOSFET 221-1 is connected to the data line 12 connected to the pixel circuit 20-1. An input terminal of the switch circuit 224-1 is connected to the data supply line 18, and an output terminal of the switch circuit 224-1 is connected to the data line 12 connected to the pixel circuit 20-1.

[0079] Similarly, the potential VINI is supplied to the source of the MOSFET 221-2 from the control circuit 3, and the drain of the MOSFET 221-2 is connected to the data line 12 connected to the pixel circuit 20-2. The input terminal of the switch circuit 224-2 is connected to the data supply line 18, and the output terminal of the switch circuit 224-2 is connected to the data line 12 connected to the pixel circuit 20-2.

[0080] Similarly, the potential VINI is supplied to the source of the MOSFET 221-3 from the control circuit 3, and the drain of the MOSFET 221-3 is connected to the data line 12 connected to the pixel circuit 20-3. The input terminal of the switch circuit 224-3 is connected to the data supply line 18, and the output terminal of the switch circuit 224-3 is connected to the data line 12 connected to the pixel circuit 20-3.

[0081] The source of the MOSFET 222 is supplied with the potential VREF from the control circuit 3, and the drain of the MOSFET 222 is connected to the data supply line .

[0082] The data supply line 18 is supplied with the data potential VDATA[j] generated by the j-th data potential generating circuit 23 .

[0083] A control signal XGINI is input to the gates of the MOSFETs 221-1, 221-2, and 221-3 from the control circuit 3. A control signal XGREF is input to the gate of the MOSFET 222 from the control circuit 3.

[0084] A control signal SEL1 is input to a first control terminal of the switch circuit 224-1 from the control circuit 3, and a control signal XSEL1 is input to a second control terminal of the switch circuit 224-1 from the control circuit 3. The control signal SEL1 and the control signal XSEL1 are digital signals whose logical levels are inverted from each other.

[0085] A control signal SEL2 is input to a first control terminal of the switch circuit 224-2 from the control circuit 3, and a control signal XSEL2 is input to a second control terminal of the switch circuit 224-2 from the control circuit 3. The control signal SEL2 and the control signal XSEL2 are digital signals whose logical levels are inverted from each other.

[0086] A control signal SEL3 is input to a first control terminal of the switch circuit 224-3 from the control circuit 3, and a control signal XSEL3 is input to a second control terminal of the switch circuit 224-3 from the control circuit 3. The control signal SEL3 and the control signal XSEL3 are digital signals whose logical levels are inverted from each other.

[0087] MOSFET 221-1 controls the supply of potential VINI to data line 12 connected to pixel circuit 20-1. MOSFET 221-2 controls the supply of potential VINI to data line 12 connected to pixel circuit 20-2. MOSFET 221-3 controls the supply of potential VINI to data line 12 connected to pixel circuit 20-3. Specifically, when the control signal XGINI is at L level, MOSFET 221-1 is turned on to supply potential VINI to data line 12 connected to pixel circuit 20-1, MOSFET 221-2 is turned on to supply potential VINI to data line 12 connected to pixel circuit 20-2, and MOSFET 221-3 is turned on to supply potential VINI to data line 12 connected to pixel circuit 20-3. Furthermore, when the control signal XGINI is at an H level, MOSFET 221-1 is turned off and no potential VINI is supplied to the data line 12 connected to pixel circuit 20-1, MOSFET 221-2 is turned off and no potential VINI is supplied to the data line 12 connected to pixel circuit 20-2, and MOSFET 221-3 is turned off and no potential VINI is supplied to the data line 12 connected to pixel circuit 20-3.

[0088] The MOSFET 222 controls the supply of the potential VREF to the data supply line 18. Specifically, when the control signal XGREF is at an L level, the MOSFET 222 is turned on and the potential VREF is supplied to the data supply line 18, and when the control signal XGREF is at an H level, the MOSFET 222 is turned off and the potential VREF is not supplied to the data supply line 18.

[0089] The switch circuit 224-1 controls the electrical connection between the data line 12 connected to the pixel circuit 20-1 and the data supply line 18. The switch circuit 224-2 controls the electrical connection between the data line 12 connected to the pixel circuit 20-2 and the data supply line 18. The switch circuit 224-3 controls the electrical connection between the data line 12 connected to the pixel circuit 20-3 and the data supply line 18. Specifically, when the control signals SEL1 and XSEL1 are at H level and L level, respectively, the switch circuit 224-1 is turned on, and the data line 12 connected to the pixel circuit 20-1 is electrically connected to the data supply line 18, and when the control signals SEL1 and XSEL1 are at L level and H level, respectively, the switch circuit 224-1 is turned off, and the data line 12 connected to the pixel circuit 20-1 is electrically disconnected from the data supply line 18. Furthermore, when the control signals SEL2 and XSEL2 are at H level and L level, respectively, the switch circuit 224-2 is turned on, electrically connecting the data line 12 connected to the pixel circuit 20-2 and the data supply line 18, and when the control signals SEL2 and XSEL2 are at L level and H level, respectively, the switch circuit 224-2 is turned off, electrically disconnecting the data line 12 connected to the pixel circuit 20-2 from the data supply line 18. Furthermore, when the control signals SEL3 and XSEL3 are at H level and L level, respectively, the switch circuit 224-3 is turned on, electrically connecting the data line 12 connected to the pixel circuit 20-3 and the data supply line 18, and when the control signals SEL3 and XSEL3 are at L level and H level, respectively, the switch circuit 224-3 is turned off, electrically disconnecting the data line 12 connected to the pixel circuit 20-3 from the data supply line 18.

[0090] When the data line 12 connected to the pixel circuit 20-1 is electrically connected to the data supply line 18 by the switch circuit 224-1, the data potential VDATA[j] is transferred from the data supply line 18 to the data line 12. Similarly, when the data line 12 connected to the pixel circuit 20-2 is electrically connected to the data supply line 18 by the switch circuit 224-2, the data potential VDATA[j] is transferred from the data supply line 18 to the data line 12. Similarly, when the data line 12 connected to the pixel circuit 20-3 is electrically connected to the data supply line 18 by the switch circuit 224-3, the data potential VDATA[j] is transferred from the data supply line 18 to the data line 12.

[0091] The control signals XGINI, SEL1, XSEL1, SEL2, XSEL2, SEL3, and XSEL3 are input in common to the n data line driving circuits 22.

[0092] 12, 10-bit image data VIDX that is switched in a time-division manner to R data, B data, and G data of m pixels P in a j column is input from the control circuit 3 to the j-th data potential generating circuit 23. In Fig. 12, the most significant bits of the image data VIDX are denoted as D9, D8, D7, D6, D5, D4, D3, D2, D1, and D0.

[0093] The data potential generating circuit 23 includes a capacitive DAC having capacitive elements 231-0 to 231-9 and 232, and switch circuits 233-0 to 233-9 and 234.

[0094] One end of each of the capacitive elements 231-0 to 231-4 and the output terminal of the switch circuit 234 are connected to one end of the capacitive element 232. One end of each of the capacitive elements 231-5 to 231-9 is connected to the other end of the capacitive element 232 and the data supply line 18. The other end of each of the capacitive elements 231-0 to 231-9 is connected to the output terminal of each of the switch circuits 233-0 to 233-9. A potential VL is supplied from the control circuit 3 to a first input terminal of each of the switch circuits 233-0 to 233-9, and a potential VH higher than the potential VL is supplied from the control circuit 3 to a second input terminal of each of the switch circuits 233-0 to 233-9. Bits D0 to D9 of the image data VIDX are input from the control circuit 3 to the control terminal of each of the switch circuits 233-0 to 233-9, respectively. When bit Dk is at an L level, switch circuit 233-k establishes electrical continuity between its first input terminal and output terminal, and when bit Dk is at an H level, it establishes electrical continuity between its second input terminal and output terminal. That is, switch circuit 233-k outputs a potential VL when bit Dk is at an L level, and outputs a potential VH when bit Dk is at an H level. k is an integer between 0 and 9.

[0095] If the capacitance value of the capacitive element 231-k is Ck, then, for example, C0:C1:C2:C3:C4:C5:C6:C7:C8:C9=1:2:4:8:16:1:2:4:8:16. The capacitance value Cser of the capacitive element 232 may be the same as C0 and C5. Note that a certain degree of error is allowed for the capacitance values ​​C0 to C9 and Cser as long as linearity is maintained between the value of the input 10-bit image data VIDX and the output data potential VDATA[j].

[0096] An input terminal of the switch circuit 234 is supplied with a potential VRST from the control circuit 3, and a control signal XRST is input from the control circuit 3 to a control terminal of the switch circuit 234. When the control signal XRST is at an L level, the input terminal and output terminal of the switch circuit 234 are electrically connected, and when the control signal XRST is at an H level, the input terminal and output terminal are not electrically connected. Therefore, when the control signal XRST is at an L level, the potential VRST is supplied to one end of each of the capacitive elements 231-0 to 231-4 and one end of the capacitive element 232. Note that one end of the capacitive elements 231-5 to 231-9 and the other end of the capacitive element 232 are connected to the data supply line 18, and therefore, when the control signal XGREF is at an L level, the potential VREF is supplied thereto. Therefore, when the control signal XRST and the control signal XGREF are both at an L level, the charges accumulated in the capacitive elements 231-0 to 231-9 and 232 are initialized.

[0097] On the other hand, when the control signals XRST and XGREF are both at H level, charges corresponding to the logic levels of the bits D0 to D9 are accumulated in each of the capacitive elements 231-0 to 231-9. Since one end of each of the capacitive elements 231-0 to 231-4 is connected to one end of the capacitive element 232, the one end of the capacitive element 232 has a potential corresponding to the logic levels of the bits D0 to D4. Furthermore, since one end of each of the capacitive elements 231-5 to 231-9 is connected to the other end of the capacitive element 232, the other end of the capacitive element 232 has a potential that is a potential corresponding to the logic levels of the bits D5 to D9, shifted in accordance with the potential at the one end of the capacitive element 232. Therefore, the potential at the other end of the capacitive element 232 changes linearly with the bits D9 to D0, and is supplied to the data supply line 18 as the data potential VDATA[j].

[0098] In this way, the jth data potential generating circuit 23, under the control of the control circuit 3, acquires and D / A converts the R data, B data, and G data of the m pixels P in the jth column included in the image data VIDX output from the control circuit 3 at timings specified by the control circuit 3, and generates data potentials VDATA[j] to be supplied to the 3j-2th, 3j-1st, and 3j-th data lines 12. Therefore, the data potential VDATA[j] switches in a time-division manner at the timings at which the R data, B data, or G data is written to the 3m pixel circuits 20 corresponding to the m pixels P in the jth column.

[0099] Next, the operation of the display device 1 of the second embodiment will be described with reference to Figs. 13 to 19. Fig. 13 is a timing chart showing an example of waveforms of various signals in the display device 1 of the second embodiment. Figs. 14 to 19 are diagrams in which the on / off of the MOSFET and switch circuit in each period and supply paths of various potentials are added to Fig. 12. Note that the description of operations similar to those of the display device 1 of the first embodiment will be omitted or simplified.

[0100] 13, during a horizontal scanning period 1H for the i-th row, the scanning line driving circuit 21 commonly outputs control signals XGEL[i], XGOR[i], XGCMP[i] and a scanning signal XGWR[i] to 3n pixel circuits 20 corresponding to n pixels P in the i-th row. Furthermore, the control circuit 3 commonly outputs control signals XGINI, XGREF, SEL1, XSEL1, SEL2, XSEL2, SEL3, and XSEL3 to n data line driving circuits 22. Note that FIG. 13 is a timing chart focusing on the horizontal scanning period 1H for the i-th row after the horizontal scanning periods 1H for the 1st to (i-1)th rows have ended.

[0101] 13, the horizontal scanning period 1H of the i-th row includes an initialization period a, a compensation period b after the initialization period a, and a writing period d after the compensation period b. The writing period d further includes a first writing period d1, a second writing period d2, and a third writing period d3. After the writing period d, there is a gap, followed by a light emitting period e, and after a period of one frame, the horizontal scanning period 1H of the i-th row begins again.

[0102] As shown in FIG. 13, in the horizontal scanning period 1H of the i-th row, during the initialization period a, the scanning signal XGWR[i] is at L level. Furthermore, the control signal XGOR[i] is at L level, and the control signals XGEL[i] and XGCMP[i] are at H level. Furthermore, the control signals XGREF, XGINI, and XRST are at L level. Furthermore, the control signals SEL1, SEL2, and SEL3 are at L level, and the control signals XSEL1, XSEL2, and XSEL3 are at H level. Therefore, as shown in FIG. 14, during the initialization period a, in the pixel circuits 20-1, 20-2, and 20-3, the MOSFETs 203 and 206 are turned on, and the MOSFETs 204 and 205 are turned off. Furthermore, in the data line driving circuit 22, the MOSFETs 221-1, 221-2, 221-3, and 222 are turned on, and the switch circuits 224-1, 224-2, and 224-3 are turned off. Therefore, in pixel circuits 20-1, 20-2, and 20-3, potential VINI is supplied to the gate of MOSFET 202 and the other end of capacitive element 201 via data line 12. Furthermore, potential V0 is supplied to the anode of light-emitting element 207 via power supply line 15. That is, the potentials of data line 12, the gate of MOSFET 202, and the other end of capacitive element 201 are initialized to potential VINI, and the potential of the anode of light-emitting element 207 is initialized to potential V0. Furthermore, in data line driving circuit 22, a predetermined potential VREF is supplied to data supply line 18, which is the output node of the capacitive DAC, one end of each of capacitive elements 231-5 to 231-9, and the other end of capacitive element 232, and potential VRST is supplied to one end of each of capacitive elements 231-0 to 231-4 and one end of capacitive element 232, and the charges accumulated in capacitive elements 231-0 to 231-9 and 232 are initialized.

[0103] As shown in FIG. 13, in the horizontal scanning period 1H of the i-th row, during the compensation period b, the scanning signal XGWR[i] is at the L level. Furthermore, the control signals XGOR[i] and XGCMP[i] are at the L level, and the control signal XGEL[i] is at the H level. Furthermore, the control signal XGINI is at the H level, and the control signals XGREF and XRST are at the L level. Furthermore, the control signals SEL1, SEL2, and SEL3 are at the L level, and the control signals XSEL1, XSEL2, and XSEL3 are at the H level. Therefore, as shown in FIG. 15, during the compensation period b, in the pixel circuits 20-1, 20-2, and 20-3, the MOSFETs 203, 204, and 206 are turned on, and the MOSFET 205 is turned off. Furthermore, in the data line driving circuit 22, the MOSFETs 221-1, 221-2, and 221-3 are turned off, the MOSFET 222 is turned on, and the switch circuits 224-1, 224-2, and 224-3 are turned off. Therefore, in pixel circuits 20-1, 20-2, and 20-3, a current flows from the power supply line carrying potential VEL to the gate of MOSFET 202 via MOSFETs 202, 204, and 205, causing the potentials of data line 12, the gate of MOSFET 202, and the other end of capacitive element 201 to rise from potential VINI. At this time, MOSFET 202 is in a state where its gate and drain are connected, i.e., a diode-connected state, so that the voltage between the gate and source of MOSFET 202 converges to the threshold voltage Vth of MOSFET 202. Since MOSFET 202 is a P-channel type, the threshold voltage Vth is a negative voltage. Because potential VEL is supplied to the source of MOSFET 202, the potentials of data line 12, the gate of MOSFET 202, and the other end of capacitive element 201 converge to potential (VEL-|Vth|). In addition, the potential of the anode of light-emitting element 207 remains at potential V0. Furthermore, in the data line driving circuit 22, a predetermined potential VREF is supplied to the data supply line 18, which is the output node of the capacitive DAC, and the initialization of the charges accumulated in the capacitive elements 231-0 to 231-9 and 232 continues.

[0104] 13, in the horizontal scanning period 1H of the i-th row, the scanning signal XGWR[i] is at the L level during the writing period d. Also, the control signal XGOR[i] is at the L level, and the control signals XGCMP[i] and XGEL[i] are at the H level. Also, the control signal XGINI is at the H level. Therefore, as shown in FIGS. 16, 17, and 18, in the writing period d, the MOSFETs 203 and 206 are turned on and the MOSFETs 204 and 205 are turned off in the pixel circuits 20-1, 20-2, and 20-3.

[0105] 16, the MOSFET 222 is turned off, and the data potential generating circuit 23 generates and outputs a data potential VDATA[j] to the data supply line 18. The data potential VDATA[j] is then transferred from the data supply line 18 to the data line 12 connected to the pixel circuit 20-1 via the switch circuit 224-1, and is then supplied to the other end of the capacitive element 201 and the gate of the MOSFET 202 via the MOSFET 203 in the pixel circuit 20-1.

[0106] 17, the MOSFET 222 is turned off, and the data potential generating circuit 23 generates and outputs a data potential VDATA[j] to the data supply line 18. The data potential VDATA[j] is then transferred from the data supply line 18 to the data line 12 connected to the pixel circuit 20-2 via the switch circuit 224-2, and is then supplied to the other end of the capacitive element 201 and the gate of the MOSFET 202 via the MOSFET 203 in the pixel circuit 20-2.

[0107] 18, the MOSFET 222 is turned off, and the data potential generating circuit 23 generates and outputs a data potential VDATA[j] to the data supply line 18. The data potential VDATA[j] is then transferred from the data supply line 18 to the data line 12 connected to the pixel circuit 20-3 via the switch circuit 224-3, and is then supplied to the other end of the capacitive element 201 and the gate of the MOSFET 202 via the MOSFET 203 in the pixel circuit 20-3.

[0108] Immediately before each of the first write period d1, the second write period d2, and the third write period d3, the control signals XGREF and XRST go to L level, the MOSFET 222 turns on, and the charges accumulated in the capacitance elements 231-0 to 231-9 and 232 are initialized.

[0109] Here, just before both the MOSFET 203 and the switch circuit 224-1 of the pixel circuit 20-1 are turned on, the potential of the data line 12 is potential (VEL-|Vth|), and when both the MOSFET 203 and the switch circuit 224-1 are turned on, the potential of the data supply line 18 becomes the data potential VDATA[j]. Therefore, due to capacitive coupling between the capacitor 25 and the capacitive elements 231-0 to 231-9, 232 of the data potential generating circuit 23, the potential of the data line 12 becomes potential ((Cd·(VEL-|Vth|)+Cst·VDATA[j]) / (Cd+Cst)). Here, Cd is the capacitance value of the capacitor 25, and Cst is the combined capacitance value of the capacitor 25 and the capacitive elements 231-0 to 231-9, 232. The same applies to the potentials of the data lines 12 connected to the pixel circuits 20-2 and 20-3, respectively. Thereafter, when the scanning signal XGWR[j] goes low, the MOSFETs 203 are turned off in the pixel circuits 20-1, 20-2, and 20-3, and the potential of the gate of the MOSFET 202 is fixed at the potential ((Cd·(VEL−|Vth|)+Cst·VDATA[j]) / (Cd+Cst)).

[0110] As shown in Fig. 13, in the horizontal scanning period 1H of the i-th row, the scanning signal XGWR[i] is at H level during the light emission period e. Also, the control signal XGEL[i] is at L level, and the control signals XGCMP[i] and XGOR[i] are at H level. Therefore, as shown in Fig. 19, in the light emission period e, in the pixel circuits 20-1, 20-2, and 20-3, the MOSFET 205 is turned on, and the MOSFETs 203, 204, and 206 are turned off. Therefore, the current flowing from the source to the drain of the MOSFET 202 is supplied to the light emitting element 207 via the MOSFET 205, causing the light emitting element 207 to emit light. The potential of the source of MOSFET 202 is potential VEL, and the potential of the gate of MOSFET 202 is potential ((Cd·(VEL−|Vth|)+Cst·VDATA[j]) / (Cd+Cst)), so that a current according to the data potential VDATA[j] is supplied to light-emitting element 207 while compensating for the threshold voltage Vth of MOSFET 202.

[0111] As shown in Figure 13, in the horizontal scanning period 1H of the i+1th row following the horizontal scanning period 1H of the i-th row, the control signals XGEL[i+1], XGOR[i+1], XGCMP[i+1] and scanning signal XGWR[i+1] have waveforms that are shifted by a time equivalent to the cycle of the horizontal scanning period 1H from the control signals XGEL[i], XGOR[i], XGCMP[i] and scanning signal XGWR[i].

[0112] In the second embodiment, the MOSFET 202 is an example of a "first transistor," the MOSFET 203 is an example of a "second transistor," the MOSFET 204 is an example of a "third transistor," and the MOSFET 205 is an example of a "fourth transistor." The potential VINI is an example of a "first potential," and the potential VREF is an example of a "second potential." The initialization period a is an example of a "first period," the compensation period b is an example of a "second period," the writing period d is an example of a "third period," and the light-emitting period e is an example of a "fourth period."

[0113] As described above, in the display device 1 of the second embodiment, during the initialization period a, the potential of the gate of the MOSFET 202 is initialized to the potential VINI, and during the write period d, the data potential VDATA[j] is supplied to the gate of the MOSFET 202. Then, during the compensation period b between the initialization period a and the write period d, the voltage between the gate and source of the MOSFET 202 is set to the threshold voltage Vth, so that during the write period d, the gate of the MOSFET 202 is held at a potential at which the threshold voltage Vth is compensated. Specifically, during the first write period d1, the second write period d2, and the third write period d3 included in the write period d, the gate of the MOSFET 202 is held at a potential at which the threshold voltage Vth is compensated due to coupling between the capacitance of the capacitive DAC, the output node of which is connected to the data supply line 18, and the capacitance 25 of the data line 12. Therefore, during the light emission period e, the light emitting element 207 is supplied with a current corresponding to the data potential VDATA[j] while the threshold voltage Vth of the MOSFET 202 is compensated, allowing the light emitting element 207 to emit light with precision. Therefore, according to the display device 1 of the second embodiment, there is no need to provide a coupling capacitance between the data line 12 and the pixel circuit 20, and the data line driving circuit 22 can be simplified and its area size can be reduced.

[0114] Furthermore, according to the display device 1 of the second embodiment, after the data supply line 18, which is the output node of the capacitive DAC, is initialized to the potential VREF, the capacitive DAC performs D / A conversion in the first write period d1, the second write period d2, and the third write period d3, thereby reducing the time required for D / A conversion.

[0115] Furthermore, according to the display device 1 of the second embodiment, a capacitive DAC that generates the data potential VDATA[j] is connected to the data supply line 18, so there is no need to provide a capacitive element for storing data on the data supply line 18, which is advantageous for miniaturization.

[0116] 2.Electronic equipment A head-mounted display will be described as an example of the electronic device of this embodiment. Fig. 20 is a perspective view that schematically shows a head-mounted display 900, which is an example of the electronic device of this embodiment.

[0117] As shown in Fig. 20, the head mounted display 900 is a head-mounted display that has an appearance similar to glasses. The head mounted display 900 is worn on the head of an observer. The observer is a user who uses the head mounted display 900. The head mounted display 900 allows the observer to view image light formed by a virtual image, and also allows the observer to view an external world image in a see-through manner.

[0118] The head mounted display 900 has, for example, a first display unit 910a, a second display unit 910b, a frame 920, a first temple 930a, and a second temple 930b.

[0119] The first display unit 910a and the second display unit 910b display images. Specifically, the first display unit 910a displays a virtual image for the observer's right eye. The second display unit 910b displays a virtual image for the observer's left eye. The display units 910a and 910b each include, for example, an image forming device 911 and a light guide device 915.

[0120] The image forming device 911 forms image light. The image forming device 911 has an optical system, such as a light source and a projection device, and an external member 912. The external member 912 houses the light source and the projection device.

[0121] The light guide device 915 covers the viewer's eyes. The light guide device 915 guides the image light formed by the image forming device 911, and allows the viewer to view the image light overlapping with external light.

[0122] The frame 920 supports the first display unit 910a and the second display unit 910b. The frame 920, for example, surrounds the display units 910a and 910b. In the illustrated example, the image forming device 911 of the first display unit 910a is attached to one end of the frame 920. The image forming device 911 of the second display unit 910b is attached to the other end of the frame 920.

[0123] A first temple 930a and a second temple 930b extend from the frame 920. In the illustrated example, the first temple 930a extends from one end of the frame 920. The second temple 930b extends from the other end of the frame 920.

[0124] The first temple 930a and the second temple 930b are suspended over the ears of the viewer when the viewer wears the head mounted display 900. The viewer's head is positioned between the temples 930a and 930b.

[0125] 21 is a diagram schematically illustrating an image forming device 911 and a light guide device 915 of a first display unit 910a of a head mounted display 900. The first display unit 910a and the second display unit 910b basically have the same configuration. Therefore, the following description of the first display unit 910a can also be applied to the second display unit 910b.

[0126] As shown in FIG. 21, the image forming device 911 includes, for example, a display device 1 as a light source and a projection device 914 for forming an image.

[0127] The projection device 914 projects the image light emitted from the display device 1 toward the light guide device 915. The projection device 914 is, for example, a projection lens. The lens constituting the projection device 914 may have an axially symmetrical surface as its lens surface.

[0128] The light guiding device 915 is accurately positioned relative to the projection device 914, for example, by being screwed to the lens barrel of the projection device 914. The light guiding device 915 has, for example, an image light guiding member 916 that guides the image light, and a see-through member 918 for see-through.

[0129] The image light emitted from the projection device 914 is incident on the image light guide member 916. The image light guide member 916 is a prism that guides the image light toward the viewer's eyes. The image light that has entered the image light guide member 916 is repeatedly reflected on the inner surface of the image light guide member 916, and is then reflected by the reflective layer 917 and emitted from the image light guide member 916. The image light that has emitted from the image light guide member 916 reaches the viewer's eyes. The reflective layer 917 is made of, for example, a metal or a dielectric multilayer film. The reflective layer 917 may be a half mirror.

[0130] The transparent member 918 is adjacent to the image light guiding member 916. The transparent member 918 is fixed to the image light guiding member 916. For example, the outer surface of the transparent member 918 is continuous with the outer surface of the image light guiding member 916. The transparent member 918 allows the viewer to see outside light through it. The image light guiding member 916 also has a function of allowing the viewer to see outside light through it, in addition to the function of guiding image light. Note that the head mounted display 900 may be configured not to allow the viewer to see outside light through it.

[0131] The electronic device of this embodiment includes a display device 1 in which the circuit for driving the pixel circuits 20 is simplified to reduce the area size, and therefore can be easily miniaturized.

[0132] The electronic device having the display device 1 is not limited to a head-mounted display, but may be, for example, an EVF, a projector, a wearable display such as a smartwatch, or an in-vehicle head-up display. EVF is an abbreviation for Electronic View Finder.

[0133] The present invention is not limited to the present embodiment, and various modifications are possible within the scope of the present invention.

[0134] The above-described embodiments and modifications are merely examples, and the present invention is not limited to these. For example, the embodiments and modifications can be combined as appropriate.

[0135] The present invention includes configurations that are substantially the same as the configurations described in the embodiments, for example, configurations with the same functions, methods, and results, or configurations with the same purpose and effects. The present invention also includes configurations in which non-essential parts of the configurations described in the embodiments are replaced. The present invention also includes configurations that achieve the same effects or purposes as the configurations described in the embodiments. The present invention also includes configurations in which publicly known technology is added to the configurations described in the embodiments.

[0136] The following can be derived from the above-described embodiment and modifications.

[0137] One aspect of the display device is The scan line and The data line and pixel circuits provided corresponding to the scanning lines and the data lines; a data potential generating circuit that generates a data potential; the pixel circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a light emitting element; the first transistor supplies a current to the light emitting element according to a voltage between a gate and a source; the second transistor controls an electrical connection between the data line and the gate of the first transistor in response to a potential of the scan line; the third transistor controls an electrical connection between the data line and the drain of the first transistor; the fourth transistor controls an electrical connection between the light emitting element and the drain of the first transistor; In the first period, the second transistor is turned on, the third transistor and the fourth transistor are turned off, and a predetermined first potential is supplied to the gate of the first transistor via the data line; In a second period after the first period, the second transistor and the third transistor are turned on, the fourth transistor is turned off, and the data line is electrically connected to the gate and the drain of the first transistor; In a third period after the second period, The second transistor is turned on, the third transistor and the fourth transistor are turned off, and the data potential is supplied to the gate of the first transistor via the data line and the second transistor.

[0138] In this display device, during a first period, the potential of the gate of the first transistor is initialized to a first potential, and during a third period, a data potential is supplied to the gate of the first transistor. Then, during a second period between the first and third periods, the voltage between the gate and source of the first transistor is set to the threshold voltage, and therefore, during the third period, the gate of the first transistor is maintained at a potential at which the threshold voltage is compensated. Therefore, the light-emitting element is supplied with a current corresponding to the data potential while compensating for the threshold voltage of the first transistor, allowing for accurate light emission. Therefore, with this display device, there is no need to provide a coupling capacitance between the data line and the pixel circuit, and the circuitry for driving the pixel circuit can be simplified and its area size reduced.

[0139] In one aspect of the display device, The data potential generating circuit may include a capacitive DAC that outputs the data potential.

[0140] In one aspect of the display device, During the second period, a predetermined second potential may be supplied to the output node of the capacitive DAC.

[0141] According to this display device, the output node of the capacitive DAC is initialized to the second potential in the second period, and then the capacitive DAC performs D / A conversion in the third period, thereby reducing the time required for D / A conversion.

[0142] One aspect of the display device is a data supply line to which the data potential generated by the data potential generating circuit is supplied; a switch circuit for controlling electrical connection between the data line and the data supply line; During the first period and the second period, the switch circuit is turned off, In the third period, the switch circuit may be turned on, and the data potential output from the data potential generating circuit may be transferred from the data supply line to the data line.

[0143] According to this display device, during the third period, the capacitance of the capacitive DAC connected to the data supply line and the capacitance of the data line couple to hold the gate of the first transistor at a potential at which its threshold voltage is compensated, allowing the light-emitting element to emit light with precision. Also, according to this display device, since the capacitive DAC that generates the data potential is connected to the data supply line, there is no need to provide a capacitive element for data retention on the data supply line, which is advantageous for miniaturization.

[0144] In one aspect of the display device, The data potential generating circuit may include an amplifier circuit.

[0145] One aspect of the display device is a data supply line to which the data potential generated by the data potential generating circuit is supplied; A data transfer line; a capacitive element connected to the data transfer line; a first switch circuit that controls an electrical connection between the data line and the data transfer line; a second switch circuit that controls an electrical connection between the data transfer line and the data supply line; During the first period and the second period, the first switch circuit is turned off, During the first period and the third period, the second switch circuit is turned off, during a period overlapping with a part of the second period, the second switch circuit is turned on, the data potential output from the data potential generation circuit is transferred from the data supply line to the data transfer line, and the data potential transferred to the data transfer line is held in the capacitive element; In the third period, the first switch circuit may be turned on, and the data potential held in the capacitance element may be supplied to the gate of the first transistor.

[0146] According to this display device, during a period overlapping with a part of the second period, the data potential transferred from the data supply line to the data transfer line is held in the capacitive element, and during a third period, due to coupling between the capacitive element and the capacitance of the data line, the gate of the first transistor is held at a potential at which its threshold voltage is compensated, thereby enabling the light-emitting element to emit light with precision.Furthermore, according to this display device, since the period during which the data potential is transferred from the data supply line to the data transfer line and held in the capacitive element overlaps with a part of the second period, the time required to write data to the pixel circuit can be shortened.

[0147] In one aspect of the display device, In a fourth period after the third period, The second transistor and the third transistor may be turned off, the fourth transistor may be turned on, and a current flowing from the source to the drain of the first transistor may be supplied to the light-emitting element via the fourth transistor, causing the light-emitting element to emit light.

[0148] According to this display device, in the fourth period, the light-emitting element is supplied with a current corresponding to the potential held at the gate of the first transistor in the third period while compensating for the threshold voltage of the first transistor, thereby enabling the light-emitting element to emit light with precision.

[0149] One aspect of the electronic device is The display device has one aspect of the above.

[0150] This electronic device has a display device with a reduced area size achieved by simplifying the circuitry that drives the pixel circuits, and therefore can be easily miniaturized. [Explanation of symbols]

[0151] 1... display device, 2... display panel, 3... control circuit, 11... scanning line, 12... data line, 15... power supply line, 17-1, 17-2, 17-3... data transfer line, 18... data supply line, 20, 20-1, 20-2, 20-3... pixel circuit, 21... scanning line drive circuit, 22... data line drive circuit, 23... data potential generation circuit, 25... capacitor, 112... display area, 120... FPC, 124... external connection terminal, 130... case, 201... capacitance element, 202 to 206... MOSFET, 207... light emitting element, 221-1, 221-2, 221-3... MOSFET, 222, 222-1, 222-2, 222-3... MOSF ET, 223-1, 223-2, 223-3...switch circuits, 224-1, 224-2, 224-3...switch circuits, 225-1, 225-2, 225-3...capacitive elements, 231-0 to 231-9...capacitive elements, 232...capacitive elements, 233-0 to 233-9, 234...switch circuits, 900...head mounted display, 910a...first display unit, 910b...second display unit, 911...image forming device, 912...external member, 914...projection device, 915...light guide device, 916...image light guide member, 917...reflective layer, 918...transparent member, 920...frame, 930a...first temple, 930b...second temple

Claims

1. The scan line and The data line and pixel circuits provided corresponding to the scanning lines and the data lines; a data potential generating circuit that generates a data potential; the pixel circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a light emitting element; the first transistor supplies a current to the light emitting element according to a voltage between a gate and a source; the second transistor controls an electrical connection between the data line and the gate of the first transistor in response to a potential of the scanning line; the third transistor controls an electrical connection between the data line and the drain of the first transistor; the fourth transistor controls an electrical connection between the light emitting element and the drain of the first transistor; In the first period, the second transistor is turned on, the third transistor and the fourth transistor are turned off, and a predetermined first potential is supplied to the gate of the first transistor via the data line; In a second period after the first period, the second transistor and the third transistor are turned on, the fourth transistor is turned off, and the data line is electrically connected to the gate and the drain of the first transistor; In a third period after the second period, a display device in which the second transistor is turned on, the third transistor and the fourth transistor are turned off, and the data potential is supplied to the gate of the first transistor via the data line and the second transistor;

2. In claim 1, The data potential generating circuit includes a capacitive DAC that outputs the data potential.

3. In claim 2, In the second period, a predetermined second potential is supplied to the output node of the capacitive DAC.

4. In claim 2, a data supply line to which the data potential generated by the data potential generating circuit is supplied; a switch circuit for controlling electrical connection between the data line and the data supply line; the switch circuit is turned off during the first period and the second period; In the third period, the switch circuit is turned on, and the data potential output from the data potential generating circuit is transferred from the data supply line to the data line.

5. In claim 1, The display device, wherein the data potential generating circuit includes an amplifier circuit.

6. In claim 1, a data supply line to which the data potential generated by the data potential generating circuit is supplied; A data transfer line; a capacitive element connected to the data transfer line; a first switch circuit for controlling an electrical connection between the data line and the data transfer line; a second switch circuit that controls an electrical connection between the data transfer line and the data supply line; the first switch circuit is turned off during the first period and the second period; During the first period and the third period, the second switch circuit is turned off, during a period overlapping with a part of the second period, the second switch circuit is turned on, the data potential output from the data potential generation circuit is transferred from the data supply line to the data transfer line, and the data potential transferred to the data transfer line is held in the capacitive element; In the third period, the first switch circuit is turned on, and the data potential held in the capacitance element is supplied to the gate of the first transistor.

7. In claim 1, In a fourth period after the third period, the second transistor and the third transistor are turned off, the fourth transistor is turned on, and a current flowing from the source to the drain of the first transistor is supplied to the light-emitting element via the fourth transistor, causing the light-emitting element to emit light.

8. An electronic device comprising the display device according to claim 1 .

Images