Semiconductor device

Abstract

To provide a semiconductor device that suppresses an increase in package size.SOLUTION: A semiconductor device comprises: a second semiconductor chip communicating with a first semiconductor chip via a signal wire; and a signal latch unit which, when receiving a start signal indicating that an operation of detecting the state of the first semiconductor chip will start, counts up the count value in accordance with a specific clock signal, and latches on the basis of the count value the value of a signal indicating the first state of the first semiconductor chip and the value of a signal indicating the second state of the first semiconductor chip that is different from the first state that have been received via the signal wire. The signal latch unit is provided on the second semiconductor chip.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] The multi-die package disclosed in Patent Document 1 has many inter-chip signal lines for multiple dies (semiconductor chips) to communicate data. For example, if there is only one type of status signal for multiple semiconductor chips to check each other's status, one signal line is used for the multiple semiconductor chips to communicate with each other. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2018-510512 Summary of the Invention [Problem to be solved by the invention]

[0004] However, when there are multiple types of status signals to check multiple statuses, the number of signal lines to individually transmit each status signal increases, the number of terminals on the semiconductor device to connect the multiple signal lines increases, and the size of the package that mounts the multiple semiconductor devices also increases. As such, the conventional technology leaves room for improvement in terms of transmitting status signals in inter-chip communication.

[0005] In view of the above circumstances, the present disclosure has an object to provide a semiconductor device that suppresses an increase in package size. [Means for solving the problem]

[0006] In order to solve the above problem, the semiconductor device according to the present disclosure comprises a second semiconductor chip that communicates with a first semiconductor chip via a signal line, and a signal capturing unit that, when receiving a start signal indicating the start of an operation to detect the state of the first semiconductor chip, counts up a count value according to a specific clock signal, and captures, based on the count value, the value of a signal indicating a first state of the first semiconductor chip received via the signal line and the value of a signal indicating a second state of the first semiconductor chip that is different from the first state, and the signal capturing unit is provided in the second semiconductor chip. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is an external view of a semiconductor device 100 according to an embodiment of the present disclosure. [Figure 2A] FIG. 2A is a hardware configuration diagram of a semiconductor device 100 according to an embodiment of the present disclosure. [Figure 2B] FIG. 2B is a hardware configuration diagram of the semiconductor device 100 according to the embodiment of the present disclosure. [Figure 3] FIG. 3 is a diagram showing an example of the configuration of the semiconductor device 100. As shown in FIG. [Figure 4] FIG. 4 is a timing chart for explaining the operation of the semiconductor device 100. In FIG. [Figure 5] FIG. 5 is a diagram showing an example of the configuration of a semiconductor device 100A according to a comparative example. [Figure 6] FIG. 6 is a timing chart for explaining the operation of the semiconductor device 100A according to the comparative example. [Figure 7] FIG. 7 is a diagram showing an example of the configuration of a semiconductor device 100-1 according to a modified example. [Figure 8] FIG. 8 is a timing chart for explaining the operation of the semiconductor device 100-1 according to the modified example. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments will be described with reference to the drawings. Note that the same or similar reference numerals are used to designate the same functions or configurations, and descriptions thereof will be omitted as appropriate.

[0009] (Embodiment) FIG. 1 is an external view of a semiconductor device 100 according to an embodiment of the present disclosure. FIGS. 2A and 2B are hardware configuration diagrams of the semiconductor device 100 according to an embodiment of the present disclosure. The semiconductor device 100 may be interpreted as a multi-die integrated circuit. The semiconductor device 100 may include a first semiconductor chip 101 and a second semiconductor chip 102. Each of the first semiconductor chip 101 and the second semiconductor chip 102 may be interpreted as a die. As shown in FIG. 2A, the second semiconductor chip 102 communicates with the first semiconductor chip 101 via a signal line SW and a bus BUS.

[0010] 2B, the semiconductor device 100 may include an input / output I / F (Interface) 41, a memory 42, and a processor 43. The input / output I / F 41 may be interpreted as an interface for communicating with external devices. The memory 42 may store a program 42a that monitors a state. The processor 43 may execute a specific process by deploying the program 42a. The functions realized by the program 42a may be interpreted as a signal acquisition unit and a state detection unit, which will be described later.

[0011] Next, the details of the configuration of the semiconductor device 100 will be specifically described with reference to Fig. 3. Fig. 3 is a diagram showing an example of the configuration of the semiconductor device 100.

[0012] (First semiconductor chip 101) The first semiconductor chip 101 may include a frame start signal generator 1, a counter 2, a selector 3, a status signal generator 4, and a clock generator 5.

[0013] (Frame start signal generator 1) The frame start signal generating unit 1 may generate a frame start signal VS synchronized with the clock clock_m. The frame start signal VS may be interpreted as a signal that synchronizes the count start timing of the first semiconductor chip 101 and the second semiconductor chip 102. The frame start signal VS may be interpreted as a start signal that indicates the start of an operation to detect the state of the first semiconductor chip 101.

[0014] (Counter 2) The counter 2 may start counting a count value count_m with the clock clock_m at the timing when the frame start signal VS is generated, and output the count value count_m. Specifically, when the potential of the frame start signal VS rises from a low level to a high level (VS_rise=H), the counter 2 resets the count value count_m and continues to count up while the frame start signal VS is at a high level.

[0015] (Selection 3) The selection unit 3 may generate and output a selection signal S12_SEL corresponding to the count value count_m. Specifically, when the count value count_m is a first value, the selection unit 3 may generate and output a first selection signal (S1_SEL) for selecting the value of a signal indicating a first state. When the count value count_m is a second value different from the first value, the selection unit 3 may generate and output a second selection signal (S2_SEL) for selecting the value of a signal indicating a second state.

[0016] (Status signal generator 4) The status signal generation unit 4 may switch and output a signal S12 indicating a status of the first semiconductor chip 101 corresponding to the type of the selection signal S12_SEL generated by the selection unit 3. Specifically, when the status signal generation unit 4 receives a first selection signal (S1_SEL), it may generate and output a signal (S1) indicating a first status of the first semiconductor chip 101. When the status signal generation unit 4 receives a second selection signal (S2_SEL), it may generate and output a signal (S2) indicating a second status of the first semiconductor chip 101. The signal S12 may be transmitted to the second semiconductor chip 102 via one signal line SW.

[0017] (Clock generation unit 5) The clock generating section 5 may generate a clock clock_m, which is a clock signal with a specific frequency.

[0018] (Second semiconductor chip 102) The second semiconductor chip 102 may include a signal acquisition section 10, a state detection section 20, and a clock generation section 30.

[0019] (Signal acquisition unit 10) When the signal acquisition unit 10 receives a frame start signal VS, it counts up the count value count_s according to the clock clock_s, and based on the count value count_s, it acquires the value of a signal indicating a first state of the first semiconductor chip 101 received via the signal line and the value of a signal indicating a second state of the first semiconductor chip 101 different from the first state, and may hold the values ​​of these signals.

[0020] Specifically, the signal acquisition unit 10 may count up the count value count_s when the potential of the frame start signal VS rises from a low level to a high level, and may acquire a signal (S1) indicating a first state when the count value count_s is a first value, and may acquire a signal (S2) indicating a second state when the count value count_s is a second value different from the first value.

[0021] The signal acquisition unit 10 may include a frame start detection unit 11, a counter 12, a selection unit 13, and a holding unit 14.

[0022] (Frame start detection unit 11) The frame start detection unit 11 may detect the rising edge of the frame start signal VS and generate and output a signal VS_rise indicating that the rising edge of the frame start signal VS has been detected. Specifically, the frame start detection unit 11 may include a register (e.g., a flip-flop) and an AND circuit (logical product unit). The register outputs an output signal VS_FF1 one clock after the rising edge of the frame start signal VS, and the AND circuit changes the potential of the signal VS_rise from low to high at the rising edge of the frame start signal VS, and when a signal obtained by inverting the level of the output signal VS_FF1 is input, changes the potential of the signal VS_rise from high to low.

[0023] (Counter 12) The counter 12 may start counting up the count value count_s when the frame start detection unit 11 detects the rising edge of the frame start signal VS. Specifically, the counter 12 may reset the count value count_s and start counting up when the potential of the signal VS_rise changes from high level to low level.

[0024] (Selection section 13) The selection unit 13 may generate and output a selection signal according to the count value count_s. Specifically, when the count value count_s is a first value, the selection unit 13 may generate and output a first selection signal S1_SEL for selecting the value of the signal indicating a first state. When the count value count_s is a second value different from the first value, the selection unit 13 may generate and output a second selection signal S2_SEL for selecting the value of the signal indicating a second state.

[0025] (Holding part 14) The holding unit 14 may latch the state of the signal selected by the selection unit 13. Specifically, when the first selection signal S1_SEL is input, the holding unit 14 may hold the value of the signal S12 indicating the first state transmitted from the first semiconductor chip 101, and output a signal S1_FF indicating the state to the state detection unit 20. Furthermore, when the second selection signal S2_SEL is input, the holding unit 14 may hold the value of the signal S12 indicating the second state transmitted from the first semiconductor chip 101, and output a signal S2_FF indicating the state to the state detection unit 20.

[0026] (Status detection unit 20) The state detection section 20 may detect the state of the first semiconductor chip 101 based on the value of the signal S1_FF indicating the first state and the value of the signal S2_FF indicating the second state, both held in the holding section 14.

[0027] Specifically, for example, when the value of signal S1_FF is low level, the state detection unit 20 may determine that the specific first function of the first semiconductor chip 101 is normal, and when the value of signal S1_FF is high level, the state detection unit 20 may determine that the specific first function of the first semiconductor chip 101 is abnormal. For example, when the value of signal S2_FF is low level, the state detection unit 20 may determine that the specific second function of the first semiconductor chip 101 is normal, and when the value of signal S2_FF is high level, the state detection unit 20 may determine that the specific second function of the first semiconductor chip 101 is abnormal.

[0028] In addition, in the semiconductor device 100 of the present disclosure, the first semiconductor chip 101 may have functions similar to those of the second semiconductor chip 102, and the second semiconductor chip 102 may have functions similar to those of the first semiconductor chip 101.

[0029] Next, the operation of the semiconductor device 100 will be described with reference to Fig. 4. Fig. 4 is a timing chart for explaining the operation of the semiconductor device 100.

[0030] At time t1, when the potential of the frame start signal VS changes from low level L to high level H, the potential of the signal VS_rise changes from high level H to low level L. This causes the first semiconductor chip 101 and the second semiconductor chip 102 to start counting.

[0031] For a certain period of time from time t2, the count value count_m is counted up by the clock clock_s. If the value of the count value count_m is, for example, 2 at time t3, the first selection signal S1_SEL is generated, and the value of the signal S1 indicating the first state is loaded into the second semiconductor chip 102. Since the potential of the signal S1 indicating the first state is low at time t3, the potential of the signal S1_FF indicating the first state changes from high to low at time t4.

[0032] If the value of the count value count_m is, for example, 3 at time t4, the second selection signal S2_SEL is generated, and the value of the signal S2 indicating the second state is captured in the second semiconductor chip 102. Since the potential of the signal S2 indicating the second state is high at time t4, the potential of the signal S2_FF indicating the second state remains high at time t5.

[0033] In this way, in the semiconductor device 100 of the present disclosure, a signal S12 indicating multiple states of the first semiconductor chip 101 can be transmitted to one signal line SW, and the second semiconductor chip 102 can detect the state of the first semiconductor chip 101 by using a potential change in the frame start signal VS as a trigger.

[0034] 5 is a diagram showing an example of the configuration of a semiconductor device 100A according to a comparative example. The semiconductor device 100A includes a plurality of signal lines SW for transmitting a signal S1 indicating a first state and a signal S2 indicating a second state.

[0035] 6 is a timing chart for explaining the operation of the semiconductor device 100A according to the comparative example. As shown in FIG. 6, when the potential of the frame start signal VS changes from low level L to high level H, the second semiconductor chip 102A detects the potential levels of the signals S1 and S2 transmitted to the respective signal lines SW. This makes it possible to detect multiple states of the first semiconductor chip 101A. However, in the semiconductor device 100A, as the number of types of signals increases, the number of signal lines SW also increases, which increases the number of terminals on the semiconductor device 100A for connecting the signal lines SW, and this may also increase the size of the package in which the semiconductor device 100A is mounted.

[0036] (Variation) 7 is a diagram showing an example of the configuration of a semiconductor device 100-1 according to a modified example. The semiconductor device 100-1 includes a signal capturing unit 10-1 instead of the signal capturing unit 10. The signal capturing unit 10-1 may include a frame start detecting unit 11 and a counter 12, similar to the signal capturing unit 10. The signal capturing unit 10-1 may include a selection unit 13-1, a holding unit 14-1, and a majority vote holding unit 15 instead of the selection unit 13 and the holding unit 14.

[0037] The selection unit 13-1 may output a first selection signal S1_SEL for successively selecting the value of the signal indicating the first state multiple times until the count value count_s reaches from a first value to a second value greater than the first value. The selection unit 13-1 may output a second selection signal S2_SEL for successively selecting the value of the signal indicating the second state multiple times until the count value count_s reaches from a third value greater than the second value to a fourth value greater than the third value.

[0038] The holding unit 14-1 may hold the value of the signal (S1_FF1, S1_FF2, S1_FF3) indicating the first state multiple times in succession when the first selection signal S1_SEL is input, and may hold the value of the signal (S2_FF1, S2_FF2, S2_FF3) indicating the second state multiple times in succession when the second selection signal S2_SEL is input. Note that the range in which these signals are held (selected) multiple times in succession can be changed arbitrarily.

[0039] The majority vote holding unit 15 may take a majority vote between the values ​​of the signals indicating the first states that have been held multiple times in succession and the values ​​of the signals indicating the second states, and hold the most prevalent signal value among the values ​​of the signals indicating the first states and the most prevalent signal value among the values ​​of the signals indicating the second states. Note that the number of holds (latches) required for the majority vote can be changed as desired.

[0040] In addition, in the semiconductor device 100-1 of the present disclosure, the first semiconductor chip 101 may have functions similar to those of the second semiconductor chip 102-1, and the second semiconductor chip 102-1 may have functions similar to those of the first semiconductor chip 101.

[0041] FIG. 8 is a timing chart for explaining the operation of the semiconductor device 100-1 according to the modified example.

[0042] At time t1, when the potential of the frame start signal VS changes from low level L to high level H, the potential of the signal VS_rise changes from high level H to low level L.

[0043] This causes counting to begin in the first semiconductor chip 101 and the second semiconductor chip 102-1. Specifically, counting begins for a certain period of time from time t2 when the clocks (clock_s, clock_m) after time t1 are input.

[0044] For example, when the count value count_m is between 0 and 5, the first semiconductor chip 101 outputs a signal S1 indicating a first state based on the state signal S12. At this time, the second semiconductor chip 102-1 generates a first selection signal S1_SEL to continuously capture the signal S1 indicating the first state multiple times. In other words, the second semiconductor chip 102-1 captures the value of the signal S1 indicating the first state every time the clock clock_s is input.

[0045] When the count value count_m is 0 to 5, the potential of the signal S1 indicating these first states is low, so the potential of each of the signals (S1_FF1, S1_FF2, S1_FF3) indicating the first states changes from high to low. The majority vote holding unit 15 takes a majority vote of the values ​​of the signals (S1_FF1, S1_FF2, S1_FF3) indicating the first states that have been held multiple times in succession. In this case, all three signals are low, so the majority vote holding unit 15 holds the signal S1_FF indicating the first state at low level and outputs the signal to the state detection unit 20.

[0046] When the count value count_m is between 6 and 11, the first semiconductor chip 101 outputs a signal S2 indicating the second state based on the state signal S12. At this time, the second semiconductor chip 102-1 captures the signal S2 indicating the second state by generating a second selection signal S2_SEL. In other words, the second semiconductor chip 102-1 captures the value of the signal S2 indicating the second state every time the clock clock_s is input.

[0047] When the count value count_m is 6 to 11, the potential of the signal S2 indicating these second states is high, so the potential of each of the signals (S2_FF1, S2_FF2, S2_FF3) indicating the second states remains high. The majority vote holding unit 15 takes a majority vote of the values ​​of the signals (S2_FF1, S2_FF2, S2_FF3) indicating the second states that have been held multiple times in succession. In this case, all three signals are high, so the majority vote holding unit 15 holds the signal S2_FF indicating the second state at high level and outputs the signal to the state detection unit 20.

[0048] (Actions and Effects) As described above, the semiconductor device 100, 100-1 of the present disclosure can transmit the signal S12 indicating multiple states of the first semiconductor chip 101 to a single signal line SW, and the second semiconductor chip 102 can detect the state of the first semiconductor chip 101 using a potential change in the frame start signal VS as a trigger. Therefore, even if the number of types of signals increases, an increase in the number of signal lines SW can be suppressed. Furthermore, the number of terminals on the semiconductor device 100, 100-1 for connecting the signal lines SW does not increase, and an increase in the size of the package in which the semiconductor device 100, 100-1 is mounted can be suppressed.

[0049] The first semiconductor chip 101 may be interpreted as either a master chip or a slave chip. When the first semiconductor chip 101 is the master chip, the second semiconductor chips 102 and 102-1 may be interpreted as slave chips, and when the first semiconductor chip 101 is the slave chip, the second semiconductor chips 102 and 102-1 may be interpreted as master chips.

[0050] In addition, the following supplementary notes are provided in relation to the above description.

[0051] (Appendix 1) a second semiconductor chip that communicates with the first semiconductor chip via a signal line; a signal capturing unit that, when receiving a start signal indicating the start of an operation to detect the state of the first semiconductor chip, counts up a count value in accordance with a specific clock signal, and captures, based on the count value, a value of a signal indicating a first state of the first semiconductor chip received via the signal line and a value of a signal indicating a second state of the first semiconductor chip different from the first state; The semiconductor device, wherein the signal capturing unit is provided on the second semiconductor chip. (Appendix 2) The signal acquisition unit a counter that starts counting up the count value when the start signal is received; a selection unit that outputs a first selection signal for selecting a value of the signal indicating the first state when the count value is a first value, and outputs a second selection signal for selecting a value of the signal indicating the second state when the count value is a second value different from the first value; a holding unit that holds the value of a signal indicating the first state when the first selection signal is input, and that holds the value of a signal indicating the second state when the second selection signal is input. (Appendix 3) The signal acquisition unit a counter that starts counting up the count value when the start signal is received; a selector that outputs a first selection signal for successively selecting the value of the signal indicating the first state multiple times until the count value reaches a second value greater than the first value from a first value, and outputs a second selection signal for successively selecting the value of the signal indicating the second state multiple times until the count value reaches a fourth value greater than the third value from a third value greater than the second value; a holding unit that holds the value of the signal indicating the first state multiple times in succession when the first selection signal is input, and that holds the value of the signal indicating the second state multiple times in succession when the second selection signal is input; 3. The semiconductor device according to claim 1, further comprising: a majority vote holding unit that takes a majority vote between the values ​​of the plurality of signals indicating the first state and the values ​​of the plurality of signals indicating the second state that are held multiple times in succession, and holds the signal value that is most prevalent among the values ​​of the plurality of signals indicating the first state and the signal value that is most prevalent among the values ​​of the plurality of signals indicating the second state. (Appendix 4) 4. The semiconductor device according to claim 2, further comprising a state detection unit that detects the state of the first semiconductor chip based on the value of the signal indicating the first state and the value of the signal indicating the second state held in the holding unit. (Appendix 5) a second semiconductor chip that communicates with the first semiconductor chip via a signal line; a signal capturing unit that, when receiving a start signal indicating the start of an operation to detect the state of the first semiconductor chip, counts up a count value in accordance with a specific clock signal, and captures, based on the count value, a value of a signal indicating a first state of the first semiconductor chip received via the signal line and a value of a signal indicating a second state of the first semiconductor chip different from the first state; The semiconductor device, wherein the signal capturing unit is provided on the second semiconductor chip. [Explanation of symbols]

[0052] 1 Frame start signal generator 2 Counters 3 Selection section 4. Status signal generator 5. Clock generation unit 10, 10-1 Signal acquisition section 11 Frame start detection section 12 Counters 13, 13-1 Selection section 14, 14-1 Holding part 15 Majority Holder 20 Status detection unit 30 Clock generation unit 42 memory 42a Program 43 processors 100, 100A, 100-1 Semiconductor device 101, 101A first semiconductor chip 102, 102A, 102-1 second semiconductor chip

Claims

1. a second semiconductor chip that communicates with the first semiconductor chip via a signal line; a signal capturing unit that, when receiving a start signal indicating the start of an operation to detect the state of the first semiconductor chip, counts up a count value in accordance with a specific clock signal, and captures, based on the count value, a value of a signal indicating a first state of the first semiconductor chip received via the signal line and a value of a signal indicating a second state of the first semiconductor chip different from the first state; The signal capturing unit is provided on the second semiconductor chip.

2. The signal acquisition unit a counter that starts counting up the count value when the start signal is received; a selector that outputs a first selection signal for selecting a value of the signal indicating the first state when the count value is a first value, and outputs a second selection signal for selecting a value of the signal indicating the second state when the count value is a second value different from the first value; 2. The semiconductor device according to claim 1, further comprising a holding section that holds a value of a signal indicating the first state when the first selection signal is input, and that holds a value of a signal indicating the second state when the second selection signal is input.

3. The signal acquisition unit a counter that starts counting up the count value when the start signal is received; a selector that outputs a first selection signal for successively selecting the value of the signal indicating the first state multiple times until the count value reaches a second value greater than the first value from a first value, and outputs a second selection signal for successively selecting the value of the signal indicating the second state multiple times until the count value reaches a fourth value greater than the third value from a third value greater than the second value; a holding unit that holds the value of the signal indicating the first state multiple times in succession when the first selection signal is input, and that holds the value of the signal indicating the second state multiple times in succession when the second selection signal is input; 2. The semiconductor device according to claim 1, further comprising: a majority vote holding unit that takes a majority vote between the values ​​of the plurality of signals indicating the first state and the values ​​of the plurality of signals indicating the second state that are held multiple times in succession, and holds the signal value that is most prevalent among the values ​​of the plurality of signals indicating the first state and the signal value that is most prevalent among the values ​​of the plurality of signals indicating the second state.

4. 4. The semiconductor device according to claim 2, further comprising a state detection unit that detects a state of the first semiconductor chip based on the value of the signal indicating the first state and the value of the signal indicating the second state held in the holding unit.

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