Semiconductor package

Abstract

To provide a semiconductor package in which two dies are stacked, and a manufacturing method for the semiconductor package.SOLUTION: A semiconductor package according to the present invention includes a plurality of semiconductor chips, a plurality of bonding pads existing between the semiconductor chips, a bonding insulating layer surrounding the bonding pads between the semiconductor chips, and a void control unit existing between the bonding pads. The bonding pads are directly connected to the semiconductor chips. The bonding insulating layer is directly connected to the semiconductor chips. The void control unit is a cavity closed by the bonding insulating layer, any one semiconductor chip of the semiconductor chips and the bonding insulating layer, or the semiconductor chips and the bonding insulating layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor package, and more particularly to a semiconductor package in which two dies are directly stacked by wafer-to-wafer bonding. [Background technology]

[0002] Due to the rapid development of the electronics industry and user demands, electronic devices are becoming smaller and lighter. As electronic devices become smaller and lighter, the semiconductor packages used therein are also becoming smaller and lighter, and there is a demand for higher integration and higher speed for the semiconductor packages. To meet this demand for higher integration and higher speed for semiconductor packages, semiconductor packages including stacked semiconductor chips have been developed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Korean Patent Publication No. 10-2008-0001623 Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention has been made in view of the above-mentioned conventional techniques, and an object of the present invention is to provide a semiconductor package having a semiconductor chip in which two dies are stacked. [Means for solving the problem]

[0005] In order to achieve the above-mentioned object, a semiconductor package according to one aspect of the present invention comprises a plurality of semiconductor chips, a plurality of bonding pads interposed between the plurality of semiconductor chips, a bonding insulating layer surrounding the plurality of bonding pads between the plurality of semiconductor chips, and a void control section interposed between the plurality of bonding pads, wherein the plurality of bonding pads are directly connected to the plurality of semiconductor chips, the bonding insulating layer is directly connected to the plurality of semiconductor chips, and the void control section is a cavity closed by the bonding insulating layer, any one of the plurality of semiconductor chips and the bonding insulating layer, or the plurality of semiconductor chips and the bonding insulating layer.

[0006] In order to achieve the above object, according to another aspect of the present invention, a semiconductor package includes a first semiconductor chip including a first semiconductor substrate having an active surface and an inactive surface opposite to each other and a plurality of first through-hole electrodes penetrating the first semiconductor substrate, a second semiconductor substrate having an active surface and an inactive surface opposite to each other and a plurality of second through-hole electrodes penetrating the second semiconductor substrate, the second semiconductor substrate being stacked on the first semiconductor chip such that the active surface of the second semiconductor substrate faces the inactive surface of the first semiconductor substrate, and a plurality of second semiconductor chips including a bottom second semiconductor chip and a top second semiconductor chip. The semiconductor device comprises a conductor chip, a plurality of bonding pads respectively interposed between the first semiconductor chip and the bottommost second semiconductor chip and between the plurality of adjacent second semiconductor chips, electrically connecting the plurality of first through electrodes and the plurality of second through electrodes, a bonding insulating layer surrounding the plurality of bonding pads between the first semiconductor chip and the bottommost second semiconductor chip and between the plurality of adjacent second semiconductor chips, and a first void control section interposed between the plurality of bonding pads, wherein the first void control section includes a cavity. [Effects of the Invention]

[0007] The semiconductor package of the present invention is formed by sequentially directly bonding a first semiconductor chip and a plurality of second semiconductor chips, thereby preventing bonding defects or voids caused by surface roughness between the first semiconductor chip and the plurality of second semiconductor chips during direct bonding. Furthermore, the semiconductor package of the present invention can control bonding defects or voids through a plurality of void control units, thereby providing a semiconductor package with improved reliability.

[0008] The effects of the present invention are not limited to those described above, and unmentioned effects will be clearly understood by those skilled in the art to which the present invention pertains from the present specification and drawings. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a schematic cross-sectional view illustrating a bonding structure according to an embodiment of the present invention; [Figure 2] 1 is a schematic plan view illustrating a first example of a bonding structure according to an embodiment of the present invention. [Figure 3A] FIG. 10 is a schematic plan view illustrating a second example of a bonding structure according to an embodiment of the present invention. [Figure 3B] FIG. 10 is a schematic plan view illustrating a third example of a bonding structure according to an embodiment of the present invention. [Figure 3C] FIG. 10 is a schematic plan view illustrating a fourth example of a bonding structure according to an embodiment of the present invention. [Figure 3D] FIG. 10 is a schematic plan view illustrating a fifth example of a bonding structure according to an embodiment of the present invention. [Figure 4] 10 is a schematic cross-sectional view illustrating a bonding structure according to another embodiment of the present invention; [Figure 5] 10 is a schematic cross-sectional view illustrating a bonding structure according to yet another embodiment of the present invention; [Figure 6]1 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention; [Figure 7] 2A to 2C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 8] 2A to 2C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 9] 2A to 2C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 10] 2A to 2C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. [Figure 11] 2A to 2C are cross-sectional views illustrating a method for manufacturing a semiconductor package according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0010] The advantages and features of the present invention, as well as methods for achieving them, will become clearer with reference to the following detailed embodiments in conjunction with the drawings. However, the present invention is not limited to the following embodiments, and may be embodied in various different forms. However, the present embodiments are provided to fully disclose the invention and fully convey the scope of the invention to those skilled in the art to which the present invention pertains, and the present invention is defined by the claims. In the drawings, the relative sizes of layers and regions are exaggerated for clarity of explanation.

[0011] When an element is referred to as being "connected to" or "coupled to" another element, this includes being directly connected to or coupled to the other element, or having other elements interposed therebetween. On the other hand, when an element is referred to as being "directly connected to" or "directly coupled to" another element, this means that there are no other elements interposed therebetween.

[0012] Like reference numerals refer to like elements throughout the specification. "And / or" includes each and every combination of one or more of the referenced items.

[0013] When an element or layer is referred to as being "on" or "on top of" another element or layer, it means not only directly on the other element or layer, but also when there are other layers or elements between them. On the other hand, when an element is referred to as being "directly on" or "directly above," it means that there are no other elements or layers between them.

[0014] Furthermore, spatially relative terms such as "bottom," "low," "top," and "upper" are used solely for convenience in describing relationships with other elements or features herein and may be interpreted to encompass various orientations of the device during use or operation other than as depicted. For example, if the device in the drawings were inverted, elements that are below other elements or features would then be above the other elements or features. Thus, the term "bottom" can encompass both an upper and lower orientation. The device may be rotated in a different orientation (e.g., rotated 90 degrees or otherwise) and the spatially relative descriptors used herein interpreted accordingly.

[0015] Even if terms such as "first," "second," etc. are used to describe various elements, components, and / or sections, it goes without saying that these elements, components, and / or sections are not limited by these terms. These terms are used only to distinguish one element, component, or section from another element, component, or section. Therefore, a first element, first component, or first section referred to below may also be a second element, second component, or second section within the technical spirit of the present invention.

[0016] The terms used herein are for the purpose of describing the present embodiment and are not intended to limit the present invention. In this specification, the singular forms "a," "an," and "the" also include the plural forms unless otherwise specified. When used in this specification, the words "comprises" and / or "comprising" do not exclude the presence or addition of one or more other components, steps, operations, and / or elements to which a reference is made.

[0017] Unless otherwise defined, all terms (including technical and scientific terms) used herein will be used in the sense commonly understood by a person of ordinary skill in the art to which the invention belongs. Furthermore, terms defined in commonly used dictionaries will not be interpreted ideally or excessively unless otherwise clearly defined.

[0018] Hereinafter, specific examples of the embodiments of the present invention will be described in detail with reference to the drawings. The same reference numerals are used for the same components in the drawings, and redundant explanations thereof will be omitted.

[0019] In this specification, the horizontal direction includes a first horizontal direction (X direction) and a second horizontal direction (Y direction) that intersect with each other. A direction that intersects with the first horizontal direction (X direction) and the second horizontal direction (Y direction) is referred to as a vertical direction (Z direction). In this specification, a vertical level is referred to as a height level according to the vertical direction (Z direction) of any configuration.

[0020] FIG. 1 is a schematic cross-sectional view illustrating a bonding structure 10 according to an embodiment of the present invention.

[0021] FIG. 2 is a schematic plan view illustrating a first example of a bonding structure 10 according to an embodiment of the present invention.

[0022] FIG. 1 corresponds to a cross section taken along line X1-X1' in FIG.

[0023] FIG. 2 is a plan view of the first level, designated "LV1" in FIG.

[0024] Referring to Figures 1 and 2, the bonding structure 10 includes a plurality of semiconductor chips CP including a lower semiconductor chip 12 and an upper semiconductor chip 14, a plurality of bonding pads 22 interposed between the plurality of semiconductor chips CP to connect the plurality of semiconductor chips CP to each other, a bonding insulating layer 24 interposed between the plurality of semiconductor chips CP to surround the plurality of bonding pads 22, and a plurality of void control portions 26.

[0025] The plurality of semiconductor chips CP are memory semiconductor chips. In an exemplary embodiment, the plurality of semiconductor chips CP are heterogeneous memory semiconductor chips. In one embodiment, any one of the plurality of semiconductor chips CP includes a serial-parallel conversion circuit and is a buffer chip for controlling the other plurality of semiconductor chips CP. In this case, the other plurality of semiconductor chips CP are memory chips including memory cells. In another exemplary embodiment, the plurality of semiconductor chips CP are homogeneous memory semiconductor chips. In one embodiment, the plurality of semiconductor chips CP are memory chips including memory cells.

[0026] The semiconductor chips CP are electrically connected to each other to transmit and receive signals and are provided with power and ground through the bonding pads 22. The bonding pads 22 are interposed between the semiconductor chips CP.

[0027] The bonding pads 22 are arranged spaced apart in a first horizontal direction (X direction) and a second horizontal direction (Y direction). The bonding pads 22 form at least one row and at least one column of the bonding pads 22. For example, the bonding pads 22 may include a first bonding pad group arranged spaced apart in the first horizontal direction (X direction), and the first bonding pad group includes a plurality of bonding pads 22 arranged spaced apart in the second horizontal direction (Y direction). The bonding pads 22 may also include a second bonding pad group arranged spaced apart in the second horizontal direction (Y direction), and the second bonding pad group includes a plurality of bonding pads 22 arranged spaced apart in the first horizontal direction (X direction). The first bonding pad group forms at least one row of the bonding pads 22, and the second bonding pad group forms at least one column of the bonding pads 22. The bonding pads 22 are circular as shown in FIG. 2, but this is merely an example and various shapes may be used. In an exemplary embodiment, "shape" refers to the shape of a bond pad (eg, bond pad 22) on the layout.

[0028] In an exemplary embodiment, the multiple bonding pads 22 are formed by forming conductive material layers on the surfaces of the multiple semiconductor chips CP that face each other, expanding the conductive material layers with heat so that they contact each other, and then diffusing metal atoms in the conductive material layers so that the conductive material layers become integrated with each other through diffusion bonding.

[0029] The plurality of bonding pads 22 are surrounded in a planar manner by a bonding insulating layer 24. The bonding insulating layer 24 is interposed between the plurality of semiconductor chips CP and surrounds each of the plurality of bonding pads 22.

[0030] In an exemplary embodiment, the bonding insulating layer 24 is formed through diffusion bonding, in which an insulating material layer is formed on each of the surfaces of the semiconductor chips CP that face each other, the insulating material layers are expanded by heat so that they contact each other, and atoms in the insulating material layers are diffused so that the insulating material layers become integrated with each other.

[0031] In an exemplary embodiment, the plurality of bonding pads 22 include a material capable of diffusion bonding, such as Cu, Al, or W. In an exemplary embodiment, the bonding insulation layer 24 is made of any one of SiO, SiN, SiCN, SiCO, and a polymer material. The polymer material is benzocyclobutene (BCB), polyimide (PI), polybenzoxazole (PBO), silicone, acrylate, or epoxy. For example, the bonding insulation layer 24 is made of silicon oxide.

[0032] The bonding structure 10 includes a plurality of void control portions 26 interposed between a plurality of semiconductor chips CP. The void control portions 26 have various shapes, such as slit shapes, groove shapes, or recess shapes. The void control portions 26 include any cavity filled with any inert gas or gaseous substance (including, but not limited to, air).

[0033] The plurality of void control portions 26 are interposed between pairs of adjacent bonding pads 22 among the plurality of bonding pads 22. The void control portions 26 are separated from the plurality of bonding pads 22 with a part of the bonding insulating layer 24 interposed therebetween.

[0034] The plurality of void control portions 26 are defined by any one of the plurality of semiconductor chips CP and the bonding insulating layer 24, and include any cavities closed by any one of the plurality of semiconductor chips CP and the bonding insulating layer 24. As one embodiment, as shown in FIG. 1 , the plurality of void control portions 26 include any cavities defined by the upper semiconductor chip 14 and the bonding insulating layer 24, and closed by the upper semiconductor chip 14 and the bonding insulating layer 24. As another embodiment, the plurality of void control portions 26 include any cavities defined by the lower semiconductor chip 12 and the bonding insulating layer 24, and closed by the lower semiconductor chip 12 and the bonding insulating layer 24.

[0035] In an exemplary embodiment, the plurality of void control portions 26 are interposed between any one of the plurality of semiconductor chips CP and the bonding insulating layer 24. In one embodiment, the plurality of void control portions 26 are interposed between the upper semiconductor chip 14 and the bonding insulating layer 24. In another embodiment, the plurality of void control portions 26 are interposed between the lower semiconductor chip 12 and the bonding insulating layer 24.

[0036] The vertical height of the multiple void control portions 26 in the vertical direction (Z direction) is not limited to half the height of the bonding insulating layer 24 in the vertical direction (Z direction) as shown in the figure, and may have various heights. For example, the vertical height of the multiple void control portions 26 in the vertical direction (Z direction) is smaller than half the height of the bonding insulating layer 24 in the vertical direction (Z direction).

[0037] 2, the void control portions 26 have a line shape extending in one direction, a line shape extending in another direction intersecting the one direction, and a cross shape. For example, the void control portions 26 include a line shape extending in a first horizontal direction (X direction), a line shape extending in a second horizontal direction (Y direction), and a cross shape extending in both the first horizontal direction (X direction) and the second horizontal direction (Y direction). However, this is merely an example, and the void control portions 26 may have various shapes. Other various shapes of the void control portions 26 will be described later in the description of FIGS. 3A, 3B, 3C, 3D, and 3E.

[0038] Furthermore, the multiple void control parts 26 have three shapes, namely, a line shape extending in one direction, a line shape extending in the other direction, and a cross shape, as shown in the figure, but this is merely an example, and the multiple void control parts 26 may have one shape or two or more shapes. For example, the multiple void control parts 26 all have a line shape extending in one direction.

[0039] In this specification, among the plurality of void control units 26, the void control unit 26 facing the vertex of the chip edge CP_E is referred to as a vertex void control unit 26VT. In one embodiment, the vertex void control unit 26VT has a different shape from the other plurality of void control units 26, while in another embodiment, the vertex void control unit 26VT has the same shape as the other plurality of void control units 26.

[0040] The plurality of void control portions 26 extend in a first horizontal direction (X direction) and a second horizontal direction (Y direction), and the horizontal lengths of the plurality of void control portions 26 in the first horizontal direction (X direction) and the second horizontal direction (Y direction) are not limited to those shown in the figure. The plurality of void control portions 26 may overlap with a plurality of rows and columns of the plurality of bonding pads 22 in the first horizontal direction (X direction) and the second horizontal direction (Y direction), respectively. For example, the plurality of void control portions 26 overlap with two rows and two columns of the plurality of bonding pads 22 in the first horizontal direction (X direction) and the second horizontal direction (Y direction), respectively.

[0041] The plurality of void control portions 26 are arranged adjacent to chip edges CP_E of the plurality of semiconductor chips CP. In the exemplary embodiment, one end of each of the plurality of void control portions 26 faces the chip edge CP_E and is spaced apart from the chip edge CP_E with a part of the bonding insulating layer 24 interposed therebetween.

[0042] The void control units 26 function to control bonding defects or voids that may occur during the process of bonding the semiconductor chips CP together. Although it is inevitable that bonding defects or voids will be formed during bonding of the semiconductor chips CP due to the surface roughness of the semiconductor chips CP, the positions at which the bonding defects or voids are formed can be controlled using the void control units 26, thereby reducing or preventing the formation of bonding defects or voids at positions other than the positions at which the void control units 26 are formed.

[0043] FIG. 3A is a schematic plan view illustrating a second example of a bonding structure 10a according to an embodiment of the present invention.

[0044] Referring to Figure 3A, the bonding structure 10a is substantially identical to the bonding structure 10 described in Figures 1 and 2, except that it includes multiple void control portions 26a instead of multiple void control portions 26. Therefore, the following description will focus on the differences from the bonding structure 10.

[0045] The multiple void control parts 26a have a line shape extending in a first horizontal direction (X direction), a line shape extending in a second horizontal direction (Y direction), and a line shape extending in a diagonal direction between the first horizontal direction (X direction) and the second horizontal direction (Y direction).

[0046] In one embodiment, among the plurality of void control parts 26, the void control part corresponding to the vertex void control part (26VT in FIG. 2) in FIG. 2 has a linear shape extending in the diagonal direction.

[0047] FIG. 3B is a schematic plan view illustrating a third example of a bonding structure 10b according to an embodiment of the present invention.

[0048] Referring to Figure 3B, the bonding structure 10b is substantially identical to the bonding structure 10 described in Figures 1 and 2, but includes multiple void control portions 26b instead of multiple void control portions 26, so the following description will focus on the differences from the bonding structure 10.

[0049] In an exemplary embodiment, a portion of the bonding insulating layer 24 and the void control portion 26b are interposed between selected bonding pads 22 from among the plurality of bonding pads 22. Meanwhile, only a portion of the bonding insulating layer 24 is interposed between the remaining bonding pads 22 from among the plurality of bonding pads 22, and the void control portion 26b is omitted. In one embodiment, only a portion of the bonding insulating layer 24 is interposed between the bonding pads 22 facing the chip edge CP_E from among the plurality of bonding pads 22, and the void control portion 26b is omitted. For example, as shown in FIG. 3B , only a portion of the bonding insulating layer 24 is interposed between the bonding pads 22 facing the vertex of the chip edge CP_E, and the void control portion 26b is omitted.

[0050] FIG. 3C is a schematic plan view illustrating a fourth example of a bonding structure 10c according to an embodiment of the present invention.

[0051] Referring to Figure 3C, the bonding structure 10c is substantially identical to the bonding structure 10 described in Figures 1 and 2, but includes multiple void control portions 26c instead of multiple void control portions 26, so the following description will focus on the differences from the bonding structure 10.

[0052] As described above in the explanation of Figures 1 and 2, the multiple void control parts 26c extend in the first horizontal direction (X direction) and the second horizontal direction (Y direction), but the horizontal lengths of the multiple void control parts 26c extending in the first horizontal direction (X direction) and the second horizontal direction (Y direction) are not limited to those shown in the figures.

[0053] In the exemplary embodiment, the plurality of void control portions 26c overlap one row and one column of bonding pads 22 in the first horizontal direction (X direction) and the second horizontal direction (Y direction), respectively. For example, the plurality of void control portions 26c overlap one row and one column of bonding pads 22 in the first horizontal direction (X direction) and the second horizontal direction (Y direction), respectively. In some other embodiments, not shown, the plurality of void control portions 26c overlap two rows and two columns of bonding pads 22 in the first horizontal direction (X direction) and the second horizontal direction (Y direction), respectively.

[0054] The plurality of bonding pads 22 include a plurality of outer bonding pads 22E facing the chip edge CP_E, and a plurality of inner bonding pads 22C spaced apart from the chip edge CP_E with the plurality of outer bonding pads 22E interposed therebetween.

[0055] The plurality of void control portions 26c include a plurality of outer void control portions 260. The plurality of outer void control portions 260 are interposed between the chip edge CP_E and a plurality of outer bonding pads 22E facing the chip edge CP_E. Each outer void control portion 260 is separated from an adjacent outer bonding pad 22E by a portion of the bonding insulating layer 24. In one embodiment, the plurality of outer void control portions 260 are arranged adjacent to the vertices of the chip edge CP_E, but this is merely an example, and the plurality of outer void control portions 260 are not limited to being arranged at positions adjacent to the vertices of the chip edge CP_E. For example, the plurality of outer void control portions 260 are arranged spaced apart along each side of the chip edge CP_E.

[0056] FIG. 3D is a schematic plan view illustrating a fifth example of a bonding structure 10d according to an embodiment of the present invention.

[0057] Referring to Figure 3D, the bonding structure 10d is substantially identical to the bonding structure 10 described in Figures 1 and 2, but differs in that it includes multiple void control portions 26d instead of multiple void control portions 26. Therefore, the following description will focus on the differences from the bonding structure 10.

[0058] As described above in the explanation of Figures 1 and 2, the multiple void control units 26d extend in the first horizontal direction (X direction) and the second horizontal direction (Y direction), and the horizontal lengths of the multiple void control units 26d extending in the first horizontal direction (X direction) and the second horizontal direction (Y direction) are not limited to those shown in the figures.

[0059] In the exemplary embodiment, the plurality of void control portions 26d overlap one row and one column of bonding pads 22 in the first horizontal direction (X direction) and the second horizontal direction (Y direction), respectively. For example, the plurality of void control portions 26d overlap one row and one column of bonding pads 22 in the first horizontal direction (X direction) and the second horizontal direction (Y direction), respectively.

[0060] The plurality of bonding pads 22 include a plurality of outer bonding pads 22E facing the chip edge CP_E, and a plurality of inner bonding pads 22C spaced apart from the chip edge CP_E with the plurality of outer bonding pads 22E interposed therebetween.

[0061] The plurality of void control units 26d includes a plurality of inner void control units 261. The plurality of inner void control units 261 are interposed between the plurality of outer bonding pads 22E and the plurality of inner bonding pads 22C adjacent thereto, and between the plurality of inner bonding pads 22C. The inner void control units 261 are separated from the plurality of bonding pads 22A by a portion of the bonding insulating layer 24. In some cases, bonding defects or voids may occur in the central region of the semiconductor chip CP, rather than in the edge region adjacent to the chip edge CP_E of the semiconductor chip CP. In such cases, the plurality of inner void control units 261 serve to control the bonding defects or voids occurring in the central region of the semiconductor chip CP.

[0062] The plurality of void control units 26 include a plurality of outer void control units 260. The plurality of outer void control units 260 are interposed between the chip edge CP_E and a plurality of outer bonding pads 22E facing the chip edge CP_E. Each outer void control unit 260 is separated from an adjacent outer bonding pad 22E by a portion of the bonding insulating layer 24. In one embodiment, the plurality of outer void control units 260 are arranged adjacent to the vertices of the chip edge CP_E, but this is merely an example, and the plurality of outer void control units 260 are not limited to being arranged at positions adjacent to the vertices of the chip edge CP_E. For example, the plurality of outer void control units 260 are arranged spaced apart along each side of the chip edge CP_E.

[0063] FIG. 4 is a schematic cross-sectional view illustrating a bonding structure 20 according to another embodiment of the present invention.

[0064] Referring to Figure 4, compared to the bonding structure 10 described in Figures 1 and 2, the bonding structure 20 includes multiple void control portions 26_2, unlike the bonding structure 10 which includes multiple void control portions 26.Therefore, the following description will focus on the differences from the bonding structure 10.

[0065] The plurality of void control portions 26_2 are interposed between pairs of adjacent bonding pads 22 among the plurality of bonding pads 22. The void control portions 26_2 are separated from the plurality of bonding pads 22 with a part of the bonding insulating layer 24 interposed therebetween.

[0066] In the exemplary embodiment, the plurality of void control portions 26_2 are defined by the bonding insulating layer 24 and two semiconductor chips CP spaced apart with the bonding insulating layer 24 sandwiched therebetween. The plurality of void control portions 26_2 include any cavities enclosed by the bonding insulating layer 24 and the two semiconductor chips CP spaced apart with the bonding insulating layer 24 sandwiched therebetween. As one embodiment, as shown in FIG. 4 , the plurality of void control portions 26_2 are defined by the bonding insulating layer 24, the lower semiconductor chip 12, and the upper semiconductor chip 14. The plurality of void control portions 26_2 include any cavities enclosed by the bonding insulating layer 24, the lower semiconductor chip 12, and the upper semiconductor chip 14. In the exemplary embodiment, the vertical height of the plurality of void control portions 26_2 in the vertical direction (Z direction) is substantially the same as the vertical height of the bonding insulating layer 24 in the vertical direction (Z direction).

[0067] FIG. 5 is a schematic cross-sectional view illustrating a bonding structure 30 according to yet another embodiment of the present invention.

[0068] Referring to Figure 5, compared to the bonding structure 10 described in Figures 1 and 2, the bonding structure 30 includes multiple void control portions 26_3, whereas the bonding structure 10 includes multiple void control portions 26. Therefore, the following description will focus on the differences from the bonding structure 10.

[0069] The plurality of void control portions 26_3 are interposed between pairs of adjacent bonding pads 22 among the plurality of bonding pads 22. The void control portions 26_3 are separated from the plurality of bonding pads 22 with a part of the bonding insulating layer 24 interposed therebetween.

[0070] In the exemplary embodiment, the plurality of void control portions 26_3 include any cavity that is completely surrounded and closed by the bonding insulating layer 24. As one embodiment, as shown in FIG. 5 , the plurality of void control portions 26_3 are separated from the lower semiconductor chip 12 by a portion of the bonding insulating layer 24, and are separated from the upper semiconductor chip 14 by a portion of the bonding insulating layer 24. In the exemplary embodiment, the vertical height of the plurality of void control portions 26_3 in the vertical direction (Z direction) is smaller than the vertical height of the bonding insulating layer 24 in the vertical direction (Z direction).

[0071] FIG. 6 is a cross-sectional view illustrating a semiconductor package 100 according to an embodiment of the present invention.

[0072] 6, the semiconductor package 100 includes a first semiconductor chip CP1 and a plurality of second semiconductor chips CP2. While the semiconductor package 100 is illustrated in FIG. 6 as including four second semiconductor chips CP2, this is not limiting. For example, the semiconductor package 100 includes two or more second semiconductor chips CP2. In an exemplary embodiment, the semiconductor package 100 includes a number of second semiconductor chips CP2 that is a multiple of four.

[0073] 6, a second semiconductor chip CP22 is stacked on the first semiconductor chip CP1, another second semiconductor chip CP24 is stacked on the second semiconductor chip CP22, another second semiconductor chip CP26 is stacked on the second semiconductor chip CP24, and another second semiconductor chip CP28 is stacked on the second semiconductor chip CP26. For convenience of explanation, the second semiconductor chip CP22 located at the bottom of the second semiconductor chips CP2 and above the first semiconductor chip CP1 is defined as the bottom second semiconductor chip CP22, and the second semiconductor chip CP28 located at the top is defined as the top second semiconductor chip CP28.

[0074] The first semiconductor chip CP1 includes a first semiconductor substrate 110 having an active surface and a non-active surface opposite to each other, a first discrete element disposed on the active surface of the first semiconductor substrate 110, a first wiring structure 120 disposed on the active surface of the first semiconductor substrate 110, and a plurality of first through electrodes 130 connected to the first wiring structure 120 and passing through the first semiconductor substrate 110. The first wiring structure 120 includes a first wiring layer 122, a first wiring pattern 124, and a first wiring via 126.

[0075] The first semiconductor chip CP1 further includes a plurality of chip pads 140 disposed on the underside of the first semiconductor chip CP1 and electrically connected to the first wiring structure 120. The plurality of chip pads 140 are electrically connected to the first wiring patterns 124 and the first wiring vias 126, and are electrically connected to the first individual elements through the first wiring patterns 124 and the first wiring vias 126.

[0076] In the semiconductor package 100, the first semiconductor chip CP1 is disposed such that the active surface of the first semiconductor substrate 110 faces the bottom and the non-active surface faces the top.

[0077] The second semiconductor chip CP2 includes a second semiconductor substrate 210 having an active surface and a non-active surface opposite to each other, second discrete elements disposed on the active surface of the second semiconductor substrate 210, a second wiring structure 220 disposed on the active surface of the second semiconductor substrate 210, and a plurality of second through-electrodes 230 connected to the second wiring structure 220 and penetrating the second semiconductor substrate 210. The second wiring structure 220 includes a second wiring layer 222, a second wiring pattern 224, and second wiring vias 226.

[0078] The second semiconductor chip CP2 is disposed in the semiconductor package 100 with the active surface of the second semiconductor substrate 210 facing the bottom and the non-active surface facing the top. That is, the second semiconductor chip CP2 is disposed with the active surface of the second semiconductor substrate 210 facing the non-active surface of the first semiconductor chip CP1.

[0079] The first semiconductor substrate 110 and the second semiconductor substrate 210 may include a semiconductor material such as silicon (Si). Alternatively, the first semiconductor substrate 110 and the second semiconductor substrate 210 may include a semiconductor material such as germanium (Ge). The first semiconductor substrate 110 and the second semiconductor substrate 210 may include a conductive region, for example, a well doped with impurities. The first semiconductor substrate 110 and the second semiconductor substrate 210 may have various isolation structures such as a shallow trench isolation (STI) structure.

[0080] Each of the first and second discrete elements includes a variety of types of individual devices, including various microelectronic devices, such as metal-oxide-semiconductor field effect transistors (MOSFETs) such as complementary metal-oxide-semiconductor transistors (CMOS transistors), large scale integration (system LSIs), image sensors such as CMOS imaging sensors (CISs), micro-electro-mechanical systems (MEMSs), active elements, and passive elements.

[0081] Each of the first and second individual elements further includes conductive wiring or conductive plugs that electrically connect the individual elements included in the first or second individual element to conductive regions of the first or second semiconductor substrate 110 or 210. The individual elements are electrically isolated from adjacent individual elements by insulating films.

[0082] The first semiconductor chip CP1 or the second semiconductor chip CP2 is a memory semiconductor chip. In an exemplary embodiment, the first semiconductor chip CP1 includes a serial-parallel conversion circuit and is a buffer chip for controlling the second semiconductor chips CP2. The second semiconductor chips CP2 are memory chips including memory cells. For example, the semiconductor package 100 including the first semiconductor chip CP1 and the second semiconductor chips CP2 is a High Bandwidth Memory (HBM), the first semiconductor chip CP1 is referred to as an HBM controller die, and each of the second semiconductor chips CP2 is referred to as a DRAM die.

[0083] The first wiring structure 120 includes a first wiring layer 122, a plurality of first wiring patterns 124 surrounded by the first wiring layer 122, and a plurality of first wiring vias 126 electrically connected to the plurality of first wiring patterns 124. In an exemplary embodiment, the plurality of first wiring patterns 124 and the plurality of first wiring vias 126 are located at different vertical levels, and the first wiring structure 120 forms a multi-layer wiring structure.

[0084] The second wiring structure 220 includes a second wiring layer 222, a plurality of second wiring patterns 224 surrounded by the second wiring layer 222, and a plurality of second wiring vias 226 electrically connected to the plurality of second wiring patterns 224. In an exemplary embodiment, the plurality of second wiring patterns 224 and the plurality of second wiring vias 226 are located at different vertical levels, and the second wiring structure 220 forms a multi-layer wiring structure.

[0085] When first wiring structure 120 and second wiring structure 220 have a multilayer wiring structure, first wiring layer 122 and second wiring layer 222 have a multilayer structure in which a plurality of insulating layers are stacked in accordance with the multilayer wiring structure.

[0086] In an exemplary embodiment, the first wiring layer 122 and the second wiring layer 222 include an insulating material. For example, the first wiring layer 122 and the second wiring layer 222 are made of silicon oxide, silicon nitride, silicon oxynitride, an insulating material with a lower dielectric constant than silicon oxide, or a combination thereof. In an exemplary embodiment, the first wiring layer 122 and the second wiring layer 222 are made of a tetraethyl orthosilicate (TEOS) film or an ultralow K (ULK) film having an ultralow dielectric constant K of approximately 2.2 to 2.4. The ULK film includes a SiOC film or a SiCOH film.

[0087] In an exemplary embodiment, the first wiring pattern 124, the first wiring via 126, the second wiring pattern 224, and the second wiring via 226 include a conductive material. For example, the first wiring pattern 124, the first wiring via 126, the second wiring pattern 224, and the second wiring via 226 include aluminum, copper, or tungsten. In an exemplary embodiment, the first wiring pattern 124, the first wiring via 126, the second wiring pattern 224, and the second wiring via 226 include a wiring barrier film and a wiring metal layer. The wiring barrier film includes a metal, a metal nitride, or an alloy. The wiring metal layer includes at least one metal selected from W, Al, Ti, Ta, Ru, Mn, and Cu.

[0088] In an exemplary embodiment, each of the first through electrode 130 and the second through electrode 230 is formed as a through silicon via (TSV). Each of the first through electrode 130 and the second through electrode 230 includes a conductive plug penetrating the first semiconductor substrate 110 and the second semiconductor substrate 210, respectively, and a conductive barrier film surrounding the conductive plug. The conductive plug has a cylindrical shape, and the conductive barrier film has a cylindrical shape surrounding the sidewall of the conductive plug. Via insulating films are interposed between the first through electrode 130 and the first semiconductor substrate 110 and between the second through electrode 230 and the second semiconductor substrate 210, surrounding the sidewalls of the first through electrode 130 and the second through electrode 230. The first through electrode 130 and the second through electrode 230 are formed in any one of a via-first, via-middle, or via-last structure.

[0089] The first semiconductor chip CP1 and the second semiconductor chips CP2 are electrically connected to each other via a plurality of bonding pads 310 to transmit and receive signals and to receive power and ground. The bonding pads 310 are interposed between the first semiconductor chip CP1 and the bottom second semiconductor chip CP22 and between adjacent second semiconductor chips CP2. The bonding insulating layer 320 is interposed between the first semiconductor chip CP1 and the bottom second semiconductor chip CP22 and between adjacent second semiconductor chips CP2, and is disposed to surround the bonding pads 310. The bonding insulating layer 320 surrounds the bonding pads 310 in a planar manner.

[0090] The plurality of bonding pads 310 are respectively interposed between the first through-hole electrode 130 and the second wiring pattern 224 and second wiring via 226 of the second wiring structure 220, and between the second through-hole electrode 230 and the second wiring pattern 224 and second wiring via 226 of the second wiring structure 220. The plurality of bonding pads 310 electrically connect the second wiring pattern 224 and second wiring via 226 of the second wiring structure 220 to the first through-hole electrode 130 or the second through-hole electrode 230. That is, the plurality of bonding pads 310 electrically connect the plurality of first through-hole electrodes 130 of the first semiconductor chip CP1 to the plurality of second through-hole electrodes 230 of each of the plurality of second semiconductor chips CP2.

[0091] In an exemplary embodiment, the plurality of bonding pads 310 are formed by forming conductive material layers on the surfaces of two adjacent chips among the first semiconductor chip CP1 and the plurality of second semiconductor chips CP2 that face each other, expanding the conductive material layers by heat to contact each other, and diffusing metal atoms in the conductive material layers to integrate the conductive material layers. A method for forming the plurality of bonding pads 310 will be described in detail in the description of the manufacturing process.

[0092] In an exemplary embodiment, the bonding insulating layer 320 is formed by forming an insulating material layer on each of the surfaces of two adjacent chips among the first semiconductor chip CP1 and the plurality of second semiconductor chips CP2 that face each other, expanding the insulating material layers by heat so that they contact each other, and diffusing atoms in the insulating material layers to form an integrated structure. A method for forming the bonding insulating layer 320 will be described in detail in the description of the manufacturing process.

[0093] Among the plurality of bonding insulating layers 320, the bonding insulating layer 320 interposed between the first semiconductor chip CP1 and the bottommost second semiconductor chip CP22 is referred to as a bottommost bonding insulating layer 320L.

[0094] The bottom bonding insulating layer 320L includes a portion that overlaps the bottom second semiconductor chip CP22 in the vertical direction (Z direction) and a portion that does not overlap the bottom second semiconductor chip CP22 in the vertical direction (Z direction).

[0095] The height in the vertical direction (Z direction) of the portion of the lowest bonding insulating layer 320L that overlaps the lowest second semiconductor chip CP22 is greater than the height in the vertical direction (Z direction) of the portion of the lowest bonding insulating layer 320L that does not overlap the lowest second semiconductor chip CP22. That is, the lowest bonding insulating layer 320L includes a recess 320R in the portion of the lowest bonding insulating layer 320L that does not overlap the lowest second semiconductor chip CP22. Due to the recess 320R, the portion of the upper surface of the lowest bonding insulating layer 320L that overlaps the lowest second semiconductor chip CP22 protrudes upward compared to the portion that does not overlap the lowest second semiconductor chip CP22.

[0096] The bottommost bonding insulating layer 320L covers a portion of the top surface of the first semiconductor chip CP1 that does not overlap with the bottommost second semiconductor chip CP22. The bottommost bonding insulating layer 320L covers a portion of the top surface of the first semiconductor chip CP1 that overlaps with the bottommost second semiconductor chip CP22 but is not covered by the bonding pads 310.

[0097] Of the multiple bonding insulating layers 320, the remaining bonding insulating layers 320 other than the lowest bonding insulating layer 320L cover the portions of the upper and lower surfaces of the second semiconductor chip CP2 that are not covered by the multiple bonding pads 310.

[0098] A plurality of first void control units 330 are interposed between the first semiconductor chip CP1 and the bottommost second semiconductor chip CP22 and between a plurality of adjacent second semiconductor chips CP2. The plurality of first void control units 330 correspond to the plurality of void control units (26, 26a, 26b, 26c, 26d, 26_2, 26_3) described in Figures 1, 2, 3A, 3B, 3C, 3D, 4, and 5. The plurality of first void control units 330 were described in detail in the description of the plurality of void control units (26, 26a, 26b, 26c, 26d, 26_2, 26_3) in Figures 1, 2, 3A, 3B, 3C, 3D, 4, and 5, and will therefore be described briefly below.

[0099] The plurality of first void control portions 330 are interposed between pairs of adjacent bonding pads 310 among the plurality of bonding pads 310. Each of the plurality of first void control portions 330 is separated from the adjacent bonding pad 310 with a part of the bonding insulating layer 320 sandwiched therebetween.

[0100] The multiple first void control portions 330 are defined by the bonding insulating layer 320, the first semiconductor chip CP1, and at least one second semiconductor chip CP2, and include any cavity closed by the bonding insulating layer 320, the first semiconductor chip CP1, and at least one second semiconductor chip CP2.

[0101] In one embodiment, the plurality of first void control portions 330 include any cavities closed by the bonding insulating layer 320. In another embodiment, the plurality of first void control portions 330 include cavities closed by the bonding insulating layer 320 and the first semiconductor chip CP1. For example, the plurality of first void control portions 330 expose a portion of the bonding insulating layer 320 on the top surface of the first semiconductor chip CP1. Also, the plurality of first void control portions 330 include any cavities closed by the bonding insulating layer 320 and the second semiconductor chip CP2. For example, the plurality of first void control portions 330 expose a portion of the bonding insulating layer 320 on the top surface of the second semiconductor chip CP2 or a portion of the bottom surface of the second semiconductor chip CP2.

[0102] In yet another embodiment, the plurality of first void control portions 330 include cavities enclosed by the bonding insulating layer 320, the first semiconductor chip CP1, and the bottommost second semiconductor chip CP22, and cavities enclosed by the bonding insulating layer 320 and the plurality of second semiconductor chips CP2. For example, the plurality of first void control portions 330 penetrate the bonding insulating layer 320 in the vertical direction (Z direction) to expose a portion of the top surface of the first semiconductor chip CP1 and a portion of the bottom surface of the bottommost second semiconductor chip CP22. The plurality of first void control portions 330 penetrate the bonding insulating layer 320 in the vertical direction (Z direction) to expose a portion of the top and bottom surfaces of the plurality of second semiconductor chips CP2.

[0103] A dummy support substrate 400 is disposed on the uppermost second semiconductor chip CP28. The dummy support substrate 400 includes a semiconductor material such as silicon (Si). In an exemplary embodiment, the dummy support substrate 400 is made of only a semiconductor material. For example, the dummy support substrate 400 is a portion of a bare wafer.

[0104] In an exemplary embodiment, the horizontal width of the first semiconductor chip CP1 in the first horizontal direction (X direction) is the same as or larger than the horizontal width of the second semiconductor chip CP2 in the first horizontal direction (X direction). For example, the horizontal width of the first semiconductor chip CP1 is approximately 11 mm, and the horizontal width of the second semiconductor chip CP2 is approximately 10 mm. In an exemplary embodiment, the horizontal width of the second semiconductor chip CP2 in the first horizontal direction (X direction) is the same as or larger than the horizontal width of the dummy support substrate 400 in the first horizontal direction (X direction). For example, the horizontal width of the second semiconductor chip CP2 is approximately 10 mm, and the horizontal width of the dummy support substrate 400 is approximately 9 mm.

[0105] In an exemplary embodiment, the vertical height (e.g., thickness) of the first semiconductor chip CP1 in the vertical direction (Z direction) is the same as or greater than the vertical height of the second semiconductor chip CP2 in the vertical direction (Z direction). For example, the vertical height of the first semiconductor chip CP1 is approximately 60 mm, and the vertical height of the second semiconductor chip CP2 is approximately 40 mm. In an exemplary embodiment, the vertical height of the first semiconductor chip CP1 in the vertical direction (Z direction) is smaller than the vertical height of the dummy support substrate 400 in the vertical direction (Z direction). For example, the vertical height of the first semiconductor chip CP1 is approximately 60 mm, and the vertical height of the dummy support substrate 400 is approximately 200 mm.

[0106] A plurality of support bonding pads 340 and a support bonding insulating layer 350 are interposed between the uppermost second semiconductor chip CP28 and the dummy support substrate 400. The plurality of support bonding pads 340 are surrounded in a planar manner by the support bonding insulating layer 350. The support bonding insulating layer 350 is disposed between the uppermost second semiconductor chip CP28 and the dummy support substrate 400 so as to surround the plurality of support bonding pads 340. The support bonding insulating layer 350 covers portions of the upper surface of the uppermost second semiconductor chip CP28 and the lower surface of the dummy support substrate 400 that are not covered by the plurality of support bonding pads 340.

[0107] In an exemplary embodiment, the plurality of support bonding pads 340 are formed by forming conductive material layers on the upper surface of the uppermost second semiconductor chip CP28 and the lower surface of the dummy support substrate 400, which face each other, and then expanding the conductive material layers by heat to contact each other and diffusing metal atoms in the conductive material layers to integrate the conductive material layers. A method for forming the plurality of support bonding pads 340 will be described in detail in the description of the manufacturing process.

[0108] In an exemplary embodiment, the support bonding insulating layer 350 is formed by forming an insulating material layer on each of the upper surface of the uppermost second semiconductor chip CP28 and the lower surface of the dummy support substrate 400, which face each other, and then expanding the insulating material layers by heat to contact each other and diffusing atoms in the insulating material layers to form an integrated structure. A method for forming the support bonding insulating layer 350 will be described in detail in the description of the manufacturing process.

[0109] A plurality of second void control units 360 are interposed between the uppermost second semiconductor chip CP28 and the dummy support substrate 400. Similar to the first void control unit 330, the plurality of second void control units 360 have configurations corresponding to the plurality of void control units (26, 26a, 26b, 26c, 26d, 26_2, 26_3) described in Figures 1, 2, 3A, 3B, 3C, 3D, 4, and 5. The plurality of second void control units 360 have been specifically described in the description of the plurality of void control units (26, 26a, 26b, 26c, 26d, 26_2, 26_3) in Figures 1, 2, 3A, 3B, 3C, 3D, 4, and 5, and will therefore be described briefly below.

[0110] The plurality of second void control portions 360 are interposed between adjacent support bonding pads 340 among the plurality of support bonding pads 340. Each of the plurality of second void control portions 360 is spaced apart from the adjacent support bonding pad 340 with a portion of the support bonding insulating layer 350 sandwiched therebetween.

[0111] The multiple second void control portions 360 are defined by the support bonding insulating layer 350, the top second semiconductor chip CP28, and the dummy support substrate 400, and include any cavities closed by the support bonding insulating layer 350, the top second semiconductor chip CP28, and the dummy support substrate 400.

[0112] In one embodiment, the plurality of second void control portions 360 include any cavities closed by the support bonding insulating layer 350. In another embodiment, the plurality of second void control portions 360 include cavities closed by the support bonding insulating layer 350 and the uppermost second semiconductor chip CP28. For example, the plurality of second void control portions 360 face a portion of the upper surface of the uppermost second semiconductor chip CP28. Furthermore, the plurality of second void control portions 360 include any cavities closed by the bonding insulating layer 320 and the dummy support substrate 400. For example, the plurality of second void control portions 360 face a portion of the lower surface of the dummy support substrate 400.

[0113] In yet another embodiment, the plurality of second void control portions 360 include cavities enclosed by the support bonding insulating layer 350, the uppermost second semiconductor chip CP28, and the dummy support substrate 400. For example, the plurality of second void control portions 360 penetrate the support bonding insulating layer 350 in the vertical direction (Z direction) to expose a portion of the upper surface of the uppermost second semiconductor chip CP28 and a portion of the lower surface of the dummy support substrate 400.

[0114] In an exemplary embodiment, the plurality of bonding pads 310 and the plurality of support bonding pads 340 include a material capable of diffusion bonding, such as Cu, Al, or W. In an exemplary embodiment, the bonding insulation layer 320 and the support bonding insulation layer 350 are made of any one of SiO, SiN, SiCN, SiCO, and a polymer material. The polymer material may be benzocyclobutene (BCB), polyimide (PI), polybenzoxazole (PBO), silicone, acrylate, or epoxy. For example, the bonding insulation layer 320 and the support bonding insulation layer 350 are made of silicon oxide. In an exemplary embodiment, the bonding insulation layer 320 and the support bonding insulation layer 350 are made of the same material. The bonding insulation layer 320 and the support bonding insulation layer 350 have a thickness of, for example, about 100 nm to 1 mm.

[0115] In this specification, the first void control portions 330 and the second void control portions 360 are referred to as a plurality of void control portions. Each of the void control portions has a variety of shapes, such as a slit shape, a groove shape, or a recess shape. Each of the void control portions includes any cavity that can be filled with any substantially inert gas or gaseous substance (including, but not limited to, air).

[0116] The plurality of void control units serves to control bonding defects or voids that occur during a process of bonding the first semiconductor chip CP1 and the bottommost second semiconductor chip CP22 and the plurality of second semiconductor chips CP2 to each other. Although it is inevitable that bonding defects or voids will be formed during bonding between the first semiconductor chip CP1 and the plurality of second semiconductor chips CP2 due to the surface roughness of the first semiconductor chip CP1 and the plurality of second semiconductor chips CP2, the plurality of void control units can control the positions where the bonding defects or voids are formed, thereby reducing or preventing the formation of bonding defects or voids in positions other than the positions where the plurality of void control units are formed.

[0117] The semiconductor package 100 includes a package molding layer 500 that covers a portion of the top surface of the first semiconductor chip CP1 that is not covered by the lowermost second semiconductor chip CP22. The package molding layer 500 surrounds sidewalls of the second semiconductor chips CP2 and a sidewall of the dummy support substrate 400. The package molding layer 500 includes, for example, an epoxy molding compound (EMC).

[0118] Although the package molding layer 500 is shown as not covering the top surface of the dummy support substrate 400 , it is not limited thereto and may extend to cover the top surface of the dummy support substrate 400 .

[0119] In the exemplary embodiment, the semiconductor package 100 further includes a base redistribution layer 610 disposed on the underside of the first semiconductor chip CP1. The base redistribution layer 610 includes a package redistribution insulating layer 612, a plurality of package redistribution vias 614, and a package redistribution line pattern 616.

[0120] In an exemplary embodiment, a plurality of package rewiring insulating layers 612 are stacked, and the package rewiring insulating layers 612 are formed of, for example, a photo imageable dielectric (PID) or a photosensitive polyimide (PSPI).

[0121] The package rewiring vias 614 penetrate the package rewiring insulating layer 612 and are connected to the package rewiring line patterns 616. The package rewiring vias 614 are planarly surrounded by the package rewiring insulating layer 612. In an exemplary embodiment, a plurality of package rewiring line patterns 616 are stacked. Each of the plurality of package rewiring line patterns 616 is disposed on the package rewiring insulating layer 612. In an exemplary embodiment, the plurality of package rewiring vias 614 are formed integrally with the package rewiring line patterns 616.

[0122] The package redistribution vias 614 and the package redistribution line pattern 616 may be made of a metal, such as, but not limited to, copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), or ruthenium (Ru), or an alloy thereof. In some embodiments, the package redistribution vias 614 and the package redistribution line pattern 616 are formed by depositing a metal or metal alloy on a seed layer including titanium, titanium nitride, or titanium tungsten.

[0123] The plurality of package rewiring vias 614 and package rewiring line patterns 616 are electrically coupled to the plurality of chip pads 140. In an exemplary embodiment, at least some of the plurality of rewiring vias 614 contact the plurality of chip pads 140. For example, in the case where a plurality of package rewiring insulating layers 612 are included, the rewiring via 614 penetrating the topmost package rewiring insulating layer 612 contacts the chip pad 140.

[0124] In the illustrative embodiment, the package rewiring vias 614 have a tapered shape that narrows in horizontal width from bottom to top, i.e., the package rewiring vias 614 have a wider horizontal width in the direction away from the first semiconductor chip CP1.

[0125] A package pad 640 is disposed on the lower surface of the base redistribution layer 610. In an exemplary embodiment, the package pad 640 includes the same material as the package redistribution line pad 640. A plurality of package pads 640 are provided, and each of the package pads 640 contacts a plurality of package connecting terminals 650. For example, the package connecting terminals 650 are solder balls or bumps.

[0126] In the exemplary embodiment, the semiconductor package 100 does not include a base redistribution layer 610. For example, the plurality of package connecting terminals 650 are attached to the plurality of chip pads 140.

[0127] 7, 8, 9, 10, and 11 are cross-sectional views showing the steps of a method for manufacturing a semiconductor package according to an embodiment of the present invention.

[0128] 7, the first semiconductor chip CP1 is attached to the first support substrate SS1. After a first release film RF1 is attached to the top surface of the first support substrate SS1, the first semiconductor chip CP1 is attached to the first release film RF1. The first semiconductor chip CP1 is attached to the first release film RF1 so that the first wiring structure 120 faces the first support substrate SS1. The plurality of chip pads 140 exposed on the bottom surface of the first semiconductor substrate 110 are attached to the first release film RF1.

[0129] Thereafter, a plurality of first preliminary bonding pads 310a and a first preliminary bonding insulating layer 320a are formed on the upper surface of the first semiconductor chip CP1. The plurality of first preliminary bonding pads 310a are arranged on the upper surface, i.e., the non-active surface, of the first semiconductor chip CP1. The plurality of first preliminary bonding pads 310a are arranged on the upper surface of the first semiconductor chip CP1 so as to be connected to the plurality of first through-electrodes 130. The first preliminary bonding insulating layer 320a is formed on the upper surface, i.e., the non-active surface, of the first semiconductor chip CP1 to surround side surfaces of the plurality of first preliminary bonding pads 310a. The first preliminary bonding insulating layer 320a covers the upper surface of the first semiconductor chip CP1 and the side surfaces of the plurality of first preliminary bonding pads 310a, but does not cover the upper surfaces of the plurality of first preliminary bonding pads 310a, leaving them exposed.

[0130] Specifically, to form the first preliminary bonding insulating layer 320a, an insulating film covering the upper surface of the first semiconductor chip CP1 is formed on the upper surface of the first semiconductor chip CP1, and then a plurality of local regions are removed from the upper surface of the insulating film to form a plurality of first preliminary bonding pads 310a in the plurality of local regions.

[0131] In an exemplary embodiment, although not shown, after forming the plurality of first preliminary bonding pads 310a, a plurality of local regions are removed from the upper surface of the insulating film to form a plurality of first void control portions 330 in the plurality of local regions. In one embodiment, the upper surface of the first semiconductor chip CP1 is exposed by removing the plurality of local regions from the upper surface of the insulating film. For example, the upper surface of the first semiconductor chip CP1 is exposed from the plurality of first void control portions 330. In another embodiment, even when the plurality of local regions are removed from the upper surface of the insulating film, the upper surface of the first semiconductor chip CP1 is not exposed, and a portion of the insulating film remains on the upper surface of the first semiconductor chip CP1. For example, the upper surface of the first semiconductor chip CP1 is not exposed from the plurality of first void control portions 330, and the first preliminary bonding insulating layer 320a is exposed.

[0132] The first void control portions 330 are formed between the first preliminary bonding pads 310a and are spaced apart from the first preliminary bonding pads 310a with portions of the first preliminary bonding insulating layers 320a interposed therebetween.

[0133] 8, a plurality of second preliminary bonding pads 310b and a second preliminary bonding insulating layer 320b are formed on the lower surface of the lowest second semiconductor chip CP22. The plurality of second preliminary bonding pads 310b are arranged on the lower surface of the lowest second semiconductor chip CP22, i.e., the lower surface of the second wiring structure 220. The plurality of second preliminary bonding pads 310b are arranged on the lower surface of the lowest second semiconductor chip CP22 to be connected to the second wiring pattern 224 and the second wiring vias 226. The second preliminary bonding insulating layer 320b is formed on the lower surface of the lowest second semiconductor chip CP22 to surround side surfaces of the plurality of second preliminary bonding pads 310b. The second preliminary bonding insulating layer 320b covers the lower surface of the lowest second semiconductor chip CP22 and the side surfaces of the plurality of second preliminary bonding pads 310b, but exposes the lower surfaces of the plurality of second preliminary bonding pads 310b.

[0134] Specifically, an insulating film covering the lower surface of the lowermost second semiconductor chip CP22 is formed on the lower surface of the lowermost second semiconductor chip CP22 to form the second preliminary bonding insulating layer 320b, and then a plurality of local regions are removed from the lower surface of the insulating film to form a plurality of second preliminary bonding pads 310b in the plurality of local regions.

[0135] In an exemplary embodiment, after forming the plurality of second preliminary bonding pads 310b, a plurality of local regions are removed from the lower surface of the insulating film to form a plurality of first void control portions 330 in the plurality of local regions. In one embodiment, the lower surface of the bottommost second semiconductor chip CP22 is exposed by removing the plurality of local regions from the lower surface of the insulating film. For example, the lower surface of the bottommost second semiconductor chip CP22 is exposed through the plurality of first void control portions 330. In another embodiment, even when the plurality of local regions are removed from the lower surface of the insulating film, the lower surface of the bottommost second semiconductor chip CP22 is not exposed, and a portion of the insulating film remains on the lower surface of the bottommost second semiconductor chip CP22. For example, the lower surface of the bottommost second semiconductor chip CP22 is not exposed through the plurality of first void control portions 330, and a portion of the second preliminary bonding insulating layer 320b is exposed.

[0136] The first void control portions 330 are formed between the second preliminary bonding pads 310b and are spaced apart from the second preliminary bonding pads 310b with a portion of the second preliminary bonding insulating layer 320b interposed therebetween.

[0137] 4, a plurality of local regions are removed from the upper surface of the insulating film covering the upper surface of the first semiconductor chip CP1 to form the first preliminary bonding insulating layer 320a, and a plurality of local regions are removed from the lower surface of the insulating film covering the lower surface of the bottommost second semiconductor chip CP22 to form the second preliminary bonding insulating layer 320b, thereby forming a plurality of first void control portions 330 in the plurality of local regions. In one embodiment, the upper surface of the first semiconductor chip CP1 and the lower surface of the bottommost second semiconductor chip CP22 are exposed by removing the plurality of local regions. For example, the upper surface of the first semiconductor chip CP1 and the lower surface of the bottommost second semiconductor chip CP22 are exposed through the plurality of first void control portions 330.

[0138] The plurality of first void control portions 330 are formed between the plurality of first preliminary bonding pads 310a and the plurality of second preliminary bonding pads 310b, and are spaced apart from the plurality of first preliminary bonding pads 310a and the plurality of second preliminary bonding pads 310b by a portion of the first preliminary bonding insulating layer 320a and a portion of the second preliminary bonding insulating layer 320b.

[0139] In yet another exemplary embodiment, to form a void control portion corresponding to the void control portion 26_3 of FIG. 5 , a plurality of local regions are removed from the upper surface of the insulating film covering the upper surface of the first semiconductor chip CP1 to form the first preliminary bonding insulating layer 320a, and a plurality of local regions are removed from the lower surface of the insulating film covering the lower surface of the bottommost second semiconductor chip CP22 to form the second preliminary bonding insulating layer 320b, as described above, to form a plurality of first void control portions 330 in the plurality of local regions. In one embodiment, even after the plurality of local regions are removed, the upper surface of the first semiconductor chip CP1 and the lower surface of the bottommost second semiconductor chip CP22 are not exposed, and portions of the insulating film remain on the upper surface of the first semiconductor chip CP1 and the lower surface of the bottommost second semiconductor chip CP22. For example, the upper surface of the first semiconductor chip CP1 and the lower surface of the bottommost second semiconductor chip CP22 are not exposed through the plurality of first void control portions 330, and portions of the first preliminary bonding insulating layer 320a and the second preliminary bonding insulating layer 320b are exposed.

[0140] The plurality of first void control portions 330 are formed between the plurality of first preliminary bonding pads 310a and the plurality of second preliminary bonding pads 310b, and are spaced apart from the plurality of first preliminary bonding pads 310a and the plurality of second preliminary bonding pads 310b by a portion of the first preliminary bonding insulating layer 320a and a portion of the second preliminary bonding insulating layer 320b.

[0141] Then, the bottom second semiconductor chip CP22 is aligned on the first semiconductor chip CP1 so that the plurality of first preliminary bonding pads 310a and the plurality of second preliminary bonding pads 310b face each other, and the first semiconductor chip CP1 and the bottom second semiconductor chip CP22 are bonded to each other. In an exemplary embodiment, the plurality of first preliminary bonding pads 310a and the plurality of second preliminary bonding pads 310b, and the first preliminary bonding insulating layer 320a and the second preliminary bonding insulating layer 320b are bonded to each other by heat, pressure, or a combination thereof.

[0142] In an exemplary embodiment, the bottom second semiconductor chip CP22 is positioned on the first semiconductor chip CP1, and heat is applied at a first temperature, followed by heat at a second temperature higher than the first temperature to form a plurality of bonding pads 310 in which a plurality of corresponding first preliminary bonding pads 310a and a plurality of corresponding second preliminary bonding pads 310b are coupled together, and a bonding insulation layer 320 in which a first preliminary bonding insulation layer 320a and a second preliminary bonding insulation layer 320b are coupled together.

[0143] The corresponding first preliminary bonding pads 310a and second preliminary bonding pads 310b are thermally expanded to contact each other, and then the first preliminary bonding pads 310a and the second preliminary bonding pads 310b are diffusion bonded to each other through the diffusion of metal atoms to form a plurality of bonding pads 310. Similarly, the first preliminary bonding insulating layer 320a and the second preliminary bonding insulating layer 320b are thermally expanded to contact each other, and then the first preliminary bonding pads 310a and the second preliminary bonding insulating layer 320b are diffusion bonded to each other through the diffusion of atoms to form a bonding insulating layer 320. In an exemplary embodiment, the first preliminary bonding pads 310a and the second preliminary bonding pads 310b and the first preliminary bonding insulating layer 320a and the second preliminary bonding insulating layer 320b are bonded to each other through covalent bonds. As a result, the bottom-most second semiconductor chip CP22 is directly bonded to the first semiconductor chip CP1 without a separate adhesive layer.

[0144] In some embodiments, before bonding the plurality of first preliminary bonding pads 310a and the plurality of second preliminary bonding pads 310b together, a step of treating the exposed surfaces of the plurality of first preliminary bonding pads 310a and the plurality of second preliminary bonding pads 310b with hydrogen plasma is further performed to strengthen the bonding strength between them.

[0145] By bonding the plurality of first preliminary bonding pads 310a and the plurality of second preliminary bonding pads 310b, the plurality of first void control portions 330 are formed as any cavities filled with any inert gas or gaseous material. In an exemplary embodiment, the plurality of first void control portions 330 are any cavities enclosed by the bonding insulating layer 320, the first semiconductor chip CP1 and the bonding insulating layer 320, the bottom second semiconductor chip CP22 and the bonding insulating layer 320, or the first semiconductor chip CP1, the bottom second semiconductor chip CP22 and the bonding insulating layer 320.

[0146] The width in the first horizontal direction (X direction) of the first preliminary bonding insulating layer 320a on the upper surface of the first semiconductor chip CP1 is substantially the same as the horizontal width in the first horizontal direction (X direction) of the first semiconductor chip CP1. The width in the first horizontal direction (X direction) of the second preliminary bonding insulating layer 320b on the lower surface of the lowest second semiconductor chip CP22 is substantially the same as the horizontal width in the first horizontal direction (X direction) of the lowest second semiconductor chip CP22. Therefore, a portion of the first preliminary bonding insulating layer 320a contacts the second preliminary bonding insulating layer 320b to form the bonding insulating layer 320, and the remainder of the first preliminary bonding insulating layer 320a does not contact the second preliminary bonding insulating layer 320b. The portion of the first preliminary bonding insulating layer 320a that contacts the second preliminary bonding insulating layer 320b overlaps the lowest second semiconductor chip CP22 in the vertical direction (Z direction).

[0147] Then, a plurality of first preliminary bonding pads 310a and a first preliminary bonding insulating layer 320a are formed on the upper surface of the lowest second semiconductor chip CP22. The plurality of first preliminary bonding pads 310a are arranged on the upper surface, i.e., the non-active surface, of the lowest second semiconductor chip CP22. The plurality of first preliminary bonding pads 310a are arranged on the upper surface of the lowest second semiconductor chip CP22 to be connected to the plurality of second through-hole electrodes 230. The first preliminary bonding insulating layer 320a is formed on the upper surface, i.e., the non-active surface, of the lowest second semiconductor chip CP22 to surround side surfaces of the plurality of first preliminary bonding pads 310a. The first preliminary bonding insulating layer 320a covers the lowermost second semiconductor chip CP22 and the side surfaces of the plurality of first preliminary bonding pads 310a, but exposes the upper surfaces of the plurality of first preliminary bonding pads 310a without covering them.

[0148] 9, the remaining second semiconductor chips (CP24, CP26, CP28) of the plurality of second semiconductor chips CP2, excluding the bottommost second semiconductor chip CP22, are sequentially disposed on the bottommost second semiconductor chip CP22 located on the first semiconductor chip CP1. A plurality of second preliminary bonding pads 310b and a second preliminary bonding insulating layer 320b are formed on the bottom surfaces of the remaining second semiconductor chips (CP24, CP26, CP28) of the plurality of second semiconductor chips CP2, excluding the bottommost second semiconductor chip CP22. A plurality of first preliminary bonding pads 310a and a first preliminary bonding insulating layer 320a are formed on the top surfaces of the remaining second semiconductor chips (CP24, CP26) of the plurality of second semiconductor chips CP2, excluding the bottommost second semiconductor chip CP22 and the topmost second semiconductor chip CP28. A first pre-support bonding pad 320a and a first pre-support bonding insulating layer 330a are formed on the upper surface of the uppermost second semiconductor chip CP28.

[0149] As described above, a plurality of first void control portions 330 are formed by removing a plurality of local regions from the upper surface of the insulating film for forming the first preliminary bonding insulating layer 320a, a plurality of first void control portions 330 are formed by removing a plurality of local regions from the lower surface of the insulating film for forming the second preliminary bonding insulating layer 320b, or a plurality of first void control portions 330 are formed by removing a plurality of local regions from the upper surface of the insulating film for forming the first preliminary bonding insulating layer 320a and the lower surface of the insulating film for forming the second preliminary bonding insulating layer 320b.

[0150] Thereafter, the remaining second semiconductor chips (CP24, CP26, CP28) of the plurality of second semiconductor chips CP2, excluding the bottommost second semiconductor chip CP22, are sequentially aligned on the bottommost second semiconductor chip CP22 so that the plurality of first preliminary bonding pads 310a and the plurality of second preliminary bonding pads 310b face each other, and are sequentially bonded. In an exemplary embodiment, the plurality of first preliminary bonding pads 310a and the plurality of second preliminary bonding pads 310b, and the first preliminary bonding insulating layer 320a and the second preliminary bonding insulating layer 320b are bonded by heat, pressure, or a combination thereof.

[0151] A plurality of corresponding first preliminary bonding pads 310a and a plurality of corresponding second preliminary bonding pads 310b are bonded to each other to form a plurality of bonding pads 310. Similarly, a first preliminary bonding insulating layer 320a and a second preliminary bonding insulating layer 320b are bonded to each other to form a bonding insulating layer 320. As a result, the remaining second semiconductor chips (CP24, CP26, CP28) of the plurality of second semiconductor chips CP2, except for the bottommost second semiconductor chip CP22, are sequentially bonded directly onto the bottommost second semiconductor chip CP22 without a separate adhesive layer.

[0152] The remaining second semiconductor chips (CP24, CP26, CP28) of the plurality of second semiconductor chips CP2, excluding the bottommost second semiconductor chip CP22, are sequentially bonded onto the bottommost second semiconductor chip CP22, and the plurality of first void control portions 330 are any cavities filled with any inert gas or gaseous material. In an exemplary embodiment, the plurality of first void control portions 330 are any cavities enclosed by the bonding insulating layer 320, any one second semiconductor chip CP2 of the plurality of second semiconductor chips CP2 and the bonding insulating layer 320, and the plurality of second semiconductor chips CP2 and the bonding insulating layer 320.

[0153] 10, after forming second preliminary support bonding pads 320b and a second preliminary support bonding insulating layer 330b on the lower surface of the dummy support substrate 400, the dummy support substrate 400 is disposed on the uppermost second semiconductor chip CP28. The dummy support substrate 400 is disposed on the uppermost second semiconductor chip CP28 using an edge of the uppermost second semiconductor chip CP28 as an alignment key.

[0154] Similar to the process of forming a plurality of first void control portions 330, a plurality of second void control portions 360 are formed by removing a plurality of local areas from the upper surface of the insulating film for forming the first preliminary support bonding insulating layer 350a, a plurality of second void control portions 360 are formed by removing a plurality of local areas from the lower surface of the insulating film for forming the second preliminary support bonding insulating layer 350b, or a plurality of second void control portions 360 are formed by removing a plurality of local areas from the upper surface of the insulating film for forming the first preliminary support bonding insulating layer 350a and the lower surface of the insulating film for forming the second preliminary support bonding insulating layer 350b.

[0155] Similar to the plurality of first void control portions 330, the plurality of second void control portions 360 expose either the uppermost second semiconductor chip CP28 or the dummy support substrate 400. In another embodiment, the plurality of second void control portions 360 expose the first preliminary support bonding insulating layer 350a without exposing the uppermost second semiconductor chip CP28, or expose the second preliminary support bonding insulating layer 350b without exposing the dummy support substrate 400.

[0156] Thereafter, as described above, the dummy support substrate 400 is aligned on the uppermost second semiconductor chip CP28 so that the plurality of first pre-support bonding pads 340a and the plurality of second pre-support bonding pads 340b face each other, and the dummy support substrate 400 is bonded to the uppermost second semiconductor chip CP28. In an exemplary embodiment, the plurality of first pre-support bonding pads 340a and the plurality of second pre-support bonding pads 340b, and the first pre-support bonding insulating layer 350a and the second pre-support bonding insulating layer 350b are bonded by heat, pressure, or a combination thereof.

[0157] A plurality of corresponding first preliminary support bonding pads 340a and a plurality of corresponding second preliminary support bonding pads 340b are bonded to each other to form a plurality of support bonding pads 340. Similarly, a first preliminary support bonding insulating layer 350a and a second preliminary support bonding insulating layer 350b are bonded to each other to form a support bonding insulating layer 350. As a result, the dummy support substrate 400 is directly bonded onto the uppermost second semiconductor chip CP28 without a separate adhesive layer.

[0158] By bonding the dummy support substrate 400 to the top second semiconductor chip CP28, the plurality of second void control portions 360 are any cavities filled with any inert gas or gaseous material. In the exemplary embodiment, the plurality of second void control portions 360 are any cavities closed by the support bonding insulating layer 350, the top second semiconductor chip CP28 and the support bonding insulating layer 350, the dummy support substrate 400 and the support bonding insulating layer 350, the top second semiconductor chip CP28, the dummy support substrate 400 and the support bonding insulating layer 350.

[0159] Thereafter, a package molding layer 500 is formed on the first semiconductor chip CP1 to cover the top surface of the first semiconductor chip CP1 and surround the side surfaces of the plurality of second semiconductor chips CP2 and the dummy support substrate 400.

[0160] After the package molding layer 500 is formed, the first supporting substrate SS1 to which the first release film RF1 is attached is separated from the first semiconductor chip CP1.

[0161] 11, in the resultant structure of FIG. 10, a base redistribution layer 610 is formed on the first wiring structure 120 of the first semiconductor chip CP1. The inverted resultant structure of FIG. 10 is attached to a second support substrate (not shown) to which a second release film (not shown) is attached, thereby forming the base redistribution layer 610. Depending on the process, the second release film may be omitted. In this case, the second release film is formed on the upper surface of the second support substrate, and the dummy support substrate 400 and the package molding layer 500 are attached to the upper surface of the second release film.

[0162] The base redistribution layer 610 includes a package redistribution insulating layer 612, a plurality of package redistribution vias 614, and a plurality of package redistribution line patterns 616. At least some of the plurality of package redistribution vias 614 or at least some of the plurality of package redistribution line patterns 616 are formed to contact the plurality of chip pads 140. Of the plurality of package redistribution line patterns 616, the package redistribution line patterns 616 arranged on the upper surface of the base redistribution layer 610 form package pads 640.

[0163] A plurality of package connecting terminals 650 are attached to the plurality of package pads 640, respectively. For example, the package connecting terminals 650 are solder balls or bumps. In some processes, the base redistribution layer 610 is omitted. In that case, the plurality of package connecting terminals 650 are attached to the plurality of chip pads 140.

[0164] Although the embodiments of the present invention have been described in detail above with reference to the drawings, the present invention is not limited to the above-described embodiments and can be modified in various ways without departing from the technical concept of the present invention. [Explanation of symbols]

[0165] 10, 10a, 10b, 10c, 10d, 20, 30 Bonding structures 12, 14 Lower and upper semiconductor chips 22 Bonding Pad 22C, 22E inner and outer bonding pads 24 Bonding insulation layer 26, 26a, 26b, 26c, 26d, 26_2, 26_3 Void control section 26VT Vertex Void Control Unit 100 Semiconductor Packages 110, 210 First and second semiconductor substrates 120, 220 1st and 2nd wiring structure 122, 222 1st and 2nd wiring layer 124, 224 First and second wiring patterns 126, 226 1st and 2nd wiring vias 130, 230 1st and 2nd through electrode 140 Chip Pad 260, 261 outer and inner void control sections 310 Bonding Pad 310a, 310b First and second spare bonding pads 320 Bonding Insulation Layer 320a, 320b First and second preliminary insulating layers 320L Bottom bonding insulation layer 320R recess 330, 360 First and second void control sections 340 Support Bonding Pad 340a, 340b First and second auxiliary support bonding pads 350 Support Bonding Insulation Layer 350a, 350b First and second pre-support bonding insulating layers 400 Dummy support board 500 Package Molding Layer 610 base redistribution layer 612 Package rewiring insulation layer 614 Package Redistribution Vias 616 Package rewiring line pattern 640 Package Pad 650 Package connecting terminal CP semiconductor chip CP_E Chip Edge CP1 First semiconductor chip CP2, CP24, CP26 Second semiconductor chip CP22 Bottom Second Semiconductor Chip CP28 top second semiconductor chip RF1 First release film SS1 First support substrate

Claims

1. a plurality of semiconductor chips; a plurality of bonding pads interposed between the plurality of semiconductor chips; a bonding insulating layer surrounding the bonding pads between the semiconductor chips; a void control section interposed between the plurality of bonding pads, the plurality of bonding pads are directly connected to the plurality of semiconductor chips; the bonding insulating layer is directly connected to the semiconductor chips; The void control portion is a cavity closed by the bonding insulation layer, any one of the semiconductor chips and the bonding insulation layer, or the semiconductor chips and the bonding insulation layer.

2. 2. The semiconductor package of claim 1, wherein the vertical height of the void-controlling portion is equal to or smaller than the vertical height of the bonding insulating layer.

3. The semiconductor package of claim 1 , wherein the void control portion is spaced apart from the plurality of bonding pads with a portion of the bonding insulating layer interposed therebetween.

4. The semiconductor package according to claim 1 , wherein the void control portion is interposed between any one of the plurality of semiconductor chips and the bonding insulating layer.

5. the void control section is separated from a first semiconductor chip of the plurality of semiconductor chips with a first portion of the bonding insulating layer interposed therebetween; The semiconductor package of claim 1 , wherein the void control portion is spaced apart from a second semiconductor chip of the plurality of semiconductor chips across a second portion of the bonding insulating layer.

6. The semiconductor package according to claim 1 , wherein the void control portion has a linear shape extending in one direction.

7. The semiconductor package according to claim 1 , wherein the void control portion has a cross shape.

8. the plurality of bonding pads comprises at least one row, at least one column, or a combination thereof; 2. The semiconductor package of claim 1, wherein the void control portion overlaps at least one row of the plurality of bonding pads in a first horizontal direction or at least one column of the plurality of bonding pads in a second horizontal direction.

9. 2. The semiconductor package according to claim 1, wherein one end of the void control portion faces chip edges of the plurality of semiconductor chips.

10. a first semiconductor chip including a first semiconductor substrate having an active surface and a non-active surface opposite to each other, and a plurality of first through-electrodes penetrating the first semiconductor substrate; a plurality of second semiconductor chips including a bottom second semiconductor chip and a top second semiconductor chip, each of which includes a second semiconductor substrate having an active surface and a non-active surface opposite to each other, and a plurality of second through electrodes penetrating the second semiconductor substrate, the active surface of the second semiconductor substrate facing the non-active surface of the first semiconductor substrate; a plurality of bonding pads respectively interposed between the first semiconductor chip and the bottom second semiconductor chip and between the plurality of second semiconductor chips adjacent to each other, electrically connecting the plurality of first through-hole electrodes and the plurality of second through-hole electrodes; a bonding insulating layer surrounding the bonding pads between the first semiconductor chip and the bottom second semiconductor chip and between the second semiconductor chips adjacent to each other; a first void control portion interposed between the plurality of bonding pads; The semiconductor package, wherein the first void control portion includes a cavity.

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