Detection circuit, receiving circuit, and semiconductor integrated circuit

Abstract

To reduce power consumption and a circuit area when detecting an idle mode based on a differential input voltage.SOLUTION: A detection circuit for receiving a differential input voltage and detecting whether or not the differential input voltage is a voltage state indicating an idle mode, has: a differential input circuit for receiving the differential input voltage and generating a first differential detection current according to the differential input voltage; a detection current generation circuit configuring a current mirror circuit with the differential input circuit, for generating a second differential detection current according to the first differential detection current; and a detection voltage generation circuit for receiving the second differential detection current and generating a detection voltage having a voltage according to the second differential detection current, wherein a differential current value of the first differential detection current is different between a case in which a differential voltage value of the differential input voltage is smaller than a first threshold value and a case in which the differential voltage value is larger than the first threshold value.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a detection circuit, a receiving circuit, and a semiconductor integrated circuit. [Background technology]

[0002] Patent Document 1 describes an optical signal detection circuit that detects the presence or absence of an input optical signal based on a differential signal obtained by photoelectric conversion of an optical signal. The differential amplifier circuit differentially amplifies the differential signal input via a coupling capacitor and outputs the amplified output signal. The differential current summing circuit adjusts the DC offset voltage of the positive-phase and negative-phase signals of the amplified output signal by adding a DC current corresponding to an input offset adjustment voltage to the positive-phase and negative-phase signals, and outputs the result as a current summing output signal. The comparator compares the voltage values ​​of the positive-phase and negative-phase signals of the current summing output signal and outputs the comparison result as a comparison output signal. The holding circuit rectifies the comparison output signal and charges a holding capacitor, and discharges the resulting DC holding voltage through a discharge resistor. The hysteresis comparator circuit compares the holding voltage with two different decision threshold voltages determined by an input sensitivity adjustment voltage, and outputs the comparison result as an optical signal detection signal indicating the presence or absence of an input optical signal.

[0003] Non-Patent Document 1 describes an electrical idle detector that detects an electrical idle (EI) signal using a peak detector including a source follower. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-255056 [Non-patent literature]

[0005] [Non-Patent Document 1] Nawathe et al., "Implementation of an 8-Core, 64-Thread, Power-Efficient SPARC Server on a Chip", IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.43, NO.1, JANUARY 2008 Summary of the Invention [Problem to be solved by the invention]

[0006] Patent Document 1 uses a differential amplifier circuit, which requires operation at a high power supply voltage, thereby increasing power consumption, and requires the use of large-sized transistors, thereby increasing the circuit area.

[0007] Non-Patent Document 1 uses a source follower. Since a source follower has a voltage gain of 1 or less, the signal is attenuated, so a high voltage gain is required, which increases power consumption and the circuit area due to the need to use large transistors.

[0008] An object of the present invention is to provide a detection circuit that can reduce power consumption and circuit area when detecting an idle mode based on a differential input voltage. [Means for solving the problem]

[0009] The detection circuit receives a differential input voltage and detects whether the differential input voltage is in a voltage state indicating an idle mode, and includes a differential input circuit that receives the differential input voltage and generates a first differential detection current corresponding to the differential input voltage, a detection current generation circuit that forms a current mirror circuit with the differential input circuit and generates a second differential detection current corresponding to the first differential detection current, and a detection voltage generation circuit that receives the second differential detection current and generates a detection voltage having a voltage corresponding to the second differential detection current, and the differential current value of the first differential detection current differs between when the differential voltage value of the differential input voltage is smaller than a first threshold value and when the differential voltage value is larger than the first threshold value. [Effects of the Invention]

[0010] When the idle mode is detected based on the differential input voltage, the power consumption and the circuit area can be reduced. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a semiconductor integrated circuit according to this embodiment. [Figure 2] FIG. 2 is a circuit diagram showing an example of the configuration of the detection circuit. [Figure 3] FIG. 3 is a diagram showing an example of a voltage waveform for explaining the operation of the detection circuit. [Figure 4] FIG. 4 is a diagram showing an example of a simulation result of a voltage waveform. [Figure 5] FIG. 5 is a diagram showing an example of a simulation result of a voltage waveform. DETAILED DESCRIPTION OF THE INVENTION

[0012] 1 is a block diagram showing an example of the configuration of a semiconductor integrated circuit 100 according to this embodiment. The semiconductor integrated circuit 100 includes a receiving circuit 101 and an internal circuit 102. The receiving circuit 101 receives differential input voltages IP and IN, and outputs received data to the internal circuit 102. The internal circuit 102 processes the received data.

[0013] The receiving circuit 101 receives input voltages IP and IN. The input voltages IP and IN are differential input voltages. As shown in FIG. 3, during the active mode period T2, the input voltages IP and IN are differential input voltages representing data signals, one at a high level and the other at a low level. During the electrical idle (EI) mode period T1, the input voltages IP and IN represent electrical idle (EI) signals and are both at a substantially low level. Hereinafter, electrical idle (EI) will be simply referred to as idle.

[0014] The receiving circuit 101 includes a termination resistor 111, a continuous time linear equalizer (CTLE) 112, a decision feedback equalizer (DFE) 113, a demultiplexer (DEMUX) 114, a clock generating circuit 115, a detection circuit 116, and a control circuit 117.

[0015] The termination resistor 111 is connected between the transmission lines of the input voltages IP and IN. The continuous-time linear equalizer 112 reduces inter-symbol interference jitter (ISI jitter) of the received differential input voltages IP and IN. The clock generation circuit 115 generates a clock signal. The decision feedback equalizer 113, in synchronization with the clock signal generated by the clock generation circuit, decides and equalizes the differential input voltage output by the continuous-time linear equalizer 112, and outputs received data. The demultiplexer circuit 114 converts the received data output by the decision feedback equalizer 113 from serial to parallel, and outputs the parallel received data to the internal circuit 102.

[0016] The detection circuit 116 receives the differential input voltages IP and IN and outputs a detection signal DET indicating whether the differential input voltages IP and IN are in a voltage state indicating a predetermined idle mode. As shown in Fig. 3, during the idle mode period T1, the detection signal DET is at a high level. During the active mode period T2, the detection signal DET is at a low level.

[0017] When a high-level detection signal DET is output, indicating that the differential input voltages IP and IN are in a voltage state indicative of a predetermined idle mode, the control circuit 117 controls the power-down signal PD to be high, thereby turning off the power supplies to the continuous-time linear equalizer 112, the decision feedback equalizer 113, the demultiplexer circuit 114, and the clock generation circuit 115. For example, when the continuous-time linear equalizer 112, the decision feedback equalizer 113, the demultiplexer circuit 114, and the clock generation circuit 115 receive a high-level power-down signal PD, they are each disconnected from at least one of the power supply potential node and the reference potential node by their switching transistors. This allows the receiving circuit 101 to reduce power consumption in the idle mode.

[0018] Furthermore, when a low-level detection signal DET is output, indicating that the differential input voltages IP and IN are not in a voltage state indicative of the predetermined idle mode, the control circuit 117 controls the power-down signal PD to be low, turning on the power supplies to the continuous-time linear equalizer 112, the decision feedback equalizer 113, the demultiplexer circuit 114, and the clock generation circuit 115. For example, upon receiving a low-level power-down signal PD, the continuous-time linear equalizer 112, the decision feedback equalizer 113, the demultiplexer circuit 114, and the clock generation circuit 115 are connected to the power supply potential node and the reference potential node by their switching transistors, respectively. As a result, in active mode, the receiving circuit 101 is enabled for operation.

[0019] Fig. 2 is a circuit diagram showing an example of the configuration of the detection circuit 116 in Fig. 1. The detection circuit 116 has p-channel field effect transistors 201-211, n-channel field effect transistors 212-214, resistors 215-226, capacitors 227-228, and a comparison circuit 229.

[0020] The power supply potential node VDD is, for example, a node at a power supply potential of 0.8 V. The reference potential node VSS is, for example, a node at ground potential of 0 V. The bias potential nodes BP and BN are bias potential nodes, respectively. The input voltages IP and IN are the same as the input voltages IP and IN in FIG. 1, respectively.

[0021] Resistor 215 is connected between power supply potential node VDD and the source of p-channel field effect transistor 201. The gate of p-channel field effect transistor 201 is connected to bias potential node BP, and the drain is connected to the source of p-channel field effect transistor 210. The gate of p-channel field effect transistor 210 is connected to the node of input voltage IP, and the drain is connected to reference potential node VSS.

[0022] Resistor 216 is connected between power supply potential node VDD and the source of p-channel field effect transistor 202. The gate of p-channel field effect transistor 202 is connected to bias potential node BP, and the drain is connected to the source of p-channel field effect transistor 211. The gate of p-channel field effect transistor 211 is connected to the node of input voltage IN, and the drain is connected to reference potential node VSS.

[0023] The resistor 217 is connected between the power supply potential node VDD and the source of the p-channel field effect transistor 203. The gate and drain of the p-channel field effect transistor 203 are connected to the drain of the n-channel field effect transistor 212.

[0024] The resistor 218 is connected between the power supply potential node VDD and the source of the p-channel field effect transistor 204. The p-channel field effect transistor 204 has a gate connected to the bias potential node BP and a drain connected to the drain of the n-channel field effect transistor 212.

[0025] The resistor 219 is connected between the power supply potential node VDD and the source of the p-channel field effect transistor 205. The p-channel field effect transistor 205 has a gate connected to the bias potential node BP and a drain connected to the drain of the n-channel field effect transistor 213.

[0026] The resistor 220 is connected between the power supply potential node VDD and the source of the p-channel field effect transistor 206. The gate and drain of the p-channel field effect transistor 206 are connected to the drain of the n-channel field effect transistor 213.

[0027] The n-channel field effect transistor 212 has a gate connected to the source of the p-channel field effect transistor 210 and a source connected to the drain of the n-channel field effect transistor 214 .

[0028] The n-channel field effect transistor 213 has a gate connected to the source of the p-channel field effect transistor 211 and a source connected to the drain of the n-channel field effect transistor 214 .

[0029] The gate of the n-channel field effect transistor 214 is connected to the bias potential node BN. The resistor 224 is connected between the source of the n-channel field effect transistor 214 and the reference potential node VSS.

[0030] Resistor 221 is connected between power supply potential node VDD and the source of p-channel field effect transistor 207. The gate of p-channel field effect transistor 207 is connected to the drain of n-channel field effect transistor 212, and the drain is connected to node N1.

[0031] Resistor 222 is connected between power supply potential node VDD and the source of p-channel field effect transistor 208. The gate of p-channel field effect transistor 208 is connected to the drain of n-channel field effect transistor 213, and the drain is connected to node N1.

[0032] The resistor 223 is connected between the power supply potential node VDD and the source of the p-channel field effect transistor 209. The p-channel field effect transistor 209 has a gate connected to the bias potential node BP and a drain connected to the node N1.

[0033] A capacitor 227 is connected between the node N1 and the reference potential node VSS. A resistor 225 is connected between the node N1 and the reference potential node VSS. A resistor 226 is connected between the node N1 and the node N2. A capacitor 228 is connected between the node N2 and the reference potential node VSS.

[0034] The detection voltage PK is the voltage of the node N2. The comparator circuit 229 compares the detection voltage PK with the reference voltage REF and outputs a detection signal DET. The detection signal DET indicates whether the differential input voltages IP and IN are in a voltage state indicating a predetermined idle mode.

[0035] The detection circuit 116 includes a level shift circuit 230, a differential pair circuit 231, a peak detection circuit 232, and a low-pass filter circuit 233. The level shift circuit 230 includes p-channel field effect transistors 201, 202, 210, and 211, and resistors 215 and 216. The p-channel field effect transistors 201 and 202 are constant current sources. A voltage SP is the gate voltage of the n-channel field effect transistor 212. A voltage SN is the gate voltage of the n-channel field effect transistor 213. The voltages SP and SN are differential voltages.

[0036] FIG. 3 is a diagram illustrating an example of voltage waveforms for explaining the operation of the detection circuit 116 of FIG. 2. The period before time t1 is the idle mode period T1. The period from time t1 to t2 is the active mode period T2. The period after time t2 is the idle mode period. During the active mode period T2, the input voltages IP and IN are differential input voltages representing data signals, one of which is high and the other is low. During the idle mode period T1, the input voltages IP and IN represent idle signals and are both approximately low. The level shift circuit 230 level-shifts the differential input voltages IP and IN, which are in the range of, for example, 0V to 190mV, and outputs differential voltages SP and SN, which are in the range of, for example, 500mV to 675mV. The voltage range of the differential voltages SP and SN is the voltage range in which the n-channel field-effect transistors 212 and 213 of the differential pair operate in their operating regions.

[0037] The differential pair circuit 231 includes a differential pair of n-channel field-effect transistors 212 and 213, resistors 217 to 220, and 224, p-channel field-effect transistors 203 to 206, and an n-channel field-effect transistor 214. The p-channel field-effect transistors 203 and 206 are each diode-connected. The p-channel field-effect transistors 204 and 205 are each constant current sources. The gates of the n-channel field-effect transistors 212 and 213 receive differential voltages SP and SN that have been level-shifted by the level shift circuit 230. A current corresponding to the voltage SP flows through the drain of the n-channel field-effect transistor 212. A current corresponding to the voltage SN flows through the drain of the n-channel field-effect transistor 213. Since the voltages SP and SN are differential voltages, a differential current (differential detection current) flows through the drains of the n-channel field-effect transistors 212 and 213. The differential pair circuit 231 generates a differential detection current corresponding to the differential voltages SP and SN.

[0038] The level shift circuit 230 increases the common-mode voltage of the differential input voltages IP and IN to the operating range of the differential pair of n-channel field-effect transistors 212 and 213, and outputs the differential voltages SP and SN. The differential pair of n-channel field-effect transistors 212 and 213 removes the common-mode voltage of the differential voltages SP and SN.

[0039] The level shift circuit 230 and the differential pair circuit 231 constitute a differential input circuit, which receives differential input voltages IP and IN and generates a differential detection current according to the differential input voltages IP and IN.

[0040] The peak detection circuit 232 includes a differential pair of p-channel field-effect transistors 207 and 208, a p-channel field-effect transistor 209, and resistors 221 to 223. The p-channel field-effect transistor 209 is a constant current source for fine adjustment. The gates of the p-channel field-effect transistors 207 and 208 receive a differential voltage corresponding to the differential current flowing through the drains of the n-channel field-effect transistors 212 and 213. The p-channel field-effect transistors 203 and 207 form a current mirror circuit in which the gates of both are connected to the drain of the n-channel field-effect transistor 212, and the same or proportional currents flow through them. The p-channel field-effect transistors 206 and 208 form a current mirror circuit in which the gates of both are connected to the drain of the n-channel field-effect transistor 213, and the same or proportional currents flow through them. Because a differential current flows through the drains of the n-channel field-effect transistors 212 and 213, a differential current (differential detection current) also flows through the drains of the p-channel field-effect transistors 207 and 208. A current (peak current) flows through node N1, which is the sum of the drain currents of p-channel field effect transistors 207 and 208. Peak detection circuit 232 is a detection current generation circuit, and forms a current mirror circuit together with differential pair circuit 231, and generates a differential current (differential detection current) corresponding to the differential current flowing through the drains of n-channel field effect transistors 212 and 213.

[0041] When the differential voltages SP and SN become a common-mode voltage, almost no current flows through the drains of the differential pair of n-channel field-effect transistors 212 and 213. In that case, almost no current flows through the drains of the differential pair of p-channel field-effect transistors 207 and 208. Therefore, a minute current is always allowed to flow through p-channel field-effect transistor 209, which is a non-adjustment constant current source.

[0042] The tail current of the differential pair of p-channel field effect transistors 207 and 208 flows through resistor 225. Resistor 225 receives the differential current flowing through the drains of p-channel field effect transistors 207 and 208, and generates a voltage according to the differential current flowing through the drains of p-channel field effect transistors 207 and 208. Resistor 225 converts the current flowing through node N1 into a voltage.

[0043] The low-pass filter circuit 233 has a resistor 226 and a capacitor 228, and low-pass filters the voltage at the node N1 and outputs the low-pass filtered detection voltage PK to the node N2. The detection voltage PK is a voltage in which high-frequency components are reduced compared to the voltage at the node N1. The capacitor 227 assists the low-pass filtering function of the low-pass filter circuit 233. Note that the capacitor 227 may be omitted.

[0044] Resistor 225 and low-pass filter circuit 233 constitute a detection voltage generation circuit, which receives the differential current flowing through the drains of p-channel field-effect transistors 207 and 208, and generates a detection voltage PK having a voltage corresponding to the differential current flowing through the drains of p-channel field-effect transistors 207 and 208.

[0045] The comparator circuit 229 compares the detection voltage PK with the reference voltage REF and outputs a detection signal DET indicating whether the differential input voltages IP and IN are in a voltage state indicating a predetermined idle mode. Specifically, when the detection voltage PK is lower than the reference voltage REF, the comparator circuit 229 outputs a high-level detection signal DET indicating that the differential input voltages IP and IN are in a voltage state indicating a predetermined idle mode.

[0046] FIG. 4 is a diagram showing an example of a simulation result of a voltage waveform around time t1 in FIG. 3. FIG. 5 is a diagram showing an example of a simulation result of a voltage waveform around time t2 in FIG. 3. Before time t1 is an idle mode period T1. From time t1 to t2 is an active mode period T2. After time t2 is an idle mode period T1. The differential input voltage IPN is a voltage of (input voltage IP)-(input voltage IN). The detection voltage PK is the voltage of node N2 in FIG. 2. The detection signal DET is an output signal of the comparison circuit 229 in FIG. 2.

[0047] During the stable period of the idle mode period T1 before time t1 in FIG. 4, as shown in FIG. 3, the input voltages IP and IN are substantially the same voltage, so the differential input voltage IPN is substantially 0 V. Because the input voltages IP and IN are both low, the currents flowing through the drains of the differential pair of n-channel field-effect transistors 212 and 213 are both small, and the currents flowing through the drains of the differential pair of p-channel field-effect transistors 207 and 208 are also small. As a result, the detection voltage PK is low. Because the detection voltage PK is lower than the reference voltage REF, the comparator circuit 229 outputs a high-level detection signal DET. During the idle mode period T1, the detection signal DET is high.

[0048] Near time t1 in Figure 4, the amplitude of the differential input voltage IPN gradually increases. As a result, the total current flowing through the drains of the n-channel field-effect transistors 212 and 213 of the differential pair gradually increases, and the total current flowing through the drains of the p-channel field-effect transistors 207 and 208 of the differential pair also gradually increases. As a result, the detection voltage PK gradually increases. After time t1, the comparison circuit 229 outputs a low-level detection signal DET because the detection voltage PK is higher than the reference voltage REF. During the active mode period T2, the detection signal DET is low.

[0049] Around time t2 in Figure 5, the amplitude of the differential input voltage IPN gradually decreases. As a result, the total current flowing through the drains of the n-channel field-effect transistors 212 and 213 of the differential pair gradually decreases, and the total current flowing through the drains of the p-channel field-effect transistors 207 and 208 of the differential pair also gradually decreases. As a result, the detection voltage PK gradually decreases. After time t2, the comparison circuit 229 outputs a high-level detection signal DET because the detection voltage PK is lower than the reference voltage REF. During the idle mode period T1, the detection signal DET is high.

[0050] By providing the low-pass filter circuit 233, it is possible to reduce noise that occurs when the detection signal DET alternates between high and low levels at high frequencies around times t1 and t2.

[0051] As described above, the detection circuit 116 can output a high-level detection signal DET during the idle mode period T1 and a low-level detection signal DET during the active mode period T2. The detection circuit 116 can detect with high accuracy the detection signal DET that indicates whether the differential input voltages IP and IN are in a voltage state that indicates the idle mode.

[0052] Non-Patent Document 1 uses a source follower with a high voltage gain, which requires operation at a high power supply voltage, thereby increasing power consumption, and requires the use of large-sized transistors, thereby increasing the circuit area.

[0053] The detection circuit 116 according to this embodiment uses a current mirror circuit instead of a source follower with a high voltage gain, and therefore can lower the power supply voltage (e.g., 0.8 V) of the power supply potential node VDD, reduce power consumption, reduce the transistor size, and reduce the circuit area.

[0054] Furthermore, since the comparator circuit 229 compares the low-frequency detection voltage DET output by the low-pass filter circuit 233 with the reference voltage REF, high-speed operation is not required, and power consumption and circuit area can be reduced.

[0055] It should be noted that the above-described embodiments are merely examples of specific embodiments for carrying out the present invention, and the technical scope of the present invention should not be construed as being limited by these embodiments. In other words, the present invention can be carried out in various forms without departing from its technical concept or main features. [Industrial Applicability]

[0056] When the idle mode is detected based on the differential input voltage, the power consumption and the circuit area can be reduced. [Explanation of symbols]

[0057] 229 Comparison circuit 230 Level Shift Circuit 231 Differential Pair Circuit 232 Peak detection circuit 233 Low-pass filter circuit

Claims

1. A detection circuit that receives a differential input voltage and detects whether the differential input voltage is in a voltage state indicative of an idle mode, a differential input circuit that receives the differential input voltage and generates a first differential detection current in response to the differential input voltage; a detection current generating circuit that forms a current mirror circuit together with the differential input circuit and generates a second differential detection current corresponding to the first differential detection current; a detection voltage generating circuit that receives the second differential detection current and generates a detection voltage having a voltage corresponding to the second differential detection current; and The differential current value of the first differential detection current differs between when the differential voltage value of the differential input voltage is smaller than a first threshold value and when the differential voltage value is larger than the first threshold value. Detection circuit.

2. a comparison circuit that compares the detected voltage with a reference voltage and outputs a signal indicating whether the difference voltage value of the differential input voltage indicates the idle mode; 2. The detection circuit of claim 1, comprising:

3. 2. The detection circuit according to claim 1, wherein the differential input circuit comprises a first differential pair of transistors through which the first differential detection current flows.

4. the differential input circuit has a level shift circuit that level-shifts the differential input voltage; 4. The detection circuit of claim 3, wherein the transistors of the first differential pair receive a differential input voltage level-shifted by the level shift circuit.

5. The detection circuit according to any one of claims 1 to 4, wherein the detection current generation circuit has a second differential pair of transistors that receives a differential voltage corresponding to the first differential detection current and flows the second differential detection current.

6. 6. The detection circuit according to claim 5, wherein the detection voltage generation circuit has a resistor through which a tail current of the transistors of the second differential pair flows.

7. 7. The detection circuit according to claim 1, wherein the detection voltage generation circuit includes a low-pass filter circuit that low-pass filters the detection voltage.

8. a continuous-time linear equalizer circuit for reducing intersymbol interference jitter in the received differential input voltage; a detection circuit that receives the received differential input voltage and detects whether the differential input voltage is in a voltage state indicative of an idle mode; a control circuit that controls a power supply of the continuous-time linear equalization circuit to be turned off when it is detected that the differential input voltage is in a voltage state that indicates the idle mode; The detection circuit a differential input circuit that receives the differential input voltage and generates a first differential detection current in response to the differential input voltage; a detection current generating circuit that forms a current mirror circuit together with the differential input circuit and generates a second differential detection current corresponding to the first differential detection current; a detection voltage generating circuit that receives the second differential detection current and generates a detection voltage having a voltage corresponding to the second differential detection current; and The differential current value of the first differential detection current differs between when the differential voltage value of the differential input voltage is smaller than a first threshold value and when the differential voltage value is larger than the first threshold value. Receiver circuit.

9. a comparison circuit that compares the detected voltage with a reference voltage and outputs a signal indicating whether the difference voltage value of the differential input voltage indicates the idle mode; 9. The receiving circuit of claim 8, comprising:

10. a decision feedback equalization circuit that determines and equalizes the input voltage output from the continuous-time linear equalization circuit and outputs received data; a demultiplexer circuit that converts the received data output by the decision feedback equalization circuit from serial to parallel; and 10. The receiving circuit according to claim 8, wherein the control circuit further controls to turn off the power supplies of the decision feedback equalizer circuit and the demultiplexer circuit.

11. 11. The receiver circuit according to claim 8, wherein the differential input circuit has a first differential pair of transistors through which the first differential detection current flows.

12. the differential input circuit has a level shift circuit that level-shifts the differential input voltage; 12. The receiving circuit according to claim 11, wherein the transistors of the first differential pair receive a differential input voltage level-shifted by the level shift circuit.

13. The receiving circuit according to any one of claims 8 to 12, wherein the detection current generating circuit has a second differential pair of transistors that receives a differential voltage corresponding to the first differential detection current and flows the second differential detection current.

14. a receiving circuit that receives a differential input voltage and outputs received data; an internal circuit for processing the received data; The receiving circuit a continuous-time linear equalizer circuit for reducing intersymbol interference jitter in the received differential input voltage; a detection circuit that receives the received differential input voltage and detects whether the differential input voltage is in a voltage state indicative of an idle mode; a control circuit that controls a power supply of the continuous-time linear equalization circuit to be turned off when it is detected that the differential input voltage is in a voltage state indicating the idle mode; The detection circuit a differential input circuit that receives the differential input voltage and generates a first differential detection current in response to the differential input voltage; a detection current generating circuit that forms a current mirror circuit together with the differential input circuit and generates a second differential detection current corresponding to the first differential detection current; a detection voltage generating circuit that receives the second differential detection current and generates a detection voltage having a voltage corresponding to the second differential detection current; and The differential current value of the first differential detection current differs between when the differential voltage value of the differential input voltage is smaller than a first threshold value and when the differential voltage value is larger than the first threshold value. Semiconductor integrated circuit.

15. a comparison circuit that compares the detected voltage with a reference voltage and outputs a signal indicating whether the difference voltage value of the differential input voltage indicates the idle mode; The semiconductor integrated circuit according to claim 14 , comprising:

16. a decision feedback equalization circuit that determines and equalizes the input voltage output from the continuous-time linear equalization circuit and outputs received data; a demultiplexer circuit that converts the received data output by the decision feedback equalization circuit from serial to parallel; and 16. The semiconductor integrated circuit according to claim 14, wherein the control circuit further controls to turn off the power supplies of the decision feedback equalizer circuit and the demultiplexer circuit.

17. 17. The semiconductor integrated circuit according to claim 14, wherein the differential input circuit has a first differential pair of transistors through which the first differential detection current flows.

18. the differential input circuit has a level shift circuit that level-shifts the differential input voltage; 18. The semiconductor integrated circuit according to claim 17, wherein the transistors of the first differential pair receive a differential input voltage level-shifted by the level shift circuit.

19. The semiconductor integrated circuit according to any one of claims 14 to 18, wherein the detection current generating circuit has a second differential pair of transistors that receives a differential voltage corresponding to the first differential detection current and flows the second differential detection current.

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