Manufacturing method for semiconductor device

Abstract

To provide a method of reducing bonding failure while performing minute bonding of a semiconductor chip in a case of performing three-dimensional implementation of the semiconductor chip.SOLUTION: A manufacturing method for a semiconductor device includes steps of: preparing a first semiconductor substrate including a first insulating film and a first electrode; preparing a second semiconductor substrate including a second insulating film and a plurality of second electrodes; dividing the second semiconductor substrate into pieces and acquiring a plurality of semiconductor chips each including an insulating film part corresponding to the second insulating film and at least one second electrode; attaching the first insulating film of the first semiconductor substrate and the insulating film part of the semiconductor chip to each other; and directly bonding the first electrode of the first semiconductor substrate and the second electrode of the semiconductor chip to each other. In this manufacturing method, at least one of the first insulating film and the second insulating film contains an organic material.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which an individual semiconductor chip is bonded to a semiconductor substrate (another semiconductor chip, a semiconductor wafer, or the like). [Background technology]

[0002] In recent years, three-dimensional packaging has been considered to improve the integration density of LSIs. Non-Patent Document 1 discloses an example of three-dimensional packaging of semiconductor chips. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] FC Chen et al., “Systemon Integrated Chips(SoIC TM) for 3D Heterogeneous Integration”, 2019IEEE 69th Electronic Components and Technology Conference (ECTC), p.594-599(2019) Summary of the Invention [Problem to be solved by the invention]

[0004] In the case of three-dimensional semiconductor chip packaging, hybrid bonding technology used in wafer-to-wafer (W2W) bonding is being considered to achieve fine bonding of device wiring and prevent misalignment during bonding. However, unlike W2W, three-dimensional semiconductor chip packaging involves the generation of foreign matter (cutting debris) during the singulation process, which can potentially adhere to the bonding interface of semiconductor chips (the insulating film used in hybrid bonding). This insulating film is typically made of inorganic materials such as silicon dioxide (SiO2), but due to its hardness, any foreign matter that adheres can create large voids in the insulating film, with diameters approaching 1,000 times the height of the foreign matter, toward the bonding interface. Therefore, simply applying hybrid bonding technology used in W2W to three-dimensional semiconductor chip packaging could result in bonding failures due to these voids. However, using high-purity clean rooms and equipment to prevent these bonding failures requires significant capital investment.

[0005] SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a method for reducing bonding defects while performing fine bonding of semiconductor chips when three-dimensionally mounting semiconductor chips. [Means for solving the problem]

[0006] A method for manufacturing a semiconductor device according to one aspect of the present invention includes the steps of: preparing a first semiconductor substrate having a first substrate body and a first insulating film and a first electrode provided on one surface of the first substrate body; preparing a second semiconductor substrate having a second substrate body and a second insulating film and a plurality of second electrodes provided on one surface of the second substrate body; polishing at least one of the first and second semiconductor substrates; singulating the second semiconductor substrate to obtain a plurality of semiconductor chips, each of which has an insulating film portion corresponding to the second insulating film and at least one second electrode; aligning the second electrode of at least one of the plurality of semiconductor chips with the first electrode of the first semiconductor substrate; bonding the first insulating film of the first semiconductor substrate and the insulating film portion of the semiconductor chip together; and bonding the first electrode of the first semiconductor substrate to the second electrode of the semiconductor chip. In this manufacturing method, at least one of the first insulating film and the second insulating film contains an organic material.

[0007] In the above-described manufacturing method, at least one of the insulating films of the first semiconductor substrate and the second semiconductor substrate (semiconductor chip) contains an organic material. Organic materials generally have a lower modulus of elasticity than inorganic materials. By using such a soft material for the insulating film in hybrid bonding, even if foreign particles generated during dicing during semiconductor chip separation adhere to the insulating film, the insulating film around the foreign particles easily deforms, allowing the foreign particles to be contained within the organic material without creating large voids in the insulating film. In other words, the influence of foreign particles can be suppressed by the insulating film containing an organic material. Therefore, the above-described manufacturing method can reduce bonding defects while performing fine bonding of semiconductor chips. Furthermore, although not limited to this, this manufacturing method can reduce bonding defects, eliminating the need for highly clean rooms and equipment to prevent bonding defects, thereby easing limitations on the manufacturing location of the above-described semiconductor device.

[0008] In the manufacturing method, in the polishing step, one side of the first semiconductor substrate may be polished using a CMP method so that the surface of the first electrode is flush with the surface of the first insulating film or is recessed relative to the surface of the first insulating film. Also, in the polishing step, one side of the second semiconductor substrate may be polished using a CMP method so that the surfaces of each of the plurality of second electrodes are flush with the surface of the second insulating film or are recessed relative to the surface of the second insulating film. By performing such polishing, the first electrode and the second electrode are prevented from contacting each other prematurely in the step of bonding the insulating films, and the step of bonding the first insulating film of the first semiconductor substrate and the insulating film portion of the semiconductor chip to each other can be more reliably performed.

[0009] In the above manufacturing method, in the bonding step, the insulating film portion of the semiconductor chip may be bonded to the first insulating film of the first semiconductor substrate at a temperature where the temperature difference between the semiconductor chip and the first semiconductor substrate is within 10°C or at room temperature. In this case, the semiconductor chip can be bonded to the first semiconductor substrate while suppressing misalignment. Furthermore, bonding is possible even if the first insulating film of the first semiconductor substrate and the insulating film portion of the semiconductor chip are made of different materials.

[0010] In the above manufacturing method, the modulus of elasticity of the organic material contained in at least one of the first insulating film and the second insulating film may be 7.0 GPa or less. In this case, even if foreign matter generated by dicing during the separation into semiconductor chips adheres to the bonding interface, the foreign matter can be more reliably contained within the organic material without creating large voids, thereby further reducing bonding defects. The modulus of elasticity of the organic material is preferably 5.0 GPa or less, more preferably 2.0 GPa or less. Note that the modulus of elasticity referred to here means Young's modulus.

[0011] In the above manufacturing method, the thermal expansion coefficient of the organic material contained in at least one of the first insulating film and the second insulating film may be 70 ppm / k or less, and more preferably 50 ppm / k or less, in the thickness direction. In this case, the thermal expansion coefficient of the organic material becomes equal to or close to the thermal expansion coefficients of the first electrode and the second electrode, and when heat is applied, the difference in thermal expansion between the insulating layer and the electrode becomes close, further reducing bonding defects. Note that the organic material specified here may have the above-mentioned elastic modulus, or may have an elastic modulus different from the above-mentioned elastic modulus.

[0012] In the above manufacturing method, the organic material contained in the second insulating film may have a polishing rate that is five times or less than the polishing rate of the metal material constituting the second electrode. For example, when the polishing rate of the metal material constituting the second electrode is 50 nm / min, the polishing rate of the organic material contained in the second insulating film is preferably 200 nm / min or less (four times or less), more preferably 100 nm / min or less (two times or less), and even more preferably 50 nm / min or less (the same or less). Such a polishing rate relationship makes it easier to polish the second insulating film containing the organic material and the second electrode, and can simplify the polishing process. The polishing rate relationship between the first insulating film and the first electrode may be the same as above.

[0013] In the above manufacturing method, the organic material contained in at least one of the first insulating film and the second insulating film may include polyimide, a polyimide precursor (e.g., polyimide ester or polyamic acid), polyamideimide, benzocyclobutene (BCB), polybenzoxazole (PBO), or a PBO precursor. The organic material contained in at least one of the first insulating film and the second insulating film may include a photosensitive resin, a thermosetting non-conductive film, or a thermosetting resin. When a photosensitive resin is used, the process of fabricating the connection electrodes can be simplified. When a thermosetting non-conductive film is used, the time required for the process of fabricating the insulating layer can be shortened.

[0014] In the above manufacturing method, the thickness of the second insulating film may be thicker than the thickness of the first insulating film. In this case, most of the foreign matter that adheres to the bonding interface during separation into semiconductor chips or chip mounting can be contained by the second insulating film, thereby further reducing bonding defects. On the other hand, the thickness of the second insulating film may be thinner than the thickness of the first insulating film. In this case, the height of the mounted semiconductor chip can be reduced. The thicknesses of the first insulating film and the second insulating film may be determined according to the height of the corresponding electrodes. [Effects of the Invention]

[0015] According to the present invention, it is possible to provide a method for reducing bonding defects while performing fine bonding of semiconductor chips when three-dimensionally mounting semiconductor chips. [Brief explanation of the drawings]

[0016] [Figure 1] FIG. 1 is a cross-sectional view schematically showing an example of a semiconductor device manufactured by a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 2] 2A to 2C are diagrams sequentially showing a method for manufacturing the semiconductor device shown in FIG. [Figure 3] FIG. 3 is a diagram showing in more detail the bonding method in the method for manufacturing the semiconductor device shown in FIG. [Figure 4] 4A to 4C are diagrams showing a method for manufacturing the semiconductor device shown in FIG. 1, sequentially illustrating steps subsequent to the step shown in FIG. [Figure 5] FIG. 5 is a diagram showing an example in which the method for manufacturing a semiconductor device according to one embodiment of the present invention is applied to Chip-to-Wafer (C2W). DETAILED DESCRIPTION OF THE INVENTION

[0017] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In the following description, the same or equivalent parts will be denoted by the same reference numerals, and duplicate explanations will be omitted. Furthermore, unless otherwise specified, positional relationships such as up, down, left, and right will be based on the positional relationships shown in the drawings. Furthermore, the dimensional ratios of the drawings are not limited to those shown in the drawings.

[0018] (Configuration of semiconductor device) 1 is a cross-sectional view schematically illustrating an example of a semiconductor device manufactured by the manufacturing method according to the present embodiment. As shown in FIG. 1, the semiconductor device 1 is an example of a semiconductor package, and includes a first semiconductor chip 10 (first semiconductor substrate), a second semiconductor chip 20 (semiconductor chip), a pillar portion 30, a redistribution layer 40, a substrate 50, and a circuit board 60.

[0019] The first semiconductor chip 10 is a semiconductor chip such as an LSI (Large Scale Integrated Circuit) chip or a CMOS (Complementary Metal Oxide Semiconductor) sensor, and the second semiconductor chip 20 is mounted vertically (downward in the height direction) to form a three-dimensional mounting structure. The second semiconductor chip 20 is a semiconductor chip such as an LSI or memory, and is a chip component having a smaller area in a plan view than the first semiconductor chip 10. The second semiconductor chip 20 is bonded to the back surface of the first semiconductor chip 10 by chip-to-chip (C2C) bonding. The first semiconductor chip 10 and the second semiconductor chip 20 are finely bonded to each other by hybrid bonding, the details of which will be described later, with their respective terminal electrodes and surrounding insulating films firmly and without misalignment.

[0020] The pillar portion 30 is a connection portion in which a plurality of pillars 31 made of, for example, copper (Cu) are sealed with resin 32. The plurality of pillars 31 are conductive members extending from the upper surface to the lower surface of the pillar portion 30 and may have a cylindrical shape with a diameter of, for example, 3 μm to 20 μm (for example, a diameter of 5 μm) and may be arranged so that the center-to-center pitch between the pillars 31 is 15 μm or less. The plurality of pillars 31 flip-chip connect the lower terminal electrodes of the first semiconductor chip 10 to the upper terminal electrodes of the rewiring layer 40. By using the pillar portion 30, the semiconductor device 1 can form connection electrodes without using a technique called TMV (Through Mold Via), which involves drilling holes in a mold and soldering the connections. The pillar portion 30 has, for example, a thickness approximately the same as that of the second semiconductor chip 20 and is arranged on the lateral side of the second semiconductor chip 20 in the horizontal direction. In addition, instead of the pillar portion 30, this portion may be composed of multiple solder balls, and the solder balls may be used to electrically connect the lower terminal electrode of the first semiconductor chip 10 and the upper terminal electrode of the rewiring layer 40.

[0021] The rewiring layer 40 is a wiring layer having a terminal pitch conversion function, which is a function of the package substrate. It is a layer in which a rewiring pattern is formed using polyimide and copper wiring, etc., on the insulating film below the second semiconductor chip 20 and on the underside of the pillar portions 30. The rewiring layer 40 is formed with the first semiconductor chip 10 and the second semiconductor chip 20, etc., turned upside down (see FIG. 4(d)). The rewiring layer 40 electrically connects the terminal electrodes on the underside of the second semiconductor chip 20 and the terminal electrodes of the first semiconductor chip 10 via the pillar portions 30 to the terminal electrodes of the substrate 50. The terminal pitch of the substrate 50 is wider than the terminal pitch of the first semiconductor chip 10 (pillars 31) and the second semiconductor chip 20. Various electronic components 51 may be mounted on the substrate 50. If there is a large difference in the terminal pitch between the rewiring layer 40 and the substrate 50, an inorganic interposer, etc., may be used to electrically connect the rewiring layer 40 and the substrate 50.

[0022] The circuit board 60 is a substrate on which the first semiconductor chip 10 and the second semiconductor chip 20 are mounted, and has a plurality of through electrodes inside that are electrically connected to the substrate 50 that is connected to the first semiconductor chip 10, the second semiconductor chip 20, and electronic components 51. In the circuit board 60, these through electrodes electrically connect the terminal electrodes of the first semiconductor chip 10 and the second semiconductor chip to terminal electrodes 61 provided on the back surface of the circuit board 60.

[0023] (Method of manufacturing a semiconductor device) Next, a method for manufacturing the semiconductor device 1 will be described with reference to Fig. 2 to Fig. 4. Fig. 2 is a diagram sequentially showing a method for manufacturing the semiconductor device shown in Fig. 1. Fig. 3 is a diagram more specifically showing a bonding method (hybrid bonding) in the method for manufacturing the semiconductor device shown in Fig. 2. Fig. 4 is a diagram sequentially showing steps subsequent to the steps shown in Fig. 2 in the method for manufacturing the semiconductor device shown in Fig. 1.

[0024] The semiconductor device 1 can be manufactured, for example, through the following steps (a) to (p). (a) A step of preparing a first semiconductor substrate 100 corresponding to a first semiconductor chip 10. (b) A step of preparing a second semiconductor substrate 200 corresponding to the second semiconductor chip 20. (c) A step of polishing the first semiconductor substrate 100. (d) A step of polishing the second semiconductor substrate 200. (e) A step of dividing the second semiconductor substrate 200 into individual pieces to obtain a plurality of semiconductor chips 205. (f) A step of aligning the terminal electrodes 203 of each of the plurality of semiconductor chips 205 with the terminal electrodes 103 of the first semiconductor substrate 100. (g) A step of bonding the insulating film 102 of the first semiconductor substrate 100 and each insulating film portion 202b of the plurality of semiconductor chips 205 together (see FIG. 3(b)). (h) A step of bonding the terminal electrodes 103 of the first semiconductor substrate 100 to the terminal electrodes 203 of each of the plurality of semiconductor chips 205 (see FIG. 3(c)). (i) A step of forming a plurality of pillars 300 (corresponding to pillars 31) on the connection surface of the first semiconductor substrate 100 and between the plurality of semiconductor chips 205. (j) A step of molding a resin 301 onto the connection surface of the first semiconductor substrate 100 so as to cover the semiconductor chip 205 and the pillar 300, thereby obtaining a semi-finished product M1. (k) A step of grinding and thinning the upper part of the semi-finished product M1 molded in step (j) to obtain a semi-finished product M2. (m) A step of forming a wiring layer 400 corresponding to the rewiring layer 40 on the semi-finished product M2 thinned in the step (k). (n) A step of cutting the semi-finished product M3 on which the wiring layer 400 has been formed in the step (m) along the cutting lines A so as to obtain the individual semiconductor devices 1. (p) A step of inverting the semiconductor device 1a made into an individual semiconductor device in the step (n) and placing it on the substrate 50 and the circuit board 60 (see FIG. 1).

[0025] [Step (a) and Step (b)] Step (a) is a step of preparing a first semiconductor substrate 100, which is a silicon substrate on which integrated circuits composed of semiconductor elements and wiring connecting the elements are formed, corresponding to a plurality of first semiconductor chips 10. In step (a), as shown in FIG. 2(a), a plurality of terminal electrodes 103 (first electrodes) made of copper, aluminum, or the like are provided at predetermined intervals on one surface 101a of a first substrate body 101 made of silicon or the like, and an insulating film 102 (first insulating film) made of an organic material is also provided. The insulating film 102 may be provided on the one surface 101a of the first substrate body 101 before the plurality of terminal electrodes 103 are provided, or the insulating film 102 may be provided after the plurality of terminal electrodes 103 are provided on the one surface 101a of the first substrate body 101. Note that a predetermined interval is provided between the plurality of terminal electrodes 103 in order to form pillars 300 in a step described below, and another terminal electrode (not shown) connected to the pillars 300 is formed between the plurality of terminal electrodes 103.

[0026] Step (b) is a step of preparing a second semiconductor substrate 200, which is a silicon substrate on which integrated circuits made of semiconductor elements and wiring connecting them are formed, corresponding to a plurality of second semiconductor chips 20. In step (b), as shown in (a) of FIG. 2, a plurality of terminal electrodes 203 (a plurality of second electrodes) made of copper, aluminum, or the like are continuously provided on one surface 201a of a second substrate main body 201 made of silicon or the like, and an insulating film 202 (a second insulating film) made of an organic material is also provided. The insulating film 202 may be provided on the one surface 201a of the second substrate main body 201 before the plurality of terminal electrodes 203 are provided, or the insulating film 202 may be provided after the plurality of terminal electrodes 203 are provided on the one surface 201a of the second substrate main body 201.

[0027] As described above, the insulating films 102 and 202 used in steps (a) and (b) are made of an organic material. This organic material contains, for example, polyimide, a polyimide precursor (e.g., polyimide ester or polyamic acid), polyamideimide, benzocyclobutene (BCB), polybenzoxazole (PBO), or a PBO precursor, and has a lower elastic modulus than inorganic materials such as silicon dioxide (SiO2). The elastic modulus of the organic material making up the insulating films 102 and 202 is, for example, 7.0 GPa or less, preferably 5.0 GPa or less or 3.0 GPa or less, and more preferably 2.0 GPa or less or 1.5 GPa or less. Note that the elastic modulus here refers to Young's modulus.

[0028] Furthermore, the organic material that constitutes the insulating films 102 and 202 preferably has a thermal expansion coefficient of 70 ppm / k or less, and more preferably 50 ppm / k or less.

[0029] Furthermore, the organic material constituting the insulating films 102 and 202 may have a polishing rate that is five times or less than the polishing rate of the metal material (e.g., copper or aluminum) constituting the corresponding terminal electrode 103 or 203. For example, if the metal material constituting the terminal electrode 103 or 203 is copper and has a polishing rate of 50 nm / min, the polishing rate of the organic material constituting the insulating films 102 and 202 is preferably 200 nm / min or less (four times or less), more preferably 100 nm / min or less (two times or less), and even more preferably 50 nm / min or less (the same or less).

[0030] The organic material forming the insulating films 102 and 202 may be a photosensitive resin, a thermosetting non-conductive film (NCF), or a thermosetting resin. This organic material may be an underfill material. The organic material forming the insulating films 102 and 202 may also be a heat-resistant resin.

[0031] [Step (c) and step (d)] Step (c) is a step of polishing the first semiconductor substrate 100. In step (c), as shown in FIG. 3(a), the first surface 101a of the first semiconductor substrate 100 can be polished using a CMP (Chemical Mechanical Polishing) method so that the surfaces 103a of the terminal electrodes 103 are at the same level as or slightly lower (recessed) than the surface 102a of the insulating film 102. In step (c), the first semiconductor substrate 100 can also be polished by the CMP method under conditions that selectively and deeply polish the terminal electrodes 103 made of, for example, copper. In step (c), the surfaces 103a of the terminal electrodes 103 may be polished by the CMP method so that they are flush with the surface 102a of the insulating film 102.

[0032] Step (d) is a step of polishing the second semiconductor substrate 200. In step (d), as shown in FIG. 3A, the first surface 201a of the second semiconductor substrate 200 may be polished using the CMP method so that the surfaces 203a of the terminal electrodes 203 are at the same level as or slightly lower (recessed) than the surface 202a of the insulating film 202. In step (d), the second semiconductor substrate 200 is polished by the CMP method under conditions that selectively and deeply polish the terminal electrodes 203 made of, for example, copper. In step (d), the CMP method may be used to polish the surfaces 203a of the terminal electrodes 203 so that they are flush with the surface 202a of the insulating film 202.

[0033] In steps (c) and (d), the insulating film 102 may be polished so that the thickness of the insulating film 202 is the same as that of the insulating film 202. Alternatively, the insulating film 202 may be polished so that the thickness of the insulating film 202 is greater than that of the insulating film 102. On the other hand, the insulating film 202 may be polished so that the thickness of the insulating film 202 is less than that of the insulating film 102. When the insulating film 202 is thicker than that of the insulating film 102, the insulating film 202 can contain most of the foreign matter that adheres to the bonding interface during separation into semiconductor chips 205 or during chip mounting, thereby further reducing bonding defects. On the other hand, when the insulating film 202 is thinner than that of the insulating film 102, the height of the mounted semiconductor chip 205, i.e., the semiconductor device 1, can be reduced.

[0034] [Step (e)] Step (e) is a step of singulating the second semiconductor substrate 200 to obtain a plurality of semiconductor chips 205. In step (e), as shown in FIG. 2(b), the second semiconductor substrate 200 is singulated into a plurality of semiconductor chips 205 by cutting means such as dicing. When dicing the second semiconductor substrate 200, the insulating film 202 may be covered with a protective material or the like before being singulated. In step (e), the insulating film 202 of the second semiconductor substrate 200 is divided into insulating film portions 202b corresponding to each semiconductor chip 205. Note that, for example, plasma dicing, stealth dicing, or laser dicing can be used as a dicing method for singulating the second semiconductor substrate 200. Furthermore, a thin film such as an organic film that can be removed with water or TMAH, or a carbon film that can be removed with plasma, may be provided as a surface protective material for the second semiconductor substrate 200 during dicing.

[0035] [Process (f)] Step (f) is a step of aligning the terminal electrodes 203 of each of the multiple semiconductor chips 205 with the terminal electrodes 103 of the first semiconductor substrate 100. In step (f), as shown in (c) of Fig. 2, each semiconductor chip 205 is aligned so that the terminal electrodes 203 of each semiconductor chip 205 face the corresponding multiple terminal electrodes 103 of the first semiconductor substrate 100. For this alignment, an alignment mark or the like may be provided on the first semiconductor substrate 100.

[0036] [Process (g)] Step (g) is a step of bonding the insulating film 102 of the first semiconductor substrate 100 and each insulating film portion 202b of each of the multiple semiconductor chips 205 to each other. In step (g), after removing organic matter or metal oxide adhering to the surface of each semiconductor chip 205, the semiconductor chip 205 is aligned with the first semiconductor substrate 100 as shown in FIG. 2(c). After this is completed, the insulating film portion 202b of each of the multiple semiconductor chips 205 is bonded to the insulating film 102 of the first semiconductor substrate 100 by hybrid bonding (see FIG. 3(b)). At this time, the insulating film portions of the multiple semiconductor chips 205 and the insulating film 102 of the first semiconductor substrate 100 may be uniformly heated before bonding. The temperature difference between the semiconductor chips 205 and the first semiconductor substrate 100 during bonding is preferably, for example, 10°C or less. By such heat bonding at a uniform temperature, the insulating film 102 and the insulating film portion 202b are bonded to form an insulating bond portion S1, and the multiple semiconductor chips 205 are mechanically and firmly attached to the first semiconductor substrate 100. Furthermore, because the heat bonding is performed at a uniform temperature, misalignment at the bonding portion is unlikely to occur, allowing for highly accurate bonding. At this attachment stage, the terminal electrodes 103 of the first semiconductor substrate 100 and the terminal electrodes 203 of the semiconductor chip 205 are spaced apart from each other and are not connected (but are aligned). Note that the semiconductor chip 205 may be attached to the first semiconductor substrate 100 by other bonding methods, such as room temperature bonding.

[0037] [Process (h)] Step (h) is a step of bonding the terminal electrodes 103 of the first semiconductor substrate 100 to the terminal electrodes 203 of each of the multiple semiconductor chips 205. In step (h), as shown in FIG. 2(d), after the bonding in step (g) is completed, a predetermined amount of heat H and / or pressure is applied to bond the terminal electrodes 103 of the first semiconductor substrate 100 to each of the terminal electrodes 203 of the multiple semiconductor chips 205 by hybrid bonding (see FIG. 3(c)). When the terminal electrodes 103 and 203 are made of copper, the annealing temperature in step (g) is preferably 150°C or higher and 400°C or lower, and more preferably 200°C or higher and 300°C or lower. This bonding process forms an electrode bonding portion S2 where the terminal electrode 103 and the corresponding terminal electrode 203 are bonded, and the terminal electrodes 103 and 203 are firmly bonded mechanically and electrically. The electrode bonding in step (h) is carried out after the lamination in step (g), but may be carried out simultaneously with the lamination in step (g).

[0038] As a result of the above, multiple semiconductor chips 205 are electrically and mechanically mounted at predetermined positions with high precision on the first semiconductor substrate 100. Note that, for example, a reliability test (connection test, etc.) of the product may be performed at the stage of the semi-finished product shown in Fig. 2(d), and only non-defective products may be used in the subsequent steps. Next, an example of a method for manufacturing a semiconductor device using such a semi-finished product will be described with reference to Fig. 4.

[0039] [Step (i)] Step (i) is a step of forming a plurality of pillars 300 on the connection surface 100a of the first semiconductor substrate 100 and between a plurality of semiconductor chips 205. In step (i), as shown in FIG. 4A, a large number of pillars 300 made of, for example, copper are formed between the plurality of semiconductor chips 205. The pillars 300 can be formed, for example, from copper plating, conductive paste, or copper pins. One end of each pillar 300 is formed to connect to a terminal electrode of the first semiconductor substrate 100 that is not connected to the terminal electrode 203 of the semiconductor chip 205, and the other end extends upward. The pillars 300 have a diameter of, for example, 10 μm to 100 μm and a height of, for example, 10 μm to 1000 μm. Note that, for example, 1 to 10,000 pillars 300 may be provided between a pair of semiconductor chips 205.

[0040] [Process (j)] Step (j) is a step of molding a resin 301 onto the connection surface 100a of the first semiconductor substrate 100 so as to cover the semiconductor chips 205 and the pillars 300. In step (j), as shown in FIG. 4B, for example, epoxy resin or the like is molded to entirely cover the semiconductor chips 205 and the pillars 300. Examples of molding methods include compression molding or transfer molding, and laminating a film-like epoxy film. This resin molding fills the spaces between the pillars 300 and between the pillars 300 and the semiconductor chips 205 with resin. This forms a semi-finished product M1 filled with resin. A curing process may be performed after molding the epoxy resin or the like. Furthermore, when steps (i) and (j) are performed substantially simultaneously, i.e., when the pillars 300 are formed at the same time as the resin molding, the pillars may be formed using imprinting, which is a fine transfer technique, and a conductive paste or electrolytic plating.

[0041] [Process (k)] Step (k) is a step of grinding and thinning the semi-finished product M1, which is made up of the resin 301, the plurality of pillars 300, and the plurality of semiconductor chips 205 molded in step (j), to obtain a semi-finished product M2. In step (k), as shown in FIG. 4(c), the upper side of the semi-finished product M1 is polished with a grinder or the like to thin the resin-molded first semiconductor substrate 100 and the like, thereby obtaining a semi-finished product M2. By polishing in step (k), the thicknesses of the semiconductor chips 205, the pillars 300, and the resin 301 are thinned to, for example, about several tens of μm, and the semiconductor chip 205 has a shape corresponding to the second semiconductor chip 20, and the pillars 300 and the resin 301 have shapes corresponding to the pillar portions 30.

[0042] [Process (m)] Step (m) is a step of forming a wiring layer 400 corresponding to the rewiring layer 40 on the semi-finished product M2 thinned in step (k). In step (m), as shown in FIG. 4(d), a rewiring pattern is formed using polyimide and copper wiring or the like on the second semiconductor chip 20 and pillar portion 30 of the ground semi-finished product M2. This forms a semi-finished product M3 having a wiring structure in which the terminal pitch of the second semiconductor chip 20 and pillar portion 30 is widened.

[0043] [Step (n) and step (p)] Step (n) is a step of cutting the semi-finished product M3 on which the wiring layer 400 has been formed in step (m) along the cutting line A to obtain the individual semiconductor devices 1. In step (n), as shown in (d) of FIG. 4, the semiconductor device substrate is cut along the cutting line A by dicing or the like to obtain the individual semiconductor devices 1. Thereafter, in step (p), the semiconductor devices 1a separated in step (n) are inverted and placed on the substrate 50 and the circuit board 60 to obtain the multiple semiconductor devices 1 shown in FIG.

[0044] As described above, according to the semiconductor device manufacturing method of this embodiment, the insulating film 102 of the first semiconductor substrate 100 and the insulating film 202 (insulating film portion 202b) of the second semiconductor substrate 200 (semiconductor chip 205) are made of an organic material. Organic materials generally have a lower elastic modulus than inorganic materials. By using such a soft material for the insulating film in hybrid bonding, even if foreign particles generated during dicing when the second semiconductor substrate 200 is separated into semiconductor chips 205 adhere to the insulating film, the insulating film around the foreign particles can be easily deformed, and the foreign particles can be contained within the organic material without creating large voids in the insulating film. In other words, the insulating film containing an organic material can suppress the influence of foreign particles. Therefore, according to the manufacturing method of this embodiment, it is possible to reduce bonding defects while finely bonding the first semiconductor substrate 100 and the semiconductor chip 205. Note that if the organic material used for the insulating film is made of a material with a low elastic modulus or has a highly tough resin composition, damage to the semiconductor device 1 manufactured by the above manufacturing method can be more reliably prevented.

[0045] Furthermore, in the manufacturing method of a semiconductor device according to this embodiment, in the polishing steps (c) and (d), the one surface 101a side of the first semiconductor substrate 100 is polished using the CMP method so that each surface 103a of the plurality of terminal electrodes 103 is at the same height as the surface 102a of the insulating film 102 or is recessed relative to the surface 102a of the insulating film 102. Furthermore, the one surface 201a side of the second semiconductor substrate 200 is polished using the CMP method so that each surface 203a of the plurality of terminal electrodes 203 is at the same height as the surface 202a of the insulating film 202 or is recessed relative to the surface 202a of the insulating film 202. By performing such polishing, the step (g) of bonding the insulating film 102 of the first semiconductor substrate 100 and each insulating film portion 202b of the semiconductor chip 205 to each other can be more reliably performed, thereby preventing misalignment between electrodes bonded by hybrid bonding.

[0046] Furthermore, in the manufacturing method of the semiconductor device according to this embodiment, in the bonding step (g), the insulating film portion 202b of the semiconductor chip 205 is bonded to the first insulating film 102 of the first semiconductor substrate 100 at a temperature where the temperature difference between the semiconductor chip 205 and the first semiconductor substrate 100 is within 10°C, or at room temperature. By performing such temperature control, it is possible to bond the multiple semiconductor chips 205 to the first semiconductor substrate 100 while suppressing misalignment.

[0047] Furthermore, in the method for manufacturing a semiconductor device according to this embodiment, the modulus of elasticity of the organic material constituting the insulating film 102 and the insulating film 202 may be 7.0 GPa or less. In this case, even if foreign matter adheres to the bonding interface during singulation into semiconductor chips 205 or during chip mounting, the foreign matter can be contained within the organic material without further creating large voids, thereby further reducing bonding defects.

[0048] Furthermore, in the method for manufacturing a semiconductor device according to this embodiment, the thermal expansion coefficient of the organic material constituting the insulating film 102 and the insulating film 202 may be 70 ppm / k or less. In this case, the thermal expansion coefficient of the organic material constituting the insulating film becomes equal to or close to the thermal expansion coefficient of the terminal electrode 103 and the terminal electrode 203. Even if heat or the like is generated during use of the semiconductor device 1, the thermal expansion of the insulating layer and the terminal electrode becomes approximately the same, and damage to the semiconductor device 1 due to the difference in thermal expansion coefficient can be prevented.

[0049] Furthermore, in the method for manufacturing a semiconductor device according to this embodiment, the organic material contained in the insulating film 102 may have a polishing rate that is five times or less than the polishing rate of the metal material that constitutes the terminal electrode 103, and the organic material contained in the insulating film 202 may have a polishing rate that is five times or less than the polishing rate of the metal material that constitutes the terminal electrode 203. In this case, the steps (c) and (d) of polishing the insulating film and the terminal electrode are easier to perform, and the polishing steps (c) and (d) can be simplified.

[0050] Although one embodiment of the present invention has been described in detail above, the present invention is not limited to the above embodiment. For example, in the process shown in FIG. 4 , after the step (i) of forming the pillars 300, the step (j) of molding the resin 301 and the step (k) of grinding and thinning the resin 301 and the like are performed in this order. However, the step (j) of molding the resin 301 onto the connection surface of the first semiconductor substrate 100 may be performed first, followed by the step (k) of grinding and thinning the resin 301 to a predetermined thickness, and then the step (i) of forming the pillars 300. In this case, the work of grinding the pillars 300 can be reduced, and since the portions of the pillars 300 that need to be ground are no longer necessary, material costs can be reduced.

[0051] Although the above embodiment describes an example of C2C bonding, the present invention may also be applied to chip-to-wafer (C2W) bonding shown in FIG. 5. In C2W, a semiconductor wafer 410 (first semiconductor substrate) is prepared, which includes a substrate body 411 (first substrate body), an insulating film 412 (first insulating film) provided on one surface of the substrate body 411, and a plurality of terminal electrodes 413 (first electrodes). A semiconductor substrate (second semiconductor substrate) is also prepared, which includes a substrate body 421 (second substrate body), an insulating film portion 422 (second insulating film) provided on one surface of the substrate body 421, and a plurality of terminal electrodes 423 (second electrodes) before being singulated into a plurality of semiconductor chips 420. Then, one surface of the semiconductor wafer 410 and one surface of the second semiconductor substrate before being singulated into the semiconductor chips 420 are polished by CMP or the like, similar to the above steps (c) and (d). Thereafter, the second semiconductor substrate is subjected to a singulation process similar to that in step (e) to obtain a plurality of semiconductor chips 420.

[0052] Next, as shown in FIG. 5(a), the terminal electrodes 423 of the semiconductor chip 420 are aligned with the terminal electrodes 413 of the semiconductor wafer 410 (step (f)). Then, the insulating film 412 of the semiconductor wafer 410 and the insulating film portion 422 of the semiconductor chip 420 are attached to each other (step (g)), and the terminal electrodes 413 of the semiconductor wafer 410 and the terminal electrodes 423 of the semiconductor chip 420 are bonded to each other (step (h)), thereby obtaining the semi-finished product shown in FIG. 5(b). As a result, the insulating film 412 and the insulating film portion 422 are bonded to form an insulating bonding portion S3, and the semiconductor chip 420 is attached to the semiconductor wafer 410 mechanically firmly and with high precision. Furthermore, the terminal electrodes 413 and the corresponding terminal electrodes 423 are bonded to form an electrode bonding portion S4, and the terminal electrodes 413 and 423 are bonded to each other mechanically and electrically firmly.

[0053] 5(c) and 5(d), a plurality of semiconductor chips 420 are bonded to a semiconductor wafer 410 in a similar manner to obtain a semiconductor device 401. Note that the plurality of semiconductor chips 420 may be bonded to the semiconductor wafer 410 one by one by hybrid bonding, or may be bonded to the semiconductor wafer 410 collectively by hybrid bonding.

[0054] In the manufacturing method of semiconductor device 401, similar to the manufacturing method of semiconductor device 1 described above, the insulating film 412 of the semiconductor wafer 410 and the insulating film portion 422 of the semiconductor chip 420 are composed of an organic material. By using such a soft material for the insulating film in hybrid bonding, even if foreign particles generated during dicing during the process of dividing the semiconductor chips 420 adhere to the insulating film, the insulating film around the foreign particles easily deforms, allowing the foreign particles to be contained within the organic material without creating large voids in the insulating film. In other words, the insulating film containing the organic material can mitigate the effects of foreign particles. Therefore, similar to the C2C manufacturing method described above, the C2W manufacturing method can achieve fine bonding between the semiconductor wafer 410 and the semiconductor chips 420 while reducing bonding defects.

[0055] Furthermore, in the above-described method for manufacturing a semiconductor device, the insulating film 102 of the semiconductor substrate 110 and the insulating film 202 of the semiconductor chip 205 are made of organic materials, but these insulating films may contain inorganic materials in part. That is, as long as there is a part made of organic material that can contain the above-described foreign matter, the remaining part of the insulating film may be made of inorganic material. [Explanation of symbols]

[0056] 1, 1a, 401...semiconductor device, 10...first semiconductor chip, 20...second semiconductor chip, 30...pillar portion, 40...rewiring layer, 50...substrate, 60...circuit board, 61...terminal electrode, 100...first semiconductor substrate, 101...first substrate main body, 101a...one surface, 102...insulating film (first insulating film), 103...terminal electrode (first electrode), 103a...surface, 200...second semiconductor substrate, 201...second substrate main body, 201a...one surface, 202...insulating film (second insulating film), 203...terminal electrode (second electrode), 203a...surface, 205... Semiconductor chip, 300...pillar, 301...resin, 410...semiconductor wafer (first semiconductor substrate), 411...substrate body (first substrate body), 412...insulating film (first insulating film), 413...terminal electrode (first electrode), 420...semiconductor chip (second semiconductor substrate), 421...substrate body (second substrate body), 422...insulating film portion (second insulating film), 423...terminal electrode (second electrode), A...cutting line, H...heat, M1 to M3...semi-finished product, S1...insulating junction portion, S2...electrode junction portion, S3...insulating junction portion, S4...electrode junction portion.

Claims

1. providing a first semiconductor substrate having a first insulating film and a first electrode; providing a second semiconductor substrate having a second insulating film and a plurality of second electrodes; a step of dividing the second semiconductor substrate into individual semiconductor chips, each of which includes an insulating film portion corresponding to the second insulating film and at least one of the second electrodes; a step of bonding the first insulating film of the first semiconductor substrate and the insulating film portion of the semiconductor chip together; directly bonding the first electrode of the first semiconductor substrate to the second electrode of the semiconductor chip; at least one of the first insulating film and the second insulating film contains an organic material; A method for manufacturing a semiconductor device.

2. a first insulating film and a second insulating film each containing an inorganic material; The method for manufacturing a semiconductor device according to claim 1 .

3. After the first insulating film and the insulating film portion are bonded to each other, the first electrode and the second electrode are directly bonded to each other. The method for manufacturing a semiconductor device according to claim 1 or 2.

4. Both the first electrode and the second electrode are made of copper, and copper electrodes are bonded to each other. The method for manufacturing a semiconductor device according to any one of claims 1 to 3.

5. the modulus of elasticity of the organic material contained in at least one of the first insulating film and the second insulating film is 7.0 GPa or less; The method for manufacturing a semiconductor device according to any one of claims 1 to 4.

6. the thermal expansion coefficient of the organic material contained in at least one of the first insulating film and the second insulating film is 70 ppm / k or less; The method for manufacturing a semiconductor device according to any one of claims 1 to 5.

7. the organic material contained in at least one of the first insulating film and the second insulating film includes polyimide, a polyimide precursor, polyamideimide, benzocyclobutene (BCB), polybenzoxazole (PBO), a PBO precursor, a photosensitive resin, a thermosetting non-conductive film, or a thermosetting resin; The method for manufacturing a semiconductor device according to any one of claims 1 to 6.

8. a step of sealing the semiconductor chip with resin; grinding the encapsulated resin and the semiconductor chip; forming a wiring layer on the ground surface of the semiconductor chip; The method for manufacturing a semiconductor device according to any one of claims 1 to 7.

9. The method further includes a step of cutting a semi-finished product in which the plurality of semiconductor chips are attached to the first semiconductor substrate to obtain a plurality of semiconductor devices, each of which includes at least one first semiconductor chip included in the first semiconductor substrate and one second semiconductor chip that is the semiconductor chip included in the second semiconductor substrate. The method for manufacturing a semiconductor device according to any one of claims 1 to 8.

10. 10. The method for manufacturing a semiconductor device according to claim 1, wherein an organic material is used as at least one of the first insulating film and the second insulating film.

11. The organic material according to claim 10 , wherein the organic material has a film shape.

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