Information processing system, program and information processing method

Abstract

To improve power saving effect compared to loading the entire operating system (OS) running on a single processor into one volatile storage device.SOLUTION: In a controller 100, an OS is divided into a core layer OS module that detects an IO interrupt, a DD layer OS module that performs packet filtering processing, and a real OS layer OS module that processes packet data. The core layer OS module is loaded into an SRAM 20. A DRAM 10 is divided into a divided area 10a into which the DD layer OS module individually subjected to power supply control is loaded, and a normal area 10b into which the real OS layer OS module is loaded. When a CPU transitions to a power-saving mode, the whole performs self-refresh operation. When the DD layer OS module is needed, the refresh operation is released only for the divided area 10a. Only when the real OS layer OS module is needed, the refresh operation of the normal area 10b is released.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to an information processing system, a program, and an information processing method. [Background technology]

[0002] Conventionally, many multifunction peripherals have a function that automatically switches to a power-saving mode, such as a power-saving mode or a sleep mode, to reduce power consumption if the peripheral remains inactive for a predetermined period of time during normal operation. That is, the multifunction peripheral has a power-saving mode that operates in a power-saving state separate from the normal mode during normal operation. When the user operates the operation panel while the multifunction peripheral is in the power-saving mode, the multifunction peripheral automatically returns from the power-saving mode and returns to the normal state in which the multifunction peripheral can be used.

[0003] Incidentally, a multifunction peripheral may be requested to check the status of the multifunction peripheral or to perform processing such as printing via a network from an information processing device such as a personal computer (hereinafter referred to as "PC") For this reason, even in a power saving state, it is necessary for the multifunction peripheral to respond to requests via the network, and various techniques for this purpose have been proposed.

[0004] For example, Patent Document 1 proposes an image forming apparatus that is capable of returning a status message with low power consumption and at low cost even when in a power-saving state.

[0005] FIG. 6 is a schematic block diagram showing the main components of a controller 200 equipped with multiple CPUs, as described in Patent Document 1. The controller 200 includes a main CPU 202, a storage 4, a boot ROM 6, a sub-CPU 204, a DRAM power-saving control function 206, a DRAM 10, and an SRAM 20, all of which are connected to a control line 8. The DRAM 10 is connected to the control line 8 via the DRAM power-saving control function 206. The main CPU 202 performs overall control of the image forming apparatus in normal mode. The sub-CPU 204 does not employ more complex logic than the main CPU 202 and has a smaller memory capacity, allowing it to operate with less power consumption. When this conventional controller 200 transitions to power-saving mode, only the sub-CPU 204 of the multiple CPUs is energized to perform processes such as status monitoring, thereby achieving both external response and power saving. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Patent No. 444032 specification [Patent Document 2] Japanese Patent Application Publication No. 2018-061284 Summary of the Invention [Problem to be solved by the invention]

[0007] If multiple processors are used to achieve both external response and power saving, the hardware and software configuration will become complex in order to achieve cooperation between the processors, so if possible, it is desirable to configure it with a single processor.

[0008] On the other hand, if the entire operating system is loaded onto a single volatile memory device when configured with a single processor, power must continue to be supplied to the entire volatile memory device even when the system enters power-saving mode, and it is not possible to reduce the power supplied to the volatile memory device.

[0009] The present invention aims to improve power saving effects compared to loading the entire operating system running on a single processor into one volatile storage device. [Means for solving the problem]

[0010] The information processing system of the present invention comprises a processor, a volatile first storage device that does not lose data by remaining powered even in power saving mode, and volatile second and third storage devices that are subject to refresh control in power saving mode, and the processor, at startup, loads into the first storage device a first module that has the function of detecting an interrupt due to data reception, among modules that are divided into multiple parts according to the functions of the operating system, loads into the second storage device a second module that has the function of controlling communication between hardware and software in response to a request from the first module, and loads into the third storage device a third module that has the function of processing the data or running an application for processing the data in response to a request from the second module, refreshes the second and third storage devices in power saving mode, and when the interrupt is detected by the first module in power saving mode, cancels the refresh of the second and third storage devices into which the module necessary for processing the data is loaded.

[0011] Furthermore, when the first module detects the interrupt during power saving mode, the processor cancels the refresh of the second storage device if it determines that the second module is necessary to process the data, and cancels the refresh of the third storage device if the second module determines that the third module is necessary to process the data.

[0012] The processor is also characterized in that, at startup, it loads the application into the third storage device and runs the application that is determined by the third module to need to be run.

[0013] The first module includes a kernel, the second module includes a device driver, and the third module includes modules of the operating system excluding the kernel and the device driver.

[0014] The second storage device and the third storage device are formed by dividing one DRAM into two areas, and the processor controls refresh for each of the areas.

[0015] The processor also refreshes the DRAM in power saving mode, and when the first module detects the interrupt in power saving mode, if it determines that the second module is necessary to process the data, it cancels the refresh of only the area of ​​the DRAM where the second module is loaded.

[0016] The program of the present invention enables a computer having a processor, a volatile first storage device that does not lose data when powered even in power saving mode, and volatile second and third storage devices that are subject to refresh control in power saving mode to realize the following functions on startup: a function of loading into the first storage device a first module that has the function of detecting an interrupt due to data reception, among modules that are divided into multiple parts according to the functions of the operating system; a function of loading into the second storage device a second module that has the function of controlling communication between hardware and software in response to a request from the first module; a function of loading into the third storage device a third module that has the function of processing the data or running an application for processing the data in response to a request from the second module; a function of refreshing the second and third storage devices in power saving mode; and a function of canceling the refresh of the second and third storage devices into which the module necessary for processing the data is loaded when the interrupt is detected by the first module in power saving mode.

[0017] The information processing method of the present invention is characterized in that a processor provided in an information processing system includes a volatile first storage device that does not lose data when powered on even in power saving mode, and volatile second and third storage devices that are subject to refresh control in power saving mode, and at startup, loads into the first storage device a first module that has the function of detecting an interrupt due to data reception, among modules formed by dividing into multiple parts according to the functions of the operating system, loads into the second storage device a second module that has the function of controlling communication between hardware and software in response to a request from the first module, loads into the third storage device a third module that has the function of processing the data or running an application for processing the data in response to a request from the second module, refreshes the second storage device and the third storage device in power saving mode, and when the interrupt is detected by the first module in power saving mode, cancels the refresh of the second storage device and the third storage device into which the module necessary for processing the data is loaded. [Effects of the Invention]

[0018] According to the invention as set forth in claim 1, it is possible to improve the power saving effect compared to when the entire operating system running on a single processor is loaded into one volatile storage device.

[0019] According to the invention as set forth in claim 2, the power saving state of the storage device can be gradually released.

[0020] According to the invention as set forth in claim 3, desired processing can be performed on received data.

[0021] According to the invention as set forth in claim 4, it is possible to operate in order only the part of the operating system that is necessary to process data received by an interrupt.

[0022] According to the invention as set forth in claim 5, only the minimum number of modules required can be operated in the power saving mode.

[0023] According to the sixth aspect of the present invention, the second module can be operated with only the area where the second module is loaded being subject to cancellation of refresh.

[0024] According to the seventh aspect of the present invention, it is possible to improve the power saving effect compared to the case where the entire operating system running on a single processor is loaded into one volatile storage device.

[0025] According to the invention as set forth in claim 8, it is possible to improve the power saving effect compared to the case where the entire operating system running on a single processor is loaded into one volatile storage device. [Brief explanation of the drawings]

[0026] [Figure 1] 1 is a schematic block diagram showing a hardware configuration of an image forming apparatus according to an embodiment of the present invention; [Figure 2] FIG. 2 is a block diagram showing a controller according to the present embodiment. [Figure 3] 10 is a flowchart showing a startup process according to the present embodiment. [Figure 4] FIG. 2 is a diagram showing the relationship between a physical address space and a virtual address space in the present embodiment. [Figure 5A] 10 is a flowchart showing a process during operation in a power saving mode in the present embodiment. [Figure 5B] 5B is a flowchart continuing from FIG. 5A. [Figure 6] FIG. 1 is a schematic block diagram showing the main parts of a conventional controller equipped with multiple CPUs. DETAILED DESCRIPTION OF THE INVENTION

[0027] Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

[0028] 1 is a schematic block diagram showing the hardware configuration of an image forming apparatus 1 according to the present embodiment. The image forming apparatus 1 is a multifunction peripheral equipped with various functions such as a printing function, a copying function, and a scanning function, and is a device with a built-in computer. The image forming apparatus 1 has a controller 100, an operation panel 102, a scanner 103, a printer 104, and a network interface (IF) 105. The controller 100 is a control board corresponding to the computer.

[0029] Fig. 2 is a block diagram showing the configuration of the controller 100 according to this embodiment, and corresponds to the controller 200 shown in Fig. 6. Note that the same components as those in the controller 200 are denoted by the same reference numerals.

[0030] The controller 100 in this embodiment is a control board that mounts a CPU 2, a storage 4, a boot ROM 6, a DRAM power saving control function 12, a DRAM 10, and an SRAM 20, and each is connected to a control line 8. The DRAM 10 is connected to the control line 8 via the DRAM power saving control function 12. Components that are not used in the description of this embodiment are omitted from FIG. 2.

[0031] The CPU 2 controls the operation of various mechanisms installed in the image forming apparatus 1, such as the scanner 103 and printer 104, in accordance with an operating system (hereinafter referred to as "OS") or various libraries and applications (hereinafter simply referred to as "apps") loaded into the DRAM 10 or SRAM 20. The storage 4 is a storage means for storing software such as applications. The boot ROM 6 is a storage means for storing computer programs that are automatically executed immediately after the computer is started up.

[0032] DRAM (Dynamic RAM) 10 is a volatile semiconductor memory device, and in this embodiment, it is divided into a second memory device and a third memory device and controlled by a DRAM power saving control function 12. In this embodiment, the memory area corresponding to the second memory device is an area formed by dividing DRAM 10, and therefore will be referred to as a "divided area" 10a in the following description. On the other hand, in this embodiment, the memory area corresponding to the third memory device is a memory area other than divided area 10a divided from DRAM 10, and is an area into which applications and the like are normally loaded, and therefore will be referred to as a "normal area" 10b in the following description.

[0033] The DRAM 10 of this embodiment can operate in a self-refresh mode. "Self-refresh mode" is a method in which a refresh command signal is automatically generated inside the DRAM 10 when the DRAM 10 is not operating, and a refresh operation is performed. "Refresh" refers to the operation of periodically rewriting data while the DRAM 10 is operating by periodically replenishing charge in the memory cells. Refreshing preserves data in the DRAM 10 without erasing it, and can also be expected to have a power-saving effect. When the DRAM 10 of this embodiment transitions to a power-saving mode, power is no longer supplied, and therefore the DRAM 10 is subject to refresh control in the power-saving mode.

[0034] The SRAM (Static RAM) 20 is a volatile semiconductor memory device, and in this embodiment, it is provided as a first memory device that remains energized even in the power saving mode so that data is not lost even without performing a refresh operation. Note that, although the present embodiment uses the SRAM 20 as the first memory device, the DRAM 10 can also be used if it remains energized in the power saving mode in the same way as in the normal mode.

[0035] Incidentally, the "power saving mode" is an operation mode different from the normal mode, which is a normal state in which devices such as the scanner 103 mounted on the image forming apparatus 1 are operable, and is an operation mode in which the image forming apparatus 1 enters a power saving state by stopping the supply of power to devices such as the scanner 103. In the power saving mode of this embodiment, the supply of power to the DRAM 10, which will be described later, is controlled. If the image forming apparatus 1 remains inactive for a predetermined period of time, the operation mode of the image forming apparatus 1 automatically transitions from the normal mode to the power saving mode. This limits the operation of functions such as the scanner function provided by the image forming apparatus 1, but reduces power consumption.

[0036] The DRAM power saving control function 12 is a means for realizing, by hardware or software, a function for controlling power saving in the DRAM 10, which is a feature of this embodiment. The DRAM power saving control function 12 controls the power supply and self-refresh operation for each memory area formed by dividing the DRAM 10. In this embodiment, the divided area 10a and the normal area 10b can be controlled separately.

[0037] When the image forming apparatus 1 is started, the OS is loaded into a volatile storage device. In this embodiment, a single OS is divided into multiple modules according to the functions of the OS. Each module formed by the division is loaded into the DRAM 10 or the SRAM 20. Specifically, the OS is divided into three layers of modules: a core layer, a DD (Device Driver) layer, and an actual OS layer, as shown in FIG. 2.

[0038] The core layer OS module is a module that includes the kernel, which is the core of the OS, and is the first module with the function of detecting interrupts caused by receiving data. For example, it detects an IO interrupt that occurs when the reception of a packet via a network is detected as a trigger. To enable interrupt detection even in power-saving mode, the core layer OS module is loaded into SRAM 20, which is available even in power-saving mode. Although the modules in the three layers may work together to perform kernel processing in the OS, the core layer OS module performs the core function of detecting IO interrupts, which is the core of the OS.

[0039] The DD layer OS module is a second module with a device driver function that controls communication between hardware and software in response to requests from the core layer OS module. For example, the DD layer OS module receives packets received by the core layer OS module and performs packet filtering processing. "Packet filtering processing" is one of the network control functions of communication devices and computers, and refers to the process of accepting or discarding data (i.e., packets) received from outside according to certain criteria set by an administrator or other person. The DD layer OS module is loaded into the partitioned area 10a.

[0040] The actual OS layer OS module is a third module that has the function of processing packet data generated by the DD layer OS module performing packet filtering processing in response to a request from the DD layer OS module, or running an application for processing the packet data. The actual OS layer OS module can also be said to be a module that realizes functions of the OS other than those possessed by the core layer OS module and the DD layer OS module.

[0041] In this embodiment, the description will be given assuming that the open source OS Linux (registered trademark) is used as the OS, but it is not necessary to be limited to Linux.

[0042] As described above, in this embodiment, a single OS is divided into a core layer OS module, a DD layer OS module, and a real OS layer OS module, which are loaded into the SRAM 20, the divided area 10a, and the normal area 10b, respectively, when the image forming apparatus 1 is started. In addition, software other than the OS, for example, various libraries and applications as shown in FIG. 2, are loaded into the normal area 10b and executed.

[0043] The OS used in this embodiment is naturally pre-installed on the image forming device 1, but it can also be provided via a communication means or stored on a computer-readable recording medium such as a USB memory.

[0044] Next, the operation of this embodiment will be described. First, the operation at the time of startup of image forming apparatus 1 will be described with reference to the flowchart shown in FIG.

[0045] When the image forming apparatus 1 is started, the boot loader stored in the boot ROM 6 loads the OS stored in the storage 4 into memory. That is, the boot loader loads the core layer OS module into the SRAM 20 (step S101), the DD layer OS module into the divided area 10a (step S102), and the real OS layer OS module into the normal area 10b (step S103). The boot loader knows the location address of each OS module in the physical address, and loads the OS module into the address location specified by the location address.

[0046] Next, the boot loader maps each OS module into the virtual address space (step S104). Symbols such as functions and variables in each OS module are linked so that they can be referenced and called. Once the OS loading is complete, the OS initializes the system by mapping various libraries and applications into the virtual address space (step S105). The concept of mapping into this virtual address space will be explained using FIG. 4.

[0047] In Figure 4, the left side of the drawing is the same as the DRAM 10 and SRAM 20 shown in Figure 2 and corresponds to the so-called physical address space. On the other hand, the right side of the drawing corresponds to the virtual address space. The size of the virtual address space depends on the amount of information that the CPU 2 can handle. For example, if the amount of information is expressed in 32 bits, the size of the virtual address space is 4 GB. As indicated by the dashed arrow in Figure 4, the boot loader maps the core layer OS module, DD layer OS module, and real OS layer OS module in that order from the top address of the virtual address space 30. Next, the boot loader maps various libraries and applications as necessary.

[0048] As described above, when the image forming apparatus 1 is powered on and started up, each OS module that constitutes the OS is loaded into the divided area 10a of the SRAM 20 and the DRAM 10, and into the normal area 10b of the DRAM 10, and is also mapped into the virtual address space. Then, the image forming apparatus 1 starts operating in the normal mode.

[0049] Subsequently, when a predetermined condition for transitioning to the power-saving mode is met, such as when the image forming apparatus 1 receives no external input via the network for a certain period of time, the image forming apparatus 1 transitions from the normal mode to the power-saving mode. At this time, the DRAM power-saving control function 12 performs a self-refresh operation on all areas of the DRAM 10, i.e., both the partitioned area 10a and the normal area 10b. As a result, the DRAM 10 is no longer powered when the image forming apparatus 1 transitions to the power-saving mode, so the DD layer OS module and the real OS layer OS module are rendered inoperable. Meanwhile, the SRAM 2 remains powered. This allows the core layer OS module to remain capable of responding to data reception interrupts from the outside via the network.

[0050] According to this embodiment, the power supply to the DRAM 10 can be stopped, and therefore the power saving effect can be increased accordingly.

[0051] The operation of the controller 100 in the power saving mode will be described below with reference to the flowcharts shown in FIGS. 5A and 5B.

[0052] As described above, the core layer OS module is loaded into SRAM 20, and therefore is capable of responding to data reception interrupts (hereinafter also referred to as "IO interrupts") from outside via a network even in power saving mode. An IO interrupt is detected, for example, by hardware, which notifies the core layer OS module of the occurrence of the IO interrupt. That is, the core layer OS module is in a waiting state until the IO interrupt occurs (N in step S121). Then, upon the occurrence of the IO interrupt (Y in step S121), the core layer OS module receives a notification from the hardware (step S122) and detects the interrupt due to data reception. Here, a portion of the data received by the IO interrupt, i.e., a packet, is stored in a buffer in SRAM 20. Next, the core layer OS module identifies the cause of the IO interrupt (step S123). This identification method may be the same as in the past.

[0053] If it is determined that the core layer OS module can handle the IO interrupt (Y in step S124), the core layer OS module sends a response such as an ACK to the packet sender (step S125). Then, the controller 100 goes to step 121 and returns to the state of waiting for an IO interrupt.

[0054] Thus, according to this embodiment, the controller 100 can respond to data reception interrupts even when operating in power saving mode, and can therefore receive packets sent from the outside without missing any.

[0055] On the other hand, if it is determined that the core layer OS module cannot complete the response to the IO interrupt that occurred (N in step S124), the core layer OS module then executes packet reception processing to receive all packets that make up the data (step S126). Furthermore, the DRAM power-saving control function 12 stops the refresh operation in the divided area 10a in response to an instruction from the core layer OS module and releases the refresh state (step S127). This causes the DD layer OS module loaded in the divided area 10a to return from an inoperable state to an operable normal state. The core layer OS module then passes the received packet to the DD layer OS module and requests packet filtering processing (step S128). In response to this request, the DD layer OS module performs packet filtering processing and generates data (step S129). For example, a device driver of the network interface 105 analyzes packets received via the network and generates received data.

[0056] The DD layer OS module determines whether it is necessary to return the real OS layer OS module, for example, because an application needs to be used when processing the generated received data. This is similar to the determination made by the core layer OS module in step S124, and can also be said to be a determination as to whether the DD layer OS module can complete the process for the generated received data.

[0057] Here, if it is determined that the restoration of the real OS layer OS module is not necessary (N in step S130), the DD layer OS module responds with an ACK or the like to the packet sender (step S131), and notifies the core layer OS module that processing in the DD layer OS module is complete (step S132). By receiving the notification from the DD layer OS module, the core layer OS module can determine that operation in the DD layer OS module is no longer necessary, and therefore causes the DRAM power saving control function 12 to perform a self-refresh operation on the divided area 10a of the DRAM 10. That is, the DD layer OS module transitions to a self-refresh state and enters a power saving state (step S133).

[0058] On the other hand, if it is determined that the actual OS layer OS module needs to be restored (Y in step S130), the DRAM power saving control function 12 stops the refresh operation in the normal area 10b in response to an instruction from the DRAM layer OS module, and releases the refresh state (step S134). That is, when it becomes necessary to restore the actual OS layer OS module, the power saving state of the entire DRAM 10 is released.

[0059] When the power saving state is released, the real OS layer OS module loaded in the normal area 10b returns from an inoperable state to an operable normal state. Then, the DD layer OS module passes the generated data to the real OS layer OS module and notifies it to perform data processing (step S135). In response to this notification, the real OS layer OS module executes kernel processing in the real OS layer OS module (step S136). In the kernel processing in the real OS layer OS module, if an application is required for data processing, the application determined to be required for that operation is identified, and performs tasks such as allocating virtual address space and scheduling threads. Then, the real OS layer OS module notifies the application that should perform data processing (step S137). The notified application starts operating under the operational control of the real OS layer OS module and performs the specified data processing on the data.

[0060] When the real OS layer OS module is in an operable state, power is supplied to the entire DRAM 10 in addition to the SRAM 20, so the power saving state in the controller 100 is canceled and the controller 100 operates in a normal state. Therefore, the power saving mode processing ends.

[0061] As described above, according to this embodiment, when an IO interrupt is detected by the core layer OS module during power saving mode, the refresh of the divided area 10a or the normal area 10b, into which a module necessary for processing data consisting of received packets is loaded, is canceled. Specifically, when the core layer OS module determines that the DD layer OS module is necessary for data processing, the refresh of the divided area 10a is canceled. Then, when the DD layer OS module determines that the real OS layer OS module is necessary for data processing, the refresh of the normal area 10b is canceled. In this way, in this embodiment, the power saving effect is improved by making only the storage areas 20, 10a, and 10b into which the necessary OS modules are loaded operable.

[0062] According to this embodiment, a single OS is used, which simplifies the software configuration, and since the image forming device 1 only needs to be equipped with a single CPU 2 to operate it, the occurrence of packet loss can be reduced.

[0063] In this embodiment, the DRAM 10 is divided, and the DD layer OS module is loaded into the divided area 10a formed by the division. If the SRAM 20 has a sufficient storage area capacity, the DD layer OS module may be loaded into the SRAM 20.

[0064] In the above description, the real OS layer OS module is loaded into the normal area 10b of the DRAM 10 together with various libraries and applications. However, the area other than the divided area 10a of the DRAM 10 may be subdivided, and the real OS layer OS module may be loaded into a divided area different from the various libraries and applications. In other words, the DRAM 10 may be divided into three or more areas, and the software to be loaded into the normal area 10b may be classified according to function, etc., and the classified software may be loaded into each of the storage areas formed by the subdivided area.

[0065] Although the "information processing system" in this embodiment has been described as being configured by a single image forming apparatus 1 as an example, it may also be configured by an information processing apparatus such as a PC.

[0066] In the above embodiments, the term "processor" refers to a processor in a broad sense, and includes general-purpose processors (e.g., CPU: Central Processing Unit, etc.) and dedicated processors (e.g., GPU: Graphics Processing Unit, ASIC: Application Specific Integrated Circuit, FPGA: Field Programmable Gate Array, programmable logic device, etc.).

[0067] (Addendum) (((1))) a processor; a volatile first storage device that remains powered even in a power saving mode so that data is not lost; a volatile second storage device and a volatile third storage device that are subject to refresh control in a power saving mode; Equipped with The processor: At startup, loading a first module having a function of detecting an interrupt due to data reception into the first storage device, among modules formed by dividing the operating system into a plurality of modules according to the functions of the operating system; loading a second module into the second storage device, the second module having a function of controlling communication between hardware and software in response to a request from the first module; loading a third module into the third storage device, the third module having a function of processing the data or running an application for processing the data in response to a request from the second module; In a power saving mode, the second storage device and the third storage device are refreshed; When the interrupt is detected by the first module during the power saving mode, the refresh of one of the second storage device and the third storage device in which a module necessary for processing the data is loaded is canceled. An information processing system comprising: (((2))) The processor: When the interrupt is detected by the first module during a power saving mode, the refresh of the second storage device is cancelled if the second module determines that the interrupt is necessary for processing the data; canceling the refresh of the third storage device when the second module determines that the third module is necessary for processing the data; The information processing system according to (((1))) is characterized in that: (((3))) The processor: At startup, loading the application into the third storage device; running the application determined by the third module to require execution; 1. The information processing system according to claim 1, wherein the information processing system comprises: (((4))) the first module includes a kernel; the second module includes a device driver; the third module includes modules of the operating system excluding a kernel and a device driver; 1. An information processing system according to any one of ((1))) to (((3))). (((5))) the second storage device and the third storage device are formed by dividing one DRAM into two areas, the processor controls refresh for each of the areas; 1. An information processing system according to any one of ((1))) to (((4))). (((6))) The processor refreshes the DRAM in a power saving mode, When the first module detects the interrupt during the power saving mode, if it determines that the second module is necessary for processing the data, it cancels refresh only in the area of ​​the DRAM where the second module is loaded. The information processing system according to (((5))) is characterized in that: (((7))) a processor; a volatile first storage device that remains powered even in a power saving mode so that data is not lost; a volatile second storage device and a volatile third storage device that are subject to refresh control in a power saving mode; A computer comprising: At startup, a function of loading a first module having a function of detecting an interrupt due to data reception, among a plurality of modules formed by dividing the operating system into a plurality of modules according to the functions of the operating system, into the first storage device; a function of loading a second module into the second storage device, the second module having a function of controlling communication between hardware and software in response to a request from the first module; a function of loading a third module into the third storage device, the third module having a function of processing the data or running an application for processing the data in response to a request from the second module; a function of refreshing the second storage device and the third storage device in a power saving mode; a function of canceling refresh of one of the second storage device and the third storage device in which a module necessary for processing the data is loaded when the interrupt is detected by the first module during a power saving mode; A program to achieve this. (((8))) The information processing system includes a processor that includes a volatile first storage device that is powered on even in a power saving mode so that data is not lost, and volatile second and third storage devices that are subject to refresh control in the power saving mode. At startup, loading a first module having a function of detecting an interrupt due to data reception into the first storage device, among modules formed by dividing the operating system into a plurality of modules according to the functions of the operating system; loading a second module into the second storage device, the second module having a function of controlling communication between hardware and software in response to a request from the first module; loading a third module into the third storage device, the third module having a function of processing the data or running an application for processing the data in response to a request from the second module; In a power saving mode, the second storage device and the third storage device are refreshed; When the interrupt is detected by the first module during the power saving mode, the refresh of one of the second storage device and the third storage device in which a module necessary for processing the data is loaded is canceled. An information processing method comprising:

[0068] According to the invention described in (((1))), it is possible to improve the power saving effect compared to when the entire operating system running on a single processor is loaded into one volatile storage device. According to the invention described in (((2))), the power saving state of the storage device can be gradually released. According to the invention described in (((3))), desired processing can be performed on received data. According to the invention described in (((4))), it is possible to operate in order only the part of the operating system that is necessary to process data received by an interrupt. According to the invention described in (((5))), only the minimum number of modules required can be operated in the power saving mode. According to the invention described in (((6))), the second module can be operated with only the area where the second module is loaded as a target for canceling refresh. According to the invention described in (((7))), it is possible to improve the power saving effect compared to when the entire operating system running on a single processor is loaded into one volatile storage device. According to the invention described in (((8))), it is possible to improve the power saving effect compared to when the entire operating system running on a single processor is loaded into one volatile storage device. [Explanation of symbols]

[0069] 1 image forming device, 2 CPU, 4 storage, 6 boot ROM, 8 control line, 10 DRAM, 10a divided area, 10b normal area, 12 DRAM power saving control function, 20 SRAM, 30 virtual address space, 100 controller, 102 operation panel, 103 scanner, 104 printer, 105 network interface (IF).

Claims

1. a processor; a volatile first storage device that is powered on even in a power saving mode so that data is not lost; a volatile second storage device and a volatile third storage device that are subject to refresh control in a power saving mode; Equipped with The processor: At startup, loading a first module having a function of detecting an interrupt due to data reception into the first storage device, among modules formed by dividing the operating system into a plurality of modules according to the functions of the operating system; loading a second module into the second storage device, the second module having a function of controlling communication between hardware and software in response to a request from the first module; loading a third module into the third storage device, the third module having a function of processing the data or running an application for processing the data in response to a request from the second module; In a power saving mode, the second storage device and the third storage device are refreshed; When the interrupt is detected by the first module during the power saving mode, the refresh of one of the second storage device and the third storage device in which a module necessary for processing the data is loaded is canceled. An information processing system comprising:

2. The processor: When the first module detects the interrupt during the power saving mode, the first module cancels the refresh of the second storage device if it determines that the second module is necessary for processing the data; canceling the refresh of the third storage device when the second module determines that the third module is necessary for processing the data; 2. The information processing system according to claim 1, wherein:

3. The processor: At startup, loading the application into the third storage device; running the application determined by the third module to require execution; 3. The information processing system according to claim 2.

4. the first module includes a kernel; the second module includes a device driver; the third module includes modules of an operating system excluding a kernel and a device driver; 2. The information processing system according to claim 1, wherein:

5. the second memory device and the third memory device are formed by dividing one DRAM into two areas, the processor controls refresh for each of the areas; 2. The information processing system according to claim 1, wherein:

6. The processor refreshes the DRAM in a power saving mode, When the first module detects the interrupt during the power saving mode, if it determines that the second module is necessary for processing the data, it cancels refresh only in the area of ​​the DRAM where the second module is loaded.

6. The information processing system according to claim 5.

7. a processor; a volatile first storage device that is powered on even in a power saving mode so that data is not lost; a volatile second storage device and a volatile third storage device that are subject to refresh control in a power saving mode; A computer comprising: At startup, a function of loading a first module having a function of detecting an interrupt due to reception of data, among a plurality of modules formed by dividing the operating system into a plurality of modules according to the functions of the operating system, into the first storage device; a function of loading a second module into the second storage device, the second module having a function of controlling communication between hardware and software in response to a request from the first module; a function of loading a third module into the third storage device, the third module having a function of processing the data or running an application for processing the data in response to a request from the second module; a function of refreshing the second storage device and the third storage device in a power saving mode; a function of canceling refresh of one of the second storage device and the third storage device in which a module necessary for processing the data is loaded when the interrupt is detected by the first module during a power saving mode; A program to achieve this.

8. The information processing system includes a processor that includes a volatile first storage device that is powered on even in a power saving mode so that data is not lost, and volatile second and third storage devices that are subject to refresh control in the power saving mode, At startup, loading a first module having a function of detecting an interrupt due to data reception into the first storage device, among modules formed by dividing the operating system into a plurality of modules according to the functions of the operating system; loading a second module into the second storage device, the second module having a function of controlling communication between hardware and software in response to a request from the first module; loading a third module into the third storage device, the third module having a function of processing the data or running an application for processing the data in response to a request from the second module; In a power saving mode, the second storage device and the third storage device are refreshed; When the interrupt is detected by the first module during the power saving mode, the refresh of one of the second storage device and the third storage device in which a module necessary for processing the data is loaded is canceled. An information processing method comprising:

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