Logarithmic transformation device and system

Abstract

To provide a logarithmic transformation device with a small circuit scale.SOLUTION: A logarithmic transformation device comprises a bit position detection circuit, a polynomial selection circuit 322, a polynomial arithmetic circuit 323, and a logarithmic arithmetic circuit. The bit position detection circuit detects the digit bit position bp0 that is the bit position of the most significant bit whose bit value is 1 within the bit sequence Sx representing a number in binary. The polynomial selection circuit 322 selects one polynomial from a plurality of polynomials based on bits at bit positions at least one position lower than the digit bit position bp0 within the number bit sequence Sx. The polynomial arithmetic circuit 323 calculates the decimal part of the logarithm based on the selected polynomial and the M-bit sequence within the number bit sequence Sx that is lower than the digit bit position bp0. The logarithmic arithmetic circuit generates a logarithm bit sequence representing the logarithm based on the decimal part of the logarithm and the integer part of the logarithm based on the digit bit position bp0.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] The present disclosure relates to logarithmic conversion devices and systems. [Background technology]

[0002] Patent Document 1 discloses a technique relating to a logarithmic conversion device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-338390 Summary of the Invention [Problem to be solved by the invention]

[0004] There is a demand for a reduction in circuit scale.

[0005] Therefore, an object of the present disclosure is to provide a logarithmic conversion device with a small circuit scale. [Means for solving the problem]

[0006] One aspect of a logarithmic conversion device is a logarithmic conversion device that converts a number into a logarithm, and includes: a bit position detection circuit that detects the digit bit position of the most significant bit, which has a bit value of 1, in a bit string that represents the number in binary; a polynomial selection circuit that selects one polynomial from a plurality of polynomials based on a bit in the bit string that is at least one bit position lower than the digit bit position; a polynomial arithmetic circuit that calculates the fractional part of the logarithm based on the polynomial selected by the polynomial selection circuit and an M-bit string in the bit string that is lower than the digit bit position; and a logarithm arithmetic circuit that generates a logarithm bit string that represents the logarithm based on the fractional part of the logarithm and the integer part of the logarithm based on the digit bit position.

[0007] One aspect of the system includes a power supply side system, a load side system including a motor that drives a robot, and a cable connecting the power supply side system and the load side system, wherein the power supply side system includes a coupler unit that extracts a communication signal from the power supply voltage applied to the cable, an increase / decrease unit that amplifies or attenuates the amplitude of the communication signal based on an operating amount, a measurement unit that includes the logarithmic conversion device, converts the number indicating the amplitude of the communication signal into a logarithm, and outputs a measurement value of the amplitude based on the logarithm, and an increase / decrease control unit that determines the operating amount based on the measurement value and a target value. [Effects of the Invention]

[0008] The circuit scale can be reduced. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a schematic diagram illustrating an example of a processing system to which a logarithmic conversion device according to the present disclosure is applied. [Figure 2] 3 is a schematic diagram showing an example of the configuration of a power supply side communication unit and a load side communication unit. FIG. [Figure 3] FIG. 10 is a schematic diagram showing an example of a processing system in which the load is a brushless DC motor. [Figure 4] FIG. 2 is a schematic diagram illustrating an example of the configuration of an RF front-end circuit. [Figure 5] FIG. 1 is a schematic diagram illustrating an example of the configuration of a logarithmic conversion device. [Figure 6] 10 is a graph showing the correspondence between the value M and the decimal part yd of the logarithm y. [Figure 7] 10 is a graph showing the correspondence between the decimal part Md of a value M and the decimal part yd of a logarithm y. [Figure 8] 10A and 10B are diagrams illustrating specific examples of bit strings in a logarithmic conversion device. [Figure 9] FIG. 2 is a schematic diagram showing an example of a specific configuration of a decimal arithmetic circuit. [Figure 10] FIG. 10 is a schematic diagram illustrating an example of the configuration of a logarithmic conversion device according to a second embodiment. [Figure 11]FIG. 10 is a schematic diagram showing an example of a specific configuration of an M operation circuit according to the second embodiment. [Figure 12] 10A and 10B are diagrams illustrating examples of bit strings processed by a rounding circuit. [Figure 13] 10A and 10B are diagrams illustrating examples of bit strings generated by a supplement circuit. [Figure 14] 10A and 10B are diagrams illustrating other examples of bit strings processed by the rounding circuit. [Figure 15] 1 is a schematic diagram showing a first example of a specific configuration of a bit position detection circuit. [Figure 16] 10A and 10B are diagrams illustrating examples of bit strings in a bit position detection circuit. [Figure 17] FIG. 10 is a schematic diagram showing a second example of the configuration of the bit position detection circuit. [Figure 18] 10A and 10B are diagrams illustrating examples of bit strings. [Figure 19] FIG. 2 is a diagram showing an example of a specific configuration of a group position detection circuit. [Figure 20] 10A and 10B are diagrams illustrating examples of bit strings. [Figure 21] FIG. 2 is a schematic diagram illustrating an example of the configuration of a bit position detection circuit. [Figure 22] FIG. 10 is a schematic diagram illustrating an example of the configuration of a logarithmic conversion device according to a fourth embodiment. [Figure 23] FIG. 2 is a schematic diagram illustrating an example of the configuration of a constant multiplication circuit. [Figure 24] 10 is a graph showing the relationship between the number x and the error of the measured value PV. [Figure 25] 10 is a graph showing the relationship between the number x and the error of the measurement value PV (provisionally calculated value). [Figure 26] 1 is a graph showing a polynomial. [Figure 27] 10 is a graph showing the relationship between the number x and the error of the measurement value PV using the correspondence relationship information after offset. DETAILED DESCRIPTION OF THE INVENTION

[0010] First Embodiment <System> 1 is a schematic diagram showing an example of a processing system 1000 to which a logarithmic conversion device 1 (described later) according to the present disclosure is applied. As shown in FIG. 1, the processing system 1000 includes, for example, a load-side system 200 having a load 210, a power supply-side system 100 that outputs a power supply voltage to be supplied to the load 210, and a cable 600 that connects the load-side system 200 and the power supply-side system 100. The power supply voltage output by the power supply-side system 100 is supplied to the load-side system 200 via the cable 600. The power supply-side system 100 and the load-side system 200 can communicate with each other via the cable 600.

[0011] The power supply side system 100 includes, for example, a power supply unit 110 that outputs a power supply voltage to be supplied to a load 210. The power supply unit 110 and the load 210 are connected to each other by a power line 500 that transmits the power supply voltage output by the power supply unit 110. The power line 500 can transmit power to be supplied to the load 210. A cable 600 constitutes a part of the power line 500. The power line 500 is made up of a power supply side power line that transmits the power supply voltage within the power supply side system 100, the cable 600, and a load side power line that transmits the power supply voltage within the load side system 200.

[0012] The power supply side system 100 includes, for example, a power supply side communication device 120 (also simply referred to as communication device 120) in addition to the power supply unit 110. The load side system 200 includes, for example, a load side communication device 220 (also simply referred to as communication device 220) in addition to the load 210. The power supply side communication device 120 and the load side communication device 220 form a communication system 320.

[0013] The power supply side communication device 120 and the load side communication device 220 can, for example, perform power line communication (PLC) with each other via a power line 500. The communication method between the power supply side communication device 120 and the load side communication device 220 may be HD-PLC (registered trademark: High Definition Power Line Communication), or another method.

[0014] The power supply side communication device 120 includes, for example, a power supply side communication section 130 (also simply referred to as communication section 130) and a power supply side interface circuit 140 (also simply referred to as interface circuit 140). The power supply side interface circuit 140 is inserted into the power line 500. The power supply voltage output by the power supply section 110 is input to the cable 600 via the interface circuit 140.

[0015] The interface circuit 140 is capable of, for example, performing low-pass filtering on the power supply voltage output by the power supply unit 110. The power supply voltage that has been subjected to low-pass filtering by the interface circuit 140 is input to the cable 600.

[0016] The load-side communication device 220 includes, for example, a load-side communication unit 230 (also simply referred to as the communication unit 230) and a load-side interface circuit 240 (also simply referred to as the interface circuit 240). The load-side interface circuit 240 is inserted into the power line 500. The power supply voltage transmitted to the load-side system 200 by the cable 600 is supplied to the load 210 through the interface circuit 240.

[0017] The interface circuit 240 can, for example, perform low-pass filtering on the power supply voltage that is input, and supplies the power supply voltage that has undergone low-pass filtering to the load 210.

[0018] The power supply side communication unit 130 and the load side communication unit 230 can communicate with each other via the power line 500, the power supply side interface circuit 140, and the load side interface circuit 240. The power supply side interface circuit 140 and the load side interface circuit 240 constitute an interface system 340. The power supply side communication unit 130 and the load side communication unit 230 can communicate with each other via the power line 500 and the interface system 340.

[0019] The communication units 130 and 230 may perform two-way communication or one-way communication. In the former case, the communication units 130 and 230 each function as a transmitting / receiving unit, and the communication devices 120 and 220 each function as a transmitting / receiving device. On the other hand, in the latter case, the communication units 130 and 230 may each function as a transmitting unit and a receiving unit, and the communication devices 120 and 220 may each function as a transmitting device and a receiving device. Alternatively, the communication units 130 and 230 may each function as a receiving unit and a transmitting unit, and the communication devices 120 and 220 may each function as a receiving device and a transmitting device.

[0020] For example, consider a case where the communication unit 130 transmits a communication signal and the communication unit 230 receives the communication signal from the communication unit 130. In this case, the interface circuit 140 superimposes the communication signal transmitted by the communication unit 130 onto the power line 500. In other words, the interface circuit 140 superimposes the communication signal transmitted by the communication unit 130 on the power supply voltage transmitted by the power line 500. Meanwhile, the interface circuit 240 extracts the communication signal from the power line 500 on which the communication signal is superimposed. The communication unit 230 receives the communication signal extracted by the interface circuit 240.

[0021] Also, consider a case where the communication unit 230 transmits a communication signal and the communication unit 130 receives the communication signal from the communication unit 230. In this case, the interface circuit 240 superimposes the communication signal transmitted by the communication unit 230 onto the power line 500. In other words, the interface circuit 240 superimposes the communication signal transmitted by the communication unit 230 on the power supply voltage transmitted by the power line 500. Meanwhile, the interface circuit 140 extracts the communication signal from the power line 500 on which the communication signal is superimposed. The communication unit 130 receives the communication signal extracted by the interface circuit 140.

[0022] 2 is a schematic diagram showing an example of the configuration of the power supply side communication unit 130 and the load side communication unit 230. In this example, the configuration of the power supply side communication unit 130 and the configuration of the load side communication unit 230 are the same, but they may also be different. Hereinafter, when there is no need to distinguish between the power supply side communication unit 130 and the load side communication unit 230, they may each be simply referred to as a communication unit. Furthermore, the power supply side interface circuit 140 or the load side interface circuit 240 connected to the communication unit may also be simply referred to as an interface circuit.

[0023] 2, the communication unit includes, for example, a control unit 400, a storage unit 410, and an RF front-end circuit 420. RF is an abbreviation for Radio Frequency. The communication unit can also be referred to as, for example, a communication circuit.

[0024] The control unit 400 can comprehensively manage the operation of the communication unit by controlling the other components of the communication unit. The control unit 400 can also be called, for example, a control circuit. The control unit 400 includes, for example, at least one processor. The at least one processor may include, for example, a CPU (Central Processing Unit).

[0025] The storage unit 410 may include a non-transitory recording medium readable by the CPU of the control unit 400, such as a read-only memory (ROM) and a random access memory (RAM). The storage unit 410 stores, for example, a program 410a for controlling the communication unit. Various functions of the control unit 400 are realized, for example, by the CPU of the control unit 400 executing the program 410a in the storage unit 410.

[0026] When the communication unit transmits a communication signal to the interface circuit, the control unit 400 generates the communication signal (also referred to as a transmission signal) and inputs it to the RF front-end circuit 420. The control unit 400 generates the communication signal by, for example, performing digital modulation processing using information to be transmitted. The communication signal can also be referred to as a modulated signal. The modulation method used by the control unit 400 may be, for example, FSK, QPSK, or another method. The control unit 400 may use MSK, which is a type of FSK. FSK is an abbreviation for Frequency Shift Keying, MSK is an abbreviation for Minimum Shift Keying, and QPSK is an abbreviation for Quadrature Phase Shift Keying.

[0027] When the communication unit transmits a communication signal to the interface circuit, the RF front-end circuit 420 converts, for example, a digital communication signal input from the control unit 400 into an analog format. Then, the RF front-end circuit 420 transmits the analog communication signal to the interface circuit. The RF front-end circuit 420 may amplify the analog communication signal and output the amplified communication signal to the interface circuit. The RF front-end circuit 420 may convert a single-ended communication signal generated by the control unit 400 into a differential format and transmit the signal, or may transmit the communication signal generated by the control unit 400 in single-ended format. The control unit 400 may convert the generated digital communication signal into an analog format and input the analog communication signal to the RF front-end circuit 420.

[0028] When the communication unit receives a communication signal, the RF front-end circuit 420 receives the communication signal extracted by the interface circuit from the power line 500 and performs, for example, attenuation and filtering on the received communication signal. The RF front-end circuit 420 then converts the attenuated and filtered communication signal from analog to digital format and inputs the digital communication signal to the control unit 400. When receiving a differential communication signal, the RF front-end circuit 420 may convert the communication signal from differential format to single-ended format and input it to the control unit 400. The control unit 400 performs demodulation processing or the like on the communication signal (also referred to as a received signal) input from the RF front-end circuit 420 to obtain information contained in the communication signal. Note that the RF front-end circuit 420 may input the analog communication signal to the control unit 400, and the control unit 400 may convert the input communication signal from analog format to digital format.

[0029] The configuration of the communication unit is not limited to the above example. For example, the control unit 400 may include multiple CPUs. The control unit 400 may also include at least one DSP (Digital Signal Processor). All or some of the functions of the control unit 400 may be realized by a hardware circuit that does not require software to realize the function. The storage unit 410 may also include a computer-readable non-transitory recording medium other than ROM and RAM. The communication unit may also include a microcomputer having the control unit 400 and the storage unit 410.

[0030] The load 210 included in the load-side system 200 may be any type. For example, the load 210 may be an actuator. In this case, the load 210 may be a motor, a hydraulic actuator, a pneumatic actuator, or an electric actuator that does not use a motor.

[0031] <Example of processing system> A specific example of the processing system 1000 will be described below. FIG. 3 is a schematic diagram showing an example of the processing system 1000 in which the load 210 is a motor (e.g., an AC servo motor or a brushless DC motor). DC is an abbreviation for Direct Current. A brushless DC motor is also called a three-phase motor and has three coils. The three coils may be connected in a star connection or a delta connection. The brushless DC motor serving as the load 210 may be used to drive a robot, a belt conveyor, or other applications. Hereinafter, the term "brushless DC motor" or "brushless motor" simply refers to the brushless DC motor serving as the load 210.

[0032] In the processing system 1000 (also referred to as processing system 1000A) shown in FIG. 3, the power supply unit 110 outputs a power supply voltage to the brushless DC motor. The power line 500 transmits the power supply voltage output from the power supply unit 110 to the brushless DC motor. The power line 500 is a three-phase power line and is composed of a U-phase power line 510, a V-phase power line 520, and a W-phase power line 530. The U-phase power line 510, the V-phase power line 520, and the W-phase power line 530 each extend from the power supply unit 110 to the brushless DC motor. The cable 600 connecting the power supply side system 100 and the load side system 200 constitutes a part of each of the U-phase power line 510, the V-phase power line 520, and the W-phase power line 530.

[0033] The power supply unit 110 includes, for example, an inverter circuit. The power supply unit 110 can also be referred to as, for example, a power supply circuit. The inverter circuit generates and outputs a U-phase voltage, a V-phase voltage, and a W-phase voltage. The U-phase power line 510 transmits the U-phase voltage output from the power supply unit 110 to the brushless DC motor. The V-phase power line 520 transmits the V-phase voltage output from the power supply unit 110 to the brushless DC motor. The W-phase power line 530 transmits the W-phase voltage output from the power supply unit 110 to the brushless DC motor. Each of the U-phase voltage, V-phase voltage, and W-phase voltage is a square wave voltage, and can be referred to as a square wave power supply voltage for the brushless motor. The square wave voltage includes a fundamental wave component and a harmonic component. The brushless motor is PWM-controlled by supplying the square wave U-phase voltage, V-phase voltage, and W-phase voltage to the brushless motor. PWM is an abbreviation for Pulse Width Modulation. The maximum values ​​of the U-phase voltage, V-phase voltage, and W-phase voltage are, for example, several hundred volts.

[0034] The power supply side interface circuit 140 is inserted into the U-phase power line 510, the V-phase power line 520, and the W-phase power line 530. In the example of FIG. 3, the interface circuit 140 includes a low-pass filter LPG1. The interface circuit 140 (specifically, the low-pass filter LPG1) is capable of performing low-pass filtering on the U-phase voltage, the V-phase voltage, and the W-phase voltage output by the power supply unit 110. The U-phase voltage, the V-phase voltage, and the W-phase voltage that have been low-pass filtered by the interface circuit 140 are input to the cable 600.

[0035] The interface circuit 140 performs low-pass filtering on the U-phase voltage, passing the fundamental component of the U-phase voltage and attenuating the harmonic components of the U-phase voltage. The interface circuit 140 performs low-pass filtering on the V-phase voltage, passing the fundamental component of the V-phase voltage and attenuating the harmonic components of the V-phase voltage. The interface circuit 140 performs low-pass filtering on the W-phase voltage, passing the fundamental component of the W-phase voltage and attenuating the harmonic components of the W-phase voltage. The cable 600 receives the U-phase voltage, which includes a fundamental component and harmonic components attenuated by the interface circuit 140; the V-phase voltage, which includes a fundamental component and harmonic components attenuated by the interface circuit 140; and the W-phase voltage, which includes a fundamental component and harmonic components attenuated by the interface circuit 140. The fundamental components of the U-phase voltage, V-phase voltage, and W-phase voltage have the same frequency, e.g., several kHz. Note that the frequencies of the fundamental components of the U-phase voltage, V-phase voltage, and W-phase voltage are not limited to this.

[0036] Load-side interface circuit 240 is inserted into U-phase power line 510, V-phase power line 520, and W-phase power line 530. In the example of FIG. 3, interface circuit 240 includes low-pass filter LPG2. Load-side interface circuit 240 (specifically, low-pass filter LPG2) is capable of performing low-pass filtering on the U-phase voltage, V-phase voltage, and W-phase voltage transmitted to load-side system 200 via cable 600. The U-phase voltage, V-phase voltage, and W-phase voltage that have been low-pass filtered by interface circuit 240 are supplied to load 210, i.e., the brushless motor.

[0037] The interface circuit 240 performs low-pass filtering on the U-phase voltage, passing the fundamental component of the U-phase voltage and attenuating the harmonic components of the U-phase voltage. The interface circuit 240 performs low-pass filtering on the V-phase voltage, passing the fundamental component of the V-phase voltage and attenuating the harmonic components of the V-phase voltage. The interface circuit 240 performs low-pass filtering on the W-phase voltage, passing the fundamental component of the W-phase voltage and attenuating the harmonic components of the W-phase voltage. The brushless motor receives the U-phase voltage, which includes a fundamental component and harmonic components attenuated by the interface circuit 240; the V-phase voltage, which includes a fundamental component and harmonic components attenuated by the interface circuit 240; and the W-phase voltage, which includes a fundamental component and harmonic components attenuated by the interface circuit 240.

[0038] As described above, in the processing system 1000A, the U-phase voltage, V-phase voltage, and W-phase voltage output by the power supply unit 110 are supplied to the brushless motor after being low-pass filtered by the interface circuits 140 and 240. This reduces high-frequency noise contained in the power supply voltage of the brushless motor.

[0039] In the processing system 1000A, the power supply side communication device 120 and the load side communication device 220 can perform, for example, bidirectional communication. Furthermore, the power supply side communication device 120 and the load side communication device 220 can perform, for example, differential communication. The power supply side communication unit 130 transmits a differential communication signal (also called a differential signal), and the load side communication unit 230 can receive the differential signal transmitted by the power supply side communication unit 130. Furthermore, the load side communication unit 230 transmits a differential signal, and the power supply side communication unit 130 can receive the differential signal transmitted by the load side communication unit 230. The maximum voltage of the differential signal is, for example, several volts.

[0040] Hereinafter, the differential signal transmitted by the communication unit 130 may be referred to as a power supply side differential signal, and the differential signal transmitted by the communication unit 230 may be referred to as a load side differential signal. Furthermore, each of the two paired communication signals constituting the power supply side differential signal may be referred to as a power supply side communication signal. Furthermore, each of the two paired communication signals constituting the load side differential signal may be referred to as a load side communication signal.

[0041] The power supply side interface circuit 140 includes a coupler unit CPG1. The power supply side interface circuit 140 (specifically, the coupler unit CPG1) superimposes the power supply side differential signal transmitted by the communication unit 130 onto two of the U-phase power line 510, the V-phase power line 520, and the W-phase power line 530. Specifically, the power supply side interface circuit 140 superimposes the pair of power supply side communication signals transmitted by the communication unit 130 onto two of the U-phase power line 510, the V-phase power line 520, and the W-phase power line 530, respectively.

[0042] 3 , the power supply side differential signal is superimposed on the U-phase power line 510 and the V-phase power line 520. The interface circuit 140 superimposes one power supply side communication signal on the U-phase voltage (i.e., square wave voltage) transmitted by the U-phase power line 510, and superimposes the other power supply side communication signal on the V-phase voltage (i.e., square wave voltage) transmitted by the V-phase power line 520. The U-phase power line 510 transmits the superimposed power supply side communication signal to the load side interface circuit 240, and the V-phase power line 520 transmits the superimposed power supply side communication signal to the load side interface circuit 240. The power supply side differential signal may be superimposed on the U-phase power line 510 and the W-phase power line 530, or on the V-phase power line 520 and the W-phase power line 530.

[0043] The load-side interface circuit 240 includes a coupler unit CPG2. The load-side interface circuit 240 (specifically, the coupler unit CPG2) superimposes the load-side differential signal transmitted by the communication unit 230 onto two of the U-phase power line 510, the V-phase power line 520, and the W-phase power line 530. In the example of FIG. 3 , the load-side differential signal is superimposed onto the U-phase power line 510 and the V-phase power line 520. The interface circuit 240 superimposes one load-side communication signal onto the U-phase power line 510 and the other load-side communication signal onto the V-phase power line 520. The U-phase power line 510 transmits the superimposed load-side communication signal to the interface circuit 140, and the V-phase power line 520 transmits the superimposed load-side communication signal to the interface circuit 140. The load side differential signal may be superimposed on U-phase power line 510 and W-phase power line 530, or may be superimposed on V-phase power line 520 and W-phase power line 530.

[0044] The power supply side interface circuit 140 (specifically, the coupler unit CPG1) extracts the load side differential signals from the U-phase power line 510 and the V-phase power line 520 on which the load side differential signals are superimposed, and outputs the extracted load side differential signals to the power supply side communication unit 130. The communication unit 130 receives the load side differential signals extracted by the interface circuit 140. The interface circuit 140 extracts one of the load side communication signals from the U-phase power line 510 on which the load side communication signal is superimposed, and outputs the extracted load side communication signal to the communication unit 130. The interface circuit 140 also extracts the other of the load side communication signals from the V-phase power line 520 on which the other load side communication signal is superimposed, and outputs the extracted load side communication signal to the communication unit 130.

[0045] The load-side interface circuit 240 (specifically, the coupler unit CPG2) extracts the power supply side differential signals from the U-phase power line 510 and the V-phase power line 520 on which the power supply side differential signals are superimposed, and outputs the power supply side differential signals to the load-side communication unit 230. The communication unit 230 receives the power supply side differential signals extracted by the interface circuit 240. The interface circuit 240 extracts one of the power supply side communication signals from the U-phase power line 510 on which the power supply side communication signal is superimposed, and outputs the one of the power supply side communication signals to the communication unit 230. The interface circuit 240 also extracts the other of the power supply side communication signals from the V-phase power line 520 on which the other power supply side communication signal is superimposed, and outputs the other of the power supply side communication signals to the communication unit 230.

[0046] In the processing system 1000, as shown in FIG. 3, the load side system 200 may be provided with a sensor 290 that detects the state of the load 210, and the power supply side system 100 may be provided with a control device 190 that controls the power supply unit 110 based on the detection results of the sensor 290.

[0047] The sensor 290 has, for example, a rotary encoder that detects the rotational position of a brushless motor serving as the load 210. The sensor 290 outputs sensor information indicating the detection result of the rotary encoder to the load side communication unit 230. The load side communication unit 230 transmits a load side differential signal including the sensor information from the sensor 290. The power supply side communication unit 130 receives the load side differential signal including the sensor information. In the power supply side communication unit 130, the control unit 400 acquires the sensor information included in the load side differential signal received by the RF front-end circuit 420. The sensor information acquired by the control unit 400 is input to the control device 190.

[0048] Control device 190 controls the inverter circuit of power supply unit 110 based on sensor information from power supply side communication unit 130. Control device 190 controls the inverter circuit of power supply unit 110 based on the sensor information, for example, so that the rotational position or rotational speed of the brushless motor reaches a target value. Control device 190 can control the rotation of the brushless motor via power supply unit 110.

[0049] The sensor 290 outputs sensor information in response to an output request from the control device 190, for example. The control device 190 transmits output request information indicating an output request for the sensor information to the power supply side communication unit 130. The power supply side communication unit 130 transmits a power supply side differential signal including the output request information from the control device 190. The load side communication unit 230 receives the power supply side differential signal including the output request information. In the load side communication unit 230, the control unit 400 acquires the output request information included in the power supply side differential signal received by the RF front-end circuit 420. The load side communication unit 230 outputs the acquired output request information to the sensor 290. The sensor 290 outputs the sensor information in response to receiving the output request information. The sensor information output from the sensor 290 is input to the control device 190.

[0050] 3 can be considered to be, for example, a servo system that controls a brushless motor. The power supply side system 100 can be considered to be, for example, a servo amplifier, and the load side system 200 can be considered to be, for example, a servo motor or a servo actuator.

[0051] Fig. 4 is a schematic diagram showing an example of the configuration of RF front-end circuit 420. The configuration shown in Fig. 4 is, for example, a portion of RF front-end circuit 420 that processes a differential signal (corresponding to a communication signal) extracted by interface circuit 140. As shown in Fig. 4, RF front-end circuit 420 includes an increase / decrease unit 421, an AD conversion unit 422, a measurement unit 423, and an increase / decrease control unit 424.

[0052] The increase / decrease unit 421 is a circuit that amplifies or attenuates the amplitude of a communication signal. The increase / decrease unit 421 may be a programmable gain amplifier or may be a digital gain amplifier. The increase / decrease unit 421 amplifies or attenuates the communication signal by an amount based on the manipulated variable MV. As a specific example, the increase / decrease unit 421 attenuates the amplitude of a communication signal (e.g., a received signal). In this case, the increase / decrease unit 421 is an attenuator.

[0053] The AD conversion unit 422 converts the output of the increase / decrease unit 421 from an analog signal to a digital signal.

[0054] The measurement unit 423 calculates the amplitude of the communication signal logarithmically and outputs the calculated value as a measurement value PV to the increase / decrease control unit 424. The measurement unit 423 includes a subtractor 4231, a squaring unit 4232, a corrected moving average unit 4233, a square root unit 4234, and a logarithmic conversion unit 4235. The subtractor 4231 offsets the output of the AD conversion unit 422 by a predetermined subtraction amount to calculate the amplitude of the communication signal. The squaring unit 4232 squares the output of the subtractor 4231. The corrected moving average unit 4233 calculates a corrected moving average of the output of the squaring unit 4232. The square root unit 4234 calculates the square root of the output of the corrected moving average unit 4233. The logarithmic conversion unit 4235 calculates a value obtained by multiplying the common logarithm of the output of the square root unit 4234 by "20". This value corresponds to the measured value PV, which indicates the logarithmic representation of the amplitude (effective value) of the communication signal.

[0055] The increase / decrease control unit 424 calculates a manipulated variable MV based on the measured value PV and its target value SV. The increase / decrease control unit 424 includes a subtractor 4241 and a PI control unit 4242. The subtractor 4241 calculates the deviation between the measured value PV from the logarithmic conversion unit 4235 and its target value SV. The PI control unit 4242 calculates the manipulated variable MV by proportional-integral control based on the deviation, and outputs the manipulated variable MV to the increase / decrease unit 421. The increase / decrease unit 421 amplifies or attenuates the communication signal based on the manipulated variable MV. This allows the increase / decrease unit 421 to output a communication signal converted to an appropriate amplitude in response to the target value SV.

[0056] Here, if the output value of the corrected moving average unit 4233 is called a number x, the square root unit 4234 outputs the square root √x of the number x, and the logarithm conversion unit 4235 outputs the measurement value PV obtained by multiplying the common logarithm of the square root √x by 20. Therefore, the measurement value PV is expressed by the following equation (1).

[0057] PV=20·log 10 (√x) (1) Transforming equation (1) yields equation (2) below.

[0058] PV=10·log2(x) / log2(10) =3.01 log2(x) (2) In view of equation (2), the functions of the square root unit 4234 and the logarithm conversion unit 4235 can be realized by a logarithm conversion function unit and a constant multiplication function unit, which will be described next. The logarithm conversion function unit is a function unit that converts a number x into a logarithm y (=log2(x)) with base 2. The constant multiplication function unit is a function unit that multiplies the logarithm y by a constant "3.01".

[0059] The logarithmic conversion device 1 will be described below as a logarithmic conversion function unit. The logarithmic conversion device 1 may have a constant multiplication function unit. An example of this aspect will be described in the fourth embodiment.

[0060] <Logarithmic conversion device> 5 is a schematic diagram showing an example of the configuration of the logarithmic conversion device 1. In the following, the concept of logarithmic conversion will first be described, and then an example of the configuration of the logarithmic conversion device 1 will be described.

[0061] <Logarithmic transformation concept> The logarithm y is expressed by the following equation (3).

[0062] y=log2(x) (3) Here, when the integer part yr of the logarithm y and the decimal part yd (0≦yd<1) of the logarithm y are introduced, the following equation (4) is established.

[0063] y=yr+yd (4) If the integer part yr and the decimal part yd can be calculated based on the number x, the logarithm y can be calculated based on equation (4).

[0064] Here, each value is considered as a binary number. In the following, when each value is expressed in binary, a "2" is added to the end of the code of each value. For example, the binary number of the number x is called the number x2.

[0065] For example, let us consider the case where the number x is "10". "10" is "2 3 " is larger than "2 4", so the integer part yr of the logarithm y is "3". On the other hand, the binary representation of the number x, the number x2, is "1010". And, "2 3 The number " corresponds to the most significant digit "1" in the number x2. In other words, the integer part yr of the logarithm y correlates with the digits of the number x2 in binary notation. Specifically, the integer part yr (here "3") is the value obtained by subtracting 1 from the number of digits of the number x2 (here "4"). Therefore, by detecting the number of digits of the number x2, the integer part yr of the logarithm y can be found.

[0066] Next, we will explain how to find the decimal part yd of the logarithm y. First, define the number x as follows:

[0067] x=2 y =2 (yr+yd) =2 yr M (5) Here, the value M is "2 yd " In other words, the following equation (6) holds.

[0068] yd=log2(M) (6) Since the decimal part yd of the logarithm y is equal to or greater than 0 and less than 1, the value M is equal to or greater than 1 and less than 2.

[0069] Furthermore, by transforming equation (5), the following equation (7) is derived.

[0070] M=x / 2 yr ···(7) In view of equation (7), the value M is the number x divided into 2 yr " is the value obtained by dividing the number x2 by "2 yr " division is equivalent to shifting the decimal point of number x2 to the left by the integer part yr. For example, when number x2 is "1010", the division of "2 yr The division result of " (i.e., the value M2) is "1.010". As described above, the value M2 can be obtained by shifting the decimal point in the number x2 to the left by the integer part yr of the logarithm y.

[0071] As can be seen from equation (6), the decimal part yd is the logarithm of the value M. The correspondence between this value M and the decimal part yd is known. FIG. 6 is a graph showing the correspondence between the value M and the decimal part yd of the logarithm y. In the example of FIG. 6, the binary notation of the value M (i.e., the value M2) is also shown in parentheses on the horizontal axis. If the correspondence between this value M and the decimal part yd is set in advance, the decimal part yd of the logarithm y can be found based on the value M and the correspondence.

[0072] Incidentally, since the integer part of the value M is always "1", instead of the correspondence relationship between the value M and the decimal part yd of the logarithm y, the correspondence relationship between the decimal part Md (=M-1) of the value M and the decimal part yd of the logarithm y may be set in advance. Fig. 7 is a graph showing the correspondence relationship between the decimal part Md of the value M and the decimal part yd of the logarithm y. Graph G1 in Fig. 7 shows the theoretical correspondence relationship between the decimal part Md of the value M and the decimal part yd of the logarithm y.

[0073] As described above, the integer part yr of the logarithm y can be calculated based on the number of digits of the number x, and the decimal part yd of the logarithm y can be calculated based on the value M derived from the number x. Therefore, the logarithm y can be calculated based on equation (4).

[0074] <Outline of the logarithmic conversion device> Next, an example of the configuration of the logarithmic conversion device 1 will be described. The logarithmic conversion device 1 is an electronic circuit that calculates the logarithm y of a number x. As shown in FIG. 5, a bit string Sx representing the number x is input to the logarithmic conversion device 1. The bit string Sx represents the number x in binary notation. In other words, the bit string Sx represents the number x². As an example, it is assumed here that the number of bits bx of the bit string Sx is "16." In this case, the bit position bp of the most significant bit of the bit string Sx is "15" (=bx-1), the bit position bp of the least significant bit is "0 (zero)," and the number x represented by the bit string Sx is, for example, greater than or equal to "0" and less than or equal to "65535" in decimal notation.

[0075] FIG. 8 is a diagram showing a specific example of each bit string in the logarithmic conversion device 1. In the example of FIG. 8, the number bit string Sx (=number x2) is shown as "0000101101110011." Here, "1" means that the bit is, for example, in the H state, and "0" means that the bit is, for example, in the L state. The number bit string Sx in the above specific example represents "2931" in decimal notation. In other words, the number x is "2931."

[0076] 5, the logarithmic conversion device 1 includes an integer arithmetic circuit 2, a decimal arithmetic circuit 3, and a logarithm arithmetic circuit 4. The integer arithmetic circuit 2 is a circuit that calculates the integer part yr of the logarithm y based on the number x. That is, the integer arithmetic circuit 2 generates an integer bit string Syr that indicates the integer part yr of the logarithm y based on the number bit string Sx.

[0077] Specifically, the integer arithmetic circuit 2 includes a bit position detection circuit 21. The bit position detection circuit 21 detects a digit bit position bp0, which will be described below, from the number bit string Sx. Referring also to FIG. 8, the digit bit position bp0 is the bit position bp of the most significant bit in the number bit string Sx, whose bit value is "1." In the example of FIG. 8, the digit bit position bp0 is "11." This digit bit position bp0 corresponds to the value obtained by subtracting "1" from the number of digits of the number x2, and therefore corresponds to the integer part yr of the logarithm y. The integer arithmetic circuit 2 outputs a bit string indicating the digit bit position bp0 detected by the bit position detection circuit 21 as an integer bit string Syr to the decimal arithmetic circuit 3 and the logarithm arithmetic circuit 4. A specific example of the bit position detection circuit 21 will be described in the third embodiment.

[0078] The decimal arithmetic circuit 3 is a circuit that calculates the decimal part yd of the logarithm y based on the number x and the integer part yr of the logarithm y. In other words, the decimal arithmetic circuit 3 is a circuit that generates the decimal bit string Syd indicating the decimal part yd of the logarithm y based on the number bit string Sx and the digit bit position bp0 (here, the integer bit string Syr). Here, an overview of the decimal arithmetic circuit 3 will be given, and an example of its specific configuration will be described in detail later.

[0079] First, the decimal arithmetic circuit 3 outputs the value M2 based on the bit string Sx. Specifically, the decimal arithmetic circuit 3 calculates the value M2 by shifting the decimal point of the number x2 to the left by the integer part yr of the logarithm y. In the example of Figure 8, the value M2 is "1.01101110011".

[0080] Next, the decimal arithmetic circuit 3 calculates the decimal part yd of the logarithm y based on the preset correspondence information (see FIG. 6) and the value M. Since the integer part of the value M is always "1," the decimal arithmetic circuit 3 may calculate the decimal part yd of the logarithm y based on the decimal part yd of the value M and the correspondence information (see FIG. 7). That is, the decimal arithmetic circuit 3 may generate an Md bit string SMd indicating the decimal part Md of the value M, and may generate a decimal bit string Syd based on the Md bit string SMd and the correspondence information. The Md bit string SMd may be a bit string obtained by truncating the most significant bit of the M bit string SM, as shown in FIG. 8. Alternatively, the Md bit string SMd may be a bit string obtained by replacing the most significant bit of the M bit string SM with "0." The decimal arithmetic circuit 3 outputs the decimal bit string Syd to the logarithm arithmetic circuit 4.

[0081] The logarithm calculation circuit 4 generates a logarithm bit string Sy indicating a logarithm y based on the integer bit string Syr and the fractional bit string Syd. Specifically, the logarithm calculation circuit 4 includes an adder that adds the integer bit string Syr and the fractional bit string Syd. The adder is formed by a combinational circuit. The logarithm calculation circuit 4 adds the integer bit string Syr and the fractional bit string Syd to generate the logarithm bit string Sy.

[0082] <Decimal arithmetic circuit> 9 is a schematic diagram showing an example of a specific configuration of the decimal arithmetic circuit 3. The decimal arithmetic circuit 3 is formed by, for example, a combinational circuit, and includes an M arithmetic circuit 31 and a yd arithmetic circuit 32.

[0083] The M arithmetic circuit 31 generates an M-bit sequence SM based on the multi-bit sequence Sx and the digit bit position bp0. Since the integer part of the value M is always "1" as described above, the M arithmetic circuit 31 may generate an Md-bit sequence SMd. The yd arithmetic circuit 32 generates a fractional-bit sequence Syd based on the Md-bit sequence SMd and the predetermined correspondence information.

[0084] <M arithmetic circuit> The M arithmetic circuit 31 receives the multi-bit sequence Sx and the digit bit position bp0 (here, the integer-bit sequence Syr). The M arithmetic circuit 31 may shift the multi-bit sequence Sx to the left by the shift amount obtained by subtracting the digit bit position bp0 from the number of bits bx of the multi-bit sequence Sx. In the example of FIG. 8, the number of bits bx of the multi-bit sequence Sx is "16" and the digit bit position bp0 is "11", so the shift amount is "5". By this left shift, the upper bits above the digit bit position bp0 in the multi-bit sequence Sx are truncated. That is, the bit sequence after the left shift indicates the fractional part Md of the value M (specifically, the digits after the decimal point). Therefore, the M arithmetic circuit 31 may output the bit sequence generated by the left shift as the Md-bit sequence SMd to the yd arithmetic circuit 32.

[0085] Such a shift function of the M arithmetic circuit 31 can be realized by a combinational circuit. For example, the M arithmetic circuit 31 may be a barrel shifter.

[0086] <yd arithmetic circuit> The yd arithmetic circuit 32 generates a fractional bit string Syd based on the Md bit string SMd and the correspondence information. In the first embodiment, the correspondence information is expressed as a polynomial with the fractional part Md of the value M as a variable. Specifically, as shown in FIG. 7, a polynomial is set for each of a plurality of ranges R1 and R2 for the fractional part Md. The polynomial may be a linear function or a quadratic function. Here, a linear function is used as an example. In the example of FIG. 7, the following equation (8) is set as the linear function in the range R1 where the fractional part Md is equal to or greater than 0 and less than 0.5, and the following equation (9) is set as the linear function in the range R2 where the fractional part Md is equal to or greater than 0.5 and less than 1.

[0087] yd=a1·Md+b1 ···(8) yd=a2 Md+b2 (9) Each of these polynomials is an approximation of the graph G1 in the corresponding range. That is, equation (8) is an approximation that shows the correspondence between the decimal part Md of the value M and the decimal part yd of the logarithm y in the range R1, and equation (9) is an approximation that shows the correspondence between the decimal part Md of the value M and the decimal part yd of the logarithm y in the range R2. These approximations are set in advance.

[0088] The yd calculation circuit 32 calculates the decimal part yd of the logarithm y using the polynomial of equation (8) when the decimal part Md of the value M is within range R1, and calculates the decimal part yd of the logarithm y using the polynomial of equation (9) when the decimal part Md of the value M is within range R2. More generally, the yd calculation circuit 32 selects a polynomial corresponding to the range to which the decimal part Md of the value M belongs from among a plurality of ranges, and calculates the decimal part yd of the logarithm y using the selected polynomial.

[0089] A specific example of the yd arithmetic circuit 32 will be described below with reference to FIG. 9. As shown in FIG. 9, the yd arithmetic circuit 32 includes a decimal point shift circuit 321, a polynomial selection circuit 322, and a polynomial arithmetic circuit 323. The decimal point shift circuit 321 has a function of shifting the decimal point of the Md bit string SMd to the left, and generates a bit string that indicates the value of the decimal part Md itself. The decimal point shift circuit 321 outputs the bit string (i.e., the value of the decimal part Md of the value M) to the polynomial arithmetic circuit 323. The shift function of the decimal point shift circuit 321 can be realized by a combinational circuit. For example, the decimal point shift circuit 321 may be a barrel shifter.

[0090] The polynomial selection circuit 322 selects a polynomial corresponding to the range to which the fractional part Md belongs from among multiple ranges. In the example of FIG. 7, the entire range of the fractional part Md is divided into two equal parts, range R1 and range R2. That is, in binary notation, range R1 is the range in which the fractional part Md2 is greater than or equal to "0.0" and less than "0.1," and range R2 is the range in which the fractional part Md2 is greater than or equal to "0.1" and less than "1.0." As shown in FIG. 8, when the Md bit string SMd is composed of the decimal point values ​​of the fractional part Md, the first decimal place corresponds to the most significant bit SMd[m] of the Md bit string SMd. That is, when the most significant bit SMd[m] is "0," the fractional part Md belongs to range R1, and when the most significant bit SMd[m] is "1," the fractional part Md belongs to range R2.

[0091] Therefore, the polynomial selection circuit 322 selects one of equations (8) and (9) based on the most significant bit SMd[m] of the Md bit string SMd. Specifically, when the most significant bit SMd[m] is "0," the fractional part Md is within range R1, so the polynomial selection circuit 322 selects equation (8) corresponding to range R1. On the other hand, when the most significant bit SMd[m] is "1," the fractional part Md is within range R2, so the polynomial selection circuit 322 selects equation (9) corresponding to range R2.

[0092] In the above specific example, the entire range of the decimal part Md is divided into two equal parts, but the entire range may be divided into two equal parts by the power of n (n is a natural number). n ” ranges Rk(k=1,...,2 n ) a polynomial is set for each range Rk. In view of the graph G1 in FIG. 7, if n is, for example, between "1" and "4", the polynomial for each range Rk will sufficiently approximate the graph G1 for each range Rk. n may be "3" or less, "2" or less, or even "1". Note that n may be, for example, one-fourth or less of the number of bits bx (here, "16") of the multi-bit string Sx.

[0093] For example, if n is 2, the entire range of the fractional part Md is divided into a first range R1 to a fourth range R4. In binary notation, the first range R1 is equal to or greater than 0.00 and less than 0.01, the second range R2 is equal to or greater than 0.01 and less than 0.10, the third range R3 is equal to or greater than 0.10 and less than 0.11, and the fourth range R4 is equal to or greater than 0.11 and less than 1.00. The first and second decimal places of the fractional part Md2 correspond to, for example, the most significant bit SMd[m] and the next bit SMd[m-1] of the Md bit string SMd, respectively. In this case, the polynomial selection circuit 322 selects a polynomial corresponding to the range to which the fractional part Md belongs based on the most significant bit SMd[m] and bit SMd[m-1].

[0094] More generally, the polynomial selection circuit 322 selects a polynomial corresponding to the range to which the fractional part Md belongs based on the 2 (=n) consecutive bit strings SMd[m:m-n+1] starting from the most significant bit SMd[m]. The most significant bit SMd[m] of the Md bit string SMd corresponds to the bit immediately lower than the bit at digit bit position bp0 in the few-bit string Sx (see FIG. 8). Therefore, it can be said that the polynomial selection circuit 322 selects a polynomial based on at least the bit immediately lower than the bit at digit bit position bp0 in the few-bit string Sx. More specifically, the polynomial selection circuit 322 selects a polynomial based on the n consecutive bit strings Sx[bp0-1:bp0-n] in the few-bit string Sx, with the bit immediately lower than digit bit position bp0 as the most significant bit.

[0095] Note that the polynomials in some adjacent ranges may be the same. For example, when n is 3, the entire range of the decimal portion Md is divided into a first range to an eighth range. In this case, for example, the polynomials in the first range to the third range (first polynomial) may be the same, the polynomials in the fourth range to the sixth range (second polynomial) may be the same, and the polynomials in the seventh and eighth ranges (third polynomial) may be the same. The first polynomial is an approximation formula for range A, which includes ranges 1 to 3; the second polynomial is an approximation formula for range B, which includes ranges 4 to 6; and the third polynomial is an approximation formula for range C, which includes ranges 7 and 6. In this case, the entire range of the decimal portion Md is essentially divided into three ranges A to C. If the bit string SMd[m:m-2] is either "000," "001," or "010," the fractional part Md belongs to range A, so the first polynomial is selected. If the bit string SMd[m:m-2] is either "011," "100," or "101," the fractional part Md belongs to range B, so the second polynomial is selected. If the bit string SMd[m:m-2] is either "110," or "111," the fractional part Md belongs to range C, so the third polynomial is selected. In short, the effective division number of the fractional part Md is 2 n Other ranges may be used, and the widths of the substantial ranges may differ from each other.

[0096] In the example of FIG. 9, the polynomial selection circuit 322 includes a coefficient selector 3221 and an intercept selector 3222. The coefficient selector 3221 selects one of a plurality of coefficients ak (coefficients a1 and a2 in FIG. 9) based on the fractional part Md and outputs the selected coefficient ak to the polynomial operation circuit 323. The coefficient selector 3221 is a combinational circuit, such as a multiplexer. In the example described above, the coefficient selector 3221 outputs one of the coefficients a1 and a2 according to a selection signal. For example, the most significant bit SMd[m] of the Md bit string SMd is input to the coefficient selector 3221 as a selection signal. The coefficient selector 3221 outputs the coefficient a1 when the most significant bit SMd[m] is "0", and outputs the coefficient a2 when the most significant bit SMd[m] is "1".

[0097] The intercept selector 3222 selects one of a plurality of intercepts bk (intercepts b1 and b2 in FIG. 9) based on the fractional part Md, and outputs the selected intercept bk to the polynomial calculation circuit 323. The intercept selector 3222 is, for example, a combinational circuit, and a specific example is a multiplexer. In the above example, the intercept selector 3222 outputs one of the intercepts b1 and b2 according to a selection signal. For example, the most significant bit SMd[m] of the Md bit string SMd is input to the intercept selector 3222 as a selection signal. When the most significant bit SMd[m] is "0", the intercept selector 3222 outputs the intercept b1, and when the most significant bit SMd[m] is "1", the intercept selector 3222 outputs the intercept b2.

[0098] The polynomial arithmetic circuit 323 calculates the decimal part yd of the logarithm y by performing an operation on the polynomial selected by the polynomial selection circuit 322 using the decimal part Md. In the example of Fig. 9, the polynomial arithmetic circuit 323 includes a multiplier 3231 and an adder 3232. The multiplier 3231 multiplies the coefficient a k from the coefficient selector 3221 by the decimal part Md and outputs the multiplication result to the adder 3232. The multiplier 3231 is, for example, a combinational circuit.

[0099] The adder 3232 adds the multiplication result of the multiplier 3231 and the intercept bk selected by the intercept selector 3222, and outputs the addition result as a fractional bit string Syd to the logarithm calculation circuit 4. The adder 3232 is, for example, a combinational circuit.

[0100] As described above, in the first embodiment, the yd calculation circuit 32 calculates the fractional part yd of the logarithm y using a polynomial that is set in advance for each range Rk of the fractional part Md and the fractional part Md of the value M. In this way, it is sufficient to set the coefficient and intercept of each term in the polynomial for each range Rk of the fractional part Md. Therefore, it is possible to reduce the circuit scale compared to when a table showing the correspondence between the fractional part Md of the value M and the fractional part yd of the logarithm y is implemented. Here, if the number of bits bm (for example, "15") of the fractional part Md is used, the table shows that 2 bm Corresponding data for the decimal part Md and the decimal part yd is required. In contrast, in the first embodiment, it is sufficient to set data for each coefficient and intercept for each range Rk. Therefore, the circuit scale of the yd calculation circuit 32 can be reduced.

[0101] Moreover, in the above-described specific example, a linear function is used as the polynomial for each range Rk. This allows the linear coefficients a k and intercepts b k to be set for each range Rk of the fractional part Md. This further reduces the circuit size of the yd calculation circuit 32. In other words, the above-described specific example focuses on the fact that the graph G1 has a shape that is relatively easy to approximate to a straight line over the entire range of the fractional part Md of the value M (i.e., the range greater than or equal to 0 and less than 1). The graph G1 is then divided into multiple ranges Rk, and linear approximation of the graph G1 is performed for each range Rk. This allows the yd calculation circuit 32 to calculate the fractional part yd with high accuracy and a small circuit size.

[0102] In the above specific example, the M arithmetic circuit 31, decimal point shift circuit 321, polynomial selection circuit 322, and polynomial arithmetic circuit 323 of the decimal arithmetic circuit 3 can be configured only with combinational circuits. This allows the decimal arithmetic circuit 3 to generate the decimal bit string Syd with low latency.

[0103] A logarithmic conversion device 1 that operates with such low latency is particularly useful in a processing system 1000A in which a brushless motor controls a robot. In such a processing system 1000A, the required time from detecting sensor information from the sensor 290 to reflecting that sensor information in the control of the brushless motor is extremely short. This required time is, for example, on the order of several tens of microseconds. Therefore, it is desirable for the communication unit to receive the received signal as quickly as possible. In other words, to increase or decrease the amplitude of the received signal to an appropriate value in a short time after receiving the signal, the measurement unit 423 must calculate the measured value PV in a short time. For this reason, a logarithmic conversion device 1 that can operate with low latency is particularly useful as the logarithmic conversion unit 4235 of the measurement unit 423 of the processing system 1000A.

[0104] It is not necessary for all of the M arithmetic circuit 31, decimal point shift circuit 321, polynomial selection circuit 322, and polynomial arithmetic circuit 323 to be formed by combinational circuits; at least one of them may include a sequential circuit such as a flip-flop. If the logarithmic conversion device 1 is formed only by combinational circuits or by a combination of combinational circuits and flip-flops, the logarithmic conversion device 1 can be implemented in RTL (Register Transfer Level). RTL is an abbreviation for Register Transfer Level.

[0105] <Method of determining coefficients and intercepts> Although there are no particular limitations on the method for determining the coefficient a1, the coefficient a2, the intercept b1, and the intercept b2, they can be determined, for example, as follows.

[0106] For example, coefficient a1 may be calculated using the coefficient of line L1 passing through points P11 and P12 in Figure 7, and coefficient a2 may be calculated using the coefficient of line L2 passing through points P21 and P22. Points P11 and P12 correspond to both ends of range R1 on graph G1. Points P21 and P22 correspond to both ends of range R2 on graph G1.

[0107] Now, the value expressed by the Md bit string SMd is a discrete value. Therefore, the decimal part Md is expressed as a discrete value Md[t]. Also, when the decimal part Md is a discrete value Md[t], the decimal part yd is expressed as a discrete value yd[t]. When the number of bits bm of the Md bit string SMd is used, t is equal to or greater than "0" and "(2 bm -1)”. bm -1)" is written as "(2s-1)".

[0108] Point P11 is represented by coordinates (Md[0], yd[0]), point P12 is represented by coordinates (Md[s], yd[s]), point P21 is represented by coordinates (Md[s+1], yd[s+1]), and point P22 is represented by coordinates (Md[2s-1], yd[2s-1]). Therefore, coefficients a1 and a2 are represented by the following equations (10) and (11), respectively.

[0109] a1=(yd[s]-yd[0]) / (Md[s]-Md[0])...(10) a2=(yd[2s-1]-yd[s+1]) / (Md[2s-1]-Md[s+1])...(11) The intercept b1 is determined, for example, as follows. Here, errors E1 and E2 are introduced. As shown in FIG. 7, error E1 is the error between the calculated value of the decimal part yd of logarithm y using equation (8) and the true value of the decimal part yd of logarithm y (the value on graph G1). Error E2 is the error between the value of the decimal part yd on line L1 and the true value of the decimal part yd. Intercept b1 is determined so that error E1 at the center of range R1 is half of error E2 at the center of range R1. Intercept b2 is determined in a similar manner.

[0110] Second Embodiment 10 is a schematic diagram showing an example of the configuration of a logarithmic converter 1 according to the second embodiment. First, an overview of the logarithmic converter 1 according to the second embodiment will be described below, and then each component will be described in detail.

[0111] The logarithmic conversion device 1 according to the second embodiment processes the value M2 with a predetermined number of digits. The predetermined number of digits may be three-quarters or less, half or less, or one-quarter or less of the number of bits bx of the bit string Sx. As a specific example, "7" is used as the predetermined number of digits. For example, if the number x2 is "11110111011," the value M2 is "1.1110111011," and the seven-digit value M2 is, for example, "1.111011." When calculating the seven-digit value M2 in this way, the logarithmic conversion device 1 may truncate digits to the seventh decimal place. Alternatively, the logarithmic conversion device 1 may calculate the seven-digit value M2 by rounding. In this case, the seven-digit value M2 is "1.111100." In the following example, the logarithmic conversion device 1 calculates the value M2 by rounding.

[0112] Furthermore, this rounding may result in the integer portion of the value M2 being carried up. For example, if the number x2 is "11111111011," the value M2 is "1.1111111011," and the seven-digit value M2 after rounding is "10.000000." When the value M becomes "2" due to the carry, as can be seen from equation (5), the integer portion yr of the logarithm y is carried up, and the decimal portion yd becomes "0." In the following, the logarithmic conversion device 1 also has the function of carrying up the integer portion yr.

[0113] On the other hand, there are cases where the number of digits of number x2 is less than the predetermined number of digits. For example, if number x2 is "11011," value M2 is "1.1011." In this case, the seven-digit value M2 is expressed as "1.101100." In other words, the logarithmic conversion device 1 adds "0" to the lower-order parts of value M2 so that the number of digits becomes seven.

[0114] An example of a specific configuration of the logarithmic conversion device 1 according to the second embodiment will be described below. In the example of Fig. 10, the integer arithmetic circuit 2 includes a bit position detection circuit 21 and a carry circuit 22. As in the first embodiment, the bit position detection circuit 21 detects the digit bit position bp0 based on the number bit string Sx. The bit position detection circuit 21 outputs a bit string indicating the digit bit position bp0 to the decimal arithmetic circuit 3 and the carry circuit 22 as the integer bit string Syr0 before carry.

[0115] As will be described later, the carry circuit 22 receives a carry bit Srup from the decimal arithmetic circuit 3. The carry bit Srup is a signal indicating whether or not the integer part yr needs to be carried. When a carry is necessary, the carry bit Srup is "1," and when a carry is not necessary, the carry bit Srup is "0." The carry circuit 22 includes an adder, which is a combinational circuit, and adds the carry bit Srup to the integer bit string Syr0 before the carry and outputs the result of the addition as the integer bit string Syr. As a result, when a carry is necessary, the carry circuit 22 carries the integer bit string Syr0 before the carry and outputs the integer bit string Syr. On the other hand, when a carry is not necessary, the carry circuit 22 outputs the integer bit string Syr0 before the carry as is as the integer bit string Syr.

[0116] The decimal arithmetic circuit 3 generates an M-bit string SM and a carry bit Srup indicating a value M2 of a predetermined number of digits based on the number bit string Sx and the digit bit position bp0 (i.e., the integer bit string Sry0). The decimal arithmetic circuit 3 also generates a decimal bit string Syd based on the M-bit string SM.

[0117] In the second embodiment, as shown in FIG. 10, the decimal arithmetic circuit 3 also includes an M arithmetic circuit 31 and a yd arithmetic circuit 32. However, in the second embodiment, the M arithmetic circuit 31 has the function of calculating the value M with a predetermined number of digits. Specifically, when the number of digits of the number x2 is equal to or greater than the predetermined number, the M arithmetic circuit 31 generates an M-bit string SM by rounding and outputs a carry bit Srup of "1" to the integer arithmetic circuit 2. When the number of digits of the number x2 is less than the predetermined number of digits, the M arithmetic circuit 31 generates an M-bit string SM by filling in "0"s at the lower positions. Note that in the second embodiment, the M arithmetic circuit 31 may also generate an Md-bit string SMd.

[0118] 11 is a schematic diagram showing an example of a specific configuration of the M arithmetic circuit 31 according to the second embodiment. As shown in FIG. 11, the M arithmetic circuit 31 includes a rounding circuit 33, a supplement circuit 34, a selection circuit 35, and a subtractor 36.

[0119] The rounding circuit 33 generates an Md bit string SMd indicating a decimal part Md2 after rounding based on the number bit string Sx and the digit bit position bp0. Fig. 12 is a diagram showing an example of each bit string generated by the rounding circuit 33. An example of the rounding circuit 33 will be described below with reference to Fig. 12.

[0120] As shown in FIG. 11, the rounding circuit 33 includes a truncation circuit 331, a next-digit detection circuit 332, and an adder 333. The truncation circuit 331 generates a bit string SM0 indicating the value M before rounding. Specifically, the truncation circuit 331 generates the bit string SM0 by shifting the few-bit string Sx to the right by a truncation amount Δc, which will be described below (see also FIG. 12). The truncation amount Δc is a value (here, "4") obtained by subtracting a predetermined number of digits (here, "7") from the digit bit position bp0 (here, "10") and adding "1" to the result. By this right shift, the truncation circuit 331 truncates digits (bits) in the few-bit string Sx that are less than the predetermined number of digits in the fractional part Md2 before rounding.

[0121] 11, the truncation circuit 331 includes a subtractor 3311 and a right shifter 3312. The subtractor 3311 calculates the truncation amount Δc. The subtractor 3311 is a combinational circuit, and subtracts (a predetermined number of digits - 1) from the digit bit position bp0 (here, the integer bit string Syr0) to generate a signal SΔc indicating the truncation amount Δc.

[0122] The right shifter 3312 receives a few-bit string Sx and a signal SΔc. The right shifter 3312 shifts the few-bit string Sx to the right by the truncation amount Δc. The right shifter 3312 is configured, for example, with a combinational circuit, and a specific example is a barrel shifter. The right shifter 3312 outputs the shifted bit string to the adder 333 as a bit string SM0.

[0123] The next-digit detection circuit 332 detects the bit of the digit used for rounding (hereinafter referred to as the next-digit bit Sud) in the few-bit string Sx. The next-digit bit Sud is the bit that is a predetermined number of digits (here, "7") lower than the digit bit position bp0 in the few-bit string Sx. In the example of FIG. 12, the digit bit position bp0 is "10," so the bit position bp of the next-digit bit Sud in the few-bit string Sx is "3."

[0124] The next-digit detection circuit 332 first generates a bit string Sud0 (see FIG. 12) by shifting the several-bit string Sx to the left by a left shift amount ΔL and discarding bits higher than the next-digit bit Sud. Then, the next-digit detection circuit 332 generates the next-digit bit Sud (see FIG. 12) by shifting the bit string Sud0 to the right by a predetermined right shift amount (=bx-1).

[0125] In the example of FIG. 11, the next-digit detection circuit 332 includes a subtractor 3321, a left shifter 3322, and a right shifter 3323. The subtractor 3321 is a combinational circuit that subtracts a truncation amount Δc from the number of bits bx of the few-bit string Sx to generate a signal SΔL indicating a left shift amount ΔL. The few-bit string Sx and the signal SΔL are input to the left shifter 3322. The left shifter 3322 shifts the few-bit string Sx to the left by the left shift amount ΔL to generate a bit string Sud0. The left shifter 3322 is, for example, a combinational circuit, and a specific example is a barrel shifter. This left shift shifts the bit of the digit used for rounding to the most significant bit of the bit string Sud0. The left shifter 3322 outputs the left-shifted bit string Sud0 to the right shifter 3323.

[0126] The right shifter 3323 shifts the bit string Sud0 to the right by a predetermined right shift amount, which will be explained below, to generate the next-digit bit Sud. The right shift amount is a value (here, "15") obtained by subtracting 1 from the number of bits bx of the bit string Sx, and is set in advance. The right shifter 3323 is configured, for example, with a combinational circuit, and a specific example is a barrel shifter. This right shift shifts the most significant bit of the bit string Sud0 to the least significant bit. In other words, the least significant bit of the bit string after the right shift corresponds to the next-digit bit Sud. In the example of FIG. 12, the next-digit bit Sud is "1". The right shifter 3323 outputs the next-digit bit Sud to the adder 333.

[0127] The adder 333 adds the bit string SM0 before the carry-up and the next bit Sud to generate an M-bit string SM1. When the next bit Sud is "1", "1" is added to the bit string SM0 and the bit string SM0 is carried up, and when the next bit Sud is "0", the bit string SM0 is output as is as the M-bit string SM1. In the example of FIG. 12, the M-bit string SM1 is a bit string obtained by adding "1" to the bit string SM0 and carrying it up. The adder 333 outputs the rounded M-bit string SM1 to the selection circuit 35.

[0128] As will be explained later, when the number of digits of the number x2 is equal to or greater than a predetermined number of digits, the selection circuit 35 selects the M-bit string SM1 as the M-bit string SM and outputs the selected M-bit string SM.

[0129] The supplement circuit 34 supplements the lower bits of the fractional part Md2 with "0". In other words, if the number of digits of the number x2 is less than the predetermined number of digits, the supplement circuit 34 supplements the lower bits of the fractional part Md2 with "0" so that the number of digits of the fractional part Md2 becomes the predetermined number of digits. For example, if the number x2 is "11011", the fractional part Md2 of the value M2 is "1.1011", and the number of digits of the fractional part Md2 of the value M2 is "5". If the predetermined number of digits is "7", the seven-digit fractional part Md2 becomes "1.101100" by supplementing the lower two digits of the fractional part Md2 with "0".

[0130] FIG. 13 is a diagram showing an example of each bit string generated by the filler circuit 34. The following description will also refer to FIG. 13. The filler circuit 34 shifts the several-bit string Sx to the left by a fill amount Δs to generate a fill-up M-bit string SM2. The fill amount Δs corresponds to the number of digits to be filled with "0". In the example of FIG. 13, the fill amount Δs is "2". This fill amount Δs is a value obtained by subtracting the number of digits of number x2 (here, "5") from the predetermined number of digits (here, "7"). Since the number of digits of number x2 is a value obtained by adding "1" to the digit bit position bp0, the fill amount Δs is also a value obtained by subtracting "1" and the digit bit position bp0 (here, "4") from the predetermined number of digits (here, "7"). In other words, the fill amount Δs corresponds to the absolute value of the truncation amount Δc.

[0131] In the example of FIG. 11, the fill circuit 34 includes a polarity inversion circuit 341 and a left shifter 342. The polarity inversion circuit 341 inverts the positive or negative of the result of the subtractor 3311 (i.e., the value of the signal SΔc) to generate a signal SΔs indicating the fill amount Δs, and outputs the signal SΔs to the left shifter 342. In the example of FIG. 13, since the digit bit position bp0 is "4," the value of the signal SΔc (=4-6) is "-2," and the fill amount Δs of the signal SΔs output by the polarity inversion circuit 341 is "2." The polarity inversion circuit 341 is, for example, a combinational circuit. The polarity inversion circuit 341 may include, for example, a NOT circuit that inverts the bit value indicating the positive or negative of the subtraction result (signal SΔc) of the subtractor 3311.

[0132] The left shifter 342 shifts the several-bit string Sx to the left by a fill amount Δs to generate a filled M-bit string SM2. The left shifter 342 is configured, for example, by a combinational circuit, and a specific example is a barrel shifter. This left shift fills the lower bits with "0" by the fill amount Δs. In the example of FIG. 13, the fill amount Δs is "2," so "0" is filled in the lower two bits of the M-bit string SM2. This allows the number of digits of the value M2 indicated by the M-bit string SM2 to be substantially the predetermined number of digits (7 in this case). The left shifter 342 outputs the M-bit string SM2 to the selection circuit 35.

[0133] The selection circuit 35 receives the result of the subtractor 3311 (i.e., the signal SΔc) as a selection signal. When the value of the signal SΔc is equal to or greater than "0," the selection circuit 35 selects the rounded M-bit string SM1 as the M-bit string SM and outputs the selected M-bit string SM to the subtractor 36. That is, when the number of digits in the number x2 is equal to or greater than a predetermined number of digits, the selection circuit 35 outputs the rounded M-bit string SM1 as the M-bit string SM. On the other hand, when the signal SΔc is negative, the selection circuit 35 selects the padded M-bit string SM2 as the M-bit string SM and outputs the selected M-bit string SM to the subtractor 36. That is, when the number of digits in the number x2 is less than the predetermined number of digits, the selection circuit 35 outputs the M-bit string SM2, in which "0" has been padded to the lower bits, as the M-bit string SM.

[0134] As described above, when the number x2 has a predetermined number of digits or more, an M-bit string SM1 indicating the rounded value M is output as the M-bit string SM. Note that this rounding may result in the integer part of the value M2 being carried up. In this case, the integer part yr of the logarithm y must be carried up.

[0135] Therefore, in the second embodiment, the decimal arithmetic circuit 3 also generates a carry bit Srup for carrying the integer part yr up, and outputs the carry bit Srup to the integer arithmetic circuit 2.

[0136] Fig. 14 is a diagram showing another example of each bit string by the rounding circuit 33. In the example of Fig. 14, the number bit string Sx is "0000011111111011", the bit string SM0 output by the rounding circuit 331 is "0000000001111111", and the M-bit string SM1 output by the rounding circuit 33 is "000000010000000". In this case, the number x has seven or more digits, so the selection circuit 35 outputs the M-bit string SM1 as the M-bit string SM.

[0137] In the above case, the integer part of the value M2 is carried over, so the bit string SM1 "7:6" indicating the integer part of the M-bit string SM is "10". On the other hand, if there is no carry over to the integer part of the value M2, the M-bit string SM[7:6] is "01" (see FIGS. 12 and 13). In other words, "10000000" (=64) is obtained from the M-bit string SM. 10 If the bit at the 6th bit position of the bit string SMs obtained by subtracting ) is "0" (Figures 12 and 13), then there is no need to carry it up to the integer part yr. On the other hand, if that bit is "1" (Figure 14), then there is a need to carry it up to the integer part yr. In other words, that bit corresponds to the carry bit Srup.

[0138] 11, the decimal arithmetic circuit 3 includes a subtractor 36. The subtractor 36 subtracts "64 10 " is subtracted from this "64 10 " is "10000000" in binary. The decimal operation circuit 3 outputs the bit SMs[6] at the sixth bit position of the bit string SMs of the subtraction result output by the subtractor 36 to the integer operation circuit 2 as a carry bit Srup, and outputs the bit string SMs[5:0] of the lower 6 bits to the yd operation circuit 32 as an Md bit string SMd.

[0139] The yd arithmetic circuit 32 generates a fractional bit string Syd based on the Md bit string SMd and outputs the fractional bit string Syd to the logarithm arithmetic circuit 4. The yd arithmetic circuit 32 may be the same as in the first embodiment. Even in this case, the number of bits of the Md bit string SMd is a predetermined fractional bit number (= (predetermined number of digits - 1), here "6") which is small, so the circuit scale of the yd arithmetic circuit 32 can be reduced. The number of fractional bits may be, for example, three-quarters or less, one-half or less, or one-quarter or less of the number of bits bx of the bit string Sx.

[0140] The yd calculation circuit 32 does not necessarily have to be the same as that in the first embodiment. As shown in Fig. 11, the yd calculation circuit 32 may include a table unit 325 having correspondence information in a table format between the decimal part Md2 of the value M2 having a predetermined number of digits and the decimal part yd2 of the logarithm y. Table 1 includes the correspondence table held by the table unit 325.

[0141] [Table 1]

[0142] In Table 1, the correspondence between the Md bit string SMd and the fractional bit string Syd enclosed in thick brackets corresponds to the correspondence table.

[0143] An Md bit string SMd is input to the table unit 325. The table unit 325 outputs a fractional bit string Syd corresponding to the Md bit string SMd based on the correspondence table. In the second embodiment, the number of bits of the Md bit string SMd is a predetermined fractional bit number (here, "6"), which is small, so the circuit scale of the table unit 325 can be reduced.

[0144] Moreover, in the above specific example, the M arithmetic circuit 31 calculates the value M2 by rounding off. This makes it possible to reduce the maximum value of the error (absolute value) between the value calculated by the M arithmetic circuit 31 and the true value of the value M2. This in turn makes it possible to reduce the maximum value of the error (absolute value) between the calculated value of the decimal part yd of the logarithm y and the true value.

[0145] Furthermore, in the above example, since the M operation circuit 31 is composed only of combinational circuits, the M operation circuit 31 can generate the M bit string SM and the Md bit string SMd with low latency. Note that the M operation circuit 31 does not necessarily have to be composed entirely of combinational circuits, and may partially include sequential circuits such as flip-flops.

[0146] <Third embodiment> An example of the configuration of the logarithmic conversion device 1 according to the third embodiment is similar to that of the first or second embodiment. In the third embodiment, an example of a specific configuration of the bit position detection circuit 21 of the integer arithmetic circuit 2 will be described.

[0147] 15 is a schematic diagram showing a first example of a specific configuration of the bit position detection circuit 21. First, the concept of bit position detection will be described below, and then the first example of the configuration of the bit position detection circuit 21 will be described.

[0148] As shown in Figures 12 to 14, in the few-bit string Sx, all bits higher than the digit bit position bp0 are "0". Here, in the few-bit string Sx, the number of consecutive bits whose bit value is "0" from the most significant bit is called the number of consecutive zeros Nz. In the example of Figure 12, the number of consecutive zeros Nz is "5". The digit bit position bp0 can be calculated by subtracting the number of consecutive zeros Nz from the bit position bp of the most significant bit of the few-bit string Sx (here, "15").

[0149] Therefore, the bit position detection circuit 21 includes a number of consecutive zeros calculation circuit 24 and a subtractor 25. Fig. 16 is a diagram showing an example of each bit string in the bit position detection circuit 21. An example of the bit position detection circuit 21 will be described below with reference to Fig. 16 as well.

[0150] The consecutive zeros calculation circuit 24 calculates the number of consecutive zeros Nz based on the bit string Sx. In the example of FIG. 15, the consecutive zeros calculation circuit 24 includes a plurality of NOT circuits 241, logic circuits 242 connected in multiple stages, and an adder circuit 243. The number of NOT circuits 241 is equal to the number of bits bx of the bit string Sx. In this example, the number of bits bx is 16, so 16 NOT circuits 241 are provided. Each NOT circuit 241 receives an input of a bit of the corresponding bit string Sx. That is, the i-th (i=1, . . . , bx) NOT circuit 241 receives an input of the bit whose bit position bp is (i-1) in the bit string Sx. That is, the i-th NOT circuit 241 receives an input of bit Sx[i-1]. The NOT circuit 241 is a combinational circuit that outputs the result of inverting the bits. Therefore, the bit value of each bit in the bit string Sx1, which is made up of the outputs of the multiple NOT circuits 241, is different from the bit value of several bits in the bit string Sx at the same bit position bp (see FIG. 16). Therefore, the number of consecutive zeros Nz corresponds to the number of consecutive bits with a bit value of "1" from the most significant bit in the bit string Sx1.

[0151] The number of logic circuits 242 provided is equal to the number obtained by subtracting "1" from the number of bits bx. In the example of FIG. 15, 15 logic circuits 242 are provided. The logic circuits 242 are combinational circuits, such as logical product circuits. In this case, the logic circuits 242 output the logical product of the inputs. The i-th (i=1, . . . , bx-1) logic circuit 242 receives as input the output of the i-th NOT circuit 241 and the output of the (i+1)-th logic circuit 242. The (bx-1)-th logic circuit 242 receives as input the output of the bx-th NOT circuit 241 and the output of the (bx-1)-th NOT circuit 241.

[0152] Here, we will explain the bit string Sx2 consisting of the output of the bx-th NOT circuit 241 and the outputs of the multiple logic circuits 242. As shown in Fig. 16, in the bit string Sx2, all bits higher than the digit bit position bp0 are "1", and all bits after the digit bit position bp0 are "0".

[0153] The output of each logic circuit 242 and the output of the bx-th NOT circuit 241 are input to the adder circuit 243. In other words, all bits of the bit string Sx2 are input to the adder circuit 243. The adder circuit 243 is a combinational circuit, and calculates the sum of the inputs input to it. In other words, the adder circuit 243 calculates the sum of all bits of the bit string Sx2. This sum corresponds to the number of consecutive zeros Nz in the bit string Sx. The adder circuit 243 outputs a signal indicating the number of consecutive zeros Nz to the subtractor 25.

[0154] The subtractor 25 is a combinational circuit that subtracts the number of consecutive zeros Nz from the most significant bit position bp (here, "15") and outputs a bit string indicating the subtraction result as a bit string indicating the digit bit position bp0 (for example, integer bit string Syr or integer bit string Syr0).

[0155] As described above, the bit position detection circuit 21 can detect the digit bit position bp0. Moreover, in the specific example of Fig. 15, the bit position detection circuit 21 is configured as a combinational circuit, so it can detect the digit bit position bp0 with relatively low latency.

[0156] In the bit position detection circuit 21 of FIG. 15, the output of the (i+1)th logic circuit 242 is input to the ith logic circuit 242. In this case, the output of the first logic circuit 242 requires sequential addition processing by the first to (bx-1)th logic circuits 242. This causes a delay in the operation of the first logic circuit 242. This delay increases as the number of logic circuits 242 connected in multiple stages increases. Therefore, the following aims to reduce this delay.

[0157] FIG. 17 is a schematic diagram showing a second example of the configuration of the bit position detection circuit 21. The following will first describe the concept of bit position detection. FIG. 18 is a diagram showing an example of each bit string. Here, a few-bit string Sx is equally divided into a plurality of group bit strings Sgx. For example, a few-bit string Sx with a bit number bx of "16" is equally divided into four group bit strings Sgx. In this case, the number of bits in each group bit string Sgx (hereinafter referred to as the number of bits in a group bgx) is "4". Each group bit string Sgx is composed of four consecutive bits from the few-bit string Sx. Below, the position of each group bit string Sgx will also be referred to as group position Gp. In the example of FIG. 18, the most significant group position Gp is ​​"3" and the least significant group position Gp is ​​"0 (zero)". For example, a group bit string Sgx in which the group position Gp is ​​"0" is composed of four bit strings Sx[3:0] in which the bit positions bp are "0" to "3" among several bit strings Sx.

[0158] Here, the group position Gp of the group bit string Sgx in which any one bit value is "1" and which is located at the most significant position is called group position Gp0. In the example of FIG. 18, the group position Gp0 is "2". Furthermore, in the group bit string Sgx in group position Gp0, the intra-group bit position bgp of the bit in which the bit value is "1" and which is located at the most significant position is called intra-group bit position bgp0. The digit bit position bp0 is expressed by the following equation (12).

[0159] bp0=bgx·Gp0+bgp0 =bpm-Nz =bpm-{bgx·(Gpm-Gp0)+(bgpm-bgp) ···(12) Here, bpm is the most significant bit position bp (here, "15") of the several-bit string Sx, Gpm is the most significant group position Gp (here, "3"), and bgpm is the most significant intra-group bit position bgp (here, "3"). Therefore, the bit position detection circuit 21 according to the second example detects the group position Gp0 and the intra-group bit position bgp0, and calculates the digit bit position bp0 based on equation (12). In the example of FIG. 17, the bit position detection circuit 21 includes a group position detection circuit 27, an intra-group bit position detection circuit 28, and a bit position calculation circuit 29.

[0160] Fig. 19 is a diagram showing an example of a specific configuration of group position detection circuit 27. Group position detection circuit 27 includes a plurality of NOT circuits 271, a plurality of logic circuits 272, and a bit position detection circuit 273. Fig. 20 is a diagram showing an example of each bit string.

[0161] The number of NOT circuits 271 provided is equal to the number of bits bx of the few-bit string Sx. Like the NOT circuit 241, each NOT circuit 271 receives an input of each bit of the few-bit string Sx. The outputs of the multiple NOT circuits 271 form the bit string Sx1. The number of logic circuits 272 provided is equal to the number of group bit strings Sgx. In the example of FIG. 19, four logic circuits 272 are provided. In the example of FIG. 19, the logic circuits 272 are combinational circuits and AND circuits. The first logic circuit 272 receives an input of the bit string Sx1[0:3], the second logic circuit 272 receives an input of the bit string Sx1[4:7], the third logic circuit 272 receives an input of the bit string Sx1[8:11], and the fourth logic circuit 272 receives an input of the bit string Sx1[12:15].

[0162] Each logic circuit 272 outputs "0" when at least one of the multiple input bits is "0", and outputs "1" when all four bits are "1". Hereinafter, a bit string consisting of the outputs of the multiple logic circuits 272 will be referred to as bit string Sg1 (see also FIG. 20). In this bit string Sg1, the bit position of the most significant bit whose bit value is "0" corresponds to group position Gp0.

[0163] The bit string Sg1 is input to the bit position detection circuit 273. The bit position detection circuit 273 detects the group position Gp0 from the bit string Sg1. The bit position detection circuit 273 includes first logic circuits 274 and an adder circuit 275 connected in multiple stages. The first logic circuits 274 and the adder circuit 275 are similar to the logic circuit 242 and the adder circuit 243, respectively. The number of first logic circuits 274 provided is equal to the number obtained by subtracting "1" from the number of bits in the bit string Sg1 (i.e., the number of group bit strings Sgx). The first logic circuits 274 are combinational circuits, such as a logical AND circuit. The first first logic circuit 274 receives the output of the second first logic circuit 274 and bit Sg1[0] as input, the second first logic circuit 274 receives the output of the third first logic circuit 274 and bit Sg1[1] as input, and the third first logic circuit 274 receives bit Sg1[3] and bit Sg1[2] as input.

[0164] Here, we will describe bit string Sg2, which is made up of bit Sg1[3] and the outputs of multiple first logic circuits 274. In bit string Sg2, all bits higher than group position Gp0 are "1", and all bits after group position Gp0 are "0".

[0165] All bits of bit string Sg2 are input to adder circuit 275. Adder circuit 275 is a combinational circuit that calculates the sum of the bits of bit string Sg2. In the example of FIG. 20, the sum is "1." This sum corresponds to the number of consecutive bits with a bit value of "1" starting from the most significant bit in bit string Sg1. In other words, this sum corresponds to (Gpm-Gp0) in equation (12). Therefore, it can be said that this sum indicates group position Gp0.

[0166] The intra-group bit position detection circuit 28 detects the intra-group bit position bgp0 of the most significant bit in the group bit string Sgx at group position Gp0, the bit value of which is "1". In the example of FIG. 17, the intra-group bit position detection circuit 28 includes a group selection circuit 281 and a bit position detection circuit 282.

[0167] A plurality of group bit strings Sgx1 obtained by equally dividing the bit string Sx1 are input to the group selection circuit 281. A signal indicating the group position Gp0 detected by the group position detection circuit 27 is also input to the group selection circuit 281 as a selection signal. Specifically, the output of the addition circuit 275 is input to the group selection circuit 281 as a selection signal. The group selection circuit 281 selects the group bit string Sgx1 at the group position Gp0 from the plurality of group bit strings Sgx1, and outputs this group bit string Sgx1 to the bit position detection circuit 282 as a selected bit string Sgx2.

[0168] If the several-bit string Sx is all "1", the group selection circuit 281 outputs the constant "0" provided for index 4 of the group selection circuit 281 to the bit position detection circuit 282. In the above case, the result of the subtraction in the subtractor 293 is a negative value, but the output of the subtractor 293 only handles positive values, so if the result is a negative value, the subtractor 293 always outputs "0" and proceeds with the subsequent processing.

[0169] The bit position detection circuit 282 detects the in-group bit position bgp0 of the most significant bit in the selection bit string Sgx2, where the bit value is "0". FIG. 21 is a schematic diagram showing an example of the configuration of the bit position detection circuit 282. In the example of FIG. 21, the bit position detection circuit 282 includes second logic circuits 283 and adder circuits 284 connected in multiple stages. The second logic circuits 283 and adder circuits 284 are similar to the logic circuits 242 and adder circuits 243, respectively. The number of second logic circuits 283 provided is equal to the number obtained by subtracting "1" from the number of bits in the selection bit string Sgx2 (i.e., the number of in-group bits bgx of the group bit string Sgx). The second logic circuits 283 are combinational circuits, such as a logical AND circuit. The first second logic circuit 283 receives as input the output of the second second logic circuit 283 and bit Sgx2[0], the second second logic circuit 283 receives as input the output of the third second logic circuit 283 and bit Sgx2[1], and the third second logic circuit 283 receives as input bit Sgx2[3] and bit Sgx2[2].

[0170] Here, we will describe the bit string Sgx3 consisting of bit Sgx2[3] and the outputs of multiple second logic circuits 283. In the bit string Sgx3, all bits higher than bit position bgp0 in the group are "1", and all bits after bit position bgp0 in the group are "0".

[0171] The adder circuit 284 receives the bit string Sgx3 as input. The adder circuit 284 calculates the sum of the bits in the bit string Sgx3. In the example of FIG. 20, the sum is "1." This sum corresponds to the number of consecutive bits with a bit value of "1" starting from the most significant bit in the selected bit string Sgx2. In other words, this sum corresponds to (bgpm-bgp0) in equation (12). Therefore, it can be said that this sum indicates the bit position bgp0 within the group.

[0172] The bit position calculation circuit 29 calculates the digit bit position bp0 based on the output of the group position detection circuit 27 and the output of the intra-group bit position detection circuit 28. In the example of FIG. 17, the bit position calculation circuit 29 includes a multiplier 291, an adder 292, and a subtractor 293.

[0173] The multiplier 291 is a combinational circuit that multiplies the output of the group position detection circuit 27 (specifically, the output of the adder circuit 275) by the number of intra-group bits bgx of the group bit string Sgx, and outputs the multiplication result to the adder 292. In the specific example above, the output of the group position detection circuit 27 is “1” and the number of intra-group bits bgx of the group bit string Sgx is “4”, so the multiplication result is “4”. The adder 292 is a combinational circuit that adds the output of the multiplier 291 and the output of the intra-group bit position detection circuit 28 (specifically, the output of the adder circuit 284). In the specific example above, the output of the intra-group bit position detection circuit 28 is “1”, and the output of the adder 292 is “5”. The output of the adder 292 corresponds to the number of consecutive bits whose bit value is “1” from the most significant bit in the bit string Sx1 (i.e., the number of consecutive zeros Nz).

[0174] The subtractor 293 is a combinational circuit that subtracts the output of the adder 292 (i.e., the number of consecutive zeros Nz) from the most significant bit position (here, "15") of the several-bit string Sx, and outputs the subtraction result as the digit bit position bp0.

[0175] As described above, the bit position detection circuit 21 according to the second example can also detect the digit bit position bp0. Moreover, in the second example, the number of first logic circuits 274 obtained by subtracting "1" from the number of group bit strings Sgx (here, "4"), and the number of second logic circuits 283 obtained by subtracting "1" from the number of intra-group bits bgx (here, "4") of the group bit string Sgx are provided. In the specific example described above, three first logic circuits 274 and three second logic circuits 283 are provided. Therefore, compared to the first example, the number of logic circuits connected in multiple stages can be reduced, and delays due to processing by the logic circuits connected in multiple stages can be suppressed.

[0176] Furthermore, in the above example, the bit position detection circuit 21 can be configured only by combinational circuits. This allows the bit position detection circuit 21 to detect the digit bit position bp0 with even lower latency. Furthermore, in the above example, the carry circuit 22 of the integer arithmetic circuit 2 is also configured by a combinational circuit, allowing the integer arithmetic circuit 2 to generate the integer bit string Syr with even lower latency. Note that the integer arithmetic circuit 2 does not necessarily have to be configured entirely by combinational circuits, and may partially include sequential circuits such as flip-flops.

[0177] <Fourth embodiment> In the first to third embodiments, the logarithmic converter 1 calculated the logarithm y with a base of 2. In the fourth embodiment, the logarithmic converter 1 calculates the measurement value PV shown in equation (2). Specifically, the logarithmic converter 1 calculates the measurement value PV by multiplying the logarithm y by "3.01." In other words, the logarithmic converter 1 realizes the functions of the square root unit 4234 and the logarithmic converter 4235 in FIG. 4.

[0178] FIG. 22 is a schematic diagram showing an example of the configuration of a logarithmic conversion device 1 according to the fourth embodiment. The logarithmic conversion device 1 according to the fourth embodiment converts a number x into a logarithm y while multiplying the logarithm y by a constant K. In this example, the constant K is "3.01." As shown in FIG. 22, the logarithmic conversion device 1 includes an integer arithmetic circuit 2, a decimal arithmetic circuit 3, a logarithmic arithmetic circuit 4, and a constant multiplication circuit 5. The integer arithmetic circuit 2 is the same as in the third embodiment, for example, and the decimal arithmetic circuit 3 is the same as in the first or second embodiment.

[0179] The constant multiplication circuit 5 is a circuit that multiplies the logarithm y from the logarithm calculation circuit 4 by a constant K. First, a method for multiplying the logarithm y by the constant K will be described below.

[0180] Equation (2) can be transformed as follows:

[0181] PV=3·y+0.01·y =(4-1)·y+0.01·y =4·y−y+0.01·y (13) Here, the nearest power of 2 to "0.01" is 2 -7 If (=0.007813) is adopted, equation (13) can be transformed as follows:

[0182] PV≒2 2 y-y+2 -7 ·y···(14) In equation (14), the first term on the right-hand side (i.e., logarithm y and 2 2 In binary notation, the multiplication of logarithm y2 corresponds to adding "0" to the last two digits of logarithm y2. In other words, the calculation of the first and second terms on the right side of equation (14) corresponds to the process of subtracting logarithm y2 from the value obtained by shifting logarithm y2 two places to the left, and calculating the subtracted value. In addition, the third term on the right side (i.e., the multiplication of logarithm y and 2 -7 In binary notation, this multiplication corresponds to the process of shifting the decimal point of logarithm y2 seven places to the left. In other words, the right side of equation (14) corresponds to the process of adding the value obtained by shifting logarithm y2 seven places to the right to the subtracted value.

[0183] 23 is a schematic diagram showing an example of the configuration of the constant multiplication circuit 5. The constant multiplication circuit 5 includes an integer multiplication circuit 51, a decimal multiplication circuit 52, and an adder 53.

[0184] The integer multiplication circuit 51 multiplies the logarithm y by the integer part of the constant K (here, "3"). In the example of FIG. 23, the integer multiplication circuit 51 includes a left shifter 511 and a subtractor 512. The left shifter 511 shifts the logarithmic bit string Sy to the left by a predetermined left shift amount (here, "2") and outputs the bit string Sy1 resulting from the shift. The left shifter 511 is a combinational circuit, such as a barrel shifter. This bit string Sy1 is the logarithm y multiplied by the integer part of the constant K (here, "3"). 2 (i.e., the first term of equation (14)). The predetermined left shift amount can also be said to be the exponent of the power of 2 (here, "2") that is closest to the integer part of the constant K (here, "3").

[0185] The subtractor 512 is a combinational circuit that subtracts the logarithmic bit string Sy from the bit string Sy1 to generate a bit string Sy2 and outputs the bit string Sy2 to the adder 53. The bit string Sy2 is the sum of the logarithm y and 2 2 (i.e., the calculation result of the first and second terms on the right side of equation (14)). In other words, the bit string Sy2 indicates the multiplication result of the logarithm y and the integer part of the constant K.

[0186] The decimal multiplication circuit 52 multiplies the logarithm y by an approximation of the decimal part of the constant K. The decimal multiplication circuit 52 moves the decimal point of the logarithm bit string Sy to the left. Specifically, the decimal multiplication circuit 52 includes a right shifter 521. The right shifter 521 shifts the logarithm bit string Sy to the right by a predetermined right shift amount (here, "7") and outputs the shift result as a bit string Sy3 to the adder 53. The right shifter 521 is a combinational circuit, such as a barrel shifter. This bit string Sy3 is, in binary notation, the logarithm y and 2 -7 (i.e., the third term on the right side of equation (14)). The predetermined right shift amount can also be said to be the absolute value (here, "7") of the exponent of the power of 2 that is closest to the decimal part of the constant K (here, "0.01").

[0187] The adder 53 is a combinational circuit that adds the bit string Sy2, which is the calculation result of the integer multiplication circuit 51, and the bit string Sy3, which is the calculation result of the decimal multiplication circuit 52. The calculation result of the adder 53 indicates the measurement value PV calculated by equation (14).

[0188] As described above, the constant multiplication circuit 5 is configured with a shift circuit and an adder (subtractor), so it is possible to calculate the measured value PV with a simple circuit configuration. In addition, since the constant multiplication circuit 5 is configured with a combinational circuit, it is possible to calculate the measured value PV with low latency.

[0189] Next, we consider the error associated with the approximation formula of Equation (14). FIG. 24 is a graph showing the relationship between the number x and the error in the measurement value PV. The measurement value PV is a calculated value based on Equation (14). The error is the difference between the calculated value of the measurement value PV and the true value of the measurement value PV. This error includes a multiplication error component resulting from the approximation of Equation (14) and a rounding error component resulting from the rounding of the decimal part Md2. The multiplication error component is an error component resulting from approximating the decimal part of the constant K ("0.01" in the above example) by a power of 2. In the example of FIG. 24, the maximum error is approximately 0.02 dB, and the minimum error is approximately -0.08 dB. Therefore, the maximum error (absolute value) is approximately 0.08 dB.

[0190] Next, we consider the error in the provisionally calculated value of the measurement value PV based on Equation (13). In Equation (13), no approximation is made for the multiplication by "3.01." FIG. 25 is a graph showing the relationship between the number x and the error in the measurement value PV (provisionally calculated value). Because the provisionally calculated value is calculated based on Equation (13), this error contains almost no multiplication error component but does contain a rounding error component. In the example of FIG. 25, the maximum error is approximately 0.04 dB, and the minimum error is approximately -0.05 dB. As can be seen from a comparison of FIGS. 24 and 25, the error amplitudes are almost the same in the graphs of FIGS. 24 and 25. In other words, the multiplication error component has almost no effect on the error amplitude, and the rounding error component is thought to be the main factor affecting the amplitude. On the other hand, in the graph of FIG. 25, the offset component of the error is almost zero, while in the graph of FIG. 24, the error has a negative offset component. In other words, it can be seen that the multiplication error component mainly appears as an offset component.

[0191] In the following, we aim to reduce the maximum value of the error (absolute value). As mentioned above, the multiplication error component appears as a negative offset component, so the error (absolute value) can be reduced by offsetting the measurement value PV in the positive direction. However, implementing a circuit that corrects the measurement value PV with a predetermined offset amount requires an adder or subtractor, which increases the circuit size.

[0192] Therefore, in the fourth embodiment, in order to perform an offset that reduces the error in the measurement value PV, a value that is pre-offset is used as the value of the decimal part yd in the correspondence information between the value M and the decimal part yd. For example, as in the first embodiment, when the correspondence information is expressed as a polynomial, corrected values ​​obtained by adding a predetermined offset value OFS1 to the pre-correction values ​​are used as the intercepts b1 and b2. FIG. 26 is a graph showing the polynomial. The intercept b1 is a value obtained by correcting the pre-correction intercept b10 with the predetermined offset value OFS1, and the intercept b2 is a value obtained by correcting the pre-correction intercept b20 with the predetermined offset value OFS1. Here, the predetermined offset value OFS1 is a value corresponding to the difference between the decimal part of the constant K (here, "0.01") and the power of 2 closest to the decimal part (here, "0.007813"), and is set in advance to a value that can reduce the offset component in FIG. 24. It can also be said that the offset value OFS1 is a value according to the offset component of the error in the measurement value PV based on the formula 14. The offset value OFS1 can be set in advance by, for example, simulation.

[0193] FIG. 27 is a graph showing the relationship between the number x and the error of the measurement value PV using the correspondence relationship information after offset. As can be seen from a comparison of FIG. 24 and FIG. 27, by using the offset value as the intercept bk, the error can be offset upward by approximately 0.02 dB. Conversely, an offset value OFS1 is set in advance so as to offset the error upward by approximately 0.02 dB. In the example of FIG. 27, the maximum error is approximately 0.4 dB, and the minimum error is approximately −0.06 dB. Therefore, the maximum error (absolute value) is approximately 0.06 dB. In other words, the offset can reduce the maximum error (absolute value) by approximately 30%.

[0194] In the above example, the constant multiplication circuit 5 can be configured only with combinational circuits. This allows the constant multiplication circuit 5 to calculate the measurement value PV with low latency. Note that the constant multiplication circuit 5 does not necessarily have to be configured entirely with combinational circuits, and may partially include sequential circuits such as flip-flops.

[0195] When the correspondence information is shown in a table as in the second embodiment, the value of the decimal part yd is corrected by a predetermined offset value OFS1. Table 2 shows the correspondence information.

[0196] [Table 2]

[0197] This also makes it possible to reduce the maximum value of the error (absolute value).

[0198] The functions of the elements disclosed herein may be implemented using circuitry or processing circuitry, including general-purpose processors, special-purpose processors, integrated circuits, ASICs ("application-specific integrated circuits"), conventional circuitry, and / or combinations thereof, configured to perform the disclosed elements or programmed to perform the disclosed functions. A processor is considered to be processing circuitry or circuitry when it includes transistors and other circuitry therein. In this disclosure, a circuitry, unit, or means is hardware that performs the recited function or hardware programmed to perform the function. The hardware may be any hardware disclosed herein or other known hardware that is programmed to perform or configured to perform the recited function. When the hardware is a processor, which may be considered as a type of circuitry, the circuitry, means, or unit is a combination of hardware and software, software used to configure the hardware, and / or processor.

[0199] Although the logarithmic converter 1 has been described in detail above, the above description is merely an example in all respects and does not limit the scope of the present invention. Furthermore, the various embodiments described above can be combined and applied as long as they are not mutually inconsistent. It is understood that countless variations not illustrated can be envisioned without departing from the scope of the logarithmic converter 1.

[0200] For example, the logarithmic conversion device 1 is not limited to communication systems and can be applied to general applications that perform logarithmic conversion, such as processing that outputs true values ​​as logarithms.

[0201] The present disclosure includes the following aspects.

[0202] A first aspect is a logarithmic conversion device that converts a number into a logarithm, and includes: a bit position detection circuit that detects the digit bit position of the most significant bit, which has a bit value of 1, in a number bit string that represents the number in binary; a polynomial selection circuit that selects one polynomial from a plurality of polynomials based on a bit in the number bit string that is at least one bit position lower than the digit bit position; a polynomial arithmetic circuit that calculates the fractional part of the logarithm based on the polynomial selected by the polynomial selection circuit and an M-bit string of the number bit string that is lower than the digit bit position; and a logarithm arithmetic circuit that generates a logarithm bit string that represents the logarithm based on the fractional part of the logarithm and an integer part of the logarithm based on the digit bit positions.

[0203] A second aspect is the logarithmic conversion device according to the first aspect, wherein the polynomial is a linear function.

[0204] A third aspect is the logarithmic conversion device according to the first or second aspect, wherein at least a part of the bit position detection circuit, the polynomial selection circuit, and the logarithmic calculation circuit is configured by a combinational circuit.

[0205] A fourth aspect is a logarithmic conversion device according to any one of the first to third aspects, comprising an M-operation circuit that generates the M-bit string by rounding off the few-bit string based on the next-most significant bit that is a predetermined number of digits lower than the significant bit position, and outputs a carry bit that indicates a carry to the integer part, and a carry circuit that adds the carry bit to the significant bit position to calculate the integer part of the logarithm.

[0206] A fifth aspect is a logarithmic conversion device according to any one of the first to fourth aspects, wherein the bit position detection circuit includes a group position detection circuit that detects the group position of the most significant group bit sequence, among the plurality of group bit sequences obtained by dividing the few bit sequence, whose bit value includes 1; an intra-group bit position detection circuit that detects the intra-group bit position of the most significant bit, whose bit value is 1, among the group bit sequence of the group position detected by the group position detection circuit; and a bit position calculation circuit that calculates the digit bit position based on the group position and the intra-group bit position.

[0207] A sixth aspect is a logarithmic conversion device according to the fifth aspect, wherein the group position detection circuit includes first logic circuits connected in multiple stages, the intra-group bit position detection circuit includes second logic circuits connected in multiple stages, the first logic circuits being provided in a number equal to the number obtained by subtracting 1 from the number of group bit strings, and the second logic circuits being provided in a number equal to the number obtained by subtracting 1 from the number of intra-group bits of the group bit strings.

[0208] A seventh aspect is a logarithmic conversion device according to any one of the first to sixth aspects, further comprising a constant multiplication circuit that multiplies the logarithm by a constant, the constant multiplication circuit including an integer multiplication circuit that multiplies the logarithmic bit string by the integer part of the constant, a fractional multiplication circuit that shifts the logarithmic bit string to the right by the absolute value of the exponent of the power of 2 that is closest to the fractional part of the constant, and an adder that adds the calculation results of the integer multiplication circuit and the calculation results of the fractional multiplication circuit, and the intercept of the polynomial is corrected by an offset value corresponding to the difference between the fractional part of the constant and the power.

[0209] An eighth aspect is a system comprising a power supply side system, a load side system including a motor that drives a robot, and a cable connecting the power supply side system and the load side system, wherein the power supply side system comprises a coupler unit that extracts a communication signal from the power supply voltage applied to the cable, an increase / decrease unit that amplifies or attenuates the amplitude of the communication signal based on an operating amount, a measurement unit that includes a logarithmic conversion device according to any one of the first to seventh aspects, converts the number indicating the amplitude of the communication signal into a logarithm, and outputs a measurement value of the amplitude based on the logarithm, and an increase / decrease control unit that determines the operating amount based on the measurement value and a target value. [Explanation of symbols]

[0210] 1 Logarithmic conversion device 21-bit position detection circuit 22 Carry-up circuit 27 Group position detection circuit 274 First Logic Circuit 28 Intra-group bit position detection circuit 283 Second Logic Circuit 29-bit position calculation circuit 31M calculation circuit 322 Polynomial Selection Circuit 323 Polynomial Arithmetic Circuit 4 Logarithmic calculation circuit 5 Constant multiplication circuit 51 Integer Multiplication Circuit 52 Decimal Multiplication Circuit 53 Adder 100 Power supply system 200 Load Side System 600 Cable CPG1,CPG2 coupler section 421 Increase / Decrease 423 Measuring part 424 Increase / decrease control unit

Claims

1. A logarithmic conversion device for converting a number into a logarithm, a bit position detection circuit for detecting the position of the most significant bit, which has a bit value of 1, in a string of bits representing the number in binary; a polynomial selection circuit that selects one polynomial from a plurality of polynomials based on at least a bit in the several-bit string that is one bit lower than the digit bit position; a polynomial calculation circuit that calculates a decimal part of the logarithm based on the polynomial selected by the polynomial selection circuit and an M-bit string lower than the digit bit position in the several-bit string; a logarithm calculation circuit that generates a logarithm bit string representing the logarithm based on the decimal part of the logarithm and the integer part of the logarithm based on the digit bit position; A logarithmic conversion device comprising:

2. 2. The logarithmic conversion device according to claim 1, A logarithmic conversion device, wherein the polynomial is a linear function.

3. 3. The logarithmic conversion device according to claim 1, At least a part of the bit position detection circuit, the polynomial selection circuit, and the logarithmic calculation circuit is configured by a combinational circuit.

4. 3. The logarithmic conversion device according to claim 1, an M operation circuit that generates the M-bit string by rounding off the several-bit string based on a next-digit bit that is a predetermined number of digits lower than the digit bit position, and outputs a carry bit that indicates a carry to the integer part; a carry circuit that adds the carry bit to the digit bit position to calculate the integer part of the logarithm; A logarithmic conversion device comprising:

5. 3. The logarithmic conversion device according to claim 1, The bit position detection circuit a group position detection circuit for detecting the group position of the most significant group bit string, which has a bit value of 1 and is one of the plurality of group bit strings obtained by dividing the several bit string; an intra-group bit position detection circuit that detects the intra-group bit position of the most significant bit that has a bit value of 1 in the group bit string at the group position detected by the group position detection circuit; a bit position calculation circuit that calculates the digit bit position based on the group position and the bit position within the group; A logarithmic conversion device, including:

6. 6. The logarithmic conversion device according to claim 5, the group position detection circuit includes a first logic circuit connected in multiple stages, the intra-group bit position detection circuit includes second logic circuits connected in multiple stages; the first logic circuits are provided in a number obtained by subtracting 1 from the number of the group bit strings, a logarithmic conversion device, wherein the number of the second logic circuits provided is equal to the number obtained by subtracting 1 from the number of bits in a group of the group bit string;

7. 3. The logarithmic conversion device according to claim 1, a constant multiplication circuit for multiplying the logarithm by a constant; The constant multiplication circuit an integer multiplication circuit that multiplies the logarithmic bit string by an integer part of a constant; a fractional multiplication circuit for right-shifting the logarithmic bit string by the absolute value of the exponent of the power of two that is closest to the fractional part of the constant; an adder that adds the calculation result of the integer multiplication circuit and the calculation result of the decimal multiplication circuit; Including, A logarithmic conversion device, wherein the intercept of the polynomial is corrected by an offset value corresponding to the difference between the fractional part of the constant and the power.

8. A power supply system; a load side system including a motor that drives the robot; a cable connecting the power supply side system and the load side system; Equipped with The power supply side system includes: a coupler unit that extracts a communication signal from the power supply voltage applied to the cable; an amplifying / decreasing unit that amplifies or attenuates the amplitude of the communication signal based on an operation amount; a measurement unit including the logarithmic conversion device according to claim 1 or 2, which converts the number indicating the amplitude of the communication signal into a logarithm and outputs a measurement value of the amplitude based on the logarithm; an increase / decrease control unit that calculates the manipulated variable based on the measured value and the target value; A system comprising:

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